Merge branch 'master' of https://github.com/mbedmicro/mbed

libraries/USBDevice/USBDevice/USBEndpoints.h

@@ -47,6 +47,8 @@ typedef enum {
 #include "USBEndpoints_STM32F4.h"
 #elif defined (TARGET_RZ_A1H)
 #include "USBEndpoints_RZ_A1H.h"
+#elif defined(TARGET_Maxim)
+#include "USBEndpoints_Maxim.h"
 #else
 #error "Unknown target type"
 #endif

libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h

@@ -0,0 +1,90 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS   (8)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS  (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+#define DIR_OUT       0x00
+#define DIR_IN        0x01
+#define EP_NUM(ep)    (ep >> 1)
+#define IN_EP(ep)     (ep & DIR_IN)
+#define OUT_EP(ep)    (!(ep & DIR_IN))
+
+/* Define physical endpoint numbers */
+
+/*      Endpoint    No.   */
+/*      ----------------  */
+#define EP0OUT      ((0 << 1) | DIR_OUT)
+#define EP0IN       ((0 << 1) | DIR_IN)
+#define EP1OUT      ((1 << 1) | DIR_OUT)
+#define EP1IN       ((1 << 1) | DIR_IN)
+#define EP2OUT      ((2 << 1) | DIR_OUT)
+#define EP2IN       ((2 << 1) | DIR_IN)
+#define EP3OUT      ((3 << 1) | DIR_OUT)
+#define EP3IN       ((3 << 1) | DIR_IN)
+#define EP4OUT      ((4 << 1) | DIR_OUT)
+#define EP4IN       ((4 << 1) | DIR_IN)
+#define EP5OUT      ((5 << 1) | DIR_OUT)
+#define EP5IN       ((5 << 1) | DIR_IN)
+#define EP6OUT      ((6 << 1) | DIR_OUT)
+#define EP6IN       ((6 << 1) | DIR_IN)
+#define EP7OUT      ((7 << 1) | DIR_OUT)
+#define EP7IN       ((7 << 1) | DIR_IN)
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0  (64)
+#define MAX_PACKET_SIZE_EP1  (64)
+#define MAX_PACKET_SIZE_EP2  (64)
+#define MAX_PACKET_SIZE_EP3  (64)
+#define MAX_PACKET_SIZE_EP4  (64)
+#define MAX_PACKET_SIZE_EP5  (64)
+#define MAX_PACKET_SIZE_EP6  (64)
+#define MAX_PACKET_SIZE_EP7  (64)
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoints */
+#define EPBULK_OUT  (EP1OUT)
+#define EPBULK_IN   (EP2IN)
+#define EPBULK_OUT_callback   EP1_OUT_callback
+#define EPBULK_IN_callback    EP2_IN_callback
+/* Interrupt endpoints */
+#define EPINT_OUT   (EP3OUT)
+#define EPINT_IN    (EP4IN)
+#define EPINT_OUT_callback    EP3_OUT_callback
+#define EPINT_IN_callback     EP4_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK  (64)
+#define MAX_PACKET_SIZE_EPINT   (64)

libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp

@@ -0,0 +1,473 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#if defined(TARGET_Maxim)
+
+#include "USBHAL.h"
+#include "usb_regs.h"
+#include "clkman_regs.h"
+
+#define CONNECT_INTS    (MXC_F_USB_DEV_INTEN_BRST | MXC_F_USB_DEV_INTEN_SETUP | MXC_F_USB_DEV_INTEN_EP_IN | MXC_F_USB_DEV_INTEN_EP_OUT | MXC_F_USB_DEV_INTEN_DMA_ERR)
+
+USBHAL *USBHAL::instance;
+
+typedef struct {
+    volatile uint32_t buf0_desc;
+    volatile uint32_t buf0_address;
+    volatile uint32_t buf1_desc;
+    volatile uint32_t buf1_address;
+} ep_buffer_t;
+
+typedef struct {
+    ep_buffer_t out_buffer;
+    ep_buffer_t in_buffer;
+} ep0_buffer_t;
+
+typedef struct {
+    ep0_buffer_t ep0;
+    ep_buffer_t ep[MXC_USB_NUM_EP - 1];
+} ep_buffer_descriptor_t;
+
+// Static storage for endpoint buffer descriptor table. Must be 512 byte alligned for DMA.
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma data_alignment = 512
+#else
+__attribute__ ((aligned (512))) 
+#endif
+ep_buffer_descriptor_t ep_buffer_descriptor;
+
+// static storage for temporary data buffers. Must be 32 byte alligned.
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma data_alignment = 4
+#else
+__attribute__ ((aligned (4))) 
+#endif
+static uint8_t aligned_buffer[NUMBER_OF_LOGICAL_ENDPOINTS][MXC_USB_MAX_PACKET];
+
+// contorl packet state
+static enum {
+    CTRL_NONE = 0,
+    CTRL_SETUP,
+    CTRL_OUT,
+    CTRL_IN,
+} control_state;
+
+USBHAL::USBHAL(void)
+{
+    NVIC_DisableIRQ(USB_IRQn);
+
+    // The PLL must be enabled for USB
+    MBED_ASSERT(MXC_CLKMAN->clk_config & MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE);
+
+    // Enable the USB clock
+    MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N;
+
+    // reset the device
+    MXC_USB->cn = 0;
+    MXC_USB->cn = 1;
+    MXC_USB->dev_inten = 0;
+    MXC_USB->dev_cn = 0;
+    MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
+    MXC_USB->dev_cn = 0;
+
+    // fill in callback arrays
+    epCallback[EP0OUT] = NULL;
+    epCallback[EP0IN]  = NULL;
+    epCallback[EP1OUT] = &USBHAL::EP1_OUT_callback;
+    epCallback[EP1IN ] = &USBHAL::EP1_IN_callback;
+    epCallback[EP2OUT] = &USBHAL::EP2_OUT_callback;
+    epCallback[EP2IN ] = &USBHAL::EP2_IN_callback;
+    epCallback[EP3OUT] = &USBHAL::EP3_OUT_callback;
+    epCallback[EP3IN ] = &USBHAL::EP3_IN_callback;
+    epCallback[EP4OUT] = &USBHAL::EP4_OUT_callback;
+    epCallback[EP4IN ] = &USBHAL::EP4_IN_callback;
+    epCallback[EP5OUT] = &USBHAL::EP5_OUT_callback;
+    epCallback[EP5IN ] = &USBHAL::EP5_IN_callback;
+    epCallback[EP6OUT] = &USBHAL::EP6_OUT_callback;
+    epCallback[EP6IN ] = &USBHAL::EP6_IN_callback;
+    epCallback[EP7OUT] = &USBHAL::EP7_OUT_callback;
+    epCallback[EP7IN ] = &USBHAL::EP7_IN_callback;
+
+    // clear driver state
+    control_state = CTRL_NONE;
+
+    // set the descriptor location
+    MXC_USB->ep_base = (uint32_t)&ep_buffer_descriptor;
+
+    // attach IRQ handler and enable interrupts
+    instance = this;
+    NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
+    NVIC_EnableIRQ(USB_IRQn);
+}
+
+USBHAL::~USBHAL(void)
+{
+    MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
+    MXC_USB->dev_cn = 0;
+    MXC_USB->cn = 0;
+}
+
+void USBHAL::connect(void)
+{
+    // enable interrupts
+    MXC_USB->dev_inten |= CONNECT_INTS;
+
+    // allow interrupts on ep0
+    MXC_USB->ep[0] |= MXC_F_USB_EP_INT_EN;
+
+    // pullup enable
+    MXC_USB->dev_cn |= (MXC_F_USB_DEV_CN_CONNECT | MXC_F_USB_DEV_CN_FIFO_MODE);
+}
+
+void USBHAL::disconnect(void)
+{
+    // disable interrupts
+    MXC_USB->dev_inten &= ~CONNECT_INTS;
+
+    // disable pullup
+    MXC_USB->dev_cn &= ~MXC_F_USB_DEV_CN_CONNECT;
+}
+
+void USBHAL::configureDevice(void)
+{
+    // do nothing
+}
+
+void USBHAL::unconfigureDevice(void)
+{
+    // reset endpoints
+    for (int i = 0; i < MXC_USB_NUM_EP; i++) {
+        // Disable endpoint and clear the data toggle
+        MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR;
+        MXC_USB->ep[i] |= MXC_F_USB_EP_DT;
+    }
+}
+
+void USBHAL::setAddress(uint8_t address)
+{
+    // do nothing
+}
+
+void USBHAL::remoteWakeup(void)
+{
+    // do nothing
+}
+
+static ep_buffer_t *get_desc(uint8_t endpoint)
+{
+    uint8_t epnum = EP_NUM(endpoint);
+    ep_buffer_t *desc;
+
+    if (epnum == 0) {
+        if (IN_EP(endpoint)) {
+            desc = &ep_buffer_descriptor.ep0.in_buffer;
+        } else {
+            desc = &ep_buffer_descriptor.ep0.out_buffer;
+        }
+    } else {
+        desc = &ep_buffer_descriptor.ep[epnum - 1];
+    }
+
+    return desc;
+}
+
+void USBHAL::EP0setup(uint8_t *buffer)
+{
+    memcpy(buffer, (void*)&MXC_USB->setup0, 8); // setup packet is fixed at 8 bytes
+}
+
+void USBHAL::EP0read(void)
+{
+    if (control_state == CTRL_IN) {
+        // This is the status stage. ACK.
+        MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
+        control_state = CTRL_NONE;
+        return;
+    }
+
+    control_state = CTRL_OUT;
+
+    endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
+}
+
+void USBHAL::EP0readStage(void)
+{
+    // do nothing
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
+{
+    uint32_t size;
+
+    if (MXC_USB->out_owner & 1) {
+        return 0;
+    }
+
+    // get the packet length and contents
+    ep_buffer_t *desc = get_desc(EP0OUT);
+    size = desc->buf0_desc;
+    memcpy(buffer, aligned_buffer[0], size);
+
+    return size;
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
+{
+    if ((size == 0) && (control_state != CTRL_IN)) {
+        // This is a status stage ACK. Handle in hardware.
+        MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
+        control_state = CTRL_NONE;
+        return;
+    }
+
+    control_state = CTRL_IN;
+
+    endpointWrite(EP0IN, buffer, size);
+}
+
+void USBHAL::EP0stall(void)
+{
+    stallEndpoint(0);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
+{
+    uint8_t epnum = EP_NUM(endpoint);
+
+    if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) {
+        return EP_INVALID;
+    }
+
+    if (maximumSize > MXC_USB_MAX_PACKET) {
+        return EP_INVALID;
+    }
+    
+    uint32_t mask = (1 << epnum);
+    if (MXC_USB->out_owner & mask) {
+        return EP_INVALID;
+    }
+
+    ep_buffer_t *desc = get_desc(endpoint);
+    desc->buf0_desc = maximumSize;
+    desc->buf0_address = (uint32_t)aligned_buffer[epnum];
+
+    MXC_USB->out_owner = mask;
+
+    return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead)
+{
+    if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) {
+        return EP_INVALID;
+    }
+
+    uint32_t mask = (1 << EP_NUM(endpoint));
+    if (MXC_USB->out_owner & mask) {
+        return EP_PENDING;
+    }
+
+    // get the packet length and contents
+    ep_buffer_t *desc = get_desc(endpoint);
+    *bytesRead = desc->buf0_desc;
+    memcpy(data, aligned_buffer[EP_NUM(endpoint)], *bytesRead);
+
+    return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
+{
+    uint8_t epnum = EP_NUM(endpoint);
+
+    if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || OUT_EP(endpoint)) {
+        return EP_INVALID;
+    }
+
+    if (size > MXC_USB_MAX_PACKET) {
+        return EP_INVALID;
+    }
+
+    uint32_t mask = (1 << epnum);
+    if (MXC_USB->in_owner & mask) {
+        return EP_INVALID;
+    }
+
+    memcpy(aligned_buffer[epnum], data, size);
+
+    ep_buffer_t *desc = get_desc(endpoint);
+    desc->buf0_desc = size;
+    desc->buf0_address = (uint32_t)aligned_buffer[epnum];
+
+    // start the DMA
+    MXC_USB->in_owner = mask;
+
+    return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
+{
+    uint32_t mask = (1 << EP_NUM(endpoint));
+    if (MXC_USB->in_owner & mask) {
+        return EP_PENDING;
+    }
+
+    return EP_COMPLETED;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint)
+{
+    uint8_t epnum = EP_NUM(endpoint);
+
+    if (epnum == 0) {
+        MXC_USB->ep[epnum] |= MXC_F_USB_EP_ST_STALL;
+    }
+
+    MXC_USB->ep[epnum] |= MXC_F_USB_EP_STALL;
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint)
+{
+    MXC_USB->ep[EP_NUM(endpoint)] &= ~MXC_F_USB_EP_STALL;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options)
+{
+    uint8_t epnum = EP_NUM(endpoint);
+    uint32_t ep_ctrl;
+
+    if (epnum >= NUMBER_OF_PHYSICAL_ENDPOINTS) {
+        return false;
+    }
+
+    if (IN_EP(endpoint)) {
+        ep_ctrl = (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS);
+    } else {
+        ep_ctrl = (MXC_S_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS);
+    }
+
+    ep_ctrl |= (MXC_F_USB_EP_DT | MXC_F_USB_EP_INT_EN);
+
+    MXC_USB->ep[epnum] = ep_ctrl;
+
+    return true;
+}
+
+bool USBHAL::getEndpointStallState(unsigned char endpoint)
+{
+    return !!(MXC_USB->ep[endpoint] & MXC_F_USB_EP_STALL);
+}
+
+void USBHAL::_usbisr(void)
+{
+    instance->usbisr();
+}
+
+void USBHAL::usbisr(void)
+{
+    // get and clear irqs
+    uint32_t irq_flags = MXC_USB->dev_intfl;
+    MXC_USB->dev_intfl = irq_flags;
+
+    // process only enabled interrupts
+    irq_flags &= MXC_USB->dev_inten;
+
+    // suspend 
+    if (irq_flags & MXC_F_USB_DEV_INTFL_SUSP) {
+        suspendStateChanged(1);
+    }
+
+    // bus reset
+    if (irq_flags & MXC_F_USB_DEV_INTFL_BRST) {
+
+        // reset endpoints
+        for (int i = 0; i < MXC_USB_NUM_EP; i++) {
+            // Disable endpoint and clear the data toggle
+            MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR;
+            MXC_USB->ep[i] |= MXC_F_USB_EP_DT;
+        }
+
+        // clear driver state
+        control_state = CTRL_NONE;
+
+        busReset();
+
+        // no need to process events after reset
+        return;
+    }
+
+    // Setup packet
+    if (irq_flags & MXC_F_USB_DEV_INTFL_SETUP) {
+        control_state = CTRL_SETUP;
+        EP0setupCallback();
+    }
+
+    // IN packets
+    if (irq_flags & MXC_F_USB_DEV_INTFL_EP_IN) {
+        // get and clear IN irqs
+        uint32_t in_irqs = MXC_USB->in_int;
+        MXC_USB->in_int = in_irqs;
+
+        if (in_irqs & 1) {
+            EP0in();
+        }
+
+        for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) {
+            uint32_t irq_mask = (1 << epnum);
+            if (in_irqs & irq_mask) {
+                uint8_t endpoint = (epnum << 1) | DIR_IN;
+                (instance->*(epCallback[endpoint]))();
+            }
+        }
+    }
+
+    // OUT packets
+    if (irq_flags & MXC_F_USB_DEV_INTFL_EP_OUT) {
+        // get and clear OUT irqs
+        uint32_t out_irqs = MXC_USB->out_int;
+        MXC_USB->out_int = out_irqs;
+
+        if (out_irqs & 1) {
+            EP0out();
+        }
+
+        for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) {
+            uint32_t irq_mask = (1 << epnum);
+            if (out_irqs & irq_mask) {
+                uint8_t endpoint = (epnum << 1) | DIR_OUT;
+                (instance->*(epCallback[endpoint]))();
+            }
+        }
+    }
+}
+
+#endif

libraries/USBDevice/USBMIDI/MIDIMessage.h

@@ -21,6 +21,8 @@
 
 #include "mbed.h"
 
+#define MAX_MIDI_MESSAGE_SIZE 256 // Max message size. SysEx can be up to 65536 but 256 should be fine for most usage
+
 // MIDI Message Format
 //
 // [ msg(4) | channel(4) ] [ 0 | n(7) ] [ 0 | m(7) ]
@@ -49,6 +51,16 @@ public:
             data[i] = buf[i];
     }
 
+    // New constructor, buf is a true MIDI message (not USBMidi message) and buf_len true message length.
+    MIDIMessage(uint8_t *buf, int buf_len) {
+        length=buf_len+1;
+        // first byte keeped for retro-compatibility
+        data[0]=0;
+
+        for (int i = 0; i < buf_len; i++)
+            data[i+1] = buf[i];
+    }
+
     // create messages
 
     /** Create a NoteOff message
@@ -162,6 +174,16 @@ public:
         return ControlChange(123, 0, channel);
     }
 
+     /** Create a SysEx message
+     * @param data SysEx data (including 0xF0 .. 0xF7)
+     * @param len SysEx data length
+     * @returns A MIDIMessage
+     */
+    static MIDIMessage SysEx(uint8_t *data, int len) {
+        MIDIMessage msg=MIDIMessage(data,len);
+        return msg;
+    }
+
     // decode messages
 
     /** MIDI Message Types */
@@ -174,7 +196,8 @@ public:
         ProgramChangeType,
         ChannelAftertouchType,
         PitchWheelType,
-        AllNotesOffType
+        AllNotesOffType,
+        SysExType
     };
 
     /** Read the message type
@@ -196,6 +219,7 @@ public:
             case 0xC: return ProgramChangeType;
             case 0xD: return ChannelAftertouchType;
             case 0xE: return PitchWheelType;
+            case 0xF: return SysExType;
             default: return ErrorType;
         }
     }
@@ -245,7 +269,8 @@ public:
         return p - 8192; // 0 - 16383, 8192 is center
     }
 
-    uint8_t data[4];
+    uint8_t data[MAX_MIDI_MESSAGE_SIZE+1];
+    uint8_t length=4;
 };
 
 #endif

libraries/USBDevice/USBMIDI/USBMIDI.cpp

@@ -25,8 +25,49 @@ USBMIDI::USBMIDI(uint16_t vendor_id, uint16_t product_id, uint16_t product_relea
     USBDevice::connect();
 }
 
+// write plain MIDIMessage that will be converted to USBMidi event packet
 void USBMIDI::write(MIDIMessage m) {
-    USBDevice::write(EPBULK_IN, m.data, 4, MAX_PACKET_SIZE_EPBULK);
+    // first byte keeped for retro-compatibility
+    for(int p=1; p < m.length; p+=3) {
+        uint8_t buf[4];
+        // Midi message to USBMidi event packet
+        buf[0]=m.data[1] >> 4;
+        // SysEx
+        if(buf[0] == 0xF) {
+            if((m.length - p) > 3) {
+                // SysEx start or continue
+                buf[0]=0x4;
+            } else {
+                switch(m.length - p) {
+                    case 1:
+                        // SysEx end with one byte
+                        buf[0]=0x5;
+                        break;
+                    case 2:
+                        // SysEx end with two bytes
+                        buf[0]=0x6;
+                        break;
+                    case 3:
+                        // SysEx end with three bytes
+                        buf[0]=0x7;
+                        break;
+                }
+            }
+        }
+        buf[1]=m.data[p];
+
+        if(p+1 < m.length)
+            buf[2]=m.data[p+1];
+        else
+            buf[2]=0;
+
+        if(p+2 < m.length)
+            buf[3]=m.data[p+2];
+        else
+            buf[3]=0;
+
+        USBDevice::write(EPBULK_IN, buf, 4, MAX_PACKET_SIZE_EPBULK);
+    }
 }
 
 
@@ -34,7 +75,6 @@ void USBMIDI::attach(void (*fptr)(MIDIMessage)) {
     midi_evt = fptr;
 }
 
-
 bool USBMIDI::EPBULK_OUT_callback() {
     uint8_t buf[64];
     uint32_t len;
@@ -42,7 +82,53 @@ bool USBMIDI::EPBULK_OUT_callback() {
 
     if (midi_evt != NULL) {
         for (uint32_t i=0; i<len; i+=4) {   
-            midi_evt(MIDIMessage(buf+i));
+            uint8_t data_read;
+            data_end=true;
+            switch(buf[i]) {
+            case 0x2:
+                // Two-bytes System Common Message - undefined in USBMidi 1.0
+                data_read=2;
+                break;
+            case 0x4:
+                // SysEx start or continue
+                data_end=false;
+                data_read=3;
+                break;
+            case 0x5:
+                 // Single-byte System Common Message or SysEx end with one byte
+                data_read=1;
+                break;
+            case 0x6:
+                // SysEx end with two bytes
+                data_read=2;
+                break;
+            case 0xC:
+                // Program change
+                data_read=2;
+                break;
+            case 0xD:
+                // Channel pressure
+                data_read=2;
+                break;      
+            case 0xF:
+                // Single byte
+                data_read=1;
+                break;    
+            default:
+                // Others three-bytes messages
+                data_read=3;
+                break;      
+            } 
+        
+            for(uint8_t j=1;j<data_read+1;j++) {
+                data[cur_data]=buf[i+j];
+                cur_data++;
+            }
+        
+            if(data_end) {
+                 midi_evt(MIDIMessage(data,cur_data));
+                 cur_data=0;            
+            }
        }
     }
 
@@ -51,8 +137,6 @@ bool USBMIDI::EPBULK_OUT_callback() {
     return true;
 }
 
-
-
 // Called in ISR context
 // Set configuration. Return false if the
 // configuration is not supported.

libraries/USBDevice/USBMIDI/USBMIDI.h

@@ -102,8 +102,11 @@ protected:
     virtual uint8_t * configurationDesc();
 
 private:
-    void (*midi_evt)(MIDIMessage);
+    uint8_t data[MAX_MIDI_MESSAGE_SIZE+1];
+    uint8_t cur_data=0;
+    bool data_end = true;
     
+    void (*midi_evt)(MIDIMessage);
 };
 
 #endif

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/MAX32600.sct

@@ -0,0 +1,21 @@
+
+; MAX32600
+; 256KB FLASH (0x40000) @ 0x000000000
+; 2KB RAM (0x8000) @ 0x20000000
+
+
+; MAX32600: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+
+LR_IROM1 0x00000000 0x40000  {    ; load region size_region
+    ER_IROM1 0x00000000 0x40000  {  ; load address = execution address 
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+
+    ; [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = (0x140) - alignment
+    RW_IRAM1 (0x20000000+0x140) (0x8000-0x140)  {  ; RW data
+        .ANY (+RW +ZI)
+    }
+
+}

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/startup_MAX32600.s

@@ -0,0 +1,255 @@
+;*******************************************************************************
+; Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+;
+; Permission is hereby granted, free of charge, to any person obtaining a
+; copy of this software and associated documentation files (the "Software"),
+; to deal in the Software without restriction, including without limitation
+; the rights to use, copy, modify, merge, publish, distribute, sublicense,
+; and/or sell copies of the Software, and to permit persons to whom the
+; Software is furnished to do so, subject to the following conditions:
+;
+; The above copyright notice and this permission notice shall be included
+; in all copies or substantial portions of the Software.
+;
+; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+; OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+; IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+; OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+; ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+; OTHER DEALINGS IN THE SOFTWARE.
+;
+; Except as contained in this notice, the name of Maxim Integrated
+; Products, Inc. shall not be used except as stated in the Maxim Integrated
+; Products, Inc. Branding Policy.
+;
+; The mere transfer of this software does not imply any licenses
+; of trade secrets, proprietary technology, copyrights, patents,
+; trademarks, maskwork rights, or any other form of intellectual
+; property whatsoever. Maxim Integrated Products, Inc. retains all
+; ownership rights.
+;*******************************************************************************
+
+__initial_sp        EQU     0x20008000  ; Top of RAM
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     DefaultIRQ_Handler        ; MPU Fault Handler
+                DCD     DefaultIRQ_Handler        ; Bus Fault Handler
+                DCD     DefaultIRQ_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     DefaultIRQ_Handler        ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     DefaultIRQ_Handler        ; PendSV Handler
+                DCD     SysTick_IRQHandler        ; SysTick Handler
+
+                ; Maxim 32600 Externals interrupts
+                DCD     UART0_IRQHandler          ; 16: 1 UART0
+                DCD     UART1_IRQHandler          ; 17: 2 UART1
+                DCD     I2CM0_IRQHandler          ; 18: 3 I2C Master 0
+                DCD     I2CS_IRQHandler           ; 19: 4 I2C Slave
+                DCD     USB_IRQHandler            ; 20: 5 USB
+                DCD     PMU_IRQHandler            ; 21: 6 DMA
+                DCD     AFE_IRQHandler            ; 22: 7 AFE
+                DCD     MAA_IRQHandler            ; 23: 8 MAA
+                DCD     AES_IRQHandler            ; 24: 9 AES
+                DCD     SPI0_IRQHandler           ; 25:10 SPI0
+                DCD     SPI1_IRQHandler           ; 26:11 SPI1
+                DCD     SPI2_IRQHandler           ; 27:12 SPI2
+                DCD     TMR0_IRQHandler           ; 28:13 Timer32-0
+                DCD     TMR1_IRQHandler           ; 29:14 Timer32-1
+                DCD     TMR2_IRQHandler           ; 30:15 Timer32-1
+                DCD     TMR3_IRQHandler           ; 31:16 Timer32-2
+                DCD     RSVD0_IRQHandler          ; 32:17 RSVD
+                DCD     RSVD1_IRQHandler          ; 33:18 RSVD
+                DCD     DAC0_IRQHandler           ; 34:19 DAC0  (12-bit DAC)  
+                DCD     DAC1_IRQHandler           ; 35:20 DAC1  (12-bit DAC)  
+                DCD     DAC2_IRQHandler           ; 36:21 DAC2  (8-bit DAC)
+                DCD     DAC3_IRQHandler           ; 37:22 DAC3  (8-bit DAC)
+                DCD     ADC_IRQHandler            ; 38:23 ADC
+                DCD     FLC_IRQHandler            ; 39:24 Flash Controller
+                DCD     PWRMAN_IRQHandler         ; 40:25 PWRMAN
+                DCD     CLKMAN_IRQHandler         ; 41:26 CLKMAN
+                DCD     RTC0_IRQHandler           ; 42:27 RTC INT0
+                DCD     RTC1_IRQHandler           ; 43:28 RTC INT1
+                DCD     RTC2_IRQHandler           ; 44:29 RTC INT2
+                DCD     RTC3_IRQHandler           ; 45:30 RTC INT3
+                DCD     WDT0_IRQHandler           ; 46:31 WATCHDOG0
+                DCD     WDT0_P_IRQHandler         ; 47:32 WATCHDOG0 PRE-WINDOW
+                DCD     WDT1_IRQHandler           ; 48:33 WATCHDOG1
+                DCD     WDT1_P_IRQHandler         ; 49:34 WATCHDOG1 PRE-WINDOW
+                DCD     GPIO_P0_IRQHandler        ; 50:35 GPIO Port 0 
+                DCD     GPIO_P1_IRQHandler        ; 51:36 GPIO Port 1 
+                DCD     GPIO_P2_IRQHandler        ; 52:37 GPIO Port 2 
+                DCD     GPIO_P3_IRQHandler        ; 53:38 GPIO Port 3 
+                DCD     GPIO_P4_IRQHandler        ; 54:39 GPIO Port 4 
+                DCD     GPIO_P5_IRQHandler        ; 55:40 GPIO Port 5 
+                DCD     GPIO_P6_IRQHandler        ; 56:41 GPIO Port 6 
+                DCD     GPIO_P7_IRQHandler        ; 57:42 GPIO Port 7 
+                DCD     TMR16_0_IRQHandler        ; 58:43 Timer16-s0
+                DCD     TMR16_1_IRQHandler        ; 59:44 Timer16-s1
+                DCD     TMR16_2_IRQHandler        ; 60:45 Timer16-s2
+                DCD     TMR16_3_IRQHandler        ; 61:46 Timer16-s3
+                DCD     I2CM1_IRQHandler          ; 62:47 I2C Master 1
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+Reset_Handler   PROC
+                EXPORT Reset_Handler                    [WEAK]
+                IMPORT SystemInit
+                IMPORT __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler             PROC
+                        EXPORT NMI_Handler                      [WEAK]     
+                        B       NMI_Handler
+                        ENDP
+
+HardFault_Handler       PROC
+                        EXPORT HardFault_Handler                [WEAK]             
+                        B       HardFault_Handler
+                        ENDP
+
+DefaultIRQ_Handler      PROC
+                        EXPORT DefaultIRQ_Handler               [WEAK]             
+                        B       DefaultIRQ_Handler
+                        ENDP
+
+DebugMon_Handler        PROC
+                        EXPORT DebugMon_Handler                 [WEAK]             
+                        B       DebugMon_Handler
+                        ENDP
+
+SysTick_IRQHandler      PROC
+                        EXPORT SysTick_IRQHandler               [WEAK]             
+                        B       SysTick_IRQHandler
+                        ENDP
+
+Default_Handler PROC
+
+        EXPORT UART0_IRQHandler                         [WEAK]                              
+        EXPORT UART1_IRQHandler                         [WEAK]                              
+        EXPORT I2CM0_IRQHandler                         [WEAK]                              
+        EXPORT I2CS_IRQHandler                          [WEAK]                             
+        EXPORT USB_IRQHandler                           [WEAK]             
+        EXPORT PMU_IRQHandler                           [WEAK]             
+        EXPORT AFE_IRQHandler                           [WEAK]                            
+        EXPORT MAA_IRQHandler                           [WEAK]                            
+        EXPORT AES_IRQHandler                           [WEAK]                            
+        EXPORT SPI0_IRQHandler                          [WEAK]                             
+        EXPORT SPI1_IRQHandler                          [WEAK]                             
+        EXPORT SPI2_IRQHandler                          [WEAK]                             
+        EXPORT TMR0_IRQHandler                          [WEAK]                             
+        EXPORT TMR1_IRQHandler                          [WEAK]                             
+        EXPORT TMR2_IRQHandler                          [WEAK]                             
+        EXPORT TMR3_IRQHandler                          [WEAK]                             
+        EXPORT RSVD0_IRQHandler                         [WEAK]                              
+        EXPORT RSVD1_IRQHandler                         [WEAK]                              
+        EXPORT DAC0_IRQHandler                          [WEAK]                             
+        EXPORT DAC1_IRQHandler                          [WEAK]                             
+        EXPORT DAC2_IRQHandler                          [WEAK]                             
+        EXPORT DAC3_IRQHandler                          [WEAK]                             
+        EXPORT ADC_IRQHandler                           [WEAK]             
+        EXPORT FLC_IRQHandler                           [WEAK]             
+        EXPORT PWRMAN_IRQHandler                        [WEAK]                               
+        EXPORT CLKMAN_IRQHandler                        [WEAK]                               
+        EXPORT RTC0_IRQHandler                          [WEAK]                             
+        EXPORT RTC1_IRQHandler                          [WEAK]                             
+        EXPORT RTC2_IRQHandler                          [WEAK]                             
+        EXPORT RTC3_IRQHandler                          [WEAK]                             
+        EXPORT WDT0_IRQHandler                          [WEAK]                             
+        EXPORT WDT0_P_IRQHandler                        [WEAK]                               
+        EXPORT WDT1_IRQHandler                          [WEAK]                             
+        EXPORT WDT1_P_IRQHandler                        [WEAK]                               
+        EXPORT GPIO_P0_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P1_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P2_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P3_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P4_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P5_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P6_IRQHandler                       [WEAK]                                
+        EXPORT GPIO_P7_IRQHandler                       [WEAK]                                
+        EXPORT TMR16_0_IRQHandler                       [WEAK]                                
+        EXPORT TMR16_1_IRQHandler                       [WEAK]                                
+        EXPORT TMR16_2_IRQHandler                       [WEAK]                                
+        EXPORT TMR16_3_IRQHandler                       [WEAK]                                
+        EXPORT I2CM1_IRQHandler                         [WEAK]               
+
+UART0_IRQHandler
+UART1_IRQHandler               
+I2CM0_IRQHandler
+I2CS_IRQHandler
+USB_IRQHandler
+PMU_IRQHandler
+AFE_IRQHandler
+MAA_IRQHandler
+AES_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+TMR0_IRQHandler
+TMR1_IRQHandler
+TMR2_IRQHandler
+TMR3_IRQHandler
+RSVD0_IRQHandler
+RSVD1_IRQHandler
+DAC0_IRQHandler
+DAC1_IRQHandler
+DAC2_IRQHandler
+DAC3_IRQHandler
+ADC_IRQHandler
+FLC_IRQHandler
+PWRMAN_IRQHandler
+CLKMAN_IRQHandler
+RTC0_IRQHandler
+RTC1_IRQHandler
+RTC2_IRQHandler
+RTC3_IRQHandler
+WDT0_IRQHandler
+WDT0_P_IRQHandler
+WDT1_IRQHandler
+WDT1_P_IRQHandler
+GPIO_P0_IRQHandler
+GPIO_P1_IRQHandler
+GPIO_P2_IRQHandler
+GPIO_P3_IRQHandler
+GPIO_P4_IRQHandler
+GPIO_P5_IRQHandler
+GPIO_P6_IRQHandler
+GPIO_P7_IRQHandler
+TMR16_0_IRQHandler
+TMR16_1_IRQHandler
+TMR16_2_IRQHandler
+TMR16_3_IRQHandler
+I2CM1_IRQHandler
+
+        B .
+        ENDP
+        ALIGN
+        END

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_ARM_STD/sys.cpp

@@ -0,0 +1,57 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/max32600.ld

@@ -0,0 +1,182 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+/******************************************************************************
+ *
+ * Linker configuration file, default ARM Cortex M3 produced by Maxim Integrated Inc.
+ *
+ *****************************************************************************/
+
+MEMORY
+{
+    FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* start from 0x0, fullsize flash, 256k */
+    RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* full-size SRAM, 32k */
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_GCC_ARM/startup_max32600.S

@@ -0,0 +1,262 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+    .syntax unified
+    .arch armv7-m
+
+/* Memory Model
+   The HEAP starts at the end of the DATA section and grows upward.
+   
+   The STACK starts at the end of the RAM and grows downward.
+   
+   The HEAP and stack STACK are only checked at compile time:
+   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+   
+   This is just a check for the bare minimum for the Heap+Stack area before
+   aborting compilation, it is not the run time limit:
+   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x00001000
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x00000C00
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    MemManage_Handler     /* MPU Fault Handler */
+    .long    BusFault_Handler      /* Bus Fault Handler */
+    .long    UsageFault_Handler    /* Usage Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    DebugMon_Handler      /* Debug Monitor Handler */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+    /* Externals interrupts */
+    .long UART0_IRQHandler          /* 16: 1 UART0 */
+    .long UART1_IRQHandler          /* 17: 2 UART1 */
+    .long I2CM0_IRQHandler          /* 18: 3 I2C Master 0 */
+    .long I2CS_IRQHandler           /* 19: 4 I2C Slave */
+    .long USB_IRQHandler            /* 20: 5 USB */
+    .long PMU_IRQHandler            /* 21: 6 DMA */
+    .long AFE_IRQHandler            /* 22: 7 AFE */
+    .long MAA_IRQHandler            /* 23: 8 MAA */
+    .long AES_IRQHandler            /* 24: 9 AES */
+    .long SPI0_IRQHandler           /* 25:10 SPI0 */
+    .long SPI1_IRQHandler           /* 26:11 SPI1 */
+    .long SPI2_IRQHandler           /* 27:12 SPI2 */
+    .long TMR0_IRQHandler           /* 28:13 Timer32-0 */
+    .long TMR1_IRQHandler           /* 29:14 Timer32-1 */
+    .long TMR2_IRQHandler           /* 30:15 Timer32-1 */
+    .long TMR3_IRQHandler           /* 31:16 Timer32-2 */
+    .long RSVD0_IRQHandler          /* 32:17 RSVD */
+    .long RSVD1_IRQHandler          /* 33:18 RSVD */
+    .long DAC0_IRQHandler           /* 34:19 DAC0  (12-bit DAC) */  
+    .long DAC1_IRQHandler           /* 35:20 DAC1  (12-bit DAC) */  
+    .long DAC2_IRQHandler           /* 36:21 DAC2  (8-bit DAC) */
+    .long DAC3_IRQHandler           /* 37:22 DAC3  (8-bit DAC) */
+    .long ADC_IRQHandler            /* 38:23 ADC */
+    .long FLC_IRQHandler            /* 39:24 Flash Controller */
+    .long PWRMAN_IRQHandler         /* 40:25 PWRMAN */
+    .long CLKMAN_IRQHandler         /* 41:26 CLKMAN */
+    .long RTC0_IRQHandler           /* 42:27 RTC INT0 */
+    .long RTC1_IRQHandler           /* 43:28 RTC INT1 */
+    .long RTC2_IRQHandler           /* 44:29 RTC INT2 */
+    .long RTC3_IRQHandler           /* 45:30 RTC INT3 */
+    .long WDT0_IRQHandler           /* 46:31 WATCHDOG0 */
+    .long WDT0_P_IRQHandler         /* 47:32 WATCHDOG0 PRE-WINDOW */
+    .long WDT1_IRQHandler           /* 48:33 WATCHDOG1 */
+    .long WDT1_P_IRQHandler         /* 49:34 WATCHDOG1 PRE-WINDOW */
+    .long GPIO_P0_IRQHandler        /* 50:35 GPIO Port 0  */
+    .long GPIO_P1_IRQHandler        /* 51:36 GPIO Port 1  */
+    .long GPIO_P2_IRQHandler        /* 52:37 GPIO Port 2  */
+    .long GPIO_P3_IRQHandler        /* 53:38 GPIO Port 3  */
+    .long GPIO_P4_IRQHandler        /* 54:39 GPIO Port 4  */
+    .long GPIO_P5_IRQHandler        /* 55:40 GPIO Port 5  */
+    .long GPIO_P6_IRQHandler        /* 56:41 GPIO Port 6  */
+    .long GPIO_P7_IRQHandler        /* 57:42 GPIO Port 7  */
+    .long TMR16_0_IRQHandler        /* 58:43 Timer16-s0 */
+    .long TMR16_1_IRQHandler        /* 59:44 Timer16-s1 */
+    .long TMR16_2_IRQHandler        /* 60:45 Timer16-s2 */
+    .long TMR16_3_IRQHandler        /* 61:46 Timer16-s3 */
+    .long I2CM1_IRQHandler          /* 62:47 I2C Master 1 */
+
+	
+    .text 	
+    .thumb
+    .thumb_func
+    .align 2
+    .globl   Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+.Lflash_to_ram_loop:
+    cmp     r2, r3
+    ittt    lt
+    ldrlt   r0, [r1], #4
+    strlt   r0, [r2], #4
+    blt    .Lflash_to_ram_loop
+
+.Lflash_to_ram_loop_end:
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx     r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+    .text
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+
+    def_default_handler    NMI_Handler
+    def_default_handler    HardFault_Handler
+    def_default_handler    MemManage_Handler
+    def_default_handler    BusFault_Handler
+    def_default_handler    UsageFault_Handler
+    def_default_handler    SVC_Handler
+    def_default_handler    DebugMon_Handler
+    def_default_handler    PendSV_Handler
+    def_default_handler    SysTick_Handler
+    def_default_handler    Default_Handler
+
+    .macro    def_irq_default_handler    handler_name
+    .weak     \handler_name
+    .set      \handler_name, Default_Handler
+    .endm
+ 
+    def_irq_default_handler UART0_IRQHandler          /* 16: 1 UART0 */
+    def_irq_default_handler UART1_IRQHandler          /* 17: 2 UART1 */
+    def_irq_default_handler I2CM0_IRQHandler          /* 18: 3 I2C Master 0 */
+    def_irq_default_handler I2CS_IRQHandler           /* 19: 4 I2C Slave */
+    def_irq_default_handler USB_IRQHandler            /* 20: 5 USB */
+    def_irq_default_handler PMU_IRQHandler            /* 21: 6 DMA */
+    def_irq_default_handler AFE_IRQHandler            /* 22: 7 AFE */
+    def_irq_default_handler MAA_IRQHandler            /* 23: 8 MAA */
+    def_irq_default_handler AES_IRQHandler            /* 24: 9 AES */
+    def_irq_default_handler SPI0_IRQHandler           /* 25:10 SPI0 */
+    def_irq_default_handler SPI1_IRQHandler           /* 26:11 SPI1 */
+    def_irq_default_handler SPI2_IRQHandler           /* 27:12 SPI2 */
+    def_irq_default_handler TMR0_IRQHandler           /* 28:13 Timer32-0 */
+    def_irq_default_handler TMR1_IRQHandler           /* 29:14 Timer32-1 */
+    def_irq_default_handler TMR2_IRQHandler           /* 30:15 Timer32-1 */
+    def_irq_default_handler TMR3_IRQHandler           /* 31:16 Timer32-2 */
+    def_irq_default_handler RSVD0_IRQHandler          /* 32:17 RSVD */
+    def_irq_default_handler RSVD1_IRQHandler          /* 33:18 RSVD */
+    def_irq_default_handler DAC0_IRQHandler           /* 34:19 DAC0  (12-bit DAC) */  
+    def_irq_default_handler DAC1_IRQHandler           /* 35:20 DAC1  (12-bit DAC) */  
+    def_irq_default_handler DAC2_IRQHandler           /* 36:21 DAC2  (8-bit DAC) */
+    def_irq_default_handler DAC3_IRQHandler           /* 37:22 DAC3  (8-bit DAC) */
+    def_irq_default_handler ADC_IRQHandler            /* 38:23 ADC */
+    def_irq_default_handler FLC_IRQHandler            /* 39:24 Flash Controller */
+    def_irq_default_handler PWRMAN_IRQHandler         /* 40:25 PWRMAN */
+    def_irq_default_handler CLKMAN_IRQHandler         /* 41:26 CLKMAN */
+    def_irq_default_handler RTC0_IRQHandler           /* 42:27 RTC INT0 */
+    def_irq_default_handler RTC1_IRQHandler           /* 43:28 RTC INT1 */
+    def_irq_default_handler RTC2_IRQHandler           /* 44:29 RTC INT2 */
+    def_irq_default_handler RTC3_IRQHandler           /* 45:30 RTC INT3 */
+    def_irq_default_handler WDT0_IRQHandler           /* 46:31 WATCHDOG0 */
+    def_irq_default_handler WDT0_P_IRQHandler         /* 47:32 WATCHDOG0 PRE-WINDOW */
+    def_irq_default_handler WDT1_IRQHandler           /* 48:33 WATCHDOG1 */
+    def_irq_default_handler WDT1_P_IRQHandler         /* 49:34 WATCHDOG1 PRE-WINDOW */
+    def_irq_default_handler GPIO_P0_IRQHandler        /* 50:35 GPIO Port 0  */
+    def_irq_default_handler GPIO_P1_IRQHandler        /* 51:36 GPIO Port 1  */
+    def_irq_default_handler GPIO_P2_IRQHandler        /* 52:37 GPIO Port 2  */
+    def_irq_default_handler GPIO_P3_IRQHandler        /* 53:38 GPIO Port 3  */
+    def_irq_default_handler GPIO_P4_IRQHandler        /* 54:39 GPIO Port 4  */
+    def_irq_default_handler GPIO_P5_IRQHandler        /* 55:40 GPIO Port 5  */
+    def_irq_default_handler GPIO_P6_IRQHandler        /* 56:41 GPIO Port 6  */
+    def_irq_default_handler GPIO_P7_IRQHandler        /* 57:42 GPIO Port 7  */
+    def_irq_default_handler TMR16_0_IRQHandler        /* 58:43 Timer16-s0 */
+    def_irq_default_handler TMR16_1_IRQHandler        /* 59:44 Timer16-s1 */
+    def_irq_default_handler TMR16_2_IRQHandler        /* 60:45 Timer16-s2 */
+    def_irq_default_handler TMR16_3_IRQHandler        /* 61:46 Timer16-s3 */
+    def_irq_default_handler I2CM1_IRQHandler          /* 62:47 I2C Master 1 */
+
+    .end

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/MAX32600.icf

@@ -0,0 +1,29 @@
+/* [ROM] */
+define symbol __intvec_start__        = 0x0;
+define symbol __region_ROM_start__    = 0x0;
+define symbol __region_ROM_end__      = 0x0003FFFF;
+
+/* [RAM] Vector table dynamic copy: 79 vectors * 4 bytes = 316 bytes (0x13C) */
+define symbol __NVIC_start__          = 0x00000000;
+define symbol __NVIC_end__            = 0x00000140; /* to be aligned on 8 bytes */
+define symbol __region_RAM_start__    = 0x20000000;
+define symbol __region_RAM_end__      = 0x20007FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __region_ROM_start__   to __region_ROM_end__];
+define region RAM_region      = mem:[from __region_RAM_start__   to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x800;
+define symbol __size_heap__   = 0x800;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/startup_MAX32600.s

@@ -0,0 +1,383 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+                MODULE  ?cstartup
+
+                ;; Forward declaration of sections.
+                SECTION CSTACK:DATA:NOROOT(3)
+
+                SECTION .intvec:CODE:NOROOT(2)
+
+                EXTERN  __iar_program_start
+                EXTERN  SystemInit
+                PUBLIC  __vector_table
+
+                DATA
+__vector_table  DCD     sfe(CSTACK)               /* Top of Stack */
+                DCD     Reset_Handler             /* Reset Handler */
+                DCD     NMI_Handler               /* NMI Handler */
+                DCD     HardFault_Handler         /* Hard Fault Handler */
+                DCD     DefaultIRQ_Handler        /* MPU Fault Handler */
+                DCD     DefaultIRQ_Handler        /* Bus Fault Handler */
+                DCD     DefaultIRQ_Handler        /* Usage Fault Handler */
+                DCD     0                         /* Reserved */
+                DCD     0                         /* Reserved */
+                DCD     0                         /* Reserved */
+                DCD     0                         /* Reserved */
+                DCD     DefaultIRQ_Handler        /* SVCall Handler */
+                DCD     DebugMon_Handler          /* Debug Monitor Handler */
+                DCD     0                         /* Reserved */
+                DCD     DefaultIRQ_Handler        /* PendSV Handler */
+                DCD     SysTick_IRQHandler        /* SysTick Handler */
+
+                /* Maxim 32600 Externals interrupts */
+                DCD     UART0_IRQHandler          /* 16: 1 UART0 */
+                DCD     UART1_IRQHandler          /* 17: 2 UART1 */
+                DCD     I2CM0_IRQHandler          /* 18: 3 I2C Master 0 */
+                DCD     I2CS_IRQHandler           /* 19: 4 I2C Slave */
+                DCD     USB_IRQHandler            /* 20: 5 USB */
+                DCD     PMU_IRQHandler            /* 21: 6 DMA */
+                DCD     AFE_IRQHandler            /* 22: 7 AFE */
+                DCD     MAA_IRQHandler            /* 23: 8 MAA */
+                DCD     AES_IRQHandler            /* 24: 9 AES */
+                DCD     SPI0_IRQHandler           /* 25:10 SPI0 */
+                DCD     SPI1_IRQHandler           /* 26:11 SPI1 */
+                DCD     SPI2_IRQHandler           /* 27:12 SPI2 */
+                DCD     TMR0_IRQHandler           /* 28:13 Timer32-0 */
+                DCD     TMR1_IRQHandler           /* 29:14 Timer32-1 */
+                DCD     TMR2_IRQHandler           /* 30:15 Timer32-1 */
+                DCD     TMR3_IRQHandler           /* 31:16 Timer32-2 */
+                DCD     RSVD0_IRQHandler          /* 32:17 RSVD */
+                DCD     RSVD1_IRQHandler          /* 33:18 RSVD */
+                DCD     DAC0_IRQHandler           /* 34:19 DAC0  (12-bit DAC) */  
+                DCD     DAC1_IRQHandler           /* 35:20 DAC1  (12-bit DAC) */  
+                DCD     DAC2_IRQHandler           /* 36:21 DAC2  (8-bit DAC) */
+                DCD     DAC3_IRQHandler           /* 37:22 DAC3  (8-bit DAC) */
+                DCD     ADC_IRQHandler            /* 38:23 ADC */
+                DCD     FLC_IRQHandler            /* 39:24 Flash Controller */
+                DCD     PWRMAN_IRQHandler         /* 40:25 PWRMAN */
+                DCD     CLKMAN_IRQHandler         /* 41:26 CLKMAN */
+                DCD     RTC0_IRQHandler           /* 42:27 RTC INT0 */
+                DCD     RTC1_IRQHandler           /* 43:28 RTC INT1 */
+                DCD     RTC2_IRQHandler           /* 44:29 RTC INT2 */
+                DCD     RTC3_IRQHandler           /* 45:30 RTC INT3 */
+                DCD     WDT0_IRQHandler           /* 46:31 WATCHDOG0 */
+                DCD     WDT0_P_IRQHandler         /* 47:32 WATCHDOG0 PRE-WINDOW */
+                DCD     WDT1_IRQHandler           /* 48:33 WATCHDOG1 */
+                DCD     WDT1_P_IRQHandler         /* 49:34 WATCHDOG1 PRE-WINDOW */
+                DCD     GPIO_P0_IRQHandler        /* 50:35 GPIO Port 0  */
+                DCD     GPIO_P1_IRQHandler        /* 51:36 GPIO Port 1  */
+                DCD     GPIO_P2_IRQHandler        /* 52:37 GPIO Port 2  */
+                DCD     GPIO_P3_IRQHandler        /* 53:38 GPIO Port 3  */
+                DCD     GPIO_P4_IRQHandler        /* 54:39 GPIO Port 4  */
+                DCD     GPIO_P5_IRQHandler        /* 55:40 GPIO Port 5  */
+                DCD     GPIO_P6_IRQHandler        /* 56:41 GPIO Port 6  */
+                DCD     GPIO_P7_IRQHandler        /* 57:42 GPIO Port 7  */
+                DCD     TMR16_0_IRQHandler        /* 58:43 Timer16-s0 */
+                DCD     TMR16_1_IRQHandler        /* 59:44 Timer16-s1 */
+                DCD     TMR16_2_IRQHandler        /* 60:45 Timer16-s2 */
+                DCD     TMR16_3_IRQHandler        /* 61:46 Timer16-s3 */
+                DCD     I2CM1_IRQHandler          /* 62:47 I2C Master 1 */
+
+                THUMB
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+                PUBWEAK Reset_Handler
+                SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__iar_program_start
+                BX      R0
+	
+                PUBWEAK NMI_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+                B       NMI_Handler
+
+                PUBWEAK HardFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+                B       HardFault_Handler
+
+                PUBWEAK DefaultIRQ_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DefaultIRQ_Handler
+                B       DefaultIRQ_Handler
+                   
+                PUBWEAK DebugMon_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+                B       DebugMon_Handler
+
+                PUBWEAK SysTick_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_IRQHandler
+                B       SysTick_IRQHandler
+      
+                PUBWEAK UART0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+                B       UART0_IRQHandler
+    
+                PUBWEAK UART1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+UART1_IRQHandler
+                B       UART1_IRQHandler
+    
+                PUBWEAK I2CM0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+I2CM0_IRQHandler
+                B       I2CM0_IRQHandler
+    
+                PUBWEAK I2CS_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+I2CS_IRQHandler
+                B       I2CS_IRQHandler
+     
+                PUBWEAK USB_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+USB_IRQHandler
+                B       USB_IRQHandler
+      
+                PUBWEAK PMU_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+PMU_IRQHandler
+                B       PMU_IRQHandler
+      
+                PUBWEAK AFE_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+AFE_IRQHandler
+                B       AFE_IRQHandler
+      
+                PUBWEAK MAA_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+MAA_IRQHandler
+                B       MAA_IRQHandler
+      
+                PUBWEAK AES_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+AES_IRQHandler
+                B       AES_IRQHandler
+      
+                PUBWEAK SPI0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_IRQHandler
+                B       SPI0_IRQHandler
+     
+                PUBWEAK SPI1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+                B       SPI1_IRQHandler
+     
+                PUBWEAK SPI2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+                B       SPI2_IRQHandler
+     
+                PUBWEAK TMR0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR0_IRQHandler
+                B       TMR0_IRQHandler
+     
+                PUBWEAK TMR1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR1_IRQHandler
+                B       TMR1_IRQHandler
+     
+                PUBWEAK TMR2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR2_IRQHandler
+                B       TMR2_IRQHandler
+     
+                PUBWEAK TMR3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR3_IRQHandler
+                B       TMR3_IRQHandler
+     
+                PUBWEAK RSVD0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RSVD0_IRQHandler
+                B       RSVD0_IRQHandler
+    
+                PUBWEAK RSVD1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RSVD1_IRQHandler
+                B       RSVD1_IRQHandler
+    
+                PUBWEAK DAC0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DAC0_IRQHandler
+                B       DAC0_IRQHandler
+     
+                PUBWEAK DAC1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DAC1_IRQHandler
+                B       DAC1_IRQHandler
+     
+                PUBWEAK DAC2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DAC2_IRQHandler
+                B       DAC2_IRQHandler
+     
+                PUBWEAK DAC3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DAC3_IRQHandler
+                B       DAC3_IRQHandler
+     
+                PUBWEAK ADC_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+                B       ADC_IRQHandler
+      
+                PUBWEAK FLC_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+FLC_IRQHandler
+                B       FLC_IRQHandler
+    
+                PUBWEAK PWRMAN_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+PWRMAN_IRQHandler
+                B       PWRMAN_IRQHandler
+ 
+                PUBWEAK CLKMAN_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+CLKMAN_IRQHandler
+                B       CLKMAN_IRQHandler
+ 
+                PUBWEAK RTC0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+                B       RTC0_IRQHandler
+   
+                PUBWEAK RTC1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+                B       RTC1_IRQHandler
+   
+                PUBWEAK RTC2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RTC2_IRQHandler
+                B       RTC2_IRQHandler
+   
+                PUBWEAK RTC3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+RTC3_IRQHandler
+                B       RTC3_IRQHandler
+   
+                PUBWEAK WDT0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+WDT0_IRQHandler
+                B       WDT0_IRQHandler
+   
+                PUBWEAK WDT0_P_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+WDT0_P_IRQHandler
+                B       WDT0_P_IRQHandler
+ 
+                PUBWEAK WDT1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+WDT1_IRQHandler
+                B       WDT1_IRQHandler
+   
+                PUBWEAK WDT1_P_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+WDT1_P_IRQHandler
+                B       WDT1_P_IRQHandler
+ 
+                PUBWEAK GPIO_P0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P0_IRQHandler
+                B       GPIO_P0_IRQHandler
+
+                PUBWEAK GPIO_P1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P1_IRQHandler
+                B       GPIO_P1_IRQHandler
+
+                PUBWEAK GPIO_P2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P2_IRQHandler
+                B       GPIO_P2_IRQHandler
+
+                PUBWEAK GPIO_P3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P3_IRQHandler
+                B       GPIO_P3_IRQHandler
+
+                PUBWEAK GPIO_P4_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P4_IRQHandler
+                B       GPIO_P4_IRQHandler
+
+                PUBWEAK GPIO_P5_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P5_IRQHandler
+                B       GPIO_P5_IRQHandler
+
+                PUBWEAK GPIO_P6_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P6_IRQHandler
+                B       GPIO_P6_IRQHandler
+
+                PUBWEAK GPIO_P7_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+GPIO_P7_IRQHandler
+                B       GPIO_P7_IRQHandler
+
+                PUBWEAK TMR16_0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_0_IRQHandler
+                B       TMR16_0_IRQHandler
+
+                PUBWEAK TMR16_1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_1_IRQHandler
+                B       TMR16_1_IRQHandler
+
+                PUBWEAK TMR16_2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_2_IRQHandler
+                B       TMR16_2_IRQHandler
+
+                PUBWEAK TMR16_3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+TMR16_3_IRQHandler
+                B       TMR16_3_IRQHandler
+
+                PUBWEAK I2CM1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+I2CM1_IRQHandler
+                B       I2CM1_IRQHandler  
+	
+                END

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/adc_regs.h

@@ -0,0 +1,466 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_ADC_REGS_H
+#define _MXC_ADC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  adc_regs.h
+ * @addtogroup adc ADC
+ * @{
+ */
+
+/**
+ * @brief Defines ADC Modes.
+ */
+typedef enum {
+    /** Single Mode Full Rate */
+    MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
+    /** Single Mode Low Power */
+    MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
+    /** Continuous Mode Full Rate */
+    MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
+    /** Continuous Mode Low Power */
+    MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
+    /** Single Mode Full Rate with Scan Enabled */
+    MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
+    /** Single Mode Low Power with Scan Enabled */
+    MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
+    /** Continuous Mode Full Rate with Scan Enabled */
+    MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
+    /** Continuous Mode Low Power with Scan Enabled */
+    MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
+} mxc_adc_mode_t;
+
+/**
+ * @brief Defines ADC Range Control.
+ */
+typedef enum {
+    /** Bi-polar Operation (-Vref/2 -> Vref/2) */
+    MXC_E_ADC_RANGE_HALF = 0,
+    /** Bi-polar Operation (-Vref -> Vref) */
+    MXC_E_ADC_RANGE_FULL
+} mxc_adc_range_t;
+
+/**
+ * @brief Defines ADC Bipolar operation.
+ */
+typedef enum {
+    /** Uni-polar operation (0 -> Vref) */
+    MXC_E_ADC_BI_POL_UNIPOLAR = 0,
+    /** Bi-polar operation see ADC Range Control */
+    MXC_E_ADC_BI_POL_BIPOLAR
+} mxc_adc_bi_pol_t;
+
+/**
+ * @brief Defines Decimation Filter Modes.
+ */
+typedef enum {
+    /** Decimation Filter ByPassed */
+    MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
+    /** Output Average Only*/
+    MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
+    /** Output Average and Raw Data (Test Mode Only) */
+    MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
+} mxc_adc_avg_mode_t;
+
+/**
+ * @brief Defines ADC StartMode Modes.
+ */
+typedef enum {
+    /** StarMode via Software */
+    MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
+    /** StarMode via PulseTrain */
+    MXC_E_ADC_STRT_MODE_PULSETRAIN
+} mxc_adc_strt_mode_t;
+
+/**
+ * @brief Defines Mux Channel Select for the Positive Input to the ADC.
+ */
+typedef enum {
+    /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8-  */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
+    /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9-  */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
+    /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
+    /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
+    /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
+    /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13-  */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
+    /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14-  */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
+    /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15-  */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
+    /** Single Mode Input AIN8+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
+    /** Single Mode Input AIN9+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
+    /** Single Mode Input AIN10+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
+    /** Single Mode Input AIN11+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
+    /** Single Mode Input AIN12+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
+    /** Single Mode Input AIN13+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
+    /** Single Mode Input AIN14+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
+    /** Single Mode Input AIN15+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
+    /** Positive Input VSSADC */
+    MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
+    /** Positive Input TMON_R */
+    MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
+    /** Positive Input VDDA/4 */
+    MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
+    /** Positive Input PWRMAN_TST */
+    MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
+    /** Positive Input Ain0Div */
+    MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
+    /** Positive Input OpAmp OUTA */
+    MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
+    /** Positive Input OpAmp OUTB */
+    MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
+    /** Positive Input OpAmp OUTC */
+    MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
+    /** Positive Input OpAmp OUTD */
+    MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
+    /** Positive INA+ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
+    /** Positive SNO_or */
+    MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
+    /** Positive SCM_or */
+    MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
+    /** Positive TPROBE_sense */
+    MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
+    /** Positive VREFDAC */
+    MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
+    /** Positive VREFADJ */
+    MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
+    /** Positive Vdd3xtal */
+    MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
+} mxc_adc_pga_mux_ch_sel_t;
+
+/**
+ * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
+ */
+typedef enum {
+    /** Differential Mode Disabled */
+    MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
+    /** Differential Mode Enabled */
+    MXC_E_ADC_PGA_MUX_DIFF_ENABLE
+} mxc_adc_pga_mux_diff_t;
+
+/**
+ * @brief Defines the PGA Gain Options.
+ */
+typedef enum {
+    /** PGA Gain = 1 */
+    MXC_E_ADC_PGA_GAIN_1 = 0,
+    /** PGA Gain = 2 */
+    MXC_E_ADC_PGA_GAIN_2,
+    /** PGA Gain = 4 */
+    MXC_E_ADC_PGA_GAIN_4,
+    /** PGA Gain = 8 */
+    MXC_E_ADC_PGA_GAIN_8,
+} mxc_adc_pga_gain_t;
+
+/**
+ * @brief Defines the Switch Control Mode.
+ */
+typedef enum {
+    /** Switch Control Mode = Software */
+    MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
+    /** Switch Control Mode = Pulse Train */
+    MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
+} mxc_adc_spst_sw_ctrl_t;
+
+/**
+ * @brief Defines the number of channels to scan when Scan Mode is enabled.
+ */
+typedef enum {
+    /** Number of Channels to Scan = 1 */
+    MXC_E_ADC_SCAN_CNT_1 = 0,
+    /** Number of Channels to Scan = 2 */
+    MXC_E_ADC_SCAN_CNT_2,
+    /** Number of Channels to Scan = 3 */
+    MXC_E_ADC_SCAN_CNT_3,
+    /** Number of Channels to Scan = 4 */
+    MXC_E_ADC_SCAN_CNT_4,
+    /** Number of Channels to Scan = 5 */
+    MXC_E_ADC_SCAN_CNT_5,
+    /** Number of Channels to Scan = 6 */
+    MXC_E_ADC_SCAN_CNT_6,
+    /** Number of Channels to Scan = 7 */
+    MXC_E_ADC_SCAN_CNT_7,
+    /** Number of Channels to Scan = 8 */
+    MXC_E_ADC_SCAN_CNT_8,
+} mxc_adc_scan_cnt_t;
+
+/*                                              Offset   Register Description
+                                                ======   =================================================== */
+typedef struct {
+    __IO uint32_t ctrl0;                    /*  0x0000   ADC Control Register 0                              */
+    __IO uint32_t pga_ctrl;                 /*  0x0004   PGA Control Register                                */
+    __IO uint32_t tg_ctrl0;                 /*  0x0008   ADC Timing Generator Control 0                      */
+    __IO uint32_t tg_ctrl1;                 /*  0x000C   ADC Timing Generator Control 1                      */
+    __IO uint32_t limit;                    /*  0x0010   ADC Limit Settings                                  */
+    __IO uint32_t intr;                     /*  0x0014   ADC Interrupt Flags and Enable/Disable Controls     */
+    __IO uint32_t out;                      /*  0x0018   ADC Output Register                                 */
+} mxc_adc_regs_t;
+
+/*                                              Offset   Register Description
+                                                ======   =================================================== */
+typedef struct {
+    __IO uint32_t ctrl1;                    /*  0x0000   ADC Control Register 1                              */
+    __IO uint32_t scan1;                    /*  0x0004   ADC Auto-Scan Settings 1                            */
+    __IO uint32_t scan2;                    /*  0x0008   ADC Auto-Scan Settings 2                            */
+    __IO uint32_t ro_cal0;                  /*  0x000C   ADC Ring Osc Calibration 0                          */
+    __IO uint32_t ro_cal1;                  /*  0x0010   ADC Ring Osc Calibration 1                          */
+} mxc_adccfg_regs_t;
+
+typedef struct {
+    __IO uint16_t data;                     /*  0x0000   Read to pull sample data from ADC FIFO              */
+} mxc_adc_fifo_regs_t;
+
+/*
+   Register offsets for module ADC, ADCCFG, ADC_FIFO
+*/
+#define MXC_R_ADC_OFFS_CTRL0                      ((uint32_t)0x00000000UL)
+#define MXC_R_ADC_OFFS_PGA_CTRL                   ((uint32_t)0x00000004UL)
+#define MXC_R_ADC_OFFS_TG_CTRL0                   ((uint32_t)0x00000008UL)
+#define MXC_R_ADC_OFFS_TG_CTRL1                   ((uint32_t)0x0000000CUL)
+#define MXC_R_ADC_OFFS_LIMIT                      ((uint32_t)0x00000010UL)
+#define MXC_R_ADC_OFFS_INTR                       ((uint32_t)0x00000014UL)
+#define MXC_R_ADC_OFFS_OUT                        ((uint32_t)0x00000018UL)
+
+#define MXC_R_ADCCFG_OFFS_CTRL1                   ((uint32_t)0x00000000UL)
+#define MXC_R_ADCCFG_OFFS_SCAN1                   ((uint32_t)0x00000004UL)
+#define MXC_R_ADCCFG_OFFS_SCAN2                   ((uint32_t)0x00000008UL)
+#define MXC_R_ADCCFG_OFFS_RO_CAL0                 ((uint32_t)0x0000000CUL)
+#define MXC_R_ADCCFG_OFFS_RO_CAL1                 ((uint32_t)0x00000010UL)
+#define MXC_R_ADC_FIFO_OFFS_DATA                  ((uint32_t)0x00000000UL)
+
+/*
+   Field positions and masks for module ADC.
+*/
+#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS                    0
+#define MXC_F_ADC_CTRL0_ADC_WAKE_CNT                        ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
+#define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS                   5
+#define MXC_F_ADC_CTRL0_ADC_STRT_MODE                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_RANGE_POS                       6
+#define MXC_F_ADC_CTRL0_ADC_RANGE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
+#define MXC_F_ADC_CTRL0_ADC_BI_POL_POS                      7
+#define MXC_F_ADC_CTRL0_ADC_BI_POL                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
+#define MXC_F_ADC_CTRL0_ADC_DV_REG_POS                      8
+#define MXC_F_ADC_CTRL0_ADC_DV_REG                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
+#define MXC_F_ADC_CTRL0_ADC_DV_POS                          9
+#define MXC_F_ADC_CTRL0_ADC_DV                              ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
+#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS                   10
+#define MXC_F_ADC_CTRL0_ADC_LMT_DMODE                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS                     11
+#define MXC_F_ADC_CTRL0_ADC_SMP_EXT                         ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
+#define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS                      12
+#define MXC_F_ADC_CTRL0_ADC_CLK_EN                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS                     13
+#define MXC_F_ADC_CTRL0_CPU_ADC_RST                         ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_START_POS                   14
+#define MXC_F_ADC_CTRL0_CPU_ADC_START                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
+#define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS                      15
+#define MXC_F_ADC_CTRL0_CPU_ADC_EN                          ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
+#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS                   18
+#define MXC_F_ADC_CTRL0_ADC_FIFO_FULL                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
+#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS                  19
+#define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
+#define MXC_F_ADC_CTRL0_AVG_MODE_POS                        20
+#define MXC_F_ADC_CTRL0_AVG_MODE                            ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
+#define MXC_F_ADC_CTRL0_CPU_DAC_START_POS                   22
+#define MXC_F_ADC_CTRL0_CPU_DAC_START                       ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
+#define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS                    24
+#define MXC_F_ADC_CTRL0_ADC_CLK_MODE                        ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
+#define MXC_F_ADC_CTRL0_ADC_MODE_POS                        28
+#define MXC_F_ADC_CTRL0_ADC_MODE                            ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
+
+#define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS                     0
+#define MXC_F_ADC_PGA_CTRL_PGA_GAIN                         ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS           2
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN               ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS                  3
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST                      ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS            4
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY                ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS                  5
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK                      ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS               6
+#define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS                   ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
+#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS                 8
+#define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT                     ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS                   13
+#define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN                       ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS                     14
+#define MXC_F_ADC_PGA_CTRL_MUX_DIFF                         ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS                     15
+#define MXC_F_ADC_PGA_CTRL_MUX_MODE                         ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
+#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS              20
+#define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT                  ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
+#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS                   24
+#define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL                       ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
+
+#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS                  0
+#define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT                      ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
+#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS                 16
+#define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT                     ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
+
+#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS                  0
+#define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT                      ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS                  4
+#define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT                      ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS                 8
+#define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT                     ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS                  12
+#define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT                      ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
+#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS                  16
+#define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT                      ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
+
+#define MXC_F_ADC_LIMIT_LO_LIMIT_POS                        0
+#define MXC_F_ADC_LIMIT_LO_LIMIT                            ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
+#define MXC_F_ADC_LIMIT_HI_LIMIT_POS                        16
+#define MXC_F_ADC_LIMIT_HI_LIMIT                            ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
+
+#define MXC_F_ADC_INTR_FIFO_AF_POS                          6
+#define MXC_F_ADC_INTR_FIFO_AF                              ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
+#define MXC_F_ADC_INTR_OUT_RNG_IF_POS                       7
+#define MXC_F_ADC_INTR_OUT_RNG_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
+#define MXC_F_ADC_INTR_HI_RNG_IF_POS                        8
+#define MXC_F_ADC_INTR_HI_RNG_IF                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
+#define MXC_F_ADC_INTR_LO_RNG_IF_POS                        9
+#define MXC_F_ADC_INTR_LO_RNG_IF                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
+#define MXC_F_ADC_INTR_DONE_IF_POS                          10
+#define MXC_F_ADC_INTR_DONE_IF                              ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_UF_IF_POS                       11
+#define MXC_F_ADC_INTR_FIFO_UF_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_OF_IF_POS                       12
+#define MXC_F_ADC_INTR_FIFO_OF_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_3Q_IF_POS                       13
+#define MXC_F_ADC_INTR_FIFO_3Q_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_2Q_IF_POS                       14
+#define MXC_F_ADC_INTR_FIFO_2Q_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
+#define MXC_F_ADC_INTR_FIFO_1Q_IF_POS                       15
+#define MXC_F_ADC_INTR_FIFO_1Q_IF                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
+#define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS                  16
+#define MXC_F_ADC_INTR_SPST0_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS                  17
+#define MXC_F_ADC_INTR_SPST1_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS                  18
+#define MXC_F_ADC_INTR_SPST2_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS                  19
+#define MXC_F_ADC_INTR_SPST3_CTRL_MODE                      ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
+#define MXC_F_ADC_INTR_OUT_RNG_IE_POS                       23
+#define MXC_F_ADC_INTR_OUT_RNG_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
+#define MXC_F_ADC_INTR_HI_RNG_IE_POS                        24
+#define MXC_F_ADC_INTR_HI_RNG_IE                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
+#define MXC_F_ADC_INTR_LO_RNG_IE_POS                        25
+#define MXC_F_ADC_INTR_LO_RNG_IE                            ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
+#define MXC_F_ADC_INTR_DONE_IE_POS                          26
+#define MXC_F_ADC_INTR_DONE_IE                              ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_UF_IE_POS                       27
+#define MXC_F_ADC_INTR_FIFO_UF_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_OF_IE_POS                       28
+#define MXC_F_ADC_INTR_FIFO_OF_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_3Q_IE_POS                       29
+#define MXC_F_ADC_INTR_FIFO_3Q_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_2Q_IE_POS                       30
+#define MXC_F_ADC_INTR_FIFO_2Q_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
+#define MXC_F_ADC_INTR_FIFO_1Q_IE_POS                       31
+#define MXC_F_ADC_INTR_FIFO_1Q_IE                           ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
+
+#define MXC_F_ADC_OUT_DATA_REG_POS                          0
+#define MXC_F_ADC_OUT_DATA_REG                              ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
+
+#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS                    16
+#define MXC_F_ADC_CTRL1_ADC_SCAN_CNT                        ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
+
+#define MXC_F_ADC_SCAN1_ADC_SCAN0_POS                       0
+#define MXC_F_ADC_SCAN1_ADC_SCAN0                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN1_POS                       8
+#define MXC_F_ADC_SCAN1_ADC_SCAN1                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN2_POS                       16
+#define MXC_F_ADC_SCAN1_ADC_SCAN2                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
+#define MXC_F_ADC_SCAN1_ADC_SCAN3_POS                       24
+#define MXC_F_ADC_SCAN1_ADC_SCAN3                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
+
+#define MXC_F_ADC_SCAN2_ADC_SCAN4_POS                       0
+#define MXC_F_ADC_SCAN2_ADC_SCAN4                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN5_POS                       8
+#define MXC_F_ADC_SCAN2_ADC_SCAN5                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN6_POS                       16
+#define MXC_F_ADC_SCAN2_ADC_SCAN6                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
+#define MXC_F_ADC_SCAN2_ADC_SCAN7_POS                       24
+#define MXC_F_ADC_SCAN2_ADC_SCAN7                           ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
+
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS                     0
+#define MXC_F_ADC_RO_CAL0_RO_CAL_EN                         ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS                    1
+#define MXC_F_ADC_RO_CAL0_RO_CAL_RUN                        ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS                   2
+#define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD                       ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
+#define MXC_F_ADC_RO_CAL0_TRM_MU_POS                        8
+#define MXC_F_ADC_RO_CAL0_TRM_MU                            ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
+#define MXC_F_ADC_RO_CAL0_RO_TRM_POS                        23
+#define MXC_F_ADC_RO_CAL0_RO_TRM                            ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
+
+#define MXC_F_ADC_RO_CAL1_TRM_INIT_POS                      0
+#define MXC_F_ADC_RO_CAL1_TRM_INIT                          ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
+#define MXC_F_ADC_RO_CAL1_TRM_MIN_POS                       10
+#define MXC_F_ADC_RO_CAL1_TRM_MIN                           ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
+#define MXC_F_ADC_RO_CAL1_TRM_MAX_POS                       20
+#define MXC_F_ADC_RO_CAL1_TRM_MAX                           ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _MXC_ADC_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/aes_regs.h

@@ -0,0 +1,159 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_AES_REGS_H_
+#define _MXC_AES_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  aes_regs.h
+ * @addtogroup aes AES
+ * @{
+ */
+
+/**
+ * @brief  Settings for AES_CTRL.CRYPT_MODE 
+ */
+typedef enum {
+    MXC_E_AES_CTRL_ENCRYPT_MODE = 0,
+    MXC_E_AES_CTRL_DECRYPT_MODE = 1
+} mxc_aes_ctrl_crypt_mode_t;
+
+/**
+ * @brief Settings for AES_CTRL.EXP_KEY_MODE 
+ */
+typedef enum {
+    MXC_E_AES_CTRL_CALC_NEW_EXP_KEY = 0,
+    MXC_E_AES_CTRL_USE_LAST_EXP_KEY = 1
+} mxc_aes_ctrl_exp_key_mode_t;
+
+/**
+ * @brief Settings for AES_CTRL.KEY_SIZE 
+ */
+typedef enum {
+    MXC_E_AES_CTRL_KEY_SIZE_128 = 0,
+    MXC_E_AES_CTRL_KEY_SIZE_192 = 1,
+    MXC_E_AES_CTRL_KEY_SIZE_256 = 2
+} mxc_aes_ctrl_key_size_t;
+
+/*                                       Offset   Register Description
+                                         ======   =========================================================== */
+typedef struct {
+    __IO uint32_t ctrl;              /*  0x0000   AES Control and Status                                      */
+    __I uint32_t rsv004;             /*  0x0004                                                               */
+    __IO uint32_t erase_all;         /*  0x0008   Write to Trigger AES Memory Erase                           */
+} mxc_aes_regs_t;
+
+/*                                       Offset   Register Description
+                                         ======   =========================================================== */
+typedef struct {
+    __IO uint32_t inp[4];            /*  0x0000   AES Input 0..3                                              */
+    __IO uint32_t key[8];            /*  0x0010   AES Key 0..7                                                */
+    __IO uint32_t out[4];            /*  0x0030   AES Output 0..3                                             */
+    __IO uint32_t expkey[8];         /*  0x0040   AES Expanded Key Data 0..7                                  */
+} mxc_aes_mem_regs_t;
+
+/*
+   Register offsets for module AES.
+*/
+#define MXC_R_AES_OFFS_CTRL                       ((uint32_t)0x00000000UL)
+#define MXC_R_AES_OFFS_ERASE_ALL                  ((uint32_t)0x00000008UL)
+#define MXC_R_AES_MEM_OFFS_INP0                   ((uint32_t)0x00000000UL)
+#define MXC_R_AES_MEM_OFFS_INP1                   ((uint32_t)0x00000004UL)
+#define MXC_R_AES_MEM_OFFS_INP2                   ((uint32_t)0x00000008UL)
+#define MXC_R_AES_MEM_OFFS_INP3                   ((uint32_t)0x0000000CUL)
+#define MXC_R_AES_MEM_OFFS_KEY0                   ((uint32_t)0x00000010UL)
+#define MXC_R_AES_MEM_OFFS_KEY1                   ((uint32_t)0x00000014UL)
+#define MXC_R_AES_MEM_OFFS_KEY2                   ((uint32_t)0x00000018UL)
+#define MXC_R_AES_MEM_OFFS_KEY3                   ((uint32_t)0x0000001CUL)
+#define MXC_R_AES_MEM_OFFS_KEY4                   ((uint32_t)0x00000020UL)
+#define MXC_R_AES_MEM_OFFS_KEY5                   ((uint32_t)0x00000024UL)
+#define MXC_R_AES_MEM_OFFS_KEY6                   ((uint32_t)0x00000028UL)
+#define MXC_R_AES_MEM_OFFS_KEY7                   ((uint32_t)0x0000002CUL)
+#define MXC_R_AES_MEM_OFFS_OUT0                   ((uint32_t)0x00000030UL)
+#define MXC_R_AES_MEM_OFFS_OUT1                   ((uint32_t)0x00000034UL)
+#define MXC_R_AES_MEM_OFFS_OUT2                   ((uint32_t)0x00000038UL)
+#define MXC_R_AES_MEM_OFFS_OUT3                   ((uint32_t)0x0000003CUL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY0                ((uint32_t)0x00000040UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY1                ((uint32_t)0x00000044UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY2                ((uint32_t)0x00000048UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY3                ((uint32_t)0x0000004CUL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY4                ((uint32_t)0x00000050UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY5                ((uint32_t)0x00000054UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY6                ((uint32_t)0x00000058UL)
+#define MXC_R_AES_MEM_OFFS_EXPKEY7                ((uint32_t)0x0000005CUL)
+
+#define MXC_F_AES_CTRL_START_POS                  0
+#define MXC_F_AES_CTRL_START                      ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_START_POS))
+#define MXC_F_AES_CTRL_CRYPT_MODE_POS             1
+#define MXC_F_AES_CTRL_CRYPT_MODE                 ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+#define MXC_F_AES_CTRL_EXP_KEY_MODE_POS           2
+#define MXC_F_AES_CTRL_EXP_KEY_MODE               ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+#define MXC_F_AES_CTRL_KEY_SIZE_POS               3
+#define MXC_F_AES_CTRL_KEY_SIZE                   ((uint32_t)(0x00000003UL << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_F_AES_CTRL_INTEN_POS                  5
+#define MXC_F_AES_CTRL_INTEN                      ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTEN_POS))
+#define MXC_F_AES_CTRL_INTFL_POS                  6
+#define MXC_F_AES_CTRL_INTFL                      ((uint32_t)(0x00000001UL << MXC_F_AES_CTRL_INTFL_POS))
+
+#define MXC_V_AES_CTRL_ENCRYPT_MODE               0
+#define MXC_V_AES_CTRL_DECRYPT_MODE               1
+#define MXC_S_AES_CTRL_ENCRYPT_MODE               ((uint32_t)(MXC_V_AES_CTRL_ENCRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+#define MXC_S_AES_CTRL_DECRYPT_MODE               ((uint32_t)(MXC_V_AES_CTRL_DECRYPT_MODE << MXC_F_AES_CTRL_CRYPT_MODE_POS))
+
+#define MXC_V_AES_CTRL_CALC_NEW_EXP_KEY           0
+#define MXC_V_AES_CTRL_USE_LAST_EXP_KEY           1
+#define MXC_S_AES_CTRL_CALC_NEW_EXP_KEY           ((uint32_t)(MXC_V_AES_CTRL_CALC_NEW_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+#define MXC_S_AES_CTRL_USE_LAST_EXP_KEY           ((uint32_t)(MXC_V_AES_CTRL_USE_LAST_EXP_KEY << MXC_F_AES_CTRL_EXP_KEY_MODE_POS))
+
+#define MXC_V_AES_CTRL_KEY_SIZE_128               0
+#define MXC_V_AES_CTRL_KEY_SIZE_192               1
+#define MXC_V_AES_CTRL_KEY_SIZE_256               2
+#define MXC_S_AES_CTRL_KEY_SIZE_128               ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_128 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_S_AES_CTRL_KEY_SIZE_192               ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_192 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+#define MXC_S_AES_CTRL_KEY_SIZE_256               ((uint32_t)(MXC_V_AES_CTRL_KEY_SIZE_256 << MXC_F_AES_CTRL_KEY_SIZE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_AES_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/afe_regs.h

@@ -0,0 +1,626 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_AFE_REGS_H
+#define _MXC_AFE_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  afe_regs.h
+ * @addtogroup afe AFE
+ * @{
+ */
+
+/**
+ * @brief Defines Configure Options for the LED Ports.
+ */
+typedef enum {
+    /** LED Sink Port 0 with OpAmp A, LED Sink Port 1 with OpAmp C */
+    MXC_E_AFE_LED_CFG_PORT_OPAMP_A_C = 0,
+    /** LED Sink Port 0 with OpAmp B, LED Sink Port 1 with OpAmp D */
+    MXC_E_AFE_LED_CFG_PORT_OPAMP_B_D,
+    /** Disable LED Sink Port 0,Disable LED Sink Port 1 */
+    MXC_E_AFE_LED_CFG_PORT_DISABLED,
+} mxc_afe_led_cfg_port_t;
+
+/**
+ * @brief Setup of Wake Up Detector for LPCs.
+ */
+typedef enum {
+    /** IDLE */
+    MXC_E_AFE_EN_WUD_COMP_IDLE = 0,
+    /** Activate WUD for falling edges */
+    MXC_E_AFE_EN_WUD_COMP_FALLING_EDGE = 2,
+    /** Activate WUD for rising edges */
+    MXC_E_AFE_EN_WUD_COMP_RISING_EDGE = 3
+} mxc_afe_en_wud_comp_t;
+
+/**
+ * @brief LPC InMode.
+ */
+typedef enum {
+    /** InMode: both Nch and Pch */
+    MXC_E_AFE_IN_MODE_COMP_NCH_PCH = 0,
+    /** InMode: only Nch  */
+    MXC_E_AFE_IN_MODE_COMP_NCH,
+    /** InMode: only Pch  */
+    MXC_E_AFE_IN_MODE_COMP_PCH,
+} mxc_afe_in_mode_comp_t;
+
+/**
+ * @brief LPC Bias.
+ */
+typedef enum {
+    /** BIAS 0.52uA Delay 4.0us  */
+    MXC_E_AFE_BIAS_MODE_COMP_0 = 0,
+    /** BIAS 1.4uA Delay 1.7us  */
+    MXC_E_AFE_BIAS_MODE_COMP_1,
+    /** BIAS 2.8uA Delay 1.1us  */
+    MXC_E_AFE_BIAS_MODE_COMP_2,
+    /** BIAS 5.1uA Delay 0.7us  */
+    MXC_E_AFE_BIAS_MODE_COMP_3
+} mxc_afe_bias_mode_comp_t;
+
+/**
+ * @brief TMON Current Value.
+ */
+typedef enum {
+    /** TMON Current 4uA  */
+    MXC_E_AFE_TMON_CURRENT_VAL_0 = 0,
+    /** TMON Current 60uA  */
+    MXC_E_AFE_TMON_CURRENT_VAL_1,
+    /** TMON Current 64uA  */
+    MXC_E_AFE_TMON_CURRENT_VAL_2,
+    /** TMON Current 120uA  */
+    MXC_E_AFE_TMON_CURRENT_VAL_3
+} mxc_afe_tmon_current_t;
+
+/**
+ * @brief REFADC and REFDAC Voltage Select.
+ */
+typedef enum {
+    /** Voltage Reference = 1.024 V */
+    MXC_E_AFE_REF_VOLT_SEL_1024 = 0,
+    /** Voltage Reference = 1.5 V */
+    MXC_E_AFE_REF_VOLT_SEL_1500,
+    /** Voltage Reference = 2.048 V */
+    MXC_E_AFE_REF_VOLT_SEL_2048,
+    /** Voltage Reference = 2.5 V */
+    MXC_E_AFE_REF_VOLT_SEL_2500
+} mxc_afe_ref_volt_sel_t;
+
+/**
+ * @brief Selection for DAC VOltage Reference, REFADC or REFDAC.
+ */
+typedef enum {
+    /** DAC Voltage Reference = REFADC */
+    MXC_E_AFE_DAC_REF_REFADC = 0,
+    /** DAC Voltage Reference = REFDAC */
+    MXC_E_AFE_DAC_REF_REFDAC
+} mxc_afe_dac_ref_t;
+
+/**
+ * @brief Selection for LPC Hysteresis.
+ */
+typedef enum {
+    /** LPC Hysteresis = 0 mV */
+    MXC_E_AFE_HYST_COMP_0 = 0,
+    /** LPC Hysteresis = 7.5 mV */
+    MXC_E_AFE_HYST_COMP_1,
+    /** LPC Hysteresis = 15 mV */
+    MXC_E_AFE_HYST_COMP_2,
+    /** LPC Hysteresis = 30 mV */
+    MXC_E_AFE_HYST_COMP_3
+} mxc_afe_hyst_comp_t;
+
+/**
+ * @brief Selection for MUX for  SCM_or_sel.
+ */
+typedef enum {
+    /** SCM_or = HIZ */
+    MXC_E_AFE_SCM_OR_SEL_HIZ = 0,
+    /** SCM_or = SCM0 */
+    MXC_E_AFE_SCM_OR_SEL_SCM0,
+    /** SCM_or = SCM1 */
+    MXC_E_AFE_SCM_OR_SEL_SCM1,
+    /** SCM_or = SCM2 */
+    MXC_E_AFE_SCM_OR_SEL_SCM2,
+    /** SCM_or = SCM3 */
+    MXC_E_AFE_SCM_OR_SEL_SCM3
+} mxc_afe_scm_or_sel_t;
+
+/**
+ * @brief Selection for MUX for  SNO_or_sel.
+ */
+typedef enum {
+    /** SNO_or = HIZ */
+    MXC_E_AFE_SNO_OR_SEL_HIZ = 0,
+    /** SNO_or = SNO0 */
+    MXC_E_AFE_SNO_OR_SEL_SNO0,
+    /** SNO_or = SNO1 */
+    MXC_E_AFE_SNO_OR_SEL_SNO1,
+    /** SNO_or = SNO2 */
+    MXC_E_AFE_SNO_OR_SEL_SNO2,
+    /** SNO_or = SNO3 */
+    MXC_E_AFE_SNO_OR_SEL_SNO3
+} mxc_afe_sno_or_sel_t;
+
+/**
+ * @brief Selection for MUX  DACx_sel.
+ */
+typedef enum {
+    /** dacx  = DACOP */
+    MXC_E_AFE_DACX_SEL_P = 0,
+    /** dacx  = DACON */
+    MXC_E_AFE_DACX_SEL_N
+} mxc_afe_dacx_sel_t;
+
+/**
+ * @brief Selection for state of Switch.
+ */
+typedef enum {
+    /** Switch is OPEN */
+    MXC_E_AFE_CLOSE_SPST_SWITCH_OPEN = 0,
+    /** Switch is CLOSED */
+    MXC_E_AFE_CLOSE_SPST_SWITCH_CLOSE
+} mxc_afe_close_spst_t;
+
+/**
+ * @brief Switch to Connect Positive Pad to GND.
+ */
+typedef enum {
+    /** Positive Pad GND Switch OPEN */
+    MXC_E_AFE_GND_SEL_OPAMP_SWITCH_OPEN = 0,
+    /** Positive Pad GND Switch CLOSED */
+    MXC_E_AFE_GND_SEL_OPAMP_SWITCH_CLOSED
+} mxc_afe_gnd_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for OpPsel.
+ */
+typedef enum {
+    /** OpPsel = INx+ */
+    MXC_E_AFE_P_IN_SEL_OPAMP_INPLUS = 0,
+    /** OpPsel = DAC_or */
+    MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR,
+    /** OpPsel = SNO_or */
+    MXC_E_AFE_P_IN_SEL_OPAMP_SNO_OR,
+    /** OpPsel = DAC_or also output on INx+ */
+    MXC_E_AFE_P_IN_SEL_OPAMP_DAC_OR_AND_INPLUS
+} mxc_afe_p_in_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for OpNsel.
+ */
+typedef enum {
+    /** OpNsel = INx- */
+    MXC_E_AFE_N_IN_SEL_OPAMP_INMINUS = 0,
+    /** OpNsel = OUTx */
+    MXC_E_AFE_N_IN_SEL_OPAMP_OUT,
+    /** OpNsel = SCM_or */
+    MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR,
+    /**OpNsel = SCM_or also output on INx- */
+    MXC_E_AFE_N_IN_SEL_OPAMP_SCM_OR_AND_INMINUS,
+} mxc_afe_n_in_sel_opamp_t;
+
+/**
+ * @brief MUX Selection for DAC_sel.
+ */
+typedef enum {
+    /** DAC_or = DAC0 */
+    MXC_E_AFE_DAC_SEL_DAC0 = 0,
+    /** DAC_or = DAC1 */
+    MXC_E_AFE_DAC_SEL_DAC1,
+    /** DAC_or = DAC2P */
+    MXC_E_AFE_DAC_SEL_DAC2P,
+    /** DAC_or = DAC3P */
+    MXC_E_AFE_DAC_SEL_DAC3P
+} mxc_afe_dac_sel_t;
+
+/**
+ * @brief MUX Selection for NPAD_sel.
+ */
+typedef enum {
+    /** NPAD_Sel = HIZ */
+    MXC_E_AFE_NPAD_SEL_HIZ = 0,
+    /** NPAD_Sel = LED Observe Port */
+    MXC_E_AFE_NPAD_SEL_LED_OBS_PORT,
+    /** NPAD_Sel = DAC_or */
+    MXC_E_AFE_NPAD_SEL_DAC_OR,
+    /** NPAD_Sel = DAC_or and LED Observe Port */
+    MXC_E_AFE_NPAD_SEL_DAC_OR_AND_LED_OBS_PORT
+} mxc_afe_npad_sel_t;
+
+/**
+ * @brief MUX Selection for CmpPSel.
+ */
+typedef enum {
+    /** CmpPSel = INx+ */
+    MXC_E_AFE_POS_IN_SEL_COMP_INPLUS = 0,
+    /** CmpPSel = SCM */
+    MXC_E_AFE_POS_IN_SEL_COMP_SCM,
+    /** CmpPSel = dac1 */
+    MXC_E_AFE_POS_IN_SEL_COMP_DAC1,
+    /** CmpPSel = DAC3P */
+    MXC_E_AFE_POS_IN_SEL_COMP_DAC3P,
+    /** CmpPSel = LED Observe Port */
+    MXC_E_AFE_POS_IN_SEL_COMP_LED_OBS_PORT,
+    /** CmpPSel = dac1 also output on INx+ */
+    MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_INPLUS,
+    /** CmpPSel = DAC3P also output on INx+ */
+    MXC_E_AFE_POS_IN_SEL_COMP_DAC3P_AND_INPLUS,
+    /** CmpPSel = dac1 also output on SCM */
+    MXC_E_AFE_POS_IN_SEL_COMP_DAC1_AND_SCM
+} mxc_afe_pos_in_sel_comp_t;
+
+/**
+ * @brief MUX Selection for CmpNSel.
+ */
+typedef enum {
+    /** CmpNSel = INx- */
+    MXC_E_AFE_NEG_IN_SEL_COMP_INMINUS = 0,
+    /** CmpNSel = SNO */
+    MXC_E_AFE_NEG_IN_SEL_COMP_SNO,
+    /** CmpNSel = dac0 */
+    MXC_E_AFE_NEG_IN_SEL_COMP_DAC0,
+    /** CmpNSel = DAC2P */
+    MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P,
+    /** CmpNSel = LED Observation Port */
+    MXC_E_AFE_NEG_IN_SEL_COMP_LED_OBS_PORT,
+    /** CmpNSel = dac0 also output on INx- */
+    MXC_E_AFE_NEG_IN_SEL_COMP_DAC0_AND_INMINUS,
+    /** CmpNSel = DAC2 also output on INx- */
+    MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_INMINUS,
+    /** CmpNSel = DAC2 also output on SNO */
+    MXC_E_AFE_NEG_IN_SEL_COMP_DAC2P_AND_SNO
+} mxc_afe_neg_in_sel_comp_t;
+
+/*                                      Offset   Register Description
+                                        ======   ==================================================== */
+typedef struct {
+    __IO uint32_t intr;             /*  0x0000   Analog Front End Interrupt Flags and Enable/Disable  */
+    __IO uint32_t ctrl0;            /*  0x0004   Analog Front End Control 0                           */
+    __IO uint32_t ctrl1;            /*  0x0008   Analog Front End Control 1                           */
+    __IO uint32_t ctrl2;            /*  0x000C   Analog Front End Control 2                           */
+    __IO uint32_t ctrl3;            /*  0x0010   Analog Front End Control 3                           */
+    __IO uint32_t ctrl4;            /*  0x0014   Analog Front End Control 4                           */
+    __IO uint32_t ctrl5;            /*  0x0018   Analog Front End Control 5                           */
+} mxc_afe_regs_t;
+
+/*
+   Register offsets for module AFE.
+*/
+#define MXC_R_AFE_OFFS_INTR                   ((uint32_t)0x00000000UL)
+#define MXC_R_AFE_OFFS_CTRL0                  ((uint32_t)0x00000004UL)
+#define MXC_R_AFE_OFFS_CTRL1                  ((uint32_t)0x00000008UL)
+#define MXC_R_AFE_OFFS_CTRL2                  ((uint32_t)0x0000000CUL)
+#define MXC_R_AFE_OFFS_CTRL3                  ((uint32_t)0x00000010UL)
+#define MXC_R_AFE_OFFS_CTRL4                  ((uint32_t)0x00000014UL)
+#define MXC_R_AFE_OFFS_CTRL5                  ((uint32_t)0x00000018UL)
+
+/*
+   Field positions and masks for module AFE.
+*/
+#define MXC_F_AFE_INTR_OP_COMP0_IF_POS                      0
+#define MXC_F_AFE_INTR_OP_COMP0_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_IF_POS                      1
+#define MXC_F_AFE_INTR_OP_COMP1_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_IF_POS                      2
+#define MXC_F_AFE_INTR_OP_COMP2_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_IF_POS                      3
+#define MXC_F_AFE_INTR_OP_COMP3_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_IF_POS                      4
+#define MXC_F_AFE_INTR_LP_COMP0_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_IF_POS                      5
+#define MXC_F_AFE_INTR_LP_COMP1_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_IF_POS                      6
+#define MXC_F_AFE_INTR_LP_COMP2_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IF_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_IF_POS                      7
+#define MXC_F_AFE_INTR_LP_COMP3_IF                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IF_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS                 8
+#define MXC_F_AFE_INTR_OP_COMP0_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS                 9
+#define MXC_F_AFE_INTR_OP_COMP1_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS                 10
+#define MXC_F_AFE_INTR_OP_COMP2_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS                 11
+#define MXC_F_AFE_INTR_OP_COMP3_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS                 12
+#define MXC_F_AFE_INTR_LP_COMP0_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS                 13
+#define MXC_F_AFE_INTR_LP_COMP1_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS                 14
+#define MXC_F_AFE_INTR_LP_COMP2_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS                 15
+#define MXC_F_AFE_INTR_LP_COMP3_NMI_PMU                     ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_NMI_PMU_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_POL_POS                     16
+#define MXC_F_AFE_INTR_OP_COMP0_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_POL_POS                     17
+#define MXC_F_AFE_INTR_OP_COMP1_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_POL_POS                     18
+#define MXC_F_AFE_INTR_OP_COMP2_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_POL_POS                     19
+#define MXC_F_AFE_INTR_OP_COMP3_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_POL_POS                     20
+#define MXC_F_AFE_INTR_LP_COMP0_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_POL_POS                     21
+#define MXC_F_AFE_INTR_LP_COMP1_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_POL_POS                     22
+#define MXC_F_AFE_INTR_LP_COMP2_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_POL_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_POL_POS                     23
+#define MXC_F_AFE_INTR_LP_COMP3_POL                         ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_POL_POS))
+#define MXC_F_AFE_INTR_OP_COMP0_IE_POS                      24
+#define MXC_F_AFE_INTR_OP_COMP0_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP0_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP1_IE_POS                      25
+#define MXC_F_AFE_INTR_OP_COMP1_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP1_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP2_IE_POS                      26
+#define MXC_F_AFE_INTR_OP_COMP2_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP2_IE_POS))
+#define MXC_F_AFE_INTR_OP_COMP3_IE_POS                      27
+#define MXC_F_AFE_INTR_OP_COMP3_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_OP_COMP3_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP0_IE_POS                      28
+#define MXC_F_AFE_INTR_LP_COMP0_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP0_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP1_IE_POS                      29
+#define MXC_F_AFE_INTR_LP_COMP1_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP1_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP2_IE_POS                      30
+#define MXC_F_AFE_INTR_LP_COMP2_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP2_IE_POS))
+#define MXC_F_AFE_INTR_LP_COMP3_IE_POS                      31
+#define MXC_F_AFE_INTR_LP_COMP3_IE                          ((uint32_t)(0x00000001UL << MXC_F_AFE_INTR_LP_COMP3_IE_POS))
+
+#define MXC_F_AFE_CTRL0_LED_CFG_POS                         0
+#define MXC_F_AFE_CTRL0_LED_CFG                             ((uint32_t)(0x0000000FUL << MXC_F_AFE_CTRL0_LED_CFG_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS                 4
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP0_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS                 5
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP1_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS                 6
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP2_POS))
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS                 7
+#define MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL0_CLEAR_WUD_COMP3_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS                    8
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP0                        ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP0_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS                    10
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP1                        ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP1_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS                    12
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP2                        ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP2_POS))
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS                    14
+#define MXC_F_AFE_CTRL0_EN_WUD_COMP3                        ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_EN_WUD_COMP3_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS                   16
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP0                       ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP0_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS                   18
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP1                       ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP1_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS                   20
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP2                       ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP2_POS))
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS                   22
+#define MXC_F_AFE_CTRL0_IN_MODE_COMP3                       ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_IN_MODE_COMP3_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS                 24
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP0                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP0_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS                 26
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP1                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP1_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS                 28
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP2                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP2_POS))
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS                 30
+#define MXC_F_AFE_CTRL0_BIAS_MODE_COMP3                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL0_BIAS_MODE_COMP3_POS))
+
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS           0
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN               ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_EN_POS))
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS          1
+#define MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL              ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_TEMP_SENSE_CURRENT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS           3
+#define MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN               ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_FAST_PWRDN_EN_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS           4
+#define MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN               ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_FAST_PWRDN_EN_POS))
+#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS                 5
+#define MXC_F_AFE_CTRL1_REF_BANDGAP_SEL                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BANDGAP_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS                6
+#define MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL                    ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS                8
+#define MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL                    ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_SEL_POS                         10
+#define MXC_F_AFE_CTRL1_REF_SEL                             ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_SEL_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS                 11
+#define MXC_F_AFE_CTRL1_REF_ADC_POWERUP                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS                 12
+#define MXC_F_AFE_CTRL1_REF_DAC_POWERUP                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS                 13
+#define MXC_F_AFE_CTRL1_REF_BLK_POWERUP                     ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_BLK_POWERUP_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_COMP_POS                    14
+#define MXC_F_AFE_CTRL1_REF_ADC_COMP                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_ADC_COMP_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_COMP_POS                    15
+#define MXC_F_AFE_CTRL1_REF_DAC_COMP                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_REF_DAC_COMP_POS))
+#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS               16
+#define MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN                   ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_ADC_TEST_GAIN_POS))
+#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS               18
+#define MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN                   ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL1_REF_DAC_TEST_GAIN_POS))
+#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS                   20
+#define MXC_F_AFE_CTRL1_ABUS_PAGE_2_0                       ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL1_ABUS_PAGE_2_0_POS))
+#define MXC_F_AFE_CTRL1_PLL_TST_EN_POS                      23
+#define MXC_F_AFE_CTRL1_PLL_TST_EN                          ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_PLL_TST_EN_POS))
+#define MXC_F_AFE_CTRL1_V1EXTADJ_POS                        25
+#define MXC_F_AFE_CTRL1_V1EXTADJ                            ((uint32_t)(0x0000001FUL << MXC_F_AFE_CTRL1_V1EXTADJ_POS))
+#define MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS                    30
+#define MXC_F_AFE_CTRL1_TMON_CUR_SEL                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL1_TMON_CUR_SEL_POS))
+
+#define MXC_F_AFE_CTRL2_HYST_COMP0_POS                      0
+#define MXC_F_AFE_CTRL2_HYST_COMP0                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP0_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP1_POS                      2
+#define MXC_F_AFE_CTRL2_HYST_COMP1                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP1_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP2_POS                      4
+#define MXC_F_AFE_CTRL2_HYST_COMP2                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP2_POS))
+#define MXC_F_AFE_CTRL2_HYST_COMP3_POS                      6
+#define MXC_F_AFE_CTRL2_HYST_COMP3                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL2_HYST_COMP3_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP0_POS                    8
+#define MXC_F_AFE_CTRL2_HY_POL_COMP0                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP0_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP1_POS                    9
+#define MXC_F_AFE_CTRL2_HY_POL_COMP1                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP1_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP2_POS                    10
+#define MXC_F_AFE_CTRL2_HY_POL_COMP2                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP2_POS))
+#define MXC_F_AFE_CTRL2_HY_POL_COMP3_POS                    11
+#define MXC_F_AFE_CTRL2_HY_POL_COMP3                        ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_HY_POL_COMP3_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP0_POS                   12
+#define MXC_F_AFE_CTRL2_POWERUP_COMP0                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP0_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP1_POS                   13
+#define MXC_F_AFE_CTRL2_POWERUP_COMP1                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP1_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP2_POS                   14
+#define MXC_F_AFE_CTRL2_POWERUP_COMP2                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP2_POS))
+#define MXC_F_AFE_CTRL2_POWERUP_COMP3_POS                   15
+#define MXC_F_AFE_CTRL2_POWERUP_COMP3                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_POWERUP_COMP3_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN0_POS                      16
+#define MXC_F_AFE_CTRL2_DACOUT_EN0                          ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN0_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN1_POS                      17
+#define MXC_F_AFE_CTRL2_DACOUT_EN1                          ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN1_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN2_POS                      18
+#define MXC_F_AFE_CTRL2_DACOUT_EN2                          ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN2_POS))
+#define MXC_F_AFE_CTRL2_DACOUT_EN3_POS                      19
+#define MXC_F_AFE_CTRL2_DACOUT_EN3                          ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DACOUT_EN3_POS))
+#define MXC_F_AFE_CTRL2_SCM_OR_SEL_POS                      20
+#define MXC_F_AFE_CTRL2_SCM_OR_SEL                          ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SCM_OR_SEL_POS))
+#define MXC_F_AFE_CTRL2_SNO_OR_SEL_POS                      23
+#define MXC_F_AFE_CTRL2_SNO_OR_SEL                          ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL2_SNO_OR_SEL_POS))
+#define MXC_F_AFE_CTRL2_DAC0_SEL_POS                        26
+#define MXC_F_AFE_CTRL2_DAC0_SEL                            ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC0_SEL_POS))
+#define MXC_F_AFE_CTRL2_DAC1_SEL_POS                        27
+#define MXC_F_AFE_CTRL2_DAC1_SEL                            ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL2_DAC1_SEL_POS))
+
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS                  12
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP0                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS                  13
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP1                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS                  14
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP2                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS                  15
+#define MXC_F_AFE_CTRL3_POWERUP_OPAMP3                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_POWERUP_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS                  16
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP0                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS                  17
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP1                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS                  18
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP2                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS                  19
+#define MXC_F_AFE_CTRL3_GND_SEL_OPAMP3                      ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_GND_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST0_POS                     20
+#define MXC_F_AFE_CTRL3_CLOSE_SPST0                         ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST0_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST1_POS                     21
+#define MXC_F_AFE_CTRL3_CLOSE_SPST1                         ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST1_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST2_POS                     22
+#define MXC_F_AFE_CTRL3_CLOSE_SPST2                         ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST2_POS))
+#define MXC_F_AFE_CTRL3_CLOSE_SPST3_POS                     23
+#define MXC_F_AFE_CTRL3_CLOSE_SPST3                         ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_CLOSE_SPST3_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS                   24
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP0                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS                   25
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP1                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS                   26
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP2                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS                   27
+#define MXC_F_AFE_CTRL3_EN_PCH_OPAMP3                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_PCH_OPAMP3_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS                   28
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP0                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP0_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS                   29
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP1                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP1_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS                   30
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP2                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP2_POS))
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS                   31
+#define MXC_F_AFE_CTRL3_EN_NCH_OPAMP3                       ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL3_EN_NCH_OPAMP3_POS))
+
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS                 0
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS                 2
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS                 4
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS                 6
+#define MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS                 8
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS                 10
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS                 12
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS))
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS                 14
+#define MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3                     ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_A_POS                       16
+#define MXC_F_AFE_CTRL4_DAC_SEL_A                           ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_A_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_B_POS                       18
+#define MXC_F_AFE_CTRL4_DAC_SEL_B                           ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_B_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_C_POS                       20
+#define MXC_F_AFE_CTRL4_DAC_SEL_C                           ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_C_POS))
+#define MXC_F_AFE_CTRL4_DAC_SEL_D_POS                       22
+#define MXC_F_AFE_CTRL4_DAC_SEL_D                           ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_DAC_SEL_D_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_A_POS                      24
+#define MXC_F_AFE_CTRL4_NPAD_SEL_A                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_A_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_B_POS                      26
+#define MXC_F_AFE_CTRL4_NPAD_SEL_B                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_B_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_C_POS                      28
+#define MXC_F_AFE_CTRL4_NPAD_SEL_C                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_C_POS))
+#define MXC_F_AFE_CTRL4_NPAD_SEL_D_POS                      30
+#define MXC_F_AFE_CTRL4_NPAD_SEL_D                          ((uint32_t)(0x00000003UL << MXC_F_AFE_CTRL4_NPAD_SEL_D_POS))
+
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS               0
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP0_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS               3
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP1_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS               6
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP2_POS))
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS               9
+#define MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_P_IN_SEL_LP_COMP3_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS               12
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP0_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS               15
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP1_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS               18
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP2_POS))
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS               21
+#define MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3                   ((uint32_t)(0x00000007UL << MXC_F_AFE_CTRL5_N_IN_SEL_LP_COMP3_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP0_POS                         24
+#define MXC_F_AFE_CTRL5_OP_CMP0                             ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP0_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP1_POS                         25
+#define MXC_F_AFE_CTRL5_OP_CMP1                             ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP1_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP2_POS                         26
+#define MXC_F_AFE_CTRL5_OP_CMP2                             ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP2_POS))
+#define MXC_F_AFE_CTRL5_OP_CMP3_POS                         27
+#define MXC_F_AFE_CTRL5_OP_CMP3                             ((uint32_t)(0x00000001UL << MXC_F_AFE_CTRL5_OP_CMP3_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_AFE_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/clkman_regs.h

@@ -0,0 +1,493 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_CLKMAN_REGS_H_
+#define _MXC_CLKMAN_REGS_H_ 
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  clkman_regs.h
+ * @addtogroup clkman CLKMAN
+ * @{
+ */
+
+/**
+ * @brief Defines clock input selections for the phase locked loop.
+ */
+typedef enum {
+    /** Input select for high frequency crystal oscillator */
+    MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0,
+    /** Input select for 24MHz ring oscillator */
+    MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO,
+} mxc_clkman_pll_input_select_t;
+
+/**
+ * @brief Defines clock input frequency for the phase locked loop.
+ */
+typedef enum {
+    /** Input frequency of 24MHz */
+    MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0,
+    /** Input frequency of 12MHz */
+    MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ,
+    /** Input frequency of 8MHz */
+    MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ,
+} mxc_clkman_pll_divisor_select_t;
+
+/**
+ * @brief Defines terminal count for PLL stable.
+ */
+typedef enum {
+    /** Clock stable after 2^8 = 256 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0,
+    /** Clock stable after 2^9 = 512 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS,
+    /** Clock stable after 2^10 = 1024 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS,
+    /** Clock stable after 2^11 = 2048 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS,
+    /** Clock stable after 2^12 = 4096 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS,
+    /** Clock stable after 2^13 = 8192 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS,
+    /** Clock stable after 2^14 = 16384 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS,
+    /** Clock stable after 2^15 = 32768 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS,
+    /** Clock stable after 2^16 = 65536 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS,
+    /** Clock stable after 2^17 = 131072 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS,
+    /** Clock stable after 2^18 = 262144 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS,
+    /** Clock stable after 2^19 = 524288 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS,
+    /** Clock stable after 2^20 = 1048576 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS,
+    /** Clock stable after 2^21 = 2097152 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS,
+    /** Clock stable after 2^22 = 4194304 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS,
+    /** Clock stable after 2^23 = 8388608 clock cycles */
+    MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS
+} mxc_clkman_stability_count_t;
+
+/**
+ * @brief Defines clock source selections for system clock.
+ */
+typedef enum {
+    /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */
+    MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0,
+    /** Clock select for 24MHz ring oscillator */
+    MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO,
+    /** Clock select for high frequency crystal oscillator */
+    MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX,
+    /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */
+    MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2
+} mxc_clkman_system_source_select_t;
+
+/**
+ * @brief Defines clock source selections for analog to digital converter clock.
+ */
+typedef enum {
+    /** Clock select for system clock frequency */
+    MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0,
+    /** Clock select for 8MHz phase locked loop output */
+    MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ,
+    /** Clock select for high frequency crystal oscillator */
+    MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX,
+    /** Clock select for 24MHz ring oscillator */
+    MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO,
+} mxc_clkman_adc_source_select_t;
+
+/**
+ * @brief Defines clock source selections for watchdog timer clock.
+ */
+typedef enum {
+    /** Clock select for system clock frequency */
+    MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0,
+    /** Clock select for 8MHz phase locked loop output */
+    MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC,
+    /** Clock select for high frequency crystal oscillator */
+    MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO,
+    /** Clock select for 24MHz ring oscillator */
+    MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO,
+} mxc_clkman_wdt_source_select_t;
+
+/**
+ * @brief Defines clock scales for various clocks.
+ */
+typedef enum {
+    /** Clock disabled */
+    MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0,
+    /** Clock enabled */
+    MXC_E_CLKMAN_CLK_SCALE_ENABLED,
+    /** Clock scale for dividing by 2 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_2,
+    /** Clock scale for dividing by 4 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_4,
+    /** Clock scale for dividing by 8 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_8,
+    /** Clock scale for dividing by 16 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_16,
+    /** Clock scale for dividing by 32 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_32,
+    /** Clock scale for dividing by 64 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_64,
+    /** Clock scale for dividing by 128 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_128,
+    /** Clock scale for dividing by 256 */
+    MXC_E_CLKMAN_CLK_SCALE_DIV_256
+} mxc_clkman_clk_scale_t;
+
+/**
+ * @brief Defines Setting of the Clock Gates .
+ */
+typedef enum {
+    /** Clock Gater is Off */
+    MXC_E_CLKMAN_CLK_GATE_OFF  = 0,
+    /** Clock Gater is Dynamic */
+    MXC_E_CLKMAN_CLK_GATE_DYNAMIC,
+    /** Clock Gater is On */
+    MXC_E_CLKMAN_CLK_GATE_ON
+} mxc_clkman_clk_gate_t;
+
+/*                                               Offset   Register Description
+                                                 ======   ===================================================================== */
+typedef struct {
+    __IO uint32_t clk_config;                /*  0x0000   System Clock Configuration                                  */
+    __IO uint32_t clk_ctrl;                  /*  0x0004   System Clock Controls                                                 */
+    __IO uint32_t intfl;                     /*  0x0008   Interrupt Flags                                             */
+    __IO uint32_t inten;                     /*  0x000C   Interrupt Enable/Disable Controls                           */
+    __IO uint32_t trim_calc;                 /*  0x0010   Trim Calculation Controls                                   */
+    __I uint32_t rsv0014[4];                 /*  0x0014                                                               */
+    __IO uint32_t i2c_timer_ctrl;            /*  0x0024   I2C Timer Control                                           */
+    __I uint32_t rsv0028[6];                 /*  0x0028                                                               */
+    __IO uint32_t clk_ctrl_0_system;         /*  0x0040   Control Settings for CLK0 - System Clock                    */
+    __IO uint32_t clk_ctrl_1_gpio;           /*  0x0044   Control Settings for CLK1 - GPIO Module Clock               */
+    __IO uint32_t clk_ctrl_2_pt;             /*  0x0048   Control Settings for CLK2 - Pulse Train Module Clock        */
+    __IO uint32_t clk_ctrl_3_spi0;           /*  0x004C   Control Settings for CLK3 - SPI0 Master Clock               */
+    __IO uint32_t clk_ctrl_4_spi1;           /*  0x0050   Control Settings for CLK4 - SPI1 Master Clock               */
+    __IO uint32_t clk_ctrl_5_spi2;           /*  0x0054   Control Settings for CLK5 - SPI2 Master Clock               */
+    __IO uint32_t clk_ctrl_6_i2cm;           /*  0x0058   Control Settings for CLK6 - Clock for all I2C Masters       */
+    __IO uint32_t clk_ctrl_7_i2cs;           /*  0x005C   Control Settings for CLK7 - I2C Slave Clock                 */
+    __IO uint32_t clk_ctrl_8_lcd_chpump;     /*  0x0060   Control Settings for CLK8 - LCD Charge Pump Clock           */
+    __IO uint32_t clk_ctrl_9_puf;            /*  0x0064   Control Settings for CLK9 - PUF Clock                       */
+    __IO uint32_t clk_ctrl_10_prng;          /*  0x0068   Control Settings for CLK10 - PRNG Clock                     */
+    __IO uint32_t clk_ctrl_11_wdt0;          /*  0x006C   Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk  */
+    __IO uint32_t clk_ctrl_12_wdt1;          /*  0x0070   Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk  */
+    __IO uint32_t clk_ctrl_13_rtc_int_sync;  /*  0x0074   Control Settings for CLK13 - RTC Interrupt Sync Clock       */
+    __IO uint32_t clk_ctrl_14_dac0;          /*  0x0078   Control Settings for CLK14 - 12-bit DAC 0 Clock             */
+    __IO uint32_t clk_ctrl_15_dac1;          /*  0x007C   Control Settings for CLK15 - 12-bit DAC 1 Clock             */
+    __IO uint32_t clk_ctrl_16_dac2;          /*  0x0080   Control Settings for CLK16 - 8-bit DAC 0 Clock              */
+    __IO uint32_t clk_ctrl_17_dac3;          /*  0x0084   Control Settings for CLK17 - 8-bit DAC 1 Clock              */
+    __I uint32_t rsv0088[30];                /*  0x0088                                                               */
+    __IO uint32_t crypt_clk_ctrl_0_aes;      /*  0x0100   Control Settings for Crypto Clock 0 - AES                   */
+    __IO uint32_t crypt_clk_ctrl_1_maa;      /*  0x0104   Control Settings for Crypto Clock 1 - MAA                   */
+    __IO uint32_t crypt_clk_ctrl_2_prng;     /*  0x0108   Control Settings for Crypto Clock 2 - PRNG                  */
+    __I uint32_t rsv010C[13];                /*  0x010C                                                               */
+    __IO uint32_t clk_gate_ctrl0;            /*  0x0140   Dynamic Clock Gating Control Register 0                     */
+    __IO uint32_t clk_gate_ctrl1;            /*  0x0144   Dynamic Clock Gating Control Register 1                     */
+    __IO uint32_t clk_gate_ctrl2;            /*  0x0148   Dynamic Clock Gating Control Register 2                     */
+} mxc_clkman_regs_t;
+
+/*
+   Register offsets for module CLKMAN.
+*/
+#define MXC_R_CLKMAN_OFFS_CLK_CONFIG                ((uint32_t)0x00000000UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL                  ((uint32_t)0x00000004UL)
+#define MXC_R_CLKMAN_OFFS_INTFL                     ((uint32_t)0x00000008UL)
+#define MXC_R_CLKMAN_OFFS_INTEN                     ((uint32_t)0x0000000CUL)
+#define MXC_R_CLKMAN_OFFS_TRIM_CALC                 ((uint32_t)0x00000010UL)
+#define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL            ((uint32_t)0x00000024UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM         ((uint32_t)0x00000040UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO           ((uint32_t)0x00000044UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT             ((uint32_t)0x00000048UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0           ((uint32_t)0x0000004CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1           ((uint32_t)0x00000050UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2           ((uint32_t)0x00000054UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM           ((uint32_t)0x00000058UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS           ((uint32_t)0x0000005CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP     ((uint32_t)0x00000060UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF            ((uint32_t)0x00000064UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG          ((uint32_t)0x00000068UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0          ((uint32_t)0x0000006CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1          ((uint32_t)0x00000070UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC  ((uint32_t)0x00000074UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0          ((uint32_t)0x00000078UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1          ((uint32_t)0x0000007CUL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2          ((uint32_t)0x00000080UL)
+#define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3          ((uint32_t)0x00000084UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES      ((uint32_t)0x00000100UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA      ((uint32_t)0x00000104UL)
+#define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG     ((uint32_t)0x00000108UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0            ((uint32_t)0x00000140UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1            ((uint32_t)0x00000144UL)
+#define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2            ((uint32_t)0x00000148UL)
+
+/*
+   Field positions and masks for module CLKMAN.
+*/
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS                  0
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS                  1
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS             2
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE                 ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS               4
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST                   ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS              9
+#define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL                  ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS                  12
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS                 13
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N                     ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS            14
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT                ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS          16
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS             18
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE                 ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS                  19
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS         20
+#define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS               24
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE                   ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS              25
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS))
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS      28
+#define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT          ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS          1
+#define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS              3
+#define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS                    4
+#define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS                    8
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS             9
+#define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT                 ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS                 12
+#define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N                     ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS              16
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS       17
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS              20
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS       21
+#define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS))
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS                     24
+#define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE                         ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
+
+#define MXC_F_CLKMAN_INTFL_RING_STABLE_POS                      0
+#define MXC_F_CLKMAN_INTFL_RING_STABLE                          ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS))
+#define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS                       1
+#define MXC_F_CLKMAN_INTFL_PLL_STABLE                           ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS))
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS                    2
+#define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
+
+#define MXC_F_CLKMAN_INTEN_RING_STABLE_POS                      0
+#define MXC_F_CLKMAN_INTEN_RING_STABLE                          ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS))
+#define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS                       1
+#define MXC_F_CLKMAN_INTEN_PLL_STABLE                           ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS))
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS                    2
+#define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE                        ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
+
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS                 0
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL                     ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS              1
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START                  ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS          2
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED              ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS                  3
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE                      ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS            16
+#define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS                ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
+
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS        0
+#define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN            ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS    0
+#define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE        ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS         0
+#define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE             ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS    0
+#define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE        ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS           0
+#define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE               ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS   0
+#define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE       ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS   0
+#define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE       ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0
+#define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE     ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS        0
+#define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE            ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS     0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE         ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS    0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE        ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS   0
+#define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE       ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS           0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS        2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS        4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS         6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS          8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS    10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER        ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS        12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS         14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS         16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS        18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS        20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS        22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS        24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS     26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER         ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS     28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER         ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS           30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS       0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS           2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS       4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS       6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER           ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS        8
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS        10
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS           12
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS           14
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS          16
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS    18
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER        ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS          20
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS          22
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS          24
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS         26
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS         28
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER             ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS          30
+#define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER              ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS))
+
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS           0
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS           2
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS        4
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER            ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS))
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS           6
+#define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER               ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_CLKMAN_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis.h

@@ -0,0 +1,40 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "max32600.h"
+#include "cmsis_nvic.h"
+
+#endif

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.c

@@ -0,0 +1,65 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#include "cmsis_nvic.h"
+
+#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_ARM_STD)
+__attribute__((aligned(256)))
+#endif
+#if defined(TOOLCHAIN_IAR)
+#pragma data_alignment=256
+#endif
+static void (*ramVectorTable[MXC_IRQ_COUNT])(void);
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR != (uint32_t)ramVectorTable) {
+        uint32_t *old_vectors = (uint32_t*)SCB->VTOR;
+        vectors = (uint32_t*)ramVectorTable;
+        for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)ramVectorTable;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/cmsis_nvic.h

@@ -0,0 +1,53 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS      MXC_IRQ_COUNT
+#define NVIC_USER_IRQ_OFFSET  16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MBED_CMSIS_NVIC_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/crc_regs.h

@@ -0,0 +1,89 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_CRC_REGS_H_
+#define _MXC_CRC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  crc_regs.h
+ * @addtogroup crc CRC
+ * @{
+ */
+
+/*                                             Offset   Register Description
+                                               ======   ======================================================= */
+typedef struct {
+    __IO uint32_t reseed;                  /*  0x0000   CRC-16/CRC-32 Reseed Controls                           */
+    __IO uint32_t seed16;                  /*  0x0004   Reseed Value for CRC-16 Calculations                    */
+    __IO uint32_t seed32;                  /*  0x0008   Reseed Value for CRC-32 Calculations                    */
+} mxc_crc_regs_t;
+
+/*                                             Offset   Register Description
+                                               ======   ======================================================= */
+typedef struct {
+    __IO uint32_t value16[512];            /*  0x0000   Write Next CRC-16 Data Value / Read CRC-16 Result Value */
+    __IO uint32_t value32[512];            /*  0x0800   Write Next CRC-32 Data Value / Read CRC-32 Result Value */
+} mxc_crc_data_regs_t;
+
+/*
+   Register offsets for module CRC.
+*/
+#define MXC_R_CRC_OFFS_RESEED           ((uint32_t)0x00000000UL)
+#define MXC_R_CRC_OFFS_SEED16           ((uint32_t)0x00000004UL)
+#define MXC_R_CRC_OFFS_SEED32           ((uint32_t)0x00000008UL)
+#define MXC_R_CRC_DATA_OFFS_VALUE16     ((uint32_t)0x00000000UL)
+#define MXC_R_CRC_DATA_OFFS_VALUE32     ((uint32_t)0x00000800UL)
+
+/*
+   Field positions and masks for module CRC.
+*/
+#define MXC_F_CRC_RESEED_CRC16_POS      0
+#define MXC_F_CRC_RESEED_CRC16          ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC16_POS))
+#define MXC_F_CRC_RESEED_CRC32_POS      1
+#define MXC_F_CRC_RESEED_CRC32          ((uint32_t)(0x00000001UL << MXC_F_CRC_RESEED_CRC32_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_CRC_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/dac_regs.h

@@ -0,0 +1,180 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_DAC_REGS_H
+#define _MXC_DAC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  dac_regs.h
+ * @addtogroup dac DAC
+ * @{
+ */
+
+/**
+ * @brief Defines the DAC Operational Modes.
+ */
+typedef enum {
+    /** DAC OpMode FIFO */
+    MXC_E_DAC_OP_MODE_FIFO = 0,
+    /** DAC OpMode Sample Count */
+    MXC_E_DAC_OP_MODE_DACSMPLCNT,
+    /** DAC OpMode DAC_REG Control */
+    MXC_E_DAC_OP_MODE_DAC_REG,
+    /** DAC OpMode Continuous */
+    MXC_E_DAC_OP_MODE_CONTINUOUS
+} mxc_dac_op_mode_t;
+
+/**
+ * @brief Defines the DAC Interpolation Options.
+ */
+typedef enum {
+    /** DAC Interpolation is Disabled */
+    MXC_E_DAC_INTERP_MODE_DISABLED = 0,
+    /** DAC Interpolation 2:1 */
+    MXC_E_DAC_INTERP_MODE_2_TO_1,
+    /** DAC Interpolation 4:1 */
+    MXC_E_DAC_INTERP_MODE_4_TO_1,
+    /** DAC Interpolation 8:1 */
+    MXC_E_DAC_INTERP_MODE_8_TO_1
+} mxc_dac_interp_mode_t;
+
+/**
+ * @brief Defines the DAC Start Modes.
+ */
+typedef enum {
+    /** Start on FIFO Not Empty */
+    MXC_E_DAC_START_MODE_FIFO_NOT_EMPTY = 0,
+    /** Start on ADC generated Start Strobe */
+    MXC_E_DAC_START_MODE_ADC_STROBE,
+    /** Start on DAC generated Start Strobe */
+    MXC_E_DAC_START_MODE_DAC_STROBE
+} mxc_dac_start_mode_t;
+
+/*                                                  Offset   Register Description
+                                                    ======   ================================================== */
+typedef struct {
+    __IO uint32_t ctrl0;                        /*  0x0000   DAC Control Register 0                             */
+    __IO uint32_t rate;                         /*  0x0004   DAC Output Rate Control                            */
+    __IO uint32_t ctrl1_int;                    /*  0x0008   DAC Control Register 1, Interrupt Flags and Enable */
+    __IO uint32_t reg;                          /*  0x000C   DAC Data Register                                  */
+    __IO uint32_t trm;                          /*  0x0010   DAC Trim Register */
+} mxc_dac_regs_t;
+
+/*                                                  Offset   Register Description
+                                                    ======   ================================================== */
+typedef struct {
+    union {
+        __IO uint8_t output_8;                  /*  0x0000   Write to push values to DAC output FIFO            */
+        __IO uint16_t output_16;                /*  0x0000   Write to push values to DAC output FIFO            */
+    };
+} mxc_dac_fifo_t;
+
+/*
+   Register offsets for module DAC12.
+*/
+#define MXC_R_DAC_OFFS_CTRL0                    ((uint32_t)0x00000000UL)
+#define MXC_R_DAC_OFFS_RATE                     ((uint32_t)0x00000004UL)
+#define MXC_R_DAC_OFFS_CTRL1_INT                ((uint32_t)0x00000008UL)
+#define MXC_R_DAC_FIFO_OFFS_OUTPUT              ((uint32_t)0x00000000UL)
+
+/*
+   Field positions and masks for module DAC.
+*/
+#define MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS         0
+#define MXC_F_DAC_CTRL0_FIFO_AE_CNT             ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS))
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS    5
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL        ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS))
+#define MXC_F_DAC_CTRL0_FIFO_EMPTY_POS          6
+#define MXC_F_DAC_CTRL0_FIFO_EMPTY              ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_EMPTY_POS))
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS   7
+#define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY       ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS))
+#define MXC_F_DAC_CTRL0_INTERP_MODE_POS         8
+#define MXC_F_DAC_CTRL0_INTERP_MODE             ((uint32_t)(0x00000007UL << MXC_F_DAC_CTRL0_INTERP_MODE_POS))
+#define MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS         12
+#define MXC_F_DAC_CTRL0_FIFO_AF_CNT             ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS))
+#define MXC_F_DAC_CTRL0_START_MODE_POS          16
+#define MXC_F_DAC_CTRL0_START_MODE              ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_START_MODE_POS))
+#define MXC_F_DAC_CTRL0_CPU_START_POS           20
+#define MXC_F_DAC_CTRL0_CPU_START               ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CPU_START_POS))
+#define MXC_F_DAC_CTRL0_OP_MODE_POS             24
+#define MXC_F_DAC_CTRL0_OP_MODE                 ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_OP_MODE_POS))
+#define MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS      26
+#define MXC_F_DAC_CTRL0_POWER_MODE_1_0          ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS))
+#define MXC_F_DAC_CTRL0_POWER_ON_POS            28
+#define MXC_F_DAC_CTRL0_POWER_ON                ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_ON_POS))
+#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS       29
+#define MXC_F_DAC_CTRL0_CLOCK_GATE_EN           ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS))
+#define MXC_F_DAC_CTRL0_POWER_MODE_2_POS        30
+#define MXC_F_DAC_CTRL0_POWER_MODE_2            ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_MODE_2_POS))
+#define MXC_F_DAC_CTRL0_RESET_POS               31
+#define MXC_F_DAC_CTRL0_RESET                   ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_RESET_POS))
+
+#define MXC_F_DAC_RATE_RATE_CNT_POS             0
+#define MXC_F_DAC_RATE_RATE_CNT                 ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_RATE_CNT_POS))
+#define MXC_F_DAC_RATE_SAMPLE_CNT_POS           16
+#define MXC_F_DAC_RATE_SAMPLE_CNT               ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_SAMPLE_CNT_POS))
+
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS     0
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF         ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS    1
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF        ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS 2
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF     ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS       3
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW           ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS))
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS     16
+#define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE         ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS    17
+#define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE        ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS 18
+#define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE     ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS))
+#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS  28
+#define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE      ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS))
+#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS  29
+#define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE      ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _DAC12_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h

@@ -0,0 +1,210 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_FLC_REGS_H
+#define _MXC_FLC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  flc_regs.h
+ * @addtogroup flc FLC
+ * @{
+ */
+/*                                          Offset   Register Description
+                                            ======   ======================================================= */
+typedef struct {
+    __IO uint32_t faddr;                /*  0x0000   Flash Operation Address                                 */
+    __IO uint32_t fckdiv;               /*  0x0004   Flash Clock Rate Divisor                                */
+    __IO uint32_t ctrl;                 /*  0x0008   Flash Control Register                                  */
+    __I uint32_t rsv000C[6];            /*  0x000C                                                           */
+    __IO uint32_t intr;                 /*  0x0024   Flash Controller Interrupt Flags and Enable/Disable 0   */
+    __I uint32_t rsv0028[2];            /*  0x0028                                                           */
+    __IO uint32_t fdata;                /*  0x0030   Flash Operation Data Register                           */
+    __I uint32_t rsv0034[7];            /*  0x0034                                                           */
+    __IO uint32_t perform;              /*  0x0050   Flash Performance Settings                              */
+    __I uint32_t rsv0054[11];           /*  0x0054                                                           */
+    __IO uint32_t status;               /*  0x0080   Security Status Flags                                   */
+    __I uint32_t rsv0084;               /*  0x0084                                                           */
+    __IO uint32_t security;             /*  0x0088   Flash Controller Security Settings                      */
+    __I uint32_t rsv008C[4];            /*  0x008C                                                           */
+    __IO uint32_t bypass;               /*  0x009C   Status Flags for DSB Operations                         */
+    __IO uint32_t user_option;          /*  0x0100   Used to set DSB Access code and Auto-Lock in info block */
+    __I uint32_t rsv0104[15];           /*  0x0104                                                           */
+    __IO uint32_t ctrl2;                /*  0x0140   Flash Control Register 2                                */
+    __IO uint32_t intfl1;               /*  0x0144   Interrupt Flags Register 1                              */
+    __IO uint32_t inten1;               /*  0x0148   Interrupt Enable/Disable Register 1                     */
+    __I uint32_t rsv014C;               /*  0x014C                                                           */
+    __IO uint32_t disable_xr0;          /*  0x0150   Disable Flash Page Exec/Read Register 0                 */
+    __IO uint32_t disable_xr1;          /*  0x0154   Disable Flash Page Exec/Read Register 1                 */
+    __IO uint32_t disable_xr2;          /*  0x0158   Disable Flash Page Exec/Read Register 2                 */
+    __IO uint32_t disable_xr3;          /*  0x015C   Disable Flash Page Exec/Read Register 3                 */
+    __IO uint32_t disable_we0;          /*  0x0160   Disable Flash Page Write/Erase Register 0               */
+    __IO uint32_t disable_we1;          /*  0x0164   Disable Flash Page Write/Erase Register 1               */
+    __IO uint32_t disable_we2;          /*  0x0168   Disable Flash Page Write/Erase Register 2               */
+    __IO uint32_t disable_we3;          /*  0x016C   Disable Flash Page Write/Erase Register 3               */
+} mxc_flc_regs_t;
+
+/*
+   Register offsets for module FLC.
+*/
+#define MXC_R_FLC_OFFS_FADDR                          ((uint32_t)0x00000000UL)
+#define MXC_R_FLC_OFFS_FCKDIV                         ((uint32_t)0x00000004UL)
+#define MXC_R_FLC_OFFS_CTRL                           ((uint32_t)0x00000008UL)
+#define MXC_R_FLC_OFFS_INTR                           ((uint32_t)0x00000024UL)
+#define MXC_R_FLC_OFFS_FDATA                          ((uint32_t)0x00000030UL)
+#define MXC_R_FLC_OFFS_PERFORM                        ((uint32_t)0x00000050UL)
+#define MXC_R_FLC_OFFS_STATUS                         ((uint32_t)0x00000080UL)
+#define MXC_R_FLC_OFFS_SECURITY                       ((uint32_t)0x00000088UL)
+#define MXC_R_FLC_OFFS_BYPASS                         ((uint32_t)0x0000009CUL)
+#define MXC_R_FLC_OFFS_USER_OPTION                    ((uint32_t)0x00000100UL)
+#define MXC_R_FLC_OFFS_CTRL2                          ((uint32_t)0x00000140UL)
+#define MXC_R_FLC_OFFS_INTFL1                         ((uint32_t)0x00000144UL)
+#define MXC_R_FLC_OFFS_INTEN1                         ((uint32_t)0x00000148UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR0                    ((uint32_t)0x00000150UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR1                    ((uint32_t)0x00000154UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR2                    ((uint32_t)0x00000158UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR3                    ((uint32_t)0x0000015CUL)
+#define MXC_R_FLC_OFFS_DISABLE_WE0                    ((uint32_t)0x00000160UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE1                    ((uint32_t)0x00000164UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE2                    ((uint32_t)0x00000168UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE3                    ((uint32_t)0x0000016CUL)
+
+#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE               ((uint8_t)0x55)
+#define MXC_V_FLC_ERASE_CODE_MASS_ERASE               ((uint8_t)0xAA)
+
+#define MXC_V_FLC_FLSH_UNLOCK_KEY                     ((uint8_t)0x2)
+
+/*
+   Field positions and masks for module FLC.
+*/
+#define MXC_F_FLC_FADDR_FADDR_POS                     0
+#define MXC_F_FLC_FADDR_FADDR                         ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
+
+#define MXC_F_FLC_FCKDIV_FCKDIV_POS                   0
+#define MXC_F_FLC_FCKDIV_FCKDIV                       ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
+
+#define MXC_F_FLC_CTRL_WRITE_POS                      0
+#define MXC_F_FLC_CTRL_WRITE                          ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
+#define MXC_F_FLC_CTRL_MASS_ERASE_POS                 1
+#define MXC_F_FLC_CTRL_MASS_ERASE                     ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
+#define MXC_F_FLC_CTRL_PAGE_ERASE_POS                 2
+#define MXC_F_FLC_CTRL_PAGE_ERASE                     ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
+#define MXC_F_FLC_CTRL_ERASE_CODE_POS                 8
+#define MXC_F_FLC_CTRL_ERASE_CODE                     ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS          16
+#define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK              ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
+#define MXC_F_FLC_CTRL_WRITE_ENABLE_POS               17
+#define MXC_F_FLC_CTRL_WRITE_ENABLE                   ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
+#define MXC_F_FLC_CTRL_PENDING_POS                    24
+#define MXC_F_FLC_CTRL_PENDING                        ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS           25
+#define MXC_F_FLC_CTRL_INFO_BLOCK_VALID               ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS            27
+#define MXC_F_FLC_CTRL_AUTO_INCRE_MODE                ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS                28
+#define MXC_F_FLC_CTRL_FLSH_UNLOCK                    ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
+
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS           0
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IF               ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS         1
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS           9
+#define MXC_F_FLC_INTR_FLASH_OP_DONE_IE               ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS))
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS         10
+#define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS))
+
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS       8
+#define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN           ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS             0
+#define MXC_F_FLC_PERFORM_DELAY_SE_EN                 ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
+
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS        0
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW            ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS))
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS        1
+#define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC            ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS))
+#define MXC_F_FLC_STATUS_AUTO_LOCK_POS                3
+#define MXC_F_FLC_STATUS_AUTO_LOCK                    ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
+
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS          0
+#define MXC_F_FLC_SECURITY_DEBUG_DISABLE              ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS        8
+#define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK            ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS          31
+#define MXC_F_FLC_SECURITY_SECURITY_LOCK              ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
+
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS    0
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE        ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS          1
+#define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE              ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
+#define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE     ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS       3
+#define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE           ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
+
+#define MXC_F_FLC_CTRL2_FLASH_LVE_POS                 0
+#define MXC_F_FLC_CTRL2_FLASH_LVE                     ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS           8
+#define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL               ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
+
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS        0
+#define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS       1
+#define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR           ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS        2
+#define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS         3
+#define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
+
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS        0
+#define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS       1
+#define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR           ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS        2
+#define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS         3
+#define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_FLC_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/gpio_regs.h

@@ -0,0 +1,477 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_GPIO_REGS_H_
+#define _MXC_GPIO_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  gpio_regs.h
+ * @addtogroup gpio GPIO
+ * @{
+ */
+
+/*                                             Offset          Register Description
+                                            =============   ========================================== */
+typedef struct {
+    __I uint32_t rsv000[16];            /*  0x0000-0x003C                                              */
+
+    __IO uint32_t free[8];              /*  0x0040-0x005C   Port P[0..7] Free for GPIO Operation Flags */
+    __I uint32_t rsv060[8];             /*  0x0060-0x007C                                              */
+
+    __IO uint32_t out_mode[8];          /*  0x0080-0x009C   Port P[0..7] GPIO Output Drive Mode        */
+    __I uint32_t rsv0A0[8];             /*  0x00A0-0x00BC                                              */
+
+    __IO uint32_t out_val[8];           /*  0x00C0-0x00DC   Port P[0..7] GPIO Output Value             */
+    __I uint32_t rsv0E0[8];             /*  0x00E0-0x00FC                                              */
+
+    __IO uint32_t func_sel[8];          /*  0x0100-0x011C   Port P[0..7] GPIO Function Select          */
+    __I uint32_t rsv120[8];             /*  0x0120-0x013C                                              */
+
+    __IO uint32_t in_mode[8];           /*  0x0140-0x015C   Port P[0..7] GPIO Input Monitoring Mode    */
+    __I uint32_t rsv160[8];             /*  0x0160-0x017C                                              */
+
+    __IO uint32_t in_val[8];            /*  0x0180-0x019C   Port P[0..7] GPIO Input Value              */
+    __I uint32_t rsv1A0[8];             /*  0x01A0-0x01BC                                              */
+
+    __IO uint32_t int_mode[8];          /*  0x01C0-0x01DC   Port P[0..7] Interrupt Detection Mode      */
+    __I uint32_t rsv1E0[8];             /*  0x01E0-0x01FC                                              */
+
+    __IO uint32_t intfl[8];             /*  0x0200-0x021C   Port P[0..7] Interrupt Flags               */
+    __I uint32_t rsv220[8];             /*  0x0220-0x023C                                              */
+
+    __IO uint32_t inten[8];             /*  0x0240-0x025C   Port P[0..7] Interrupt Enables             */
+} mxc_gpio_regs_t;
+
+/*
+   Register offsets for module GPIO.
+*/
+#define MXC_R_GPIO_OFFS_FREE_P0                   ((uint32_t)0x00000040UL)
+#define MXC_R_GPIO_OFFS_FREE_P1                   ((uint32_t)0x00000044UL)
+#define MXC_R_GPIO_OFFS_FREE_P2                   ((uint32_t)0x00000048UL)
+#define MXC_R_GPIO_OFFS_FREE_P3                   ((uint32_t)0x0000004CUL)
+#define MXC_R_GPIO_OFFS_FREE_P4                   ((uint32_t)0x00000050UL)
+#define MXC_R_GPIO_OFFS_FREE_P5                   ((uint32_t)0x00000054UL)
+#define MXC_R_GPIO_OFFS_FREE_P6                   ((uint32_t)0x00000058UL)
+#define MXC_R_GPIO_OFFS_FREE_P7                   ((uint32_t)0x0000005CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P0               ((uint32_t)0x00000080UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P1               ((uint32_t)0x00000084UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P2               ((uint32_t)0x00000088UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P3               ((uint32_t)0x0000008CUL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P4               ((uint32_t)0x00000090UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P5               ((uint32_t)0x00000094UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P6               ((uint32_t)0x00000098UL)
+#define MXC_R_GPIO_OFFS_OUT_MODE_P7               ((uint32_t)0x0000009CUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P0                ((uint32_t)0x000000C0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P1                ((uint32_t)0x000000C4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P2                ((uint32_t)0x000000C8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P3                ((uint32_t)0x000000CCUL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P4                ((uint32_t)0x000000D0UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P5                ((uint32_t)0x000000D4UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P6                ((uint32_t)0x000000D8UL)
+#define MXC_R_GPIO_OFFS_OUT_VAL_P7                ((uint32_t)0x000000DCUL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P0               ((uint32_t)0x00000100UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P1               ((uint32_t)0x00000104UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P2               ((uint32_t)0x00000108UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P6               ((uint32_t)0x00000118UL)
+#define MXC_R_GPIO_OFFS_FUNC_SEL_P7               ((uint32_t)0x0000011CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P0                ((uint32_t)0x00000140UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P1                ((uint32_t)0x00000144UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P2                ((uint32_t)0x00000148UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P3                ((uint32_t)0x0000014CUL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P4                ((uint32_t)0x00000150UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P5                ((uint32_t)0x00000154UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P6                ((uint32_t)0x00000158UL)
+#define MXC_R_GPIO_OFFS_IN_MODE_P7                ((uint32_t)0x0000015CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P0                 ((uint32_t)0x00000180UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P1                 ((uint32_t)0x00000184UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P2                 ((uint32_t)0x00000188UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P3                 ((uint32_t)0x0000018CUL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P4                 ((uint32_t)0x00000190UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P5                 ((uint32_t)0x00000194UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P6                 ((uint32_t)0x00000198UL)
+#define MXC_R_GPIO_OFFS_IN_VAL_P7                 ((uint32_t)0x0000019CUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P0               ((uint32_t)0x000001C0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P1               ((uint32_t)0x000001C4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P2               ((uint32_t)0x000001C8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P3               ((uint32_t)0x000001CCUL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P4               ((uint32_t)0x000001D0UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P5               ((uint32_t)0x000001D4UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P6               ((uint32_t)0x000001D8UL)
+#define MXC_R_GPIO_OFFS_INT_MODE_P7               ((uint32_t)0x000001DCUL)
+#define MXC_R_GPIO_OFFS_INTFL_P0                  ((uint32_t)0x00000200UL)
+#define MXC_R_GPIO_OFFS_INTFL_P1                  ((uint32_t)0x00000204UL)
+#define MXC_R_GPIO_OFFS_INTFL_P2                  ((uint32_t)0x00000208UL)
+#define MXC_R_GPIO_OFFS_INTFL_P3                  ((uint32_t)0x0000020CUL)
+#define MXC_R_GPIO_OFFS_INTFL_P4                  ((uint32_t)0x00000210UL)
+#define MXC_R_GPIO_OFFS_INTFL_P5                  ((uint32_t)0x00000214UL)
+#define MXC_R_GPIO_OFFS_INTFL_P6                  ((uint32_t)0x00000218UL)
+#define MXC_R_GPIO_OFFS_INTFL_P7                  ((uint32_t)0x0000021CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P0                  ((uint32_t)0x00000240UL)
+#define MXC_R_GPIO_OFFS_INTEN_P1                  ((uint32_t)0x00000244UL)
+#define MXC_R_GPIO_OFFS_INTEN_P2                  ((uint32_t)0x00000248UL)
+#define MXC_R_GPIO_OFFS_INTEN_P3                  ((uint32_t)0x0000024CUL)
+#define MXC_R_GPIO_OFFS_INTEN_P4                  ((uint32_t)0x00000250UL)
+#define MXC_R_GPIO_OFFS_INTEN_P5                  ((uint32_t)0x00000254UL)
+#define MXC_R_GPIO_OFFS_INTEN_P6                  ((uint32_t)0x00000258UL)
+#define MXC_R_GPIO_OFFS_INTEN_P7                  ((uint32_t)0x0000025CUL)
+
+
+/*
+   Field positions and masks for module GPIO.
+*/
+#define MXC_F_GPIO_FREE_PIN0_POS                             0
+#define MXC_F_GPIO_FREE_PIN0                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS))
+#define MXC_F_GPIO_FREE_PIN1_POS                             1
+#define MXC_F_GPIO_FREE_PIN1                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS))
+#define MXC_F_GPIO_FREE_PIN2_POS                             2
+#define MXC_F_GPIO_FREE_PIN2                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS))
+#define MXC_F_GPIO_FREE_PIN3_POS                             3
+#define MXC_F_GPIO_FREE_PIN3                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS))
+#define MXC_F_GPIO_FREE_PIN4_POS                             4
+#define MXC_F_GPIO_FREE_PIN4                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS))
+#define MXC_F_GPIO_FREE_PIN5_POS                             5
+#define MXC_F_GPIO_FREE_PIN5                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS))
+#define MXC_F_GPIO_FREE_PIN6_POS                             6
+#define MXC_F_GPIO_FREE_PIN6                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS))
+#define MXC_F_GPIO_FREE_PIN7_POS                             7
+#define MXC_F_GPIO_FREE_PIN7                                ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS))
+
+#define MXC_F_GPIO_OUT_MODE_PIN0_POS                         0
+#define MXC_F_GPIO_OUT_MODE_PIN0                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN1_POS                         4
+#define MXC_F_GPIO_OUT_MODE_PIN1                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN2_POS                         8
+#define MXC_F_GPIO_OUT_MODE_PIN2                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN3_POS                        12
+#define MXC_F_GPIO_OUT_MODE_PIN3                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN4_POS                        16
+#define MXC_F_GPIO_OUT_MODE_PIN4                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN5_POS                        20
+#define MXC_F_GPIO_OUT_MODE_PIN5                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN6_POS                        24
+#define MXC_F_GPIO_OUT_MODE_PIN6                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_F_GPIO_OUT_MODE_PIN7_POS                        28
+#define MXC_F_GPIO_OUT_MODE_PIN7                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_OUT_VAL_PIN0_POS                          0
+#define MXC_F_GPIO_OUT_VAL_PIN0                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN1_POS                          1
+#define MXC_F_GPIO_OUT_VAL_PIN1                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN2_POS                          2
+#define MXC_F_GPIO_OUT_VAL_PIN2                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN3_POS                          3
+#define MXC_F_GPIO_OUT_VAL_PIN3                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN4_POS                          4
+#define MXC_F_GPIO_OUT_VAL_PIN4                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN5_POS                          5
+#define MXC_F_GPIO_OUT_VAL_PIN5                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN6_POS                          6
+#define MXC_F_GPIO_OUT_VAL_PIN6                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS))
+#define MXC_F_GPIO_OUT_VAL_PIN7_POS                          7
+#define MXC_F_GPIO_OUT_VAL_PIN7                             ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS))
+
+#define MXC_F_GPIO_FUNC_SEL_PIN0_POS                         0
+#define MXC_F_GPIO_FUNC_SEL_PIN0                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN1_POS                         4
+#define MXC_F_GPIO_FUNC_SEL_PIN1                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN2_POS                         8
+#define MXC_F_GPIO_FUNC_SEL_PIN2                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN3_POS                        12
+#define MXC_F_GPIO_FUNC_SEL_PIN3                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN4_POS                        16
+#define MXC_F_GPIO_FUNC_SEL_PIN4                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN5_POS                        20
+#define MXC_F_GPIO_FUNC_SEL_PIN5                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN6_POS                        24
+#define MXC_F_GPIO_FUNC_SEL_PIN6                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS))
+#define MXC_F_GPIO_FUNC_SEL_PIN7_POS                        28
+#define MXC_F_GPIO_FUNC_SEL_PIN7                            ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS))
+
+#define MXC_F_GPIO_IN_MODE_PIN0_POS                          0
+#define MXC_F_GPIO_IN_MODE_PIN0                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS))
+#define MXC_F_GPIO_IN_MODE_PIN1_POS                          4
+#define MXC_F_GPIO_IN_MODE_PIN1                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS))
+#define MXC_F_GPIO_IN_MODE_PIN2_POS                          8
+#define MXC_F_GPIO_IN_MODE_PIN2                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS))
+#define MXC_F_GPIO_IN_MODE_PIN3_POS                         12
+#define MXC_F_GPIO_IN_MODE_PIN3                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS))
+#define MXC_F_GPIO_IN_MODE_PIN4_POS                         16
+#define MXC_F_GPIO_IN_MODE_PIN4                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS))
+#define MXC_F_GPIO_IN_MODE_PIN5_POS                         20
+#define MXC_F_GPIO_IN_MODE_PIN5                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS))
+#define MXC_F_GPIO_IN_MODE_PIN6_POS                         24
+#define MXC_F_GPIO_IN_MODE_PIN6                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS))
+#define MXC_F_GPIO_IN_MODE_PIN7_POS                         28
+#define MXC_F_GPIO_IN_MODE_PIN7                             ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_IN_VAL_PIN0_POS                           0
+#define MXC_F_GPIO_IN_VAL_PIN0                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS))
+#define MXC_F_GPIO_IN_VAL_PIN1_POS                           1
+#define MXC_F_GPIO_IN_VAL_PIN1                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS))
+#define MXC_F_GPIO_IN_VAL_PIN2_POS                           2
+#define MXC_F_GPIO_IN_VAL_PIN2                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS))
+#define MXC_F_GPIO_IN_VAL_PIN3_POS                           3
+#define MXC_F_GPIO_IN_VAL_PIN3                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS))
+#define MXC_F_GPIO_IN_VAL_PIN4_POS                           4
+#define MXC_F_GPIO_IN_VAL_PIN4                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS))
+#define MXC_F_GPIO_IN_VAL_PIN5_POS                           5
+#define MXC_F_GPIO_IN_VAL_PIN5                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS))
+#define MXC_F_GPIO_IN_VAL_PIN6_POS                           6
+#define MXC_F_GPIO_IN_VAL_PIN6                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS))
+#define MXC_F_GPIO_IN_VAL_PIN7_POS                           7
+#define MXC_F_GPIO_IN_VAL_PIN7                              ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS))
+
+#define MXC_F_GPIO_INT_MODE_PIN0_POS                         0
+#define MXC_F_GPIO_INT_MODE_PIN0                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS))
+#define MXC_F_GPIO_INT_MODE_PIN1_POS                         4
+#define MXC_F_GPIO_INT_MODE_PIN1                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS))
+#define MXC_F_GPIO_INT_MODE_PIN2_POS                         8
+#define MXC_F_GPIO_INT_MODE_PIN2                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS))
+#define MXC_F_GPIO_INT_MODE_PIN3_POS                        12
+#define MXC_F_GPIO_INT_MODE_PIN3                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS))
+#define MXC_F_GPIO_INT_MODE_PIN4_POS                        16
+#define MXC_F_GPIO_INT_MODE_PIN4                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS))
+#define MXC_F_GPIO_INT_MODE_PIN5_POS                        20
+#define MXC_F_GPIO_INT_MODE_PIN5                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS))
+#define MXC_F_GPIO_INT_MODE_PIN6_POS                        24
+#define MXC_F_GPIO_INT_MODE_PIN6                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS))
+#define MXC_F_GPIO_INT_MODE_PIN7_POS                        28
+#define MXC_F_GPIO_INT_MODE_PIN7                            ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS))
+
+#define MXC_F_GPIO_INTFL_PIN0_POS                            0
+#define MXC_F_GPIO_INTFL_PIN0                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS))
+#define MXC_F_GPIO_INTFL_PIN1_POS                            1
+#define MXC_F_GPIO_INTFL_PIN1                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS))
+#define MXC_F_GPIO_INTFL_PIN2_POS                            2
+#define MXC_F_GPIO_INTFL_PIN2                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS))
+#define MXC_F_GPIO_INTFL_PIN3_POS                            3
+#define MXC_F_GPIO_INTFL_PIN3                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS))
+#define MXC_F_GPIO_INTFL_PIN4_POS                            4
+#define MXC_F_GPIO_INTFL_PIN4                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS))
+#define MXC_F_GPIO_INTFL_PIN5_POS                            5
+#define MXC_F_GPIO_INTFL_PIN5                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS))
+#define MXC_F_GPIO_INTFL_PIN6_POS                            6
+#define MXC_F_GPIO_INTFL_PIN6                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS))
+#define MXC_F_GPIO_INTFL_PIN7_POS                            7
+#define MXC_F_GPIO_INTFL_PIN7                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS))
+
+#define MXC_F_GPIO_INTEN_PIN0_POS                            0
+#define MXC_F_GPIO_INTEN_PIN0                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS))
+#define MXC_F_GPIO_INTEN_PIN1_POS                            1
+#define MXC_F_GPIO_INTEN_PIN1                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS))
+#define MXC_F_GPIO_INTEN_PIN2_POS                            2
+#define MXC_F_GPIO_INTEN_PIN2                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS))
+#define MXC_F_GPIO_INTEN_PIN3_POS                            3
+#define MXC_F_GPIO_INTEN_PIN3                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS))
+#define MXC_F_GPIO_INTEN_PIN4_POS                            4
+#define MXC_F_GPIO_INTEN_PIN4                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS))
+#define MXC_F_GPIO_INTEN_PIN5_POS                            5
+#define MXC_F_GPIO_INTEN_PIN5                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS))
+#define MXC_F_GPIO_INTEN_PIN6_POS                            6
+#define MXC_F_GPIO_INTEN_PIN6                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS))
+#define MXC_F_GPIO_INTEN_PIN7_POS                            7
+#define MXC_F_GPIO_INTEN_PIN7                               ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS))
+
+
+/*
+   Field values and shifted values for module GPIO.
+*/
+#define MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN0_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN0_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN0_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN0_POS))
+#define MXC_S_GPIO_FREE_PIN0_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN0_AVAILABLE      << MXC_F_GPIO_FREE_PIN0_POS))
+
+#define MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN1_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN1_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN1_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN1_POS))
+#define MXC_S_GPIO_FREE_PIN1_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN1_AVAILABLE      << MXC_F_GPIO_FREE_PIN1_POS))
+
+#define MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN2_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN2_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN2_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN2_POS))
+#define MXC_S_GPIO_FREE_PIN2_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN2_AVAILABLE      << MXC_F_GPIO_FREE_PIN2_POS))
+
+#define MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN3_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN3_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN3_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN3_POS))
+#define MXC_S_GPIO_FREE_PIN3_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN3_AVAILABLE      << MXC_F_GPIO_FREE_PIN3_POS))
+
+#define MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN4_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN4_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN4_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN4_POS))
+#define MXC_S_GPIO_FREE_PIN4_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN4_AVAILABLE      << MXC_F_GPIO_FREE_PIN4_POS))
+
+#define MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN5_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN5_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN5_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN5_POS))
+#define MXC_S_GPIO_FREE_PIN5_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN5_AVAILABLE      << MXC_F_GPIO_FREE_PIN5_POS))
+
+#define MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN6_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN6_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN6_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN6_POS))
+#define MXC_S_GPIO_FREE_PIN6_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN6_AVAILABLE      << MXC_F_GPIO_FREE_PIN6_POS))
+
+#define MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE                                      ((uint32_t)(0x0x00000000UL))
+#define MXC_V_GPIO_FREE_PIN7_AVAILABLE                                          ((uint32_t)(0x0x00000001UL))
+
+#define MXC_S_GPIO_FREE_PIN7_NOT_AVAILABLE                                      ((uint32_t)(MXC_V_GPIO_FREE_PIN7_NOT_AVAILABLE  << MXC_F_GPIO_FREE_PIN7_POS))
+#define MXC_S_GPIO_FREE_PIN7_AVAILABLE                                          ((uint32_t)(MXC_V_GPIO_FREE_PIN7_AVAILABLE      << MXC_F_GPIO_FREE_PIN7_POS))
+
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP                                  ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN                                          ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP                              ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_OUT_MODE_HIGH_Z                                              ((uint32_t)(0x00000003UL))
+#define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z                                       ((uint32_t)(0x00000004UL))
+#define MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE                                        ((uint32_t)(0x00000005UL))
+#define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z                                         ((uint32_t)(0x00000006UL))
+#define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE                                          ((uint32_t)(0x00000007UL))
+#define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z                                         ((uint32_t)(0x00000008UL))
+#define MXC_V_GPIO_OUT_MODE_FAST_DRIVE                                          ((uint32_t)(0x00000009UL))
+
+#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN0_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN0_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN1_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN1_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN2_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN2_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN3_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN3_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN4_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN4_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN5_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN5_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN6_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN6_POS))
+
+#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z_WEAK_PULLUP                             ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP      << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN              << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_OPEN_DRAIN_WEAK_PULLUP                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP  << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_HIGH_Z                                         ((uint32_t)(MXC_V_GPIO_OUT_MODE_HIGH_Z                  << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_HIGH_Z                                  ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z           << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_NORMAL_DRIVE                                   ((uint32_t)(MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE            << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_SLOW_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_SLOW_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_HIGH_Z                                    ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z             << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+#define MXC_S_GPIO_OUT_MODE_PIN7_FAST_DRIVE                                     ((uint32_t)(MXC_V_GPIO_OUT_MODE_FAST_DRIVE              << MXC_F_GPIO_OUT_MODE_PIN7_POS))
+
+#define MXC_V_GPIO_INT_MODE_DISABLED                                            ((uint32_t)(0x00000000UL))
+#define MXC_V_GPIO_INT_MODE_FALLING_EDGE                                        ((uint32_t)(0x00000001UL))
+#define MXC_V_GPIO_INT_MODE_RISING_EDGE                                         ((uint32_t)(0x00000002UL))
+#define MXC_V_GPIO_INT_MODE_BOTH_EDGES                                          ((uint32_t)(0x00000003UL))
+#define MXC_V_GPIO_INT_MODE_LOW_LEVEL                                           ((uint32_t)(0x00000004UL))
+#define MXC_V_GPIO_INT_MODE_HIGH_LEVEL                                          ((uint32_t)(0x00000005UL))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_GPIO_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/i2cm_regs.h

@@ -0,0 +1,192 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_I2CM_REGS_H_
+#define _MXC_I2CM_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  i2cm_regs.h
+ * @addtogroup i2cm I2CM
+ * @{
+ */
+
+/*                                      Offset   Register Description
+                                        ======   ================================================ */
+typedef struct {
+    __IO uint32_t fs_clk_div;       /*  0x0000   Full Speed SCL Clock Settings                    */
+    __IO uint32_t hs_clk_div;       /*  0x0004   High Speed SCL Clock Settings                    */
+    __I uint32_t rsv0008;           /*  0x0008                                                    */
+    __IO uint32_t timeout;          /*  0x000C   [TO_CNTL] Timeout and Auto-Stop Settings         */
+    __IO uint32_t ctrl;             /*  0x0010   [EN_CNTL] I2C Master Control Register            */
+    __IO uint32_t trans;            /*  0x0014   [MSTR_CNTL] I2C Master Tx Start and Status Flags */
+    __IO uint32_t intfl;            /*  0x0018   Interrupt Flags                                  */
+    __IO uint32_t inten;            /*  0x001C   Interrupt Enable/Disable Controls                */
+    __I uint32_t rsv0020[2];        /*  0x0020                                                    */
+    __IO uint32_t bb;               /*  0x0028   Bit-Bang Control Register                        */
+} mxc_i2cm_regs_t;
+
+/*                                      Offset   Register Description
+                                        ======   ================================================ */
+typedef struct {
+    __IO uint32_t trans[512];       /*  0x0000   I2C Master Transaction FIFO                      */
+    __IO uint32_t rslts[512];       /*  0x0800   I2C Master Results FIFO                          */
+} mxc_i2cm_fifo_regs_t;
+
+/*
+   Register offsets for module I2CM.
+*/
+#define MXC_R_I2CM_OFFS_FS_CLK_DIV                ((uint32_t)0x00000000UL)
+#define MXC_R_I2CM_OFFS_HS_CLK_DIV                ((uint32_t)0x00000004UL)
+#define MXC_R_I2CM_OFFS_TIMEOUT                   ((uint32_t)0x0000000CUL)
+#define MXC_R_I2CM_OFFS_CTRL                      ((uint32_t)0x00000010UL)
+#define MXC_R_I2CM_OFFS_TRANS                     ((uint32_t)0x00000014UL)
+#define MXC_R_I2CM_OFFS_INTFL                     ((uint32_t)0x00000018UL)
+#define MXC_R_I2CM_OFFS_INTEN                     ((uint32_t)0x0000001CUL)
+#define MXC_R_I2CM_OFFS_BB                        ((uint32_t)0x00000028UL)
+#define MXC_R_I2CM_OFFS_AHB_RETRY                 ((uint32_t)0x00000030UL)
+
+#define MXC_R_I2CM_FIFO_OFFS_TRANS                ((uint32_t)0x00000000UL)
+#define MXC_R_I2CM_FIFO_OFFS_RSLTS                ((uint32_t)0x00000800UL)
+
+/*
+   Field positions and masks for module I2CM.
+*/
+#define MXC_S_I2CM_TRANS_TAG_START                0x000
+#define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK           0x100
+#define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK          0x200
+#define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT         0x400
+#define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK          0x500
+#define MXC_S_I2CM_TRANS_TAG_STOP                 0x700
+#define MXC_S_I2CM_RSTLS_TAG_DATA                 0x100
+#define MXC_S_I2CM_RSTLS_TAG_EMPTY                0x200
+
+#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS               0
+#define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV                   ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS))
+#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS                   8
+#define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT                       ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS))
+#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS                   20
+#define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT                       ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS))
+
+#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS                   16
+#define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT                       ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS                 24
+#define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS))
+
+#define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS                      2
+#define MXC_F_I2CM_CTRL_TX_FIFO_EN                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS                      3
+#define MXC_F_I2CM_CTRL_RX_FIFO_EN                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS                   7
+#define MXC_F_I2CM_CTRL_MSTR_RESET_EN                       ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS))
+
+#define MXC_F_I2CM_TRANS_TX_START_POS                       0
+#define MXC_F_I2CM_TRANS_TX_START                           ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS))
+#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS                 1
+#define MXC_F_I2CM_TRANS_TX_IN_PROGRESS                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS))
+#define MXC_F_I2CM_TRANS_TX_DONE_POS                        2
+#define MXC_F_I2CM_TRANS_TX_DONE                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS))
+#define MXC_F_I2CM_TRANS_TX_NACKED_POS                      3
+#define MXC_F_I2CM_TRANS_TX_NACKED                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS))
+#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS                 4
+#define MXC_F_I2CM_TRANS_TX_LOST_ARBITR                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS                     5
+#define MXC_F_I2CM_TRANS_TX_TIMEOUT                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS))
+
+#define MXC_F_I2CM_INTFL_TX_DONE_POS                        0
+#define MXC_F_I2CM_INTFL_TX_DONE                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS))
+#define MXC_F_I2CM_INTFL_TX_NACKED_POS                      1
+#define MXC_F_I2CM_INTFL_TX_NACKED                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS))
+#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS                 2
+#define MXC_F_I2CM_INTFL_TX_LOST_ARBITR                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS                     3
+#define MXC_F_I2CM_INTFL_TX_TIMEOUT                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS                  4
+#define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS               5
+#define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY                   ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS              6
+#define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY                  ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS                7
+#define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS                8
+#define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS))
+#define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS                   9
+#define MXC_F_I2CM_INTFL_RX_FIFO_FULL                       ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS))
+
+#define MXC_F_I2CM_INTEN_TX_DONE_POS                        0
+#define MXC_F_I2CM_INTEN_TX_DONE                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS))
+#define MXC_F_I2CM_INTEN_TX_NACKED_POS                      1
+#define MXC_F_I2CM_INTEN_TX_NACKED                          ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS))
+#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS                 2
+#define MXC_F_I2CM_INTEN_TX_LOST_ARBITR                     ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS))
+#define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS                     3
+#define MXC_F_I2CM_INTEN_TX_TIMEOUT                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS))
+#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS                  4
+#define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS               5
+#define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY                   ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS                  6
+#define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS                7
+#define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS                8
+#define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL                    ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS))
+#define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS                   9
+#define MXC_F_I2CM_INTEN_RX_FIFO_FULL                       ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS))
+
+#define MXC_F_I2CM_BB_BB_SCL_OUT_POS                        0
+#define MXC_F_I2CM_BB_BB_SCL_OUT                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS))
+#define MXC_F_I2CM_BB_BB_SDA_OUT_POS                        1
+#define MXC_F_I2CM_BB_BB_SDA_OUT                            ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS))
+#define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS                     2
+#define MXC_F_I2CM_BB_BB_SCL_IN_VAL                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS))
+#define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS                     3
+#define MXC_F_I2CM_BB_BB_SDA_IN_VAL                         ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS))
+#define MXC_F_I2CM_BB_RX_FIFO_CNT_POS                       16
+#define MXC_F_I2CM_BB_RX_FIFO_CNT                           ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/icc_regs.h

@@ -0,0 +1,96 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_ICC_REGS_H_
+#define _MXC_ICC_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  icc_regs.h
+ * @addtogroup icc ICC
+ * @{
+ */
+
+/*                                              Offset   Register Description
+                                                ======   =================================================== */
+typedef struct {
+    __IO uint32_t id;                       /*  0x0000   Device ID Register                                  */
+    __IO uint32_t mem_cfg;                  /*  0x0004   Memory Configuration                                */
+    __I uint32_t rsv0008[62];               /*  0x0008                                                       */
+    __IO uint32_t ctrl_stat;                /*  0x0100   Control and Status                                  */
+    __I uint32_t rsv0104[383];              /*  0x0104                                                       */
+    __IO uint32_t invdt_all;                /*  0x0700   Invalidate (Clear) Cache Control                    */
+} mxc_icc_regs_t;
+
+/*
+   Register offsets for module ICC.
+*/
+#define MXC_R_ICC_OFFS_ID                       ((uint32_t)0x00000000UL)
+#define MXC_R_ICC_OFFS_MEM_CFG                  ((uint32_t)0x00000004UL)
+#define MXC_R_ICC_OFFS_CTRL_STAT                ((uint32_t)0x00000100UL)
+#define MXC_R_ICC_OFFS_INVDT_ALL                ((uint32_t)0x00000700UL)
+
+/*
+   Field positions and masks for module ICC.
+*/
+#define MXC_F_ICC_ID_RTL_VERSION_POS            0
+#define MXC_F_ICC_ID_RTL_VERSION                ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_RTL_VERSION_POS))
+#define MXC_F_ICC_ID_PART_NUM_POS               6
+#define MXC_F_ICC_ID_PART_NUM                   ((uint32_t)(0x0000000FUL << MXC_F_ICC_ID_PART_NUM_POS))
+#define MXC_F_ICC_ID_CACHE_ID_POS               10
+#define MXC_F_ICC_ID_CACHE_ID                   ((uint32_t)(0x0000003FUL << MXC_F_ICC_ID_CACHE_ID_POS))
+
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS        0
+#define MXC_F_ICC_MEM_CFG_CACHE_SIZE            ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_CACHE_SIZE_POS))
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS  16
+#define MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE      ((uint32_t)(0x0000FFFFUL << MXC_F_ICC_MEM_CFG_MAIN_MEMORY_SIZE_POS))
+
+#define MXC_F_ICC_CTRL_STAT_ENABLE_POS          0
+#define MXC_F_ICC_CTRL_STAT_ENABLE              ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_ENABLE_POS))
+#define MXC_F_ICC_CTRL_STAT_READY_POS           16
+#define MXC_F_ICC_CTRL_STAT_READY               ((uint32_t)(0x00000001UL << MXC_F_ICC_CTRL_STAT_READY_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_ICC_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/ioman_regs.h

@@ -0,0 +1,508 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_IOMAN_REGS_H_
+#define _MXC_IOMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  ioman_regs.h
+ * @addtogroup ioman IO MUX Manager
+ * @{
+ */
+
+typedef enum {
+    /** Pin Mapping 'A' */
+    MXC_E_IOMAN_MAPPING_A = 0,
+    /** Pin Mapping 'B' */
+    MXC_E_IOMAN_MAPPING_B,
+    /** Pin Mapping 'C' */
+    MXC_E_IOMAN_MAPPING_C,
+    /** Pin Mapping 'D' */
+    MXC_E_IOMAN_MAPPING_D,
+    /** Pin Mapping 'E' */
+    MXC_E_IOMAN_MAPPING_E,
+    /** Pin Mapping 'F' */
+    MXC_E_IOMAN_MAPPING_F,
+    /** Pin Mapping 'G' */
+    MXC_E_IOMAN_MAPPING_G,
+    /** Pin Mapping 'H' */
+    MXC_E_IOMAN_MAPPING_H,
+} ioman_mapping_t;
+
+/*                                      Offset   Register Description
+                                        ======   ========================================== */
+typedef struct {
+    __IO uint32_t wud_req0;         /*  0x0000   Wakeup Detect Mode Request Register 0      */
+    __IO uint32_t wud_req1;         /*  0x0004   Wakeup Detect Mode Request Register 1      */
+    __IO uint32_t wud_ack0;         /*  0x0008   Wakeup Detect Mode Acknowledge Register 0  */
+    __IO uint32_t wud_ack1;         /*  0x000C   Wakeup Detect Mode Acknowledge Register 1  */
+    __IO uint32_t ali_req0;         /*  0x0010   Analog Input Request Register 0            */
+    __IO uint32_t ali_req1;         /*  0x0014   Analog Input Request Register 1            */
+    __IO uint32_t ali_ack0;         /*  0x0018   Analog Input Acknowledge Register 0        */
+    __IO uint32_t ali_ack1;         /*  0x001C   Analog Input Acknowledge Register 1        */
+    __IO uint32_t spi0_req;         /*  0x0020   SPI0 I/O Mode Request                      */
+    __IO uint32_t spi0_ack;         /*  0x0024   SPI0 I/O Mode Acknowledge                  */
+    __IO uint32_t spi1_req;         /*  0x0028   SPI1 I/O Mode Request                      */
+    __IO uint32_t spi1_ack;         /*  0x002C   SPI1 I/O Mode Acknowledge                  */
+    __IO uint32_t spi2_req;         /*  0x0030   SPI2 I/O Mode Request                      */
+    __IO uint32_t spi2_ack;         /*  0x0034   SPI2 I/O Mode Acknowledge                  */
+    __IO uint32_t uart0_req;        /*  0x0038   UART0 I/O Mode Request                     */
+    __IO uint32_t uart0_ack;        /*  0x003C   UART0 I/O Mode Acknowledge                 */
+    __IO uint32_t uart1_req;        /*  0x0040   UART1 I/O Mode Request                     */
+    __IO uint32_t uart1_ack;        /*  0x0044   UART1 I/O Mode Acknowledge                 */
+    __IO uint32_t i2cm0_req;        /*  0x0048   I2C Master 0 I/O Request                   */
+    __IO uint32_t i2cm0_ack;        /*  0x004C   I2C Master 0 I/O Acknowledge               */
+    __IO uint32_t i2cs0_req;        /*  0x0050   I2C Slave 0 I/O Request                    */
+    __IO uint32_t i2s0_ack;         /*  0x0054   I2C Slave 0 I/O Acknowledge                */
+    __IO uint32_t lcd_com_req;      /*  0x0058   LCD COM Driver I/O Request                 */
+    __IO uint32_t lcd_com_ack;      /*  0x005C   LCD COM Driver I/O Acknowledge             */
+    __IO uint32_t lcd_seg_req0;     /*  0x0060   LCD SEG Driver I/O Request Register 0      */
+    __IO uint32_t lcd_seg_req1;     /*  0x0064   LCD SEG Driver I/O Request Register 1      */
+    __IO uint32_t lcd_seg_ack0;     /*  0x0068   LCD SEG Driver I/O Acknowledge Register 0  */
+    __IO uint32_t lcd_seg_ack1;     /*  0x006C   LCD SEG Driver I/O Acknowledge Register 1  */
+    __IO uint32_t crnt_req;         /*  0x0070   Current Drive I/O Request Register         */
+    __IO uint32_t io_crnt_ack;      /*  0x0074   Current Drive I/O Acknowledge Register     */
+    __IO uint32_t crnt_mode;        /*  0x0078   Current Drive I/O Mode Control             */
+    __IO uint32_t ali_connect0;     /*  0x007C   Analog I/O Connection Control Register 0   */
+    __IO uint32_t ali_connect1;     /*  0x0080   Analog I/O Connection Control Register 1   */
+    __IO uint32_t i2cm1_req;        /*  0x0084   I2C Master 1 I/O Request                   */
+    __IO uint32_t i2cm1_ack;        /*  0x0088   I2C Master 1 I/O Acknowledge               */
+    __IO uint32_t padx_control;     /*  0x008C   PADX Control                               */
+} mxc_ioman_regs_t;
+
+
+/*
+   Register offsets for module IOMAN.
+*/
+#define MXC_R_IOMAN_OFFS_WUD_REQ0                 ((uint32_t)0x00000000UL)
+#define MXC_R_IOMAN_OFFS_WUD_REQ1                 ((uint32_t)0x00000004UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK0                 ((uint32_t)0x00000008UL)
+#define MXC_R_IOMAN_OFFS_WUD_ACK1                 ((uint32_t)0x0000000CUL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ0                 ((uint32_t)0x00000010UL)
+#define MXC_R_IOMAN_OFFS_ALI_REQ1                 ((uint32_t)0x00000014UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK0                 ((uint32_t)0x00000018UL)
+#define MXC_R_IOMAN_OFFS_ALI_ACK1                 ((uint32_t)0x0000001CUL)
+#define MXC_R_IOMAN_OFFS_SPI0_REQ                 ((uint32_t)0x00000020UL)
+#define MXC_R_IOMAN_OFFS_SPI0_ACK                 ((uint32_t)0x00000024UL)
+#define MXC_R_IOMAN_OFFS_SPI1_REQ                 ((uint32_t)0x00000028UL)
+#define MXC_R_IOMAN_OFFS_SPI1_ACK                 ((uint32_t)0x0000002CUL)
+#define MXC_R_IOMAN_OFFS_SPI2_REQ                 ((uint32_t)0x00000030UL)
+#define MXC_R_IOMAN_OFFS_SPI2_ACK                 ((uint32_t)0x00000034UL)
+#define MXC_R_IOMAN_OFFS_UART0_REQ                ((uint32_t)0x00000038UL)
+#define MXC_R_IOMAN_OFFS_UART0_ACK                ((uint32_t)0x0000003CUL)
+#define MXC_R_IOMAN_OFFS_UART1_REQ                ((uint32_t)0x00000040UL)
+#define MXC_R_IOMAN_OFFS_UART1_ACK                ((uint32_t)0x00000044UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_REQ                ((uint32_t)0x00000048UL)
+#define MXC_R_IOMAN_OFFS_I2CM0_ACK                ((uint32_t)0x0000004CUL)
+#define MXC_R_IOMAN_OFFS_I2CS0_REQ                ((uint32_t)0x00000050UL)
+#define MXC_R_IOMAN_OFFS_I2SC0_ACK                ((uint32_t)0x00000054UL)
+#define MXC_R_IOMAN_OFFS_LCD_COM_REQ              ((uint32_t)0x00000058UL)
+#define MXC_R_IOMAN_OFFS_LCD_COM_ACK              ((uint32_t)0x0000005CUL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ0             ((uint32_t)0x00000060UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_REQ1             ((uint32_t)0x00000064UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK0             ((uint32_t)0x00000068UL)
+#define MXC_R_IOMAN_OFFS_LCD_SEG_ACK1             ((uint32_t)0x0000006CUL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_REQ              ((uint32_t)0x00000070UL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_ACK              ((uint32_t)0x00000074UL)
+#define MXC_R_IOMAN_OFFS_IO_CRNT_MODE             ((uint32_t)0x00000078UL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT0             ((uint32_t)0x0000007CUL)
+#define MXC_R_IOMAN_OFFS_ALI_CONNECT1             ((uint32_t)0x00000080UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_REQ                ((uint32_t)0x00000084UL)
+#define MXC_R_IOMAN_OFFS_I2CM1_ACK                ((uint32_t)0x00000088UL)
+#define MXC_R_IOMAN_OFFS_PADX_CONTROL             ((uint32_t)0x0000008CUL)
+
+
+/*
+   Field positions and masks for module IOMAN.
+*/
+#define MXC_F_IOMAN_WUD_REQ0_PORT0_POS                      0
+#define MXC_F_IOMAN_WUD_REQ0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT0_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT1_POS                      8
+#define MXC_F_IOMAN_WUD_REQ0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT1_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT2_POS                      16
+#define MXC_F_IOMAN_WUD_REQ0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT2_POS))
+#define MXC_F_IOMAN_WUD_REQ0_PORT3_POS                      24
+#define MXC_F_IOMAN_WUD_REQ0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_PORT3_POS))
+
+#define MXC_F_IOMAN_WUD_REQ1_PORT4_POS                      0
+#define MXC_F_IOMAN_WUD_REQ1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT4_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT5_POS                      8
+#define MXC_F_IOMAN_WUD_REQ1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT5_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT6_POS                      16
+#define MXC_F_IOMAN_WUD_REQ1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT6_POS))
+#define MXC_F_IOMAN_WUD_REQ1_PORT7_POS                      24
+#define MXC_F_IOMAN_WUD_REQ1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_PORT7_POS))
+
+#define MXC_F_IOMAN_WUD_ACK0_PORT0_POS                      0
+#define MXC_F_IOMAN_WUD_ACK0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT0_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT1_POS                      8
+#define MXC_F_IOMAN_WUD_ACK0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT1_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT2_POS                      16
+#define MXC_F_IOMAN_WUD_ACK0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT2_POS))
+#define MXC_F_IOMAN_WUD_ACK0_PORT3_POS                      24
+#define MXC_F_IOMAN_WUD_ACK0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_PORT3_POS))
+
+#define MXC_F_IOMAN_WUD_ACK1_PORT4_POS                      0
+#define MXC_F_IOMAN_WUD_ACK1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT4_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT5_POS                      8
+#define MXC_F_IOMAN_WUD_ACK1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT5_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT6_POS                      16
+#define MXC_F_IOMAN_WUD_ACK1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT6_POS))
+#define MXC_F_IOMAN_WUD_ACK1_PORT7_POS                      24
+#define MXC_F_IOMAN_WUD_ACK1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_PORT7_POS))
+
+#define MXC_F_IOMAN_ALI_REQ0_PORT0_POS                      0
+#define MXC_F_IOMAN_ALI_REQ0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT0_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT1_POS                      8
+#define MXC_F_IOMAN_ALI_REQ0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT1_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT2_POS                      16
+#define MXC_F_IOMAN_ALI_REQ0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT2_POS))
+#define MXC_F_IOMAN_ALI_REQ0_PORT3_POS                      24
+#define MXC_F_IOMAN_ALI_REQ0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_PORT3_POS))
+
+#define MXC_F_IOMAN_ALI_REQ1_PORT4_POS                      0
+#define MXC_F_IOMAN_ALI_REQ1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT4_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT5_POS                      8
+#define MXC_F_IOMAN_ALI_REQ1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT5_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT6_POS                      16
+#define MXC_F_IOMAN_ALI_REQ1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT6_POS))
+#define MXC_F_IOMAN_ALI_REQ1_PORT7_POS                      24
+#define MXC_F_IOMAN_ALI_REQ1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_PORT7_POS))
+
+#define MXC_F_IOMAN_ALI_ACK0_PORT0_POS                      0
+#define MXC_F_IOMAN_ALI_ACK0_PORT0                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT0_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT1_POS                      8
+#define MXC_F_IOMAN_ALI_ACK0_PORT1                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT1_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT2_POS                      16
+#define MXC_F_IOMAN_ALI_ACK0_PORT2                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT2_POS))
+#define MXC_F_IOMAN_ALI_ACK0_PORT3_POS                      24
+#define MXC_F_IOMAN_ALI_ACK0_PORT3                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_PORT3_POS))
+
+#define MXC_F_IOMAN_ALI_ACK1_PORT4_POS                      0
+#define MXC_F_IOMAN_ALI_ACK1_PORT4                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT4_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT5_POS                      8
+#define MXC_F_IOMAN_ALI_ACK1_PORT5                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT5_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT6_POS                      16
+#define MXC_F_IOMAN_ALI_ACK1_PORT6                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT6_POS))
+#define MXC_F_IOMAN_ALI_ACK1_PORT7_POS                      24
+#define MXC_F_IOMAN_ALI_ACK1_PORT7                          ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_PORT7_POS))
+
+#define MXC_F_IOMAN_SPI_MAPPING_POS                         0
+#define MXC_F_IOMAN_SPI_MAPPING                             ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPI_MAPPING_POS))
+#define MXC_F_IOMAN_SPI_CORE_IO_POS                         4
+#define MXC_F_IOMAN_SPI_CORE_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_CORE_IO_POS))
+#define MXC_F_IOMAN_SPI_SS0_IO_POS                          8
+#define MXC_F_IOMAN_SPI_SS0_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS0_IO_POS))
+#define MXC_F_IOMAN_SPI_SS1_IO_POS                          9
+#define MXC_F_IOMAN_SPI_SS1_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS1_IO_POS))
+#define MXC_F_IOMAN_SPI_SS2_IO_POS                          10
+#define MXC_F_IOMAN_SPI_SS2_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS2_IO_POS))
+#define MXC_F_IOMAN_SPI_SS3_IO_POS                          11
+#define MXC_F_IOMAN_SPI_SS3_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS3_IO_POS))
+#define MXC_F_IOMAN_SPI_SS4_IO_POS                          12
+#define MXC_F_IOMAN_SPI_SS4_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SS4_IO_POS))
+#define MXC_F_IOMAN_SPI_SR0_IO_POS                          16
+#define MXC_F_IOMAN_SPI_SR0_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR0_IO_POS))
+#define MXC_F_IOMAN_SPI_SR1_IO_POS                          17
+#define MXC_F_IOMAN_SPI_SR1_IO                              ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_SR1_IO_POS))
+#define MXC_F_IOMAN_SPI_QUAD_IO_POS                         20
+#define MXC_F_IOMAN_SPI_QUAD_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_QUAD_IO_POS))
+#define MXC_F_IOMAN_SPI_FAST_MODE_POS                       24
+#define MXC_F_IOMAN_SPI_FAST_MODE                           ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPI_FAST_MODE_POS))
+
+#define MXC_F_IOMAN_UART_MAPPING_POS                        0
+#define MXC_F_IOMAN_UART_MAPPING                            ((uint32_t)(0x00000003UL << MXC_F_IOMAN_UART_MAPPING_POS))
+#define MXC_F_IOMAN_UART_CORE_IO_POS                        4
+#define MXC_F_IOMAN_UART_CORE_IO                            ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CORE_IO_POS))
+#define MXC_F_IOMAN_UART_CTS_IO_POS                         5
+#define MXC_F_IOMAN_UART_CTS_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_CTS_IO_POS))
+#define MXC_F_IOMAN_UART_RTS_IO_POS                         6
+#define MXC_F_IOMAN_UART_RTS_IO                             ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART_RTS_IO_POS))
+
+#define MXC_F_IOMAN_I2CM_MAPPING_POS                        0
+#define MXC_F_IOMAN_I2CM_MAPPING                            ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM_MAPPING_POS))
+#define MXC_F_IOMAN_I2CM_CORE_IO_POS                        4
+#define MXC_F_IOMAN_I2CM_CORE_IO                            ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM_CORE_IO_POS))
+
+#define MXC_F_IOMAN_I2CS_MAPPING_POS                        0
+#define MXC_F_IOMAN_I2CS_MAPPING                            ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_MAPPING_POS))
+#define MXC_F_IOMAN_I2CS_CORE_IO_POS                        4
+#define MXC_F_IOMAN_I2CS_CORE_IO                            ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_CORE_IO_POS))
+
+#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS                  0
+#define MXC_F_IOMAN_LCD_COM_REQ_COM_IO                      ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_REQ_COM_IO_POS))
+
+#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS                  0
+#define MXC_F_IOMAN_LCD_COM_ACK_COM_IO                      ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_COM_ACK_COM_IO_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS              0
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_24_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS              1
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_25_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS              2
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_26_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS              3
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_27_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS              4
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_28_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS              5
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_29_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS              6
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_30_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS              7
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_31_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS              8
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_32_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS              9
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_33_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS              10
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_34_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS              11
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_35_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS              12
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_36_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS              13
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_37_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS              14
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_38_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS              15
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_39_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS              16
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_40_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS              17
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_41_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS              18
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_42_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS              19
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_43_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS              20
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_44_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS              21
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_45_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS              22
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_46_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS              23
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_47_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS              24
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_48_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS              25
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_49_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS              26
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_50_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS              27
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_51_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS              28
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_52_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS              29
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_53_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS              30
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_54_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS              31
+#define MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ0_IO_REQ_55_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS              0
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_56_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS              1
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_57_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS              2
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_58_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS              3
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_59_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS              4
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_60_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS              5
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_61_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS              6
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_62_POS))
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS              7
+#define MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_REQ1_IO_REQ_63_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS              0
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_24_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS              1
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_25_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS              2
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_26_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS              3
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_27_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS              4
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_28_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS              5
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_29_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS              6
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_30_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS              7
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_31_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS              8
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_32_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS              9
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_33_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS              10
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_34_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS              11
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_35_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS              12
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_36_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS              13
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_37_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS              14
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_38_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS              15
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_39_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS              16
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_40_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS              17
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_41_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS              18
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_42_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS              19
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_43_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS              20
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_44_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS              21
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_45_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS              22
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_46_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS              23
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_47_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS              24
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_48_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS              25
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_49_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS              26
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_50_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS              27
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_51_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS              28
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_52_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS              29
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_53_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS              30
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_54_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS              31
+#define MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK0_IO_ACK_55_POS))
+
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS              0
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_56_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS              1
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_57_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS              2
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_58_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS              3
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_59_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS              4
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_60_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS              5
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_61_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS              6
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_62_POS))
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS              7
+#define MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63                  ((uint32_t)(0x00000001UL << MXC_F_IOMAN_LCD_SEG_ACK1_IO_ACK_63_POS))
+
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS               0
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS               1
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS               2
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS               3
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS               4
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS               5
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS               6
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS               7
+#define MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_REQ_IO_REQ_CRNT7_POS))
+
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS               0
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS               1
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS               2
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS               3
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS               4
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS               5
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS               6
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS               7
+#define MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7                   ((uint32_t)(0x00000001UL << MXC_F_IOMAN_CRNT_ACK_IO_ACK_CRNT7_POS))
+
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS                  0
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT0                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT0_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS                  4
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT1                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT1_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS                  8
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT2                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT2_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS                  12
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT3                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT3_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS                  16
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT4                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT4_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS                  20
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT5                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT5_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS                  24
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT6                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT6_POS))
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS                  28
+#define MXC_F_IOMAN_CRNT_MODE_IO_CRNT7                      ((uint32_t)(0x0000000FUL << MXC_F_IOMAN_CRNT_MODE_IO_CRNT7_POS))
+
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS     0
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL         ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_POWER_CONTROL_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS    4
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE        ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_OUT_MODE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS 6
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE     ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO0_INPUT_STATE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS    8
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE        ((uint32_t)(0x00000003UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_OUT_MODE_POS))
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS 10
+#define MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE     ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PADX_CONTROL_PADX_GPIO1_INPUT_STATE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_IOMAN_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/lcd_regs.h

@@ -0,0 +1,70 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_LCD_REGS_H
+#define _MXC_LCD_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  lcd_regs.h
+ * @addtogroup lcd LCD
+ * @{
+ */
+
+#define MXC_LCD_ADDRESS_SEGS 21
+
+/*                                 Offset   Register Description
+                                   ======   ======================================================= */
+typedef struct {    
+    __IO uint32_t lcfg;         /* 0x0000                                                           */
+    __IO uint32_t lcra;         /* 0x0004                                                           */
+    __IO uint32_t lpcf;         /* 0x0008  LCD Port Configuration Register                          */
+    __IO uint32_t lcaddr;       /* 0x000C                                                           */
+    __IO uint32_t lcdata;       /* 0x0010  LCD Memory Data Read / Write                             */
+    __IO uint32_t lpwrctrl;     /* 0x0014  LCD Power Control                                        */
+} mxc_lcd_regs_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _MXC_LCD_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/maa_regs.h

@@ -0,0 +1,124 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_MAA_REGS_H_
+#define _MXC_MAA_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  maa_regs.h
+ * @addtogroup maa MAA
+ * @{
+ */
+
+/*                                    Offset   Register Description
+                                      ======   ========================================================== */
+typedef struct {
+    __IO uint32_t ctrl;           /*  0x0000   MAA Control, Configuration and Status                      */
+    __IO uint32_t maws;           /*  0x0004   MAA Word (Operand) Size, Big/Little Endian Mode Select     */
+} mxc_maa_regs_t;
+
+/*                                    Offset   Register Description
+                                      ======   ========================================================== */
+typedef struct {
+    __IO uint32_t seg0[16];        /*  0x0000   [64 bytes] MAA Memory Segment 0                            */
+    __IO uint32_t seg1[16];        /*  0x0040   [64 bytes] MAA Memory Segment 1                            */
+    __IO uint32_t seg2[16];        /*  0x0080   [64 bytes] MAA Memory Segment 2                            */
+    __IO uint32_t seg3[16];        /*  0x00C0   [64 bytes] MAA Memory Segment 3                            */
+    __IO uint32_t seg4[16];        /*  0x0100   [64 bytes] MAA Memory Segment 4                            */
+    __IO uint32_t seg5[16];        /*  0x0140   [64 bytes] MAA Memory Segment 5                            */
+} mxc_maa_mem_regs_t;
+
+/*
+   Register offsets for module MAA.
+*/
+#define MXC_R_MAA_OFFS_CTRL         ((uint32_t)0x00000000UL)
+#define MXC_R_MAA_OFFS_MAWS         ((uint32_t)0x00000004UL)
+#define MXC_R_MAA_MEM_OFFS_SEG0     ((uint32_t)0x00000000UL)
+#define MXC_R_MAA_MEM_OFFS_SEG1     ((uint32_t)0x00000040UL)
+#define MXC_R_MAA_MEM_OFFS_SEG2     ((uint32_t)0x00000080UL)
+#define MXC_R_MAA_MEM_OFFS_SEG3     ((uint32_t)0x000000C0UL)
+#define MXC_R_MAA_MEM_OFFS_SEG4     ((uint32_t)0x00000100UL)
+#define MXC_R_MAA_MEM_OFFS_SEG5     ((uint32_t)0x00000140UL)
+
+/*
+   Field positions and masks for module MAA.
+*/
+#define MXC_F_MAA_CTRL_START_POS    0
+#define MXC_F_MAA_CTRL_START        ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_START_POS))
+#define MXC_F_MAA_CTRL_OPSEL_POS    1
+#define MXC_F_MAA_CTRL_OPSEL        ((uint32_t)(0x00000007UL << MXC_F_MAA_CTRL_OPSEL_POS))
+#define MXC_F_MAA_CTRL_OCALC_POS    4
+#define MXC_F_MAA_CTRL_OCALC        ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_OCALC_POS))
+#define MXC_F_MAA_CTRL_INTEN_POS    5
+#define MXC_F_MAA_CTRL_INTEN        ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_INTEN_POS))
+#define MXC_F_MAA_CTRL_IF_DONE_POS  6
+#define MXC_F_MAA_CTRL_IF_DONE      ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_DONE_POS))
+#define MXC_F_MAA_CTRL_IF_ERROR_POS 7
+#define MXC_F_MAA_CTRL_IF_ERROR     ((uint32_t)(0x00000001UL << MXC_F_MAA_CTRL_IF_ERROR_POS))
+#define MXC_F_MAA_CTRL_OFS_A_POS    8
+#define MXC_F_MAA_CTRL_OFS_A        ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_A_POS))
+#define MXC_F_MAA_CTRL_OFS_B_POS    10
+#define MXC_F_MAA_CTRL_OFS_B        ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_B_POS))
+#define MXC_F_MAA_CTRL_OFS_EXP_POS  12
+#define MXC_F_MAA_CTRL_OFS_EXP      ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_EXP_POS))
+#define MXC_F_MAA_CTRL_OFS_MOD_POS  14
+#define MXC_F_MAA_CTRL_OFS_MOD      ((uint32_t)(0x00000003UL << MXC_F_MAA_CTRL_OFS_MOD_POS))
+#define MXC_F_MAA_CTRL_SEG_A_POS    16
+#define MXC_F_MAA_CTRL_SEG_A        ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_A_POS))
+#define MXC_F_MAA_CTRL_SEG_B_POS    20
+#define MXC_F_MAA_CTRL_SEG_B        ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_B_POS))
+#define MXC_F_MAA_CTRL_SEG_RES_POS  24
+#define MXC_F_MAA_CTRL_SEG_RES      ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_RES_POS))
+#define MXC_F_MAA_CTRL_SEG_TMP_POS  28
+#define MXC_F_MAA_CTRL_SEG_TMP      ((uint32_t)(0x0000000FUL << MXC_F_MAA_CTRL_SEG_TMP_POS))
+
+#define MXC_F_MAA_MAWS_MODLEN_POS   0
+#define MXC_F_MAA_MAWS_MODLEN       ((uint32_t)(0x000003FFUL << MXC_F_MAA_MAWS_MODLEN_POS))
+#define MXC_F_MAA_MAWS_BYTESWAP_POS 16
+#define MXC_F_MAA_MAWS_BYTESWAP     ((uint32_t)(0x00000001UL << MXC_F_MAA_MAWS_BYTESWAP_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_MAA_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/max32600.h

@@ -0,0 +1,666 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MAX32600_H_
+#define _MAX32600_H_
+
+#include <stdint.h>
+
+typedef enum IRQn_Type {
+    NonMaskableInt_IRQn = -14,
+    HardFault_IRQn = -13,
+    MemoryManagement_IRQn = -12,
+    BusFault_IRQn = -11,
+    UsageFault_IRQn = -10,
+    SVCall_IRQn = -5,
+    DebugMonitor_IRQn = -4,
+    PendSV_IRQn = -2,
+    SysTick_IRQn = -1,
+
+    /* Externals interrupts */
+    UART0_IRQn = 0,      /* 16:01 UART0 */
+    UART1_IRQn,          /* 17: 2 UART1 */
+    I2CM0_IRQn,          /* 18: 3 I2C Master 0 */
+    I2CS_IRQn,           /* 19: 4 I2C Slave */
+    USB_IRQn,            /* 20: 5 USB */
+    PMU_IRQn,            /* 21: 6 DMA */
+    AFE_IRQn,            /* 22: 7 AFE */
+    MAA_IRQn,            /* 23: 8 MAA */
+    AES_IRQn,            /* 24: 9 AES */
+    SPI0_IRQn,           /* 25:10 SPI0 */
+    SPI1_IRQn,           /* 26:11 SPI1 */
+    SPI2_IRQn,           /* 27:12 SPI2 */
+    TMR0_IRQn,           /* 28:13 Timer32-0 */
+    TMR1_IRQn,           /* 29:14 Timer32-1 */
+    TMR2_IRQn,           /* 30:15 Timer32-1 */
+    TMR3_IRQn,           /* 31:16 Timer32-2 */
+    RSVD0_IRQn,          /* 32:17 RSVD */
+    RSVD1_IRQn,          /* 33:18 RSVD */
+    DAC0_IRQn,           /* 34:19 DAC0  (12-bit DAC) */
+    DAC1_IRQn,           /* 35:20 DAC1  (12-bit DAC) */
+    DAC2_IRQn,           /* 36:21 DAC2  (8-bit DAC) */
+    DAC3_IRQn,           /* 37:22 DAC3  (8-bit DAC) */
+    ADC_IRQn,            /* 38:23 ADC */
+    FLC_IRQn,            /* 39:24 Flash Controller */
+    PWRMAN_IRQn,         /* 40:25 PWRMAN */
+    CLKMAN_IRQn,         /* 41:26 CLKMAN */
+    RTC0_IRQn,           /* 42:27 RTC INT0 */
+    RTC1_IRQn,           /* 43:28 RTC INT1 */
+    RTC2_IRQn,           /* 44:29 RTC INT2 */
+    RTC3_IRQn,           /* 45:30 RTC INT3 */
+    WDT0_IRQn,           /* 46:31 WATCHDOG0 */
+    WDT0_P_IRQn,         /* 47:32 WATCHDOG0 PRE-WINDOW */
+    WDT1_IRQn,           /* 48:33 WATCHDOG1 */
+    WDT1_P_IRQn,         /* 49:34 WATCHDOG1 PRE-WINDOW */
+    GPIO_P0_IRQn,        /* 50:35 GPIO Port 0  */
+    GPIO_P1_IRQn,        /* 51:36 GPIO Port 1  */
+    GPIO_P2_IRQn,        /* 52:37 GPIO Port 2  */
+    GPIO_P3_IRQn,        /* 53:38 GPIO Port 3  */
+    GPIO_P4_IRQn,        /* 54:39 GPIO Port 4  */
+    GPIO_P5_IRQn,        /* 55:40 GPIO Port 5  */
+    GPIO_P6_IRQn,        /* 56:41 GPIO Port 6  */
+    GPIO_P7_IRQn,        /* 57:42 GPIO Port 7  */
+    TMR16_0_IRQn,        /* 58:43 Timer16-s0 */
+    TMR16_1_IRQn,        /* 59:44 Timer16-s1 */
+    TMR16_2_IRQn,        /* 60:45 Timer16-s2 */
+    TMR16_3_IRQn,        /* 61:46 Timer16-s3 */
+    I2CM1_IRQn,          /* 62:47 I2C Master 1 */
+    MXC_IRQ_EXT_COUNT,
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels         */
+
+#include <core_cm3.h>                       /* Processor and core peripherals */
+#include "system_max32600.h"                /* System Header */
+
+/* ================================================================================ */
+/* ==================       Device Specific Memory Section       ================== */
+/* ================================================================================ */
+
+#define MXC_FLASH_MEM_BASE    0x00000000UL
+#define MXC_FLASH_PAGE_SIZE   0x1000        // 256 x 128b = 4KB
+#define MXC_FLASH_MEM_SIZE    0x00040000UL
+#define MXC_SYS_MEM_BASE      0x20000000UL
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+/*******************************************************************************/
+/*                                            General Purpose I/O Ports (GPIO) */
+
+#define MXC_BASE_GPIO                   ((uint32_t)0x40000000UL)
+#define MXC_GPIO                        ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
+#define MXC_BASE_GPIO_BITBAND           ((uint32_t)0x42000000UL)
+
+#define MXC_GPIO_GET_IRQ(i)             (((unsigned int)i) + GPIO_P0_IRQn)
+
+
+/*******************************************************************************/
+/*                                                      Pulse Train Generation */
+
+#define MXC_CFG_PT_INSTANCES             (13)
+
+#define MXC_BASE_PTG                     ((uint32_t)0x40001000UL)
+#define MXC_PTG                          ((mxc_ptg_regs_t *)MXC_BASE_PTG)
+#define MXC_BASE_PT                      ((uint32_t)0x40001008UL)
+#define MXC_PT                           ((mxc_pt_regs_t *)MXC_BASE_PT)
+#define MXC_BASE_PT0                     ((uint32_t)0x40001008UL)
+#define MXC_PT0                          ((mxc_pt_regs_t *)MXC_BASE_PT0)
+#define MXC_BASE_PT1                     ((uint32_t)0x40001010UL)
+#define MXC_PT1                          ((mxc_pt_regs_t *)MXC_BASE_PT1)
+#define MXC_BASE_PT2                     ((uint32_t)0x40001018UL)
+#define MXC_PT2                          ((mxc_pt_regs_t *)MXC_BASE_PT2)
+#define MXC_BASE_PT3                     ((uint32_t)0x40001020UL)
+#define MXC_PT3                          ((mxc_pt_regs_t *)MXC_BASE_PT3)
+#define MXC_BASE_PT4                     ((uint32_t)0x40001028UL)
+#define MXC_PT4                          ((mxc_pt_regs_t *)MXC_BASE_PT4)
+#define MXC_BASE_PT5                     ((uint32_t)0x40001030UL)
+#define MXC_PT5                          ((mxc_pt_regs_t *)MXC_BASE_PT5)
+#define MXC_BASE_PT6                     ((uint32_t)0x40001038UL)
+#define MXC_PT6                          ((mxc_pt_regs_t *)MXC_BASE_PT6)
+#define MXC_BASE_PT7                     ((uint32_t)0x40001040UL)
+#define MXC_PT7                          ((mxc_pt_regs_t *)MXC_BASE_PT7)
+#define MXC_BASE_PT8                     ((uint32_t)0x40001048UL)
+#define MXC_PT8                          ((mxc_pt_regs_t *)MXC_BASE_PT8)
+#define MXC_BASE_PT9                     ((uint32_t)0x40001050UL)
+#define MXC_PT9                          ((mxc_pt_regs_t *)MXC_BASE_PT9)
+#define MXC_BASE_PT10                    ((uint32_t)0x40001058UL)
+#define MXC_PT10                         ((mxc_pt_regs_t *)MXC_BASE_PT10)
+#define MXC_BASE_PT11                    ((uint32_t)0x40001060UL)
+#define MXC_PT11                         ((mxc_pt_regs_t *)MXC_BASE_PT11)
+
+/*                                       PT12, PT13, PT14 are not used         */
+
+/*******************************************************************************/
+/*                                                        CRC-16/CRC-32 Engine */
+
+#define MXC_BASE_CRC                    ((uint32_t)0x40010000UL)
+#define MXC_CRC_REGS                    ((mxc_crc_regs_t *)MXC_BASE_CRC)
+
+#define MXC_BASE_CRC_DATA               ((uint32_t)0x4010B000UL)
+#define MXC_CRC_DATA                    ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
+
+/*******************************************************************************/
+/*                                                 Trust Protection Unit (TPU) */
+
+#define MXC_BASE_TPU                     ((uint32_t)0x40011000UL)
+#define MXC_TPU                          ((mxc_tpu_regs_t *)MXC_BASE_TPU)
+
+#define MXC_BASE_TPU_TSR                 ((uint32_t)0x40011C00UL)
+#define MXC_TPU_TSR                      ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
+
+/*******************************************************************************/
+/*                                                    AES Cryptographic Engine */
+
+#define MXC_BASE_AES                     ((uint32_t)0x40011400UL)
+#define MXC_AES                          ((mxc_aes_regs_t *)MXC_BASE_AES)
+
+#define MXC_BASE_AES_MEM                 ((uint32_t)0x4010A000UL)
+#define MXC_AES_MEM                      ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
+
+
+/*******************************************************************************/
+/*                                                    MAA Cryptographic Engine */
+
+#define MXC_BASE_MAA                     ((uint32_t)0x40011800UL)
+#define MXC_MAA                          ((mxc_maa_regs_t *)MXC_BASE_MAA)
+
+#define MXC_BASE_MAA_MEM                 ((uint32_t)0x4010A800UL)
+#define MXC_MAA_MEM                      ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
+
+/*******************************************************************************/
+/*                                                    32-Bit PWM Timer/Counter */
+
+#define MXC_CFG_TMR_INSTANCES            (4)
+
+#define MXC_BASE_TMR0                    ((uint32_t)0x40012000UL)
+#define MXC_BASE_TMR0_BITBAND            ((uint32_t)0x42240000UL)
+#define MXC_TMR0                         ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
+
+#define MXC_BASE_TMR1                    ((uint32_t)0x40013000UL)
+#define MXC_BASE_TMR1_BITBAND            ((uint32_t)0x42260000UL)
+#define MXC_TMR1                         ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
+
+#define MXC_BASE_TMR2                    ((uint32_t)0x40014000UL)
+#define MXC_BASE_TMR2_BITBAND            ((uint32_t)0x42280000UL)
+#define MXC_TMR2                         ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
+
+#define MXC_BASE_TMR3                    ((uint32_t)0x40015000UL)
+#define MXC_BASE_TMR3_BITBAND            ((uint32_t)0x422A0000UL)
+#define MXC_TMR3                         ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
+
+
+#define MXC_TMR_GET_IRQ_32(i)            ((i) == 0 ? TMR0_IRQn :    \
+                                          (i) == 1 ? TMR1_IRQn :    \
+                                          (i) == 2 ? TMR2_IRQn :    \
+                                          (i) == 3 ? TMR3_IRQn : 0)
+
+#define MXC_TMR_GET_IRQ_16(i)            ((i) == 0 ? TMR0_IRQn :    \
+                                          (i) == 1 ? TMR1_IRQn :    \
+                                          (i) == 2 ? TMR2_IRQn :    \
+                                          (i) == 3 ? TMR3_IRQn :    \
+                                          (i) == 4 ? TMR16_0_IRQn :    \
+                                          (i) == 5 ? TMR16_1_IRQn :    \
+                                          (i) == 6 ? TMR16_2_IRQn :    \
+                                          (i) == 7 ? TMR16_3_IRQn : 0)
+
+#define MXC_TMR_GET_BASE(i)              ((i) == 0 ? MXC_BASE_TMR0 : \
+                                          (i) == 1 ? MXC_BASE_TMR1 : \
+                                          (i) == 2 ? MXC_BASE_TMR2 : \
+                                          (i) == 3 ? MXC_BASE_TMR3 : 0)
+
+#define MXC_TMR_GET_TMR(i)               ((i) == 0 ? MXC_TMR0 : \
+                                          (i) == 1 ? MXC_TMR1 : \
+                                          (i) == 2 ? MXC_TMR2 : \
+                                          (i) == 3 ? MXC_TMR3 : 0)
+/*******************************************************************************/
+/*                                                              Watchdog Timer */
+
+#define MXC_CFG_WDT_INSTANCES            (2)
+
+#define MXC_BASE_WDT0                    ((uint32_t)0x40021000UL)
+#define MXC_BASE_WDT0_BITBAND            ((uint32_t)0x42420000UL)
+#define MXC_WDT0                         ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
+
+#define MXC_BASE_WDT1                    ((uint32_t)0x40022000UL)
+#define MXC_BASE_WDT1_BITBAND            ((uint32_t)0x42440000UL)
+#define MXC_WDT1                         ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
+
+#define MXC_WDT_GET_IRQ(i)               ((i) == 0 ? WDT0_IRQn : \
+                                          (i) == 1 ? WDT1_IRQn : 0)
+
+#define MXC_WDT_GET_IRQ_P(i)             ((i) == 0 ? WDT0_P_IRQn : \
+                                          (i) == 1 ? WDT1_P_IRQn : 0)
+
+#define MXC_WDT_GET_BASE(i)              ((i) == 0 ? MXC_BASE_WDT0 : \
+                                          (i) == 1 ? MXC_BASE_WDT1 : 0)
+
+#define MXC_WDT_GET_WDT(i)               ((i) == 0 ? MXC_WDT0 : \
+                                          (i) == 1 ? MXC_WDT1 : 0)
+
+/*******************************************************************************/
+/*                                                               SPI Interface */
+
+#define MXC_CFG_SPI_INSTANCES            (3)
+#define MXC_CFG_SPI_FIFO_DEPTH           (16)
+
+#define MXC_BASE_SPI0                    ((uint32_t)0x40030000UL)
+#define MXC_SPI0                         ((mxc_spi_regs_t *)MXC_BASE_SPI0)
+
+#define MXC_BASE_SPI0_TXFIFO             ((uint32_t)0x40100000UL)
+#define MXC_SPI0_TXFIFO                  ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO)
+#define MXC_BASE_SPI0_RXFIFO             ((uint32_t)0x40100800UL)
+#define MXC_SPI0_RXFIFO                  ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO)
+
+#define MXC_BASE_SPI1                    ((uint32_t)0x40031000UL)
+#define MXC_SPI1                         ((mxc_spi_regs_t *)MXC_BASE_SPI1)
+
+#define MXC_BASE_SPI1_TXFIFO             ((uint32_t)0x40101000UL)
+#define MXC_SPI1_TXFIFO                  ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO)
+#define MXC_BASE_SPI1_RXFIFO             ((uint32_t)0x40101800UL)
+#define MXC_SPI1_RXFIFO                  ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO)
+
+#define MXC_BASE_SPI2                    ((uint32_t)0x40032000UL)
+#define MXC_SPI2                         ((mxc_spi_regs_t *)MXC_BASE_SPI2)
+
+#define MXC_BASE_SPI2_TXFIFO             ((uint32_t)0x40102000UL)
+#define MXC_SPI2_TXFIFO                  ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO)
+#define MXC_BASE_SPI2_RXFIFO             ((uint32_t)0x40102800UL)
+#define MXC_SPI2_RXFIFO                  ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO)
+
+
+#define MXC_SPI_GET_IRQ(i)               ((i) == 0 ? SPI0_IRQn :       \
+                                          (i) == 1 ? SPI1_IRQn :       \
+                                          (i) == 2 ? SPI2_IRQn : 0)
+
+#define MXC_SPI_GET_BASE(i)              ((i) == 0 ? MXC_BASE_SPI0 :      \
+                                          (i) == 1 ? MXC_BASE_SPI1 :      \
+                                          (i) == 2 ? MXC_BASE_SPI2 : 0)
+
+#define MXC_SPI_GET_SPI(i)               ((i) == 0 ? MXC_SPI0 :      \
+                                          (i) == 1 ? MXC_SPI1 :      \
+                                          (i) == 2 ? MXC_SPI2 : 0)
+
+#define MXC_SPI_GET_RXFIFO(i)            ((i) == 0 ? MXC_SPI0_RXFIFO :      \
+                                          (i) == 1 ? MXC_SPI1_RXFIFO :      \
+                                          (i) == 2 ? MXC_SPI2_RXFIFO : 0)
+
+#define MXC_SPI_GET_TXFIFO(i)            ((i) == 0 ? MXC_SPI0_TXFIFO :      \
+                                          (i) == 1 ? MXC_SPI1_TXFIFO :      \
+                                          (i) == 2 ? MXC_SPI2_TXFIFO : 0)
+
+#define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0)
+#define MXC_SPI_BASE_TO_INSTANCE(base)     (((uint32_t)(base) & 0x00003000) >> 12)
+
+
+/*******************************************************************************/
+/*                                                              UART Interface */
+
+#define MXC_CFG_UART_INSTANCES           (2)
+
+#define MXC_BASE_UART0                   ((uint32_t)0x40038000UL)
+#define MXC_BASE_UART0_BITBAND           ((uint32_t)0x42700000UL)
+#define MXC_UART0                        ((mxc_uart_regs_t *)MXC_BASE_UART0)
+
+#define MXC_BASE_UART1                   ((uint32_t)0x40039000UL)
+#define MXC_BASE_UART1_BITBAND           ((uint32_t)0x42720000UL)
+#define MXC_UART1                        ((mxc_uart_regs_t *)MXC_BASE_UART1)
+
+
+#define MXC_UART_GET_IRQ(i)              ((i) == 0 ? UART0_IRQn :      \
+                                          (i) == 1 ? UART1_IRQn : 0)
+
+#define MXC_UART_GET_BASE(i)             ((i) == 0 ? MXC_BASE_UART0 :     \
+                                          (i) == 1 ? MXC_BASE_UART1 : 0)
+
+#define MXC_UART_GET_UART(i)             ((i) == 0 ? MXC_UART0 :     \
+                                          (i) == 1 ? MXC_UART1 : 0)
+
+#define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0)
+#define MXC_UART_BASE_TO_INSTANCE(base)     (((uint32_t)(base) & 0x00001000) >> 12)
+
+
+/*******************************************************************************/
+/*                                                        I2C Master Interface */
+
+#define MXC_CFG_I2CM_INSTANCES           (2)
+
+#define MXC_BASE_I2CM0                   ((uint32_t)0x40040000UL)
+#define MXC_BASE_I2CM0_BITBAND           ((uint32_t)0x42800000UL)
+#define MXC_I2CM0                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
+#define MXC_BASE_I2CM0_TX_FIFO           ((uint32_t)0x40103000UL)
+#define MXC_BASE_I2CM0_RX_FIFO           ((uint32_t)0x40103800UL)
+
+#define MXC_BASE_I2CM1                   ((uint32_t)0x40042000UL)
+#define MXC_BASE_I2CM1_BITBAND           ((uint32_t)0x42840000UL)
+#define MXC_I2CM1                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
+#define MXC_BASE_I2CM1_TX_FIFO           ((uint32_t)0x4010D000UL)
+#define MXC_BASE_I2CM1_RX_FIFO           ((uint32_t)0x4010D800UL)
+
+#define MXC_I2CM_GET_IRQ(i)              ((i) == 0 ? I2CM0_IRQn :      \
+                                          (i) == 1 ? I2CM1_IRQn : 0)
+
+#define MXC_I2CM_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2CM0 :     \
+                                          (i) == 1 ? MXC_BASE_I2CM1 : 0)
+
+#define MXC_I2CM_GET_I2CM(i)             ((i) == 0 ? MXC_I2CM0 :     \
+                                          (i) == 1 ? MXC_I2CM1 : 0)
+
+#define MXC_I2CM_GET_BASE_TX_FIFO(i)     ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO :  \
+                                          (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0)
+
+#define MXC_I2CM_GET_BASE_RX_FIFO(i)     ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO :  \
+                                          (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0)
+
+#define MXC_I2CM_INSTANCE_TO_BASE(instance)   (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0)
+#define MXC_I2CM_BASE_TO_INSTANCE(base)       (((uint32_t)(base) & 0x00002000) >> 13)
+
+
+/*******************************************************************************/
+/*                                                         I2C Slave Interface */
+
+#define MXC_CFG_I2CS_INSTANCES           (1)
+
+#define MXC_BASE_I2CS0                   ((uint32_t)0x40041000UL)
+#define MXC_BASE_I2CS0_BITBAND           ((uint32_t)0x42820000UL)
+#define MXC_I2CS0                        ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
+
+#define MXC_BASE_I2CS0_FIFO              ((uint32_t)0x40104000UL)
+#define MXC_I2CS0_FIFO                   ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
+
+
+
+/*******************************************************************************/
+/*                                                                        DACs */
+
+#define MXC_CFG_DAC_INSTANCES            (4)
+#define MXC_CFG_DAC_FIFO_DEPTH           (32)
+
+#define MXC_BASE_DAC0                    ((uint32_t)0x40050000UL)
+#define MXC_DAC0                         ((mxc_dac_regs_t *)MXC_BASE_DAC0)
+#define MXC_BASE_DAC0_FIFO               ((uint32_t)0x40105000UL)
+#define MXC_DAC0_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
+#define MXC_DAC0_WIDTH                   ((uint8_t)(2))
+
+#define MXC_BASE_DAC1                    ((uint32_t)0x40051000UL)
+#define MXC_DAC1                         ((mxc_dac_regs_t *)MXC_BASE_DAC1)
+#define MXC_BASE_DAC1_FIFO               ((uint32_t)0x40106000UL)
+#define MXC_DAC1_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
+#define MXC_DAC1_WIDTH                   ((uint8_t)(2))
+
+#define MXC_BASE_DAC2                    ((uint32_t)0x40052000UL)
+#define MXC_DAC2                         ((mxc_dac_regs_t *)MXC_BASE_DAC2)
+#define MXC_BASE_DAC2_FIFO               ((uint32_t)0x40107000UL)
+#define MXC_DAC2_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
+#define MXC_DAC2_WIDTH                   ((uint8_t)(1))
+
+#define MXC_BASE_DAC3                    ((uint32_t)0x40053000UL)
+#define MXC_DAC3                         ((mxc_dac_regs_t *)MXC_BASE_DAC3)
+#define MXC_BASE_DAC3_FIFO               ((uint32_t)0x40108000UL)
+#define MXC_DAC3_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
+#define MXC_DAC3_WIDTH                   ((uint8_t)(1))
+
+
+#define MXC_DAC_GET_IRQ(i)               ((i) == 0 ? DAC0_IRQn :     \
+                                          (i) == 1 ? DAC1_IRQn :     \
+                                          (i) == 2 ? DAC2_IRQn :     \
+                                          (i) == 3 ? DAC3_IRQn : 0)
+
+
+#define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
+                             i == 1 ? MXC_BASE_DAC1 : \
+                             i == 2 ? MXC_BASE_DAC2 : \
+                             i == 3 ? MXC_BASE_DAC3 : 0)
+
+#define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
+                             i == 1 ? MXC_BASE_DAC1_FIFO : \
+                             i == 2 ? MXC_BASE_DAC2_FIFO  : \
+                             i == 3 ? MXC_BASE_DAC3_FIFO  : 0)
+
+#define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
+                                     i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
+                                     i == 2 ? PMU_IRQ_DAC2_FIFO_AE  : \
+                                     i == 3 ? PMU_IRQ_DAC3_FIFO_AE  : 0)
+
+#define MXC_DAC_GET_DAC(i)  (i == 0 ? MXC_DAC0 : \
+                             i == 1 ? MXC_DAC1 : \
+                             i == 2 ? MXC_DAC2 : \
+                             i == 3 ? MXC_DAC3 : 0)
+
+#define MXC_DAC_GET_WIDTH(i)  (i == 0 ? MXC_DAC0_WIDTH : \
+                               i == 1 ? MXC_DAC1_WIDTH : \
+                               i == 2 ? MXC_DAC2_WIDTH : \
+                               i == 3 ? MXC_DAC3_WIDTH : 0)
+
+
+/*******************************************************************************/
+/*                                                            Analog Front End */
+
+#define MXC_BASE_AFE                     ((uint32_t)0x4005401CUL)
+#define MXC_AFE                          ((mxc_afe_regs_t *)MXC_BASE_AFE)
+
+
+
+/*******************************************************************************/
+/*                                                                         ADC */
+
+#define MXC_CFG_ADC_FIFO_DEPTH           ((uint32_t)(32))
+
+#define MXC_BASE_ADC                     ((uint32_t)0x40054000UL)
+#define MXC_ADC                          ((mxc_adc_regs_t *)MXC_BASE_ADC)
+
+#define MXC_BASE_ADCCFG                  ((uint32_t)0x40054038UL)
+#define MXC_ADCCFG                       ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
+
+#define MXC_BASE_ADC_FIFO                ((uint32_t)0x40109000UL)
+#define MXC_ADC_FIFO                     ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO)
+
+
+
+/*******************************************************************************/
+/*                                                                         LCD */
+#define MXC_BASE_LCD                     ((uint32_t)0x40060000)
+#define MXC_LCD                          ((mxc_lcd_regs_t *)MXC_BASE_LCD)
+
+/*******************************************************************************/
+/*                  Peripheral Management Unit (PMU) - formerly DMA Controller */
+
+#define MXC_CFG_PMU_CHANNELS             (6)
+
+#define MXC_BASE_PMU0                    ((uint32_t)0x40070000UL)
+#define MXC_PMU0                         ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
+#define MXC_BASE_PMU1                    ((uint32_t)0x40070020UL)
+#define MXC_PMU1                         ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
+#define MXC_BASE_PMU2                    ((uint32_t)0x40070040UL)
+#define MXC_PMU2                         ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
+#define MXC_BASE_PMU3                    ((uint32_t)0x40070060UL)
+#define MXC_PMU3                         ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
+#define MXC_BASE_PMU4                    ((uint32_t)0x40070080UL)
+#define MXC_PMU4                         ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
+#define MXC_BASE_PMU5                    ((uint32_t)0x400700A0UL)
+#define MXC_PMU5                         ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
+
+#define MXC_BASE_PMU_BITBAND            ((uint32_t)0x42E00000UL)
+#define MXC_BASE_PMU_BITBAND_CHOFFSET   ((uint32_t)0x00000400UL)
+/*******************************************************************************/
+
+typedef enum {
+    PMU_IRQ_DAC0_FIFO_AE,
+    PMU_IRQ_DAC1_FIFO_AE,
+    PMU_IRQ_DAC2_FIFO_AE,
+    PMU_IRQ_DAC3_FIFO_AE,
+    PMU_IRQ_DAC0_DONE,
+    PMU_IRQ_DAC1_DONE,
+    PMU_IRQ_DAC2_DONE,
+    PMU_IRQ_DAC3_DONE,
+    PMU_IRQ_ADC_FIFO_AF,
+    PMU_IRQ_ADC_DONE,
+    PMU_IRQ_I2C_MST0_DONE,
+    PMU_IRQ_I2C_MST1_DONE,
+    PMU_IRQ_SPI0_RSLTS_DONE,
+    PMU_IRQ_SPI1_RSLTS_DONE,
+    PMU_IRQ_SPI2_RSLTS_DONE,
+    PMU_IRQ_MAA_DONE,
+    PMU_IRQ_SPI0_TX_FIFO_AE,
+    PMU_IRQ_SPI0_RSLTS_FIFO_AF,
+    PMU_IRQ_SPI1_TX_FIFO_AE,
+    PMU_IRQ_SPI1_RSLTS_FIFO_AF,
+    PMU_IRQ_SPI2_TX_FIFO_AE,
+    PMU_IRQ_SPI3_RSLTS_FIFO_AF,
+    PMU_IRQ_I2C_MST0_TRANS_FIFO,
+    PMU_IRQ_I2C_MST0_RSLT_FIFO,
+    PMU_IRQ_I2C_MST1_TRANS_FIFO,
+    PMU_IRQ_I2C_MST2_RSLT_FIFO,
+    PMU_IRQ_I2C_SLV_TRANS_FIFO,
+    PMU_IRQ_I2C_SLV_RSLT_FIFO,
+    PMU_IRQ_UART0_TX_FIFO,
+    PMU_IRQ_UART0_RX_FIFO,
+    PMU_IRQ_UART1_TX_FIFO,
+    PMU_IRQ_UART1_RX_FIFO,
+    PMU_IRQ_SPI0_EXCP,
+    PMU_IRQ_SPI1_EXCP,
+    PMU_IRQ_SPI2_EXCP,
+    PMU_IRQ_RSVD0,
+    PMU_IRQ_I2C_MST0_EXCP,
+    PMU_IRQ_I2C_MST1_EXCP,
+    PMU_IRQ_I2C_SLV_EXCP,
+    PMU_IRQ_RSVD1,
+    PMU_IRQ_GPIO0,
+    PMU_IRQ_GPIO1,
+    PMU_IRQ_GPIO2,
+    PMU_IRQ_GPIO3,
+    PMU_IRQ_GPIO4,
+    PMU_IRQ_GPIO5,
+    PMU_IRQ_GPIO6,
+    PMU_IRQ_GPIO7,
+    PMU_IRQ_GPIO8,
+    PMU_IRQ_AFE_COMP_NMI,
+    PMU_IRQ_AES_ENGINE,
+} pmu_int_mask_t;
+
+/*******************************************************************************/
+/*                                                                         USB */
+
+#define MXC_BASE_USB                     ((uint32_t)0x4010C000UL)
+#define MXC_USB                          ((mxc_usb_regs_t *)MXC_BASE_USB)
+
+#define MXC_USB_MAX_PACKET               (64)
+#define MXC_USB_NUM_EP                   (8)
+
+
+/*******************************************************************************/
+/*                                                Instruction Cache Controller */
+
+#define MXC_BASE_ICC                     ((uint32_t)0x40080000UL)
+#define MXC_ICC                          ((mxc_icc_regs_t *)MXC_BASE_ICC)
+
+/*                                                              System Manager */
+
+#define MXC_BASE_SYSMAN                 ((uint32_t)0x40090000UL)
+
+/*******************************************************************************/
+/*                                                               Clock Manager */
+
+#define MXC_BASE_CLKMAN                  ((uint32_t)0x40090400UL)
+#define MXC_CLKMAN                       ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
+
+
+/*******************************************************************************/
+/*                                                               Power Manager */
+
+#define MXC_BASE_PWRMAN                  ((uint32_t)0x40090800UL)
+#define MXC_PWRMAN                       ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
+
+/*******************************************************************************/
+/*                                                                 I/O Manager */
+
+#define MXC_BASE_IOMAN                   ((uint32_t)0x40090C00UL)
+#define MXC_IOMAN                        ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
+
+
+/*******************************************************************************/
+/*                                                           RTC: Timer/Alarms */
+
+#define MXC_BASE_RTCTMR                 ((uint32_t)0x40090A00UL)
+#define MXC_RTCTMR                       ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
+
+#define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn :    \
+                               i == 1 ? RTC1_IRQn :    \
+                               i == 2 ? RTC2_IRQn :    \
+                               i == 3 ? RTC3_IRQn : 0)
+
+#define MXC_BASE_RTCCFG                  ((uint32_t)0x40090A70UL)
+#define MXC_RTCCFG                       ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
+/*******************************************************************************/
+/*                                                        RTC: Power Sequencer */
+
+#define MXC_BASE_PWRSEQ                  ((uint32_t)0x40090A30UL)
+#define MXC_PWRSEQ                       ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
+
+/*******************************************************************************/
+/*                                                       Trim Shadow Registers */
+
+#define MXC_BASE_TRIM                    ((uint32_t)0x400E0000UL)
+#define MXC_TRIM                         ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
+
+/*******************************************************************************/
+/*                                          Flash Memory Controller / Security */
+
+#define MXC_BASE_FLC                     ((uint32_t)0x400F0000UL)
+#define MXC_FLC                          ((mxc_flc_regs_t *)MXC_BASE_FLC)
+#define MXC_BASE_FLC_BITBAND             ((uint32_t)0x43E00000UL)
+#define MXC_FLC_PAGE_SIZE_SHIFT          11
+#define MXC_FLC_PAGE_SIZE                (1 << MXC_FLC_PAGE_SIZE_SHIFT)
+#define MXC_FLC_PAGE_ERASE_MSK           ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
+
+/*******************************************************************************/
+
+#define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
+
+/*******************************************************************************/
+
+#define BITBAND(reg, bit)        ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
+#define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0
+#define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1
+#define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
+
+/*******************************************************************************/
+
+#endif  /* _MAX32600_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pmu_regs.h

@@ -0,0 +1,111 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PMU_REGS_H_
+#define _MXC_PMU_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  pmu_regs.h
+ * @addtogroup pmu PMU
+ * @{
+ */
+
+/*                                     Offset   Register Description
+                                       ======   ======================================================== */
+typedef struct {
+    __IO uint32_t dscadr;          /*  0x0000   Starting Descriptor Address                              */
+    __IO uint32_t cfg;             /*  0x0004   Channel Configuration                                    */
+    __IO uint32_t loop;            /*  0x0008   Channel Loop Counters                                    */
+    __IO uint32_t op;              /*  0x000C   Current Descriptor DWORD 0 (OP)                          */
+    __IO uint32_t dsc1;            /*  0x0010   Current Descriptor DWORD 1                               */
+    __IO uint32_t dsc2;            /*  0x0014   Current Descriptor DWORD 2                               */
+    __IO uint32_t dsc3;            /*  0x0018   Current Descriptor DWORD 3                               */
+    __IO uint32_t dsc4;            /*  0x001C   Current Descriptor DWORD 4                               */
+} mxc_pmu_regs_t;
+
+/*
+   Register offsets for module PMU.
+*/
+#define MXC_R_PMU_OFFS_DSCADR                     ((uint32_t)0x00000000UL)
+#define MXC_R_PMU_OFFS_CFG                        ((uint32_t)0x00000004UL)
+#define MXC_R_PMU_OFFS_LOOP                       ((uint32_t)0x00000008UL)
+#define MXC_R_PMU_OFFS_OP                         ((uint32_t)0x0000000CUL)
+#define MXC_R_PMU_OFFS_DSC1                       ((uint32_t)0x00000010UL)
+#define MXC_R_PMU_OFFS_DSC2                       ((uint32_t)0x00000014UL)
+#define MXC_R_PMU_OFFS_DSC3                       ((uint32_t)0x00000018UL)
+#define MXC_R_PMU_OFFS_DSC4                       ((uint32_t)0x0000001CUL)
+
+/*
+   Field positions and masks for module PMU.
+*/
+#define MXC_F_PMU_CFG_ENABLE_POS                            0
+#define MXC_F_PMU_CFG_ENABLE                                ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
+#define MXC_F_PMU_CFG_LL_STOPPED_POS                        2
+#define MXC_F_PMU_CFG_LL_STOPPED                            ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
+#define MXC_F_PMU_CFG_MANUAL_POS                            3
+#define MXC_F_PMU_CFG_MANUAL                                ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
+#define MXC_F_PMU_CFG_BUS_ERROR_POS                         4
+#define MXC_F_PMU_CFG_BUS_ERROR                             ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
+#define MXC_F_PMU_CFG_TO_STAT_POS                           6
+#define MXC_F_PMU_CFG_TO_STAT                               ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
+#define MXC_F_PMU_CFG_TO_SEL_POS                            11
+#define MXC_F_PMU_CFG_TO_SEL                                ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
+#define MXC_F_PMU_CFG_PS_SEL_POS                            14
+#define MXC_F_PMU_CFG_PS_SEL                                ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
+#define MXC_F_PMU_CFG_INTERRUPT_POS                         16
+#define MXC_F_PMU_CFG_INTERRUPT                             ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
+#define MXC_F_PMU_CFG_INT_EN_POS                            17
+#define MXC_F_PMU_CFG_INT_EN                                ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
+#define MXC_F_PMU_CFG_BURST_SIZE_POS                        24
+#define MXC_F_PMU_CFG_BURST_SIZE                            ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
+
+#define MXC_F_PMU_LOOP_COUNTER_0_POS                        0
+#define MXC_F_PMU_LOOP_COUNTER_0                            ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
+#define MXC_F_PMU_LOOP_COUNTER_1_POS                        16
+#define MXC_F_PMU_LOOP_COUNTER_1                            ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_PMU_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pt_regs.h

@@ -0,0 +1,175 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PT_REGS_H_
+#define _MXC_PT_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  pt_regs.h
+ * @addtogroup pt PT
+ * @{
+ */
+
+typedef struct {
+    __IO uint32_t ctrl;
+    __IO uint32_t resync;
+} mxc_ptg_regs_t;
+
+/*                                      Offset   Register Description
+                                        ======   ================================================== */
+typedef struct {
+    __IO uint32_t rate_length;      /*  0x0000   Pulse train Output length and rate                 */
+    __IO uint32_t train;            /*  0x0004   Pulse Train Output Pattern                         */
+} mxc_pt_regs_t;
+
+/*
+   Register offsets for module PT.
+*/
+#define MXC_R_PTG_OFFS_CTRL                         ((uint32_t)0x00000000UL)
+#define MXC_R_PTG_OFFS_RESYNC                       ((uint32_t)0x00000004UL)
+#define MXC_R_PT_OFFS_RATE_LENGTH                   ((uint32_t)0x00000000UL)
+#define MXC_R_PT_OFFS_TRAIN                         ((uint32_t)0x00000004UL)
+
+
+/*
+   Field positions and masks for module PT.
+*/
+#define MXC_F_PT_CTRL_ENABLE_ALL_POS                1
+#define MXC_F_PT_CTRL_ENABLE_ALL                    ((uint32_t)(0x00000001UL << MXC_F_PT_CTRL_ENABLE_ALL_POS))
+
+#define MXC_F_PT_RESYNC_PT0_POS                     0
+#define MXC_F_PT_RESYNC_PT0                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS))
+#define MXC_F_PT_RESYNC_PT1_POS                     1
+#define MXC_F_PT_RESYNC_PT1                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS))
+#define MXC_F_PT_RESYNC_PT2_POS                     2
+#define MXC_F_PT_RESYNC_PT2                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS))
+#define MXC_F_PT_RESYNC_PT3_POS                     3
+#define MXC_F_PT_RESYNC_PT3                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS))
+#define MXC_F_PT_RESYNC_PT4_POS                     4
+#define MXC_F_PT_RESYNC_PT4                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS))
+#define MXC_F_PT_RESYNC_PT5_POS                     5
+#define MXC_F_PT_RESYNC_PT5                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS))
+#define MXC_F_PT_RESYNC_PT6_POS                     6
+#define MXC_F_PT_RESYNC_PT6                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS))
+#define MXC_F_PT_RESYNC_PT7_POS                     7
+#define MXC_F_PT_RESYNC_PT7                         ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS))
+
+#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS       0
+#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL           ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS))
+#define MXC_F_PT_RATE_LENGTH_MODE_POS               27
+#define MXC_F_PT_RATE_LENGTH_MODE                   ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS))
+
+/*
+   Field values and shifted values for module PT.
+*/
+#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN    ((uint32_t)(0x0x00000000UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE       ((uint32_t)(0x0x00000001UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN     ((uint32_t)(0x0x00000002UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN     ((uint32_t)(0x0x00000003UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN     ((uint32_t)(0x0x00000004UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN     ((uint32_t)(0x0x00000005UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN     ((uint32_t)(0x0x00000006UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN     ((uint32_t)(0x0x00000007UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN     ((uint32_t)(0x0x00000008UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN     ((uint32_t)(0x0x00000009UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN    ((uint32_t)(0x0x00000010UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN    ((uint32_t)(0x0x00000011UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN    ((uint32_t)(0x0x00000012UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN    ((uint32_t)(0x0x00000013UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN    ((uint32_t)(0x0x00000014UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN    ((uint32_t)(0x0x00000015UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN    ((uint32_t)(0x0x00000016UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN    ((uint32_t)(0x0x00000017UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN    ((uint32_t)(0x0x00000018UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN    ((uint32_t)(0x0x00000019UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN    ((uint32_t)(0x0x00000020UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN    ((uint32_t)(0x0x00000021UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN    ((uint32_t)(0x0x00000022UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN    ((uint32_t)(0x0x00000023UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN    ((uint32_t)(0x0x00000024UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN    ((uint32_t)(0x0x00000025UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN    ((uint32_t)(0x0x00000026UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN    ((uint32_t)(0x0x00000027UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN    ((uint32_t)(0x0x00000028UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN    ((uint32_t)(0x0x00000029UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN    ((uint32_t)(0x0x00000030UL))
+#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN    ((uint32_t)(0x0x00000031UL))
+
+#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE       ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE      << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT_PATTERN     ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT_PATTERN    << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT_PATTERN    ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT_PATTERN   << MXC_F_PT_RATE_LENGTH_MODE_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_PT_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrman_regs.h

@@ -0,0 +1,386 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PWRMAN_REGS_H_
+#define _MXC_PWRMAN_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  pwrman_regs.h
+ * @addtogroup pwrman PWRMAN
+ * @{
+ */
+
+/**
+ * @brief Defines PAD Modes for Wake Up Detection.
+ */
+typedef enum {
+    /** WUD Mode for Selected PAD = Clear/Activate */
+    MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
+    /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
+    MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
+    /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
+    MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
+    /** WUD Mode for Selected PAD = No pad state change */
+    MXC_E_PWRMAN_PAD_MODE_NONE
+} mxc_pwrman_pad_mode_t;
+
+/*                                          Offset   Register Description
+                                            ======   =========================================== */
+typedef struct {
+    __IO uint32_t pwr_rst_ctrl;         /*  0x0000   Power Reset Control and Status              */
+    __IO uint32_t intfl;                /*  0x0004   Interrupt Flags                             */
+    __IO uint32_t inten;                /*  0x0008   Interrupt Enable/Disable Controls           */
+    __IO uint32_t svm_events;           /*  0x000C   SVM Event Status Flags (read-only)          */
+    __IO uint32_t wud_ctrl;             /*  0x0010   Wake-Up Detect Control                      */
+    __IO uint32_t wud_pulse0;           /*  0x0014   WUD Pulse To Mode Bit 0                     */
+    __IO uint32_t wud_pulse1;           /*  0x0018   WUD Pulse To Mode Bit 1                     */
+    __I uint32_t rsv001C[5];            /*  0x001C                                               */
+
+    __IO uint32_t wud_seen0;            /*  0x0030   Wake-up Detect Status for P0/P1/P2/P3       */
+    __IO uint32_t wud_seen1;            /*  0x0034   Wake-up Detect Status for P4/P5/P6/P7       */
+    __IO uint32_t die_type;             /*  0x0038   Die ID Register (Device Type)               */
+    __IO uint32_t base_part_num;        /*  0x003C   Base Part Number                            */
+    __IO uint32_t mask_id0;             /*  0x0040   Mask ID Register 0                          */
+    __IO uint32_t mask_id1;             /*  0x0044   Mask ID Register 1                          */
+    __IO uint32_t peripheral_reset;     /*  0x0048   Peripheral Reset Control Register           */
+} mxc_pwrman_regs_t;
+
+/*
+   Register offsets for module PWRMAN.
+*/
+#define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL          ((uint32_t)0x00000000UL)
+#define MXC_R_PWRMAN_OFFS_INTFL                 ((uint32_t)0x00000004UL)
+#define MXC_R_PWRMAN_OFFS_INTEN                 ((uint32_t)0x00000008UL)
+#define MXC_R_PWRMAN_OFFS_SVM_EVENTS            ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRMAN_OFFS_WUD_CTRL              ((uint32_t)0x00000010UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE0            ((uint32_t)0x00000014UL)
+#define MXC_R_PWRMAN_OFFS_WUD_PULSE1            ((uint32_t)0x00000018UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN0             ((uint32_t)0x00000030UL)
+#define MXC_R_PWRMAN_OFFS_WUD_SEEN1             ((uint32_t)0x00000034UL)
+#define MXC_R_PWRMAN_OFFS_DIE_TYPE              ((uint32_t)0x00000038UL)
+#define MXC_R_PWRMAN_OFFS_BASE_PART_NUM         ((uint32_t)0x0000003CUL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID0              ((uint32_t)0x00000040UL)
+#define MXC_R_PWRMAN_OFFS_MASK_ID1              ((uint32_t)0x00000044UL)
+#define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET      ((uint32_t)0x00000048UL)
+
+/*
+   Field positions and masks for module PWRMAN.
+*/
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS          0
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE              ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS           1
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS           2
+#define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS             3
+#define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS           4
+#define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS       5
+#define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS        8
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS      9
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET          ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS             12
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS         16
+#define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT             ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS     17
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN         ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS      18
+#define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT          ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS        19
+#define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS            20
+#define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS       21
+#define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS                   22
+#define MXC_F_PWRMAN_PWR_RST_CTRL_POR                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS        31
+#define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
+
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS                 0
+#define MXC_F_PWRMAN_INTFL_V1_8_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS                 1
+#define MXC_F_PWRMAN_INTFL_V3_3_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS                  2
+#define MXC_F_PWRMAN_INTFL_RTC_WARNING                      ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS                   3
+#define MXC_F_PWRMAN_INTFL_V3_3_RESET                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS                 4
+#define MXC_F_PWRMAN_INTFL_VDDA_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS                 0
+#define MXC_F_PWRMAN_INTEN_V1_8_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS                 1
+#define MXC_F_PWRMAN_INTEN_V3_3_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS                  2
+#define MXC_F_PWRMAN_INTEN_RTC_WARNING                      ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS                   3
+#define MXC_F_PWRMAN_INTEN_V3_3_RESET                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS                 4
+#define MXC_F_PWRMAN_INTEN_VDDA_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS            0
+#define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS            1
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS             2
+#define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS              3
+#define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS))
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS            4
+#define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
+
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS                0
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT                    ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS                  8
+#define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE                      ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS                 12
+#define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS                    0
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO0                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS                    1
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO1                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS                    2
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO2                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS                    3
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO3                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS                    4
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO4                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS                    5
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO5                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS                    6
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO6                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS                    7
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO7                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS                    8
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO8                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS                    9
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO9                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS                   10
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO10                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS                   11
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO11                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS                   12
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO12                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS                   13
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO13                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS                   14
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO14                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS                   15
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO15                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS                   16
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO16                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS                   17
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO17                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS                   18
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO18                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS                   19
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO19                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS                   20
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO20                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS                   21
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO21                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS                   22
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO22                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS                   23
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO23                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS                   24
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO24                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS                   25
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO25                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS                   26
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO26                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS                   27
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO27                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS                   28
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO28                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS                   29
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO29                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS                   30
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO30                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS                   31
+#define MXC_F_PWRMAN_WUD_SEEN0_GPIO31                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
+
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS                   0
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO32                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS                   1
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO33                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS                   2
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO34                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS                   3
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO35                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS                   4
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO36                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS                   5
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO37                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS                   6
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO38                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS                   7
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO39                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS                   8
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO40                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS                   9
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO41                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS                   10
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO42                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS                   11
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO43                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS                   12
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO44                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS                   13
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO45                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS                   14
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO46                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS                   15
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO47                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS                   16
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO48                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS                   17
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO49                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS                   18
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO50                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS                   19
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO51                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS                   20
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO52                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS                   21
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO53                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS                   22
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO54                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS                   23
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO55                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS                   24
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO56                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS                   25
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO57                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS                   26
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO58                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS                   27
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO59                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS                   28
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO60                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS                   29
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO61                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS                   30
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO62                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS))
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS                   31
+#define MXC_F_PWRMAN_WUD_SEEN1_GPIO63                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS))
+
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS     0
+#define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER         ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
+#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS       28
+#define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS))
+
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS               0
+#define MXC_F_PWRMAN_MASK_ID0_REVISION_ID                   ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS                   4
+#define MXC_F_PWRMAN_MASK_ID0_MASK_ID                       ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
+
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS                   0
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID                       ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS            31
+#define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
+
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS             0
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS             1
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS            2
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS            3
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS            4
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS            5
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS         6
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0             ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS               7
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_USB                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS               8
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS              9
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS              10
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS              11
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS              12
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS               13
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS               14
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS              15
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS       16
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS              17
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS              18
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS              19
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS             20
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS             21
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS              22
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS               23
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS               24
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS               25
+#define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PWRMAN_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/pwrseq_regs.h

@@ -0,0 +1,299 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_PWRSEQ_REGS_H
+#define _MXC_PWRSEQ_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  pwrseq_regs.h
+ * @addtogroup pwrseq PWRSEQ
+ * @{
+ */
+
+/*                                      Offset   Register Description
+                                        ======   ================================================= */
+typedef struct {
+    __IO uint32_t reg0;             /*  0x0000   Power Sequencer Control Register 0                */
+    __IO uint32_t reg1;             /*  0x0004   Power Sequencer Control Register 1                */
+    __IO uint32_t reg2;             /*  0x0008   Power Sequencer Control Register 2                */
+    __IO uint32_t reg3;             /*  0x000C   Power Sequencer Control Register 3                */
+    __IO uint32_t reg4;             /*  0x0010   Power Sequencer Control Register 4                */
+    __IO uint32_t reg5;             /*  0x0014   Power Sequencer Control Register 5 (Trim 0)       */
+    __IO uint32_t reg6;             /*  0x0018   Power Sequencer Control Register 6 (Trim 1)       */
+    __I uint32_t rsv001C;           /*  0x001C                                                     */
+    __IO uint32_t flags;            /*  0x0020   Power Sequencer Flags                             */
+    __IO uint32_t msk_flags;        /*  0x0024   Power Sequencer Flags Mask Register               */
+} mxc_pwrseq_regs_t;
+
+
+/*
+   Register offsets for module PWRSEQ.
+*/
+#define MXC_R_PWRSEQ_OFFS_REG0                    ((uint32_t)0x00000000UL)
+#define MXC_R_PWRSEQ_OFFS_REG1                    ((uint32_t)0x00000004UL)
+#define MXC_R_PWRSEQ_OFFS_REG2                    ((uint32_t)0x00000008UL)
+#define MXC_R_PWRSEQ_OFFS_REG3                    ((uint32_t)0x0000000CUL)
+#define MXC_R_PWRSEQ_OFFS_REG4                    ((uint32_t)0x00000010UL)
+#define MXC_R_PWRSEQ_OFFS_REG5                    ((uint32_t)0x00000014UL)
+#define MXC_R_PWRSEQ_OFFS_REG6                    ((uint32_t)0x00000018UL)
+#define MXC_R_PWRSEQ_OFFS_FLAGS                   ((uint32_t)0x00000020UL)
+#define MXC_R_PWRSEQ_OFFS_MSK_FLAGS               ((uint32_t)0x00000024UL)
+
+
+/*
+   Field positions and masks for module PWRSEQ.
+*/
+#define MXC_F_PWRSEQ_REG0_PWR_LP1_POS                       0
+#define MXC_F_PWRSEQ_REG0_PWR_LP1                           ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS                1
+#define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS                2
+#define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS                 3
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS                 4
+#define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS                5
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS                6
+#define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS                  7
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS                  8
+#define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS                  9
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS                  10
+#define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS                 11
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS                 12
+#define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS                13
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS                14
+#define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS                15
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS                16
+#define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS              17
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS              18
+#define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS))
+#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS                19
+#define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS))
+
+#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS                0
+#define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG                    ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS                  8
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS            9
+#define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS                  10
+#define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS              11
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS             12
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS             13
+#define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS))
+#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS               14
+#define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS))
+
+#define MXC_F_PWRSEQ_REG2_PWR_RST3_POS                      0
+#define MXC_F_PWRSEQ_REG2_PWR_RST3                          ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W3_POS                        5
+#define MXC_F_PWRSEQ_REG2_PWR_W3                            ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W1_POS                        10
+#define MXC_F_PWRSEQ_REG2_PWR_W1                            ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS                    15
+#define MXC_F_PWRSEQ_REG2_PWR_W1_LOW                        ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS                      20
+#define MXC_F_PWRSEQ_REG2_PWR_WRTC                          ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS))
+#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS                    25
+#define MXC_F_PWRSEQ_REG2_PWR_WVDDA3                        ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS))
+
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS                     0
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL                         ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS               3
+#define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK                   ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS                    5
+#define MXC_F_PWRSEQ_REG3_PWR_SVMSEL                        ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS            8
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO                ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS              10
+#define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL                  ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS               13
+#define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX                   ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS                15
+#define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS                 16
+#define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS))
+#define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS                     17
+#define MXC_F_PWRSEQ_REG3_PWR_BO_TC                         ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS))
+
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS              0
+#define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS            1
+#define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS             2
+#define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS              3
+#define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS           4
+#define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS               5
+#define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS))
+#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS               6
+#define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS))
+
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS               0
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG                   ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS               6
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8                   ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS               10
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3                   ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS))
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS             15
+#define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF                 ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS))
+
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS             0
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS                 ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS           3
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES               ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS           7
+#define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES               ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
+
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS               0
+#define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS               1
+#define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS             2
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS            3
+#define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS              4
+#define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS                5
+#define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS                 6
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS                7
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS                 8
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS             9
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS                10
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS                11
+#define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS               12
+#define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS                    13
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0                        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS                    14
+#define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1                        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS             15
+#define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS                 16
+#define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS             17
+#define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS          18
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS        19
+#define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS                20
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS))
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS               21
+#define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS))
+
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS           1
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS         2
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS        3
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS          4
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS            5
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS             6
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS            7
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS             8
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS         9
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS            10
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS            11
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS           12
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS                13
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS                14
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS         15
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS             16
+#define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS         17
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS      18
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP          ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS    19
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS            20
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS))
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS           21
+#define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_PWRSEQ_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/rtc_regs.h

@@ -0,0 +1,246 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_RTC_REGS_H
+#define _MXC_RTC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  rtc_regs.h
+ * @addtogroup rtc RTCTMR
+ * @{
+ */
+
+/**
+ * @brief Defines clock divider for 4096Hz input clock.
+ */
+typedef enum {
+    /** (4kHz) divide input clock by 2^0 = 1 */
+    MXC_E_RTC_PRESCALE_DIV_2_0 = 0,
+    /** (2kHz) divide input clock by 2^1 = 2 */
+    MXC_E_RTC_PRESCALE_DIV_2_1,
+    /** (1kHz) divide input clock by 2^2 = 4 */
+    MXC_E_RTC_PRESCALE_DIV_2_2,
+    /** (512Hz) divide input clock by 2^3 = 8 */
+    MXC_E_RTC_PRESCALE_DIV_2_3,
+    /** (256Hz) divide input clock by 2^4 = 16 */
+    MXC_E_RTC_PRESCALE_DIV_2_4,
+    /** (128Hz) divide input clock by 2^5 = 32 */
+    MXC_E_RTC_PRESCALE_DIV_2_5,
+    /** (64Hz) divide input clock by 2^6 = 64 */
+    MXC_E_RTC_PRESCALE_DIV_2_6,
+    /** (32Hz) divide input clock by 2^7 = 128 */
+    MXC_E_RTC_PRESCALE_DIV_2_7,
+    /** (16Hz) divide input clock by 2^8 = 256 */
+    MXC_E_RTC_PRESCALE_DIV_2_8,
+    /** (8Hz) divide input clock by 2^9 = 512 */
+    MXC_E_RTC_PRESCALE_DIV_2_9,
+    /** (4Hz) divide input clock by 2^10 = 1024 */
+    MXC_E_RTC_PRESCALE_DIV_2_10,
+    /** (2Hz) divide input clock by 2^11 = 2048 */
+    MXC_E_RTC_PRESCALE_DIV_2_11,
+    /** (1Hz) divide input clock by 2^12 = 4096 */
+    MXC_E_RTC_PRESCALE_DIV_2_12,
+} mxc_rtc_prescale_t;
+
+/*                                          Offset   Register Description
+                                            ======   ========================================= */
+typedef struct {
+    __IO uint32_t ctrl;                 /*  0x0000   RTC Timer Control                         */
+    __IO uint32_t timer;                /*  0x0004   RTC Timer Count Value                     */
+    __IO uint32_t comp[2];              /*  0x0008   RTC Alarm (0..1) Compare Registers        */
+    __IO uint32_t flags;                /*  0x0010   CPU Interrupt and RTC Domain Flags        */
+    __I uint32_t rsv0014;               /*  0x0014                                             */
+    __IO uint32_t inten;                /*  0x0018   Interrupt Enable Controls                 */
+    __IO uint32_t prescale;             /*  0x001C   RTC Timer Prescale Setting                */
+    __I uint32_t rsv0020;               /*  0x0020                                             */
+    __IO uint32_t prescale_mask;        /*  0x0024   RTC Timer Prescale Compare Mask           */
+    __IO uint32_t trim_ctrl;            /*  0x0028   RTC Timer Trim Controls                   */
+    __IO uint32_t trim_value;           /*  0x002C   RTC Timer Trim Adjustment Interval        */
+} mxc_rtctmr_regs_t;
+
+/*
+   Register offsets for module RTCTMR.
+*/
+#define MXC_R_RTCTMR_OFFS_CTRL                    ((uint32_t)0x00000000UL)
+#define MXC_R_RTCTMR_OFFS_TIMER                   ((uint32_t)0x00000004UL)
+#define MXC_R_RTCTMR_OFFS_COMP_0                  ((uint32_t)0x00000008UL)
+#define MXC_R_RTCTMR_OFFS_COMP_1                  ((uint32_t)0x0000000CUL)
+#define MXC_R_RTCTMR_OFFS_FLAGS                   ((uint32_t)0x00000010UL)
+#define MXC_R_RTCTMR_OFFS_INTEN                   ((uint32_t)0x00000018UL)
+#define MXC_R_RTCTMR_OFFS_PRESCALE                ((uint32_t)0x0000001CUL)
+#define MXC_R_RTCTMR_OFFS_PRESCALE_MASK           ((uint32_t)0x00000024UL)
+#define MXC_R_RTCTMR_OFFS_TRIM_CTRL               ((uint32_t)0x00000028UL)
+#define MXC_R_RTCTMR_OFFS_TRIM_VALUE              ((uint32_t)0x0000002CUL)
+
+/*
+   Field positions and masks for module RTCTMR.
+*/
+#define MXC_F_RTC_CTRL_ENABLE_POS                           0
+#define MXC_F_RTC_CTRL_ENABLE                               ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ENABLE_POS))
+#define MXC_F_RTC_CTRL_CLEAR_POS                            1
+#define MXC_F_RTC_CTRL_CLEAR                                ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLEAR_POS))
+#define MXC_F_RTC_CTRL_PENDING_POS                          2
+#define MXC_F_RTC_CTRL_PENDING                              ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PENDING_POS))
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS                  3
+#define MXC_F_RTC_CTRL_USE_ASYNC_FLAGS                      ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_USE_ASYNC_FLAGS_POS))
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS                   4
+#define MXC_F_RTC_CTRL_AGGRESSIVE_RST                       ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_AGGRESSIVE_RST_POS))
+#define MXC_F_RTC_CTRL_EN_ACTIVE_POS                        16
+#define MXC_F_RTC_CTRL_EN_ACTIVE                            ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_EN_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS              17
+#define MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE                  ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_GOTO_LOW_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS            18
+#define MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE                ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_SM_EN_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS               19
+#define MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE                   ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_OSC_FRCE_ST_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_SET_ACTIVE_POS                       20
+#define MXC_F_RTC_CTRL_SET_ACTIVE                           ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_SET_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CLR_ACTIVE_POS                       21
+#define MXC_F_RTC_CTRL_CLR_ACTIVE                           ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS              22
+#define MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE                  ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_ROLLOVER_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS            23
+#define MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE                ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_CMPR0_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS           24
+#define MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE               ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_PRESCALE_UPDATE_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS                 25
+#define MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE                     ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR1_CLR_ACTIVE_POS))
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS                 26
+#define MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE                     ((uint32_t)(0x00000001UL << MXC_F_RTC_CTRL_CMPR0_CLR_ACTIVE_POS))
+
+#define MXC_F_RTC_FLAGS_COMP0_POS                           0
+#define MXC_F_RTC_FLAGS_COMP0                               ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_POS))
+#define MXC_F_RTC_FLAGS_COMP1_POS                           1
+#define MXC_F_RTC_FLAGS_COMP1                               ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_POS))
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP_POS                   2
+#define MXC_F_RTC_FLAGS_PRESCALE_COMP                       ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCALE_COMP_POS))
+#define MXC_F_RTC_FLAGS_OVERFLOW_POS                        3
+#define MXC_F_RTC_FLAGS_OVERFLOW                            ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_POS))
+#define MXC_F_RTC_FLAGS_TRIM_POS                            4
+#define MXC_F_RTC_FLAGS_TRIM                                ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_POS))
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS                    8
+#define MXC_F_RTC_FLAGS_COMP0_FLAG_A                        ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP0_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS                    9
+#define MXC_F_RTC_FLAGS_COMP1_FLAG_A                        ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_COMP1_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS                   10
+#define MXC_F_RTC_FLAGS_PRESCL_FLAG_A                       ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_PRESCL_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS                 11
+#define MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A                     ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_OVERFLOW_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS                     12
+#define MXC_F_RTC_FLAGS_TRIM_FLAG_A                         ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_TRIM_FLAG_A_POS))
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS                 31
+#define MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS                     ((uint32_t)(0x00000001UL << MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS_POS))
+
+#define MXC_F_RTC_INTEN_COMP0_POS                           0
+#define MXC_F_RTC_INTEN_COMP0                               ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP0_POS))
+#define MXC_F_RTC_INTEN_COMP1_POS                           1
+#define MXC_F_RTC_INTEN_COMP1                               ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_COMP1_POS))
+#define MXC_F_RTC_INTEN_PRESCALE_COMP_POS                   2
+#define MXC_F_RTC_INTEN_PRESCALE_COMP                       ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_PRESCALE_COMP_POS))
+#define MXC_F_RTC_INTEN_OVERFLOW_POS                        3
+#define MXC_F_RTC_INTEN_OVERFLOW                            ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_OVERFLOW_POS))
+#define MXC_F_RTC_INTEN_TRIM_POS                            4
+#define MXC_F_RTC_INTEN_TRIM                                ((uint32_t)(0x00000001UL << MXC_F_RTC_INTEN_TRIM_POS))
+
+#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS              0
+#define MXC_F_RTC_PRESCALE_WIDTH_SELECTION                  ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_WIDTH_SELECTION_POS))
+
+#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS               0
+#define MXC_F_RTC_PRESCALE_MASK_COMP_MASK                   ((uint32_t)(0x0000000FUL << MXC_F_RTC_PRESCALE_MASK_COMP_MASK_POS))
+
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS               0
+#define MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R                   ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_ENABLE_R_POS))
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS           1
+#define MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R               ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_FASTER_OVR_R_POS))
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS               2
+#define MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R                   ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_CTRL_TRIM_SLOWER_R_POS))
+
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS                 0
+#define MXC_F_RTC_TRIM_VALUE_TRIM_VALUE                     ((uint32_t)(0x0003FFFFUL << MXC_F_RTC_TRIM_VALUE_TRIM_VALUE_POS))
+#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS               18
+#define MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL                   ((uint32_t)(0x00000001UL << MXC_F_RTC_TRIM_VALUE_TRIM_CONTROL_POS))
+
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS            0
+#define MXC_F_RTC_NANO_CNTR_NANORING_COUNTER                ((uint32_t)(0x0000FFFFUL << MXC_F_RTC_NANO_CNTR_NANORING_COUNTER_POS))
+
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN_POS                      0
+#define MXC_F_RTC_CLK_CTRL_OSC1_EN                          ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC1_EN_POS))
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN_POS                      1
+#define MXC_F_RTC_CLK_CTRL_OSC2_EN                          ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_OSC2_EN_POS))
+#define MXC_F_RTC_CLK_CTRL_NANO_EN_POS                      2
+#define MXC_F_RTC_CLK_CTRL_NANO_EN                          ((uint32_t)(0x00000001UL << MXC_F_RTC_CLK_CTRL_NANO_EN_POS))
+
+#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS                0
+#define MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE                    ((uint32_t)(0x00000001UL << MXC_F_RTC_DSEN_CTRL_DSEN_DISABLE_POS))
+
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS                   0
+#define MXC_F_RTC_OSC_CTRL_OSC_BYPASS                       ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_BYPASS_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS                1
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R                    ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_R_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS              2
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL                  ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_SEL_POS))
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS                3
+#define MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O                    ((uint32_t)(0x00000001UL << MXC_F_RTC_OSC_CTRL_OSC_DISABLE_O_POS))
+
+/*                                      Offset   Register Description
+                                        ======   ===================================================================== */
+typedef struct {
+    __IO uint32_t nano_counter;     /*  0x0000   Nanoring Counter Read Register                                        */
+    __IO uint32_t clk_ctrl;         /*  0x0004   RTC Clock Control Settings                                            */
+    __IO uint32_t dsen_ctrl;        /*  0x0008   Dynamic Tamper Sensor Control                                         */
+    __IO uint32_t osc_ctrl;         /*  0x000C   RTC Oscillator Control                                                */
+} mxc_rtccfg_regs_t;
+
+/*
+   Register offsets for module RTCCFG.
+*/
+#define MXC_R_RTCCFG_OFFS_NANO_COUNTER            ((uint32_t)0x00000000UL)
+#define MXC_R_RTCCFG_OFFS_CLK_CTRL                ((uint32_t)0x00000004UL)
+#define MXC_R_RTCCFG_OFFS_DSEN_CTRL               ((uint32_t)0x00000008UL)
+#define MXC_R_RTCCFG_OFFS_OSC_CTRL                ((uint32_t)0x0000000CUL)
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_RTC_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/spi_regs.h

@@ -0,0 +1,215 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_SPI_REGS_H
+#define _MXC_SPI_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  spi_regs.h
+ * @addtogroup spi SPI
+ * @{
+ */
+
+/*                                       Offset   Register Description
+                                         ======   ============================================ */
+typedef struct {
+    __IO uint32_t mstr_cfg;          /*  0x0000   SPI Master Configuration Register            */
+    __IO uint32_t ss_sr_polarity;    /*  0x0004   Polarity Control for SS and SR Signals       */
+    __IO uint32_t gen_ctrl;          /*  0x0008   SPI Master General Control Register          */
+    __IO uint32_t fifo_ctrl;         /*  0x000C   SPI Master FIFO Control Register             */
+    __IO uint32_t spcl_ctrl;         /*  0x0010   SPI Master Special Mode Controls             */
+    __IO uint32_t intfl;             /*  0x0014   SPI Master Interrupt Flags                   */
+    __IO uint32_t inten;             /*  0x0018   SPI Master Interrupt Enable/Disable Settings */
+    __I uint32_t rsv001C;            /*  0x001C   Deprecated - was SPI_AHB_RETRY               */
+} mxc_spi_regs_t;
+
+/**
+ * @brief TX FIFO register. Can do 8, 16, or 32 bit access.
+ */
+typedef struct {
+    union {
+        __O uint8_t txfifo_8;
+        __O uint16_t txfifo_16;
+        __O uint32_t txfifo_32;
+    };
+} mxc_spi_txfifo_regs_t;
+
+/**
+ * @brief RX FIFO register. Can do 8, 16, or 32 bit access.
+ */
+typedef struct {
+    union {
+        __I uint8_t rxfifo_8;
+        __I uint16_t rxfifo_16;
+        __I uint32_t rxfifo_32;
+    };
+} mxc_spi_rxfifo_regs_t;
+
+/*
+   Register offsets for module SPI.
+*/
+#define MXC_R_SPI_OFFS_MSTR_CFG                   ((uint32_t)0x00000000UL)
+#define MXC_R_SPI_OFFS_SS_SR_POLARITY             ((uint32_t)0x00000004UL)
+#define MXC_R_SPI_OFFS_GEN_CTRL                   ((uint32_t)0x00000008UL)
+#define MXC_R_SPI_OFFS_FIFO_CTRL                  ((uint32_t)0x0000000CUL)
+#define MXC_R_SPI_OFFS_SPCL_CTRL                  ((uint32_t)0x00000010UL)
+#define MXC_R_SPI_OFFS_INTFL                      ((uint32_t)0x00000014UL)
+#define MXC_R_SPI_OFFS_INTEN                      ((uint32_t)0x00000018UL)
+
+#define MXC_R_SPI_FIFO_OFFS_TRANS                 ((uint32_t)0x00000000UL)
+#define MXC_R_SPI_FIFO_OFFS_RSLTS                 ((uint32_t)0x00000800UL)
+
+/*
+   Field positions and masks for module SPI.
+*/
+#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS                    0
+#define MXC_F_SPI_MSTR_CFG_SLAVE_SEL                        ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS))
+#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS              3
+#define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE                  ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS))
+#define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS                     4
+#define MXC_F_SPI_MSTR_CFG_SPI_MODE                         ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS))
+#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS                    6
+#define MXC_F_SPI_MSTR_CFG_PAGE_SIZE                        ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS))
+#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS                   8
+#define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK                       ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS                   12
+#define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK                       ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS                    16
+#define MXC_F_SPI_MSTR_CFG_ACT_DELAY                        ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS))
+#define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS                  18
+#define MXC_F_SPI_MSTR_CFG_INACT_DELAY                      ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS))
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS               20
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK                   ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS))
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS               24
+#define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK                   ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS))
+
+#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS            0
+#define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY                ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS))
+#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS            8
+#define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY                ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS))
+
+#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS                  0
+#define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN                      ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS                   1
+#define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN                       ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS                   2
+#define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN                       ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS))
+#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS                3
+#define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE                    ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS                 4
+#define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT                     ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS                     5
+#define MXC_F_SPI_GEN_CTRL_BB_SR_IN                         ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS                6
+#define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT                    ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS                   8
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN                       ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS                  12
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT                      ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS))
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS                16
+#define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN                    ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS))
+
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS              0
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL                  ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS                8
+#define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED                    ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS))
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS              16
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL                  ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS                24
+#define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED                    ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS))
+
+#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS              0
+#define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE                  ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS))
+#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS                  1
+#define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN                      ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS))
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS              4
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT                  ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS            8
+#define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN                ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
+
+#define MXC_F_SPI_INTFL_TX_STALLED_POS                      0
+#define MXC_F_SPI_INTFL_TX_STALLED                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS))
+#define MXC_F_SPI_INTFL_RX_STALLED_POS                      1
+#define MXC_F_SPI_INTFL_RX_STALLED                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS))
+#define MXC_F_SPI_INTFL_TX_READY_POS                        2
+#define MXC_F_SPI_INTFL_TX_READY                            ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS))
+#define MXC_F_SPI_INTFL_RX_DONE_POS                         3
+#define MXC_F_SPI_INTFL_RX_DONE                             ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS))
+#define MXC_F_SPI_INTFL_TX_FIFO_AE_POS                      4
+#define MXC_F_SPI_INTFL_TX_FIFO_AE                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS))
+#define MXC_F_SPI_INTFL_RX_FIFO_AF_POS                      5
+#define MXC_F_SPI_INTFL_RX_FIFO_AF                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS))
+
+#define MXC_F_SPI_INTEN_TX_STALLED_POS                      0
+#define MXC_F_SPI_INTEN_TX_STALLED                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS))
+#define MXC_F_SPI_INTEN_RX_STALLED_POS                      1
+#define MXC_F_SPI_INTEN_RX_STALLED                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS))
+#define MXC_F_SPI_INTEN_TX_READY_POS                        2
+#define MXC_F_SPI_INTEN_TX_READY                            ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS))
+#define MXC_F_SPI_INTEN_RX_DONE_POS                         3
+#define MXC_F_SPI_INTEN_RX_DONE                             ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS))
+#define MXC_F_SPI_INTEN_TX_FIFO_AE_POS                      4
+#define MXC_F_SPI_INTEN_TX_FIFO_AE                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS))
+#define MXC_F_SPI_INTEN_RX_FIFO_AF_POS                      5
+#define MXC_F_SPI_INTEN_RX_FIFO_AF                          ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS))
+
+#define MXC_F_SPI_FIFO_DIR_POS                              0
+#define MXC_F_SPI_FIFO_DIR                                  ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS))
+#define MXC_F_SPI_FIFO_UNIT_POS                             2
+#define MXC_F_SPI_FIFO_UNIT                                 ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS))
+#define MXC_F_SPI_FIFO_SIZE_POS                             4
+#define MXC_F_SPI_FIFO_SIZE                                 ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS))
+#define MXC_F_SPI_FIFO_WIDTH_POS                            9
+#define MXC_F_SPI_FIFO_WIDTH                                ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS))
+#define MXC_F_SPI_FIFO_ALT_POS                              11
+#define MXC_F_SPI_FIFO_ALT                                  ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS))
+#define MXC_F_SPI_FIFO_FLOW_POS                             12
+#define MXC_F_SPI_FIFO_FLOW                                 ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS))
+#define MXC_F_SPI_FIFO_DASS_POS                             13
+#define MXC_F_SPI_FIFO_DASS                                 ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_SPI_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.c

@@ -0,0 +1,144 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "max32600.h"
+#include "clkman_regs.h"
+#include "pwrman_regs.h"
+#include "ioman_regs.h"
+#include "trim_regs.h"
+#include "flc_regs.h"
+#include "pwrseq_regs.h"
+#include "dac_regs.h"
+#include "icc_regs.h"
+
+/* Application developer should override where necessary with different external HFX source */
+#ifndef __SYSTEM_HFX
+#define __SYSTEM_HFX 8000000
+#endif
+
+uint32_t SystemCoreClock = 24000000;
+
+void SystemCoreClockUpdate(void)
+{
+    switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
+        case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8:
+            SystemCoreClock = 3000000;
+            break;
+        case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO:
+        case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2:
+            SystemCoreClock = 24000000;
+            break;
+        case MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX:
+            SystemCoreClock = __SYSTEM_HFX;
+            break;
+    }
+
+    uint32_t shift = MXC_CLKMAN->clk_ctrl_0_system;
+    if (shift) {
+        SystemCoreClock = SystemCoreClock >> (shift - 1);
+    }
+}
+
+/* power seq registers */
+static void set_pwr_regs(void)
+{
+    uint32_t dac2trim =  MXC_DAC2->reg & 0xff00ffff;
+    uint32_t dac3trim =  MXC_DAC3->reg & 0xff00ffff;
+    dac2trim = dac2trim + MXC_TRIM->trim_reg_36;
+    dac3trim = dac3trim + MXC_TRIM->trim_reg_37;
+    MXC_PWRSEQ->reg5 = MXC_TRIM->trim_reg_13;
+    MXC_PWRSEQ->reg6 = MXC_TRIM->trim_reg_14;
+    MXC_DAC0->trm = MXC_TRIM->trim_reg_34;
+    MXC_DAC1->trm = MXC_TRIM->trim_reg_35;
+    MXC_DAC2->reg = dac2trim;
+    MXC_DAC3->reg = dac3trim;
+}
+
+void ICC_Enable(void)
+{
+    /* clock gater must be 'on' not 'dynamic' for cache control */
+    uint32_t temp = MXC_CLKMAN->clk_gate_ctrl0;
+    temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
+    temp |= (MXC_E_CLKMAN_CLK_GATE_ON << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
+    MXC_CLKMAN->clk_gate_ctrl0 = temp;
+
+
+    /* invalidate, wait, enable */
+    MXC_ICC->invdt_all = 0xFFFF;
+    while(!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
+    MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
+
+    /* must invalidate a second time for proper use */
+    MXC_ICC->invdt_all = 1;
+
+    /* clock gater 'dynamic' safe again */
+    temp = MXC_CLKMAN->clk_gate_ctrl0;
+    temp &= ~MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER;
+    temp |= (MXC_E_CLKMAN_CLK_GATE_DYNAMIC << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS);
+    MXC_CLKMAN->clk_gate_ctrl0 = temp;
+}
+
+// This function to be implemented by the hal
+extern void low_level_init(void);
+
+void SystemInit(void)
+{
+    set_pwr_regs();
+
+    // enable instruction cache
+    ICC_Enable();
+
+    low_level_init();
+
+    // Clear IO Active
+    MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE);
+
+    // Set WUD Clear
+    MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR);
+
+    // Set IO Active
+    MXC_PWRMAN->pwr_rst_ctrl = (MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE |
+                                MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED);
+
+    MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN;
+
+    // set systick to the RTC input 32.768kHz clock, not system clock; this is needed to keep JTAG alive during sleep
+    MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
+
+    SystemCoreClockUpdate();
+}

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/system_max32600.h

@@ -0,0 +1,53 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef SYSTEM_MAX32600_H_
+#define SYSTEM_MAX32600_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+extern void SystemInit (void);
+
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_MAX32600_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tmr_regs.h

@@ -0,0 +1,146 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TMR_REGS_H
+#define _MXC_TMR_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  tmr_regs.h
+ * @addtogroup tmr TMR
+ * @{
+ */
+
+/**
+ * @brief Defines timer modes for 16 and 32-bit timers
+ */
+typedef enum {
+    /** 32-bit or 16-bit timer one-shot mode */
+    MXC_E_TMR_MODE_ONE_SHOT = 0,
+    /** 32-bit or 16-bit timer one-shot mode */
+    MXC_E_TMR_MODE_CONTINUOUS,
+    /** 32-bit timer counter mode */
+    MXC_E_TMR_MODE_COUNTER,
+    /** 32-bit timer pulse width modulation mode */
+    MXC_E_TMR_MODE_PWM,
+    /** 32-bit timer capture mode */
+    MXC_E_TMR_MODE_CAPTURE,
+    /** 32-bit timer compare mode */
+    MXC_E_TMR_MODE_COMPARE,
+    /** 32-bit timer gated mode */
+    MXC_E_TMR_MODE_GATED,
+    /** 32-bit timer measure mode */
+    MXC_E_TMR_MODE_MEASURE
+} mxc_tmr_mode_t;
+
+/*                                          Offset   Register Description
+                                            ======   ============================================== */
+typedef struct {
+    __IO uint32_t ctrl;                 /*  0x0000   Timer Control Register                         */
+    __IO uint32_t count32;              /*  0x0004   [32 bit] Current Count Value                   */
+    __IO uint32_t term_cnt32;           /*  0x0008   [32 bit] Terminal Count Setting                */
+    __IO uint32_t pwm_cap32;            /*  0x000C   [32 bit] PWM Compare Setting or Capture/Measure Value */
+    __IO uint32_t count16_0;            /*  0x0010   [16 bit] Current Count Value, 16-bit Timer0    */
+    __IO uint32_t term_cnt16_0;         /*  0x0014   [16 bit] Terminal Count Setting, 16-bit Timer0 */
+    __IO uint32_t count16_1;            /*  0x0018   [16 bit] Current Count Value, 16-bit Timer1    */
+    __IO uint32_t term_cnt16_1;         /*  0x001C   [16 bit] Terminal Count Setting, 16-bit Timer1 */
+    __IO uint32_t intfl;                /*  0x0020   Timer Module Interrupt Flags                   */
+    __IO uint32_t inten;                /*  0x0024   Timer Module Interrupt Enable/Disable Settings */
+} mxc_tmr_regs_t;
+
+/*
+   Register offsets for module TMR.
+*/
+#define MXC_R_TMR_OFFS_CTRL                       ((uint32_t)0x00000000UL)
+#define MXC_R_TMR_OFFS_COUNT32                    ((uint32_t)0x00000004UL)
+#define MXC_R_TMR_OFFS_TERM_CNT32                 ((uint32_t)0x00000008UL)
+#define MXC_R_TMR_OFFS_PWM_CAP32                  ((uint32_t)0x0000000CUL)
+#define MXC_R_TMR_OFFS_COUNT16_0                  ((uint32_t)0x00000010UL)
+#define MXC_R_TMR_OFFS_TERM_CNT16_0               ((uint32_t)0x00000014UL)
+#define MXC_R_TMR_OFFS_COUNT16_1                  ((uint32_t)0x00000018UL)
+#define MXC_R_TMR_OFFS_TERM_CNT16_1               ((uint32_t)0x0000001CUL)
+#define MXC_R_TMR_OFFS_INTFL                      ((uint32_t)0x00000020UL)
+#define MXC_R_TMR_OFFS_INTEN                      ((uint32_t)0x00000024UL)
+
+/*
+   Field positions and masks for module TMR.
+*/
+#define MXC_F_TMR_CTRL_MODE_POS                             0
+#define MXC_F_TMR_CTRL_MODE                                 ((uint32_t)(0x00000007UL << MXC_F_TMR_CTRL_MODE_POS))
+#define MXC_F_TMR_CTRL_TMR2X16_POS                          3
+#define MXC_F_TMR_CTRL_TMR2X16                              ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_TMR2X16_POS))
+#define MXC_F_TMR_CTRL_PRESCALE_POS                         4
+#define MXC_F_TMR_CTRL_PRESCALE                             ((uint32_t)(0x0000000FUL << MXC_F_TMR_CTRL_PRESCALE_POS))
+#define MXC_F_TMR_CTRL_POLARITY_POS                         8
+#define MXC_F_TMR_CTRL_POLARITY                             ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_POLARITY_POS))
+#define MXC_F_TMR_CTRL_ENABLE0_POS                          12
+#define MXC_F_TMR_CTRL_ENABLE0                              ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE0_POS))
+#define MXC_F_TMR_CTRL_ENABLE1_POS                          13
+#define MXC_F_TMR_CTRL_ENABLE1                              ((uint32_t)(0x00000001UL << MXC_F_TMR_CTRL_ENABLE1_POS))
+
+#define MXC_F_TMR_COUNT16_0_VALUE_POS                       0
+#define MXC_F_TMR_COUNT16_0_VALUE                           ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_0_VALUE_POS))
+
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS               0
+#define MXC_F_TMR_TERM_CNT16_0_TERM_COUNT                   ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_0_TERM_COUNT_POS))
+
+#define MXC_F_TMR_COUNT16_1_VALUE_POS                       0
+#define MXC_F_TMR_COUNT16_1_VALUE                           ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_COUNT16_1_VALUE_POS))
+
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS               0
+#define MXC_F_TMR_TERM_CNT16_1_TERM_COUNT                   ((uint32_t)(0x0000FFFFUL << MXC_F_TMR_TERM_CNT16_1_TERM_COUNT_POS))
+
+#define MXC_F_TMR_INTFL_TIMER0_POS                          0
+#define MXC_F_TMR_INTFL_TIMER0                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER0_POS))
+#define MXC_F_TMR_INTFL_TIMER1_POS                          1
+#define MXC_F_TMR_INTFL_TIMER1                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTFL_TIMER1_POS))
+
+#define MXC_F_TMR_INTEN_TIMER0_POS                          0
+#define MXC_F_TMR_INTEN_TIMER0                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER0_POS))
+#define MXC_F_TMR_INTEN_TIMER1_POS                          1
+#define MXC_F_TMR_INTEN_TIMER1                              ((uint32_t)(0x00000001UL << MXC_F_TMR_INTEN_TIMER1_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_TMR_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h

@@ -0,0 +1,108 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TPU_REGS_H_
+#define _MXC_TPU_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  tpu_regs.h
+ * @addtogroup tpu TPU
+ * @{
+ */
+
+/*                                               Offset   Register Description
+                                                 ======   ================================================== */
+typedef struct {
+    __I uint32_t rsv0000;                    /*  0x0000   Reserved                                          */
+    __I uint32_t rsv0004;                    /*  0x0004   Reserved - PUF Control (Deprecated)               */
+    __I uint32_t rsv0008;                    /*  0x0008   Reserved - PUF Output (Deprecated)                */
+    __I uint32_t rsv000C[125];               /*  0x000C                                                     */
+    __IO uint32_t prng_user_entropy;         /*  0x0200   PRNG User Entropy Value                           */
+    __IO uint32_t prng_rnd_num;              /*  0x0204   PRNG Random Number Output                         */
+} mxc_tpu_regs_t;
+
+/*                                               Offset   Register Description
+                                                 ======   ================================================= */
+typedef struct {
+    __IO uint32_t status;                    /*  0x0000   Dynamic Tamper Sensor Status                      */
+    __IO uint32_t ctrl0;                     /*  0x0004   Dynamic Tamper Sensor Control 0                   */
+    __IO uint32_t ctrl1;                     /*  0x0008   Dynamic Tamper Sensor Control 1                   */
+    __IO uint32_t sks0;                      /*  0x0010   TPU Secure Key Storage Register 0                 */
+    __IO uint32_t sks1;                      /*  0x0014   TPU Secure Key Storage Register 0                 */
+    __IO uint32_t sks2;                      /*  0x0018   TPU Secure Key Storage Register 0                 */
+    __IO uint32_t sks3;                      /*  0x001C   TPU Secure Key Storage Register 0                 */
+} mxc_tpu_tsr_regs_t;
+
+/*
+   Register offsets for module TPU.
+*/
+#define MXC_R_TPU_OFFS_PRNG_USER_ENTROPY    ((uint32_t)0x00000200UL)
+#define MXC_R_TPU_OFFS_PRNG_RND_NUM         ((uint32_t)0x00000204UL)
+#define MXC_R_TPU_TSR_OFFS_STATUS           ((uint32_t)0x00000000UL)
+#define MXC_R_TPU_TSR_OFFS_CTRL0            ((uint32_t)0x00000004UL)
+#define MXC_R_TPU_TSR_OFFS_CTRL1            ((uint32_t)0x00000008UL)
+#define MXC_R_TPU_TSR_OFFS_SKS0             ((uint32_t)0x00000010UL)
+#define MXC_R_TPU_TSR_OFFS_SKS1             ((uint32_t)0x00000014UL)
+#define MXC_R_TPU_TSR_OFFS_SKS2             ((uint32_t)0x00000018UL)
+#define MXC_R_TPU_TSR_OFFS_SKS3             ((uint32_t)0x0000001CUL)
+
+
+/*
+   Field positions and masks for module TPU.
+*/
+#define MXC_F_TPU_CTRL0_ERR_THR_POS         0
+#define MXC_F_TPU_CTRL0_ERR_THR             ((uint32_t)(0x0000001FUL << MXC_F_TPU_CTRL0_ERR_THR_POS))
+#define MXC_F_TPU_CTRL0_OUT_FREQ_POS        5
+#define MXC_F_TPU_CTRL0_OUT_FREQ            ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_OUT_FREQ_POS))
+#define MXC_F_TPU_CTRL0_CLOCK_DIV_POS       8
+#define MXC_F_TPU_CTRL0_CLOCK_DIV           ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_CLOCK_DIV_POS))
+#define MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS     14
+#define MXC_F_TPU_CTRL0_RTC_TX_BUSY         ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS))
+#define MXC_F_TPU_CTRL0_LOCK_POS            15
+#define MXC_F_TPU_CTRL0_LOCK                ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_LOCK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_TPU_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/trim_regs.h

@@ -0,0 +1,92 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_TRIM_REGS_H
+#define _MXC_TRIM_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+typedef struct {
+    __IO uint32_t trim_reg_00;
+    __IO uint32_t trim_reg_01;
+    __IO uint32_t trim_reg_02;
+    __IO uint32_t trim_reg_03;
+    __IO uint32_t trim_reg_04;
+    __IO uint32_t trim_reg_05;
+    __IO uint32_t trim_reg_06;
+    __IO uint32_t trim_reg_07;
+    __IO uint32_t trim_reg_08;
+    __IO uint32_t trim_reg_09;
+    __IO uint32_t trim_reg_10;
+    __IO uint32_t trim_reg_11;
+    __IO uint32_t trim_reg_12;
+    __IO uint32_t trim_reg_13;
+    __IO uint32_t trim_reg_14;
+    __IO uint32_t trim_reg_15;
+    __IO uint32_t trim_reg_16;
+    __IO uint32_t trim_reg_17;
+    __IO uint32_t trim_reg_18;
+    __IO uint32_t trim_reg_19;
+    __IO uint32_t trim_reg_20;
+    __IO uint32_t trim_reg_21;
+    __IO uint32_t trim_reg_22;
+    __IO uint32_t trim_reg_23;
+    __IO uint32_t trim_reg_24;
+    __IO uint32_t trim_reg_25;
+    __IO uint32_t trim_reg_26;
+    __IO uint32_t trim_reg_27;
+    __IO uint32_t trim_reg_28;
+    __IO uint32_t trim_reg_29;
+    __IO uint32_t trim_reg_30;
+    __IO uint32_t trim_reg_31;
+    __IO uint32_t trim_reg_32;
+    __IO uint32_t trim_reg_33;
+    __IO uint32_t trim_reg_34;
+    __IO uint32_t trim_reg_35;
+    __IO uint32_t trim_reg_36;
+    __IO uint32_t trim_reg_37;
+    __IO uint32_t trim_reg_38;
+    __IO uint32_t trim_reg_39;
+    __IO uint32_t trim_reg_40;
+    __IO uint32_t trim_reg_41;
+} mxc_ftr_regs_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_TRIM_REGS_H */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/uart_regs.h

@@ -0,0 +1,175 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_UART_REGS_H_
+#define _MXC_UART_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  uart_regs.h
+ * @addtogroup uart UART
+ * @{
+ */
+
+/*                                      Offset   Register Description
+                                        ======   ============================================== */
+typedef struct {
+    __IO uint32_t ctrl;             /*  0x0000   UART Control Register                          */
+    __IO uint32_t status;           /*  0x0004   UART Status Register                           */
+    __IO uint32_t inten;            /*  0x0008   Interrupt Enable/Disable Controls              */
+    __IO uint32_t intfl;            /*  0x000C   Interrupt Flags                                */
+    __IO uint32_t baud_int;         /*  0x0010   Baud Rate Setting (Integer Portion)            */
+    __IO uint32_t baud_div_128;     /*  0x0014   Baud Rate Setting                              */
+    __IO uint32_t tx_fifo_out;      /*  0x0018   TX FIFO Output End (read-only)                 */
+    __IO uint32_t hw_flow_ctrl;     /*  0x001C   Hardware Flow Control Register                 */
+    __IO uint32_t tx_rx_fifo;       /*  0x0020   Write to load TX FIFO, Read to unload RX FIFO  */
+} mxc_uart_regs_t;
+
+
+/*
+    Register offsets for module UART.
+*/
+#define MXC_R_UART_OFFS_CTRL                      ((uint32_t)0x00000000UL)
+#define MXC_R_UART_OFFS_STATUS                    ((uint32_t)0x00000004UL)
+#define MXC_R_UART_OFFS_INTEN                     ((uint32_t)0x00000008UL)
+#define MXC_R_UART_OFFS_INTFL                     ((uint32_t)0x0000000CUL)
+#define MXC_R_UART_OFFS_BAUD_INT                  ((uint32_t)0x00000010UL)
+#define MXC_R_UART_OFFS_BAUD_DIV_128              ((uint32_t)0x00000014UL)
+#define MXC_R_UART_OFFS_TX_FIFO_OUT               ((uint32_t)0x00000018UL)
+#define MXC_R_UART_OFFS_HW_FLOW_CTRL              ((uint32_t)0x0000001CUL)
+#define MXC_R_UART_OFFS_TX_RX_FIFO                ((uint32_t)0x00000020UL)
+
+/*
+   Field positions and masks for module UART.
+*/
+#define MXC_F_UART_CTRL_RX_THRESHOLD_POS                    0
+#define MXC_F_UART_CTRL_RX_THRESHOLD                        ((uint32_t)(0x00000007UL << MXC_F_UART_CTRL_RX_THRESHOLD_POS))
+#define MXC_F_UART_CTRL_PARITY_ENABLE_POS                   4
+#define MXC_F_UART_CTRL_PARITY_ENABLE                       ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_ENABLE_POS))
+#define MXC_F_UART_CTRL_PARITY_MODE_POS                     5
+#define MXC_F_UART_CTRL_PARITY_MODE                         ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_MODE_POS))
+#define MXC_F_UART_CTRL_PARITY_BIAS_POS                     6
+#define MXC_F_UART_CTRL_PARITY_BIAS                         ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_PARITY_BIAS_POS))
+#define MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS                   8
+#define MXC_F_UART_CTRL_TX_FIFO_FLUSH                       ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_TX_FIFO_FLUSH_POS))
+#define MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS                   9
+#define MXC_F_UART_CTRL_RX_FIFO_FLUSH                       ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_RX_FIFO_FLUSH_POS))
+#define MXC_F_UART_CTRL_CHAR_LENGTH_POS                     10
+#define MXC_F_UART_CTRL_CHAR_LENGTH                         ((uint32_t)(0x00000003UL << MXC_F_UART_CTRL_CHAR_LENGTH_POS))
+#define MXC_F_UART_CTRL_STOP_BIT_MODE_POS                   12
+#define MXC_F_UART_CTRL_STOP_BIT_MODE                       ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_STOP_BIT_MODE_POS))
+#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS                 13
+#define MXC_F_UART_CTRL_HW_FLOW_CTRL_EN                     ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_HW_FLOW_CTRL_EN_POS))
+#define MXC_F_UART_CTRL_BAUD_CLK_EN_POS                     14
+#define MXC_F_UART_CTRL_BAUD_CLK_EN                         ((uint32_t)(0x00000001UL << MXC_F_UART_CTRL_BAUD_CLK_EN_POS))
+
+#define MXC_F_UART_STATUS_TX_BUSY_POS                       0
+#define MXC_F_UART_STATUS_TX_BUSY                           ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_BUSY_POS))
+#define MXC_F_UART_STATUS_RX_BUSY_POS                       1
+#define MXC_F_UART_STATUS_RX_BUSY                           ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_BUSY_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS                 4
+#define MXC_F_UART_STATUS_RX_FIFO_EMPTY                     ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_EMPTY_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_FULL_POS                  5
+#define MXC_F_UART_STATUS_RX_FIFO_FULL                      ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_RX_FIFO_FULL_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS                 6
+#define MXC_F_UART_STATUS_TX_FIFO_EMPTY                     ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_EMPTY_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_FULL_POS                  7
+#define MXC_F_UART_STATUS_TX_FIFO_FULL                      ((uint32_t)(0x00000001UL << MXC_F_UART_STATUS_TX_FIFO_FULL_POS))
+#define MXC_F_UART_STATUS_RX_FIFO_CHARS_POS                 8
+#define MXC_F_UART_STATUS_RX_FIFO_CHARS                     ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_RX_FIFO_CHARS_POS))
+#define MXC_F_UART_STATUS_TX_FIFO_CHARS_POS                 12
+#define MXC_F_UART_STATUS_TX_FIFO_CHARS                     ((uint32_t)(0x0000000FUL << MXC_F_UART_STATUS_TX_FIFO_CHARS_POS))
+
+#define MXC_F_UART_INTEN_RX_FRAME_ERROR_POS                 0
+#define MXC_F_UART_INTEN_RX_FRAME_ERROR                     ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_FRAME_ERROR_POS))
+#define MXC_F_UART_INTEN_RX_PARITY_ERROR_POS                1
+#define MXC_F_UART_INTEN_RX_PARITY_ERROR                    ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_PARITY_ERROR_POS))
+#define MXC_F_UART_INTEN_CTS_CHANGE_POS                     2
+#define MXC_F_UART_INTEN_CTS_CHANGE                         ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_CTS_CHANGE_POS))
+#define MXC_F_UART_INTEN_RX_OVERRUN_POS                     3
+#define MXC_F_UART_INTEN_RX_OVERRUN                         ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVERRUN_POS))
+#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS              4
+#define MXC_F_UART_INTEN_RX_OVER_THRESHOLD                  ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_RX_OVER_THRESHOLD_POS))
+#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS                5
+#define MXC_F_UART_INTEN_TX_ALMOST_EMPTY                    ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_ALMOST_EMPTY_POS))
+#define MXC_F_UART_INTEN_TX_HALF_EMPTY_POS                  6
+#define MXC_F_UART_INTEN_TX_HALF_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_UART_INTEN_TX_HALF_EMPTY_POS))
+
+#define MXC_F_UART_INTFL_RX_FRAME_ERROR_POS                 0
+#define MXC_F_UART_INTFL_RX_FRAME_ERROR                     ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_FRAME_ERROR_POS))
+#define MXC_F_UART_INTFL_RX_PARITY_ERROR_POS                1
+#define MXC_F_UART_INTFL_RX_PARITY_ERROR                    ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_PARITY_ERROR_POS))
+#define MXC_F_UART_INTFL_CTS_CHANGE_POS                     2
+#define MXC_F_UART_INTFL_CTS_CHANGE                         ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_CTS_CHANGE_POS))
+#define MXC_F_UART_INTFL_RX_OVERRUN_POS                     3
+#define MXC_F_UART_INTFL_RX_OVERRUN                         ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVERRUN_POS))
+#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS              4
+#define MXC_F_UART_INTFL_RX_OVER_THRESHOLD                  ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_RX_OVER_THRESHOLD_POS))
+#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS                5
+#define MXC_F_UART_INTFL_TX_ALMOST_EMPTY                    ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_ALMOST_EMPTY_POS))
+#define MXC_F_UART_INTFL_TX_HALF_EMPTY_POS                  6
+#define MXC_F_UART_INTFL_TX_HALF_EMPTY                      ((uint32_t)(0x00000001UL << MXC_F_UART_INTFL_TX_HALF_EMPTY_POS))
+
+#define MXC_F_UART_BAUD_INT_FBAUD_POS                       0
+#define MXC_F_UART_BAUD_INT_FBAUD                           ((uint32_t)(0x00000FFFUL << MXC_F_UART_BAUD_INT_FBAUD_POS))
+
+#define MXC_F_UART_BAUD_DIV_128_DIV_POS                     0
+#define MXC_F_UART_BAUD_DIV_128_DIV                         ((uint32_t)(0x0000007FUL << MXC_F_UART_BAUD_DIV_128_DIV_POS))
+
+#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS                  0
+#define MXC_F_UART_TX_FIFO_OUT_TX_FIFO                      ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_FIFO_OUT_TX_FIFO_POS))
+
+#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS               0
+#define MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT                   ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_CTS_INPUT_POS))
+#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS              1
+#define MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT                  ((uint32_t)(0x00000001UL << MXC_F_UART_HW_FLOW_CTRL_RTS_OUTPUT_POS))
+
+#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS                 0
+#define MXC_F_UART_TX_RX_FIFO_FIFO_DATA                     ((uint32_t)(0x000000FFUL << MXC_F_UART_TX_RX_FIFO_FIFO_DATA_POS))
+#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS              8
+#define MXC_F_UART_TX_RX_FIFO_PARITY_ERROR                  ((uint32_t)(0x00000001UL << MXC_F_UART_TX_RX_FIFO_PARITY_ERROR_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_UART_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/usb_regs.h

@@ -0,0 +1,480 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_USB_REGS_H_
+#define _MXC_USB_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  usb_regs.h
+ * @addtogroup usb USB
+ * @{
+ */
+
+/*                                                Offset   Register Description
+                                                  ======   ================================================ */
+typedef struct {
+    __IO uint32_t cn;                         /*  0x0000   USB Control Register                             */
+    __I uint32_t rsv0004[127];                /*  0x0004                                                    */
+    __IO uint32_t dev_addr;                   /*  0x0200   USB Device Address Register                      */
+    __IO uint32_t dev_cn;                     /*  0x0204   USB Device Control Register                      */
+    __IO uint32_t dev_intfl;                  /*  0x0208   USB Device Interrupt                             */
+    __IO uint32_t dev_inten;                  /*  0x020C   USB Device Interrupt Enable                      */
+    __I uint32_t rsv0210[4];                  /*  0x0210                                                    */
+    __IO uint32_t ep_base;                    /*  0x0220   USB Endpoint Descriptor Table Base Address       */
+    __IO uint32_t cur_buf;                    /*  0x0224   USB Current Endpoint Buffer Register             */
+    __IO uint32_t in_owner;                   /*  0x0228   USB IN Endpoint Buffer Owner Register            */
+    __IO uint32_t out_owner;                  /*  0x022C   USB OUT Endpoint Buffer Owner Register           */
+    __IO uint32_t in_int;                     /*  0x0230   USB IN Endpoint Buffer Available Interrupt       */
+    __IO uint32_t out_int;                    /*  0x0234   USB OUT Endpoint Data Available Interrupt        */
+    __IO uint32_t nak_int;                    /*  0x0238   USB IN Endpoint NAK Interrupt                    */
+    __IO uint32_t dma_err_int;                /*  0x023C   USB DMA Error Interrupt                          */
+    __IO uint32_t buf_ovr_int;                /*  0x0240   USB Buffer Overflow Interrupt                    */
+    __I uint32_t rsv0244[7];                  /*  0x0244                                                    */
+    __IO uint32_t setup0;                     /*  0x0260   USB SETUP Packet Bytes 0 to 3                    */
+    __IO uint32_t setup1;                     /*  0x0264   USB SETUP Packet Bytes 4 to 7                    */
+    __I uint32_t rsv0268[6];                  /*  0x0268                                                    */
+    __IO uint32_t ep[MXC_USB_NUM_EP];         /*  0x0280   USB Endpoint Control Registers                   */
+} mxc_usb_regs_t;
+
+
+/*
+   Register offsets for module USB.
+*/
+#define MXC_R_USB_OFFS_CN                       ((uint32_t)0x00000000UL)
+#define MXC_R_USB_OFFS_DEV_ADDR                 ((uint32_t)0x00000200UL)
+#define MXC_R_USB_OFFS_DEV_CN                   ((uint32_t)0x00000204UL)
+#define MXC_R_USB_OFFS_DEV_INTFL                ((uint32_t)0x00000208UL)
+#define MXC_R_USB_OFFS_DEV_INTEN                ((uint32_t)0x0000020CUL)
+#define MXC_R_USB_OFFS_EP_BASE                  ((uint32_t)0x00000220UL)
+#define MXC_R_USB_OFFS_CUR_BUF                  ((uint32_t)0x00000224UL)
+#define MXC_R_USB_OFFS_IN_OWNER                 ((uint32_t)0x00000228UL)
+#define MXC_R_USB_OFFS_OUT_OWNER                ((uint32_t)0x0000022CUL)
+#define MXC_R_USB_OFFS_IN_INT                   ((uint32_t)0x00000230UL)
+#define MXC_R_USB_OFFS_OUT_INT                  ((uint32_t)0x00000234UL)
+#define MXC_R_USB_OFFS_NAK_INT                  ((uint32_t)0x00000238UL)
+#define MXC_R_USB_OFFS_DMA_ERR_INT              ((uint32_t)0x0000023CUL)
+#define MXC_R_USB_OFFS_BUF_OVR_INT              ((uint32_t)0x00000240UL)
+#define MXC_R_USB_OFFS_SETUP0                   ((uint32_t)0x00000260UL)
+#define MXC_R_USB_OFFS_SETUP1                   ((uint32_t)0x00000264UL)
+#define MXC_R_USB_OFFS_EP0                      ((uint32_t)0x00000280UL)
+#define MXC_R_USB_OFFS_EP1                      ((uint32_t)0x00000284UL)
+#define MXC_R_USB_OFFS_EP2                      ((uint32_t)0x00000288UL)
+#define MXC_R_USB_OFFS_EP3                      ((uint32_t)0x0000028CUL)
+#define MXC_R_USB_OFFS_EP4                      ((uint32_t)0x00000290UL)
+#define MXC_R_USB_OFFS_EP5                      ((uint32_t)0x00000294UL)
+#define MXC_R_USB_OFFS_EP6                      ((uint32_t)0x00000298UL)
+#define MXC_R_USB_OFFS_EP7                      ((uint32_t)0x0000029CUL)
+
+
+/*
+   Field positions and masks for module USB.
+*/
+#define MXC_F_USB_CN_USB_EN_POS                 0
+#define MXC_F_USB_CN_USB_EN                     ((uint32_t)(0x00000001UL << MXC_F_USB_CN_USB_EN_POS))
+
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR_POS         0
+#define MXC_F_USB_DEV_ADDR_DEV_ADDR             ((uint32_t)(0x0000007FUL << MXC_F_USB_DEV_ADDR_DEV_ADDR_POS))
+
+#define MXC_F_USB_DEV_CN_SIGRWU_POS             2
+#define MXC_F_USB_DEV_CN_SIGRWU                 ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_SIGRWU_POS))
+#define MXC_F_USB_DEV_CN_CONNECT_POS            3
+#define MXC_F_USB_DEV_CN_CONNECT                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_CONNECT_POS))
+#define MXC_F_USB_DEV_CN_ULPM_POS               4
+#define MXC_F_USB_DEV_CN_ULPM                   ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_ULPM_POS))
+#define MXC_F_USB_DEV_CN_URST_POS               5
+#define MXC_F_USB_DEV_CN_URST                   ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_URST_POS))
+#define MXC_F_USB_DEV_CN_VBGATE_POS             6
+#define MXC_F_USB_DEV_CN_VBGATE                 ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_VBGATE_POS))
+#define MXC_F_USB_DEV_CN_FIFO_MODE_POS          9
+#define MXC_F_USB_DEV_CN_FIFO_MODE              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_CN_FIFO_MODE_POS))
+
+#define MXC_F_USB_DEV_INTFL_DPACT_POS           0
+#define MXC_F_USB_DEV_INTFL_DPACT               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DPACT_POS))
+#define MXC_F_USB_DEV_INTFL_RWU_DN_POS          1
+#define MXC_F_USB_DEV_INTFL_RWU_DN              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTFL_BACT_POS            2
+#define MXC_F_USB_DEV_INTFL_BACT                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BACT_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_POS            3
+#define MXC_F_USB_DEV_INTFL_BRST                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_POS))
+#define MXC_F_USB_DEV_INTFL_SUSP_POS            4
+#define MXC_F_USB_DEV_INTFL_SUSP                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SUSP_POS))
+#define MXC_F_USB_DEV_INTFL_NO_VBUS_POS         5
+#define MXC_F_USB_DEV_INTFL_NO_VBUS             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_POS            6
+#define MXC_F_USB_DEV_INTFL_VBUS                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_POS))
+#define MXC_F_USB_DEV_INTFL_BRST_DN_POS         7
+#define MXC_F_USB_DEV_INTFL_BRST_DN             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTFL_SETUP_POS           8
+#define MXC_F_USB_DEV_INTFL_SETUP               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_SETUP_POS))
+#define MXC_F_USB_DEV_INTFL_EP_IN_POS           9
+#define MXC_F_USB_DEV_INTFL_EP_IN               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_IN_POS))
+#define MXC_F_USB_DEV_INTFL_EP_OUT_POS          10
+#define MXC_F_USB_DEV_INTFL_EP_OUT              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTFL_EP_NAK_POS          11
+#define MXC_F_USB_DEV_INTFL_EP_NAK              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTFL_DMA_ERR_POS         12
+#define MXC_F_USB_DEV_INTFL_DMA_ERR             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTFL_BUF_OVR_POS         13
+#define MXC_F_USB_DEV_INTFL_BUF_OVR             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_BUF_OVR_POS))
+#define MXC_F_USB_DEV_INTFL_VBUS_ST_POS         16
+#define MXC_F_USB_DEV_INTFL_VBUS_ST             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTFL_VBUS_ST_POS))
+
+#define MXC_F_USB_DEV_INTEN_DPACT_POS           0
+#define MXC_F_USB_DEV_INTEN_DPACT               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DPACT_POS))
+#define MXC_F_USB_DEV_INTEN_RWU_DN_POS          1
+#define MXC_F_USB_DEV_INTEN_RWU_DN              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_RWU_DN_POS))
+#define MXC_F_USB_DEV_INTEN_BACT_POS            2
+#define MXC_F_USB_DEV_INTEN_BACT                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BACT_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_POS            3
+#define MXC_F_USB_DEV_INTEN_BRST                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_POS))
+#define MXC_F_USB_DEV_INTEN_SUSP_POS            4
+#define MXC_F_USB_DEV_INTEN_SUSP                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SUSP_POS))
+#define MXC_F_USB_DEV_INTEN_NO_VBUS_POS         5
+#define MXC_F_USB_DEV_INTEN_NO_VBUS             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_NO_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_VBUS_POS            6
+#define MXC_F_USB_DEV_INTEN_VBUS                ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_VBUS_POS))
+#define MXC_F_USB_DEV_INTEN_BRST_DN_POS         7
+#define MXC_F_USB_DEV_INTEN_BRST_DN             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BRST_DN_POS))
+#define MXC_F_USB_DEV_INTEN_SETUP_POS           8
+#define MXC_F_USB_DEV_INTEN_SETUP               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_SETUP_POS))
+#define MXC_F_USB_DEV_INTEN_EP_IN_POS           9
+#define MXC_F_USB_DEV_INTEN_EP_IN               ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_IN_POS))
+#define MXC_F_USB_DEV_INTEN_EP_OUT_POS          10
+#define MXC_F_USB_DEV_INTEN_EP_OUT              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_OUT_POS))
+#define MXC_F_USB_DEV_INTEN_EP_NAK_POS          11
+#define MXC_F_USB_DEV_INTEN_EP_NAK              ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_EP_NAK_POS))
+#define MXC_F_USB_DEV_INTEN_DMA_ERR_POS         12
+#define MXC_F_USB_DEV_INTEN_DMA_ERR             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_DMA_ERR_POS))
+#define MXC_F_USB_DEV_INTEN_BUF_OVR_POS         13
+#define MXC_F_USB_DEV_INTEN_BUF_OVR             ((uint32_t)(0x00000001UL << MXC_F_USB_DEV_INTEN_BUF_OVR_POS))
+
+#define MXC_F_USB_EP_BASE_EP_BASE_POS           9
+#define MXC_F_USB_EP_BASE_EP_BASE               ((uint32_t)(0x007FFFFFUL << MXC_F_USB_EP_BASE_EP_BASE_POS))
+
+#define MXC_F_USB_CUR_BUF_OUT_BUF_POS           0
+#define MXC_F_USB_CUR_BUF_OUT_BUF               ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_OUT_BUF_POS))
+#define MXC_F_USB_CUR_BUF_IN_BUF_POS            16
+#define MXC_F_USB_CUR_BUF_IN_BUF                ((uint32_t)(0x000000FFUL << MXC_F_USB_CUR_BUF_IN_BUF_POS))
+
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER_POS       0
+#define MXC_F_USB_IN_OWNER_BUF0_OWNER           ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER_POS       16
+#define MXC_F_USB_IN_OWNER_BUF1_OWNER           ((uint32_t)(0x000000FFUL << MXC_F_USB_IN_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS      0
+#define MXC_F_USB_OUT_OWNER_BUF0_OWNER          ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF0_OWNER_POS))
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS      16
+#define MXC_F_USB_OUT_OWNER_BUF1_OWNER          ((uint32_t)(0x000000FFUL << MXC_F_USB_OUT_OWNER_BUF1_OWNER_POS))
+
+#define MXC_F_USB_IN_INT_INBAV0_POS             0
+#define MXC_F_USB_IN_INT_INBAV0                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV0_POS))
+#define MXC_F_USB_IN_INT_INBAV1_POS             1
+#define MXC_F_USB_IN_INT_INBAV1                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV1_POS))
+#define MXC_F_USB_IN_INT_INBAV2_POS             2
+#define MXC_F_USB_IN_INT_INBAV2                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV2_POS))
+#define MXC_F_USB_IN_INT_INBAV3_POS             3
+#define MXC_F_USB_IN_INT_INBAV3                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV3_POS))
+#define MXC_F_USB_IN_INT_INBAV4_POS             4
+#define MXC_F_USB_IN_INT_INBAV4                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV4_POS))
+#define MXC_F_USB_IN_INT_INBAV5_POS             5
+#define MXC_F_USB_IN_INT_INBAV5                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV5_POS))
+#define MXC_F_USB_IN_INT_INBAV6_POS             6
+#define MXC_F_USB_IN_INT_INBAV6                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV6_POS))
+#define MXC_F_USB_IN_INT_INBAV7_POS             7
+#define MXC_F_USB_IN_INT_INBAV7                 ((uint32_t)(0x00000001UL << MXC_F_USB_IN_INT_INBAV7_POS))
+
+#define MXC_F_USB_OUT_INT_OUTDAV0_POS           0
+#define MXC_F_USB_OUT_INT_OUTDAV0               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV0_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV1_POS           1
+#define MXC_F_USB_OUT_INT_OUTDAV1               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV1_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV2_POS           2
+#define MXC_F_USB_OUT_INT_OUTDAV2               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV2_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV3_POS           3
+#define MXC_F_USB_OUT_INT_OUTDAV3               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV3_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV4_POS           4
+#define MXC_F_USB_OUT_INT_OUTDAV4               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV4_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV5_POS           5
+#define MXC_F_USB_OUT_INT_OUTDAV5               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV5_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV6_POS           6
+#define MXC_F_USB_OUT_INT_OUTDAV6               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV6_POS))
+#define MXC_F_USB_OUT_INT_OUTDAV7_POS           7
+#define MXC_F_USB_OUT_INT_OUTDAV7               ((uint32_t)(0x00000001UL << MXC_F_USB_OUT_INT_OUTDAV7_POS))
+
+#define MXC_F_USB_NAK_INT_NAK0_POS              0
+#define MXC_F_USB_NAK_INT_NAK0                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK0_POS))
+#define MXC_F_USB_NAK_INT_NAK1_POS              1
+#define MXC_F_USB_NAK_INT_NAK1                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK1_POS))
+#define MXC_F_USB_NAK_INT_NAK2_POS              2
+#define MXC_F_USB_NAK_INT_NAK2                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK2_POS))
+#define MXC_F_USB_NAK_INT_NAK3_POS              3
+#define MXC_F_USB_NAK_INT_NAK3                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK3_POS))
+#define MXC_F_USB_NAK_INT_NAK4_POS              4
+#define MXC_F_USB_NAK_INT_NAK4                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK4_POS))
+#define MXC_F_USB_NAK_INT_NAK5_POS              5
+#define MXC_F_USB_NAK_INT_NAK5                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK5_POS))
+#define MXC_F_USB_NAK_INT_NAK6_POS              6
+#define MXC_F_USB_NAK_INT_NAK6                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK6_POS))
+#define MXC_F_USB_NAK_INT_NAK7_POS              7
+#define MXC_F_USB_NAK_INT_NAK7                  ((uint32_t)(0x00000001UL << MXC_F_USB_NAK_INT_NAK7_POS))
+
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS      0
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR0          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR0_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS      1
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR1          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR1_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS      2
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR2          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR2_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS      3
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR3          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR3_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS      4
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR4          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR4_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS      5
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR5          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR5_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS      6
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR6          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR6_POS))
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS      7
+#define MXC_F_USB_DMA_ERR_INT_DMA_ERR7          ((uint32_t)(0x00000001UL << MXC_F_USB_DMA_ERR_INT_DMA_ERR7_POS))
+
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS      0
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR0          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR0_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS      1
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR1          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR1_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS      2
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR2          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR2_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS      3
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR3          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR3_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS      4
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR4          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR4_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS      5
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR5          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR5_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS      6
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR6          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR6_POS))
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS      7
+#define MXC_F_USB_BUF_OVR_INT_BUF_OVR7          ((uint32_t)(0x00000001UL << MXC_F_USB_BUF_OVR_INT_BUF_OVR7_POS))
+
+#define MXC_F_USB_SETUP0_BYTE0_POS              0
+#define MXC_F_USB_SETUP0_BYTE0                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE0_POS))
+#define MXC_F_USB_SETUP0_BYTE1_POS              8
+#define MXC_F_USB_SETUP0_BYTE1                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE1_POS))
+#define MXC_F_USB_SETUP0_BYTE2_POS              16
+#define MXC_F_USB_SETUP0_BYTE2                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE2_POS))
+#define MXC_F_USB_SETUP0_BYTE3_POS              24
+#define MXC_F_USB_SETUP0_BYTE3                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP0_BYTE3_POS))
+
+#define MXC_F_USB_SETUP1_BYTE4_POS              0
+#define MXC_F_USB_SETUP1_BYTE4                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE4_POS))
+#define MXC_F_USB_SETUP1_BYTE5_POS              8
+#define MXC_F_USB_SETUP1_BYTE5                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE5_POS))
+#define MXC_F_USB_SETUP1_BYTE6_POS              16
+#define MXC_F_USB_SETUP1_BYTE6                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE6_POS))
+#define MXC_F_USB_SETUP1_BYTE7_POS              24
+#define MXC_F_USB_SETUP1_BYTE7                  ((uint32_t)(0x000000FFUL << MXC_F_USB_SETUP1_BYTE7_POS))
+
+#define MXC_F_USB_EP0_EP_DIR_POS                0
+#define MXC_F_USB_EP0_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP0_EP_DIR_POS))
+#define MXC_F_USB_EP0_EP_BUF2_POS               3
+#define MXC_F_USB_EP0_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_BUF2_POS))
+#define MXC_F_USB_EP0_EP_INT_EN_POS             4
+#define MXC_F_USB_EP0_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_INT_EN_POS))
+#define MXC_F_USB_EP0_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP0_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_NAK_EN_POS))
+#define MXC_F_USB_EP0_EP_DT_POS                 6
+#define MXC_F_USB_EP0_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_DT_POS))
+#define MXC_F_USB_EP0_EP_STALL_POS              8
+#define MXC_F_USB_EP0_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_STALL_POS))
+#define MXC_F_USB_EP0_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP0_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_STALL_POS))
+#define MXC_F_USB_EP0_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP0_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP0_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP1_EP_DIR_POS                0
+#define MXC_F_USB_EP1_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP1_EP_DIR_POS))
+#define MXC_F_USB_EP1_EP_BUF2_POS               3
+#define MXC_F_USB_EP1_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_BUF2_POS))
+#define MXC_F_USB_EP1_EP_INT_EN_POS             4
+#define MXC_F_USB_EP1_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_INT_EN_POS))
+#define MXC_F_USB_EP1_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP1_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_NAK_EN_POS))
+#define MXC_F_USB_EP1_EP_DT_POS                 6
+#define MXC_F_USB_EP1_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_DT_POS))
+#define MXC_F_USB_EP1_EP_STALL_POS              8
+#define MXC_F_USB_EP1_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_STALL_POS))
+#define MXC_F_USB_EP1_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP1_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_STALL_POS))
+#define MXC_F_USB_EP1_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP1_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP1_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP2_EP_DIR_POS                0
+#define MXC_F_USB_EP2_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP2_EP_DIR_POS))
+#define MXC_F_USB_EP2_EP_BUF2_POS               3
+#define MXC_F_USB_EP2_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_BUF2_POS))
+#define MXC_F_USB_EP2_EP_INT_EN_POS             4
+#define MXC_F_USB_EP2_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_INT_EN_POS))
+#define MXC_F_USB_EP2_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP2_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_NAK_EN_POS))
+#define MXC_F_USB_EP2_EP_DT_POS                 6
+#define MXC_F_USB_EP2_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_DT_POS))
+#define MXC_F_USB_EP2_EP_STALL_POS              8
+#define MXC_F_USB_EP2_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_STALL_POS))
+#define MXC_F_USB_EP2_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP2_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_STALL_POS))
+#define MXC_F_USB_EP2_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP2_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP2_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP3_EP_DIR_POS                0
+#define MXC_F_USB_EP3_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP3_EP_DIR_POS))
+#define MXC_F_USB_EP3_EP_BUF2_POS               3
+#define MXC_F_USB_EP3_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_BUF2_POS))
+#define MXC_F_USB_EP3_EP_INT_EN_POS             4
+#define MXC_F_USB_EP3_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_INT_EN_POS))
+#define MXC_F_USB_EP3_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP3_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_NAK_EN_POS))
+#define MXC_F_USB_EP3_EP_DT_POS                 6
+#define MXC_F_USB_EP3_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_DT_POS))
+#define MXC_F_USB_EP3_EP_STALL_POS              8
+#define MXC_F_USB_EP3_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_STALL_POS))
+#define MXC_F_USB_EP3_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP3_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_STALL_POS))
+#define MXC_F_USB_EP3_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP3_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP3_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP4_EP_DIR_POS                0
+#define MXC_F_USB_EP4_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP4_EP_DIR_POS))
+#define MXC_F_USB_EP4_EP_BUF2_POS               3
+#define MXC_F_USB_EP4_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_BUF2_POS))
+#define MXC_F_USB_EP4_EP_INT_EN_POS             4
+#define MXC_F_USB_EP4_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_INT_EN_POS))
+#define MXC_F_USB_EP4_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP4_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_NAK_EN_POS))
+#define MXC_F_USB_EP4_EP_DT_POS                 6
+#define MXC_F_USB_EP4_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_DT_POS))
+#define MXC_F_USB_EP4_EP_STALL_POS              8
+#define MXC_F_USB_EP4_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_STALL_POS))
+#define MXC_F_USB_EP4_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP4_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_STALL_POS))
+#define MXC_F_USB_EP4_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP4_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP4_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP5_EP_DIR_POS                0
+#define MXC_F_USB_EP5_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP5_EP_DIR_POS))
+#define MXC_F_USB_EP5_EP_BUF2_POS               3
+#define MXC_F_USB_EP5_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_BUF2_POS))
+#define MXC_F_USB_EP5_EP_INT_EN_POS             4
+#define MXC_F_USB_EP5_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_INT_EN_POS))
+#define MXC_F_USB_EP5_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP5_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_NAK_EN_POS))
+#define MXC_F_USB_EP5_EP_DT_POS                 6
+#define MXC_F_USB_EP5_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_DT_POS))
+#define MXC_F_USB_EP5_EP_STALL_POS              8
+#define MXC_F_USB_EP5_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_STALL_POS))
+#define MXC_F_USB_EP5_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP5_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_STALL_POS))
+#define MXC_F_USB_EP5_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP5_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP5_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP6_EP_DIR_POS                0
+#define MXC_F_USB_EP6_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP6_EP_DIR_POS))
+#define MXC_F_USB_EP6_EP_BUF2_POS               3
+#define MXC_F_USB_EP6_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_BUF2_POS))
+#define MXC_F_USB_EP6_EP_INT_EN_POS             4
+#define MXC_F_USB_EP6_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_INT_EN_POS))
+#define MXC_F_USB_EP6_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP6_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_NAK_EN_POS))
+#define MXC_F_USB_EP6_EP_DT_POS                 6
+#define MXC_F_USB_EP6_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_DT_POS))
+#define MXC_F_USB_EP6_EP_STALL_POS              8
+#define MXC_F_USB_EP6_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_STALL_POS))
+#define MXC_F_USB_EP6_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP6_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_STALL_POS))
+#define MXC_F_USB_EP6_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP6_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP6_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP7_EP_DIR_POS                0
+#define MXC_F_USB_EP7_EP_DIR                    ((uint32_t)(0x00000003UL << MXC_F_USB_EP7_EP_DIR_POS))
+#define MXC_F_USB_EP7_EP_BUF2_POS               3
+#define MXC_F_USB_EP7_EP_BUF2                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_BUF2_POS))
+#define MXC_F_USB_EP7_EP_INT_EN_POS             4
+#define MXC_F_USB_EP7_EP_INT_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_INT_EN_POS))
+#define MXC_F_USB_EP7_EP_NAK_EN_POS             5
+#define MXC_F_USB_EP7_EP_NAK_EN                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_NAK_EN_POS))
+#define MXC_F_USB_EP7_EP_DT_POS                 6
+#define MXC_F_USB_EP7_EP_DT                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_DT_POS))
+#define MXC_F_USB_EP7_EP_STALL_POS              8
+#define MXC_F_USB_EP7_EP_STALL                  ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_STALL_POS))
+#define MXC_F_USB_EP7_EP_ST_STALL_POS           9
+#define MXC_F_USB_EP7_EP_ST_STALL               ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_STALL_POS))
+#define MXC_F_USB_EP7_EP_ST_ACK_POS             10
+#define MXC_F_USB_EP7_EP_ST_ACK                 ((uint32_t)(0x00000001UL << MXC_F_USB_EP7_EP_ST_ACK_POS))
+
+#define MXC_F_USB_EP_DIR_POS                    (0)
+#define MXC_F_USB_EP_DIR                        ((uint32_t)(0x00000003UL << MXC_F_USB_EP_DIR_POS))
+
+#define MXC_V_USB_EP_DIR_DISABLE                ((uint32_t)0x00000000UL)
+#define MXC_V_USB_EP_DIR_OUT                    ((uint32_t)0x00000001UL)
+#define MXC_V_USB_EP_DIR_IN                     ((uint32_t)0x00000002UL)
+#define MXC_V_USB_EP_DIR_CONTROL                ((uint32_t)0x00000003UL)
+
+#define MXC_S_USB_EP_DIR_DISABLE                (MXC_V_USB_EP_DIR_DISABLE << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_OUT                    (MXC_V_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_IN                     (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS)
+#define MXC_S_USB_EP_DIR_CONTROL                (MXC_V_USB_EP_DIR_CONTROL << MXC_F_USB_EP_DIR_POS)
+
+#define MXC_F_USB_EP_BUF2_POS                   (3)
+#define MXC_F_USB_EP_BUF2                       ((uint32_t)(0x00000001UL << MXC_F_USB_EP_BUF2_POS))
+#define MXC_F_USB_EP_INTEN_POS                  (4)
+#define MXC_F_USB_EP_INT_EN                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP_INTEN_POS))
+#define MXC_F_USB_EP_NAK_EN_POS                 (5)
+#define MXC_F_USB_EP_NAK_EN                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP_NAK_EN_POS))
+#define MXC_F_USB_EP_DT_POS                     (6)
+#define MXC_F_USB_EP_DT                         ((uint32_t)(0x00000001UL << MXC_F_USB_EP_DT_POS))
+#define MXC_F_USB_EP_STALL_POS                  (8)
+#define MXC_F_USB_EP_STALL                      ((uint32_t)(0x00000001UL << MXC_F_USB_EP_STALL_POS))
+#define MXC_F_USB_EP_ST_STALL_POS               (9)
+#define MXC_F_USB_EP_ST_STALL                   ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_STALL_POS))
+#define MXC_F_USB_EP_ST_ACK_POS                 (10)
+#define MXC_F_USB_EP_ST_ACK                     ((uint32_t)(0x00000001UL << MXC_F_USB_EP_ST_ACK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif /* _MXC_USB_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/wdt_regs.h

@@ -0,0 +1,150 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#ifndef _MXC_WDT_REGS_H_
+#define _MXC_WDT_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @file  wdt_regs.h
+ * @addtogroup wdt WDT
+ * @{
+ */
+
+/**
+ * @brief Defines watchdog timer periods
+ */
+typedef enum {
+    /** 2^31 cycle period */
+    MXC_E_WDT_PERIOD_2_31_CLKS = 0,
+    /** 2^30 cycle period */
+    MXC_E_WDT_PERIOD_2_30_CLKS,
+    /** 2^29 cycle period */
+    MXC_E_WDT_PERIOD_2_29_CLKS,
+    /** 2^28 cycle period */
+    MXC_E_WDT_PERIOD_2_28_CLKS,
+    /** 2^27 cycle period */
+    MXC_E_WDT_PERIOD_2_27_CLKS,
+    /** 2^26 cycle period */
+    MXC_E_WDT_PERIOD_2_26_CLKS,
+    /** 2^25 cycle period */
+    MXC_E_WDT_PERIOD_2_25_CLKS,
+    /** 2^24 cycle period */
+    MXC_E_WDT_PERIOD_2_24_CLKS,
+    /** 2^23 cycle period */
+    MXC_E_WDT_PERIOD_2_23_CLKS,
+    /** 2^22 cycle period */
+    MXC_E_WDT_PERIOD_2_22_CLKS,
+    /** 2^21 cycle period */
+    MXC_E_WDT_PERIOD_2_21_CLKS,
+    /** 2^20 cycle period */
+    MXC_E_WDT_PERIOD_2_20_CLKS,
+    /** 2^19 cycle period */
+    MXC_E_WDT_PERIOD_2_19_CLKS,
+    /** 2^18 cycle period */
+    MXC_E_WDT_PERIOD_2_18_CLKS,
+    /** 2^17 cycle period */
+    MXC_E_WDT_PERIOD_2_17_CLKS,
+    /** 2^16 cycle period */
+    MXC_E_WDT_PERIOD_2_16_CLKS,
+} mxc_wdt_period_t;
+
+/*                                  Offset   Register Description
+                                    ======   ================================================ */
+typedef struct {
+    __IO uint32_t ctrl;         /*  0x0000   Watchdog Timer Control Register                  */
+    __IO uint32_t clear;        /*  0x0004   Watchdog Clear Register (Feed Dog)               */
+    __IO uint32_t int_rst_fl;   /*  0x0008   Watchdog Interrupt/Reset Flags                   */
+    __IO uint32_t int_rst_en;   /*  0x000C   Interrupt/Reset Enable/Disable Controls          */
+    __I uint32_t rsv0010;       /*  0x0010                                                    */
+    __IO uint32_t lock_ctrl;    /*  0x0014   Lock Register Setting for WDT CTRL               */
+} mxc_wdt_regs_t;
+
+/*
+   Register offsets for module WDT.
+*/
+#define MXC_R_WDT_OFFS_CTRL                       ((uint32_t)0x00000000UL)
+#define MXC_R_WDT_OFFS_CLEAR                      ((uint32_t)0x00000004UL)
+#define MXC_R_WDT_OFFS_INT_RST_FL                 ((uint32_t)0x00000008UL)
+#define MXC_R_WDT_OFFS_INT_RST_EN                 ((uint32_t)0x0000000CUL)
+#define MXC_R_WDT_OFFS_LOCK_CTRL                  ((uint32_t)0x00000014UL)
+
+#define MXC_V_WDT_WDLOCK_LOCK_KEY                 ((uint8_t)0x24)
+#define MXC_V_WDT_WDLOCK_UNLOCK_KEY               ((uint8_t)0x42)
+
+
+/*
+   Field positions and masks for module WDT.
+*/
+#define MXC_F_WDT_CTRL_INT_PERIOD_POS       0
+#define MXC_F_WDT_CTRL_INT_PERIOD           ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS))
+#define MXC_F_WDT_CTRL_RST_PERIOD_POS       4
+#define MXC_F_WDT_CTRL_RST_PERIOD           ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS))
+#define MXC_F_WDT_CTRL_EN_TIMER_POS         8
+#define MXC_F_WDT_CTRL_EN_TIMER             ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS))
+#define MXC_F_WDT_CTRL_EN_CLOCK_POS         9
+#define MXC_F_WDT_CTRL_EN_CLOCK             ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS))
+#define MXC_F_WDT_CTRL_WAIT_PERIOD_POS      12
+#define MXC_F_WDT_CTRL_WAIT_PERIOD          ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
+
+#define MXC_F_WDT_FLAGS_TIMEOUT_POS         0
+#define MXC_F_WDT_FLAGS_TIMEOUT             ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS))
+#define MXC_F_WDT_FLAGS_PRE_WIN_POS         1
+#define MXC_F_WDT_FLAGS_PRE_WIN             ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS))
+#define MXC_F_WDT_FLAGS_RESET_OUT_POS       2
+#define MXC_F_WDT_FLAGS_RESET_OUT           ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS))
+
+#define MXC_F_WDT_ENABLE_TIMEOUT_POS        0
+#define MXC_F_WDT_ENABLE_TIMEOUT            ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS))
+#define MXC_F_WDT_ENABLE_PRE_WIN_POS        1
+#define MXC_F_WDT_ENABLE_PRE_WIN            ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS))
+#define MXC_F_WDT_ENABLE_RESET_OUT_POS      2
+#define MXC_F_WDT_ENABLE_RESET_OUT          ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS))
+
+#define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS      0
+#define MXC_F_WDT_LOCK_CTRL_WDLOCK          ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS))
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+* @}
+*/
+
+#endif   /* _MXC_WDT_REGS_H_ */

libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/system_max32610.c

@@ -109,7 +109,7 @@ void ICC_Enable(void)
 }
 
 // This function to be implemented by the hal
-extern void low_level_init();
+extern void low_level_init(void);
 
 void SystemInit(void)
 {

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_GCC_ARM/startup_LPC824.s

@@ -98,16 +98,28 @@ __isr_vector:
 /* LPC824 interrupts */
     .long    SPI0_IRQHandler                         // SPI0 controller
     .long    SPI1_IRQHandler                         // SPI1 controller
+    .long    0                                       // Reserved
     .long    UART0_IRQHandler                        // UART0
     .long    UART1_IRQHandler                        // UART1
     .long    UART2_IRQHandler                        // UART2
-    .long    I2C_IRQHandler                         // I2C controller
+    .long    0                                       // Reserved
+    .long    I2C1_IRQHandler                         // I2C ch1 controller
+    .long    I2C0_IRQHandler                         // I2C ch0 controller
     .long    SCT_IRQHandler                          // Smart Counter Timer
     .long    MRT_IRQHandler                          // Multi-Rate Timer
     .long    CMP_IRQHandler                          // Comparator
     .long    WDT_IRQHandler                          // PIO1 (0:11)
     .long    BOD_IRQHandler                          // Brown Out Detect
+    .long    Flash_IRQHandler                        // Flash interrupt
     .long    WKT_IRQHandler                          // Wakeup timer
+    .long    ADC_SEQA_IRQHandler                     // ADC sequence A completion
+    .long    ADC_SEQB_IRQHandler                     // ADC sequence B completion
+    .long    ADC_THCMP_IRQHandler                    // ADC threshold compare
+    .long    ADC_OVR_IRQHandler                      // ADC overrun
+    .long    DMA_IRQHandler                          // DMA interrupt
+    .long    I2C2_IRQHandler                         // I2C2 controller
+    .long    I2C3_IRQHandler                         // I2C3 controller
+    .long    0                                       // Reserved
     .long    PININT0_IRQHandler                      // PIO INT0
     .long    PININT1_IRQHandler                      // PIO INT1
     .long    PININT2_IRQHandler                      // PIO INT2
@@ -181,18 +193,28 @@ Reset_Handler:
     .weak     \handler_name
     .set      \handler_name, Default_Handler
     .endm
+
     def_irq_default_handler    SPI0_IRQHandler
     def_irq_default_handler    SPI1_IRQHandler
     def_irq_default_handler    UART0_IRQHandler
     def_irq_default_handler    UART1_IRQHandler
     def_irq_default_handler    UART2_IRQHandler
-    def_irq_default_handler    I2C_IRQHandler
+    def_irq_default_handler    I2C0_IRQHandler
+    def_irq_default_handler    I2C1_IRQHandler
+    def_irq_default_handler    I2C2_IRQHandler
+    def_irq_default_handler    I2C3_IRQHandler
     def_irq_default_handler    SCT_IRQHandler
     def_irq_default_handler    MRT_IRQHandler
     def_irq_default_handler    CMP_IRQHandler
     def_irq_default_handler    WDT_IRQHandler
     def_irq_default_handler    BOD_IRQHandler
+    def_irq_default_handler    Flash_IRQHandler
     def_irq_default_handler    WKT_IRQHandler
+    def_irq_default_handler    ADC_SEQA_IRQHandler
+    def_irq_default_handler    ADC_SEQB_IRQHandler
+    def_irq_default_handler    ADC_THCMP_IRQHandler
+    def_irq_default_handler    ADC_OVR_IRQHandler
+    def_irq_default_handler    DMA_IRQHandler
     def_irq_default_handler    PININT0_IRQHandler
     def_irq_default_handler    PININT1_IRQHandler
     def_irq_default_handler    PININT2_IRQHandler

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/LPC824.ld

@@ -0,0 +1,152 @@
+/* Linker script for mbed LPC824-GCC-ARM based on LPC1114-GCC-ARM-LPC1114.ld */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+  /* Define each memory region */
+  FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */
+  RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */
+
+
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ * 
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+		*(.text.Reset_Handler)
+        *(.text.SystemInit)
+		. = 0x200;
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+        
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE (__fini_array_end = .);
+
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    .bss :
+    {
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        __bss_end__ = .;
+    } > RAM
+    
+    .heap :
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy :
+    {
+        *(.stack)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+    
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_GCC_ARM/startup_LPC824.s

@@ -0,0 +1,228 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with 
+ *   GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ * 
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+    * Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * Neither the name of the ARM Limited nor the
+      names of its contributors may be used to endorse or promote products
+      derived from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+    .syntax unified
+    .arch armv6-m
+
+/* Memory Model
+   The HEAP starts at the end of the DATA section and grows upward.
+   
+   The STACK starts at the end of the RAM and grows downward.
+   
+   The HEAP and stack STACK are only checked at compile time:
+   (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+   
+   This is just a check for the bare minimum for the Heap+Stack area before
+   aborting compilation, it is not the run time limit:
+   Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 0x80
+#endif
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+#ifdef __HEAP_SIZE
+    .equ    Heap_Size, __HEAP_SIZE
+#else
+    .equ    Heap_Size, 0x80
+#endif
+    .globl    __HeapBase
+    .globl    __HeapLimit
+__HeapBase:
+    .space    Heap_Size
+    .size __HeapBase, . - __HeapBase
+__HeapLimit:
+    .size __HeapLimit, . - __HeapLimit
+    
+    .section .isr_vector
+    .align 2
+    .globl __isr_vector
+__isr_vector:
+    .long    __StackTop            /* Top of Stack */
+    .long    Reset_Handler         /* Reset Handler */
+    .long    NMI_Handler           /* NMI Handler */
+    .long    HardFault_Handler     /* Hard Fault Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    SVC_Handler           /* SVCall Handler */
+    .long    0                     /* Reserved */
+    .long    0                     /* Reserved */
+    .long    PendSV_Handler        /* PendSV Handler */
+    .long    SysTick_Handler       /* SysTick Handler */
+
+/* LPC824 interrupts */
+    .long    SPI0_IRQHandler                         // SPI0 controller
+    .long    SPI1_IRQHandler                         // SPI1 controller
+    .long    0                                       // Reserved
+    .long    UART0_IRQHandler                        // UART0
+    .long    UART1_IRQHandler                        // UART1
+    .long    UART2_IRQHandler                        // UART2
+    .long    0                                       // Reserved
+    .long    I2C1_IRQHandler                         // I2C ch1 controller
+    .long    I2C0_IRQHandler                         // I2C ch0 controller
+    .long    SCT_IRQHandler                          // Smart Counter Timer
+    .long    MRT_IRQHandler                          // Multi-Rate Timer
+    .long    CMP_IRQHandler                          // Comparator
+    .long    WDT_IRQHandler                          // PIO1 (0:11)
+    .long    BOD_IRQHandler                          // Brown Out Detect
+    .long    Flash_IRQHandler                        // Flash interrupt
+    .long    WKT_IRQHandler                          // Wakeup timer
+    .long    ADC_SEQA_IRQHandler                     // ADC sequence A completion
+    .long    ADC_SEQB_IRQHandler                     // ADC sequence B completion
+    .long    ADC_THCMP_IRQHandler                    // ADC threshold compare
+    .long    ADC_OVR_IRQHandler                      // ADC overrun
+    .long    DMA_IRQHandler                          // DMA interrupt
+    .long    I2C2_IRQHandler                         // I2C2 controller
+    .long    I2C3_IRQHandler                         // I2C3 controller
+    .long    0                                       // Reserved
+    .long    PININT0_IRQHandler                      // PIO INT0
+    .long    PININT1_IRQHandler                      // PIO INT1
+    .long    PININT2_IRQHandler                      // PIO INT2
+    .long    PININT3_IRQHandler                      // PIO INT3
+    .long    PININT4_IRQHandler                      // PIO INT4
+    .long    PININT5_IRQHandler                      // PIO INT5
+    .long    PININT6_IRQHandler                      // PIO INT6
+    .long    PININT7_IRQHandler                      // PIO INT7
+    
+    .size    __isr_vector, . - __isr_vector
+
+    .section .text.Reset_Handler
+    .thumb
+    .thumb_func
+    .align 2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in 
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble    .Lflash_to_ram_loop_end
+
+    movs    r4, 0
+.Lflash_to_ram_loop:
+    ldr    r0, [r1,r4]
+    str    r0, [r2,r4]
+    adds    r4, 4
+    cmp    r4, r3
+    blt    .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+    ldr    r0, =SystemInit
+    blx    r0
+    ldr    r0, =_start
+    bx    r0
+    .pool
+    .size Reset_Handler, . - Reset_Handler
+    
+    .text
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_default_handler    handler_name
+    .align 1
+    .thumb_func
+    .weak    \handler_name
+    .type    \handler_name, %function
+\handler_name :
+    b    .
+    .size    \handler_name, . - \handler_name
+    .endm
+
+    def_default_handler     NMI_Handler
+    def_default_handler     HardFault_Handler
+    def_default_handler     SVC_Handler
+    def_default_handler     PendSV_Handler
+    def_default_handler     SysTick_Handler
+    def_default_handler     Default_Handler
+
+    .macro    def_irq_default_handler    handler_name
+    .weak     \handler_name
+    .set      \handler_name, Default_Handler
+    .endm
+
+    def_irq_default_handler    SPI0_IRQHandler
+    def_irq_default_handler    SPI1_IRQHandler
+    def_irq_default_handler    UART0_IRQHandler
+    def_irq_default_handler    UART1_IRQHandler
+    def_irq_default_handler    UART2_IRQHandler
+    def_irq_default_handler    I2C0_IRQHandler
+    def_irq_default_handler    I2C1_IRQHandler
+    def_irq_default_handler    I2C2_IRQHandler
+    def_irq_default_handler    I2C3_IRQHandler
+    def_irq_default_handler    SCT_IRQHandler
+    def_irq_default_handler    MRT_IRQHandler
+    def_irq_default_handler    CMP_IRQHandler
+    def_irq_default_handler    WDT_IRQHandler
+    def_irq_default_handler    BOD_IRQHandler
+    def_irq_default_handler    Flash_IRQHandler
+    def_irq_default_handler    WKT_IRQHandler
+    def_irq_default_handler    ADC_SEQA_IRQHandler
+    def_irq_default_handler    ADC_SEQB_IRQHandler
+    def_irq_default_handler    ADC_THCMP_IRQHandler
+    def_irq_default_handler    ADC_OVR_IRQHandler
+    def_irq_default_handler    DMA_IRQHandler
+    def_irq_default_handler    PININT0_IRQHandler
+    def_irq_default_handler    PININT1_IRQHandler
+    def_irq_default_handler    PININT2_IRQHandler
+    def_irq_default_handler    PININT3_IRQHandler
+    def_irq_default_handler    PININT4_IRQHandler
+    def_irq_default_handler    PININT5_IRQHandler
+    def_irq_default_handler    PININT6_IRQHandler
+    def_irq_default_handler    PININT7_IRQHandler
+
+    .end
+

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c

@@ -0,0 +1,268 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "device.h"
+#include "PeripheralPins.h"
+#include "ioman_regs.h"
+
+/*
+ * To select a peripheral function on Maxim microcontrollers, multiple
+ * configurations must be made. The mbed PinMap structure only includes one
+ * data member to hold this information. To extend the configuration storage,
+ * the "function" data member is used as a pointer to a pin_function_t
+ * structure. This structure is defined in objects.h. The definitions below
+ * include the creation of the pin_function_t structures and the assignment of
+ * the pointers to the "function" data members.
+ */
+
+/************I2C***************/
+const PinMap PinMap_I2C_SDA[] = {
+    { P2_4,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P2_6,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P1_6,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P2_2,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P7_4,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P7_6,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P7_4,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P7_6,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P0_4,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P0_6,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { NC,    NC,    0 }
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    { P2_5,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P2_7,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P1_7,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P2_3,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P7_5,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P7_7,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P7_5,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P7_7,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P0_5,  I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { P0_7,  I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
+    { NC,    NC,    0 }
+};
+
+/************UART***************/
+const PinMap PinMap_UART_TX[] = {
+    { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P7_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P7_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { NC,   NC,     0 }
+};
+
+const PinMap PinMap_UART_RX[] = {
+    { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P7_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P7_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
+    { NC,   NC,     0 }
+};
+
+const PinMap PinMap_UART_CTS[] = {
+    { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
+    { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
+    { P1_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
+    { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
+    { P7_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
+    { P7_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
+    { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
+    { NC,   NC,     0 }
+};
+
+const PinMap PinMap_UART_RTS[] = {
+    { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
+    { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
+    { P1_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
+    { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
+    { P7_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
+    { P7_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
+    { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
+    { NC,   NC,     0 }
+};
+
+/************SPI***************/
+const PinMap PinMap_SPI_SCLK[] = {
+    { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P0_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P1_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P2_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P6_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P6_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { NC,   NC,    0}
+};
+
+const PinMap PinMap_SPI_MOSI[] = {
+    { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P0_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P1_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P2_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P6_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P6_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { NC,   NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P0_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P1_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P2_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P6_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { P6_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
+    { NC,   NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+#if (defined(EM9301_CSN) && (EM9301_CSN == P0_3))
+    { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
+#else
+    { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
+#endif
+    { P0_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
+    { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
+    { P1_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
+    { P2_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
+#if (defined(EM9301_CSN) && (EM9301_CSN == P2_3))
+    { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
+#else
+    { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
+#endif
+    { P6_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
+    { P6_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
+    { NC,   NC,    0}
+};
+
+/************PWM***************/
+const PinMap PinMap_PWM[] = {
+    {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3},
+    {P0_1, PWM_0, 3}, {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2},
+    {P0_2, PWM_1, 2}, {P0_2, PWM_2, 1}, {P0_2, PWM_5, 3},
+    {P0_3, PWM_1, 3}, {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2},
+    {P0_4, PWM_2, 2}, {P0_4, PWM_4, 1}, {P0_4, PWM_6, 3},
+    {P0_5, PWM_2, 3}, {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2},
+    {P0_6, PWM_3, 2}, {P0_6, PWM_6, 1}, {P0_6, PWM_7, 3},
+    {P0_7, PWM_3, 3}, {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2},
+
+    {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3},
+    {P1_1, PWM_0, 3}, {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2},
+    {P1_2, PWM_1, 2}, {P1_2, PWM_2, 1}, {P1_2, PWM_5, 3},
+    {P1_3, PWM_1, 3}, {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2},
+    {P1_4, PWM_2, 2}, {P1_4, PWM_4, 1}, {P1_4, PWM_6, 3},
+    {P1_5, PWM_2, 3}, {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2},
+    {P1_6, PWM_3, 2}, {P1_6, PWM_6, 1}, {P1_6, PWM_7, 3},
+    {P1_7, PWM_3, 3}, {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2},
+
+    {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3},
+    {P2_1, PWM_0, 3}, {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2},
+    {P2_2, PWM_1, 2}, {P2_2, PWM_2, 1}, {P2_2, PWM_5, 3},
+    {P2_3, PWM_1, 3}, {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2},
+    {P2_4, PWM_2, 2}, {P2_4, PWM_4, 1}, {P2_4, PWM_6, 3},
+    {P2_5, PWM_2, 3}, {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2},
+    {P2_6, PWM_3, 2}, {P2_6, PWM_6, 1}, {P2_6, PWM_7, 3},
+    {P2_7, PWM_3, 3}, {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2},
+
+    {P6_0, PWM_0, 1}, {P6_0, PWM_0, 2}, {P6_0, PWM_4, 3},
+    {P6_1, PWM_0, 3}, {P6_1, PWM_1, 1}, {P6_1, PWM_4, 2},
+    {P6_2, PWM_1, 2}, {P6_2, PWM_2, 1}, {P6_2, PWM_5, 3},
+    {P6_3, PWM_1, 3}, {P6_3, PWM_3, 1}, {P6_3, PWM_5, 2},
+    {P6_4, PWM_2, 2}, {P6_4, PWM_4, 1}, {P6_4, PWM_6, 3},
+    {P6_5, PWM_2, 3}, {P6_5, PWM_5, 1}, {P6_5, PWM_6, 2},
+    {P6_6, PWM_3, 2}, {P6_6, PWM_6, 1}, {P6_6, PWM_7, 3},
+    {P6_7, PWM_3, 3}, {P6_7, PWM_7, 1}, {P6_7, PWM_7, 2},
+    
+    {P7_0, PWM_0, 1}, {P7_0, PWM_0, 2}, {P7_0, PWM_4, 3},
+    {P7_1, PWM_0, 3}, {P7_1, PWM_1, 1}, {P7_1, PWM_4, 2},
+    {P7_2, PWM_1, 2}, {P7_2, PWM_2, 1}, {P7_2, PWM_5, 3},
+    {P7_3, PWM_1, 3}, {P7_3, PWM_3, 1}, {P7_3, PWM_5, 2},
+    {P7_4, PWM_2, 2}, {P7_4, PWM_4, 1}, {P7_4, PWM_6, 3},
+    {P7_5, PWM_2, 3}, {P7_5, PWM_5, 1}, {P7_5, PWM_6, 2},
+    {P7_6, PWM_3, 2}, {P7_6, PWM_6, 1}, {P7_6, PWM_7, 3},
+    {P7_7, PWM_3, 3}, {P7_7, PWM_7, 1}, {P7_7, PWM_7, 2},
+    {NC,   NC,    0}
+};
+
+/************ADC***************/
+const PinMap PinMap_ADC[] = {
+    {AIN_0P, ADC, 0},
+    {AIN_1P, ADC, 0},
+    {AIN_2P, ADC, 0},
+    {AIN_3P, ADC, 0},
+    {AIN_4P, ADC, 0},
+    {AIN_5P, ADC, 0},
+    {AIN_6P, ADC, 0},
+    {AIN_7P, ADC, 0},
+
+    {AIN_0N, ADC, 0},
+    {AIN_1N, ADC, 0},
+    {AIN_2N, ADC, 0},
+    {AIN_3N, ADC, 0},
+    {AIN_4N, ADC, 0},
+    {AIN_5N, ADC, 0},
+    {AIN_6N, ADC, 0},
+    {AIN_7N, ADC, 0},
+    
+    {AIN_0D, ADC, 1},
+    {AIN_1D, ADC, 1},
+    {AIN_2D, ADC, 1},
+    {AIN_3D, ADC, 1},
+    {AIN_4D, ADC, 1},
+    {AIN_5D, ADC, 1},
+    {AIN_6D, ADC, 1},
+    {AIN_7D, ADC, 1},
+    {NC,     NC,  0}
+};
+
+/************DAC***************/
+const PinMap PinMap_DAC[] = {
+    {AOUT_AO, DAC0, 0},
+    {AOUT_BO, DAC1, 0},
+    {AOUT_CO, DAC2, 0},
+    {AOUT_DO, DAC3, 0},
+    {NC,      NC,   0}
+};

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.h

@@ -0,0 +1,65 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+/************I2C***************/
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+/************UART***************/
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+extern const PinMap PinMap_UART_CTS[];
+extern const PinMap PinMap_UART_RTS[];
+
+/************SPI***************/
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+/************PWM***************/
+extern const PinMap PinMap_PWM[];
+
+/************ADC***************/
+extern const PinMap PinMap_ADC[];
+
+/************DAC***************/
+extern const PinMap PinMap_DAC[];
+
+#endif

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/PortNames.h

@@ -0,0 +1,55 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0,
+    Port1 = 1,
+    Port2 = 2,
+    Port3 = 3,
+    Port4 = 4,
+    Port5 = 5,
+    Port6 = 6,
+    Port7 = 7
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PeripheralNames.h

@@ -0,0 +1,86 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    UART_0 = MXC_BASE_UART0,
+    UART_1 = MXC_BASE_UART1,
+    STDIO_UART = UART_1
+} UARTName;
+
+typedef enum {
+    I2C_0 = MXC_BASE_I2CM0,
+    I2C_1 = MXC_BASE_I2CM1
+} I2CName;
+
+typedef enum {
+    SPI_0 = MXC_BASE_SPI0,
+    SPI_1 = MXC_BASE_SPI1,
+    SPI_2 = MXC_BASE_SPI2
+} SPIName;
+
+typedef enum {
+    PWM_0 = MXC_BASE_PT0,
+    PWM_1 = MXC_BASE_PT1,
+    PWM_2 = MXC_BASE_PT2,
+    PWM_3 = MXC_BASE_PT3,
+    PWM_4 = MXC_BASE_PT4,
+    PWM_5 = MXC_BASE_PT5,
+    PWM_6 = MXC_BASE_PT6,
+    PWM_7 = MXC_BASE_PT7
+} PWMName;
+
+typedef enum {
+    ADC = MXC_BASE_ADC
+} ADCName;
+
+typedef enum {
+    DAC0 = MXC_BASE_DAC0,
+    DAC1 = MXC_BASE_DAC1,
+    DAC2 = MXC_BASE_DAC2,
+    DAC3 = MXC_BASE_DAC3,
+} DACName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/PinNames.h

@@ -0,0 +1,267 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "gpio_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT  = MXC_V_GPIO_OUT_MODE_HIGH_Z,
+    PIN_OUTPUT = MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE
+} PinDirection;
+
+#define PORT_SHIFT  12
+#define PINNAME_TO_PORT(name)   ((unsigned int)(name) >> PORT_SHIFT)
+#define PINNAME_TO_PIN(name)    ((unsigned int)(name) & ~(0xFFFFFFFF << PORT_SHIFT))
+
+typedef enum {
+    P0_0 = (0 << PORT_SHIFT) | 0,
+    P0_1 = (0 << PORT_SHIFT) | 1,
+    P0_2 = (0 << PORT_SHIFT) | 2,
+    P0_3 = (0 << PORT_SHIFT) | 3,
+    P0_4 = (0 << PORT_SHIFT) | 4,
+    P0_5 = (0 << PORT_SHIFT) | 5,
+    P0_6 = (0 << PORT_SHIFT) | 6,
+    P0_7 = (0 << PORT_SHIFT) | 7,
+
+    P1_0 = (1 << PORT_SHIFT) | 0,
+    P1_1 = (1 << PORT_SHIFT) | 1,
+    P1_2 = (1 << PORT_SHIFT) | 2,
+    P1_3 = (1 << PORT_SHIFT) | 3,
+    P1_4 = (1 << PORT_SHIFT) | 4,
+    P1_5 = (1 << PORT_SHIFT) | 5,
+    P1_6 = (1 << PORT_SHIFT) | 6,
+    P1_7 = (1 << PORT_SHIFT) | 7,
+
+    P2_0 = (2 << PORT_SHIFT) | 0,
+    P2_1 = (2 << PORT_SHIFT) | 1,
+    P2_2 = (2 << PORT_SHIFT) | 2,
+    P2_3 = (2 << PORT_SHIFT) | 3,
+    P2_4 = (2 << PORT_SHIFT) | 4,
+    P2_5 = (2 << PORT_SHIFT) | 5,
+    P2_6 = (2 << PORT_SHIFT) | 6,
+    P2_7 = (2 << PORT_SHIFT) | 7,
+
+    P3_0 = (3 << PORT_SHIFT) | 0,
+    P3_1 = (3 << PORT_SHIFT) | 1,
+    P3_2 = (3 << PORT_SHIFT) | 2,
+    P3_3 = (3 << PORT_SHIFT) | 3,
+    P3_4 = (3 << PORT_SHIFT) | 4,
+    P3_5 = (3 << PORT_SHIFT) | 5,
+    P3_6 = (3 << PORT_SHIFT) | 6,
+    P3_7 = (3 << PORT_SHIFT) | 7,
+
+    P4_0 = (4 << PORT_SHIFT) | 0,
+    P4_1 = (4 << PORT_SHIFT) | 1,
+    P4_2 = (4 << PORT_SHIFT) | 2,
+    P4_3 = (4 << PORT_SHIFT) | 3,
+    P4_4 = (4 << PORT_SHIFT) | 4,
+    P4_5 = (4 << PORT_SHIFT) | 5,
+    P4_6 = (4 << PORT_SHIFT) | 6,
+    P4_7 = (4 << PORT_SHIFT) | 7,
+
+    P5_0 = (5 << PORT_SHIFT) | 0,
+    P5_1 = (5 << PORT_SHIFT) | 1,
+    P5_2 = (5 << PORT_SHIFT) | 2,
+    P5_3 = (5 << PORT_SHIFT) | 3,
+    P5_4 = (5 << PORT_SHIFT) | 4,
+    P5_5 = (5 << PORT_SHIFT) | 5,
+    P5_6 = (5 << PORT_SHIFT) | 6,
+    P5_7 = (5 << PORT_SHIFT) | 7,
+
+    P6_0 = (6 << PORT_SHIFT) | 0,
+    P6_1 = (6 << PORT_SHIFT) | 1,
+    P6_2 = (6 << PORT_SHIFT) | 2,
+    P6_3 = (6 << PORT_SHIFT) | 3,
+    P6_4 = (6 << PORT_SHIFT) | 4,
+    P6_5 = (6 << PORT_SHIFT) | 5,
+    P6_6 = (6 << PORT_SHIFT) | 6,
+    P6_7 = (6 << PORT_SHIFT) | 7,
+
+    P7_0 = (7 << PORT_SHIFT) | 0,
+    P7_1 = (7 << PORT_SHIFT) | 1,
+    P7_2 = (7 << PORT_SHIFT) | 2,
+    P7_3 = (7 << PORT_SHIFT) | 3,
+    P7_4 = (7 << PORT_SHIFT) | 4,
+    P7_5 = (7 << PORT_SHIFT) | 5,
+    P7_6 = (7 << PORT_SHIFT) | 6,
+    P7_7 = (7 << PORT_SHIFT) | 7,
+
+    // Analog ADC pins
+    AIN_0P = (0xA << PORT_SHIFT) | 0,
+    AIN_1P = (0xA << PORT_SHIFT) | 1,
+    AIN_2P = (0xA << PORT_SHIFT) | 2,
+    AIN_3P = (0xA << PORT_SHIFT) | 3,
+    AIN_4P = (0xA << PORT_SHIFT) | 4,
+    AIN_5P = (0xA << PORT_SHIFT) | 5,
+    AIN_6P = (0xA << PORT_SHIFT) | 6,
+    AIN_7P = (0xA << PORT_SHIFT) | 7,
+
+    AIN_0N = (0xB << PORT_SHIFT) | 0,
+    AIN_1N = (0xB << PORT_SHIFT) | 1,
+    AIN_2N = (0xB << PORT_SHIFT) | 2,
+    AIN_3N = (0xB << PORT_SHIFT) | 3,
+    AIN_4N = (0xB << PORT_SHIFT) | 4,
+    AIN_5N = (0xB << PORT_SHIFT) | 5,
+    AIN_6N = (0xB << PORT_SHIFT) | 6,
+    AIN_7N = (0xB << PORT_SHIFT) | 7,
+
+    // Analog differential ADC
+    AIN_0D = (0xC << PORT_SHIFT) | 0,
+    AIN_1D = (0xC << PORT_SHIFT) | 1,
+    AIN_2D = (0xC << PORT_SHIFT) | 2,
+    AIN_3D = (0xC << PORT_SHIFT) | 3,
+    AIN_4D = (0xC << PORT_SHIFT) | 4,
+    AIN_5D = (0xC << PORT_SHIFT) | 5,
+    AIN_6D = (0xC << PORT_SHIFT) | 6,
+    AIN_7D = (0xC << PORT_SHIFT) | 7,
+
+    // OPAMP Positive supply pins
+    AOUT_AP = (0xD << PORT_SHIFT) | 0,
+    AOUT_BP = (0xD << PORT_SHIFT) | 1,
+    AOUT_CP = (0xD << PORT_SHIFT) | 2,
+    AOUT_DP = (0xD << PORT_SHIFT) | 3,
+
+    // OPAMP Negative supply pins
+    AOUT_AN = (0xE << PORT_SHIFT) | 0,
+    AOUT_BN = (0xE << PORT_SHIFT) | 1,
+    AOUT_CN = (0xE << PORT_SHIFT) | 2,
+    AOUT_DN = (0xE << PORT_SHIFT) | 3,
+
+    // DAC Output pins
+    AOUT_AO = (0xF << PORT_SHIFT) | 0,
+    AOUT_BO = (0xF << PORT_SHIFT) | 1,
+    AOUT_CO = (0xF << PORT_SHIFT) | 2,
+    AOUT_DO = (0xF << PORT_SHIFT) | 3,
+
+    LED_GREEN  = P7_4,
+    LED_RED    = P7_0,
+    LED_YELLOW = P6_6,
+    LED_BLUE   = P7_6,
+
+    // mbed original LED naming
+    LED1 = LED_RED,
+    LED2 = LED_GREEN,
+    LED3 = LED_BLUE,
+    LED4 = LED_YELLOW,
+
+    // Push button
+    SW2 = P6_4,
+    SW3 = P6_5,
+
+    // UART pins
+    USBTX = P7_3,
+    USBRX = P7_2,
+    STDIO_UART_TX = USBTX,
+    STDIO_UART_RX = USBRX,
+
+    // I2C pins
+    I2C0_SCL = P2_4,
+    I2C0_SDA = P2_5,
+
+    I2C1_SCL = P2_7,
+    I2C1_SDA = P2_6,
+
+    // UART pins
+    UART0_RX  = P1_0,
+    UART0_TX  = P1_1,
+    UART0_CTS = P1_2,
+    UART0_RTS = P1_3,
+
+    UART1_RX  = P1_2,
+    UART1_TX  = P1_3,
+    UART1_CTS = P2_6,
+    UART1_RTS = P2_7,
+
+    // SPI pins
+    SPI0_SCK  = P6_0,
+    SPI0_MOSI = P6_1,
+    SPI0_MISO = P6_2,
+    SPI0_SS   = P6_3,
+
+    SPI2_SCK  = P2_0,
+    SPI2_MOSI = P2_1,
+    SPI2_MISO = P2_2,
+    SPI2_SS   = P2_3,
+
+    // Arduino Headers
+    D0  = P1_0,
+    D1  = P1_1,
+    D2  = P1_2,
+    D3  = P1_3,
+    D4  = P1_4,
+    D5  = P1_5,
+    D6  = P1_6,
+    D7  = P1_7,
+    D8  = P2_5,
+    D9  = P2_4,
+    D10 = P2_3,
+    D11 = P2_1,
+    D12 = P2_2,
+    D13 = P2_0,
+    D14 = P2_6,
+    D15 = P2_7,
+    A0  = AIN_0P,
+    A1  = AIN_1P,
+    A2  = AIN_2P,
+    A3  = AIN_3P,
+    A4  = AIN_4P,
+    A5  = AIN_5P,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullUp,
+    OpenDrain,
+    PullNone,
+    PullDefault = PullUp
+} PinMode;
+
+typedef enum {
+    LED_ON = 0,
+    LED_OFF = 1
+} LedStates;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/TARGET_MAX32600MBED/low_level_init.c

@@ -0,0 +1,88 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "cmsis.h"
+#include "gpio_regs.h"
+#include "clkman_regs.h"
+
+/* Application developer should override where necessary with different external HFX source */
+#ifndef __SYSTEM_HFX
+#define __SYSTEM_HFX 24000000
+#endif
+
+//******************************************************************************
+// This function will get called early in system initialization
+void low_level_init(void)
+{
+    /* wait for the RO to stabilize */
+    while (!(MXC_CLKMAN->intfl & MXC_F_CLKMAN_INTFL_RING_STABLE));
+
+    /* Configure and enable the oscillator */
+    if (!(MXC_CLKMAN->clk_config & MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE)) {
+
+        MXC_CLKMAN->clk_config = (0x4 << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS);
+
+        /* Enable the external crystal */
+        MXC_CLKMAN->clk_config |= MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE;
+    }
+
+    /* Wait for external crystal to stabilize */
+    for (volatile int waitcnt = 0; waitcnt < 0x4000; waitcnt++);    // 0x4000 ~10ms 0x10000 ~35ms, 0x20000 ~75ms
+
+    /* Configure the PLL */
+    uint32_t clk_config = MXC_CLKMAN->clk_config;
+    clk_config  = (clk_config & ~MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT) | (MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS);
+
+#if (__SYSTEM_HFX == 8000000)
+    clk_config  = (clk_config & ~MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT) | (MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS);
+#elif (__SYSTEM_HFX == 12000000)
+    clk_config  = (clk_config & ~MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT) | (MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS);
+#elif (__SYSTEM_HFX == 24000000)
+    clk_config  = (clk_config & ~MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT) | (MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS);
+#else
+#error Invalid __SYSTEM_HFX setting
+#endif
+
+    clk_config |=  MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE;
+    clk_config &= ~MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS;
+    clk_config  = (clk_config & ~MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT) | (MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS);
+    MXC_CLKMAN->clk_config = clk_config;
+
+    /* Enable the PLL and wait for stable */
+    MXC_CLKMAN->clk_config |= (MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE | MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N);
+    while (!(MXC_CLKMAN->intfl & MXC_F_CLKMAN_INTFL_PLL_STABLE));
+
+    /* Switch to the PLL */
+    MXC_CLKMAN->clk_ctrl = (MXC_CLKMAN->clk_ctrl & ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) |
+                           ((MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS));
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/analogin_api.c

@@ -0,0 +1,147 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "mbed_assert.h"
+#include "analogin_api.h"
+#include "clkman_regs.h"
+#include "pwrman_regs.h"
+#include "afe_regs.h"
+#include "PeripheralPins.h"
+
+#define PGA_TRK_CNT     0x1F
+#define ADC_ACT_CNT     0x1
+#define ADC_PGA_CNT     0x1
+#define ADC_ACQ_CNT     0x1
+#define ADC_SLP_CNT     0x1
+ 
+//******************************************************************************
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    // Make sure pin is an analog pin we can use for ADC
+    MBED_ASSERT((ADCName)pinmap_peripheral(pin, PinMap_ADC) != (ADCName)NC);
+
+    // Set the object pointer
+    obj->adc = MXC_ADC;
+    obj->adccfg = MXC_ADCCFG;
+    obj->adc_fifo = MXC_ADC_FIFO;
+    obj->adc_pin = pin;
+
+    // Set the ADC clock to the system clock frequency
+    MXC_SET_FIELD(&MXC_CLKMAN->clk_ctrl, MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT,
+        (MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N | (MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM << 
+        MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS)));
+
+    // Enable AFE power
+    MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED;
+
+    // Setup and hold window
+    MXC_SET_FIELD(&obj->adc->tg_ctrl0, MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT, PGA_TRK_CNT);
+
+    // Setup sampling count and timing
+    MXC_SET_FIELD(&obj->adc->tg_ctrl1, (MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT | 
+        MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT | MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT),
+        ((ADC_PGA_CNT << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS) | 
+        (ADC_ACQ_CNT << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS) |
+        (ADC_SLP_CNT << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS) |
+        (MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT)));
+}
+
+//******************************************************************************
+float analogin_read(analogin_t *obj)
+{
+    // Convert integer to float
+    return (((float)analogin_read_u16(obj)/(float)0xFFFF));
+}
+
+//******************************************************************************
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    // Set the pin to take readings from
+    unsigned mux_pos;
+    unsigned diff = 0;
+    if(obj->adc_pin >> PORT_SHIFT == 0xB) {
+        mux_pos = (obj->adc_pin & 0xF) + 8;
+    } else {
+        mux_pos = (obj->adc_pin & 0xF);
+    }
+
+    if(obj->adc_pin >> PORT_SHIFT == 0xC) {
+        diff = 1;
+        mux_pos = (obj->adc_pin & 0xF) + 8;
+    }
+
+    // Reset the ADC
+    obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_RST;
+
+    // Enable the ADC
+    obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_EN;
+
+    // Setup the ADC clock
+    MXC_SET_FIELD(&obj->adc->ctrl0, (MXC_F_ADC_CTRL0_ADC_MODE | MXC_F_ADC_CTRL0_AVG_MODE |
+        MXC_F_ADC_CTRL0_ADC_CLK_MODE | MXC_F_ADC_CTRL0_ADC_BI_POL),
+        ((MXC_E_ADC_MODE_SMPLCNT_FULL_RATE << MXC_F_ADC_CTRL0_ADC_MODE_POS) | 
+        (MXC_E_ADC_AVG_MODE_FILTER_OUTPUT << MXC_F_ADC_CTRL0_AVG_MODE_POS) |
+        (0x2 << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS) |
+        MXC_F_ADC_CTRL0_ADC_CLK_EN));
+
+    // Setup the input multiplexor
+    MXC_SET_FIELD(&obj->adc->pga_ctrl, (MXC_F_ADC_PGA_CTRL_MUX_CH_SEL | 
+        MXC_F_ADC_PGA_CTRL_MUX_DIFF | MXC_F_ADC_PGA_CTRL_PGA_GAIN),
+        ((mux_pos << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS) |
+        (diff << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS)));
+
+    // Setup voltage reference
+    MXC_SET_FIELD(&MXC_AFE->ctrl1, MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL, 
+        (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP |
+        (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS)));
+
+    // Clear the done bit
+    obj->adc->intr = MXC_F_ADC_INTR_DONE_IF;
+
+    // Take one sample
+    obj->adc->tg_ctrl0 |= (1 << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS);
+
+    // Set the start bit to take the sample
+    obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_START;
+
+    // Wait for the conversion to complete
+    while(!(obj->adc->intr & MXC_F_ADC_INTR_DONE_IF)) {}
+
+    // Get sample from the fifo
+    uint16_t sample = (uint16_t)(obj->adc->out & 0xFFFF);
+    
+    // Disable ADC
+    obj->adc->ctrl0 &= ~MXC_F_ADC_CTRL0_CPU_ADC_EN;
+
+    return (sample - 1);
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/analogout_api.c

@@ -0,0 +1,212 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "mbed_assert.h"
+#include "analogout_api.h"
+#include "clkman_regs.h"
+#include "pwrman_regs.h"
+#include "afe_regs.h"
+#include "PeripheralPins.h"
+
+//******************************************************************************
+void analogout_init(dac_t *obj, PinName pin)
+{
+    // Make sure pin is an analog pin we can use for ADC
+    DACName dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+    MBED_ASSERT((DACName)dac != (DACName)NC);
+
+    // Set the object pointer
+    obj->dac = ((mxc_dac_regs_t*)MXC_DAC_GET_DAC((pin & 0x3)));
+    obj->dac_fifo = ((mxc_dac_fifo_t*)MXC_DAC_GET_FIFO((pin & 0x3)));
+    obj->index = (pin & 0x3);
+
+    // Set the ADC clock to the system clock frequency
+    MXC_SET_FIELD(&MXC_CLKMAN->clk_ctrl, MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT,
+        (MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N | (MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM << 
+        MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS)));
+
+    
+    // Setup the OPAMP in follower mode
+    switch(obj->index) {
+        case 0:
+            // Enable DAC clock
+            MXC_CLKMAN->clk_ctrl_14_dac0 = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
+
+            // Enable OPAMP
+            MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP0;
+
+            // Set the positive and negative inputs
+            MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_A | 
+                MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0), 
+                ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP0_POS) |
+                (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP0_POS) |
+                (0x0 << MXC_F_AFE_CTRL4_DAC_SEL_A_POS)));
+
+            // Enable N and P channel inputs
+            MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP0 | 
+                MXC_F_AFE_CTRL3_EN_NCH_OPAMP0);
+        break;
+        case 1:
+            // Enable DAC clock
+            MXC_CLKMAN->clk_ctrl_15_dac1 = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
+
+            // Enable OPAMP
+            MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP1;
+
+            // Set the positive and negative inputs
+            MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_B | 
+                MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1), 
+                ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP1_POS) |
+                (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP1_POS) |
+                (0x1 << MXC_F_AFE_CTRL4_DAC_SEL_B_POS)));
+
+            // Enable N and P channel inputs
+            MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP1 | 
+                MXC_F_AFE_CTRL3_EN_NCH_OPAMP1);
+
+        break;
+        case 2:
+            // Enable DAC clock
+            MXC_CLKMAN->clk_ctrl_16_dac2 = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
+
+            // Enable OPAMP
+            MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP2;
+
+            // Set the positive and negative inputs
+            MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_C | 
+                MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2), 
+                ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP2_POS) |
+                (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP2_POS) |
+                (0x2 << MXC_F_AFE_CTRL4_DAC_SEL_C_POS)));
+
+            // Enable N and P channel inputs
+            MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP2 | 
+                MXC_F_AFE_CTRL3_EN_NCH_OPAMP2);
+        break;
+        case 3:
+            // Enable DAC clock
+            MXC_CLKMAN->clk_ctrl_17_dac3 = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
+
+            // Enable OPAMP
+            MXC_AFE->ctrl5 &= ~MXC_F_AFE_CTRL5_OP_CMP3;
+
+            // Set the positive and negative inputs
+            MXC_SET_FIELD(&MXC_AFE->ctrl4, (MXC_F_AFE_CTRL4_DAC_SEL_D | 
+                MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3 | MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3), 
+                ((0x1 << MXC_F_AFE_CTRL4_P_IN_SEL_OPAMP3_POS) |
+                (0x1 << MXC_F_AFE_CTRL4_N_IN_SEL_OPAMP3_POS) |
+                (0x3 << MXC_F_AFE_CTRL4_DAC_SEL_D_POS)));
+
+            // Enable N and P channel inputs
+            MXC_AFE->ctrl3 |= (MXC_F_AFE_CTRL3_EN_PCH_OPAMP3 | 
+                MXC_F_AFE_CTRL3_EN_NCH_OPAMP3);
+        break;
+    }
+
+    // Enable AFE power
+    MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED;
+
+    // Setup internal voltage references
+    MXC_SET_FIELD(&MXC_AFE->ctrl1, (MXC_F_AFE_CTRL1_REF_DAC_VOLT_SEL | MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL), 
+        (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP |
+        (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS)));
+
+    // Disable interpolation
+    obj->dac->ctrl0 &= MXC_F_DAC_CTRL0_INTERP_MODE;
+}
+
+//******************************************************************************
+void analogout_write(dac_t *obj, float value)
+{
+    analogout_write_u16(obj, (uint16_t)((value/1.0) * 0xFFFF));
+}
+
+//******************************************************************************
+void analogout_write_u16(dac_t *obj, uint16_t value)
+{
+    // Enable the OPAMP
+        // Setup the OPAMP in follower mode
+    switch(obj->index) {
+        case 0:
+            MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP0;
+        break;
+        case 1:
+            MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP1;
+        break;
+        case 2:
+            MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP2;
+        break;
+        case 3:
+            MXC_AFE->ctrl3 |= MXC_F_AFE_CTRL3_POWERUP_OPAMP3;
+        break;
+    }
+
+    // Output 1 sample with minimal delay
+    obj->dac->rate |= 0x1;
+
+    // Set the start mode to output once data is in the FIFO
+    obj->dac->ctrl0 &= ~(MXC_F_DAC_CTRL0_START_MODE | MXC_F_DAC_CTRL0_OP_MODE);
+
+    // Enable the DAC
+    obj->dac->ctrl0 |= (MXC_F_DAC_CTRL0_POWER_MODE_2 | 
+        MXC_F_DAC_CTRL0_POWER_MODE_1_0 | MXC_F_DAC_CTRL0_POWER_ON | 
+        MXC_F_DAC_CTRL0_CLOCK_GATE_EN | MXC_F_DAC_CTRL0_CPU_START);
+
+    if(obj->index < 2) {
+        obj->out = (value);
+        obj->dac_fifo->output_16 = (obj->out);
+
+    } else {
+        // Convert 16 bits to 8 bits
+        obj->out = (value >> 8);
+        obj->dac_fifo->output_8 = (obj->out);
+    }
+}
+
+//******************************************************************************
+float analogout_read(dac_t *obj)
+{
+    return (((float)analogout_read_u16(obj) / (float)0xFFFF) * 1.5);
+}
+
+//******************************************************************************
+uint16_t analogout_read_u16(dac_t *obj)
+{
+    if(obj->index < 2) {
+        // Convert 12 bits to 16 bits
+        return (obj->out << 4);
+    } else {
+        // Convert 8 bits to 16 bits
+        return (obj->out << 8);
+    }
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/device.h

@@ -0,0 +1,72 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+ 
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_SERIAL_FC        1
+
+#define DEVICE_SPI              1
+
+#define DEVICE_I2C              1
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_ANALOGIN         1
+
+#define DEVICE_ANALOGOUT        1
+
+#define DEVICE_RTC              1
+
+#define DEVICE_SLEEP            1
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_ERROR_PATTERN    1
+
+#define DEVICE_CAN              0
+#define DEVICE_ETHERNET         0
+
+#include "objects.h"
+
+#endif

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_api.c

@@ -0,0 +1,94 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "gpio_regs.h"
+#include "clkman_regs.h"
+
+uint32_t gpio_set(PinName name)
+{
+    MBED_ASSERT(name != (PinName)NC);
+    pin_function(name, 0);
+    return 1 << PINNAME_TO_PIN(name);
+}
+
+void gpio_init(gpio_t *obj, PinName name)
+{
+    obj->name = name;
+    if (name == (PinName)NC) {
+        return;
+    }
+
+    unsigned int port = PINNAME_TO_PORT(name);
+    unsigned int pin = PINNAME_TO_PIN(name);
+
+    obj->reg_out = (uint32_t*)BITBAND(&MXC_GPIO->out_val[port], pin);
+    obj->reg_in = (uint32_t*)BITBAND(&MXC_GPIO->in_val[port], pin);
+
+    /* Ensure that the GPIO clock is enabled */
+    if (MXC_CLKMAN->clk_ctrl_1_gpio == MXC_E_CLKMAN_CLK_SCALE_DISABLED) {
+        MXC_CLKMAN->clk_ctrl_1_gpio = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
+    }
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    pin_mode(obj->name, mode);
+}
+
+void pin_dir(PinName name, PinDirection direction)
+{
+    MBED_ASSERT(name != (PinName)NC);
+
+    unsigned int port = PINNAME_TO_PORT(name);
+    unsigned int pin = PINNAME_TO_PIN(name);
+
+    /* Set function */
+    MXC_GPIO->func_sel[port] &= ~(0xF << (4 * pin));
+
+    /* Normal input is always enabled */
+    MXC_GPIO->in_mode[port] &= ~(0xF << (4 * pin));
+
+    /* Set requested output mode */
+    uint32_t out_mode = MXC_GPIO->out_mode[port];
+    out_mode &= ~(0xF << (4 * pin));
+    out_mode |= (direction << (4 * pin));
+    MXC_GPIO->out_mode[port] = out_mode;
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    pin_dir(obj->name, direction);
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_irq_api.c

@@ -0,0 +1,167 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "mbed_error.h"
+
+#define NUM_PORTS           8
+#define NUM_PINS_PER_PORT   8
+
+static uint32_t ids[NUM_PORTS][NUM_PINS_PER_PORT] = {{0}};
+static gpio_irq_handler irq_handler;
+
+static void handle_irq(unsigned int port)
+{
+    uint32_t intfl, in_val;
+    uint32_t mask;
+    unsigned int pin;
+
+    /* Read pin state */
+    in_val = MXC_GPIO->in_val[port];
+
+    /* Read interrupts */
+    intfl = MXC_GPIO->intfl[port] & MXC_GPIO->inten[port];
+    
+    mask = 1;
+
+    for (pin = 0; pin < NUM_PINS_PER_PORT; pin++) {
+        if (intfl & mask) {
+            if (ids[port][pin]) {
+                if (in_val & mask) {
+                    irq_handler(ids[port][pin], IRQ_RISE);
+                } else {
+                    irq_handler(ids[port][pin], IRQ_FALL);
+                }
+            }
+            MXC_GPIO->intfl[port] = mask;    /* clear interrupt */
+        }
+        mask <<= 1;
+    }
+}
+
+void gpio_irq_0(void) { handle_irq(0); }
+void gpio_irq_1(void) { handle_irq(1); }
+void gpio_irq_2(void) { handle_irq(2); }
+void gpio_irq_3(void) { handle_irq(3); }
+void gpio_irq_4(void) { handle_irq(4); }
+void gpio_irq_5(void) { handle_irq(5); }
+void gpio_irq_6(void) { handle_irq(6); }
+void gpio_irq_7(void) { handle_irq(7); }
+
+int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint32_t id)
+{
+    if (name == NC)
+        return -1;
+
+    uint8_t port = PINNAME_TO_PORT(name);
+    uint8_t pin = PINNAME_TO_PIN(name);
+
+    if ((port > NUM_PORTS) || (pin > NUM_PINS_PER_PORT)) {
+        return 1;
+    }
+
+    obj->port = port;
+    obj->pin = pin;
+
+    irq_handler = handler;
+
+    ids[port][pin] = id;
+
+    /* register handlers */
+    NVIC_SetVector(GPIO_P0_IRQn, (uint32_t)gpio_irq_0);
+    NVIC_SetVector(GPIO_P1_IRQn, (uint32_t)gpio_irq_1);
+    NVIC_SetVector(GPIO_P2_IRQn, (uint32_t)gpio_irq_2);
+    NVIC_SetVector(GPIO_P3_IRQn, (uint32_t)gpio_irq_3);
+    NVIC_SetVector(GPIO_P4_IRQn, (uint32_t)gpio_irq_4);
+    NVIC_SetVector(GPIO_P5_IRQn, (uint32_t)gpio_irq_5);
+    NVIC_SetVector(GPIO_P6_IRQn, (uint32_t)gpio_irq_6);
+    NVIC_SetVector(GPIO_P7_IRQn, (uint32_t)gpio_irq_7);
+
+    /* disable the interrupt locally */
+    MXC_GPIO->int_mode[port] &= ~(0xF << (pin*4));
+
+    /* clear a pending request */
+    MXC_GPIO->intfl[port] = 1 << pin;
+
+    /* enable the requested interrupt */
+    MXC_GPIO->inten[port] |= (1 << pin);
+    NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    /* disable interrupt */
+    MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
+    MXC_GPIO->int_mode[obj->port] &= ~(0xF << (obj->pin*4));
+
+    ids[obj->port][obj->pin] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    uint32_t int_mode = MXC_GPIO->int_mode[obj->port];
+    uint32_t curr_mode = (int_mode >> (obj->pin*4)) & 0x3;   /* only supporting edge interrupts */
+
+    uint32_t new_mode = curr_mode;
+    if (event == IRQ_FALL) {
+        if (enable) {
+            new_mode |= 0x1;
+        } else {
+            new_mode &= ~0x1;
+        }
+    } else if (event == IRQ_RISE) {
+        if (enable) {
+            new_mode |= 0x2;
+        } else {
+            new_mode &= ~0x2;
+        }
+    }
+
+    int_mode &= ~(0xF << (obj->pin*4));
+    int_mode |= (new_mode << (obj->pin*4));
+    MXC_GPIO->int_mode[obj->port] = int_mode;
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    MXC_GPIO->inten[obj->port] |= (1 << obj->pin);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    MXC_GPIO->inten[obj->port] &= ~(1 << obj->pin);
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/gpio_object.h

@@ -0,0 +1,71 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName name;
+    __IO uint32_t *reg_out;
+    __I  uint32_t *reg_in;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+    MBED_ASSERT(obj->name != (PinName)NC);
+    *obj->reg_out = !!value;
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+    MBED_ASSERT(obj->name != (PinName)NC);
+    return *obj->reg_in;
+}
+
+void pin_dir(PinName name, PinDirection direction);
+
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->name != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/i2c_api.c

@@ -0,0 +1,405 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#include "mbed_assert.h"
+#include "i2c_api.h"
+#include "cmsis.h"
+#include "i2cm_regs.h"
+#include "clkman_regs.h"
+#include "ioman_regs.h"
+#include "PeripheralPins.h"
+
+#define I2C_SLAVE_ADDR_READ_BIT     0x0001
+
+#ifndef MXC_I2CM_TX_TIMEOUT
+#define MXC_I2CM_TX_TIMEOUT         0x5000
+#endif
+
+#ifndef MXC_I2CM_RX_TIMEOUT
+#define MXC_I2CM_RX_TIMEOUT         0x5000
+#endif
+
+typedef enum {
+    /** 100KHz */
+    MXC_E_I2CM_SPEED_100KHZ = 0,
+    /** 400KHz */
+    MXC_E_I2CM_SPEED_400KHZ,
+    /** 1MHz */
+    MXC_E_I2CM_SPEED_1MHZ
+} i2cm_speed_t;
+
+/* Clock divider lookup table */
+static const uint32_t clk_div_table[3][8] = {
+    /* MXC_E_I2CM_SPEED_100KHZ */
+    {
+        /* 0:       */ 0, /* not supported */
+        /* 1: 6MHz  */ (( 3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | ( 7 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
+        /* 2: 8MHz  */ (( 4 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (10 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 48 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
+        /* 3: 12MHz */ (( 6 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (17 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 72 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
+        /* 4: 16MHz */ (( 8 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | ( 96 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
+        /* 5:       */ 0, /* not supported */
+        /* 6:       */ 0, /* not supported */
+        /* 7: 24MHz */ ((12 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (38 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (144 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
+    },
+    /* MXC_E_I2CM_SPEED_400KHZ */
+    {
+        /* 0:       */ 0, /* not supported */
+        /* 1:       */ 0, /* not supported */
+        /* 2:       */ 0, /* not supported */
+        /* 3: 12MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (1 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (18 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
+        /* 4: 16MHz */ ((2 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (2 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (24 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
+        /* 5:       */ 0, /* not supported */
+        /* 6:       */ 0, /* not supported */
+        /* 7: 24MHz */ ((3 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (5 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (36 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
+    },
+    /* MXC_E_I2CM_SPEED_1MHZ */
+    {
+        /* 0:       */ 0, /* not supported */
+        /* 1:       */ 0, /* not supported */
+        /* 2:       */ 0, /* not supported */
+        /* 3:       */ 0, /* not supported */
+        /* 4:       */ 0, /* not supported */
+        /* 5:       */ 0, /* not supported */
+        /* 6:       */ 0, /* not supported */
+        /* 7: 24MHz */ ((1 << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS) | (0 << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS) | (14 << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS)),
+    },
+};
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    // determine the I2C to use
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    mxc_i2cm_regs_t *i2c = (mxc_i2cm_regs_t*)pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT((int)i2c != NC);
+
+    obj->i2c = i2c;
+    obj->txfifo = (uint16_t*)MXC_I2CM_GET_BASE_TX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
+    obj->rxfifo = (uint16_t*)MXC_I2CM_GET_BASE_RX_FIFO(MXC_I2CM_BASE_TO_INSTANCE(i2c));
+    obj->start_pending = 0;
+	obj->stop_pending = 0;
+
+    // configure the pins
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+
+    // enable the clock
+    MXC_CLKMAN->clk_ctrl_6_i2cm = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
+
+    // reset module
+    i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
+    i2c->ctrl = 0;
+
+    // set default frequency at 100k
+    i2c_frequency(obj, 100000);
+
+    // set timeout to 255 ms and turn on the auto-stop option
+    i2c->timeout = (0xFF << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS) | MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN;
+
+    // enable tx_fifo and rx_fifo
+    i2c->ctrl |= (MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN);
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    // compute clock array index
+    int clki = ((SystemCoreClock + 1500000) / 3000000) - 1;
+
+    // get clock divider settings from lookup table
+    if ((hz < 400000) && (clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki] > 0)) {
+        obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_100KHZ][clki];
+    } else if ((hz < 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki] > 0)) {
+        obj->i2c->fs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_400KHZ][clki];
+    } else if ((hz >= 1000000) && (clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki] > 0)) {
+        obj->i2c->hs_clk_div = clk_div_table[MXC_E_I2CM_SPEED_1MHZ][clki];
+    }
+}
+
+static int write_tx_fifo(i2c_t *obj, const uint16_t data)
+{
+    int timeout = MXC_I2CM_TX_TIMEOUT;
+
+    while (*obj->txfifo) {
+        uint32_t intfl = obj->i2c->intfl;
+        if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
+            return I2C_ERROR_NO_SLAVE;
+        }
+        if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
+            return I2C_ERROR_BUS_BUSY;
+        }
+        timeout--;
+    }
+    *obj->txfifo = data;
+
+    return 0;
+}
+
+static int wait_tx_in_progress(i2c_t *obj)
+{
+    int timeout = MXC_I2CM_TX_TIMEOUT;
+
+    while ((obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS) && --timeout);
+
+    uint32_t intfl = obj->i2c->intfl;
+
+    if (intfl & MXC_F_I2CM_INTFL_TX_NACKED) {
+        i2c_reset(obj);
+        return I2C_ERROR_NO_SLAVE;
+    }
+
+    if (!timeout || (intfl & (MXC_F_I2CM_INTFL_TX_TIMEOUT | MXC_F_I2CM_INTFL_TX_LOST_ARBITR))) {
+        i2c_reset(obj);
+        return I2C_ERROR_BUS_BUSY;
+    }
+
+    return 0;
+}
+
+int i2c_start(i2c_t *obj)
+{
+    obj->start_pending = 1;
+    return 0;
+}
+
+int i2c_stop(i2c_t *obj)
+{
+    obj->start_pending = 0;
+    write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP);
+
+    return wait_tx_in_progress(obj);
+}
+
+void i2c_reset(i2c_t *obj)
+{
+    obj->i2c->ctrl = MXC_F_I2CM_CTRL_MSTR_RESET_EN;
+    obj->i2c->intfl = 0x3FF; // clear all interrupts
+    obj->i2c->ctrl = MXC_F_I2CM_CTRL_TX_FIFO_EN | MXC_F_I2CM_CTRL_RX_FIFO_EN;
+    obj->start_pending = 0;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+    int err;
+
+    // clear all interrupts
+    obj->i2c->intfl = 0x3FF;
+
+    if (obj->start_pending) {
+        obj->start_pending = 0;
+        data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_START;
+    } else {
+        data = (data & 0xFF) | MXC_S_I2CM_TRANS_TAG_TXDATA_ACK;
+    }
+
+    if ((err = write_tx_fifo(obj, data)) != 0) {
+        return err;
+    }
+
+    obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
+
+    return 0;
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+    uint16_t fifo_value;
+    int err;
+
+    // clear all interrupts
+    obj->i2c->intfl = 0x3FF;
+
+    if (last) {
+        fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_NACK;
+    } else {
+        fifo_value = MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT;
+    }
+
+    if ((err = write_tx_fifo(obj, fifo_value)) != 0) {
+        return err;
+    }
+
+    obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
+
+    int timeout = MXC_I2CM_RX_TIMEOUT;
+    while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
+            (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
+        if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+            break;
+        }
+    }
+
+    if (obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) {
+        obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
+        return *obj->rxfifo;
+    }
+
+    return -1;
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    int err, retval = 0;
+    int i;
+
+    if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+        return 0;
+    }
+
+    // clear all interrupts
+    obj->i2c->intfl = 0x3FF;
+
+    // write the address to the fifo
+    if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address))) != 0) { // start + addr (write)
+        return err;
+    }
+    obj->start_pending = 0;
+
+    // start the transaction
+    obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
+
+    // load as much of the cmd into the FIFO as possible
+    for (i = 0; i < length; i++) {
+        if ((err = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_TXDATA_ACK | data[i]))) != 0) { // cmd (expect ACK)
+            retval = (retval ? retval : err);
+            break;
+        }
+    }
+
+    if (stop) {
+		obj->stop_pending = 0;
+        if ((err = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
+            retval = (retval ? retval : err);
+        }
+
+        if ((err = wait_tx_in_progress(obj)) != 0) {
+            retval = (retval ? retval : err);
+        }
+    } else {
+        obj->stop_pending = 1;
+        int timeout = MXC_I2CM_TX_TIMEOUT;
+        // Wait for TX fifo to be empty
+        while(!(obj->i2c->intfl & MXC_F_I2CM_INTFL_TX_FIFO_EMPTY) && timeout--) {}
+    }
+
+    if (retval == 0) {
+        return length;
+    }
+
+    return retval;
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    int err, retval = 0;
+    int i = length;
+    int timeout;
+
+    if (!(obj->stop_pending) && (obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+        return 0;
+    }
+
+    // clear all interrupts
+    obj->i2c->intfl = 0x3FF;
+
+    // start + addr (read)
+    if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_START | address | I2C_SLAVE_ADDR_READ_BIT))) != 0) {
+        goto read_done;
+    }
+    obj->start_pending = 0;
+
+    while (i > 256) {
+        if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | 255))) != 0) {
+            goto read_done;
+        }
+        i -= 256;
+    }
+
+    if (i > 1) {
+        if ((retval = write_tx_fifo(obj, (MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT | (i - 2)))) != 0) {
+            goto read_done;
+        }
+    }
+
+    // start the transaction
+    obj->i2c->trans |= MXC_F_I2CM_TRANS_TX_START;
+
+    if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK)) != 0) { // NACK last data byte
+        goto read_done;
+    }
+
+    if (stop) {
+        if ((retval = write_tx_fifo(obj, MXC_S_I2CM_TRANS_TAG_STOP)) != 0) { // stop condition
+            goto read_done;
+        }
+    }
+
+    timeout = MXC_I2CM_RX_TIMEOUT;
+    i = 0;
+    while (i < length) {
+        while (!(obj->i2c->intfl & MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY) &&
+                (!(obj->i2c->bb & MXC_F_I2CM_BB_RX_FIFO_CNT))) {
+            if ((--timeout < 0) || !(obj->i2c->trans & MXC_F_I2CM_TRANS_TX_IN_PROGRESS)) {
+                retval = -3;
+                goto read_done;
+            }
+        }
+
+        timeout = MXC_I2CM_RX_TIMEOUT;
+
+        obj->i2c->intfl = MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY;
+
+        uint16_t temp = *obj->rxfifo;
+
+        if (temp & MXC_S_I2CM_RSTLS_TAG_EMPTY) {
+            continue;
+        }
+        data[i++] = (uint8_t) temp;
+    }
+
+read_done:
+
+    if (stop) {
+        obj->stop_pending = 0;
+        if ((err = wait_tx_in_progress(obj)) != 0) {
+            retval = (retval ? retval : err);
+        }
+    } else {
+        obj->stop_pending = 1;
+    }
+
+    if (retval == 0) {
+        return length;
+    }
+
+    return retval;
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/objects.h

@@ -0,0 +1,118 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+#include "gpio_object.h"
+#include "gpio_regs.h"
+#include "uart_regs.h"
+#include "i2cm_regs.h"
+#include "spi_regs.h"
+#include "pt_regs.h"
+#include "adc_regs.h"
+#include "dac_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    __IO uint32_t *reg_out;
+    __I  uint32_t *reg_in;
+};
+
+struct gpio_irq_s {
+    uint8_t port;
+    uint8_t pin;
+};
+
+struct serial_s {
+    int index;
+    mxc_uart_regs_t *uart;
+};
+
+struct i2c_s {
+    int index;
+    mxc_i2cm_regs_t *i2c;
+    volatile uint16_t *txfifo;
+    volatile uint16_t *rxfifo;
+    int start_pending;
+    int stop_pending;
+};
+
+struct spi_s {
+    int index;
+    mxc_spi_regs_t *spi;
+    mxc_spi_rxfifo_regs_t *rxfifo;
+    mxc_spi_txfifo_regs_t *txfifo;
+};
+
+struct pwmout_s {
+    mxc_pt_regs_t *pwm;
+    int period;
+    int pulse_width;
+};
+
+struct analogin_s {
+    mxc_adc_regs_t *adc;
+    mxc_adccfg_regs_t *adccfg;
+    mxc_adc_fifo_regs_t * adc_fifo;
+    PinName adc_pin;
+};
+
+struct dac_s {
+    int index;
+    uint16_t out;
+    mxc_dac_regs_t *dac;
+    mxc_dac_fifo_t * dac_fifo;
+};
+
+typedef struct {
+    volatile uint32_t *reg_req;
+    volatile uint32_t *reg_ack;
+    uint32_t req_val;
+    uint32_t ack_mask;
+} pin_function_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/pinmap.c

@@ -0,0 +1,105 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "objects.h"
+#include "gpio_regs.h"
+#include "ioman_regs.h"
+
+void pin_function(PinName name, int function)
+{
+    MBED_ASSERT(name != (PinName)NC);
+
+    if ((function >= 0) && (function <= 0xF)) {
+        unsigned int port = PINNAME_TO_PORT(name);
+        unsigned int pin = PINNAME_TO_PIN(name);
+        uint32_t temp = MXC_GPIO->func_sel[port] & ~(0xF << (pin*4));
+        MXC_GPIO->func_sel[port] = temp | ((uint32_t)function << (pin*4));
+    } else {
+        /* Assume this is a pointer to a pin function object */
+        pin_function_t *obj = (pin_function_t*)function;
+
+        if ((*obj->reg_ack & obj->ack_mask) != obj->req_val) {
+            /* Request pin mapping */
+            *obj->reg_req |= obj->req_val;
+
+            /* Check for acknowledgment */
+            MBED_ASSERT((*obj->reg_ack & obj->ack_mask) == obj->req_val);
+        }
+    }
+}
+
+void pin_mode(PinName name, PinMode mode)
+{
+    MBED_ASSERT(name != (PinName)NC);
+    unsigned int port = PINNAME_TO_PORT(name);
+    unsigned int pin = PINNAME_TO_PIN(name);
+
+    /* Must set mode while retaining direction */
+
+    /* Get the current direction */
+    uint32_t out_mode = MXC_GPIO->out_mode[port];
+    uint32_t curr_mode = (out_mode >> (pin*4)) & 0xF;
+    PinDirection dir = PIN_OUTPUT;
+    if ((curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP) || (curr_mode == MXC_V_GPIO_OUT_MODE_HIGH_Z)) {
+        dir = PIN_INPUT;
+    }
+
+    /* Set mode based on current direction */
+    uint32_t new_mode;
+    if (dir == PIN_OUTPUT) {
+        // PullUp      = not valid,
+        // OpenDrain   = MXC_V_GPIO_OUT_MODE_OD,
+        // PullNone    = MXC_V_GPIO_OUT_MODE_NORMAL,
+        if (mode == OpenDrain) {
+            new_mode = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN;
+        } else {
+            new_mode = MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE;
+        }
+    } else {
+        // PullUp      = MXC_V_GPIO_OUT_MODE_HIZPU,
+        // OpenDrain   = not valid,
+        // PullNone    = MXC_V_GPIO_OUT_MODE_HIZ,
+        if (mode == PullUp) {
+            new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP;
+        } else {
+            new_mode = MXC_V_GPIO_OUT_MODE_HIGH_Z;
+        }
+    }
+
+    /* Set new mode */
+    out_mode &= ~(0xF << (pin*4));
+    out_mode |= (new_mode << (pin*4));
+    MXC_GPIO->out_mode[port] = out_mode;
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/port_api.c

@@ -0,0 +1,97 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "gpio_regs.h"
+#include "clkman_regs.h"
+
+PinName port_pin(PortName port, int pin_n)
+{
+    return (PinName)((port << PORT_SHIFT) | pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+    obj->port = port;
+    obj->mask = mask;
+    obj->reg_out = &MXC_GPIO->out_val[port];
+    obj->reg_in  = &MXC_GPIO->in_val[port];
+
+    /* Ensure that the GPIO clock is enabled */
+    if (MXC_CLKMAN->clk_ctrl_1_gpio == MXC_E_CLKMAN_CLK_SCALE_DISABLED) {
+        MXC_CLKMAN->clk_ctrl_1_gpio = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
+    }
+
+    uint32_t i;
+    // The function is set per pin: reuse gpio logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            gpio_set(port_pin(obj->port, i));
+            pin_dir(port_pin(obj->port, i), dir);
+        }
+    }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+    uint32_t i;
+    // The mode is set per pin: reuse gpio logic
+    for (i=0; i<32; i++) {
+        if (obj->mask & (1<<i)) {
+            pin_dir(port_pin(obj->port, i), dir);
+        }
+    }
+}
+
+void port_write(port_t *obj, int value)
+{
+    *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj)
+{
+    return (*obj->reg_in & obj->mask);
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/pwmout_api.c

@@ -0,0 +1,234 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "pwmout_api.h"
+#include "pinmap.h"
+#include "ioman_regs.h"
+#include "clkman_regs.h"
+#include "PeripheralPins.h"
+
+//******************************************************************************
+void pwmout_init(pwmout_t* obj, PinName pin)
+{
+    // Make sure the pin is free for GPIO use
+    unsigned int port = (unsigned int)pin >> PORT_SHIFT;
+    unsigned int port_pin = (unsigned int)pin & ~(0xFFFFFFFF << PORT_SHIFT);
+    MBED_ASSERT(MXC_GPIO->free[port] & (0x1 << port_pin));
+
+    int i = 0;
+    PinMap pwm = PinMap_PWM[0];
+
+    // Check if there is a pulse train already active on this port
+    int pin_func = (MXC_GPIO->func_sel[port] & (0xF << (port_pin*4))) >> (port_pin*4);
+    if((pin_func > 0) && (pin_func < 4)) {
+        // Search through PinMap_PWM to find the active PT
+        while(pwm.pin != (PinName)NC) {
+            if((pwm.pin == pin) && (pwm.function == pin_func)) {
+                break;
+            }
+            pwm = PinMap_PWM[++i];
+        }
+
+    } else {
+       // Search through PinMap_PWM to find an available PT
+        int i = 0;
+        while(pwm.pin != (PinName)NC && (i > -1)) {
+            pwm = PinMap_PWM[i++];
+            if(pwm.pin == pin) {
+                // Check each instance of PT
+                while(1) {
+                    // Check to see if this PT instance is already in use
+                    if((((mxc_pt_regs_t*)pwm.peripheral)->rate_length & 
+                        MXC_F_PT_RATE_LENGTH_MODE)) {
+                        i = -1;
+                        break;
+                    } 
+
+                    // If all instances are in use, overwrite the last 
+                    pwm = PinMap_PWM[++i];
+                    if(pwm.pin != pin) {
+                        pwm = PinMap_PWM[--i];
+                        i = -1; 
+                        break;
+                    }
+
+                }
+            }
+        } 
+    }
+
+    // Make sure we found an available PWM generator
+    MBED_ASSERT(pwm.pin != (PinName)NC);
+
+    // Disable all pwm output
+    MXC_PTG->ctrl = 0;
+
+    // Enable the clock
+    MXC_CLKMAN->clk_ctrl_2_pt = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
+
+    // Set the drive mode to normal
+    MXC_SET_FIELD(&MXC_GPIO->out_mode[port], (0x7 << (port_pin*4)), (MXC_V_GPIO_OUT_MODE_NORMAL_DRIVE << (port_pin*4)));
+
+    // Set the obj pointer to the propper PWM instance
+    obj->pwm = (mxc_pt_regs_t*)pwm.peripheral;
+
+    // Initialize object period and pulse width
+    obj->period = -1; 
+    obj->pulse_width = -1;
+
+    // Disable the output
+    obj->pwm->train = 0x0;
+    obj->pwm->rate_length = 0x0;
+
+    // Configure the pin
+    pin_mode(pin, (PinMode)PullNone);
+    pin_function(pin, pwm.function);
+
+    // default to 20ms: standard for servos, and fine for e.g. brightness control
+    pwmout_period_us(obj, 20000);
+    pwmout_write    (obj, 0);
+
+    // Enable the global pwm
+    MXC_PTG->ctrl = MXC_F_PT_CTRL_ENABLE_ALL;
+}
+
+//******************************************************************************
+void pwmout_free(pwmout_t* obj)
+{
+    // Set the registers to the reset value
+    obj->pwm->train = 0;
+    obj->pwm->rate_length = 0x08000000;
+}
+
+//******************************************************************************
+static void pwmout_update(pwmout_t* obj)
+{
+    // Calculate and set the divider ratio
+    int div = (obj->period * (SystemCoreClock/1000000))/32;
+    if (div < 2){
+        div = 2;
+    }
+    MXC_SET_FIELD(&obj->pwm->rate_length, MXC_F_PT_RATE_LENGTH_RATE_CONTROL, div);
+
+    // Change the duty cycle to adjust the pulse width
+    obj->pwm->train = (0xFFFFFFFF << (32-((32*obj->pulse_width)/obj->period)));
+}
+
+
+//******************************************************************************
+void pwmout_write(pwmout_t* obj, float percent)
+{
+    // Saturate percent if outside of range
+    if(percent < 0.0) {
+        percent = 0.0;
+    } else if(percent > 1.0) {
+        percent = 1.0;
+    }
+
+    // Resize the pulse width to set the duty cycle
+    pwmout_pulsewidth_us(obj, (int)(percent*obj->period));
+}
+
+//******************************************************************************
+float pwmout_read(pwmout_t* obj)
+{
+    // Check for when pulsewidth or period equals 0
+    if((obj->pulse_width == 0) || (obj->period == 0)){
+        return 0;
+    }
+
+    // Return the duty cycle
+    return ((float)obj->pulse_width / (float)obj->period);
+}
+
+//******************************************************************************
+void pwmout_period(pwmout_t* obj, float seconds)
+{
+    pwmout_period_us(obj, (int)(seconds * 1000000.0));
+}
+
+//******************************************************************************
+void pwmout_period_ms(pwmout_t* obj, int ms)
+{
+    pwmout_period_us(obj, ms*1000);
+}
+
+//******************************************************************************
+void pwmout_period_us(pwmout_t* obj, int us)
+{
+    // Check the range of the period
+    MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock/32)));
+
+    // Set pulse width to half the period if uninitialized
+    if(obj->pulse_width == -1){
+        obj->pulse_width = us/2;
+    }
+
+    // Save the period
+    obj->period = us;
+
+    // Update the registers
+    pwmout_update(obj);
+}
+
+//******************************************************************************
+void pwmout_pulsewidth(pwmout_t* obj, float seconds)
+{
+    pwmout_pulsewidth_us(obj, (int)(seconds * 1000000.0));
+}
+
+//******************************************************************************
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
+{
+    pwmout_pulsewidth_us(obj, ms*1000);
+}
+
+//******************************************************************************
+void pwmout_pulsewidth_us(pwmout_t* obj, int us)
+{
+    // Check the range of the pulsewidth
+    MBED_ASSERT((us >= 0) && (us <= (int)(SystemCoreClock/32)));
+
+    // Initialize period to double the pulsewidth if uninitialized
+    if(obj->period == -1){
+        obj->period = 2*us;
+    }
+
+    // Save the pulsewidth
+    obj->pulse_width = us;
+
+    // Update the register
+    pwmout_update(obj);
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/rtc_api.c

@@ -0,0 +1,190 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include "rtc_api.h"
+#include "cmsis.h"
+#include "rtc_regs.h"
+#include "pwrseq_regs.h"
+#include "clkman_regs.h"
+
+static int rtc_inited = 0;
+static volatile uint32_t overflow_cnt = 0;
+static uint32_t overflow_alarm = 0;
+
+//******************************************************************************
+static void overflow_handler(void)
+{
+    MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
+    overflow_cnt++;
+
+    if (overflow_cnt == overflow_alarm) {
+        // Enable the comparator interrupt for the alarm
+        MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0;
+    }
+}
+
+//******************************************************************************
+static void alarm_handler(void)
+{
+    MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
+    MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
+}
+
+//******************************************************************************
+void rtc_init(void)
+{
+    if(rtc_inited) {
+        return;
+    }
+    rtc_inited = 1;
+
+    // Enable the clock to the synchronizer
+    MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
+
+    // Enable the clock to the RTC
+    MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
+
+    // Set the divider from the 4kHz clock
+    MXC_RTCTMR->prescale = MXC_E_RTC_PRESCALE_DIV_2_0;
+
+    // Enable the overflow interrupt
+    MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW;
+
+    // Prepare interrupt handlers
+    NVIC_SetVector(RTC0_IRQn, (uint32_t)alarm_handler);
+    NVIC_EnableIRQ(RTC0_IRQn);
+    NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
+    NVIC_EnableIRQ(RTC3_IRQn);
+
+    // Enable the RTC
+    MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
+}
+
+//******************************************************************************
+void rtc_free(void)
+{
+    if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) {
+        // Clear and disable RTC
+        MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
+        MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE;
+
+        // Wait for pending transactions
+        while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+    }
+
+    // Disable the clock to the RTC
+    MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
+
+    // Disable the clock to the synchronizer
+    MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_DISABLED;
+}
+
+//******************************************************************************
+int rtc_isenabled(void)
+{
+    return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
+}
+
+//******************************************************************************
+time_t rtc_read(void)
+{
+    unsigned int shift_amt;
+    uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
+
+    // Account for a change in the default prescaler
+    shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale;
+
+    // Ensure coherency between overflow_cnt and timer
+    do {
+        ovf_cnt_1 = overflow_cnt;
+        timer_cnt = MXC_RTCTMR->timer;
+        ovf_cnt_2 = overflow_cnt;
+    } while (ovf_cnt_1 != ovf_cnt_2);
+
+    return (timer_cnt >> shift_amt) + (ovf_cnt_1 << (32 - shift_amt));
+}
+
+//******************************************************************************
+uint64_t rtc_read_us(void)
+{
+    unsigned int shift_amt;
+    uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
+    uint64_t currentUs;
+
+    // Account for a change in the default prescaler
+    shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale;
+
+    // Ensure coherency between overflow_cnt and timer
+    do {
+        ovf_cnt_1 = overflow_cnt;
+        timer_cnt = MXC_RTCTMR->timer;
+        ovf_cnt_2 = overflow_cnt;
+    } while (ovf_cnt_1 != ovf_cnt_2);
+
+    currentUs = (((uint64_t)timer_cnt * 1000000) >> shift_amt) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - shift_amt));
+
+    return currentUs;
+}
+
+//******************************************************************************
+void rtc_write(time_t t)
+{
+    // Account for a change in the default prescaler
+    unsigned int shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale;
+
+    MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating
+    MXC_RTCTMR->timer = t << shift_amt;
+    overflow_cnt = t >> (32 - shift_amt);
+    MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;  // enable the timer while updating
+}
+
+//******************************************************************************
+void rtc_set_wakeup(uint64_t wakeupUs)
+{
+    // Account for a change in the default prescaler
+    unsigned int shift_amt = MXC_E_RTC_PRESCALE_DIV_2_12 - MXC_RTCTMR->prescale;
+
+    // Disable the alarm while it is prepared
+    MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
+    MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_COMP0;      // clear interrupt
+
+    overflow_alarm = (wakeupUs >> (32 - shift_amt)) / 1000000;
+
+    if (overflow_alarm == overflow_cnt) {
+        MXC_RTCTMR->comp[0] = (wakeupUs << shift_amt) / 1000000;
+        MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0;
+    }
+
+    // Enable wakeup from RTC
+    MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER | MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0);
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/serial_api.c

@@ -0,0 +1,355 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include <string.h>
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "serial_api.h"
+#include "uart_regs.h"
+#include "PeripheralPins.h"
+
+#define UART_NUM 2
+#define DEFAULT_BAUD 9600
+#define DEFAULT_STOP 1
+#define DEFAULT_PARITY ParityNone
+
+#define UART_ERRORS (MXC_F_UART_INTFL_RX_FRAME_ERROR | \
+                     MXC_F_UART_INTFL_RX_PARITY_ERROR | \
+                     MXC_F_UART_INTFL_RX_OVERRUN)
+
+// Variables for managing the stdio UART
+int stdio_uart_inited;
+serial_t stdio_uart;
+
+// Variables for interrupt driven
+static uart_irq_handler irq_handler;
+static uint32_t serial_irq_ids[UART_NUM];
+
+//******************************************************************************
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    // Determine which uart is associated with each pin
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+
+    // Make sure that both pins are pointing to the same uart
+    MBED_ASSERT(uart != (UARTName)NC);
+
+    // Set the obj pointer to the proper uart
+    obj->uart = (mxc_uart_regs_t*)uart;
+
+    // Set the uart index
+    obj->index = MXC_UART_BASE_TO_INSTANCE(obj->uart);
+
+    // Configure the pins
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+
+    // Flush the RX and TX FIFOs, clear the settings
+    obj->uart->ctrl = ( MXC_F_UART_CTRL_TX_FIFO_FLUSH |  MXC_F_UART_CTRL_RX_FIFO_FLUSH);
+
+    // Disable interrupts
+    obj->uart->inten = 0;
+    obj->uart->intfl = 0;
+
+    // Configure to default settings
+    serial_baud(obj, DEFAULT_BAUD);
+    serial_format(obj, 8, ParityNone, 1);
+
+    // Manage stdio UART
+    if(uart == STDIO_UART) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+//******************************************************************************
+void serial_baud(serial_t *obj, int baudrate)
+{
+    uint32_t idiv = 0, ddiv = 0, div = 0;
+
+    // Calculate the integer and decimal portions
+    div = SystemCoreClock / ((baudrate / 100) * 128);
+    idiv = (div / 100);
+    ddiv = (div - idiv * 100) * 128 / 100;
+
+    obj->uart->baud_int = idiv;
+    obj->uart->baud_div_128 = ddiv;
+
+    // Enable the baud clock
+    obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN;
+}
+
+//******************************************************************************
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+
+    // Check the validity of the inputs
+    MBED_ASSERT((data_bits > 4) && (data_bits < 9));
+    MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) ||
+                (parity == ParityEven) || (parity == ParityForced1) ||
+                (parity == ParityForced0));
+    MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
+
+    // Adjust the stop and data bits
+    stop_bits -= 1;
+    data_bits -= 5;
+
+    // Adjust the parity setting
+    int paren = 0, mode = 0;
+    switch (parity) {
+        case ParityNone:
+            paren = 0;
+            mode = 0;
+            break;
+        case ParityOdd :
+            paren = 1;
+            mode = 0;
+            break;
+        case ParityEven:
+            paren = 1;
+            mode = 1;
+            break;
+        case ParityForced1:
+            // Hardware does not support forced parity
+            MBED_ASSERT(0);
+            break;
+        case ParityForced0:
+            // Hardware does not support forced parity
+            MBED_ASSERT(0);
+            break;
+        default:
+            paren = 1;
+            mode = 0;
+            break;
+    }
+
+    obj->uart->ctrl |= ((data_bits << MXC_F_UART_CTRL_CHAR_LENGTH_POS) |
+                        (stop_bits << MXC_F_UART_CTRL_STOP_BIT_MODE_POS) |
+                        (paren << MXC_F_UART_CTRL_PARITY_ENABLE_POS) |
+                        (mode << MXC_F_UART_CTRL_PARITY_MODE_POS));
+}
+
+//******************************************************************************
+void uart_handler(mxc_uart_regs_t* uart, int id)
+{
+    // Check for errors or RX Threshold
+    if(uart->intfl & (MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS)) {
+        irq_handler(serial_irq_ids[id], RxIrq);
+        uart->intfl &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD | UART_ERRORS);
+    }
+
+    // Check for TX Threshold
+    if(uart->intfl & MXC_F_UART_INTFL_TX_ALMOST_EMPTY) {
+        irq_handler(serial_irq_ids[id], TxIrq);
+        uart->intfl &= ~(MXC_F_UART_INTFL_TX_ALMOST_EMPTY);
+    }
+}
+
+void uart0_handler(void)
+{
+    uart_handler(MXC_UART0, 0);
+}
+void uart1_handler(void)
+{
+    uart_handler(MXC_UART1, 1);
+}
+
+//******************************************************************************
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+//******************************************************************************
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    if(obj->index == 0) {
+        NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);
+        NVIC_EnableIRQ(UART0_IRQn);
+    } else {
+        NVIC_SetVector(UART1_IRQn, (uint32_t)uart1_handler);
+        NVIC_EnableIRQ(UART1_IRQn);
+    }
+
+    if(irq == RxIrq) {
+        // Set the RX FIFO Threshold to 1
+        obj->uart->ctrl &= ~MXC_F_UART_CTRL_RX_THRESHOLD;
+        obj->uart->ctrl |= 0x1;
+        // Enable RX FIFO Threshold Interrupt
+        if(enable) {
+            // Clear pending interrupts
+            obj->uart->intfl = 0;
+            obj->uart->inten |= (MXC_F_UART_INTFL_RX_OVER_THRESHOLD |
+                                 UART_ERRORS);
+        } else {
+            // Clear pending interrupts
+            obj->uart->intfl = 0;
+            obj->uart->inten &= ~(MXC_F_UART_INTFL_RX_OVER_THRESHOLD |
+                                  UART_ERRORS);
+        }
+
+    } else if (irq == TxIrq) {
+        // Enable TX Almost empty Interrupt
+        if(enable) {
+            // Clear pending interrupts
+            obj->uart->intfl = 0;
+            obj->uart->inten |= MXC_F_UART_INTFL_TX_ALMOST_EMPTY;
+        } else {
+            // Clear pending interrupts
+            obj->uart->intfl = 0;
+            obj->uart->inten &= ~MXC_F_UART_INTFL_TX_ALMOST_EMPTY;
+        }
+
+    } else {
+        MBED_ASSERT(0);
+    }
+}
+
+
+//******************************************************************************
+int serial_getc(serial_t *obj)
+{
+    int c;
+
+    // Wait for data to be available
+    while(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY) {}
+    c = obj->uart->tx_rx_fifo & 0xFF;
+
+    // Echo characters for stdio
+    if (obj->uart == (mxc_uart_regs_t*)STDIO_UART) {
+        obj->uart->tx_rx_fifo = c;
+    }
+    
+    return c;
+}
+
+//******************************************************************************
+void serial_putc(serial_t *obj, int c)
+{
+    // Append a carriage return for stdio
+    if ((c == (int)'\n') && (obj->uart == (mxc_uart_regs_t*)STDIO_UART)) {
+        while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
+        obj->uart->tx_rx_fifo = '\r';
+    }
+
+    // Wait for TXFIFO to not be full
+    while(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL) {}
+    obj->uart->tx_rx_fifo = c;
+
+}
+
+//******************************************************************************
+int serial_readable(serial_t *obj)
+{
+    return (!(obj->uart->status & MXC_F_UART_STATUS_RX_FIFO_EMPTY));
+}
+
+//******************************************************************************
+int serial_writable(serial_t *obj)
+{
+    return (!(obj->uart->status & MXC_F_UART_STATUS_TX_FIFO_FULL));
+}
+
+//******************************************************************************
+void serial_clear(serial_t *obj)
+{
+    // Clear the rx and tx fifos
+    obj->uart->ctrl |= (MXC_F_UART_CTRL_TX_FIFO_FLUSH  | MXC_F_UART_CTRL_RX_FIFO_FLUSH );
+}
+
+
+//******************************************************************************
+void serial_break_set(serial_t *obj)
+{
+    // Make sure that nothing is being sent
+    while(obj->uart->status & MXC_F_UART_STATUS_RX_BUSY) {}
+
+    // Disable the clock to pause any transmission
+    obj->uart->ctrl &= ~MXC_F_UART_CTRL_BAUD_CLK_EN ;
+}
+
+//******************************************************************************
+void serial_break_clear(serial_t *obj)
+{
+    obj->uart->ctrl |= MXC_F_UART_CTRL_BAUD_CLK_EN;
+}
+
+
+//******************************************************************************
+void serial_pinout_tx(PinName tx)
+{
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+
+//******************************************************************************
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+    if(FlowControlNone == type) {
+        // Disable hardware flow control
+        obj->uart->ctrl &= ~(MXC_F_UART_CTRL_HW_FLOW_CTRL_EN);
+        return;
+    }
+
+    // Check to see if we can use HW flow control
+    UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
+    UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
+    UARTName uart = (UARTName)pinmap_merge(uart_cts, uart_rts);
+
+    if((FlowControlCTS == type) || (FlowControlRTSCTS== type)) {
+        // Make sure pin is in the PinMap
+        MBED_ASSERT(uart_cts != (UARTName)NC);
+
+        // Enable the pin for CTS function
+        pinmap_pinout(txflow, PinMap_UART_CTS);
+    }
+
+    if((FlowControlRTS == type) || (FlowControlRTSCTS== type))  {
+        // Make sure pin is in the PinMap
+        MBED_ASSERT(uart_rts != (UARTName)NC);
+
+        // Enable the pin for RTS function
+        pinmap_pinout(rxflow, PinMap_UART_RTS);
+    }
+
+    if(FlowControlRTSCTS == type){ 
+        // Make sure that the pins are pointing to the same UART
+        MBED_ASSERT(uart != (UARTName)NC);
+    }
+
+    // Enable hardware flow control
+    obj->uart->ctrl |= MXC_F_UART_CTRL_HW_FLOW_CTRL_EN;
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/sleep.c

@@ -0,0 +1,169 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#include "sleep_api.h"
+#include "us_ticker_api.h"
+#include "cmsis.h"
+#include "pwrman_regs.h"
+#include "pwrseq_regs.h"
+#include "ioman_regs.h"
+#include "rtc_regs.h"
+
+#define MIN_DEEP_SLEEP_US       500
+
+uint64_t rtc_read_us(void);
+void rtc_set_wakeup(uint64_t wakeupUs);
+void us_ticker_deinit(void);
+void us_ticker_set(timestamp_t timestamp);
+
+static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
+
+// Normal wait mode
+void sleep(void)
+{
+    // Normal sleep mode for ARM core
+    SCB->SCR = 0;
+
+    __DSB();
+    __WFI();
+}
+
+// Work-around for issue of clearing power sequencer I/O flag
+static void clearAllGPIOWUD(void)
+{
+    uint32_t wud_req0 = MXC_IOMAN->wud_req0;
+    uint32_t wud_req1 = MXC_IOMAN->wud_req1;
+
+    // I/O must be a wakeup detect to clear
+    MXC_IOMAN->wud_req0 = 0xffffffff;
+    MXC_IOMAN->wud_req1 = 0xffffffff;
+
+    // Clear all WUDs
+    MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL;
+    MXC_PWRMAN->wud_pulse0 = 1;
+
+    // Restore WUD requests
+    MXC_IOMAN->wud_req0 = wud_req0;
+    MXC_IOMAN->wud_req1 = wud_req1;
+}
+
+// Low-power stop mode
+void deepsleep(void)
+{
+    uint64_t sleepStartRtcUs;
+    uint32_t sleepStartTickerUs;
+    int32_t sleepDurationUs;
+    uint64_t sleepEndRtcUs;
+    uint64_t elapsedUs;
+
+    __disable_irq();
+
+    // Wait for all STDIO characters to be sent. The UART clock will stop.
+    while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY);
+
+    // Record the current times
+    sleepStartRtcUs = rtc_read_us();
+    sleepStartTickerUs = us_ticker_read();
+
+    // Get the next mbed timer expiration
+    timestamp_t next_event = 0;
+    us_ticker_get_next_timestamp(&next_event);
+    sleepDurationUs = next_event - sleepStartTickerUs;
+
+    if (sleepDurationUs < MIN_DEEP_SLEEP_US) {
+        /* The next wakeup is too soon. */
+        __enable_irq();
+        return;
+    }
+
+    // Disable the us_ticker. It won't be clocked in DeepSleep
+    us_ticker_deinit();
+
+    // Prepare to wakeup from the RTC
+    rtc_set_wakeup(sleepStartRtcUs + sleepDurationUs);
+
+    // Prepare for LP1
+    uint32_t reg0 = MXC_PWRSEQ->reg0;
+    reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP;  // disable VDD3 SVM during sleep mode
+    reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP;  // disable VREG18 SVM during sleep mode
+    if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) {   // if real-time clock enabled during run
+        reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP;    // enable real-time clock during sleep mode
+    } else {
+        reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP;   // disable real-time clock during sleep mode
+    }
+    reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP;   // enable CHZY regulator during sleep mode
+    reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1;          // go into LP1
+    reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT;  // clear first boot flag
+    MXC_PWRSEQ->reg0 = reg0;
+
+    MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS);
+
+    // Deep sleep for ARM core
+    SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
+
+    // clear latches for wakeup detect
+    MXC_PWRSEQ->flags = MXC_PWRSEQ->flags;
+    if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) {
+        // attempt work-around for I/O flag clearing issue
+        clearAllGPIOWUD();
+        MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP;
+    }
+
+    // Wait for pending RTC transaction
+    while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
+
+    // Ensure that the event register is clear
+    __SEV();    // set event
+    __WFE();    // clear event
+
+    // Enter LP1
+    __WFE();
+    // Woke up from LP1
+
+    // The RTC timer does not update until the next tick
+    uint64_t tempUs = rtc_read_us();
+    do {
+        sleepEndRtcUs = rtc_read_us();
+    } while(sleepEndRtcUs == tempUs);
+
+    // Get the elapsed time from the RTC. Wakeup could have been from some other event.
+    elapsedUs = sleepEndRtcUs - sleepStartRtcUs;
+
+    // Update the us_ticker. It was not clocked during DeepSleep
+    us_ticker_init();
+    us_ticker_set(sleepStartTickerUs + elapsedUs);
+    us_ticker_get_next_timestamp(&next_event);
+    us_ticker_set_interrupt(next_event);
+
+    __enable_irq();
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/spi_api.c

@@ -0,0 +1,190 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#include <string.h>
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "spi_api.h"
+#include "pinmap.h"
+#include "ioman_regs.h"
+#include "clkman_regs.h"
+#include "PeripheralPins.h"
+
+#define DEFAULT_CHAR	8
+#define DEFAULT_MODE	0
+#define DEFAULT_FREQ 	1000000
+
+// Formatting settings
+static int spi_bits;
+
+//******************************************************************************
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    // Make sure pins are pointing to the same SPI instance
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl;
+
+    // Give the application the option to manually control Slave Select
+    if((SPIName)spi_ssel != (SPIName)NC) {
+        spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+    } else {
+        spi_cntl = spi_sclk;
+    }
+
+    SPIName spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
+
+    MBED_ASSERT((SPIName)spi != (SPIName)NC);
+
+    // Set the obj pointer to the proper SPI Instance
+    obj->spi = (mxc_spi_regs_t*)spi;
+
+    // Set the SPI index and FIFOs
+    obj->index = MXC_SPI_BASE_TO_INSTANCE(obj->spi);
+    obj->rxfifo = MXC_SPI_GET_RXFIFO(obj->index);
+    obj->txfifo = MXC_SPI_GET_TXFIFO(obj->index);
+
+    // Configure the pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    pinmap_pinout(ssel, PinMap_SPI_SSEL);
+
+    // Enable SPI and FIFOs
+    obj->spi->gen_ctrl = (MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN |
+                          MXC_F_SPI_GEN_CTRL_TX_FIFO_EN |
+                          MXC_F_SPI_GEN_CTRL_RX_FIFO_EN );
+
+    // Give instance the default settings
+    spi_format(obj, DEFAULT_CHAR, DEFAULT_MODE, 0);
+    spi_frequency(obj, DEFAULT_FREQ);
+}
+
+//******************************************************************************
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    // Check the validity of the inputs
+    MBED_ASSERT(((bits >= 1) && (bits <= 32)) && ((mode >= 0) && (mode <= 3)));
+
+    // Only supports master mode
+    MBED_ASSERT(!slave);
+
+    // Save formatting data
+    spi_bits = bits;
+
+    // Set the mode
+    obj->spi->mstr_cfg &= ~(MXC_F_SPI_MSTR_CFG_SPI_MODE);
+    obj->spi->mstr_cfg |= (mode << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS);
+}
+
+//******************************************************************************
+void spi_frequency(spi_t *obj, int hz)
+{
+    // Maximum frequency is half the system frequency
+    MBED_ASSERT((unsigned int)hz < (SystemCoreClock / 2));
+    unsigned clocks = ((SystemCoreClock/2)/(hz));
+
+    // Figure out the divider ratio
+    int clk_div = 1;
+    while(clk_div < 10) {
+        if(clocks < 0x10) {
+            break;
+        }
+        clk_div++;
+        clocks = clocks >> 1;
+    }
+
+    // Turn on the SPI clock
+    if(obj->index == 0) {
+        MXC_CLKMAN->clk_ctrl_3_spi0 = clk_div;
+    } else if(obj->index == 1) {
+        MXC_CLKMAN->clk_ctrl_4_spi1 = clk_div;
+    } else if(obj->index == 2) {
+        MXC_CLKMAN->clk_ctrl_5_spi2 = clk_div;
+    } else {
+        MBED_ASSERT(0);
+    }
+
+    // Set the number of clocks to hold sclk high and low
+    MXC_SET_FIELD(&obj->spi->mstr_cfg, (MXC_F_SPI_MSTR_CFG_SCK_HI_CLK | MXC_F_SPI_MSTR_CFG_SCK_LO_CLK),
+        ((clocks << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS) | (clocks << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS)));
+}
+
+//******************************************************************************
+int spi_master_write(spi_t *obj, int value)
+{
+    int bits = spi_bits;
+    if(spi_bits == 32) {
+        bits = 0;
+    }
+    // Create the header
+    uint16_t header = ((0x3 << MXC_F_SPI_FIFO_DIR_POS ) |  // TX and RX
+                       (0x0 << MXC_F_SPI_FIFO_UNIT_POS) | // Send bits
+                       (bits << MXC_F_SPI_FIFO_SIZE_POS) | // Number of units
+                       (0x1 << MXC_F_SPI_FIFO_DASS_POS));      // Deassert SS
+
+    // Send the message header
+    obj->txfifo->txfifo_16 = header;
+
+    // Send the data
+    if(spi_bits < 17) {
+        obj->txfifo->txfifo_16 = (uint16_t)value;
+    } else {
+        obj->txfifo->txfifo_32 = (uint32_t)value;
+    }
+
+    // Get the data
+    bits = spi_bits;
+    int result = 0;
+    int i = 0;
+    while(bits > 0) {
+        // Wait for data
+        while(((obj->spi->fifo_ctrl & MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED)
+                >> MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS) < 1) {}
+
+        result |= (obj->rxfifo->rxfifo_8 << (i++*8));
+        bits-=8;
+    }
+
+    return result;
+}
+
+//******************************************************************************
+int spi_busy(spi_t *obj)
+{
+    return !(obj->spi->intfl & MXC_F_SPI_INTFL_TX_READY);
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32600/us_ticker.c

@@ -0,0 +1,261 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+ 
+#include "mbed_error.h"
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+#include "tmr_regs.h"
+
+#define US_TIMER        MXC_TMR0
+#define US_TIMER_IRQn   TMR0_IRQn
+
+static int us_ticker_inited = 0;
+static uint32_t ticks_per_us;
+static uint32_t tick_win;
+static volatile uint64_t current_cnt;   // Hold the current ticks
+static volatile uint64_t event_cnt;     // Holds the value of the next event
+
+#define ticks_to_us(ticks)  ((ticks) / ticks_per_us);
+#define MAX_TICK_VAL    ((uint64_t)0xFFFFFFFF * ticks_per_us)
+
+//******************************************************************************
+static inline void inc_current_cnt(uint32_t inc) {
+
+    // Overflow the ticker when the us ticker overflows
+    current_cnt += inc;
+    if(current_cnt > MAX_TICK_VAL) {
+        current_cnt -= (MAX_TICK_VAL + 1);
+    }
+}
+
+//******************************************************************************
+static inline int event_passed(uint64_t current, uint64_t event) {
+
+    // Determine if the event has already happened.
+    // If the event is behind the current ticker, within a window,
+    // then the event has already happened.
+    if(((current < tick_win) && ((event < current) || 
+        (event > (MAX_TICK_VAL - (tick_win - current))))) || 
+        ((event < current) && (event > (current - tick_win)))) {
+        return 1;
+    }
+
+    return 0;
+}
+
+//******************************************************************************
+static inline uint64_t event_diff(uint64_t current, uint64_t event) {
+
+    // Check to see if the ticker will overflow before the event
+    if(current <= event) {
+        return (event - current);
+    }
+
+    return ((MAX_TICK_VAL - current) + event);
+}
+
+//******************************************************************************
+static void tmr_handler(void)
+{
+    uint32_t term_cnt32 = US_TIMER->term_cnt32;
+    US_TIMER->term_cnt32 = 0xFFFFFFFF;  // reset to max value to prevent further interrupts
+    US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1);    // clear interrupt
+    NVIC_ClearPendingIRQ(US_TIMER_IRQn);
+
+    inc_current_cnt(term_cnt32);
+
+    if (event_passed(current_cnt + US_TIMER->count32, event_cnt )) {
+        // the timestamp has expired
+        event_cnt = 0xFFFFFFFFFFFFFFFFULL;  // reset to max value
+        us_ticker_irq_handler();
+    } else {
+
+        uint64_t diff = event_diff(current_cnt, event_cnt);
+        if (diff < (uint64_t)0xFFFFFFFF) {
+            // the event occurs before the next overflow
+            US_TIMER->term_cnt32 = diff;
+
+            // Since the timer keeps counting after the terminal value is reached, it is possible that the new
+            // terminal value is in the past.    
+            if (US_TIMER->term_cnt32 < US_TIMER->count32) {
+                // the timestamp has expired
+                US_TIMER->term_cnt32 = 0xFFFFFFFF;  // reset to max value to prevent further interrupts
+                US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1);    // clear interrupt
+                NVIC_ClearPendingIRQ(US_TIMER_IRQn);
+                event_cnt = 0xFFFFFFFFFFFFFFFFULL;  // reset to max value
+                us_ticker_irq_handler();
+            }
+        }
+    }
+}
+
+//******************************************************************************
+void us_ticker_init(void)
+{
+    if (us_ticker_inited)
+        return;
+    us_ticker_inited = 1;
+
+    current_cnt = 0;
+    event_cnt = 0xFFFFFFFFFFFFFFFFULL;  // reset to max value
+
+    if (SystemCoreClock <= 1000000) {
+        error("us_ticker cannot operate at this SystemCoreClock");
+        return;
+    }
+
+    // Configure timer for 32-bit continuous mode with /1 prescaler
+    US_TIMER->ctrl = MXC_E_TMR_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS | (0 << MXC_F_TMR_CTRL_PRESCALE_POS);
+    ticks_per_us = SystemCoreClock / 1000000;
+
+    // Set the tick window to 10ms
+    tick_win = SystemCoreClock/100;
+
+    // Set timer overflow to the max
+    US_TIMER->term_cnt32 = 0xFFFFFFFF;
+    US_TIMER->pwm_cap32 = 0xFFFFFFFF;
+    US_TIMER->count32 = 0;
+
+    US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1);    // clear pending interrupts
+
+    NVIC_SetVector(US_TIMER_IRQn, (uint32_t)tmr_handler);
+    NVIC_EnableIRQ(US_TIMER_IRQn);
+
+    US_TIMER->inten |= MXC_F_TMR_INTEN_TIMER0;  // enable interrupts
+    US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0;   // enable timer
+}
+
+//******************************************************************************
+void us_ticker_deinit(void)
+{
+    US_TIMER->ctrl = 0;     // disable timer
+    US_TIMER->inten = 0;    // disable interrupts
+    US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1);    // clear interrupts
+    us_ticker_inited = 0;
+}
+
+//******************************************************************************
+uint32_t us_ticker_read(void)
+{
+    uint64_t current_cnt1, current_cnt2;
+    uint32_t term_cnt, tmr_cnt;
+    int intfl1, intfl2;
+
+    if (!us_ticker_inited)
+        us_ticker_init();
+
+    // Ensure coherency between current_cnt and US_TIMER->count32
+    do {
+        current_cnt1 = current_cnt;
+        intfl1 = US_TIMER->intfl;
+        term_cnt = US_TIMER->term_cnt32;
+        tmr_cnt = US_TIMER->count32;
+        intfl2 = US_TIMER->intfl;
+        current_cnt2 = current_cnt;
+    } while ((current_cnt1 != current_cnt2) || (intfl1 != intfl2));
+
+    if (intfl1) {
+        current_cnt1 += term_cnt;
+    }
+
+    current_cnt1 += tmr_cnt;
+
+    return (current_cnt1 / ticks_per_us);
+}
+
+//******************************************************************************
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    // Note: interrupts are disabled before this function is called.
+    US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0;  // disable timer
+
+    if (US_TIMER->intfl) {
+        US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1);    // clear interrupt
+        NVIC_ClearPendingIRQ(US_TIMER_IRQn);
+        inc_current_cnt(US_TIMER->term_cnt32);
+    }
+
+    // add and reset the current count value
+    inc_current_cnt(US_TIMER->count32);
+    US_TIMER->count32 = 0;
+
+    // add the number of cycles that the timer is disabled here for 
+    inc_current_cnt(200);
+
+    event_cnt = (uint64_t)timestamp * ticks_per_us;
+
+    // Check to see if the event has already passed
+    if (!event_passed(current_cnt, event_cnt)) {
+        uint64_t diff = event_diff(current_cnt, event_cnt);
+        if (diff < (uint64_t)0xFFFFFFFF) {
+            // the event occurs before the next overflow
+            US_TIMER->term_cnt32 = diff;
+        } else {
+            // the event occurs after the next overflow 
+            US_TIMER->term_cnt32 = 0xFFFFFFFF;  // set to max
+        }
+    } else {
+        // the requested timestamp occurs in the past
+        // set the timer up to immediately expire
+        US_TIMER->term_cnt32 = 1;
+    }
+    US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0;   // enable timer
+}
+
+//******************************************************************************
+void us_ticker_disable_interrupt(void)
+{
+    // There are no more events, set timer overflow to the max
+    US_TIMER->term_cnt32 = 0xFFFFFFFF;
+}
+
+//******************************************************************************
+void us_ticker_clear_interrupt(void)
+{
+    // cleared in the local handler
+}
+
+//******************************************************************************
+void us_ticker_set(timestamp_t timestamp)
+{
+    US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0;  // disable timer
+    current_cnt = (uint64_t)timestamp * ticks_per_us;
+    US_TIMER->count32 = 0;
+    US_TIMER->term_cnt32 = 0xFFFFFFFF;
+    US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0;   // enable timer
+
+    if (((uint64_t)timestamp * ticks_per_us) >= event_cnt) {
+        // The next timestamp has elapsed. Trigger the interrupt to handle it.
+        NVIC_SetPendingIRQ(US_TIMER_IRQn);
+    }
+}

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogin_api.c

@@ -38,11 +38,11 @@
 #include "afe_regs.h"
 #include "PeripheralPins.h"
 
-#define PGA_TRK_CNT     0x8
+#define PGA_TRK_CNT     0x1F
 #define ADC_ACT_CNT     0x1
 #define ADC_PGA_CNT     0x1
 #define ADC_ACQ_CNT     0x1
-#define ADC_SLP_CNT     0x0
+#define ADC_SLP_CNT     0x1
  
 //******************************************************************************
 void analogin_init(analogin_t *obj, PinName pin)
@@ -100,6 +100,12 @@ uint16_t analogin_read_u16(analogin_t *obj)
         mux_pos = (obj->adc_pin & 0xF) + 8;
     }
 
+    // Reset the ADC
+    obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_RST;
+
+    // Enable the ADC
+    obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_EN;
+
     // Setup the ADC clock
     MXC_SET_FIELD(&obj->adc->ctrl0, (MXC_F_ADC_CTRL0_ADC_MODE | MXC_F_ADC_CTRL0_AVG_MODE |
         MXC_F_ADC_CTRL0_ADC_CLK_MODE | MXC_F_ADC_CTRL0_ADC_BI_POL),
@@ -119,9 +125,6 @@ uint16_t analogin_read_u16(analogin_t *obj)
         (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP |
         (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS)));
 
-    // Enable the ADC
-    obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_EN;
-
     // Clear the done bit
     obj->adc->intr = MXC_F_ADC_INTR_DONE_IF;
 

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/analogout_api.c

@@ -183,8 +183,7 @@ void analogout_write_u16(dac_t *obj, uint16_t value)
         MXC_F_DAC_CTRL0_CLOCK_GATE_EN | MXC_F_DAC_CTRL0_CPU_START);
 
     if(obj->index < 2) {
-        // Convert 16 bits to 12 bits
+        obj->out = (value);
-        obj->out = (value >> 4);
         obj->dac_fifo->output_16 = (obj->out);
 
     } else {

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/gpio_irq_api.c

@@ -118,7 +118,7 @@ int gpio_irq_init(gpio_irq_t *obj, PinName name, gpio_irq_handler handler, uint3
 
     /* enable the requested interrupt */
     MXC_GPIO->inten[port] |= (1 << pin);
-    NVIC_EnableIRQ(GPIO_P0_IRQn + port);
+    NVIC_EnableIRQ((IRQn_Type)((uint32_t)GPIO_P0_IRQn + port));
 
     return 0;
 }

libraries/mbed/targets/hal/TARGET_Maxim/TARGET_MAX32610/us_ticker.c

@@ -96,7 +96,7 @@ static void tmr_handler(void)
 
     if (event_passed(current_cnt + US_TIMER->count32, event_cnt )) {
         // the timestamp has expired
-        event_cnt = -1;                   // reset to max value
+        event_cnt = 0xFFFFFFFFFFFFFFFFULL;  // reset to max value
         us_ticker_irq_handler();
     } else {
 
@@ -112,7 +112,7 @@ static void tmr_handler(void)
                 US_TIMER->term_cnt32 = 0xFFFFFFFF;  // reset to max value to prevent further interrupts
                 US_TIMER->intfl = (MXC_F_TMR_INTFL_TIMER0 | MXC_F_TMR_INTFL_TIMER1);    // clear interrupt
                 NVIC_ClearPendingIRQ(US_TIMER_IRQn);
-                event_cnt = -1;                   // reset to max value
+                event_cnt = 0xFFFFFFFFFFFFFFFFULL;  // reset to max value
                 us_ticker_irq_handler();
             }
         }
@@ -127,7 +127,7 @@ void us_ticker_init(void)
     us_ticker_inited = 1;
 
     current_cnt = 0;
-    event_cnt = -1;       // initialize to max value
+    event_cnt = 0xFFFFFFFFFFFFFFFFULL;  // reset to max value
 
     if (SystemCoreClock <= 1000000) {
         error("us_ticker cannot operate at this SystemCoreClock");

libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h

@@ -301,7 +301,7 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}
 #elif defined(TARGET_STM32F303RE)
 #define INITIAL_SP            (0x20010000UL)
 
-#elif defined(TARGET_MAX32610)
+#elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600)
 #define INITIAL_SP            (0x20008000UL)
 
 #else

libraries/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c

@@ -51,7 +51,7 @@
 #ifndef OS_TASKCNT
 #  if   defined(TARGET_LPC1768) || defined(TARGET_LPC2368)   || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\
    || defined(TARGET_KL46Z) || defined(TARGET_KL43Z)  || defined(TARGET_STM32F407) || defined(TARGET_F407VG)  || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \
-   || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610)
+   || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600)
 #    define OS_TASKCNT         14
 #  elif defined(TARGET_LPC11U24) || defined(TARGET_STM32F303RE) || defined(TARGET_LPC11U35_401)  || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
    || defined(TARGET_LPC812)   || defined(TARGET_KL25Z)         || defined(TARGET_KL05Z)        || defined(TARGET_STM32F100RB)  || defined(TARGET_STM32F051R8) \
@@ -67,7 +67,7 @@
 #ifndef OS_SCHEDULERSTKSIZE
 #  if   defined(TARGET_LPC1768) || defined(TARGET_LPC2368)   || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM) || defined(TARGET_LPC4330) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347)  || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\
    || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG)  || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) \
-   || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610)
+   || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F405RG) || defined(TARGET_K22F) || defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F401VC) || defined(TARGET_MAX32610) || defined(TARGET_MAX32600)
 #      define OS_SCHEDULERSTKSIZE    256
 #  elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401)  || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO)  || defined(TARGET_LPC1114) \
    || defined(TARGET_LPC812)   || defined(TARGET_KL25Z)         || defined(TARGET_KL05Z)        || defined(TARGET_STM32F100RB)  || defined(TARGET_STM32F051R8) \
@@ -168,7 +168,7 @@
 #elif defined(TARGET_STM32F401VC)
 #    define OS_CLOCK       84000000
 
-#elif defined(TARGET_MAX32610)
+#elif defined(TARGET_MAX32610) || defined(TARGET_MAX32600)
 #    define OS_CLOCK       24000000
 
 #  else

libraries/tests/mbed/analog/main.cpp

@@ -49,6 +49,10 @@ AnalogOut out(PA_4);
 AnalogIn in(PC_3);
 AnalogOut out(PA_5);
 
+#elif defined(TARGET_MAX32600MBED)
+AnalogIn in(AIN_7P);
+AnalogOut out(AOUT_DO);
+
 #else
 AnalogIn in(p17);
 AnalogOut out(p18);

libraries/tests/mbed/digitalin_digitalout/main.cpp

@@ -41,6 +41,10 @@ DigitalIn in(D0);
 DigitalOut out(TP3);
 DigitalIn in(TP4);
 
+#elif defined(TARGET_MAX32600MBED)
+DigitalOut out(P1_0);
+DigitalIn in(P4_7);
+
 #else
 DigitalOut out(p5);
 DigitalIn in(p25);

libraries/tests/mbed/digitalinout/main.cpp

@@ -41,6 +41,10 @@ DigitalInOut d2(D7);
 DigitalInOut d1(TP3);
 DigitalInOut d2(TP4);
 
+#elif defined(TARGET_MAX32600MBED)
+DigitalInOut d1(P1_0);
+DigitalInOut d2(P4_7);
+
 #else
 DigitalInOut d1(p5);
 DigitalInOut d2(p25);

libraries/tests/mbed/interruptin/main.cpp

@@ -62,7 +62,6 @@ void in_handler() {
 #define PIN_OUT    D1
 #define PIN_IN     D5
 
-
 #elif defined(TARGET_FF_ARDUINO)
 #define PIN_OUT    D0
 #define PIN_IN     D7
@@ -71,6 +70,10 @@ void in_handler() {
 #define PIN_OUT    P0_0
 #define PIN_IN     P0_1
 
+#elif defined(TARGET_MAX32600MBED)
+#define PIN_OUT    P1_0
+#define PIN_IN     P4_7
+
 #else
 #define PIN_IN      (p5)
 #define PIN_OUT     (p25)

libraries/tests/mbed/portinout/main.cpp

@@ -72,6 +72,15 @@
 #define P2_2    (1 << 1)
 #define PORT_2  Port1
 
+#elif defined(TARGET_MAX32600MBED)
+#define P1_1    (1 << 0)  // P1_0
+#define P1_2    (1 << 1)  // P1_1
+#define PORT_1  Port1
+
+#define P2_1    (1 << 7)  // P4_7
+#define P2_2    (1 << 6)  // P4_6
+#define PORT_2  Port4
+
 #elif defined(TARGET_NUCLEO_F030R8) || \
       defined(TARGET_NUCLEO_F070RB) || \
       defined(TARGET_NUCLEO_F072RB) || \

libraries/tests/mbed/portout/main.cpp

@@ -1,20 +1,29 @@
 #include "mbed.h"
 
 # if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088)
+#     define LED_PORT   Port1
 #     define LED1       (1 << 18) // P1.18
 #     define LED2       (1 << 20) // P1.20
 #     define LED3       (1 << 21) // P1.21
 #     define LED4       (1 << 23) // P1.23
 # elif defined(TARGET_LPC11U24) || defined(TARGET_LPC1114)
+#     define LED_PORT   Port1
 #     define LED1       (1 <<  8) // P1.8
 #     define LED2       (1 <<  9) // P1.9
 #     define LED3       (1 << 10) // P1.10
 #     define LED4       (1 << 11) // P1.11
 # elif defined(TARGET_MAXWSNENV)
+#     define LED_PORT   Port1
 #     define LED1   (1 <<  4) // P1.4
 #     define LED2   (1 <<  6) // P1.6
 #     define LED3   (1 <<  7) // P1.7
 #     define LED4   0
+# elif defined(TARGET_MAX32600MBED)
+#     define LED_PORT   Port7
+#     define LED1       (1 <<  0) // P7.0
+#     define LED2       (1 <<  6) // P7.6
+#     define LED3       (1 <<  4) // P7.4
+#     define LED4       0
 # endif
 
 #define LED_MASK    (LED1|LED2|LED3|LED4)
@@ -26,7 +35,7 @@ int mask[4] = {
     (LED3 | LED4)
 };
 
-PortOut ledport(Port1, LED_MASK);
+PortOut ledport(LED_PORT, LED_MASK);
 
 int main() {
     while (1) {

libraries/tests/mbed/portout_portin/main.cpp

@@ -72,6 +72,15 @@
 #define P2_2    (1 << 1)
 #define PORT_2  Port1
 
+#elif defined(TARGET_MAX32600MBED)
+#define P1_1    (1 << 0)  // P1_0
+#define P1_2    (1 << 1)  // P1_1
+#define PORT_1  Port1
+
+#define P2_1    (1 << 7)  // P4_7
+#define P2_2    (1 << 6)  // P4_6
+#define PORT_2  Port4
+
 #elif defined(TARGET_NUCLEO_F030R8) || \
       defined(TARGET_NUCLEO_F070RB) || \
       defined(TARGET_NUCLEO_F072RB) || \

libraries/tests/mbed/pwm/main.cpp

@@ -157,6 +157,15 @@ int main() {
     printf("Initialize PWM on pin PD_12 with duty cycle: %.2f\n", result);
 
     notify_completion(result == value ? true : false);
+#elif defined(TARGET_MAX32600MBED)
+    PwmOut pwm_1(P1_2);
+    PwmOut pwm_2(P1_3);
+
+    pwm_1.write(0.75);
+    pwm_2.write(0.50);
+
+    printf("Initialize PWM on pin P1.2 with duty cycle: %.2f\n", pwm_1.read());
+    printf("Initialize PWM on pin P1.3 with duty cycle: %.2f\n", pwm_2.read());
 #else
 #error This test is not supported on this target.
 #endif

libraries/tests/usb/device/midi/main.cpp

@@ -4,7 +4,70 @@
 USBMIDI midi;
 Serial pc(USBTX, USBRX);
 
+// MIDI IN
+void transmitMessage(MIDIMessage msg) {
+ 	switch (msg.type()) {
+        case MIDIMessage::NoteOnType:
+        	wait(0.1);
+			midi.write(MIDIMessage::NoteOn(msg.key()));
+            break;
+        case MIDIMessage::NoteOffType:
+        	wait(0.1);
+			midi.write(MIDIMessage::NoteOff(msg.key()));
+            break;
+        case MIDIMessage::ProgramChangeType:
+        	wait(0.1);
+        	midi.write(MIDIMessage::ProgramChange(msg.program()));
+            break;
+        case MIDIMessage::SysExType:
+        	wait(0.1);
+        	unsigned char tmp[64];
+            for(int i=0;i<msg.length-1;i++) {
+	            tmp[i]=msg.data[i+1];
+            }
+            midi.write(MIDIMessage::SysEx(tmp,msg.length-1));
+            break;
+        default:
+            break;
+    }    
+}
+
 int main(void)
 {
+	wait(5);
+	// MIDI OUT
+
+	// set piano
+	midi.write(MIDIMessage::ProgramChange(1));
+	wait(0.1);
+
+	// play A
+	midi.write(MIDIMessage::NoteOn(21));
+	wait(0.1);
+	midi.write(MIDIMessage::NoteOff(21));
+	wait(0.1);
+
+	// GM reset
+	unsigned char gm_reset[]={0xF0,0x7E,0x7F,0x09,0x01,0xF7};
+	midi.write(MIDIMessage::SysEx(gm_reset,6));
+	wait(0.1);
+
+	// GM Master volume max
+	unsigned char gm_master_vol_max[]={0xF0,0x7F,0x7F,0x04,0x01,0x7F,0x7F,0xF7};
+	midi.write(MIDIMessage::SysEx(gm_master_vol_max,8));
+	wait(0.1);
+
+	// GS reset
+	unsigned char gs_reset[]={0xF0,0x41,0x10,0x42,0x12,0x40,0x00,0x7F,0x00,0x41,0xF7};
+	midi.write(MIDIMessage::SysEx(gs_reset,11));
+	wait(0.1);
+
+	// GS Master volume max
+	unsigned char gs_master_vol_max[]={0xF0,0x41,0x10,0x42,0x12,0x40,0x00,0x04,0x7F,0x3D,0xF7};
+	midi.write(MIDIMessage::SysEx(gs_master_vol_max,11));
+	wait(0.1);
+
+	midi.attach(transmitMessage);
+
     while(1);
 }

workspace_tools/build_release.py

@@ -33,8 +33,8 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
     ('ARCH_PRO',     ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')),
     ('LPC2368',      ('ARM', 'GCC_ARM')),
     ('LPC812',       ('uARM','IAR')),
-    ('LPC824',       ('uARM', 'IAR', 'GCC_CR')),
+    ('LPC824',       ('uARM', 'GCC_ARM', 'IAR', 'GCC_CR')),
-    ('SSCI824',      ('uARM',)),
+    ('SSCI824',      ('uARM','GCC_ARM')),
     ('LPC1347',      ('ARM','IAR')),
     ('LPC4088',      ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')),
     ('LPC4088_DM',   ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')),

workspace_tools/export/gcc_arm_lpc824.tmpl

@@ -0,0 +1,77 @@
+# This file was automagically generated by mbed.org. For more information, 
+# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
+
+GCC_BIN = 
+PROJECT = {{name}}
+OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %}
+SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %}
+INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %}
+LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %}
+LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %}
+LINKER_SCRIPT = {{linker_script}}
+
+############################################################################### 
+AS      = $(GCC_BIN)arm-none-eabi-as
+CC      = $(GCC_BIN)arm-none-eabi-gcc
+CPP     = $(GCC_BIN)arm-none-eabi-g++
+LD      = $(GCC_BIN)arm-none-eabi-gcc
+OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy
+OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump
+SIZE 	= $(GCC_BIN)arm-none-eabi-size
+
+CPU = -mcpu=cortex-m0plus -mthumb
+CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer
+CC_FLAGS += -MMD -MP
+CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %}
+
+LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -Wl,--wrap,main
+LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref
+LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys
+
+ifeq ($(DEBUG), 1)
+  CC_FLAGS += -DDEBUG -O0
+else
+  CC_FLAGS += -DNDEBUG -Os
+endif
+
+all: $(PROJECT).bin $(PROJECT).hex 
+
+clean:
+	rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS)
+
+.s.o:
+	$(AS) $(CPU) -o $@ $<
+
+.c.o:
+	$(CC)  $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99   $(INCLUDE_PATHS) -o $@ $<
+
+.cpp.o:
+	$(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $<
+
+
+$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS)
+	$(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS)
+	@echo ""
+	@echo "*****"
+	@echo "***** You must modify vector checksum value in *.bin and *.hex files."
+	@echo "*****"
+	@echo ""
+	$(SIZE) $@
+
+$(PROJECT).bin: $(PROJECT).elf
+	@$(OBJCOPY) -O binary $< $@
+
+$(PROJECT).hex: $(PROJECT).elf
+	@$(OBJCOPY) -O ihex $< $@
+
+$(PROJECT).lst: $(PROJECT).elf
+	@$(OBJDUMP) -Sdh $< > $@
+
+lst: $(PROJECT).lst
+
+size:
+	$(SIZE) $(PROJECT).elf
+
+DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d)
+-include $(DEPS)
+

workspace_tools/export/gcc_arm_max32600mbed.tmpl

@@ -0,0 +1,72 @@
+# This file was automagically generated by mbed.org. For more information, 
+# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
+
+GCC_BIN = 
+PROJECT = {{name}}
+OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %}
+SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %}
+INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %}
+LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %}
+LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %}
+LINKER_SCRIPT = {{linker_script}}
+
+############################################################################### 
+AS      = $(GCC_BIN)arm-none-eabi-as
+CC      = $(GCC_BIN)arm-none-eabi-gcc
+CPP     = $(GCC_BIN)arm-none-eabi-g++
+LD      = $(GCC_BIN)arm-none-eabi-gcc
+OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy
+OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump
+SIZE 	= $(GCC_BIN)arm-none-eabi-size
+
+CPU = -mcpu=cortex-m3 -mthumb
+CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer
+CC_FLAGS += -MMD -MP
+CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %}
+
+LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main
+LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref
+LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys
+
+ifeq ($(DEBUG), 1)
+  CC_FLAGS += -DDEBUG -O0
+else
+  CC_FLAGS += -DNDEBUG -Os
+endif
+
+all: $(PROJECT).bin $(PROJECT).hex 
+
+clean:
+	rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS)
+
+.s.o:
+	$(AS) $(CPU) -o $@ $<
+
+.c.o:
+	$(CC)  $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99   $(INCLUDE_PATHS) -o $@ $<
+
+.cpp.o:
+	$(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $<
+
+
+$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS)
+	$(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS)
+	$(SIZE) $@
+
+$(PROJECT).bin: $(PROJECT).elf
+	@$(OBJCOPY) -O binary $< $@
+
+$(PROJECT).hex: $(PROJECT).elf
+	@$(OBJCOPY) -O ihex $< $@
+
+$(PROJECT).lst: $(PROJECT).elf
+	@$(OBJDUMP) -Sdh $< > $@
+
+lst: $(PROJECT).lst
+
+size:
+	$(SIZE) $(PROJECT).elf
+
+DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d)
+-include $(DEPS)
+

workspace_tools/export/gcc_arm_maxwsnenv.tmpl

@@ -0,0 +1,72 @@
+# This file was automagically generated by mbed.org. For more information, 
+# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
+
+GCC_BIN = 
+PROJECT = {{name}}
+OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %}
+SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %}
+INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %}
+LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %}
+LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %}
+LINKER_SCRIPT = {{linker_script}}
+
+############################################################################### 
+AS      = $(GCC_BIN)arm-none-eabi-as
+CC      = $(GCC_BIN)arm-none-eabi-gcc
+CPP     = $(GCC_BIN)arm-none-eabi-g++
+LD      = $(GCC_BIN)arm-none-eabi-gcc
+OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy
+OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump
+SIZE 	= $(GCC_BIN)arm-none-eabi-size
+
+CPU = -mcpu=cortex-m3 -mthumb
+CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer
+CC_FLAGS += -MMD -MP
+CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %}
+
+LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float -Wl,--wrap,main
+LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref
+LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys
+
+ifeq ($(DEBUG), 1)
+  CC_FLAGS += -DDEBUG -O0
+else
+  CC_FLAGS += -DNDEBUG -Os
+endif
+
+all: $(PROJECT).bin $(PROJECT).hex 
+
+clean:
+	rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS)
+
+.s.o:
+	$(AS) $(CPU) -o $@ $<
+
+.c.o:
+	$(CC)  $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99   $(INCLUDE_PATHS) -o $@ $<
+
+.cpp.o:
+	$(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $<
+
+
+$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS)
+	$(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS)
+	$(SIZE) $@
+
+$(PROJECT).bin: $(PROJECT).elf
+	@$(OBJCOPY) -O binary $< $@
+
+$(PROJECT).hex: $(PROJECT).elf
+	@$(OBJCOPY) -O ihex $< $@
+
+$(PROJECT).lst: $(PROJECT).elf
+	@$(OBJDUMP) -Sdh $< > $@
+
+lst: $(PROJECT).lst
+
+size:
+	$(SIZE) $(PROJECT).elf
+
+DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d)
+-include $(DEPS)
+

workspace_tools/export/gcc_arm_ssci824.tmpl

@@ -0,0 +1,77 @@
+# This file was automagically generated by mbed.org. For more information, 
+# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
+
+GCC_BIN = 
+PROJECT = {{name}}
+OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %}
+SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %}
+INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %}
+LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %}
+LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %}
+LINKER_SCRIPT = {{linker_script}}
+
+############################################################################### 
+AS      = $(GCC_BIN)arm-none-eabi-as
+CC      = $(GCC_BIN)arm-none-eabi-gcc
+CPP     = $(GCC_BIN)arm-none-eabi-g++
+LD      = $(GCC_BIN)arm-none-eabi-gcc
+OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy
+OBJDUMP = $(GCC_BIN)arm-none-eabi-objdump
+SIZE 	= $(GCC_BIN)arm-none-eabi-size
+
+CPU = -mcpu=cortex-m0plus -mthumb
+CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer
+CC_FLAGS += -MMD -MP
+CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %}
+
+LD_FLAGS = $(CPU) -Wl,--gc-sections --specs=nano.specs -Wl,--wrap,main
+LD_FLAGS += -Wl,-Map=$(PROJECT).map,--cref
+LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys
+
+ifeq ($(DEBUG), 1)
+  CC_FLAGS += -DDEBUG -O0
+else
+  CC_FLAGS += -DNDEBUG -Os
+endif
+
+all: $(PROJECT).bin $(PROJECT).hex 
+
+clean:
+	rm -f $(PROJECT).bin $(PROJECT).elf $(PROJECT).hex $(PROJECT).map $(PROJECT).lst $(OBJECTS) $(DEPS)
+
+.s.o:
+	$(AS) $(CPU) -o $@ $<
+
+.c.o:
+	$(CC)  $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99   $(INCLUDE_PATHS) -o $@ $<
+
+.cpp.o:
+	$(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 -fno-rtti $(INCLUDE_PATHS) -o $@ $<
+
+
+$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS)
+	$(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS)
+	@echo ""
+	@echo "*****"
+	@echo "***** You must modify vector checksum value in *.bin and *.hex files."
+	@echo "*****"
+	@echo ""
+	$(SIZE) $@
+
+$(PROJECT).bin: $(PROJECT).elf
+	@$(OBJCOPY) -O binary $< $@
+
+$(PROJECT).hex: $(PROJECT).elf
+	@$(OBJCOPY) -O ihex $< $@
+
+$(PROJECT).lst: $(PROJECT).elf
+	@$(OBJDUMP) -Sdh $< > $@
+
+lst: $(PROJECT).lst
+
+size:
+	$(SIZE) $(PROJECT).elf
+
+DEPS = $(OBJECTS:.o=.d) $(SYS_OBJECTS:.o=.d)
+-include $(DEPS)
+

workspace_tools/export/gccarm.py

@@ -40,6 +40,8 @@ class GccArm(Exporter):
         'LPC11U35_401',
         'LPC11U35_501',
         'LPC11U37H_401',
+        'LPC824',
+        'SSCI824',
         'STM32F407',
         'DISCO_F100RB',
         'DISCO_F051R8',
@@ -71,6 +73,8 @@ class GccArm(Exporter):
         'NUCLEO_L053R8',
         'NUCLEO_L073RZ',
         'DISCO_F334C8',
+        'MAX32600MBED',
+        'MAXWSNENV',
         'MTS_MDOT_F405RG',
         'MTS_MDOT_F411RE',
         'NUCLEO_L152RE',

workspace_tools/export/iar.py

@@ -60,6 +60,8 @@ class IAREmbeddedWorkbench(Exporter):
         'NUCLEO_L073RZ',
         'NUCLEO_L152RE',
         #'STM32F407', Fails to build same for GCC
+        'MAXWSNENV',
+        'MAX32600MBED',
         'MTS_MDOT_F405RG',
         'MTS_MDOT_F411RE',
         'MTS_DRAGONFLY_F411RE',

workspace_tools/export/iar_max32600mbed.ewp.tmpl

@@ -0,0 +1,957 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>22</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>debug\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>debug\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>debug\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>21</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>5.10.5.252</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>7.30.1.7765</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>MAX32600x85	Maxim MAX32600x85</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>21</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>21</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          {% for s in symbols %}
+            <state>{{s}}</state>
+          {% endfor %}
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050,Pa084,Pa093,Pa082</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>11111110</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+        {% for path in include_paths %}
+          <state>$PROJ_DIR$\{{path}}</state>
+        {% endfor %}
+          <state></state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>2</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>2</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCNoLiteralPool</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptStrategySlave</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCGuardCalls</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>9</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AsmNoLiteralPool</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>{{name}}.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>16</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>cpp.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\{{linker_script}}</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state>--skip_dynamic_initialization</state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+        {% for library in libraries %}
+          <state>$PROJ_DIR$\{{library}}</state>
+        {% endfor %}
+        {% for object in object_files %}
+          <state>$PROJ_DIR$\{{object}}</state>
+        {% endfor %}
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  {{source_files}}
+</project>

workspace_tools/export/iar_maxwsnenv.ewp.tmpl

@@ -0,0 +1,957 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>22</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>debug\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>debug\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>debug\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>21</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Full formatting.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the full configuration of the C/C++ runtime library. Full locale interface, C locale, file descriptor support, multibytes in printf and scanf, and hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>5.10.5.252</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>7.30.1.7765</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>MAX32600x85	Maxim MAX32600x85</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Full.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>21</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>21</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibThreads</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>31</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDefines</name>
+          {% for s in symbols %}
+            <state>{{s}}</state>
+          {% endfor %}
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050,Pa084,Pa093,Pa082</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>11111110</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+        {% for path in include_paths %}
+          <state>$PROJ_DIR$\{{path}}</state>
+        {% endfor %}
+          <state></state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndRwpi</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>2</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>2</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCNoLiteralPool</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptStrategySlave</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCGuardCalls</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>9</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AsmNoLiteralPool</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state>{{name}}.bin</state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>16</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>cpp.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\{{linker_script}}</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state>--skip_dynamic_initialization</state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+        {% for library in libraries %}
+          <state>$PROJ_DIR$\{{library}}</state>
+        {% endfor %}
+        {% for object in object_files %}
+          <state>$PROJ_DIR$\{{object}}</state>
+        {% endfor %}
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
+        </option>
+        <option>
+          <name>FillerStart</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>FillerEnd</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
+        </option>
+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkThreadsSlave</name>
+          <state>1</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  {{source_files}}
+</project>

workspace_tools/export/uvision4.py

@@ -73,6 +73,8 @@ class Uvision4(Exporter):
         'SEEED_TINY_BLE',
         'LPC11U37H_401',
         'DELTA_DFCM_NNN40',
+        'MAXWSNENV',
+        'MAX32600MBED',
     ]
 
     USING_MICROLIB = [

workspace_tools/export/uvision4_max32600mbed.uvopt.tmpl

@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>MAX32600MBED</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>24000000</CLKADS>
+      <OPTTT>
+        <gFlags></gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>13</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>8</FileType>
+      <tvExp>0</tvExp>
+      <Focus>0</Focus>
+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>2</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+    </File>
+  </Group>
+
+</ProjectOpt>

workspace_tools/export/uvision4_max32600mbed.uvproj.tmpl

@@ -0,0 +1,420 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
+
+  <Targets>
+    <Target>
+      <TargetName>MAX32600MBED</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MAX32600</Device>
+          <Vendor>Maxim Integrated</Vendor>
+          <Cpu>IRAM(0x20000000, 0x8000) IROM(0, 0x40000) CLOCK(24000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll></FlashDriverDll>
+          <DeviceId></DeviceId>
+          <RegisterFile></RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>{{name}}</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin -o build\{{name}}_max32600.bin build\{{name}}.axf</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments></TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection></TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver></Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll></UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection></DriverSelection>
+          </Flash1>
+          <bUseTDR>0</bUseTDR>
+          <Flash2></Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>0</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x8000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x8000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x10000000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>0</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <VariousControls>
+              <MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
+              <Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
+              <Undefine></Undefine>
+              <IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x10000000</DataAddressRange>
+            <ScatterFile>{{scatter_file}}</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc>
+            {% for file in object_files %}
+              {{file}}
+            {% endfor %}
+            </Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        {% for group,files in source_files %}
+        <Group>
+          <GroupName>{{group}}</GroupName>
+          <Files>
+            {% for file in files %}
+            <File>
+              <FileName>{{file.name}}</FileName>
+              <FileType>{{file.type}}</FileType>
+              <FilePath>{{file.path}}</FilePath>
+              {%if file.type == "1" %}
+              <FileOption>
+                <FileArmAds>
+                  <Cads>
+                    <VariousControls>
+                      <MiscControls>--c99</MiscControls>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+              {% endif %}
+            </File>
+          {% endfor %}
+          </Files>
+        </Group>
+        {% endfor %}
+      </Groups>
+    </Target>
+  </Targets>
+
+</Project>

workspace_tools/export/uvision4_maxwsnenv.uvopt.tmpl

@@ -0,0 +1,177 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>MAXWSNENV</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>24000000</CLKADS>
+      <OPTTT>
+        <gFlags></gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>1</RunSim>
+        <RunTarget>0</RunTarget>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>8</CpuCode>
+      <DllOpt>
+        <SimDllName>SARMCM3.DLL</SimDllName>
+        <SimDllArguments></SimDllArguments>
+        <SimDlgDllName>DCM.DLL</SimDlgDllName>
+        <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+        <TargetDllName>SARMCM3.DLL</TargetDllName>
+        <TargetDllArguments></TargetDllArguments>
+        <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+        <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+      </DllOpt>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>0</tRtrace>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <nTsel>13</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>src</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
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+      <tvExp>0</tvExp>
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+      <ColumnNumber>0</ColumnNumber>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <TopLine>1</TopLine>
+      <CurrentLine>2</CurrentLine>
+      <bDave2>0</bDave2>
+      <PathWithFileName>main.cpp</PathWithFileName>
+      <FilenameWithoutPath>main.cpp</FilenameWithoutPath>
+    </File>
+  </Group>
+
+</ProjectOpt>