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Fix PWM1 clock source setting error

pull/3227/head
ccli8 2016-10-18 10:32:41 +08:00 committed by Anna Bridge
parent 06b7d5df39
commit c4f0ce24c5
2 changed files with 60 additions and 41 deletions
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52
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.c
View File

@ -1,8 +1,8 @@
/**************************************************************************//**
* @file PWM.c
* @version V1.00
* $Revision: 22 $
* $Date: 14/10/02 9:21a $
* $Revision: 26 $
* $Date: 15/11/18 2:34p $
* @brief NUC472/NUC442 PWM driver source file
*
* @note
@ -52,14 +52,14 @@ uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
* existing frequency of other channel.
*/
uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
uint32_t u32ChannelNum,
uint32_t u32Frequency,
uint32_t u32DutyCycle,
uint32_t u32Frequency2)
uint32_t PWM_ConfigOutputChannel2 (PWM_T *pwm,
uint32_t u32ChannelNum,
uint32_t u32Frequency,
uint32_t u32DutyCycle,
uint32_t u32Frequency2)
{
uint32_t i;
uint32_t u32PWM_CLock;
uint32_t u32PWM_CLock = __HIRC;
uint8_t u8Divider = 1, u8Prescale = 0xFF;
uint16_t u16CNR = 0xFFFF;
@ -100,15 +100,15 @@ uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm,
}
} else if (pwm == PWM1) {
if (u32ChannelNum < 2) {
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 0)
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __HXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 1)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 2)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = SystemCoreClock;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 3)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 4)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __LIRC;
} else if (u32ChannelNum < 4) {
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
@ -207,7 +207,7 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
uint32_t u32CaptureEdge)
{
uint32_t i;
uint32_t u32PWM_CLock;
uint32_t u32PWM_CLock = __HIRC;
uint8_t u8Divider = 1, u8Prescale = 0xFF;
uint16_t u16CNR = 0xFFFF;
@ -248,15 +248,15 @@ uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm,
}
} else if (pwm == PWM1) {
if (u32ChannelNum < 2) {
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 0)
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __HXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 1)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (1 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __LXT;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 2)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (2 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = SystemCoreClock;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 3)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (3 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __HIRC;
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == 4)
else if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH01SEL_Msk) == (4 << CLK_CLKSEL2_PWM1CH01SEL_Pos))
u32PWM_CLock = __LIRC;
} else if (u32ChannelNum < 4) {
if ((CLK->CLKSEL2 & CLK_CLKSEL2_PWM1CH23SEL_Msk) == (0 << CLK_CLKSEL2_PWM1CH23SEL_Pos))
@ -451,6 +451,7 @@ uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum)
* - \ref PWM_BRK0_CPO0
* - \ref PWM_BRK0_CPO1
* - \ref PWM_BRK0_CPO2
* - \ref PWM_BRK1_LVDBK
* - \ref PWM_BK1SEL_BKP1
* - \ref PWM_BK1SEL_CPO0
* - \ref PWM_BK1SEL_CPO1
@ -463,20 +464,29 @@ void PWM_EnableFaultBrake (PWM_T *pwm,
{
if ((u32BrakeSource == PWM_BRK0_BKP0)||(u32BrakeSource == PWM_BRK0_CPO0)||(u32BrakeSource == PWM_BRK0_CPO1)||(u32BrakeSource == PWM_BRK0_CPO2))
pwm->BRKCTL |= (u32BrakeSource | PWM_BRKCTL_BRK0EN_Msk);
else if (u32BrakeSource == PWM_BRK1_LVDBK)
pwm->BRKCTL |= PWM_BRKCTL_LVDBKEN_Msk;
else
pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BK1SEL_Msk) | u32BrakeSource | PWM_BRKCTL_BRK1EN_Msk;
pwm->BRKCTL = (pwm->BRKCTL & ~PWM_BRKCTL_BKOD_Msk) | (u32LevelMask << PWM_BRKCTL_BKOD_Pos);
}
/**
* @brief This function clear fault brake flag
* @param[in] pwm The base address of PWM module
* @param[in] u32BrakeSource This parameter is not used
* @param[in] u32BrakeSource Fault brake source 0 or 1
* 0: brake 0, 1: brake 1
* @return None
* @note After fault brake occurred, application must clear fault brake source before re-enable PWM output
*/
void PWM_ClearFaultBrakeFlag (PWM_T *pwm, uint32_t u32BrakeSource)
{
pwm->INTSTS = PWM_INTSTS_BRKLK0_Msk;
if (u32BrakeSource == 0)
pwm->INTSTS = (PWM_INTSTS_BRKLK0_Msk | PWM_INTSTS_BRKIF0_Msk);
else
pwm->INTSTS = PWM_INTSTS_BRKIF1_Msk;
}
/**

49
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.h
View File

@ -1,8 +1,8 @@
/**************************************************************************//**
* @file pwm.h
* @version V1.00
* $Revision: 19 $
* $Date: 14/10/06 1:36p $
* $Revision: 22 $
* $Date: 15/11/16 2:08p $
* @brief NUC472/NUC442 PWM driver header file
*
* @note
@ -29,14 +29,18 @@ extern "C"
@{
*/
#define PWM_CHANNEL_NUM (6) /*!< PWM channel number \hideinitializer */
#define PWM_CH0 (0UL) /*!< PWM channel 0 \hideinitializer */
#define PWM_CH1 (1UL) /*!< PWM channel 1 \hideinitializer */
#define PWM_CH2 (2UL) /*!< PWM channel 2 \hideinitializer */
#define PWM_CH3 (3UL) /*!< PWM channel 3 \hideinitializer */
#define PWM_CH4 (4UL) /*!< PWM channel 4 \hideinitializer */
#define PWM_CH5 (5UL) /*!< PWM channel 5 \hideinitializer */
#define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */
#define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */
#define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */
#define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */
#define PWM_CH_4_MASK (16UL) /*!< PWM channel 4 mask \hideinitializer */
#define PWM_CH_5_MASK (32UL) /*!< PWM channel 5 mask \hideinitializer */
#define PWM_CH_6_MASK (64UL) /*!< PWM channel 6 mask \hideinitializer */
#define PWM_CH_7_MASK (128UL) /*!< PWM channel 7 mask \hideinitializer */
#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */
#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */
#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */
@ -48,10 +52,11 @@ extern "C"
#define PWM_TRIGGER_ADC_FALLING_EDGE_POINT (0x10000UL) /*!< PWM trigger ADC while output falling edge is detected \hideinitializer */
#define PWM_TRIGGER_ADC_CENTER_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (CNR + 1) \hideinitializer */
#define PWM_TRIGGER_ADC_PERIOD_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
#define PWM_BRK0_BKP0 (0UL) /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
#define PWM_BRK0_BKP0 (PWM_BRKCTL_BRK0EN_Msk) /*!< Brake0 signal source from external pin BKP0 \hideinitializer */
#define PWM_BRK0_CPO0 (PWM_BRKCTL_CPO0BKEN_Msk) /*!< Brake0 signal source from analog comparator 0 output \hideinitializer */
#define PWM_BRK0_CPO1 (PWM_BRKCTL_CPO1BKEN_Msk) /*!< Brake0 signal source from analog comparator 1 output \hideinitializer */
#define PWM_BRK0_CPO2 (PWM_BRKCTL_CPO2BKEN_Msk) /*!< Brake0 signal source from analog comparator 2 output \hideinitializer */
#define PWM_BRK1_LVDBK (PWM_BRKCTL_LVDBKEN_Msk) /*!< Brake1 signal source from level detect \hideinitializer */
#define PWM_BK1SEL_BKP1 (0UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from external pin BKP1 \hideinitializer */
#define PWM_BK1SEL_CPO0 (1UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 0 output \hideinitializer */
#define PWM_BK1SEL_CPO1 (2UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 1 output \hideinitializer */
@ -79,7 +84,7 @@ extern "C"
* @return None
* \hideinitializer
*/
#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_OUTMODE_Msk)
#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_OUTMODE_Msk)
/**
* @brief This macro disable complementary mode, and enable independent mode.
@ -87,7 +92,7 @@ extern "C"
* @return None
* \hideinitializer
*/
#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_OUTMODE_Msk)
#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_OUTMODE_Msk)
/**
* @brief This macro enable group mode
@ -95,7 +100,7 @@ extern "C"
* @return None
* \hideinitializer
*/
#define PWM_ENABLE_GROUP_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_GROUPEN_Msk)
#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_GROUPEN_Msk)
/**
* @brief This macro disable group mode
@ -103,7 +108,7 @@ extern "C"
* @return None
* \hideinitializer
*/
#define PWM_DISABLE_GROUP_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_GROUPEN_Msk)
#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_GROUPEN_Msk)
/**
* @brief This macro enable synchronous mode
@ -111,7 +116,7 @@ extern "C"
* @return None
* \hideinitializer
*/
#define PWM_ENABLE_SYNC_MODE(pwm) (pwm->CTL = pwm->CTL | PWM_CTL_SYNCEN_Msk)
#define PWM_ENABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_SYNCEN_Msk)
/**
* @brief This macro disable synchronous mode, and enable independent mode.
@ -119,7 +124,7 @@ extern "C"
* @return None
* \hideinitializer
*/
#define PWM_DISABLE_SYNC_MODE(pwm) (pwm->CTL = pwm->CTL & ~PWM_CTL_SYNCEN_Msk)
#define PWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_SYNCEN_Msk)
/**
* @brief This macro enable output inverter of specified channel(s)
@ -129,7 +134,7 @@ extern "C"
* @return None
* \hideinitializer
*/
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) (pwm->CTL |= (u32ChannelMask << PWM_CTL_PINV_Pos)
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->CTL = (((pwm)->CTL & ~PWM_CTL_PINV_Msk) | ((u32ChannelMask) << PWM_CTL_PINV_Pos)))
/**
* @brief This macro get captured rising data
@ -138,7 +143,7 @@ extern "C"
* @return None
* \hideinitializer
*/
#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->RCAPDAT0 + 2 * u32ChannelNum))
#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->RCAPDAT0 + 2 * (u32ChannelNum)))
/**
* @brief This macro get captured falling data
@ -147,7 +152,7 @@ extern "C"
* @return None
* \hideinitializer
*/
#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&pwm->FCAPDAT0 + 2 * u32ChannelNum))
#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->FCAPDAT0 + 2 * (u32ChannelNum)))
/**
* @brief This macro mask output output logic to high or low
@ -158,7 +163,7 @@ extern "C"
* @return None
* \hideinitializer
*/
#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) (pwm->MSKEN |= u32ChannelMask)
#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) ((pwm)->MSKEN |= (u32ChannelMask))
/**
* @brief This macro set the prescaler of the selected channel
@ -171,7 +176,7 @@ extern "C"
* \hideinitializer
*/
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
(pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
(pwm->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
/**
* @brief This macro set the divider of the selected channel
@ -187,7 +192,7 @@ extern "C"
* \hideinitializer
*/
#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
(pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
/**
* @brief This macro set the duty of the selected channel
@ -198,7 +203,7 @@ extern "C"
* @note This new setting will take effect on next PWM period
* \hideinitializer
*/
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (pwm->CMPDAT[u32ChannelNum] = (u32CMR))
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
/**
* @brief This macro set the period of the selected channel
@ -210,7 +215,7 @@ extern "C"
* @note PWM counter will stop if period length set to 0
* \hideinitializer
*/
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) (pwm->PERIOD[u32ChannelNum] = (u32CNR))
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
/**
* @brief This macro set the PWM aligned type
@ -224,7 +229,11 @@ extern "C"
* \hideinitializer
*/
#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
(pwm->CTL = (pwm->CTL & ~(u32ChannelMask << PWM_CTL_CNTMODE_Pos) | (u32AlignedType << PWM_CTL_CNTMODE_Pos))
do { \
(pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk); \
if ((u32AlignedType) == PWM_CENTER_ALIGNED) \
(pwm)->CTL = ((pwm)->CTL | ((u32ChannelMask) << PWM_CTL_CNTTYPE_Pos)); \
} while(0)
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,