mirror of https://github.com/ARMmbed/mbed-os.git
Modify to support GCC. (CMSIS-RTOS RTX for Cortex-A9)
Masao Hamanaka
parent
aba8a90630
commit
c46f5b894b
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@ -258,40 +258,6 @@ void _main_init (void) {
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#pragma pop
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#endif
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#else
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#if 0
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//#ifdef __MBED_CMSIS_RTOS_CA9
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__asm void __rt_entry (void) {
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IMPORT __user_setup_stackheap
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IMPORT __rt_lib_init
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IMPORT os_thread_def_main
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IMPORT osKernelInitialize
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IMPORT osKernelStart
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IMPORT osThreadCreate
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IMPORT InterruptHandlerRegister
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IMPORT PendSV_Handler
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IMPORT OS_Tick_Handler
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IMPORT exit
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BL __user_setup_stackheap
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MOV R1,R2
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BL __rt_lib_init
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BL osKernelInitialize
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LDR R0,=os_thread_def_main
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MOVS R1,#0
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BL osThreadCreate
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BL osKernelStart
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MOVS R0,#0
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LDR R1,=PendSV_Handler
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BL InterruptHandlerRegister
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MOVS R0,#134
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LDR R1,=OS_Tick_Handler
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BL InterruptHandlerRegister
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BL exit
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ALIGN
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}
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#else
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__asm void __rt_entry (void) {
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IMPORT __user_setup_stackheap
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@ -315,7 +281,6 @@ __asm void __rt_entry (void) {
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ALIGN
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}
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#endif
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#endif
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#elif defined (__GNUC__)
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@ -375,7 +340,7 @@ __attribute ((noreturn)) void __cs3_start_c (void){
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__attribute__((naked)) void software_init_hook (void) {
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__asm (
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".syntax unified\n"
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".thumb\n"
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".arm\n"
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"movs r0,#0\n"
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"movs r1,#0\n"
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"mov r4,r0\n"
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@ -0,0 +1,474 @@
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/*----------------------------------------------------------------------------
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* RL-ARM - RTX
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*----------------------------------------------------------------------------
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* Name: HAL_CA9.c
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* Purpose: Hardware Abstraction Layer for Cortex-A9
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* Rev.: 3 Sept 2013
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*----------------------------------------------------------------------------
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*
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* Copyright (c) 2012 - 2013 ARM Limited
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* All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* - Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* - Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*---------------------------------------------------------------------------*/
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.global rt_set_PSP
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.global rt_get_PSP
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.global _alloc_box
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.global _free_box
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.global PendSV_Handler
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.global OS_Tick_Handler
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.EQU CPSR_T_BIT, 0x20
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.EQU CPSR_I_BIT, 0x80
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.EQU CPSR_F_BIT, 0x40
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.EQU MODE_USR, 0x10
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.EQU MODE_FIQ, 0x11
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.EQU MODE_IRQ, 0x12
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.EQU MODE_SVC, 0x13
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.EQU MODE_ABT, 0x17
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.EQU MODE_UND, 0x1B
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.EQU MODE_SYS, 0x1F
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.EQU TCB_TID, 3 /* 'task id' offset */
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.EQU TCB_STACKF, 32 /* 'stack_frame' offset */
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.EQU TCB_TSTACK, 36 /* 'tsk_stack' offset */
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.extern rt_alloc_box
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.extern os_tsk
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.extern GICInterface_BASE
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.extern rt_pop_req
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.extern os_tick_irqack
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.extern rt_systick
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/*----------------------------------------------------------------------------
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* Functions
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*---------------------------------------------------------------------------*/
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.text
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@ For A-class, set USR/SYS stack
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@ __asm void rt_set_PSP (U32 stack) {
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rt_set_PSP:
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.arm
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MRS R1, CPSR
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CPS #MODE_SYS @no effect in USR mode
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ISB
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MOV SP, R0
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MSR CPSR_c, R1 @no effect in USR mode
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ISB
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BX LR
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@ }
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@ For A-class, get USR/SYS stack
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@ __asm U32 rt_get_PSP (void) {
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rt_get_PSP:
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.arm
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MRS R1, CPSR
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CPS #MODE_SYS @no effect in USR mode
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ISB
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MOV R0, SP
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MSR CPSR_c, R1 @no effect in USR mode
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ISB
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BX LR
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@ }
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/*--------------------------- _alloc_box ------------------------------------*/
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@ __asm void *_alloc_box (void *box_mem) {
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_alloc_box:
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/* Function wrapper for Unprivileged/Privileged mode. */
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.arm
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LDR R12,=rt_alloc_box @ __cpp(rt_alloc_box)
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MRS R2, CPSR
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LSLS R2, #28
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BXNE R12
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SVC 0
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BX LR
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@ }
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/*--------------------------- _free_box -------------------------------------*/
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@ __asm int _free_box (void *box_mem, void *box) {
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_free_box:
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/* Function wrapper for Unprivileged/Privileged mode. */
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.arm
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LDR R12,=rt_free_box @ __cpp(rt_free_box)
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MRS R2, CPSR
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LSLS R2, #28
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BXNE R12
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SVC 0
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BX LR
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@ }
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/*-------------------------- SVC_Handler -----------------------------------*/
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@ #pragma push
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@ #pragma arm
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@ __asm void SVC_Handler (void) {
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.type SVC_Handler, %function
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.global SVC_Handler
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SVC_Handler:
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@ PRESERVE8
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.arm
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.extern rt_tsk_lock
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.extern rt_tsk_unlock
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.extern SVC_Count
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.extern SVC_Table
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.extern rt_stk_check
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.extern FPUEnable
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.EQU Mode_SVC, 0x13
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SRSDB SP!, #Mode_SVC @ Push LR_SVC and SPRS_SVC onto SVC mode stack
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PUSH {R4} @ Push R4 so we can use it as a temp
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MRS R4,SPSR @ Get SPSR
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TST R4,#CPSR_T_BIT @ Check Thumb Bit
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LDRNEH R4,[LR,#-2] @ Thumb: Load Halfword
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BICNE R4,R4,#0xFF00 @ Extract SVC Number
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LDREQ R4,[LR,#-4] @ ARM: Load Word
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BICEQ R4,R4,#0xFF000000 @ Extract SVC Number
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/* Lock out systick and re-enable interrupts */
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PUSH {R0-R3,R12,LR}
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AND R12, SP, #4 @ Ensure stack is 8-byte aligned
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SUB SP, SP, R12 @ Adjust stack
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PUSH {R12, LR} @ Store stack adjustment and dummy LR to SVC stack
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BLX rt_tsk_lock
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CPSIE i
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POP {R12, LR} @ Get stack adjustment & discard dummy LR
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ADD SP, SP, R12 @ Unadjust stack
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POP {R0-R3,R12,LR}
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CMP R4,#0
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BNE SVC_User
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MRS R4,SPSR
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PUSH {R4} @ Push R4 so we can use it as a temp
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AND R4, SP, #4 @ Ensure stack is 8-byte aligned
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SUB SP, SP, R4 @ Adjust stack
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PUSH {R4, LR} @ Store stack adjustment and dummy LR
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BLX R12
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POP {R4, LR} @ Get stack adjustment & discard dummy LR
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ADD SP, SP, R4 @ Unadjust stack
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POP {R4} @ Restore R4
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MSR SPSR_cxsf,R4
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/* Here we will be in SVC mode (even if coming in from PendSV_Handler or OS_Tick_Handler) */
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Sys_Switch:
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LDR LR,=os_tsk @ __cpp(&os_tsk)
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LDM LR,{R4,LR} @ os_tsk.run, os_tsk.new
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CMP R4,LR
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BNE switching
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PUSH {R0-R3,R12,LR}
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AND R12, SP, #4 @ Ensure stack is 8-byte aligned
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SUB SP, SP, R12 @ Adjust stack
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PUSH {R12, LR} @ Store stack adjustment and dummy LR to SVC stack
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CPSID i
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BLX rt_tsk_unlock
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POP {R12, LR} @ Get stack adjustment & discard dummy LR
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ADD SP, SP, R12 @ Unadjust stack
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POP {R0-R3,R12,LR}
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POP {R4}
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RFEFD SP! @ Return from exception, no task switch
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switching:
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CLREX
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CMP R4,#0
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ADDEQ SP,SP,#12 @ Original R4, LR & SPSR do not need to be popped when we are paging in a different task
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BEQ SVC_Next @ Runtask deleted?
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PUSH {R8-R11} @ R4 and LR already stacked
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MOV R10,R4 @ Preserve os_tsk.run
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MOV R11,LR @ Preserve os_tsk.new
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ADD R8,SP,#16 @ Unstack R4,LR
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LDMIA R8,{R4,LR}
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SUB SP,SP,#4 @ Make space on the stack for the next instn
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STMIA SP,{SP}^ @ Put User SP onto stack
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POP {R8} @ Pop User SP into R8
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MRS R9,SPSR
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STMDB R8!,{R9} @ User CPSR
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STMDB R8!,{LR} @ User PC
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STMDB R8,{LR}^ @ User LR
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SUB R8,R8,#4 @ No writeback for store of User LR
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STMDB R8!,{R0-R3,R12} @ User R0-R3,R12
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MOV R3,R10 @ os_tsk.run
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MOV LR,R11 @ os_tsk.new
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POP {R9-R12}
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ADD SP,SP,#12 @ Fix up SP for unstack of R4, LR & SPSR
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STMDB R8!,{R4-R7,R9-R12} @ User R4-R11
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@ If applicable, stack VFP state
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MRC p15,0,R1,c1,c0,2 @ VFP/NEON access enabled? (CPACR)
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AND R2,R1,#0x00F00000
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CMP R2,#0x00F00000
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BNE no_outgoing_vfp
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VMRS R2,FPSCR
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STMDB R8!,{R2,R4} @ Push FPSCR, maintain 8-byte alignment
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VSTMDB R8!,{S0-S31}
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LDRB R2,[R3,#TCB_STACKF] @ Record in TCB that VFP state is stacked
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ORR R2,#2
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STRB R2,[R3,#TCB_STACKF]
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no_outgoing_vfp:
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STR R8,[R3,#TCB_TSTACK]
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MOV R4,LR
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PUSH {R4} @ Push R4 so we can use it as a temp
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AND R4, SP, #4 @ Ensure stack is 8-byte aligned
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SUB SP, SP, R4 @ Adjust stack
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PUSH {R4, LR} @ Store stack adjustment and dummy LR to SVC stack
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BLX rt_stk_check
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POP {R4, LR} @ Get stack adjustment & discard dummy LR
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ADD SP, SP, R4 @ Unadjust stack
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POP {R4} @ Restore R4
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MOV LR,R4
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SVC_Next: @ R4 == os_tsk.run, LR == os_tsk.new, R0-R3, R5-R12 corruptible
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LDR R1,=os_tsk @ __cpp(&os_tsk), os_tsk.run = os_tsk.new
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STR LR,[R1]
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LDRB R1,[LR,#TCB_TID] @ os_tsk.run->task_id
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LSL R1,#8 @ Store PROCID
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MCR p15,0,R1,c13,c0,1 @ Write CONTEXTIDR
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LDR R0,[LR,#TCB_TSTACK] @ os_tsk.run->tsk_stack
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@ Does incoming task have VFP state in stack?
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LDRB R3,[LR,#TCB_STACKF]
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TST R3,#0x2
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MRC p15,0,R1,c1,c0,2 @ Read CPACR
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ANDEQ R1,R1,#0xFF0FFFFF @ Disable VFP access if incoming task does not have stacked VFP state
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ORRNE R1,R1,#0x00F00000 @ Enable VFP access if incoming task does have stacked VFP state
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MCR p15,0,R1,c1,c0,2 @ Write CPACR
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BEQ no_incoming_vfp
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ISB @ We only need the sync if we enabled, otherwise we will context switch before next VFP instruction anyway
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VLDMIA R0!,{S0-S31}
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LDR R2,[R0]
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VMSR FPSCR,R2
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ADD R0,R0,#8
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no_incoming_vfp:
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LDR R1,[R0,#60] @ Restore User CPSR
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MSR SPSR_cxsf,R1
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LDMIA R0!,{R4-R11} @ Restore User R4-R11
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ADD R0,R0,#4 @ Restore User R1-R3,R12
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LDMIA R0!,{R1-R3,R12}
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LDMIA R0,{LR}^ @ Restore User LR
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ADD R0,R0,#4 @ No writeback for load to user LR
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LDMIA R0!,{LR} @ Restore User PC
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ADD R0,R0,#4 @ Correct User SP for unstacked user CPSR
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PUSH {R0} @ Push R0 onto stack
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LDMIA SP,{SP}^ @ Get R0 off stack into User SP
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ADD SP,SP,#4 @ Put SP back
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LDR R0,[R0,#-32] @ Restore R0
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PUSH {R0-R3,R12,LR}
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AND R12, SP, #4 @ Ensure stack is 8-byte aligned
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SUB SP, SP, R12 @ Adjust stack
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PUSH {R12, LR} @ Store stack adjustment and dummy LR to SVC stack
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CPSID i
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BLX rt_tsk_unlock
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POP {R12, LR} @ Get stack adjustment & discard dummy LR
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ADD SP, SP, R12 @ Unadjust stack
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POP {R0-R3,R12,LR}
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MOVS PC,LR @ Return from exception
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/*------------------- User SVC -------------------------------*/
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SVC_User:
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LDR R12,=SVC_Count
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LDR R12,[R12]
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CMP R4,R12 @ Check for overflow
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BHI SVC_Done
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LDR R12,=SVC_Table-4
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LDR R12,[R12,R4,LSL #2] @ Load SVC Function Address
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MRS R4,SPSR @ Save SPSR
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PUSH {R4} @ Push R4 so we can use it as a temp
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AND R4, SP, #4 @ Ensure stack is 8-byte aligned
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SUB SP, SP, R4 @ Adjust stack
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PUSH {R4, LR} @ Store stack adjustment and dummy LR
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BLX R12 @ Call SVC Function
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POP {R4, LR} @ Get stack adjustment & discard dummy LR
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ADD SP, SP, R4 @ Unadjust stack
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POP {R4} @ Restore R4
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MSR SPSR_cxsf,R4 @ Restore SPSR
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SVC_Done:
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PUSH {R0-R3,R12,LR}
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PUSH {R4} @ Push R4 so we can use it as a temp
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AND R4, SP, #4 @ Ensure stack is 8-byte aligned
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SUB SP, SP, R4 @ Adjust stack
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PUSH {R4, LR} @ Store stack adjustment and dummy LR
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CPSID i
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BLX rt_tsk_unlock
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POP {R4, LR} @ Get stack adjustment & discard dummy LR
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ADD SP, SP, R4 @ Unadjust stack
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POP {R4} @ Restore R4
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POP {R0-R3,R12,LR}
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POP {R4}
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RFEFD SP! @ Return from exception
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@ }
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@ #pragma pop
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@ #pragma push
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@ #pragma arm
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@ __asm void PendSV_Handler (U32 IRQn) {
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PendSV_Handler:
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.arm
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.extern rt_tsk_lock
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.extern IRQNestLevel
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ADD SP,SP,#8 @ fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
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@ Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher.
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PUSH {R0, R1}
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BLX rt_tsk_lock
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POP {R0, R1}
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LDR R1, =GICInterface_BASE @ __cpp(&GICInterface_BASE)
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LDR R1, [R1, #0]
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STR R0, [R1, #0x10]
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LDR R0, =IRQNestLevel @ Get address of nesting counter
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LDR R1, [R0]
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SUB R1, R1, #1 @ Decrement nesting counter
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STR R1, [R0]
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BLX rt_pop_req @ __cpp(rt_pop_req)
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POP {R1, LR} @ Get stack adjustment & discard dummy LR
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ADD SP, SP, R1 @ Unadjust stack
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||||
LDR R0,[SP,#24]
|
||||
MSR SPSR_cxsf,R0
|
||||
POP {R0-R3,R12} @ Leave SPSR & LR on the stack
|
||||
PUSH {R4}
|
||||
B Sys_Switch
|
||||
@ }
|
||||
@ #pragma pop
|
||||
|
||||
@ #pragma push
|
||||
@ #pragma arm
|
||||
@ __asm void OS_Tick_Handler (U32 IRQn) {
|
||||
OS_Tick_Handler:
|
||||
.arm
|
||||
|
||||
ADD SP,SP,#8 @ fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment)
|
||||
|
||||
PUSH {R0, R1}
|
||||
BLX rt_tsk_lock
|
||||
POP {R0, R1}
|
||||
LDR R1, =GICInterface_BASE @ __cpp(&GICInterface_BASE)
|
||||
LDR R1, [R1, #0]
|
||||
STR R0, [R1, #0x10]
|
||||
|
||||
LDR R0, =IRQNestLevel @ Get address of nesting counter
|
||||
LDR R1, [R0]
|
||||
SUB R1, R1, #1 @ Decrement nesting counter
|
||||
STR R1, [R0]
|
||||
|
||||
BLX os_tick_irqack @ __cpp(os_tick_irqack)
|
||||
BLX rt_systick @ __cpp(rt_systick)
|
||||
|
||||
POP {R1, LR} @ Get stack adjustment & discard dummy LR
|
||||
ADD SP, SP, R1 @ Unadjust stack
|
||||
|
||||
LDR R0,[SP,#24]
|
||||
MSR SPSR_cxsf,R0
|
||||
POP {R0-R3,R12} @ Leave SPSR & LR on the stack
|
||||
PUSH {R4}
|
||||
B Sys_Switch
|
||||
@ }
|
||||
@ #pragma pop
|
||||
|
||||
.global __set_PSP
|
||||
@ __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
|
||||
@ {
|
||||
__set_PSP:
|
||||
@ PRESERVE8
|
||||
.arm
|
||||
|
||||
BIC R0, R0, #7 @ensure stack is 8-byte aligned
|
||||
MRS R1, CPSR
|
||||
CPS #MODE_SYS @no effect in USR mode
|
||||
MOV SP, R0
|
||||
MSR CPSR_c, R1 @no effect in USR mode
|
||||
ISB
|
||||
BX LR
|
||||
|
||||
@ }
|
||||
|
||||
.global __set_CPS_USR
|
||||
@ __STATIC_ASM void __set_CPS_USR(void)
|
||||
@ {
|
||||
__set_CPS_USR:
|
||||
.arm
|
||||
|
||||
CPS #MODE_USR
|
||||
BX LR
|
||||
@ }
|
||||
|
||||
.END
|
||||
/*----------------------------------------------------------------------------
|
||||
* end of file
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*----------------------------------------------------------------------------
|
||||
* RL-ARM - RTX
|
||||
*----------------------------------------------------------------------------
|
||||
* Name: SVC_TABLE.S
|
||||
* Purpose: Pre-defined SVC Table for Cortex-M
|
||||
* Rev.: V4.70
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
|
||||
* All rights reserved.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* - Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
.section SVC_TABLE @, CODE, READONLY
|
||||
.align 5
|
||||
|
||||
.global SVC_Count
|
||||
|
||||
.EQU SVC_Cnt, (SVC_End-SVC_Table)/4
|
||||
|
||||
SVC_Count:
|
||||
.word SVC_Cnt
|
||||
|
||||
@ Import user SVC functions here.
|
||||
@ .extern __SVC_1
|
||||
.global SVC_Table
|
||||
SVC_Table:
|
||||
@ Insert user SVC functions here. SVC 0 used by RTL Kernel.
|
||||
@ .word __SVC_1 @ InitMemorySubsystem
|
||||
|
||||
@SVC_End
|
||||
SVC_End:
|
||||
|
||||
.END
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* end of file
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
|
@ -145,11 +145,63 @@ typedef uint32_t __attribute__((vector_size(16))) ret128;
|
|||
|
||||
#define RET_pointer __r0
|
||||
#define RET_int32_t __r0
|
||||
#define RET_uint32_t __r0
|
||||
#define RET_osStatus __r0
|
||||
#define RET_osPriority __r0
|
||||
#define RET_osEvent {(osStatus)__r0, {(uint32_t)__r1}, {(void *)__r2}}
|
||||
#define RET_osCallback {(void *)__r0, (void *)__r1}
|
||||
|
||||
#if defined (__ARM_PCS_VFP)
|
||||
|
||||
#define osEvent_type void
|
||||
#define osEvent_ret_status { __asm ("MOV r0, %0;" \
|
||||
: /* no outputs */ \
|
||||
: "r"(ret.status) \
|
||||
: "r0" \
|
||||
); \
|
||||
}
|
||||
#define osEvent_ret_value { __asm ("MOV r1, %0;" \
|
||||
"MOV r0, %1;" \
|
||||
: /* no outputs */ \
|
||||
: "r"(ret.value.v), \
|
||||
"r"(ret.status) \
|
||||
: "r0", "r1" \
|
||||
); \
|
||||
}
|
||||
#define osEvent_ret_msg { __asm ("MOV r2, %0;" \
|
||||
"MOV r1, %1;" \
|
||||
"MOV r0, %2;" \
|
||||
: /* no outputs */ \
|
||||
: "r"(ret.def.message_id), \
|
||||
"r"(ret.value.v), \
|
||||
"r"(ret.status) \
|
||||
: "r0", "r1" , "r2" \
|
||||
); \
|
||||
}
|
||||
|
||||
#define osEvent_ret_mail { __asm ("MOV r2, %0;" \
|
||||
"MOV r1, %1;" \
|
||||
"MOV r0, %2;" \
|
||||
: /* no outputs */ \
|
||||
: "r"(ret.def.mail_id), \
|
||||
"r"(ret.value.v), \
|
||||
"r"(ret.status) \
|
||||
: "r0", "r1" , "r2" \
|
||||
); \
|
||||
}
|
||||
|
||||
#define osCallback_type void
|
||||
#define osCallback_ret { __asm ("MOV r1, %0;" \
|
||||
"MOV r0, %1;" \
|
||||
: /* no outputs */ \
|
||||
: "r"(ret.arg), \
|
||||
"r"(ret.fp) \
|
||||
: "r0", "r1" \
|
||||
); \
|
||||
}
|
||||
|
||||
#else /* defined (__ARM_PCS_VFP) */
|
||||
|
||||
#define osEvent_type ret128
|
||||
#define osEvent_ret_status (ret128){ret.status}
|
||||
#define osEvent_ret_value (ret128){ret.status, ret.value.v}
|
||||
|
|
@ -159,6 +211,8 @@ typedef uint32_t __attribute__((vector_size(16))) ret128;
|
|||
#define osCallback_type ret64
|
||||
#define osCallback_ret (ret64) {(uint32_t)ret.fp, (uint32_t)ret.arg}
|
||||
|
||||
#endif /* defined (__ARM_PCS_VFP) */
|
||||
|
||||
#define SVC_ArgN(n) \
|
||||
register int __r##n __asm("r"#n);
|
||||
|
||||
|
|
@ -808,14 +862,24 @@ os_InRegs osEvent_type svcWait (uint32_t millisec) {
|
|||
|
||||
if (millisec == 0) {
|
||||
ret.status = osOK;
|
||||
#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
|
||||
osEvent_ret_status;
|
||||
return;
|
||||
#else
|
||||
return osEvent_ret_status;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* To Do: osEventSignal, osEventMessage, osEventMail */
|
||||
rt_dly_wait(rt_ms2tick(millisec));
|
||||
ret.status = osEventTimeout;
|
||||
|
||||
#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
|
||||
osEvent_ret_status;
|
||||
return;
|
||||
#else
|
||||
return osEvent_ret_status;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -1046,13 +1110,23 @@ os_InRegs osCallback_type svcTimerCall (osTimerId timer_id) {
|
|||
if (pt == NULL) {
|
||||
ret.fp = NULL;
|
||||
ret.arg = NULL;
|
||||
#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
|
||||
osCallback_ret;
|
||||
return;
|
||||
#else
|
||||
return osCallback_ret;
|
||||
#endif
|
||||
}
|
||||
|
||||
ret.fp = (void *)pt->timer->ptimer;
|
||||
ret.arg = pt->arg;
|
||||
|
||||
#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
|
||||
osCallback_ret;
|
||||
return;
|
||||
#else
|
||||
return osCallback_ret;
|
||||
#endif
|
||||
}
|
||||
|
||||
static __INLINE osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
|
||||
|
|
@ -1195,7 +1269,12 @@ os_InRegs osEvent_type svcSignalWait (int32_t signals, uint32_t millisec) {
|
|||
|
||||
if (signals & (0xFFFFFFFF << osFeature_Signals)) {
|
||||
ret.status = osErrorValue;
|
||||
#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
|
||||
osEvent_ret_status;
|
||||
return;
|
||||
#else
|
||||
return osEvent_ret_status;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (signals != 0) { // Wait for all specified signals
|
||||
|
|
@ -1212,7 +1291,12 @@ os_InRegs osEvent_type svcSignalWait (int32_t signals, uint32_t millisec) {
|
|||
ret.value.signals = 0;
|
||||
}
|
||||
|
||||
#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
|
||||
osEvent_ret_value;
|
||||
return;
|
||||
#else
|
||||
return osEvent_ret_value;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1694,24 +1778,44 @@ os_InRegs osEvent_type svcMessageGet (osMessageQId queue_id, uint32_t millisec)
|
|||
|
||||
if (queue_id == NULL) {
|
||||
ret.status = osErrorParameter;
|
||||
#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
|
||||
osEvent_ret_status;
|
||||
return;
|
||||
#else
|
||||
return osEvent_ret_status;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (((P_MCB)queue_id)->cb_type != MCB) {
|
||||
ret.status = osErrorParameter;
|
||||
#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
|
||||
osEvent_ret_status;
|
||||
return;
|
||||
#else
|
||||
return osEvent_ret_status;
|
||||
#endif
|
||||
}
|
||||
|
||||
res = rt_mbx_wait(queue_id, &ret.value.p, rt_ms2tick(millisec));
|
||||
|
||||
if (res == OS_R_TMO) {
|
||||
ret.status = millisec ? osEventTimeout : osOK;
|
||||
#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
|
||||
osEvent_ret_value;
|
||||
return;
|
||||
#else
|
||||
return osEvent_ret_value;
|
||||
#endif
|
||||
}
|
||||
|
||||
ret.status = osEventMessage;
|
||||
|
||||
#if defined (__GNUC__) && defined (__ARM_PCS_VFP)
|
||||
osEvent_ret_value;
|
||||
return;
|
||||
#else
|
||||
return osEvent_ret_value;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@
|
|||
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
|
||||
#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !NO_EXCLUSIVE_ACCESS)
|
||||
#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !defined(NO_EXCLUSIVE_ACCESS))
|
||||
#define __USE_EXCLUSIVE_ACCESS
|
||||
#else
|
||||
#undef __USE_EXCLUSIVE_ACCESS
|
||||
|
|
@ -62,7 +62,16 @@
|
|||
|
||||
#elif defined (__GNUC__) /* GNU Compiler */
|
||||
|
||||
#error GNU Compiler support not implemented for Cortex-A
|
||||
#undef __USE_EXCLUSIVE_ACCESS
|
||||
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#define __TARGET_FPU_VFP 1
|
||||
#else
|
||||
#define __TARGET_FPU_VFP 0
|
||||
#endif
|
||||
|
||||
#define __inline inline
|
||||
#define __weak __attribute__((weak))
|
||||
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
|
||||
|
|
@ -94,7 +103,6 @@ extern const U32 GICInterface_BASE;
|
|||
priority = GICI_ICCPMR; \
|
||||
GICI_ICCPMR = 0xff; \
|
||||
GICI_ICCPMR = GICI_ICCPMR - 1; \
|
||||
while(GICI_ICCPMR > priority);\
|
||||
__DSB();\
|
||||
if(!irq_dis) __enable_irq(); \
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue