From c4220ece9b34a601c30c90dba9e1b26186a85cd6 Mon Sep 17 00:00:00 2001 From: Dave Wu Date: Thu, 12 Oct 2017 12:46:54 +1100 Subject: [PATCH] Added default delay and sample times for the ADC during initialization. --- .../TARGET_ADUCM4050/api/analogin_api.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c index 06413a81d6..baa96a694e 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/analogin_api.c @@ -94,6 +94,22 @@ void analogin_init(analogin_t *obj, PinName pin) MBED_ASSERT(channel != 0xFFFFFFFF); obj->UserBuffer.nChannels = channel; + /* Set ACLK to CCLK/16 */ + adi_pwr_SetClockDivider(ADI_CLOCK_ACLK,16); + + /* Set default values for conversion and delay cycles. This sets up a sampling rate of + 16kHz. The sampling frequency is worked out from the following: + + if delay time > 0: + Fs = ACLK / [((14 + sampling time) * oversample factor) + (delay time + 2)] + if delay time = 0: + Fs = ACLK / ((14 + sampling time) * oversample factor) + + The sampling (or acquisition) and delay times are in number of ACLK clock cycles. + */ + obj->DelayCycles = 0; + obj->SampleCycles = 88; + /* Open the ADC device */ adi_adc_Open(ADC_DEV_NUM, DeviceMemory, sizeof(DeviceMemory), &hDevice); obj->hDevice = hDevice;