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Update psoc6hal to 1.5.0.20805

pull/14787/head
Dustin Crossman 2021-05-25 15:02:56 -07:00
parent 7a7f206344
commit c40bc8b279
152 changed files with 17736 additions and 4888 deletions
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0
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/LICENSE Normal file → Executable file
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2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h Normal file → Executable file
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@ -21,7 +21,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

61
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -61,19 +61,19 @@
* The following snippet initializes an ADC and one channel.
* One ADC conversion result is returned corresponding to the input at the specified
* pin.
* \snippet adc.c snippet_cyhal_adc_simple_init
* \snippet hal_adc.c snippet_cyhal_adc_simple_init
*
* \subsection subsection_adc_snippet_2 Snippet 2: Multi-channel ADC initialization and reading conversion result
* The following snippet initializes an ADC with one single-ended channel and one differential channel
* \snippet adc.c snippet_cyhal_adc_multi_init
* \snippet hal_adc.c snippet_cyhal_adc_multi_init
*
* \subsection subsection_adc_snippet_3 Snippet 3: Asynchronously read multiple channels
* The following snippet illustrates how to asynchronously read multiple scans of multiple channels.
* \snippet adc.c snippet_cyhal_adc_async_read
* \snippet hal_adc.c snippet_cyhal_adc_async_read
*
* \subsection subsection_adc_snippet_4 Snippet 4: Continuous scanning
* This snippet shows how to run the ADC in continuous mode and process results as each scan completes.
* \snippet adc.c snippet_cyhal_adc_continuous_read
* \snippet hal_adc.c snippet_cyhal_adc_continuous_read
*/
#pragma once
@ -139,6 +139,20 @@ typedef enum
CYHAL_ADC_ASYNC_READ_COMPLETE = 2u, //!< An asynchronous read operation has completed.
} cyhal_adc_event_t;
/** Selections for ADC input signals */
typedef enum
{
CYHAL_ADC_INPUT_START_SCAN, // !< Start a scan when a signal is received
}
cyhal_adc_input_t;
/** Selections for ADC output signals */
typedef enum
{
CYHAL_ADC_OUTPUT_SCAN_COMPLETE, // !< An output signal should be triggered when a scan is complete
}
cyhal_adc_output_t;
/** Perform standard averaging. Divide the accumulated value by the number of samples.
* @note This is not supported in combination with @ref CYHAL_ADC_AVG_MODE_ACCUMULATE */
#define CYHAL_ADC_AVG_MODE_AVERAGE (1u << 0)
@ -494,6 +508,43 @@ void cyhal_adc_register_callback(cyhal_adc_t *obj, cyhal_adc_event_callback_t ca
*/
void cyhal_adc_enable_event(cyhal_adc_t *obj, cyhal_adc_event_t event, uint8_t intr_priority, bool enable);
/** Connects a source signal and enables the specified input
*
* @param[in] obj The ADC object
* @param[in] source Source signal obtained from another driver's cyhal_<PERIPH>_enable_output
* @param[in] input Which input signal to connect to
* @return The status of the connection
*/
cy_rslt_t cyhal_adc_connect_digital(cyhal_adc_t *obj, cyhal_source_t source, cyhal_adc_input_t input);
/** Enables the specified output signal
*
* @param[in] obj The ADC object
* @param[in] output Which output signal to enable
* @param[out] source Pointer to user-allocated source signal object
* which will be initialized by enable_output. \p source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
*/
cy_rslt_t cyhal_adc_enable_output(cyhal_adc_t *obj, cyhal_adc_output_t output, cyhal_source_t *source);
/** Disconnect a source signal and disable ADC input
*
* @param[in] obj The ADC object
* @param[in] source Source signal from cyhal_<PERIPH>_enable_output to disable
* @param[in] input Which input signal to disconnect
* @return The status of the disconnect
*/
cy_rslt_t cyhal_adc_disconnect_digital(cyhal_adc_t *obj, cyhal_source_t source, cyhal_adc_input_t input);
/** Disables specified output signal from ADC.
*
* @param[in] obj The ADC object
* @param[in] output Which output signal to disable
* @return The status of the disablement
*/
cy_rslt_t cyhal_adc_disable_output(cyhal_adc_t *obj, cyhal_adc_output_t output);
#if defined(__cplusplus)
}
#endif

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc_impl.h Normal file → Executable file
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@ -2,11 +2,11 @@
* File Name: cyhal_clock_impl.h
*
* Description:
* PSoC 6 specific implementation for clocks API.
* Device specific implementation for clocks API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -32,14 +32,19 @@ extern "C"
#endif
/**
* \ingroup group_hal_impl_impl_adc
* \ingroup group_hal_impl_adc
* \{
* \section group_hal_impl_adc_interconnect Interconnect
* In PSoC each ADC has a single input trigger which, when activated, will
* initiate an ADC scan. Each ADC also has an output trigger which will be
* activated when a scan is completed.
*/
/** Convert all samples to be averaged back to back, before proceeding to the next channel.
* This is the default behavior. */
#define CYHAL_ADC_AVG_MODE_SEQUENTIAL (1u << (CYHAL_ADC_AVG_MODE_MAX_SHIFT + 1u))
#if defined(CY_IP_MXS40PASS_SAR_INSTANCES)
/** Convert one sample to be averaged per scan, interleaved with the rest of the channels.
* This maintains a consistent spacing of samples regardless of whether samples are averaged
* or not. However, it also means that a new value will only be provided once every n scans,
@ -51,6 +56,7 @@ extern "C"
* the working register that is used to accumulate intermediate results.
*/
#define CYHAL_ADC_AVG_MODE_INTERLEAVED (1u << (CYHAL_ADC_AVG_MODE_MAX_SHIFT + 2u))
#endif
/** \} group_hal_impl_adc */

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_analog_common.h Normal file → Executable file
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@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

10
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_clock.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -96,19 +96,19 @@
* \subsection subsection_clock_snippet_1 Snippet 1: Simple clock read only access
* The following snippet shows how get details about a clock if there is no need to adjust any of its
* settings (e.g. read only access). This does not require initializing a clock object.
* \snippet clock.c snippet_cyhal_clock_simple_access
* \snippet hal_clock.c snippet_cyhal_clock_simple_access
*
* \subsection subsection_clock_snippet_2 Snippet 2: Simple clock reservation and configuration
* The following snippet initializes a clock object, updates its frequency then enables it.
* \snippet clock.c snippet_cyhal_clock_simple_init
* \snippet hal_clock.c snippet_cyhal_clock_simple_init
*
* \subsection subsection_clock_snippet_3 Snippet 3: Clock allocation and reuse
* The following snippet shows how a clock can be allocated and reused for multiple peripheral instances.
* \snippet clock.c snippet_cyhal_clock_simple_allocate
* \snippet hal_clock.c snippet_cyhal_clock_simple_allocate
*
* \subsection subsection_clock_snippet_4 Snippet 4: Change clock source
* The following snippet shows how a to change the source of a clock.
* \snippet clock.c snippet_cyhal_clock_change_source
* \snippet hal_clock.c snippet_cyhal_clock_change_source
*
* \subsection subsection_clock_snippet_5 Snippet 5: System initialization
* \note This example is device specific. See \ref subsection_clock_snippet_5_impl for specific implementation.

6
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_clock_impl.h Normal file → Executable file
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@ -2,11 +2,11 @@
* File Name: cyhal_clock_impl.h
*
* Description:
* PSoC 6 specific implementation for clocks API.
* CAT1 specific implementation for clocks API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -49,7 +49,7 @@ extern "C"
* \subsection subsection_clock_snippet_5_impl Snippet: System initialization
* The following snippet shows the clock driver can be used to initialize all clocks in the system.
* \note This example is device specific.
* \snippet clock.c snippet_cyhal_clock_system_init_p6
* \snippet hal_clock.c snippet_cyhal_clock_system_init_p6
*/
/** \cond INTERNAL */

26
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_comp.h Normal file → Executable file
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@ -8,7 +8,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -31,8 +31,8 @@
* High level interface for interacting with an analog Comparator.
*
* \section cyhal_comp_features Features
* The analog comparator measures one input voltage from the non-inverting pin against
* a second voltage provided on the inverting pin. The result of this comparison can
* The analog comparator measures one input voltage from the non-inverting pin against
* a second voltage provided on the inverting pin. The result of this comparison can
* be used in three ways:
* - Output to pin
* - Read state via firmware (see @ref cyhal_comp_read)
@ -42,7 +42,7 @@
*
* \section cyhal_comp_quickstart Quickstart
* Call \ref cyhal_comp_init to initialize a comparator instance by providing the comparator
* object (**obj**), non-inverting input pin (**vin_p**), inverting input pin (**vin_m**), optional
* object (**obj**), non-inverting input pin (**vin_p**), inverting input pin (**vin_m**), optional
* output pin (**output**), and configuration (**cfg**).
*
* Use \ref cyhal_comp_read to read the comparator state from firmware.
@ -54,20 +54,20 @@
* \note Error checking is omitted for clarity
* \section subsection_comp_snippet_1 Snippet 1: Comparator initialization
* The following snippet initializes the comparator and powers it on
* \snippet comp.c snippet_cyhal_comp_init
* \snippet hal_comp.c snippet_cyhal_comp_init
*
* \section subsection_comp_snippet_2 Snippet 2: Comparator read value
* The following snippet reads the current comparator value into a variable
* \snippet comp.c snippet_cyhal_comp_read
* \snippet hal_comp.c snippet_cyhal_comp_read
*
* \section subsection_comp_snippet_3 Snippet 3: Comparator event registration
* The following snippet registers a callback that will be called on either a rising or falling
* edge of the comparator output.
* \snippet comp.c snippet_cyhal_comp_event
* \snippet hal_comp.c snippet_cyhal_comp_event
*
* \section subsection_comp_snippet_4 Snippet 4: Comparator powering-off and on
* The following snippet demonstrates temporarily powering-off the comparator without freeing it.
* \snippet comp.c snippet_cyhal_comp_start_stop
* \snippet hal_comp.c snippet_cyhal_comp_start_stop
*
*/
@ -116,9 +116,9 @@ typedef struct
bool hysteresis;
} cyhal_comp_config_t;
/**
* Handler for Comparator events
*
/**
* Handler for Comparator events
*
* \note Not all hardware is capable of differentiating which type of edge triggered an
* event when both rising and falling edges are enabled. If the edge cannot be determined,
* the `event` argument will be `CYHAL_COMP_RISING_EDGE | CYHAL_COMP_FALLING_EDGE`
@ -145,7 +145,7 @@ cy_rslt_t cyhal_comp_init(cyhal_comp_t *obj, cyhal_gpio_t vin_p, cyhal_gpio_t vi
void cyhal_comp_free(cyhal_comp_t *obj);
/** Changes the current operating power level of the comparator.
*
*
* If the power level is set to @ref CYHAL_POWER_LEVEL_OFF, the comparator will be powered-off
* but it will retain its configuration, so it is not necessary to reconfigure it when changing
* the power level from @ref CYHAL_POWER_LEVEL_OFF to any other value.
@ -174,7 +174,7 @@ cy_rslt_t cyhal_comp_configure(cyhal_comp_t *obj, cyhal_comp_config_t *cfg);
/** Reads the Comparator state.
*
* @param[in] obj Comparator object
* @return The Comparator state. True if the non-inverting pin voltage is greater than the
* @return The Comparator state. True if the non-inverting pin voltage is greater than the
* inverting pin voltage, false otherwise.
*/
bool cyhal_comp_read(cyhal_comp_t *obj);

6
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_comp_ctb.h Normal file → Executable file
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@ -5,7 +5,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -56,7 +56,7 @@ cy_rslt_t _cyhal_comp_ctb_init(cyhal_comp_t *obj, cyhal_gpio_t vin_p, cyhal_gpio
void _cyhal_comp_ctb_free(cyhal_comp_t *obj);
/** Changes the current operating power level of the comparator for a CTB-based comparator.
*
*
* If the power level is set to @ref CYHAL_POWER_LEVEL_OFF, the comparator will be powered-off
* but it will retain its configuration, so it is not necessary to reconfigure it when changing
* the power level from @ref CYHAL_POWER_LEVEL_OFF to any other value.
@ -85,7 +85,7 @@ cy_rslt_t _cyhal_comp_ctb_configure(cyhal_comp_t *obj, cyhal_comp_config_t *cfg)
/** Reads the Comparator state for a CTB-based comparator.
*
* @param[in] obj Comparator object
* @return The Comparator state. True if the non-inverting pin voltage is greater than the
* @return The Comparator state. True if the non-inverting pin voltage is greater than the
* inverting pin voltage, false otherwise.
*/
bool _cyhal_comp_ctb_read(cyhal_comp_t *obj);

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_comp_lp.h Normal file → Executable file
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@ -5,7 +5,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

35
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -37,7 +37,27 @@
* * One or more calls to \ref cyhal_crc_compute, to provide chunks of data
* * A single call to \ref cyhal_crc_finish, to finalize the computation and retrieve the result
*
* Many of the algorithm parameters can be customized.
* The table below provides CRC parameters for some common CRC algorithms.
* \note The Expected CRC column shows the computed CRC when the value "123456789" is passed to \ref cyhal_crc_compute.
*
* | CRC algorithm Name | Len | Polynomial |Initial seed| Data REV | Data XOR | Rem REV | Remainder XOR | Expected CRC |
* | ------------------- | --- | ---------- |----------- | -------- | -------- | ------- | ------------- | ------------ |
* | CRC-6 / CDMA2000-A | 6 | 0x27 | 0x3F | false | 0 | false | 0x00 | 0x0D |
* | CRC-6 / CDMA2000-B | 6 | 0x07 | 0x3F | false | 0 | false | 0x00 | 0x3B |
* | CRC-6 / DARC | 6 | 0x19 | 0x00 | true | 0 | true | 0x00 | 0x26 |
* | CRC-6 / ITU | 6 | 0x03 | 0x00 | true | 0 | true | 0x00 | 0x06 |
* | CRC-8 / ITU | 8 | 0x07 | 0x00 | false | 0 | false | 0x55 | 0xA1 |
* | CRC-8 / MAXIM | 8 | 0x31 | 0x00 | true | 0 | true | 0x00 | 0xA1 |
* | CRC-8 / ROHC | 8 | 0x07 | 0xFF | true | 0 | true | 0x00 | 0xD0 |
* | CRC-8 / WCDMA | 8 | 0x9B | 0x00 | true | 0 | true | 0x00 | 0x25 |
* | CRC-16 / CCITT-0 | 16 | 0x1021 | 0xFFFF | false | 0 | false | 0x0000 | 0x29B1 |
* | CRC-16 / CDMA2000 | 16 | 0xC867 | 0xFFFF | false | 0 | false | 0x0000 | 0x4C06 |
* | CRC-32 | 32 | 0x04C11DB7 | 0xFFFFFFFF | true | 0 | true | 0xFFFFFFFF | 0xCBF43926 |
* | CRC-32 / BZIP2 | 32 | 0x04C11DB7 | 0xFFFFFFFF | false | 0 | false | 0xFFFFFFFF | 0xFC891918 |
*
* \note Algorithms that have less than 8 bits, like CRC-6, populate the lower bits and leave the high order bits 0.
*
* \note Many of the algorithm parameters can be customized.
*
* See \ref crc_algorithm_t and \ref subsection_crc_snippet_1 for more details.
*
@ -48,7 +68,7 @@
* \subsection subsection_crc_snippet_1 Snippet1: CRC Generation
* The following snippet initializes a CRC generator and computes the CRC for a sample message.
*
* \snippet crc.c snippet_cyhal_crc_simple_init
* \snippet hal_crc.c snippet_cyhal_crc_simple_init
*/
#pragma once
@ -131,8 +151,13 @@ cy_rslt_t cyhal_crc_start(cyhal_crc_t *obj, const crc_algorithm_t *algorithm);
*/
cy_rslt_t cyhal_crc_compute(const cyhal_crc_t *obj, const uint8_t *data, size_t length);
/** Finalizes the CRC computation and returns the CRC for the complete set of data passed through a single call or multiple calls to \ref cyhal_crc_compute.
* \note The computed CRC pointer provided must be 4 byte aligned. Refer \ref subsection_crc_snippet_1 for more details.
/** Finalizes the CRC computation and returns the CRC for the complete set of data passed through a
* single call or multiple calls to \ref cyhal_crc_compute.
* \note The computed CRC pointer provided must be 4 byte aligned. Refer to
* \ref subsection_crc_snippet_1 for more details.
*
* \note If the length of the CRC is less than a full word, the result will be in the lower bits
* allowing the result to be downcast if desired.
*
* @param[in] obj The CRC generator object
* @param[out] crc The computed CRC

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h Normal file → Executable file
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@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

20
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h Normal file → Executable file
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@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,35 +36,35 @@
extern "C" {
#endif
/** Block count for CRYPTO blocks */
/* Block count for CRYPTO blocks */
#define CYHAL_CRYPTO_INST_COUNT CY_IP_MXCRYPTO_INSTANCES
typedef enum
{
/** CRC hardware acceleration */
/* CRC hardware acceleration */
CYHAL_CRYPTO_CRC,
/** TRNG hardware acceleration */
/* TRNG hardware acceleration */
CYHAL_CRYPTO_TRNG,
/** VU hardware acceleration */
/* VU hardware acceleration */
CYHAL_CRYPTO_VU,
/** Common features of the Crypto block */
/* Common features of the Crypto block */
CYHAL_CRYPTO_COMMON,
} cyhal_crypto_feature_t;
/** Reserve the Crypto block and enable it.
/* Reserve the Crypto block and enable it.
*
* @param[out] base Base address to the Crypto block.
* @param[out] obj Resource inst for the function (eg. CRC, TRNG) in the Crypto block.
* @param[out] resource Resource inst for the function (eg. CRC, TRNG) in the Crypto block.
* @param[in] feature feature to reserve on the Crypto block (eg. TRNG, CRC, etc.).
* @return The status of the reserve request.
*/
cy_rslt_t cyhal_crypto_reserve(CRYPTO_Type** base, cyhal_resource_inst_t *resource, cyhal_crypto_feature_t feature);
/** Free the Crypto block and disable it.
/* Free the Crypto block and disable it.
*
* @param[in] base Base address to the Crypto block.
* @param[in] obj Resource inst for the funtion in Crypto block.
* @param[in] resource Resource inst for the function in Crypto block.
* @param[in] feature Feature to free on the Crypto block (eg. TRNG, CRC, etc.).
*/
void cyhal_crypto_free(CRYPTO_Type* base, cyhal_resource_inst_t *resource, cyhal_crypto_feature_t feature);

4
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -56,7 +56,7 @@
* \subsection subsection_dac_use_case_1 Use case 1: Simple DAC initialization
* The following snippet initializes a DAC resource and assigns the output to the specified <b>pin</b> using \ref cyhal_dac_init.
* \ref cyhal_dac_write is used to set the DAC output value. \ref cyhal_dac_read is used to read back DAC register.
* \snippet dac.c snippet_cyhal_dac_simple_init
* \snippet hal_dac.c snippet_cyhal_dac_simple_init
*/
#pragma once

38
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_deprecated.h Normal file → Executable file
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@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -40,7 +40,7 @@ extern "C" {
* \addtogroup group_hal_impl_deprecated Deprecated
* \ingroup group_hal_impl
* \{
* The following PSoC 6 specific items have been deprecated and replaced by more generic items. Each item
* The following CAT1 specific items have been deprecated and replaced by more generic items. Each item
* will continue to work for now, but will be removed in a future release. All deprecated items reference
* the item that replaces it.
*/
@ -67,6 +67,40 @@ extern "C" {
*/
#define cyhal_system_deepsleep() Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)
#define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/
#define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/
#define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/
#define CYHAL_SDIO_RET_CMD_IDX_ERROR (0x04) /**< The index for the command didn't match*/
#define CYHAL_SDIO_RET_CMD_EB_ERROR (0x08) /**< There was an end bit error on the command*/
#define CYHAL_SDIO_RET_DAT_CRC_ERROR (0x10) /**< There was a data CRC Error*/
#define CYHAL_SDIO_RET_CMD_TIMEOUT (0x20) /**< The command didn't finish before the timeout period was over*/
#define CYHAL_SDIO_RET_DAT_TIMEOUT (0x40) /**< The data didn't finish before the timeout period was over*/
#define CYHAL_SDIO_RET_RESP_FLAG_ERROR (0x80) /**< There was an error in the resposne flag for command 53*/
#define CYHAL_SDIO_CLOCK_ERROR (0x100) /**< Failed to initial clock for SDIO */
#define CYHAL_SDIO_BAD_ARGUMENT (0x200) /**< Bad argument passed for SDIO */
#define CYHAL_SDIO_SEMA_NOT_INITED (0x400) /**< Semaphore is not initiated */
#define CYHAL_SDIO_FUNC_NOT_SUPPORTED (0x800) /**< Function is not supported */
#define CYHAL_SDIO_CANCELED (0x1000) /**< Operation canceled */
#define CYHAL_SDIO_PM_PENDING_ERROR (0x2000) /**< Transfer cannot be initiated after power mode transition allowed.*/
/** Semaphore not initiated error define */
#define CYHAL_SDIO_RSLT_ERR_SEMA_NOT_INITED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_SEMA_NOT_INITED))
/** Error define based on SDIO lower function return value */
#define CYHAL_SDIO_RSLT_ERR_FUNC_RET(retVal) \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, ((uint16_t)retVal)))
/** Clock initialization error define */
#define CYHAL_SDIO_RSLT_ERR_CLOCK \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CLOCK_ERROR))
/** SDHC CARD INTERRUPT event (The synchronized value of the DAT[1] interrupt input for SD mode) */
#define CYHAL_SDHC_CARD_INTERRUPT ((cyhal_sdhc_event_t)0x00100)
/** SDHC Asynchronous read operation is complete event (CYHAL_SDHC_XFER_COMPLETE is used instead) */
#define CYHAL_SDHC_ASYNC_READ_COMPLETE ((cyhal_sdhc_event_t)0x10000)
/** SDHC Asynchronous write operation is complete event (CYHAL_SDHC_XFER_COMPLETE is used instead) */
#define CYHAL_SDHC_ASYNC_WRITE_COMPLETE ((cyhal_sdhc_event_t)0x20000)
/** Enum for clock type to configure. HFCLKs are configured using different APIs and does not using this enum.
* \warning This type is deprecated. Use \ref cyhal_clock_block_t instead.
*/

112
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -33,8 +33,8 @@
* The DMA driver allows for initializing and configuring a DMA channel in
* order to trigger data transfers to and from memory and peripherals. The
* transfers occur independently of the CPU and are triggered in software.
* Multiple channels are available with user-selectable priority and transfer
* characteristics.
* Multiple channels can be active at the same time each with their own
* user-selectable priority and transfer characteristics.
*
* \section section_dma_features Features
* * CPU independent memory access
@ -58,13 +58,13 @@
* \ref cyhal_dma_configure and then the transfer is started with \ref cyhal_dma_start_transfer.<br>
* If the DMA channel is not needed anymore, it can be released by calling \ref cyhal_dma_free
*
* \snippet dma.c snippet_cyhal_dma_simple_init
* \snippet hal_dma.c snippet_cyhal_dma_simple_init
*
*
* \subsection subsection_dma_snippet_2 Snippet 2: Configuring the DMA channel based on memory requirements
* \ref cyhal_dma_configure can be used after DMA initialization to handle a variety of memory layouts.
*
* \snippet dma.c snippet_cyhal_dma_configure
* \snippet hal_dma.c snippet_cyhal_dma_configure
*
*
* \subsection subsection_dma_snippet_3 Snippet 3: Interrupts and retriggering DMA transfers
@ -74,7 +74,7 @@
* in progress. It then uses \ref cyhal_dma_enable_event() to enable the transfer complete event to
* trigger the callback function registered by \ref cyhal_dma_register_callback().
*
* \snippet dma.c snippet_cyhal_dma_events
* \snippet hal_dma.c snippet_cyhal_dma_events
*/
#pragma once
@ -146,10 +146,27 @@ typedef enum
CYHAL_DMA_DESCR_BUS_ERROR = 1 << 7, //!< Indicates that there has been a descriptor bus error
} cyhal_dma_event_t;
/** Specifies the transfer type to trigger when an input signal is received.
* */
typedef enum
{
CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT, //!< Transfer a single element when an input signal is received
CYHAL_DMA_INPUT_TRIGGER_SINGLE_BURST, //!< Transfer a single burst when an input signal is received
CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS, //!< Transfer all elements when an input signal is received
} cyhal_dma_input_t;
/** Specifies the transfer completion event that triggers a signal output. */
typedef enum
{
CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT, //!< Trigger an output when a single element is transferred
CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_BURST, //!< Trigger an output when a single burst is transferred
CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS, //!< Trigger an output when all elements are transferred
} cyhal_dma_output_t;
/** If burst_size is used, selects whether a single trigger of the channel
* transfers a single burst of burst_size or a full transfer of size length
* (that is, every burst is triggered). This will also select when a trigger
* complete event will occur; after each burst or after the full transfer */
* (that is, every burst is triggered). This will also set the initial transfer
* type that will trigger an output signal on completion.*/
typedef enum
{
CYHAL_DMA_TRANSFER_BURST, //!< A single burst is triggered and a transfer completion event will occur after the burst
@ -174,6 +191,45 @@ typedef struct
/** Event handler for DMA interrupts */
typedef void (*cyhal_dma_event_callback_t)(void *callback_arg, cyhal_dma_event_t event);
/** DMA input connection information to setup while initializing the driver. */
typedef struct
{
cyhal_source_t source; //!< Source of signal to DMA; obtained from another driver's cyhal_<PERIPH>_enable_output
cyhal_dma_input_t input; //!< DMA input signal to be driven
} cyhal_dma_src_t;
/** DMA output connection information to setup while initializing the driver. */
typedef struct
{
cyhal_dma_output_t output; //!< Output signal of DMA
cyhal_dest_t dest; //!< Destination of DMA signal
} cyhal_dma_dest_t;
/** Initialize the DMA peripheral.
*
* If a source signal is provided for \p src, this will connect the provided signal to the DMA
* just as would be done by calling \ref cyhal_dma_connect_digital. Similarly, if a destination
* target is provided for \p dest this will enable the specified output just as would be done
* by calling \ref cyhal_dma_enable_output.
* @param[out] obj Pointer to a DMA object. The caller must allocate the memory
* for this object but the init function will initialize its contents.
* @param[in] src An optional source signal to connect to the DMA
* @param[in] dest An optional destination singal to drive from the DMA
* @param[out] dest_source An optional pointer to user-allocated source signal object which
* will be initialized by enable_output. If \p dest is non-null, this must also be non-null.
* \p dest_source should be passed to (dis)connect_digital functions to (dis)connect the
* associated endpoints.
* @param[in] priority The priority of this DMA operation relative to others. The number of
* priority levels which are supported is hardware dependent. All implementations define a
* #CYHAL_DMA_PRIORITY_DEFAULT constant which is always valid. If supported, implementations will
* also define #CYHAL_DMA_PRIORITY_HIGH, #CYHAL_DMA_PRIORITY_MEDIUM, and #CYHAL_DMA_PRIORITY_LOW.
* The behavior of any other value is implementation defined. See the implementation-specific DMA
* documentation for more details.
* @param[in] direction The direction memory is copied
* @return The status of the init request
*/
cy_rslt_t cyhal_dma_init_adv(cyhal_dma_t *obj, cyhal_dma_src_t *src, cyhal_dma_dest_t *dest, cyhal_source_t *dest_source, uint8_t priority, cyhal_dma_direction_t direction);
/** Initialize the DMA peripheral.
*
* @param[out] obj Pointer to a DMA object. The caller must allocate the memory
@ -182,7 +238,7 @@ typedef void (*cyhal_dma_event_callback_t)(void *callback_arg, cyhal_dma_event_t
* @param[in] direction The direction memory is copied
* @return The status of the init request
*/
cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction);
#define cyhal_dma_init(obj, priority, direction) (cyhal_dma_init_adv(obj, NULL, NULL, NULL, priority, direction))
/** Free the DMA object. Freeing a DMA object while a transfer is in
progress (see @ref cyhal_dma_is_busy) is invalid.
@ -234,6 +290,44 @@ void cyhal_dma_register_callback(cyhal_dma_t *obj, cyhal_dma_event_callback_t ca
*/
void cyhal_dma_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intr_priority, bool enable);
/** Connects a source signal and enables the specified input to the DMA
* channel
*
* @param[in] obj The DMA object
* @param[in] source Source signal obtained from another driver's cyhal_<PERIPH>_enable_output
* @param[in] input Which input to enable
* @return The status of the connection
* */
cy_rslt_t cyhal_dma_connect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input);
/** Enables the specified output signal from a DMA channel that is triggered when a transfer is completed
*
* @param[in] obj The DMA object
* @param[in] output Which event triggers the output
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. \p source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t cyhal_dma_enable_output(cyhal_dma_t *obj, cyhal_dma_output_t output, cyhal_source_t *source);
/** Disconnects a source signal and disables the specified input to the DMA channel
*
* @param[in] obj The DMA object
* @param[in] source Source signal from cyhal_<PERIPH>_enable_output to disable
* @param[in] input Which input to disable
* @return The status of the disconnect
* */
cy_rslt_t cyhal_dma_disconnect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input);
/** Disables the specified output signal from a DMA channel
*
* @param[in] obj The DMA object
* @param[in] output Which output to disable
* @return The status of the disablement
* */
cy_rslt_t cyhal_dma_disable_output(cyhal_dma_t *obj, cyhal_dma_output_t output);
#if defined(__cplusplus)
}
#endif

50
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dmac.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -33,7 +33,7 @@
#pragma once
#ifdef CY_IP_M4CPUSS_DMAC
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
#if defined(__cplusplus)
extern "C" {
@ -42,12 +42,14 @@ extern "C" {
/** Initialize the DMAC peripheral
*
* @param[out] obj The DMA object to initialize
* @param[in] src An optional, input signal to connect to.
* @param[in] dest An optional, output target to drive.
* @param[in] priority The priority of this DMA operation relative to others. Values must be between 0-3 with 0 being the highest priority.
* @return The status of the init request
*/
cy_rslt_t _cyhal_dma_dmac_init(cyhal_dma_t *obj, uint8_t priority);
cy_rslt_t _cyhal_dma_dmac_init(cyhal_dma_t *obj, cyhal_source_t *src, cyhal_dest_t *dest, uint8_t priority);
/** Frees the DMAC specific object
/** Frees the DMAC specific object. This expects that common resources will be freed by caller.
*
* @param[in,out] obj The DMA object
*/
@ -85,10 +87,48 @@ void _cyhal_dma_dmac_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uin
*/
bool _cyhal_dma_dmac_is_busy(cyhal_dma_t *obj);
/** Connects a source signal and enables the specified input to the DMA
* channel
*
* @param[in] obj The DMA object
* @param[in] source Source signal obtained from another driver's cyhal_<PERIPH>_enable_output
* @param[in] input Which input to enable
* @return The status of the connection
* */
cy_rslt_t _cyhal_dma_dmac_connect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input);
/** Enables the specified output signal from a DMA channel that is triggered when a transfer is completed
*
* @param[in] obj The DMA object
* @param[in] output Which event triggers the output
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. \p source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t _cyhal_dma_dmac_enable_output(cyhal_dma_t *obj, cyhal_dma_output_t output, cyhal_source_t *source);
/** Disconnects a source signal and disables the specified input to the DMA channel
*
* @param[in] obj The DMA object
* @param[in] source Source signal from cyhal_<PERIPH>_enable_output to disable
* @param[in] input Which input to disable
* @return The status of the disconnect
* */
cy_rslt_t _cyhal_dma_dmac_disconnect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input);
/** Disables the specified output signal from a DMA channel
*
* @param[in] obj The DMA object
* @param[in] output Which output to disable
* @return The status of the disablement
* */
cy_rslt_t _cyhal_dma_dmac_disable_output(cyhal_dma_t *obj, cyhal_dma_output_t output);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* CY_IP_M4CPUSS_DMAC */
#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC) */
/** \} group_hal_impl_dma_dmac */

46
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dw.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -42,12 +42,14 @@ extern "C" {
/** Initialize the Datawire peripheral.
*
* @param[out] obj The DMA object to initialize
* @param[in] src An optional, input signal to connect to.
* @param[in] dest An optional, output target to drive.
* @param[in] priority The priority of this DMA operation relative to others. Values must be between 0-3 with 0 being the highest priority.
* @return The status of the init request
*/
cy_rslt_t _cyhal_dma_dw_init(cyhal_dma_t *obj, uint8_t priority);
cy_rslt_t _cyhal_dma_dw_init(cyhal_dma_t *obj, cyhal_source_t *src, cyhal_dest_t *dest, uint8_t priority);
/** Frees the Datawire specific DMA object
/** Frees the Datawire specific DMA object. This expects that common resources will be freed by caller.
*
* @param[in,out] obj The DMA object
*/
@ -85,6 +87,44 @@ void _cyhal_dma_dw_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8
*/
bool _cyhal_dma_dw_is_busy(cyhal_dma_t *obj);
/** Connects a source signal and enables the specified input to the DMA
* channel
*
* @param[in] obj The DMA object
* @param[in] source Source signal obtained from another driver's cyhal_<PERIPH>_enable_output
* @param[in] input Which input to enable
* @return The status of the connection
* */
cy_rslt_t _cyhal_dma_dw_connect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input);
/** Enables the specified output signal from a DMA channel that is triggered when a transfer is completed
*
* @param[in] obj The DMA object
* @param[in] output Which event triggers the output
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t _cyhal_dma_dw_enable_output(cyhal_dma_t *obj, cyhal_dma_output_t output, cyhal_source_t *source);
/** Disconnects a source signal and disables the specified input to the DMA channel
*
* @param[in] obj The DMA object
* @param[in] source Source signal from cyhal_<PERIPH>_enable_output to disable
* @param[in] input Which input to disable
* @return The status of the disconnect
* */
cy_rslt_t _cyhal_dma_dw_disconnect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input);
/** Disables the specified output signal from a DMA channel
*
* @param[in] obj The DMA object
* @param[in] output Which output to disable
* @return The status of the disablement
* */
cy_rslt_t _cyhal_dma_dw_disable_output(cyhal_dma_t *obj, cyhal_dma_output_t output);
#if defined(__cplusplus)
}
#endif /* __cplusplus */

30
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_impl.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -24,7 +24,7 @@
#pragma once
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA)
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M0S8CPUSSV3_DMAC)
#if defined(__cplusplus)
extern "C" {
@ -33,20 +33,32 @@ extern "C" {
/** \addtogroup group_hal_impl_dma DMA (Direct Memory Access)
* \ingroup group_hal_impl
* \{
* DW (DataWire) is one of two DMA hardware implementations for PSOC6. DW is
* designed for low latency memory to peripheral or peripheral to memory
* DW (DataWire) is one of two DMA hardware implementations for CAT1 (PSoC 6).
* DW is designed for low latency memory to peripheral or peripheral to memory
* transfers but can also perform memory to memory transfers and peripheral to
* peripheral transfers.
*
* DMAC (Direct Memory Access Controller) is the second of two DMA hardware
* implementations for PSOC6. DMAC is designed with high memory bandwidth for
* large memory to memory transfers but can perform peripheral to memory,
* memory to peripheral, and peripheral to peripheral transfers.
* implementations for CAT1 (PSoC 6). It is also the implementation that is
* found on CAT2 (PMG/PSoC 4) devices. DMAC is designed with high memory
* bandwidth for large memory to memory transfers but can perform peripheral
* to memory, memory to peripheral, and peripheral to peripheral transfers.
*
* Which DMA type is used is dependent on the exact hardware and number of DMA
* channels already in use. This implementation will attempt to use DMAC first
* for memory to memory transfers and Datawire otherwise but either type may be
* used. */
* used.
*
* \section group_hal_impl_dma_interconnect Interconnect
* For both DW and DMAC each channel has a single input and a single output
* trigger available. The input, when triggered, initiates a DMA transfer of
* the configured type (note that this also affects the type transferred by the
* SW triggering). For output, a trigger is generated when a DMA transfer of
* the configured type is completed. For DW and DMAC neither input nor output
* triggers can be disabled completely but the signals do not, of course, have
* to be connected through the interconnect.
*
* */
/** Default DMA channel priority */
#define CYHAL_DMA_PRIORITY_DEFAULT CYHAL_DMA_PRIORITY_LOW
@ -70,4 +82,4 @@ extern "C" {
}
#endif
#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) */
#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M0S8CPUSSV3_DMAC) */

4
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_drivers.h Normal file → Executable file
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@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -27,6 +27,7 @@
#include "cyhal_adc.h"
#include "cyhal_clock.h"
#include "cyhal_comp.h"
#include "cyhal_crc.h"
#include "cyhal_dac.h"
#include "cyhal_dma.h"
@ -42,6 +43,7 @@
#include "cyhal_pdmpcm.h"
#include "cyhal_pwm.h"
#include "cyhal_qspi.h"
#include "cyhal_quaddec.h"
#include "cyhal_rtc.h"
#include "cyhal_sdhc.h"
#include "cyhal_sdio.h"

6
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_ezi2c.h Normal file → Executable file
View File

@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -58,13 +58,13 @@
* The following snippet shows how to initialize and configure an EZI2C and assign the pins to the <b>sda</b> and <b>scl</b> lines.
* The <b>clk</b> need not be provided (NULL), in which case a clock resource is assigned.
*
* \snippet ezi2c.c snippet_cyhal_ezi2c_init
* \snippet hal_ezi2c.c snippet_cyhal_ezi2c_init
*
* \subsection subsection_ezi2c_snippet_2 Snippet 2: Register Callback function
* The following snippet shows how to use the \ref cyhal_ezi2c_register_callback function. The <b>callback</b> parameter
* refers to the handler which will be invoked when an event triggers.
*
* \snippet ezi2c.c snippet_cyhal_ezi2c_handler
* \snippet hal_ezi2c.c snippet_cyhal_ezi2c_handler
*/
#pragma once

11
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -58,7 +58,7 @@
* \subsection subsection_flash_use_case_1 Snippet 1: Discovering flash characteristics
* Following code snippet demonstrates how to discover flash characteristics. Refer \ref
* cyhal_flash_info_t for more information.
* \snippet flash.c snippet_cyhal_flash_get_flash_info
* \snippet hal_flash.c snippet_cyhal_flash_get_flash_info
*
* \subsection subsection_flash_use_case_2 Snippet 2: Blocking Flash Write Operation
* Following code snippet demonstrates blocking flash write.
@ -67,7 +67,7 @@
* It uses blocking flash write operation which blocks the caller until the write is
* completed. It then verifies the flash data by comparing the flash data with the
* written data.
* \snippet flash.c flag_snippet_cyhal_flash_blocking_mode_flashwrite
* \snippet hal_flash.c flag_snippet_cyhal_flash_blocking_mode_flashwrite
* \note It is recommended to declare the flash array as global variable.
*
* \subsection subsection_flash_use_case_3 Snippet 3: Non-blocking Flash Write Operation using polling
@ -77,7 +77,7 @@
* occupies one complete flash row. It uses a polling method to complete the flash
* write operation. It then verifies the flash data by comparing the flash data with
* the written data.
* \snippet flash.c flag_snippet_cyhal_flash_partially_blocking_mode_polling_flashwrite
* \snippet hal_flash.c flag_snippet_cyhal_flash_partially_blocking_mode_polling_flashwrite
* \note It is recommended to declare the flash array as global variable.
*/
@ -105,6 +105,9 @@ extern "C" {
/** Invalid argument */
#define CYHAL_FLASH_RSLT_ERR_ADDRESS \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_FLASH, 0))
/** API is not supported */
#define CYHAL_FLASH_RSLT_ERR_NOT_SUPPORTED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_FLASH, 1))
/** Unable to support due to power state */
/**
* \}

36
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_general_types.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -89,30 +89,11 @@ enum cyhal_rslt_module_chip
CYHAL_RSLT_MODULE_UART = (0x1B << 8), //!< An error occurred in UART module
CYHAL_RSLT_MODULE_USB = (0x1C << 8), //!< An error occurred in USB module
CYHAL_RSLT_MODULE_WDT = (0x1D << 8), //!< An error occurred in WDT module
// Implementation specific section
CYHAL_RSLT_MODULE_IMPL_TCPWM = (0x1E << 8), //!< An error occurred in TCPWM module (TCPWM based drivers are: Timer, PWM, Quadrature Decoder)
CYHAL_RSLT_MODULE_IMPL_SCB = (0x1F << 8), //!< An error occurred in SCB module (SCB based drivers are: I2C, SPI, UART)
};
/**
* Enum to specify all of the digital output signals supported by different hardware peripherals. These can be used
* as inputs to other peripherals if the selected device has internal routing resources.
*/
typedef enum
{
CYHAL_SIGNAL_DMA_COMPLETE, //!< DMA complete signal
CYHAL_SIGNAL_PWM_OUT, //!< PWM output signal
CYHAL_SIGNAL_PWM_OUT_INV, //!< PWM output signal inverted
CYHAL_SIGNAL_PWM_OVERFLOW, //!< PWM overflow signal
CYHAL_SIGNAL_PWM_UNDERFLOW, //!< PWM underflow signal
CYHAL_SIGNAL_PWM_COMPARE, //!< PWM period match signal
CYHAL_SIGNAL_TIMER_OVERFLOW, //!< Timer overflow signal
CYHAL_SIGNAL_TIMER_UNDERFLOW, //!< Timer underflow signal
CYHAL_SIGNAL_TIMER_CAPTURE, //!< Timer capture match signal
CYHAL_SIGNAL_QUADDEC_TC, //!< Quadrature Decoder terminal count signal. High on index event,
//!< or when counter reaches min/max value.
} cyhal_signal_digital_out_t;
/**
* \} group_hal_results
*/
@ -125,6 +106,15 @@ typedef enum {
CYHAL_ASYNC_SW,
} cyhal_async_mode_t;
/** Enum of signal edge types */
typedef enum
{
CYHAL_EDGE_TYPE_RISING_EDGE, //!< Rising edge
CYHAL_EDGE_TYPE_FALLING_EDGE, //!< Falling edge
CYHAL_EDGE_TYPE_BOTH_EDGES, //!< Both edges
CYHAL_EDGE_TYPE_LEVEL, //!< Level
} cyhal_edge_type_t;
/** @brief Selectable power levels.
*
* Power levels are defined relative to others. Higher power levels

65
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -53,13 +53,13 @@
* The following snippet initializes GPIO pin \ref P0_0 as an input with high impedance digital drive mode and initial value = <b>false</b> (low). A value is read
* from the pin and stored to a uint8_t variable (<b>read_val</b>).
* \snippet gpio.c snippet_cyhal_gpio_read
* \snippet hal_gpio.c snippet_cyhal_gpio_read
* \subsection subsection_gpio_snippet_2 Snippet 2: Writing value to a GPIO
* The following snippet initializes GPIO pin \ref P0_0 as an output pin with strong drive mode and initial value = <b>false</b> (low).
* A value = <b>true</b> (high) is written to the output driver.
* \snippet gpio.c snippet_cyhal_gpio_write
* \snippet hal_gpio.c snippet_cyhal_gpio_write
* \subsection subsection_gpio_snippet_3 Snippet 3: Reconfiguring a GPIO
* The following snippet shows how to reconfigure a GPIO pin during run-time using the firmware. The GPIO pin \ref P0_0
@ -67,7 +67,7 @@
* \note \ref cyhal_gpio_configure only changes the <b>direction</b> and the <b>drive_mode</b>
* of the pin. Previously set pin value is retained.
*
* \snippet gpio.c snippet_cyhal_gpio_reconfigure
* \snippet hal_gpio.c snippet_cyhal_gpio_reconfigure
* \subsection subsection_gpio_snippet_4 Snippet 4: Interrupts on GPIO events
* GPIO events can be mapped to an interrupt and assigned to a callback function. The callback function needs to be first registered and
@ -76,7 +76,7 @@
* of a falling edge event to trigger the callback.
* \note If no argument needs to be passed to the callback function then a NULL can be passed during registering. <br>
*
* \snippet gpio.c snippet_cyhal_gpio_interrupt
* \snippet hal_gpio.c snippet_cyhal_gpio_interrupt
*/
#pragma once
@ -85,11 +85,28 @@
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#include "cyhal_interconnect.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/** \addtogroup group_hal_results_gpio GPIO HAL Results
* GPIO specific return codes
* \ingroup group_hal_results
* \{ *//**
*/
/** The specified pin has no supported input signal */
#define CYHAL_GPIO_RSLT_ERR_NO_INPUT_SIGNAL \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_GPIO, 0))
/** The specified pin has no supported output signal */
#define CYHAL_GPIO_RSLT_ERR_NO_OUTPUT_SIGNAL \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_GPIO, 1))
/**
* \}
*/
/*******************************************************************************
* Defines
@ -221,11 +238,47 @@ void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t
*
* @param[in] pin The GPIO object
* @param[in] event The GPIO event
* @param[in] intr_priority The priority for NVIC interrupt events
* @param[in] intr_priority The priority for NVIC interrupt events. Interrupt priorities specific to a pin may not
* be supported on all platforms. Refer to platform implementation specific documentation
* for details.
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable);
/** Connects a source signal and enables an input to a pin that, when triggered, will set the pins output
*
* @param[in] pin GPIO object
* @param[in] source Source signal obtained from another driver's cyhal_<PERIPH>_enable_output
* @param[in] type Whether the incoming signal will act as a edge or level input
* @return The status of the connection
* */
cy_rslt_t cyhal_gpio_connect_digital(cyhal_gpio_t pin, cyhal_source_t source, cyhal_signal_type_t type);
/** Enables an output signal from a pin that is triggered by the pins input
*
* @param[in] pin GPIO object
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. \p source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t cyhal_gpio_enable_output(cyhal_gpio_t pin, cyhal_source_t *source);
/** Disconnects a source signal and disables an input to a pin
*
* @param[in] pin GPIO object
* @param[in] source Source signal from cyhal_<PERIPH>_enable_output to disable
* @return The status of the disconnection
* */
cy_rslt_t cyhal_gpio_disconnect_digital(cyhal_gpio_t pin, cyhal_source_t source);
/** Disables an output signal from a pin
*
* @param[in] pin GPIO object
* @return The status of the output enable
* */
cy_rslt_t cyhal_gpio_disable_output(cyhal_gpio_t pin);
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* not be used in new projects

45
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@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -36,6 +36,49 @@
extern "C" {
#endif /* __cplusplus */
#if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
/** \addtogroup group_hal_impl_gpio GPIO
* \ingroup group_hal_impl
* \{
* \section group_hal_impl_gpio_interrupt Interrupt Priorities
* In CAT1 (PSoC 6), each GPIO port has a single IRQ line. Hence, the interrupt priority
* set through \ref cyhal_gpio_enable_event for a specific pin on a port will apply
* to the all the pins in that pin's port. If multiple pins on the same port are
* set at different priorities, the priority that the last pin is set to will be applied
* to all pins used on that port.
*
* \section group_hal_impl_gpio_interconnect Interconnect
* In PSoC6 only a subset of pins available on a board are connected to input
* triggers. Another subset is connected to output triggers. Check the
* appropriate file for your board in pin_packages/ to determine what pins can
* be used. A particular pin can have 0 or 1 input triggers and 0 or 1 output
* triggers. Input triggers to a pin are used to clear/set the GPIO pins
* output. An output trigger on a pin is activated when the pins GPIO input is
* set.
*
* \} group_hal_impl_gpio
*/
#elif defined(COMPONENT_CAT2)
/** \addtogroup group_hal_impl_gpio GPIO
* \ingroup group_hal_impl
* \{
* \section group_hal_impl_gpio_interrupt Interrupt Priorities
* In CAT2 (PMG/PSoC 4), ports 0 through 3 have dedicated IRQ lines (ioss_interrupts_gpio_0_IRQn - ioss_interrupts_gpio_3_IRQn)
* and other ports are required to use the All-Port IRQ line (ioss_interrupt_gpio_IRQn).
* If multiple pins on the same port are set at different priorities, the priority that the
* last pin is set to will be applied to all pins used on that port. When using the pin that does
* not have a dedicated IRQ line (port 4 and higher) following are the implications,
* 1. The priority set through \ref cyhal_gpio_enable_event for the specific pin will
* apply to all pins on port 4 and higher.
* 2. The interrupts will not be proccessed in the same order as they were received
* because the same All-Port IRQ line will be used for all GPIOs.
*
** \section group_hal_impl_gpio_interconnect Interconnect
* PSoC 4 does not have GPIO triggers.
* \} group_hal_impl_gpio
*/
#endif
/*******************************************************************************
* Defines
*******************************************************************************/

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

558
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -23,9 +23,9 @@
*******************************************************************************/
/**
* \addtogroup group_hal_impl PSoC 6 Implementation Specific
* \addtogroup group_hal_impl CAT1 (PSoC 6) Implementation Specific
* \{
* This section provides details about the PSoC 6 implementation of the Cypress HAL.
* This section provides details about the CAT1 (PSoC 6) implementation of the Cypress HAL.
* All information within this section is platform specific and is provided for reference.
* Portable application code should depend only on the APIs and types which are documented
* in the @ref group_hal section.
@ -33,9 +33,9 @@
* \section group_hal_impl_mapping HAL Resource Hardware Mapping
* The following table shows a mapping of each HAL driver to the lower level firmware driver
* and the corresponding hardware resource. This is intended to help understand how the HAL
* is implemented for PSoC 6 and what features the underlying hardware supports.
* is implemented for CAT1 and what features the underlying hardware supports.
*
* | HAL Resource | PDL Driver(s) | PSoC 6 Hardware |
* | HAL Resource | PDL Driver(s) | CAT1 Hardware |
* | ------------------ | ------------------- | -------------------------------- |
* | ADC | cy_adc | SAR ADC |
* | Clock | cy_sysclk | All clocks (system & peripheral) |
@ -54,6 +54,7 @@
* | PDM/PCM | cy_pdm_pcm | PDM-PCM |
* | PWM | cy_pwm | TCPWM |
* | QSPI | cy_smif | QSPI (SMIF) |
* | Quadrature Decoder | cy_tcpwm_quaddec | TCPWM |
* | RTC | cy_rtc | RTC |
* | SDHC | cy_sd_host | SD Host |
* | SDIO | cy_sd_host, or NA | SD Host, or UDB |
@ -75,7 +76,7 @@
*/
/**
* \addtogroup group_hal_impl_hw_types PSoC 6 Specific Hardware Types
* \addtogroup group_hal_impl_hw_types CAT1 Specific Hardware Types
* \{
* Aliases for types which are part of the public HAL interface but whose representations
* need to vary per HAL implementation
@ -110,31 +111,29 @@ extern "C" {
* \cond INTERNAL
*/
#define CYHAL_ADC_IMPL_HEADER "cyhal_adc_impl.h" //!< Implementation specific header for ADC
#define CYHAL_CRC_IMPL_HEADER "cyhal_crc_impl.h" //!< Implementation specific header for CRC
#define CYHAL_DMA_IMPL_HEADER "cyhal_dma_impl.h" //!< Implementation specific header for DMA
#define CYHAL_CLOCK_IMPL_HEADER "cyhal_clock_impl.h" //!< Implementation specific header for Clocks
#define CYHAL_GPIO_IMPL_HEADER "cyhal_gpio_impl.h" //!< Implementation specific header for GPIO
#define CYHAL_PDMPCM_IMPL_HEADER "cyhal_pdmpcm_impl.h" //!< Implementation specific header for PDMPCM
#define CYHAL_PWM_IMPL_HEADER "cyhal_pwm_impl.h" //!< Implementation specific header for PWM
#define CYHAL_SYSTEM_IMPL_HEADER "cyhal_system_impl.h" //!< Implementation specific header for System
#define CYHAL_SYSPM_IMPL_HEADER "cyhal_syspm_impl.h" //!< Implementation specific header for System Power Management
#define CYHAL_TIMER_IMPL_HEADER "cyhal_timer_impl.h" //!< Implementation specific header for Timer
#define CYHAL_TRNG_IMPL_HEADER "cyhal_trng_impl.h" //!< Implementation specific header for TRNG
#define CYHAL_ADC_IMPL_HEADER "cyhal_adc_impl.h" //!< Implementation specific header for ADC
#define CYHAL_CRC_IMPL_HEADER "cyhal_crc_impl.h" //!< Implementation specific header for CRC
#define CYHAL_DMA_IMPL_HEADER "cyhal_dma_impl.h" //!< Implementation specific header for DMA
#define CYHAL_CLOCK_IMPL_HEADER "cyhal_clock_impl.h" //!< Implementation specific header for Clocks
#define CYHAL_GPIO_IMPL_HEADER "cyhal_gpio_impl.h" //!< Implementation specific header for GPIO
#define CYHAL_PDMPCM_IMPL_HEADER "cyhal_pdmpcm_impl.h" //!< Implementation specific header for PDMPCM
#define CYHAL_PWM_IMPL_HEADER "cyhal_pwm_impl.h" //!< Implementation specific header for PWM
#define CYHAL_QUADDEC_IMPL_HEADER "cyhal_quaddec_impl.h" //!< Implementation specific header for QUADDEC
#define CYHAL_SYSTEM_IMPL_HEADER "cyhal_system_impl.h" //!< Implementation specific header for System
#define CYHAL_SYSPM_IMPL_HEADER "cyhal_syspm_impl.h" //!< Implementation specific header for System Power Management
#define CYHAL_TIMER_IMPL_HEADER "cyhal_timer_impl.h" //!< Implementation specific header for Timer
#define CYHAL_TRNG_IMPL_HEADER "cyhal_trng_impl.h" //!< Implementation specific header for TRNG
#define CYHAL_INTERCONNECT_IMPL_HEADER "cyhal_interconnect_impl.h" //!< Implementation specific header for Interconnect
/** \endcond */
/**
*/
typedef uint32_t cyhal_source_t; //!< Routable signal source
/** Callbacks for Sleep and Deepsleep APIs */
#define cyhal_system_callback_t cy_stc_syspm_callback_t
/** @brief Event callback data object */
typedef struct {
cy_israddress callback;
void* callback_arg;
cy_israddress callback;
void* callback_arg;
} cyhal_event_callback_data_t;
/**
@ -146,12 +145,15 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXTCPWM
TCPWM_Type* base;
cyhal_resource_inst_t resource;
cyhal_clock_t clock;
bool dedicated_clock;
uint32_t clock_hz;
cyhal_event_callback_data_t callback_data;
TCPWM_Type* base;
cyhal_resource_inst_t resource;
cyhal_clock_t clock;
bool dedicated_clock;
uint32_t clock_hz;
cyhal_event_callback_data_t callback_data;
#if defined(CY_IP_MXPERI_TR)
cyhal_source_t inputs[5];
#endif
#else
void *empty;
#endif
@ -167,20 +169,20 @@ typedef struct {
*/
typedef struct {
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA)
cyhal_resource_inst_t resource;
cyhal_resource_inst_t resource;
union
{
#ifdef CY_IP_M4CPUSS_DMA
cy_stc_dma_channel_config_t dw;
cy_stc_dma_channel_config_t dw;
#endif
#ifdef CY_IP_M4CPUSS_DMAC
cy_stc_dmac_channel_config_t dmac;
cy_stc_dmac_channel_config_t dmac;
#endif
} channel_config;
union
{
#ifdef CY_IP_M4CPUSS_DMA
cy_stc_dma_descriptor_config_t dw;
cy_stc_dma_descriptor_config_t dw;
#endif
#ifdef CY_IP_M4CPUSS_DMAC
cy_stc_dmac_descriptor_config_t dmac;
@ -189,14 +191,16 @@ typedef struct {
union
{
#ifdef CY_IP_M4CPUSS_DMA
cy_stc_dma_descriptor_t dw;
cy_stc_dma_descriptor_t dw;
#endif
#ifdef CY_IP_M4CPUSS_DMAC
cy_stc_dmac_descriptor_t dmac;
#endif
} descriptor;
uint32_t irq_cause;
cyhal_event_callback_data_t callback_data;
uint32_t direction;
uint32_t irq_cause;
cyhal_event_callback_data_t callback_data;
cyhal_source_t source;
#else
void *empty;
#endif
@ -213,24 +217,25 @@ struct _cyhal_adc_channel_s;
*/
typedef struct {
#ifdef CY_IP_MXS40PASS_SAR
SAR_Type* base;
cyhal_resource_inst_t resource;
cyhal_clock_t clock;
bool dedicated_clock;
bool continuous_scanning;
SAR_Type* base;
cyhal_resource_inst_t resource;
cyhal_clock_t clock;
cyhal_source_t source;
bool dedicated_clock;
bool continuous_scanning;
/* Has at least one conversion completed since the last configuration change */
volatile bool conversion_complete;
struct _cyhal_adc_channel_s* channel_config[CY_SAR_MAX_NUM_CHANNELS];
uint8_t user_enabled_events;
cyhal_event_callback_data_t callback_data;
cyhal_async_mode_t async_mode;
cyhal_dma_t dma;
volatile bool conversion_complete;
struct _cyhal_adc_channel_s* channel_config[CY_SAR_MAX_NUM_CHANNELS];
uint8_t user_enabled_events;
cyhal_event_callback_data_t callback_data;
cyhal_async_mode_t async_mode;
cyhal_dma_t dma;
/* Always updated to contain the location where the next result should be stored */
int32_t *async_buff_orig;
int32_t *async_buff_next;
bool async_transfer_in_uv; /* Default is counts */
int32_t *async_buff_orig;
int32_t *async_buff_next;
bool async_transfer_in_uv; /* Default is counts */
/* Only decremented after all elements from a scan have been copied into async_buff */
size_t async_scans_remaining;
size_t async_scans_remaining;
#else
void *empty;
#endif
@ -245,11 +250,11 @@ typedef struct {
*/
typedef struct _cyhal_adc_channel_s { /* Struct given an explicit name to make the forward declaration above work */
#ifdef CY_IP_MXS40PASS_SAR
cyhal_adc_t* adc;
cyhal_gpio_t vplus;
cyhal_gpio_t vminus;
uint8_t channel_idx;
uint32_t minimum_acquisition_ns;
cyhal_adc_t* adc;
cyhal_gpio_t vplus;
cyhal_gpio_t vminus;
uint8_t channel_idx;
uint32_t minimum_acquisition_ns;
#else
void *empty;
#endif
@ -258,21 +263,21 @@ typedef struct _cyhal_adc_channel_s { /* Struct given an explicit name to make t
/** @brief Comparator object */
typedef struct {
#if defined(CY_IP_MXLPCOMP_INSTANCES) || defined(CY_IP_MXS40PASS_CTB_INSTANCES)
cyhal_resource_inst_t resource;
cyhal_resource_inst_t resource;
union
{
#if defined(CY_IP_MXS40PASS_CTB_INSTANCES)
CTBM_Type *base_ctb;
CTBM_Type *base_ctb;
#endif
#if defined(CY_IP_MXLPCOMP_INSTANCES)
LPCOMP_Type *base_lpcomp;
LPCOMP_Type *base_lpcomp;
#endif
};
cyhal_gpio_t pin_vin_p;
cyhal_gpio_t pin_vin_m;
cyhal_gpio_t pin_out;
cyhal_event_callback_data_t callback_data;
uint32_t irq_cause;
cyhal_gpio_t pin_vin_p;
cyhal_gpio_t pin_vin_m;
cyhal_gpio_t pin_out;
cyhal_event_callback_data_t callback_data;
uint32_t irq_cause;
#else
void *empty;
#endif
@ -287,9 +292,9 @@ typedef struct {
*/
typedef struct {
#if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT)
CRYPTO_Type* base;
cyhal_resource_inst_t resource;
uint32_t crc_width;
CRYPTO_Type* base;
cyhal_resource_inst_t resource;
uint32_t crc_width;
#endif
} cyhal_crc_t;
@ -302,12 +307,12 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXS40PASS_CTDAC
CTDAC_Type* base_dac;
CTBM_Type* base_opamp;
cyhal_resource_inst_t resource_dac;
cyhal_resource_inst_t resource_opamp;
cyhal_resource_inst_t resource_aref_opamp;
cyhal_gpio_t pin;
CTDAC_Type* base_dac;
CTBM_Type* base_opamp;
cyhal_resource_inst_t resource_dac;
cyhal_resource_inst_t resource_opamp;
cyhal_resource_inst_t resource_aref_opamp;
cyhal_gpio_t pin;
#else
void *empty;
#endif
@ -321,12 +326,12 @@ typedef struct {
* between platforms and/or HAL releases.
*/
typedef struct {
CTBM_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_vin_p;
cyhal_gpio_t pin_vin_m;
cyhal_gpio_t pin_vout;
bool is_init_success;
CTBM_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_vin_p;
cyhal_gpio_t pin_vin_m;
cyhal_gpio_t pin_vout;
bool is_init_success;
} cyhal_opamp_t;
/**
@ -349,21 +354,21 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXSCB
CySCB_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_sda;
cyhal_gpio_t pin_scl;
cyhal_clock_t clock;
bool is_shared_clock;
cy_stc_scb_i2c_context_t context;
cy_stc_scb_i2c_master_xfer_config_t rx_config;
cy_stc_scb_i2c_master_xfer_config_t tx_config;
bool is_slave;
uint32_t address;
uint32_t irq_cause;
uint16_t pending;
uint16_t events;
cyhal_event_callback_data_t callback_data;
CySCB_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_sda;
cyhal_gpio_t pin_scl;
cyhal_clock_t clock;
bool is_shared_clock;
cy_stc_scb_i2c_context_t context;
cy_stc_scb_i2c_master_xfer_config_t rx_config;
cy_stc_scb_i2c_master_xfer_config_t tx_config;
bool is_slave;
uint32_t address;
uint32_t irq_cause;
uint16_t pending;
uint16_t events;
cyhal_event_callback_data_t callback_data;
#else
void *empty;
#endif
@ -401,37 +406,37 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXAUDIOSS
I2S_Type *base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_tx_sck;
cyhal_gpio_t pin_tx_ws;
cyhal_gpio_t pin_tx_sdo;
cyhal_gpio_t pin_rx_sck;
cyhal_gpio_t pin_rx_ws;
cyhal_gpio_t pin_rx_sdi;
cyhal_gpio_t pin_mclk;
bool is_tx_slave;
bool is_rx_slave;
uint32_t mclk_hz;
uint8_t channel_length;
uint8_t word_length;
uint32_t sample_rate_hz;
cyhal_clock_t clock;
bool is_clock_owned;
uint16_t user_enabled_events;
cyhal_event_callback_data_t callback_data;
cyhal_async_mode_t async_mode;
uint8_t async_dma_priority;
cyhal_dma_t tx_dma;
cyhal_dma_t rx_dma;
I2S_Type *base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_tx_sck;
cyhal_gpio_t pin_tx_ws;
cyhal_gpio_t pin_tx_sdo;
cyhal_gpio_t pin_rx_sck;
cyhal_gpio_t pin_rx_ws;
cyhal_gpio_t pin_rx_sdi;
cyhal_gpio_t pin_mclk;
bool is_tx_slave;
bool is_rx_slave;
uint32_t mclk_hz;
uint8_t channel_length;
uint8_t word_length;
uint32_t sample_rate_hz;
cyhal_clock_t clock;
bool is_clock_owned;
uint16_t user_enabled_events;
cyhal_event_callback_data_t callback_data;
cyhal_async_mode_t async_mode;
uint8_t async_dma_priority;
cyhal_dma_t tx_dma;
cyhal_dma_t rx_dma;
// Note: When the async DMA mode is in use, these variables will always reflect the state
// that the transfer will be in after the in-progress DMA transfer, if any, is complete
volatile const void *async_tx_buff;
volatile size_t async_tx_length;
volatile void *async_rx_buff;
volatile size_t async_rx_length;
volatile bool pm_transition_ready;
cyhal_syspm_callback_data_t pm_callback;
volatile const void *async_tx_buff;
volatile size_t async_tx_length;
volatile void *async_rx_buff;
volatile size_t async_rx_length;
volatile bool pm_transition_ready;
cyhal_syspm_callback_data_t pm_callback;
#else
void *empty;
#endif
@ -445,14 +450,10 @@ typedef struct {
* between platforms and/or HAL releases.
*/
typedef struct {
#ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES
MCWDT_STRUCT_Type *base;
cyhal_resource_inst_t resource;
cyhal_event_callback_data_t callback_data;
bool clear_int_mask;
#else
void *empty;
#endif
MCWDT_STRUCT_Type *base;
cyhal_resource_inst_t resource;
cyhal_event_callback_data_t callback_data;
bool clear_int_mask;
} cyhal_lptimer_t;
/**
@ -464,20 +465,20 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXAUDIOSS_INSTANCES
PDM_Type *base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_data;
cyhal_gpio_t pin_clk;
PDM_Type *base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_data;
cyhal_gpio_t pin_clk;
/** User requested irq, see cyhal_pdm_pcm_event_t */
uint32_t irq_cause;
cyhal_event_callback_data_t callback_data;
uint8_t word_size;
cyhal_dma_t dma;
volatile bool stabilized;
volatile bool pm_transition_ready;
cyhal_syspm_callback_data_t pm_callback;
void *async_buffer;
size_t async_read_remaining;
uint32_t irq_cause;
cyhal_event_callback_data_t callback_data;
uint8_t word_size;
cyhal_dma_t dma;
volatile bool stabilized;
volatile bool pm_transition_ready;
cyhal_syspm_callback_data_t pm_callback;
void *async_buffer;
size_t async_read_remaining;
#else
void *empty;
#endif
@ -492,9 +493,9 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXTCPWM
cyhal_tcpwm_t tcpwm;
cyhal_gpio_t pin;
cyhal_gpio_t pin_compl;
cyhal_tcpwm_t tcpwm;
cyhal_gpio_t pin;
cyhal_gpio_t pin_compl;
#else
void *empty;
#endif
@ -509,27 +510,49 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXSMIF
SMIF_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_ios[8];
cyhal_gpio_t pin_sclk;
cyhal_gpio_t pin_ssel[SMIF_CHIP_TOP_SPI_SEL_NR];
SMIF_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_ios[8];
en_hsiom_sel_t saved_io_hsiom[8];
cyhal_gpio_t pin_sclk;
en_hsiom_sel_t saved_sclk_hsiom;
cyhal_gpio_t pin_ssel[SMIF_CHIP_TOP_SPI_SEL_NR];
en_hsiom_sel_t saved_ssel_hsiom[SMIF_CHIP_TOP_SPI_SEL_NR];
/* Active slave select */
cy_en_smif_slave_select_t slave_select;
cyhal_clock_t clock;
bool is_clock_owned;
uint8_t mode;
cy_stc_smif_context_t context;
cy_en_smif_data_select_t data_select;
uint32_t irq_cause;
cyhal_event_callback_data_t callback_data;
cyhal_syspm_callback_data_t pm_callback;
bool pm_transition_pending;
cy_en_smif_slave_select_t slave_select;
cyhal_clock_t clock;
bool is_clock_owned;
uint8_t mode;
cy_stc_smif_context_t context;
cy_en_smif_data_select_t data_select;
uint32_t irq_cause;
cyhal_event_callback_data_t callback_data;
cyhal_syspm_callback_data_t pm_callback;
bool pm_transition_pending;
#else
void *empty;
#endif /* ifdef CY_IP_MXSMIF */
} cyhal_qspi_t;
/**
* @brief Quadrature Decoder object
*
* Application code should not rely on the specific contents of this struct.
* They are considered an implementation detail which is subject to change
* between platforms and/or HAL releases.
*/
typedef struct {
#ifdef CY_IP_MXTCPWM
cyhal_tcpwm_t tcpwm;
cyhal_gpio_t phi_a;
cyhal_gpio_t phi_b;
cyhal_gpio_t index;
uint32_t last_counter_value;
#else
void *empty;
#endif
} cyhal_quaddec_t;
/**
* @brief RNG object
*
@ -539,8 +562,8 @@ typedef struct {
*/
typedef struct {
#if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT)
CRYPTO_Type* base;
cyhal_resource_inst_t resource;
CRYPTO_Type* base;
cyhal_resource_inst_t resource;
#else
void *empty;
#endif
@ -555,7 +578,7 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXS40SRSS_RTC
cy_stc_rtc_dst_t dst;
cy_stc_rtc_dst_t dst;
#else
void *empty;
#endif
@ -570,26 +593,40 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXSDHC
SDHC_Type* base;
cyhal_resource_inst_t resource;
cyhal_clock_t clock;
bool emmc;
cy_en_sd_host_dma_type_t dmaType;
bool enableLedControl;
cy_stc_sd_host_context_t context;
cyhal_gpio_t pin_clk;
cyhal_gpio_t pin_cmd;
cyhal_gpio_t pin_data[8];
cyhal_gpio_t pin_cardDetect;
cyhal_gpio_t pin_ioVoltSel;
cyhal_gpio_t pin_cardIfPwrEn;
cyhal_gpio_t pin_cardMechWriteProt;
cyhal_gpio_t pin_ledCtrl;
cyhal_gpio_t pin_cardEmmcReset;
uint32_t irq_cause;
cyhal_event_callback_data_t callback_data;
bool pm_transition_pending;
cyhal_syspm_callback_data_t pm_callback_data;
SDHC_Type* base;
cyhal_resource_inst_t resource;
cyhal_clock_t clock;
bool emmc;
cy_en_sd_host_dma_type_t dma_type;
uint8_t bus_width;
bool enable_led_control;
/* TOUT setting of SDHC block */
uint8_t data_timeout_tout;
bool data_timeout_auto_reconfig;
/* Desired by user data timeout in card clocks */
uint32_t data_timeout_card_clocks_user;
cy_stc_sd_host_context_t context;
cyhal_gpio_t pin_clk;
cyhal_gpio_t pin_cmd;
cyhal_gpio_t pin_data[8];
cyhal_gpio_t pin_card_detect;
cyhal_gpio_t pin_io_vol_sel;
cyhal_gpio_t pin_card_pwr_en;
cyhal_gpio_t pin_card_mech_write_prot;
cyhal_gpio_t pin_led_ctrl;
cyhal_gpio_t pin_emmc_reset;
uint32_t irq_cause;
cyhal_event_callback_data_t callback_data;
bool pm_transition_pending;
cyhal_syspm_callback_data_t pm_callback_data;
bool low_voltage_io_desired;
bool low_voltage_io_set;
uint32_t bus_frequency_hz;
/* Frequency of HF clock, that provided to SDHC block */
uint32_t block_source_freq_hz;
/* card detect GPIO callback enabled */
bool cd_gpio_cb_enabled;
uint32_t adma_descriptor_tbl[2];
#else
void *empty;
#endif
@ -604,37 +641,38 @@ typedef struct {
*/
typedef struct {
#if defined(CY_IP_MXSDHC)
SDHC_Type* base;
bool emmc;
cy_en_sd_host_dma_type_t dmaType;
cy_stc_sd_host_context_t context;
SDHC_Type* base;
bool emmc;
cy_en_sd_host_dma_type_t dma_type;
cy_stc_sd_host_context_t context;
uint32_t adma_descriptor_tbl[2];
#elif defined(CYHAL_UDB_SDIO)
cyhal_dma_t dma0Ch0;
cyhal_dma_t dma0Ch1;
cyhal_dma_t dma1Ch1;
cyhal_dma_t dma1Ch3;
stc_sdio_irq_cb_t* pfuCb;
cyhal_dma_t dma0Ch0;
cyhal_dma_t dma0Ch1;
cyhal_dma_t dma1Ch1;
cyhal_dma_t dma1Ch3;
stc_sdio_irq_cb_t* pfuCb;
#endif /* defined(CY_IP_MXSDHC) */
#if defined(CYHAL_UDB_SDIO) || defined(CY_IP_MXSDHC)
cyhal_clock_t clock;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_clk;
cyhal_gpio_t pin_cmd;
cyhal_gpio_t pin_data0;
cyhal_gpio_t pin_data1;
cyhal_gpio_t pin_data2;
cyhal_gpio_t pin_data3;
cyhal_clock_t clock;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_clk;
cyhal_gpio_t pin_cmd;
cyhal_gpio_t pin_data0;
cyhal_gpio_t pin_data1;
cyhal_gpio_t pin_data2;
cyhal_gpio_t pin_data3;
uint32_t frequencyhal_hz;
uint16_t block_size;
uint32_t irq_cause;
uint32_t frequencyhal_hz;
uint16_t block_size;
uint32_t irq_cause;
uint32_t events;
cyhal_event_callback_data_t callback_data;
uint32_t events;
cyhal_event_callback_data_t callback_data;
bool pm_transition_pending;
cyhal_syspm_callback_data_t pm_callback_data;
bool pm_transition_pending;
cyhal_syspm_callback_data_t pm_callback_data;
#else
void *empty;
#endif /* defined(CY_IP_MXSDHC) || defined(CY_IP_MXSDHC) */
@ -649,32 +687,32 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXSCB
CySCB_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_miso;
cyhal_gpio_t pin_mosi;
cyhal_gpio_t pin_sclk;
cyhal_gpio_t pin_ssel[4];
cy_en_scb_spi_polarity_t ssel_pol[4];
uint8_t active_ssel;
cyhal_clock_t clock;
cy_en_scb_spi_sclk_mode_t clk_mode;
uint8_t mode;
uint8_t data_bits;
bool is_slave;
bool alloc_clock;
uint8_t oversample_value;
bool msb_first;
cy_stc_scb_spi_context_t context;
uint32_t irq_cause;
uint16_t volatile pending;
uint8_t write_fill;
void *rx_buffer;
uint32_t rx_buffer_size;
const void *tx_buffer;
uint32_t tx_buffer_size;
bool is_async;
cyhal_event_callback_data_t callback_data;
CySCB_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_miso;
cyhal_gpio_t pin_mosi;
cyhal_gpio_t pin_sclk;
cyhal_gpio_t pin_ssel[4];
cy_en_scb_spi_polarity_t ssel_pol[4];
uint8_t active_ssel;
cyhal_clock_t clock;
cy_en_scb_spi_sclk_mode_t clk_mode;
uint8_t mode;
uint8_t data_bits;
bool is_slave;
bool alloc_clock;
uint8_t oversample_value;
bool msb_first;
cy_stc_scb_spi_context_t context;
uint32_t irq_cause;
uint16_t volatile pending;
uint8_t write_fill;
void *rx_buffer;
uint32_t rx_buffer_size;
const void *tx_buffer;
uint32_t tx_buffer_size;
bool is_async;
cyhal_event_callback_data_t callback_data;
#else
void *empty;
#endif
@ -689,8 +727,8 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXTCPWM
cyhal_tcpwm_t tcpwm;
uint32_t default_value;
cyhal_tcpwm_t tcpwm;
uint32_t default_value;
#else
void *empty;
#endif
@ -705,20 +743,20 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXSCB
CySCB_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_rx;
cyhal_gpio_t pin_tx;
cyhal_gpio_t pin_cts;
cyhal_gpio_t pin_rts;
bool is_user_clock;
cyhal_clock_t clock;
cy_stc_scb_uart_context_t context;
cy_stc_scb_uart_config_t config;
uint32_t irq_cause;
en_hsiom_sel_t saved_tx_hsiom;
en_hsiom_sel_t saved_rts_hsiom;
cyhal_event_callback_data_t callback_data;
CySCB_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_rx;
cyhal_gpio_t pin_tx;
cyhal_gpio_t pin_cts;
cyhal_gpio_t pin_rts;
bool is_user_clock;
cyhal_clock_t clock;
cy_stc_scb_uart_context_t context;
cy_stc_scb_uart_config_t config;
uint32_t irq_cause;
en_hsiom_sel_t saved_tx_hsiom;
en_hsiom_sel_t saved_rts_hsiom;
cyhal_event_callback_data_t callback_data;
#else
void *empty;
#endif
@ -733,15 +771,15 @@ typedef struct {
*/
typedef struct {
#ifdef CY_IP_MXUSBFS
USBFS_Type* base;
cy_stc_usbfs_dev_drv_context_t context;
cyhal_resource_inst_t resource;
cyhal_resource_inst_t pll_resource;
cyhal_clock_t clock;
bool shared_clock;
cyhal_gpio_t pin_dp;
cyhal_gpio_t pin_dm;
cyhal_syspm_callback_data_t pm_callback;
USBFS_Type* base;
cy_stc_usbfs_dev_drv_context_t context;
cyhal_resource_inst_t resource;
cyhal_resource_inst_t pll_resource;
cyhal_clock_t clock;
bool shared_clock;
cyhal_gpio_t pin_dp;
cyhal_gpio_t pin_dm;
cyhal_syspm_callback_data_t pm_callback;
uint8_t *rd_data[CY_USBFS_DEV_DRV_NUM_EPS_MAX];
uint32_t rd_size[CY_USBFS_DEV_DRV_NUM_EPS_MAX];
#else

7
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h Normal file → Executable file
View File

@ -8,7 +8,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -50,7 +50,7 @@
* The following snippet shows how a specific resource used directly in PDL or the
* configurators can be freed so that it can be used by HAL.<br>
*
* \snippet hw_mgr.c snippet_cyhal_hwmgr_reserve
* \snippet hal_hwmgr.c snippet_cyhal_hwmgr_reserve
*/
#pragma once
@ -79,6 +79,9 @@ extern "C" {
/** No resources of the requested type are available */
#define CYHAL_HWMGR_RSLT_ERR_NONE_FREE \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_HWMGR, 2))
/** No hardware connection available */
#define CYHAL_HWMGR_RSLT_ERR_NO_CONNECTION \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_HWMGR, 3))
/** Attempt to free a resource that was not used */
#define CYHAL_HWMGR_RSLT_WARN_UNUSED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_WARNING, CYHAL_RSLT_MODULE_HWMGR, 50))

57
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr_impl.h Executable file
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@ -0,0 +1,57 @@
/***************************************************************************//**
* \file cyhal_hwmgr_impl.h
*
* Description:
* This file provides internal device specific hardware manager utilities.
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cyhal_hw_resources.h"
#include "cyhal_triggers.h"
#if defined(__cplusplus)
extern "C" {
#endif
/** Function pointer for use with _cyhal_hwmgr_reserve_instance for getting the input
* destination of the specified hardware type given a specific block/channel */
typedef cyhal_dest_t (*_cyhal_hwmgr_get_input_dest_t)(uint8_t block_num, uint8_t channel_num);
/** Function pointer for use with _cyhal_hwmgr_reserve_instance for getting the output
* source of the specified hardware type given a specific block/channel */
typedef cyhal_source_t (*_cyhal_hwmgr_get_output_source_t)(uint8_t block_num, uint8_t channel_num);
/** Attempts to reserve a resource of the specified \p type that is able to connect to the
* \p src and \p dest signals if provided.
* @param[in] type The type of resource to reserve
* @param[in] src The optional input source to the resource type to be reserved
* @param[in] dest The optional destination target of the resource type to be reserved
* @param[in] get_src Function to use to get a source for a specific block/channel
* @param[in] get_dest Function to use to get a destination for a specific block/channel
* @param[out] resource The reserved resource if successful
* @return The status of the reservation request
*/
cy_rslt_t _cyhal_hwmgr_allocate_with_connection(cyhal_resource_t type, const cyhal_source_t *src, const cyhal_dest_t *dest,
_cyhal_hwmgr_get_output_source_t get_src, _cyhal_hwmgr_get_input_dest_t get_dest, cyhal_resource_inst_t *resource);
#if defined(__cplusplus)
}
#endif

62
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -57,23 +57,23 @@
* the <b>sda</b> and <b>scl</b> pins.
*
* Initializing as I2C master
* \snippet i2c.c snippet_cyhal_i2c_master_init
* \snippet hal_i2c.c snippet_cyhal_i2c_master_init
*
* Initializing as I2C slave
* \snippet i2c.c snippet_cyhal_i2c_slave_init
* \snippet hal_i2c.c snippet_cyhal_i2c_slave_init
*
* \subsection subsection_i2c_snippet_2 Snippet 2: Handling events
* This snippet shows how to enable and handle I2C events using \ref cyhal_i2c_enable_event and \ref cyhal_i2c_register_callback.<br>
* The <b>callback</b> parameter of \ref cyhal_i2c_register_callback is used to pass the callback handler that will be invoked when an event occurs.<br>
* The <b>event</b> parameter of \ref cyhal_i2c_enable_event is used to pass the bitmasks of events ( \ref cyhal_i2c_event_t) to be enabled.
*
* \snippet i2c.c snippet_cyhal_handle_i2c_events
* \snippet hal_i2c.c snippet_cyhal_handle_i2c_events
*
* \subsection subsection_i2c_snippet_3 Snippet 3: I2C Master Asynchronous Transfer
* This snippet shows how to implement asynchronous transfers using \ref cyhal_i2c_master_transfer_async.<br>
* \ref cyhal_i2c_abort_async is used to stop the transfer, in this case when an error occurs.
*
* \snippet i2c.c snippet_cyhal_async_transfer
* \snippet hal_i2c.c snippet_cyhal_async_transfer
*
* \section subsection_i2c_moreinformation More Information
*
@ -121,8 +121,11 @@ extern "C" {
#define CYHAL_I2C_RSLT_ERR_PREVIOUS_ASYNCH_PENDING \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 4))
/** Failed to register I2C pm callback */
#define CYHAL_I2C_RSLT_ERR_PM_CALLBACK \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 5))
#define CYHAL_I2C_RSLT_ERR_PM_CALLBACK \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 5))
/** \ref cyhal_i2c_abort_async operation failed with timeout */
#define CYHAL_I2C_RSLT_ERR_ABORT_ASYNC_TIMEOUT \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 6))
/**
* \}
*/
@ -149,6 +152,19 @@ typedef enum
CYHAL_I2C_MASTER_ERR_EVENT = 1 << 20, /**< Indicates the I2C hardware has detected an error. */
} cyhal_i2c_event_t;
/** I2C FIFO type */
typedef enum
{
CYHAL_I2C_FIFO_RX, //!< Set RX FIFO level
CYHAL_I2C_FIFO_TX, //!< Set TX FIFO level
} cyhal_i2c_fifo_type_t;
/** Enum of possible output signals from an I2C */
typedef enum
{
CYHAL_I2C_OUTPUT_TRIGGER_RX_FIFO_LEVEL_REACHED, //!< Output the RX FIFO signal which is triggered when the receive FIFO has more entries than the configured level.
CYHAL_I2C_OUTPUT_TRIGGER_TX_FIFO_LEVEL_REACHED, //!< Output the TX FIFO signal which is triggered when the transmit FIFO has less entries than the configured level.
} cyhal_i2c_output_t;
/** Handler for I2C events */
typedef void (*cyhal_i2c_event_callback_t)(void *callback_arg, cyhal_i2c_event_t event);
@ -362,6 +378,38 @@ void cyhal_i2c_register_callback(cyhal_i2c_t *obj, cyhal_i2c_event_callback_t ca
*/
void cyhal_i2c_enable_event(cyhal_i2c_t *obj, cyhal_i2c_event_t event, uint8_t intr_priority, bool enable);
/** Sets a threshold level for a FIFO that will generate an interrupt and a
* trigger output. The RX FIFO interrupt and trigger will be activated when
* the receive FIFO has more entries than the threshold. The TX FIFO interrupt
* and trigger will be activated when the transmit FIFO has less entries than
* the threshold.
*
* @param[in] obj The I2C object
* @param[in] type FIFO type to set level for
* @param[in] level Level threshold to set
* @return The status of the level set
* */
cy_rslt_t cyhal_i2c_set_fifo_level(cyhal_i2c_t *obj, cyhal_i2c_fifo_type_t type, uint16_t level);
/** Enables the specified output signal from an I2C.
*
* @param[in] obj The I2C object
* @param[in] output Which output signal to enable
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. \p source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t cyhal_i2c_enable_output(cyhal_i2c_t *obj, cyhal_i2c_output_t output, cyhal_source_t *source);
/** Disables the specified output signal from an I2C
*
* @param[in] obj The I2C object
* @param[in] output Which output signal to disable
* @return The status of the output disable
* */
cy_rslt_t cyhal_i2c_disable_output(cyhal_i2c_t *obj, cyhal_i2c_output_t output);
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* not be used in new projects

41
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2s.h Normal file → Executable file
View File

@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -43,7 +43,8 @@
* * Configurable interrupt and callback assignment from I2S events - \ref cyhal_i2s_event_t
*
* \section section_i2s_quickstart Quick Start
* Initialize an I2S instance using the \ref cyhal_i2s_init and provide the transmit (tx) and/or receive (rx) pins.<br>
* Initialize an I2S instance using the \ref cyhal_i2s_init and provide the transmit (tx) and/or receive (rx) pins. Call
* \ref cyhal_i2s_start_tx and/or \ref cyhal_i2s_start_rx to enable transmit and/or receive functionality as desired.<br>
* See \ref subsection_i2s_snippet_1 for example initialization as transmit or receive.
* \note The clock parameter (const \ref cyhal_clock_t *clk) is optional and can be set
* to NULL to generate and use an available clock resource with a default frequency.
@ -61,27 +62,27 @@
* This snippet initializes an I2S resource for transmit or receive and assigns the pins.
*
* Initializing as I2S transmitter
* \snippet i2s.c snippet_cyhal_i2s_transmit_init
* \snippet hal_i2s.c snippet_cyhal_i2s_transmit_init
*
* Initializing as I2S receiver
* \snippet i2s.c snippet_cyhal_i2s_receive_init
* \snippet hal_i2s.c snippet_cyhal_i2s_receive_init
*
* \subsection subsection_i2s_snippet_2 Snippet 2: I2S Transmit One-shot
* This snippet shows how to transmit data using \ref cyhal_i2s_write_async when the entire sample
* is available at once. <br>
*
* \snippet i2s.c snippet_cyhal_i2s_async_transmit_one_shot
* \snippet hal_i2s.c snippet_cyhal_i2s_async_transmit_one_shot
* \subsection subsection_i2s_snippet_3 Snippet 3: I2S Transmit Streaming
* This snippet shows how to transmit data using \ref cyhal_i2s_write_async when sample data is
* being continuously loaded and transmitted (e.g. streaming over the network). <br>
*
* \snippet i2s.c snippet_cyhal_i2s_async_transmit_streaming
* \snippet hal_i2s.c snippet_cyhal_i2s_async_transmit_streaming
* \subsection subsection_i2s_snippet_4 Snippet 4: I2S Receive
* This snippet shows how to receive data using \ref cyhal_i2s_read_async. <br>
*
* \snippet i2s.c snippet_cyhal_i2s_async_receive
* \snippet hal_i2s.c snippet_cyhal_i2s_async_receive
*
* \section subsection_i2s_moreinformation More Information
*
@ -220,14 +221,15 @@ void cyhal_i2s_free(cyhal_i2s_t *obj);
*/
cy_rslt_t cyhal_i2s_set_sample_rate(cyhal_i2s_t *obj, uint32_t sample_rate_hz);
/** Starts transmitting data.
/** Starts transmitting data. Transmission will continue until it is stopped by
* calling @ref cyhal_i2s_stop_tx.
*
* @param[in] obj The I2S object
* @return The status of the start request.
*/
cy_rslt_t cyhal_i2s_start_tx(cyhal_i2s_t *obj);
/** Stops transmitting data.
/** Stops transmitting data. This immediately terminates transmission.
*
* @param[in] obj The I2S object
* @return The status of the stop request.
@ -241,14 +243,15 @@ cy_rslt_t cyhal_i2s_stop_tx(cyhal_i2s_t *obj);
*/
cy_rslt_t cyhal_i2s_clear_tx(cyhal_i2s_t *obj);
/** Starts receiving data.
/** Starts receiving data. Data will continue to be received until it is
* stopped by calling @ref cyhal_i2s_stop_rx.
*
* @param[in] obj The I2S object
* @return The status of the start request.
*/
cy_rslt_t cyhal_i2s_start_rx(cyhal_i2s_t *obj);
/** Stops receiving data.
/** Stops receiving data. This immediately terminates data receipt.
*
* @param[in] obj The I2S object
* @return The status of the stop request.
@ -264,9 +267,9 @@ cy_rslt_t cyhal_i2s_clear_rx(cyhal_i2s_t *obj);
/** Read data synchronously
*
* This will read either `length` words or the number of words that are currently available in the
* receive buffer, whichever is less, then return. The value pointed to by `length` will be updated
* to reflect the number of words that were actually read.
* This will read the number of words specified by the `length` parameter, or the number of words that
* are currently available in the receive buffer, whichever is less, then return. The value pointed to
* by `length` will be updated to reflect the number of words that were actually read.
*
* @param[in] obj The I2S object
* @param[out] data The buffer for receiving
@ -298,9 +301,9 @@ cy_rslt_t cyhal_i2s_read(cyhal_i2s_t *obj, void *data, size_t* length);
cy_rslt_t cyhal_i2s_write(cyhal_i2s_t *obj, const void *data, size_t *length);
/** Checks if the transmit functionality is enabled for the specified I2S peripheral (regardless of whether data
* is currently queued for transmission).
*
* The transmit functionality can be enabled by calling @ref cyhal_i2s_start_tx and disabled by calling
* is currently queued for transmission).
*
* The transmit functionality can be enabled by calling @ref cyhal_i2s_start_tx and disabled by calling
* @ref cyhal_i2s_stop_tx
*
* @param[in] obj The I2S peripheral to check
@ -319,9 +322,9 @@ bool cyhal_i2s_is_tx_busy(cyhal_i2s_t *obj);
/** Checks if the receive functionality is enabled for the specified I2S peripheral (regardless of whether any
* unread data has been received).
*
* The receive functionality can be enabled by calling @ref cyhal_i2s_start_rx and disabled by calling
* The receive functionality can be enabled by calling @ref cyhal_i2s_start_rx and disabled by calling
* @ref cyhal_i2s_stop_rx
*
*
* @param[in] obj The I2S peripheral to check
* @return Whether the I2S receive function is enabled.
*/

50
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -26,7 +26,7 @@
*******************************************************************************/
/**
* \addtogroup group_hal_interconnect INTERCONNECT (Internal digital routing)
* \addtogroup group_hal_interconnect Interconnect (Internal Digital Routing)
* \ingroup group_hal
* \{
* High level interface to the Cypress digital routing.
@ -36,7 +36,7 @@
* The following types of connections are supported:
* * Connection from a peripheral to a pin. (A dedicated connection must exist
between the pin and the peripheral; see the device datasheet for more details)
* * Experimental support for connecting between two on-chip "trigger" terminals.
* * Connecting two peripherals in hardware using the on-chip trigger signaling
*
* \section subsection_interconnect_quickstart Quick Start
* * \ref cyhal_connect_pin can be used to connect a pin to a peripheral.(A dedicated connection must exist
@ -47,9 +47,15 @@
* \section section_interconnect_snippets Code Snippets
*
* \subsection subsection_interconnect_snippet1 Snippet 1: Connecting a pin to TCPWM block
* The following code snippet demonstrates connecting a GPIO pin to an active TCPWM block on a PSoC 6 device.
* The following code snippet demonstrates connecting a GPIO pin to an active TCPWM block on a device
* using the \ref cyhal_connect_pin. It is assumed that the TCPWM is already configured and active.<br>
* \snippet interconnect.c snippet_cyhal_interconnect_connect_pin
* \snippet hal_interconnect.c snippet_cyhal_interconnect_connect_pin
*
* \subsection subsection_interconnect_snippet2 Snippet 2: Connecting a Timer output signal to a DMA input signal
* The following code snippet demonstrates configuring and connecting a Timer
* which will overflow every 2 seconds and, in doing so, trigger a DMA channel
* start.
* \snippet hal_interconnect.c snippet_cyhal_interconnect_timer_to_dma
*/
#pragma once
@ -69,22 +75,26 @@ extern "C" {
* \{ *//**
*/
/** No connection is available */
#define CYHAL_CONNECT_RSLT_NO_CONNECTION \
/** The source and destination are already connected */
#define CYHAL_INTERCONNECT_RSLT_ALREADY_CONNECTED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 0))
/** The connections source and destination are already connected */
#define CYHAL_CONNECT_RSLT_ALREADY_CONNECTED \
/** Connection is invalid */
#define CYHAL_INTERCONNECT_RSLT_INVALID_CONNECTION \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 1))
/** Invalid trigger connection */
#define CYHAL_CONNECT_RSLT_INVALID_TRIGGER_CONNECTION \
/** Cannot disconnect. Either no connection in the first place or a bad argument */
#define CYHAL_INTERCONNECT_RSLT_CANNOT_DISCONNECT \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 2))
/**
* \}
*/
/** Indicates that a mux output does not continue to another mux */
#define CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION 0xFF
/** Trigger type */
typedef enum
{
CYHAL_SIGNAL_TYPE_LEVEL = 0, //!< Level triggered
CYHAL_SIGNAL_TYPE_EDGE = 1, //!< Edge triggered
} cyhal_signal_type_t;
/** Connect a pin to a peripheral terminal. This will route a direct connection from the pin to the peripheral.
* Any previous direct connection from the pin will be overriden.<br>
@ -100,20 +110,6 @@ cy_rslt_t cyhal_connect_pin(const cyhal_resource_pin_mapping_t *pin_connection);
*/
cy_rslt_t cyhal_disconnect_pin(cyhal_gpio_t pin);
/**
* \warning WORK IN PROGRESS. This function is not yet fully implemented.<br>
*
* Connects two digital terminals on the device using any internal interconnect. A single
* source can drive multiple destinations, but a destination can be driven by only one source.
* If the destination is already connected, or the connection can not be established an error will be returned.
* @param[in] source The source of the signal to connect
* @param[in] dest The destination of the signal to connect
* @return The status of the connect request
*/
cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest);
#if defined(__cplusplus)
}
#endif

110
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@ -0,0 +1,110 @@
/***************************************************************************//**
* \file cyhal_interconnect_impl.h
*
* \brief
* Implementation details for the PSoC4 interconnect.
*
********************************************************************************
* \copyright
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_impl_interconnect Interconnect (Internal Digital Routing)
* \ingroup group_hal_impl
* \{
* The interconnect system connects the various hardware peripherals using trigger
* signals. Triggers are output when a particular event occurs or condition is
* met by one of the peripherals. These triggers can be routed to other
* peripherals using the interconnect system in order to initiate an action at
* the destination peripheral.
*
* Peripherals must be configured to produce/accept trigger signals. Therefore
* in practice, there is no need to call \ref \_cyhal_connect_signal manually.
* Instead, use the per-peripheral cyhal_<PERI>_connect_digital or
* cyhal_<PERI>_enable_output which will handle configuring the peripheral and
* making the connections internally.
*
* Trigger routing is implemented using trigger multiplexers. A single source
* trigger can be routed to multiple destinations but a single destination can
* only be connected to a single source. There are different trigger layouts
* depending on device architecture.
*/
#if defined(COMPONENT_CAT1A)
/*
* <b>PSoC 6S1 Triggers:</b>
* \image html psoc6able2_trigger_layout.png width=800px
* <b>PSoC 6S2 Triggers:</b>
* \image html psoc6a2m_trigger_layout.png width=800px
* <b>PSoC 6S3 Triggers:</b>
* \image html psoc6a512k_trigger_layout.png width=800px
* <b>PSoC 6S4 Triggers:</b>
* \image html psoc6a256k_trigger_layout.png width=800px
*/
#elif defined(COMPONENT_CAT2)
/*
* <b>PSoC 4000S Triggers:</b>
* \image html psoc4000s_trigger_layout.png width=540px
* <b>PSoC 4100S Triggers:</b>
* \image html psoc4100s_trigger_layout.png width=540px
* <b>PSoC 4100S Plus Triggers:</b>
* \image html psoc4100sp_trigger_layout.png width=540px
* <b>PSoC 4100S Plus 256k Triggers:</b>
* \image html psoc4100sp256k_trigger_layout.png width=540px
*/
#endif /* defined(COMPONENT_CAT1A) */
#pragma once
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/** Connects two digital signals on the device using the internal interconnect.
* A single source can drive multiple destinations, but a destination can be
* driven by only one source. If the destination is already connected, or the
* connection can not be established an error will be returned.
* @param[in] source The source of the signal to connect
* @param[in] dest The destination of the signal to connect
* @param[in] type Whether the signal is edge or level triggered
* @return The status of the connect request
*/
cy_rslt_t _cyhal_connect_signal(cyhal_source_t source, cyhal_dest_t dest, cyhal_signal_type_t type);
/** Disconnects two digital signals on the device that were previously
* connected using the internal interconnect.
* @param[in] source The source of the signal to disconnect
* @param[in] dest The destination of the signal to disconnect
* @return The status of the disconnect request
*/
cy_rslt_t _cyhal_disconnect_signal(cyhal_source_t source, cyhal_dest_t dest);
/** Checks to see if a signal can be connected between the provided source and dest.
* @param[in] source The source of the signal to check
* @param[in] dest The destination of the signal to check
* @return Indication of whether a signal can connect between the provided points
*/
bool _cyhal_can_connect_signal(cyhal_source_t source, cyhal_dest_t dest);
#if defined(__cplusplus)
}
#endif
/** \} group_hal_impl_interconnect */

14
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -49,12 +49,12 @@
*
* \subsection subsection_lptimer_snippet_1 Snippet 1: LPTimer initialization with Default configuration
* The following snippet initializes a LPTimer in free running mode.
* \snippet lptimer.c snippet_cyhal_lptimer_simple_init_def
* \snippet hal_lptimer.c snippet_cyhal_lptimer_simple_init_def
*
* \subsection subsection_lptimer_snippet_2 Snippet 2: LPTimer interrupts
* The following snippet initializes a LPTimer and uses \ref cyhal_lptimer_set_match() to trigger an interrupt
* on match. Subsequent interrupts can be triggered at required times using \ref cyhal_lptimer_set_delay() called from the ISR.
* \snippet lptimer.c snippet_cyhal_lptimer_interrupt
* \snippet hal_lptimer.c snippet_cyhal_lptimer_interrupt
*/
#pragma once
@ -78,6 +78,14 @@ extern "C" {
#define CYHAL_LPTIMER_RSLT_ERR_PM_CALLBACK \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_WDT, 0))
/** Failed to execute not supported API */
#define CYHAL_LPTIMER_RSLT_ERR_NOT_SUPPORTED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_WDT, 1))
/** Timer is not enabled or it is not clocked */
#define CYHAL_LPTIMER_RSLT_ERR_DISABLED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_WDT, 2))
/**
* \}
*/

8
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_opamp.h Normal file → Executable file
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@ -8,7 +8,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -50,13 +50,13 @@
* \section subsection_opamp_snippet_1 Snippet 1: Bare opamp initialization
* The following snippet initializes a bare opamp. Note that any passive components
* (e.g. resistive feedback) must be implemented off-chip.
* \snippet opamp.c snippet_cyhal_opamp_init_diff
* \snippet hal_opamp.c snippet_cyhal_opamp_init_diff
* \section subsection_opamp_snippet_2 Snippet 2: Opamp follower initialization
* The following snippet initializes an opamp as a follower.
* \snippet opamp.c snippet_cyhal_opamp_init_follower
* \snippet hal_opamp.c snippet_cyhal_opamp_init_follower
* \section subsection_opamp_snippet_3 Snippet 3: Opamp powering-off and on
* The following snippet demonstrates temporarily powering-off the opamp without freeing it.
* \snippet opamp.c snippet_cyhal_opamp_start_stop
* \snippet hal_opamp.c snippet_cyhal_opamp_start_stop
*/
#pragma once

6
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pdmpcm.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -57,7 +57,7 @@
* \subsection subsection_pdmpcm_snippet_1 Snippet 1: PDM/PCM Initialization and Configuration
* This snippet initializes a PCM/PCM resource for conversion and assigns the pins.
*
* \snippet pdmpcm.c snippet_cyhal_pdmpcm_init
* \snippet hal_pdmpcm.c snippet_cyhal_pdmpcm_init
*
* \subsection subsection_pdmpcm_snippet_2 Snippet 2: PDM/PCM Asynchronous Receive
* This snippet shows how to receive data in the background using \ref cyhal_pdm_pcm_read_async.
@ -65,7 +65,7 @@
* to register a callback function and \ref cyhal_pdm_pcm_enable_event to enable callling the
* callback when an synchonous read completes.
*
* \snippet pdmpcm.c snippet_cyhal_pdmpcm_async_receive
* \snippet hal_pdmpcm.c snippet_cyhal_pdmpcm_async_receive
*
* \section subsection_pdmpcm_moreinformation More Information
*

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pdmpcm_impl.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2019-2020 Cypress Semiconductor Corporation
* Copyright 2019-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

75
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -56,13 +56,13 @@
* The clock frequency and the duty cycle is set using \ref cyhal_pwm_set_duty_cycle. <br>
* \ref cyhal_pwm_start starts the PWM output on the pin.
*
* \snippet pwm.c snippet_cyhal_pwm_simple_init
* \snippet hal_pwm.c snippet_cyhal_pwm_simple_init
*
*
* \subsection subsection_pwm_snippet_2 Snippet 2: Starting and stopping the PWM output
* \ref cyhal_pwm_start and \ref cyhal_pwm_stop functions can be used after PWM initialization to start and stop the PWM output.
*
* \snippet pwm.c snippet_cyhal_pwm_start_stop
* \snippet hal_pwm.c snippet_cyhal_pwm_start_stop
*
*
* \subsection subsection_pwm_snippet_3 Snippet 3: Advanced PWM output to pin
@ -70,14 +70,14 @@
* (left, right, center) and run mode (one-shot or continuous). The following snippet initializes a left-aligned, continuous running PWM
* assigned to the supplied pin. The inverted output is assigned to a second pin (<b>compl_pin</b>).
*
* \snippet pwm.c snippet_cyhal_pwm_adv_init
* \snippet hal_pwm.c snippet_cyhal_pwm_adv_init
*
*
* \subsection subsection_pwm_snippet_4 Snippet 4: Interrupts on PWM events
* PWM events like hitting the terminal count or a compare event can be used to trigger a callback function. <br>
* \ref cyhal_pwm_enable_event() can be used to enable one or more events to trigger the callback function.
*
* \snippet pwm.c snippet_cyhal_pwm_events
* \snippet hal_pwm.c snippet_cyhal_pwm_events
*/
#pragma once
@ -143,6 +143,25 @@ typedef enum {
CYHAL_PWM_CENTER_ALIGN = 2, /**< PWM is centered aligned (signal starts and ends low with a center aligned pulse) */
} cyhal_pwm_alignment_t;
/** PWM input signal */
typedef enum
{
CYHAL_PWM_INPUT_START, //!< Start signal
CYHAL_PWM_INPUT_STOP, //!< Stop signal
CYHAL_PWM_INPUT_RELOAD, //!< Reload signal
CYHAL_PWM_INPUT_COUNT, //!< Count signal
CYHAL_PWM_INPUT_CAPTURE, //!< Capture/swap signal
} cyhal_pwm_input_t;
/** PWM output signal */
typedef enum
{
CYHAL_PWM_OUTPUT_OVERFLOW, //!< Overflow signal
CYHAL_PWM_OUTPUT_UNDERFLOW, //!< Underflow signal
CYHAL_PWM_OUTPUT_COMPARE_MATCH, //!< Compare Match signal
CYHAL_PWM_OUTPUT_LINE_OUT, //!< PWM line out signal
} cyhal_pwm_output_t;
/** Handler for PWM interrupts */
typedef void(*cyhal_pwm_event_callback_t)(void *callback_arg, cyhal_pwm_event_t event);
@ -154,8 +173,8 @@ typedef void(*cyhal_pwm_event_callback_t)(void *callback_arg, cyhal_pwm_event_t
* for this object but the init function will initialize its contents.
* @param[in] pin The PWM pin to initialize. This pin is required, it cannot be \ref NC (No Connect).
* @param[in] compl_pin An optional, additional inverted output pin. <br>
* If supplied, this must be connected to the same PWM instance as <b>pin</b>, for
* PSoC 6 see \ref section_hal_impl_pwm_compl_pins.<br>
* If supplied, this must be connected to the same PWM instance as <b>pin</b>, see
* \ref section_hal_impl_pwm_compl_pins.<br>
* If this output is not needed, use \ref NC (No Connect).
* @param[in] pwm_alignment PWM alignment: left, right, or center.
* @param[in] continuous PWM run type: continuous (true) or one shot (false).
@ -229,6 +248,48 @@ void cyhal_pwm_register_callback(cyhal_pwm_t *obj, cyhal_pwm_event_callback_t ca
*/
void cyhal_pwm_enable_event(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intr_priority, bool enable);
/** Connects a source signal and configures and enables a PWM event to be
* triggered from that signal. These PWM events can be configured
* independently and connect to the same or different source signals.
*
* @param[in] obj PWM obj
* @param[in] source Source signal obtained from another driver's cyhal_<PERIPH>_enable_output
* @param[in] signal The PWM input signal
* @param[in] type The PWM input signal edge type
* @return The status of the connection
* */
cy_rslt_t cyhal_pwm_connect_digital(cyhal_pwm_t *obj, cyhal_source_t source, cyhal_pwm_input_t signal, cyhal_edge_type_t type);
/** Enables the specified output signal from a PWM that will be triggered
* when the corresponding event occurs. Multiple output signals can be
* configured simultaneously.
*
* @param[in] obj PWM obj
* @param[in] signal The PWM output signal
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. \p source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t cyhal_pwm_enable_output(cyhal_pwm_t *obj, cyhal_pwm_output_t signal, cyhal_source_t *source);
/** Disconnects a source signal and disables the PWM event.
*
* @param[in] obj PWM obj
* @param[in] source Source signal from cyhal_<PERIPH>_enable_output to disable
* @param[in] signal The PWM input signal
* @return The status of the disconnection
* */
cy_rslt_t cyhal_pwm_disconnect_digital(cyhal_pwm_t *obj, cyhal_source_t source, cyhal_pwm_input_t signal);
/** Disables the specified output signal from a PWM.
*
* @param[in] obj PWM obj
* @param[in] signal The PWM output signal
* @return The status of the output disable
* */
cy_rslt_t cyhal_pwm_disable_output(cyhal_pwm_t *obj, cyhal_pwm_output_t signal);
#if defined(__cplusplus)
}
#endif

14
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2019-2020 Cypress Semiconductor Corporation
* Copyright 2019-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -32,6 +32,18 @@
extern "C" {
#endif /* __cplusplus */
/** \addtogroup group_hal_impl_pwm PWM
* \ingroup group_hal_impl
* \{
* \section group_hal_impl_pwm_interconnect Interconnect
* In PSoC PWM channels can configure multiple input and output triggers
* simultaneously. 1 or more input triggers can be configured to initiate
* different PWM actions (e.g start, stop, reload, etc) with configurable edge
* detection on that incoming signal. Output triggers are based on certain
* events (e.g overflow, cc_match, etc).
* Note: The line_out output trigger is only available for TCPWMv2.
* \} group_hal_impl_pwm */
__STATIC_INLINE uint32_t _cyhal_pwm_convert_event(cyhal_pwm_event_t event)
{
uint32_t pdl_event = 0U;

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -51,20 +51,20 @@
* any given flash command. The cyhal_qspi_command_t.mode_bits structure has several other components which should
* be set as per the command. Mode bits are not required for single SPI read command, hence, mode_bits.disabled
* is set to TRUE in the below example code.
* \snippet qspi.c snippet_cyhal_qspi_structure_initialisation
* \snippet hal_qspi.c snippet_cyhal_qspi_structure_initialisation
* \subsection subsection_qspi_snippet_2 Code Snippet 2: QSPI initialization and Reading Flash memory
* This example function demonstrates the initialization of the QSPI component and use of the cyhal_qspi_read() function
* to complete the read operation and receive the read data in a buffer.
* \snippet qspi.c snippet_cyhal_qspi_read
* \snippet hal_qspi.c snippet_cyhal_qspi_read
* \subsection subsection_qspi_snippet_3 Code Snippet 3: Erasing Flash memory
* The following code snippet demonstrates the use of cyhal_qspi_transfer() API for sending single byte instruction
* that may or may not need any address or data bytes. It also shows the usage of status register read command within
* a while loop to poll the WIP bit status.
* \snippet qspi.c snippet_cyhal_qspi_erase
* \snippet hal_qspi.c snippet_cyhal_qspi_erase
* \note Flash memories need erase operation before programming.
* \subsection subsection_qspi_snippet_4 Code Snippet 4: Programming Flash memory
* This code snippet demonstrates the usage cyhal_qspi_write() API for executing program operation on flash memory.
* \snippet qspi.c snippet_cyhal_qspi_program
* \snippet hal_qspi.c snippet_cyhal_qspi_program
*/
#pragma once
@ -217,7 +217,7 @@ cy_rslt_t cyhal_qspi_set_frequency(cyhal_qspi_t *obj, uint32_t hz);
/** Get the actual frequency that QSPI is configured for
*
* @param[in] obj The QSPI object to configure
* @param[in] obj The QSPI object
* @return Frequency in Hz
*/
uint32_t cyhal_qspi_get_frequency(cyhal_qspi_t *obj);

327
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_quaddec.h Executable file
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@ -0,0 +1,327 @@
/***************************************************************************//**
* \file cyhal_quaddec.h
*
* \brief
* Provides a high level interface for interacting with the Quadrature Decoder.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2020-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_quaddec Quadrature Decoder
* \ingroup group_hal
* \{
* High level interface for interacting with the Quadrature Decoder hardware resource.
*
* The quadrature decoder block is commonly used to measure the time of occurrence of an event,
* to measure the time difference between two events or perform an action after a specified
* period of time.
*
* The Quadrature Decoder block provides the ability to count transitions on a pair of digital
* signals. The signals are typically provided by a speed/position feedback system mounted on
* a motor or trackball. The driver allows the user to invoke a callback function when a
* particular event occurs.
* The signals, typically called A and B, are positioned 90° out-of-phase, which results in a Gray
* code output (a sequence where only one bit changes on each count). It also allows detection of
* direction and relative position. A third optional signal, named index, is used as a reference
* to establish an absolute position once per rotation.
*
* The Quadrature Decoder operates in one of three resolution modes. (see \ref
* cyhal_quaddec_resolution_t) The mode dictates the number of events that are counted.
*
* \image html quadrature_mode.png
*
* An index event causes the counter to be set to the midpoint. For example, if the hardware
* has 16-bit resolution, the midpoint would be 0x8000. For 32-bit resolution: 0x80000000.
*
* \image html quadrature_index.png
*
* For more details about this functionality, see the "Quadrature Decoder Mode" section of the
* Technical Reference Manual.
*
* Some use case scenarios of the Quadrature Decoder:
*
* * Decode the output of a quadrature encoder (e.g., mouse, trackball, robotic axles, etc.).
* * Precision measurement of speed, acceleration, and position of a motor's rotor and with rotary
* knobs to determine user input.
*
* \section subsection_quaddec_features Features
* * Configurable resolution - \ref cyhal_quaddec_resolution_t
* * Interrupt on various events - \ref cyhal_quaddec_event_t
*
* \section subsection_quaddec_quickstart Quick Start
*
* \ref cyhal_quaddec_init can be used for quadrature decoder initialization by providing the quaddec
* object - \ref cyhal_quaddec_t, input pins, and shared clock source - <b> clk </b> (optional).
*
*
* See \ref subsection_quaddec_snippet_1.
*
* \section subsection_quaddec_sample_snippets Code Snippets
*
* \subsection subsection_quaddec_snippet_1 Snippet 1: Initialization and direction detection
* The following snippet initializes a quadrature decoder and measures the counter to determine direction.
* The <b>clk</b> may be left NULL, in which case a clock resource is automatically assigned.
* \snippet hal_quaddec.c snippet_cyhal_quaddec_direction
*
* \subsection subsection_quaddec_snippet_2 Snippet 2: Handling an event in a callback function
* The following snippet initializes a quadrature decoder and triggers an event as changes happen.
* The <b>clk</b> need not be provided (NULL), in which case a clock resource is assigned.
* \snippet hal_quaddec.c snippet_cyhal_quaddec_event_interrupt
*
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/** \addtogroup group_hal_results_quaddec Quadrature Decoder HAL Results
* Quadrature Decoder specific return codes
* \ingroup group_hal_results
* \{ *//**
*/
/** Bad argument. eg: null pointer */
#define CYHAL_QUADDEC_RSLT_ERR_BAD_ARGUMENT \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QUADDEC, 0))
/** Failed to initialize the quadrature decoder clock */
#define CYHAL_QUADDEC_RSLT_ERR_CLOCK_INIT \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QUADDEC, 1))
/** The function is not supported with a particular device */
#define CYHAL_QUADDEC_RSLT_ERR_NOT_SUPPORTED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QUADDEC, 2))
/**
* \}
*/
/*******************************************************************************
* Enumerations
*******************************************************************************/
/** Operating resolutions for the quadrature decoder */
typedef enum
{
CYHAL_QUADDEC_RESOLUTION_1X, //!< 1x resolution
CYHAL_QUADDEC_RESOLUTION_2X, //!< 2x resolution
CYHAL_QUADDEC_RESOLUTION_4X //!< 4x resolution
} cyhal_quaddec_resolution_t;
/** Quadrature decoder input signal */
typedef enum
{
CYHAL_QUADDEC_INPUT_PHI_A, //!< The "A" input of the quadrature decoder.
CYHAL_QUADDEC_INPUT_PHI_B, //!< The "B" input of the quadrature decoder.
CYHAL_QUADDEC_INPUT_STOP, //!< Stops the counter from counting when activated.
CYHAL_QUADDEC_INPUT_INDEX //!< A reference signal that resets the counter when activated.
} cyhal_quaddec_input_t;
/** Quadrature decoder output signal */
typedef enum
{
CYHAL_QUADDEC_OUTPUT_COMPARE_MATCH //!< Compare Match signal
} cyhal_quaddec_output_t;
/** Interrupt triggers for the quadrature decoder */
typedef enum
{
CYHAL_QUADDEC_IRQ_NONE = 0, //!< No interrupt handled
CYHAL_QUADDEC_IRQ_TERMINAL_COUNT = (1 << 0), //!< Interrupt when terminal count is reached
CYHAL_QUADDEC_IRQ_CAPTURE = (1 << 1), //!< Interrupt when capture value is reached
CYHAL_QUADDEC_IRQ_ALL = (1 << 2) - 1 //!< Interrupt on any event
} cyhal_quaddec_event_t;
/*******************************************************************************
* Typedefs
*******************************************************************************/
/** Handler for quadrature decoder events */
typedef void(*cyhal_quaddec_event_callback_t)(void *callback_arg, cyhal_quaddec_event_t event);
/*******************************************************************************
* Functions
*******************************************************************************/
/** Initialize the quadrature decoder peripheral and configure the pin. <br>
* See \ref subsection_quaddec_snippet_1.
*
* @param[out] obj Pointer to a quadrature decoder object. The caller must allocate the memory
* for this object but the init function will initialize its contents.
* @param[in] phi_a - The "A" input of the quadrature decoder.
* @param[in] phi_b - The "B" input of the quadrature decoder.
* @param[in] index - Optional, resets the counter when active to act as a reference position
* for the quadrature decoder.
* @param[in] resolution - The resolution that the quadrature decoder runs at
* @param[in] clk - Optional, the shared clock to use, if not provided a new clock will be
* allocated and the quadrature decoder frequency will be set to the value passed
* in with the frequency parameter.
* @param[in] frequency - This is the frequency, in hertz, to use with the clock allocated by this
* function. This parameter is only used if the clk parameter is set to NULL.
* When the clk parameter is not NULL, this must be set to zero. When the clk
* paramether is NULL, this must be set to something other than zero.
* @return The status of the init request
*/
cy_rslt_t cyhal_quaddec_init(cyhal_quaddec_t *obj, cyhal_gpio_t phi_a, cyhal_gpio_t phi_b,
cyhal_gpio_t index, cyhal_quaddec_resolution_t resolution,
const cyhal_clock_t *clk, uint32_t frequency);
/** Deinitialize the quadrature decoder object
*
* @param[in,out] obj The quadrature decoder object
*/
void cyhal_quaddec_free(cyhal_quaddec_t *obj);
/** Starts the quadrature decoder. This function also acts as a reset, in that it will trigger
* reload/index the QuadDec. When this function is called, the count value gets stored in the
* capture register and the count value is returned to the mid point. For example, if the hardware
* has 16-bit resolution, the midpoint would be 0x8000. For 32-bit resolution: 0x80000000.
* See \ref subsection_quaddec_snippet_1.
*
* @param[in] obj The quadrature decoder object
* @return The status of the start request
*/
cy_rslt_t cyhal_quaddec_start(cyhal_quaddec_t *obj);
/** Stops the quadrature decoder. Does not reset counter value. <br>
*
* @param[in] obj The quadrature decoder object
* @return The status of the stop request
*/
cy_rslt_t cyhal_quaddec_stop(cyhal_quaddec_t *obj);
/** Gets the change in the quadrature decoder counter, either positive or negative, since the last
* time that this function was called.
*
* \note This function is not intended for applications requiring high speed or high accuracy such
* as getting motor positions. It is intended for applications involving devices like radial dials.
*
* @param[in] obj The quadrature decoder object
* @return The amount that the counter has changed
*/
int32_t cyhal_quaddec_get_delta(cyhal_quaddec_t *obj);
/** Reads the current value from the quadrature decoder <br>
* The read operation works even if the counter is stopped.
* See \ref subsection_quaddec_snippet_1.
*
* @param[in] obj The quadrature decoder object
* @return The current value of the quadrature decoder counter register
*/
uint32_t cyhal_quaddec_read_counter(const cyhal_quaddec_t *obj);
/** Reads the value from the quadrature decoder's capture register <br>
* This function does not clear the counter value. The capture register
* is updated whenever there is an index event.
*
* @param[in] obj The quadrature decoder object
* @return The current value of the quadrature decoder capture register
*/
uint32_t cyhal_quaddec_read_capture(const cyhal_quaddec_t *obj);
/** Register a quadrature decoder callback handler<br>
* This function does not clear the counter value.
*
* This function will be called when one of the events enabled by \ref cyhal_quaddec_enable_event
* occurs.
*
* See \ref subsection_quaddec_snippet_2.
*
* @param[in] obj The quadrature decoder object
* @param[in] callback The callback handler which will be invoked when the event occurs
* @param[in] callback_arg Generic argument that will be provided to the callback when called
*/
void cyhal_quaddec_register_callback(cyhal_quaddec_t *obj, cyhal_quaddec_event_callback_t callback,
void *callback_arg);
/** Configure quadrature decoder event enable <br>
*
* When an enabled event occurs, the function specified by \ref cyhal_quaddec_register_callback
* will be called.
*
* See \ref subsection_quaddec_snippet_2.
*
* @param[in] obj The quadrature decoder object
* @param[in] event The quadrature decoder event type
* @param[in] intr_priority The priority for NVIC interrupt events
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_quaddec_enable_event(cyhal_quaddec_t *obj, cyhal_quaddec_event_t event,
uint8_t intr_priority, bool enable);
/** Connects a source signal and configures and enables a quadrature decoder
* event to be triggered from that signal. These quadrature decoder events can
* be configured independently and connect to the same or different source
* signals.
*
* @param[in] obj Quadrature decoder obj
* @param[in] source Source signal obtained from another driver's cyhal_<PERIPH>_enable_output
* @param[in] signal The quadrature decoder input signal
* @return The status of the connection
* */
cy_rslt_t cyhal_quaddec_connect_digital(cyhal_quaddec_t *obj, cyhal_source_t source, cyhal_quaddec_input_t signal);
/** Disconnects a source signal and disables the quadrature decoder event.
*
* @param[in] obj Quadrature decoder obj
* @param[in] source Source signal from cyhal_<PERIPH>_enable_output to disable
* @param[in] signal The quadrature decoder input signal
* @return The status of the disconnection
* */
cy_rslt_t cyhal_quaddec_disconnect_digital(cyhal_quaddec_t *obj, cyhal_source_t source, cyhal_quaddec_input_t signal);
/** Enables the specified output signal from a quadrature decoder that will be
* triggered when the corresponding event occurs. Multiple output signals can
* be configured simultaneously.
*
* @param[in] obj Quadrature decoder obj
* @param[in] signal The quadrature decoder output signal
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. \p source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t cyhal_quaddec_enable_output(cyhal_quaddec_t *obj, cyhal_quaddec_output_t signal, cyhal_source_t *source);
/** Disables the specified output signal from a quadrature decoder.
*
* @param[in] obj Quadrature decoder obj
* @param[in] signal The quadrature decoder output signal
* @return The status of the output disable
* */
cy_rslt_t cyhal_quaddec_disable_output(cyhal_quaddec_t *obj, cyhal_quaddec_output_t signal);
#if defined(__cplusplus)
}
#endif
#ifdef CYHAL_QUADDEC_IMPL_HEADER
#include CYHAL_QUADDEC_IMPL_HEADER
#endif /* CYHAL_QUADDEC_IMPL_HEADER */
/** \} group_hal_quaddec */

87
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_quaddec_impl.h Executable file
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@ -0,0 +1,87 @@
/***************************************************************************//**
* \file cyhal_quaddec_impl.h
*
* Description:
* Provides a high level interface for interacting with the Cypress PWM.
*
********************************************************************************
* \copyright
* Copyright 2019-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cyhal_tcpwm_common.h"
#if defined(CY_IP_MXTCPWM_INSTANCES) || defined(CY_IP_M0S8TCPWM_INSTANCES)
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/** \addtogroup group_hal_impl_quaddec Quadrature Decoder
* \ingroup group_hal_impl
* \{
* \section group_hal_impl_quaddec_interconnect Interconnect
* In PSoC Quadrature Decoder channels can configure multiple input and output
* triggers simultaneously. 1 or more input triggers can be configured to
* initiate different PWM actions (e.g start, stop, reload, etc) with
* configurable edge detection on that incoming signal. Output triggers are
* based on certain events (e.g overflow, cc_match, etc).
* \} group_hal_impl_quaddec */
__STATIC_INLINE uint32_t _cyhal_quaddec_convert_event(cyhal_quaddec_event_t event)
{
uint32_t pdl_event = 0U;
if (event & CYHAL_QUADDEC_IRQ_TERMINAL_COUNT)
{
pdl_event |= CY_TCPWM_INT_ON_TC;
}
if (event & CYHAL_QUADDEC_IRQ_CAPTURE)
{
pdl_event |= CY_TCPWM_INT_ON_CC;
}
return pdl_event;
}
__STATIC_INLINE void _cyhal_quaddec_register_callback(cyhal_quaddec_t *obj,
cyhal_quaddec_event_callback_t callback,
void *callback_arg)
{
_cyhal_tcpwm_register_callback(&obj->tcpwm.resource, (cy_israddress) callback, callback_arg);
}
#define cyhal_quaddec_register_callback(obj, callback, callback_arg) \
_cyhal_quaddec_register_callback(obj, callback, callback_arg)
__STATIC_INLINE void _cyhal_quaddec_enable_event(cyhal_quaddec_t *obj,
cyhal_quaddec_event_t event,
uint8_t intr_priority,
bool enable)
{
uint32_t converted = _cyhal_quaddec_convert_event(event);
_cyhal_tcpwm_enable_event(obj->tcpwm.base, &obj->tcpwm.resource, converted, intr_priority,
enable);
}
#define cyhal_quaddec_enable_event(obj, event, intr_priority, enable) \
_cyhal_quaddec_enable_event(obj, event, intr_priority, enable)
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* defined(CY_IP_MXTCPWM_INSTANCES) */

22
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -37,6 +37,7 @@
* \section section_rtc_features Features
* * Configurable interrupt and callback assignment on RTC event \ref cyhal_rtc_event_t
* * Set alarm for a specific time and date \ref cyhal_rtc_set_alarm
* * Daylight Savings Time adjustment
*
* \section section_rtc_quickstart Quick Start
*
@ -49,13 +50,12 @@
* The following code snippet initialises the RTC using the \ref cyhal_rtc_init. The current date and time are set using \ref cyhal_rtc_write.
* The current date and time is read from the RTC using \ref cyhal_rtc_read. The time structure <b> tm </b>, contains the calendar date and time which
* are broken down into its components. This structure is declared in standard C library time.h which is included by HAL.
* \snippet rtc.c snippet_cyhal_rtc_read_write_data_time
* \snippet hal_rtc.c snippet_cyhal_rtc_read_write_data_time
*
* \subsection subsection_rtc_snippet_2 Snippet 2: RTC Alarm using Callbacks
* The following code snippet configures the RTC to trigger an alarm event on a specified date and time using \ref cyhal_rtc_set_alarm.
* A callback is registered to handle the alarm event using \ref cyhal_rtc_register_callback.
* \snippet rtc.c snippet_cyhal_set_alarm_callback
* \snippet hal_rtc.c snippet_cyhal_set_alarm_callback
*/
#pragma once
@ -103,11 +103,17 @@ typedef struct
uint8_t en_month : 1; /**< Enable match of month */
} cyhal_alarm_active_t;
/** Enumeration used to configure the DST format */
/** Enumeration used to configure the DST format
*
* \note In areas of the world that practice DST, when it should begin and end is not unique. It
* can either be in fixed DST format or in relative DST format.
*/
typedef enum
{
CYHAL_RTC_DST_RELATIVE, /**< Relative DST format */
CYHAL_RTC_DST_FIXED /**< Fixed DST format */
CYHAL_RTC_DST_RELATIVE, /**< Relative DST format. eg: Begins on the last Sunday of March
and ends on the last Sunday of October. */
CYHAL_RTC_DST_FIXED /**< Fixed DST format. eg: Begins on 21st March
and ends on 21st September. */
} cyhal_rtc_dst_format_t;
/**
@ -138,7 +144,7 @@ typedef void (*cyhal_rtc_event_callback_t)(void *callback_arg, cyhal_rtc_event_t
/** Initialize the RTC peripheral
*
* Powerup the RTC in preparation for access. This function must be called
* Power up the RTC in preparation for access. This function must be called
* before any other RTC functions are called. This does not change the state
* of the RTC. It just enables access to it.
* NOTE: Before calling this, make sure all necessary System Clocks are setup

66
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -51,6 +51,34 @@ extern "C" {
#define _SCB_ARRAY_SIZE (CY_IP_M0S8SCB_INSTANCES)
#endif /* CY_IP_MXSCB_INSTANCES */
/** \addtogroup group_hal_results_scb SCB HAL Results
* SCB specific return codes
* \ingroup group_hal_results
* \{ *//**
*/
/** Bad argument */
#define CYHAL_SCB_RSLT_ERR_BAD_ARGUMENT \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_IMPL_SCB, 0))
/**
* \}
*/
/** SCB FIFO type */
typedef enum
{
CYHAL_SCB_FIFO_RX, //!< Set RX FIFO level
CYHAL_SCB_FIFO_TX, //!< Set TX FIFO level
} cyhal_scb_fifo_type_t;
/** Enum of possible output signals from an SCB */
typedef enum
{
CYHAL_SCB_OUTPUT_TRIGGER_RX_FIFO_LEVEL_REACHED, //!< Output the RX FIFO signal which is triggered when the receive FIFO has more entries than the configured level.
CYHAL_SCB_OUTPUT_TRIGGER_TX_FIFO_LEVEL_REACHED, //!< Output the TX FIFO signal which is triggered when the transmit FIFO has less entries than the configured level.
} cyhal_scb_output_t;
/** The start address of the SCB blocks */
extern CySCB_Type* const _CYHAL_SCB_BASE_ADDRESSES[_SCB_ARRAY_SIZE];
/** The interrupt number of the SCB blocks. */
@ -86,9 +114,43 @@ uint32_t _cyhal_i2c_set_peri_divider(CySCB_Type *base, uint32_t block_num, cyhal
* @param count Number of entries in pin_map
* @return Pin map pointer or NULL if none found
*/
const cyhal_resource_pin_mapping_t* _cyhal_scb_find_map(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pin_map,
const cyhal_resource_pin_mapping_t* _cyhal_scb_find_map(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pin_map,
size_t count, const cyhal_resource_inst_t *block_res);
/** Sets a threshold level for a FIFO that will generate an interrupt and a
* trigger output. The RX FIFO interrupt and trigger will be activated when
* the receive FIFO has more entries than the threshold. The TX FIFO interrupt
* and trigger will be activated when the transmit FIFO has less entries than
* the threshold.
*
* @param[in] base SCB base
* @param[in] type FIFO type to set level for
* @param[in] level Level threshold to set
* @return The status of the level set
* */
cy_rslt_t _cyhal_scb_set_fifo_level(CySCB_Type *base, cyhal_scb_fifo_type_t type, uint16_t level);
/** Enables the specified output signal from an scb.
*
* @param[in] base SCB base
* @param[in] resource SCB resource
* @param[in] output Which output signal to enable
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t _cyhal_scb_enable_output(CySCB_Type *base, cyhal_resource_inst_t resource, cyhal_scb_output_t output, cyhal_source_t *source);
/** Disables the specified output signal from an scb
*
* @param[in] base SCB base
* @param[in] resource SCB resource
* @param[in] output Which output signal to disable
* @return The status of the output disable
* */
cy_rslt_t _cyhal_scb_disable_output(CySCB_Type *base, cyhal_resource_inst_t resource, cyhal_scb_output_t output);
#define _CYHAL_SCB_FIND_MAP(pin, pin_map) \
_cyhal_scb_find_map(pin, pin_map, sizeof(pin_map)/sizeof(cyhal_resource_pin_mapping_t), NULL)
#define _CYHAL_SCB_FIND_MAP_BLOCK(pin, pin_map, block) \

566
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h Normal file → Executable file
View File

@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -50,20 +50,15 @@
* The following snippet is used to initialize the SDHC block. SDHC object - \ref cyhal_sdhc_t,
* SDHC card configuration structure (const \ref cyhal_sdhc_config_t * config). The pins connected to the SDHC block
* needs to be provided to the \ref cyhal_sdhc_init function.
* \snippet sdhc.c snippet_cyhal_sdhc_init
* \snippet hal_sdhc.c snippet_cyhal_sdhc_init
*
* \subsection subsection_sdhc_snippet_2 Snippet 2: SDHC Initialization and configuration with custom card detect pin
* The following snippet is used to initialize the SDHC block with a custom card detect pin. Cy_SD_Host_IsCardConnected()
* function needs to be over-ridden depending on the card detect pin selected.
* \snippet sdhc.c snippet_cyhal_sdhc_init_custom_card_detect
*
* \subsection subsection_sdhc_snippet_3 Snippet 3: Reading a block of data from an SD Card
* \subsection subsection_sdhc_snippet_2 Snippet 2: Reading a block of data from an SD Card
* The following snippet reads a block of data from the SD Card.
* \snippet sdhc.c snippet_cyhal_sdhc_read
* \snippet hal_sdhc.c snippet_cyhal_sdhc_read
* \subsection subsection_sdhc_snippet_4 Snippet 4: Writing a block of data to an SD Card
* \subsection subsection_sdhc_snippet_3 Snippet 3: Writing a block of data to an SD Card
* The following snippet writes a block of data to the SD Card.
* \snippet sdhc.c snippet_cyhal_sdhc_write
* \snippet hal_sdhc.c snippet_cyhal_sdhc_write
*/
@ -88,18 +83,35 @@ extern "C" {
* \{ *//**
*/
/**< Pin related Error. >*/
/** Pin related Error. */
#define CYHAL_SDHC_RSLT_ERR_PIN \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 0))
/** Requested feature is not supported on this hardware. */
#define CYHAL_SDHC_RSLT_ERR_UNSUPPORTED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 1))
/** Timeout during waiting for erase complete. */
#define CYHAL_SDHC_RSLT_ERR_ERASE_CMPLT_TIMEOUT \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 2))
/** Block count cannot be retrieved. */
#define CYHAL_SDHC_RSLT_ERR_BLOCK_COUNT_GET_FAILURE \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 3))
/** Cannot set desired SD bus frequency. */
#define CYHAL_SDHC_RSLT_ERR_SET_FREQ \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 4))
/** Incorrect function parameter. */
#define CYHAL_SDHC_RSLT_ERR_WRONG_PARAM \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 5))
/** Error occured during I/O voltage switch sequence. */
#define CYHAL_SDHC_RSLT_ERR_IO_VOLT_SWITCH_SEQ \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 6))
/** Cannot configure data timeout. */
#define CYHAL_SDHC_RSLT_ERR_TOUT_CFG \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 7))
/**
* \}
*/
/*******************************************************************************
* Enumerations
*******************************************************************************/
@ -107,37 +119,134 @@ extern "C" {
/** Card types */
typedef enum
{
CYHAL_SDHC_SD, //!< Secure Digital card
CYHAL_SDHC_SDIO, //!< SD Input Output card
CYHAL_SDHC_EMMC, //!< Embedded Multimedia card
CYHAL_SDHC_COMBO, //!< Combo Card (SD + SDIO)
CYHAL_SDHC_UNUSABLE, //!< Unusable card or unsupported type
CYHAL_SDHC_NOT_EMMC, //!< Not an eMMC card
CYHAL_SDHC_SD, //!< Secure Digital card
CYHAL_SDHC_SDIO, //!< SD Input Output card
CYHAL_SDHC_EMMC, //!< Embedded Multimedia card
CYHAL_SDHC_COMBO, //!< Combo Card (SD + SDIO)
CYHAL_SDHC_UNUSABLE, //!< Unusable card or unsupported type
CYHAL_SDHC_NOT_EMMC, //!< Not an eMMC card
} cyhal_sdhc_card_type_t;
/** SDHC interrupt triggers */
typedef enum {
CYHAL_SDHC_CMD_COMPLETE = 0x00001, //!> Command Complete
CYHAL_SDHC_XFER_COMPLETE = 0x00002, //!> Host read/write transfer is complete
CYHAL_SDHC_BGAP_EVENT = 0x00004, //!> This bit is set when both read/write transaction is stopped at the block gap
CYHAL_SDHC_DMA_INTERRUPT = 0x00008, //!> Host controller detects an SDMA Buffer Boundary during transfer
CYHAL_SDHC_BUF_WR_READY = 0x00010, //!> This bit is set if the Buffer Write Enable changes from 0 to 1
CYHAL_SDHC_BUF_RD_READY = 0x00020, //!> This bit is set if the Buffer Read Enable changes from 0 to 1
CYHAL_SDHC_CARD_INSERTION = 0x00040, //!> This bit is set if the Card Inserted in the Present State register changes from 0 to 1.
CYHAL_SDHC_CARD_REMOVAL = 0x00080, //!> This bit is set if the Card Inserted in the Present State register changes from 1 to 0.
CYHAL_SDHC_CARD_INTERRUPT = 0x00100, //!> The synchronized value of the DAT[1] interrupt input for SD mode
CYHAL_SDHC_CMD_COMPLETE = 0x00001, //!< Command Complete
CYHAL_SDHC_XFER_COMPLETE = 0x00002, //!< Host read/write transfer is complete
CYHAL_SDHC_BGAP_EVENT = 0x00004, //!< This bit is set when both read/write transaction is stopped at the block gap
CYHAL_SDHC_DMA_INTERRUPT = 0x00008, //!< Host controller detects an SDMA Buffer Boundary during transfer
CYHAL_SDHC_BUF_WR_READY = 0x00010, //!< This bit is set if the Buffer Write Enable changes from 0 to 1
CYHAL_SDHC_BUF_RD_READY = 0x00020, //!< This bit is set if the Buffer Read Enable changes from 0 to 1
CYHAL_SDHC_CARD_INSERTION = 0x00040, //!< This bit is set if the Card Inserted in the Present State register changes from 0 to 1.
CYHAL_SDHC_CARD_REMOVAL = 0x00080, //!< This bit is set if the Card Inserted in the Present State register changes from 1 to 0.
CYHAL_SDHC_INT_A = 0x00200,
CYHAL_SDHC_INT_B = 0x00400,
CYHAL_SDHC_INT_C = 0x00800,
CYHAL_SDHC_RE_TUNE_EVENT = 0x01000, //!> This bit is set if the Re-Tuning Request changes from 0 to 1
CYHAL_SDHC_FX_EVENT = 0x02000, //!> This status is set when R[14] of response register is set to 1
CYHAL_SDHC_CQE_EVENT = 0x04000, //!> This status is set if Command Queuing/Crypto event has occurred
CYHAL_SDHC_ASYNC_READ_COMPLETE = 0x10000, //!> Asynchronous read operation is complete
CYHAL_SDHC_ASYNC_WRITE_COMPLETE = 0x20000, //!> Asynchronous write operation is complete
CYHAL_SDHC_ERR_INTERRUPT = 0x08000, //!> If any of the bits in the Error Interrupt Status register are set
CYHAL_SDHC_ALL_INTERRUPTS = 0x3FFFF, //!> Is used to enable/disable all interrupts
CYHAL_SDHC_RE_TUNE_EVENT = 0x01000, //!< This bit is set if the Re-Tuning Request changes from 0 to 1
CYHAL_SDHC_FX_EVENT = 0x02000, //!< This status is set when R[14] of response register is set to 1
CYHAL_SDHC_CQE_EVENT = 0x04000, //!< This status is set if Command Queuing/Crypto event has occurred
CYHAL_SDHC_ERR_INTERRUPT = 0x08000, //!< If any of the bits in the Error Interrupt Status register are set
CYHAL_SDHC_ALL_INTERRUPTS = 0x0FEFF, //!< Is used to enable/disable all interrupts
} cyhal_sdhc_event_t;
/** I/O voltage levels */
typedef enum
{
CYHAL_SDHC_IO_VOLTAGE_3_3V, //!< I/O voltage is 3.3V.
CYHAL_SDHC_IO_VOLTAGE_1_8V //!< I/O voltage is 1.8V.
} cyhal_sdhc_io_voltage_t;
/** SDHC I/O voltage select principle */
typedef enum
{
CYHAL_SDHC_IO_VOLT_ACTION_NEGOTIATE = 0U, //!< (Recommended) HAL driver performs all steps, needed for switching I/O bus voltage to certain level: sends needed commands to prepare card, changes level of io_volt_sel pin and performs switching sequence according to SD specification.
CYHAL_SDHC_IO_VOLT_ACTION_SWITCH_SEQ_ONLY = 1U, //!< HAL driver performs switching sequence (if voltage is being switched to 1.8V) and changes io_volt_sel pin level accordingly. No commands are being send to the card in this mode.
CYHAL_SDHC_IO_VOLT_ACTION_NONE = 2U, //!< I/O voltage is changed by changing io_volt_sel pin's level. No commands are being send to the card in this mode.
} cyhal_sdhc_io_volt_action_type_t;
/** SDHC response types */
typedef enum
{
CYHAL_SDHC_RESPONSE_NONE = 0U, //!< No Response.
CYHAL_SDHC_RESPONSE_LEN_136 = 1U, //!< Response Length 136.
CYHAL_SDHC_RESPONSE_LEN_48 = 2U, //!< Response Length 48.
CYHAL_SDHC_RESPONSE_LEN_48B = 3U //!< Response Length 48. Check Busy after response.
} cyhal_sdhc_cmd_response_type_t;
/** SDHC auto command enable selection. */
typedef enum
{
CYHAL_SDHC_AUTO_CMD_NONE = 0U, //!< Auto command disable.
CYHAL_SDHC_AUTO_CMD_12 = 1U, //!< Auto command 12 enable.
CYHAL_SDHC_AUTO_CMD_23 = 2U, //!< Auto command 23 enable.
CYHAL_SDHC_AUTO_CMD_AUTO = 3U //!< Auto command Auto enable.
} cyhal_sdhc_auto_cmd_t;
/** SDHC command types */
typedef enum
{
CYHAL_SDHC_CMD_NORMAL = 0U, //!< Other commands.
CYHAL_SDHC_CMD_SUSPEND = 1U, //!< CMD52 for writing "Bus Suspend" in CCCR.
CYHAL_SDHC_CMD_RESUME = 2U, //!< CMD52 for writing "Function Select" in CCCR.
CYHAL_SDHC_CMD_ABORT = 3U //!< CMD12, CMD52 for writing "I/O Abort" in CCCR.
} cyhal_sdhc_cmd_type_t;
/** SDHC command error states */
typedef enum
{
/** Last operation did not cause any error status. */
CYHAL_SDHC_NO_ERR = 0x0000U,
/** Command timeout error. In SD/eMMC Mode, this event is set only if no response is returned
* within 64 SD clock cycles from the end bit of the command. If the Host Controller detects a CMD line conflict,
* along with Command CRC Error bit, this event is set to 1, without waiting for 64 SD/eMMC card clock cycles. */
CYHAL_SDHC_CMD_TOUT_ERR = 0x0001U,
/** Command CRC error. A Command CRC Error is generated in SD/eMMC mode when:
* 1. A response is returned and the Command Timeout Error is set to 0 (indicating no timeout),
* this bit is set to 1 when detecting a CRC error in the command response.
* 2. The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. If
* the Host Controller drives the CMD line to level 1, but detects level 0 on the CMD line at the next SD clock
* edge, then the Host Controller aborts the command (stop driving CMD line) and sets this bit to 1. The Command
* Timeout Error is also set to 1 to distinguish a CMD line conflict. */
CYHAL_SDHC_CMD_CRC_ERR = 0x0002U,
/** Command End Bit error. This bit is set after detecting that the end bit of a command response is 0 in SD/eMMC mode. */
CYHAL_SDHC_CMD_END_BIT_ERR = 0x0004U,
/** Command Index error. This bit is set if a Command Index error occurs in the command response in SD/eMMC mode. */
CYHAL_SDHC_CMD_IDX_ERR = 0x0008U,
/** Data Timeout error. This bit is set in SD/eMMC mode when detecting one of the following timeout conditions:
* * Busy timeout for R1b, R5b type
* * Busy timeout after Write CRC status
* * Write CRC Status timeout
* * Read Data timeout. */
CYHAL_SDHC_DATA_TOUT_ERR = 0x0010U,
/** Data CRC error. This error occurs in SD/eMMC mode after detecting a CRC error while transferring read data
* that uses the DAT line, detecting the Write CRC status having a value other than 010 or when writing a CRC status timeout. */
CYHAL_SDHC_DATA_CRC_ERR = 0x0020U,
/** Data End Bit error. This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read
* data that uses the DAT line or at the end bit position of the CRC status. */
CYHAL_SDHC_DATA_END_BIT_ERR = 0x0040U,
/** Current Limit error. */
CYHAL_SDHC_CUR_LMT_ERR = 0x0080U,
/** Auto CMD error. This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. This bit is set after
* detecting that any of the bits D00 to D05 in the Auto CMD Error Status register has changed from 0 to 1. D07 is
* effective in case for Auto CMD12. The Auto CMD Error Status register is valid while this bit is set to 1 and may
* be cleared by clearing this bit. */
CYHAL_SDHC_AUTO_CMD_ERR = 0x0100U,
/** ADMA error. This bit is set when the Host Controller detects an error during an ADMA-based data transfer.
* The possible reasons for an error:
* * An error response is received from the System bus;
* * ADMA3, ADMA2 Descriptors are invalid;
* * CQE Task or Transfer descriptors are invalid.
* When an error occurs, the state of the ADMA is saved in the ADMA Error Status register. */
CYHAL_SDHC_ADMA_ERR = 0x0200U,
/** Tuning error. */
CYHAL_SDHC_TUNNING_ERR = 0x0400U,
/** Response error. Host Controller Version 4.00 supports the response error check function to avoid overhead of
* the response error check by Host Driver during DMA execution. If the Response Error Check Enable is set to 1 in
* the Transfer Mode register, the Host Controller checks R1 or R5 response. If an error is detected in a response,
* this bit is set to 1. This is applicable in SD/eMMC mode. */
CYHAL_SDHC_RESP_ERR = 0x0800U,
/** Boot Acknowledgement error. This bit is set when there is a timeout for boot acknowledgement or after detecting
* the boot ACK status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. */
CYHAL_SDHC_BOOT_ACK_ERR = 0x1000U
} cyhal_sdhc_error_type_t;
/*******************************************************************************
* Typedefs
@ -150,41 +259,128 @@ typedef void (*cyhal_sdhc_event_callback_t)(void *callback_arg, cyhal_sdhc_event
* Data Structures
*******************************************************************************/
/** @brief Defines configuration options for the SDHC block */
/** Defines configuration options for the SDHC block */
typedef struct
{
bool enableLedControl; //!< Drive one IO to indicate when the card is being accessed
bool lowVoltageSignaling; //!< Whether 1.8V signaling is supported
bool isEmmc; //!< true if eMMC card, otherwise false
uint8_t busWidth; //!< The desired bus width
bool enableLedControl; //!< Drive one IO to indicate when the card is being accessed
bool lowVoltageSignaling; //!< Whether 1.8V signaling is supported
bool isEmmc; //!< true if eMMC card, otherwise false
uint8_t busWidth; //!< The desired bus width, 1-bit, 4-bit, 8-bit
} cyhal_sdhc_config_t;
/** Defines data configuration */
typedef struct
{
uint32_t* data_ptr; //!< The pointer to data for send/receive. Data will be transfered using DMA, which will be configured automaticaly by SDHC HAL driver.
uint32_t block_size; //!< The size of the data block.
uint32_t number_of_blocks; //!< The number of blocks with size block_size to send.
cyhal_sdhc_auto_cmd_t auto_command; //!< Selects which auto commands are used if any.
bool is_read; //!< true = Read from the card, false = Write to the card.
} cyhal_sdhc_data_config_t;
/** Defines command configuration for \ref cyhal_sdhc_send_cmd function */
typedef struct
{
uint32_t command_index; //!< The index of the command.
uint32_t command_argument; //!< The argument for the command.
bool enable_crc_check; //!< Enables the CRC check on the response.
cyhal_sdhc_cmd_response_type_t response_type; //!< The response type.
bool enable_idx_check; //!< Checks the index of the response.
cyhal_sdhc_cmd_type_t command_type; //!< The command type.
cyhal_sdhc_data_config_t *data_config; //!< Data transfer configuration, defined in \ref cyhal_sdhc_data_config_t. Should be NULL if data transfer is not expected for provided command.
} cyhal_sdhc_cmd_config_t;
/*******************************************************************************
* Functions
*******************************************************************************/
/** Initialize the SDHC peripheral
/** Initialize SDHC driver and corresponding hardware.
*
* @param[out] obj Pointer to an SDHC object.
* The caller must allocate the memory for this object but the init function will
* initialize its contents.
* @param[in] config The card configuration object
* @param[out] clk The pin connected to the clk signal
* @param[in] cmd The pin connected to the command signal
* @param[in] data0 The pin connected to the data0 signal
* @param[in] data1 The pin connected to the data1 signal
* @param[in] data2 The pin connected to the data2 signal
* @param[in] data3 The pin connected to the data3 signal
* @param[in] data4 The pin connected to the data4 signal
* @param[in] data5 The pin connected to the data5 signal
* @param[in] data6 The pin connected to the data6 signal
* @param[in] data7 The pin connected to the data7 signal
* @param[in] cardDetect The pin connected to the cardDetect signal
* @param[out] ioVoltSel The pin connected to the ioVoltSel signal
* @param[out] cardIfPwrEn The pin connected to the cardIfPwrEn signal
* @param[in] cardMechWriteProt The pin connected to the cardMechWriteProt signal
* @param[in] ledCtrl The pin connected to the ledCtrl signal
* @param[in] cardEmmcReset The pin connected to the cardEmmcReset signal
* @param[out] obj Pointer to an SDHC object. The caller must allocate the memory for this object but
* the init function will initialize its contents.
* @param[in] config The card configuration object
* @param[out] clk The pin connected to the clk signal
* @param[in] cmd The pin connected to the command signal
* @param[in] data0 The pin connected to the data0 signal
* @param[in] data1 The pin connected to the data1 signal. This pin can be NC if bus width is 1-bit.
* @param[in] data2 The pin connected to the data2 signal. This pin can be NC if bus width is 1-bit.
* @param[in] data3 The pin connected to the data3 signal. This pin can be NC if bus width is 1-bit.
* @param[in] data4 The pin connected to the data4 signal. This pin can be NC if bus width is less than 8-bit.
* @param[in] data5 The pin connected to the data5 signal. This pin can be NC if bus width is less than 8-bit.
* @param[in] data6 The pin connected to the data6 signal. This pin can be NC if bus width is less than 8-bit.
* @param[in] data7 The pin connected to the data7 signal. This pin can be NC if bus width is less than 8-bit.
* @param[in] card_detect The pin connected to the card_detect signal
* Card is considered as inserted if card_detect pin in low state.
* This pin can be NC.
* @param[out] io_volt_sel The pin connected to the io_volt_sel signal. This pin changes the logic level on the
* sd_io_volt_sel line. It assumes that this line is used to control a regulator connected to the VDDIO of the MCU.
* This regulator allows for switching between the 3.3V and 1.8V signaling. High level on the pin stands for
* 1.8V signaling, while low - for 3.3V.
* This pin can be NC.
* @param[out] card_pwr_en The pin connected to the card_pwr_en signal This pin can be used to enable a voltage
* regulator used to power the card. High level on the pin - card is powered. Low - card is not powered.
* This pin can be NC.
* @param[in] card_mech_write_prot The pin connected to the card_mech_write_prot signal This pin is used for card
* mechanical write protect checking.
* If pin in high state - card is mechanically write protected, if in low state - card is not mechanically write
* protected.
* \ref cyhal_sdhc_is_card_mech_write_protected function can be used to check card write protection state.
* This pin can be NC.
* @param[in] led_ctrl The pin connected to the led_ctrl signal. This pin can be NC.
* @param[in] emmc_reset The pin connected to the emmc_reset signal. This pin can be NC.
* @return The status of the init request
*
*/
cy_rslt_t cyhal_sdhc_init_hw(cyhal_sdhc_t *obj,
const cyhal_sdhc_config_t *config,
cyhal_gpio_t cmd,
cyhal_gpio_t clk,
cyhal_gpio_t data0,
cyhal_gpio_t data1,
cyhal_gpio_t data2,
cyhal_gpio_t data3,
cyhal_gpio_t data4,
cyhal_gpio_t data5,
cyhal_gpio_t data6,
cyhal_gpio_t data7,
cyhal_gpio_t card_detect,
cyhal_gpio_t io_volt_sel,
cyhal_gpio_t card_pwr_en,
cyhal_gpio_t card_mech_write_prot,
cyhal_gpio_t led_ctrl,
cyhal_gpio_t emmc_reset);
/** Initialize the connected card.
* \note This function should be called after \ref cyhal_sdhc_init_hw
*
* @param[in,out] obj The SDHC object
* @return The status of the card init request
*/
cy_rslt_t cyhal_sdhc_init_card(cyhal_sdhc_t *obj);
/** Initialize the SDHC block and connected card.
* This function is a combination of \ref cyhal_sdhc_init_hw and \ref cyhal_sdhc_init_card calls.
* \note refer to \ref cyhal_sdhc_init_hw function description for detailed parameter guidance.
*
* @param[out] obj Pointer to an SDHC object. The caller must allocate the memory for this object but
* the init function will initialize its contents.
* @param[in] config The card configuration object
* @param[out] clk The pin connected to the clk signal
* @param[in] cmd The pin connected to the command signal
* @param[in] data0 The pin connected to the data0 signal
* @param[in] data1 The pin connected to the data1 signal. This pin can be NC if bus width is 1-bit.
* @param[in] data2 The pin connected to the data2 signal. This pin can be NC if bus width is 1-bit.
* @param[in] data3 The pin connected to the data3 signal. This pin can be NC if bus width is 1-bit.
* @param[in] data4 The pin connected to the data4 signal. This pin can be NC if bus width is less than 8-bit.
* @param[in] data5 The pin connected to the data5 signal. This pin can be NC if bus width is less than 8-bit.
* @param[in] data6 The pin connected to the data6 signal. This pin can be NC if bus width is less than 8-bit.
* @param[in] data7 The pin connected to the data7 signal. This pin can be NC if bus width is less than 8-bit.
* @param[in] card_detect The pin connected to the card_detect signal
* @param[out] io_volt_sel The pin connected to the io_volt_sel signal
* @param[out] card_pwr_en The pin connected to the card_pwr_en signal
* @param[in] card_mech_write_prot The pin connected to the card_mech_write_prot signal
* @param[in] led_ctrl The pin connected to the led_ctrl signal
* @param[in] emmc_reset The pin connected to the emmc_reset signal
* @return The status of the init request
*
*/
@ -200,17 +396,17 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
cyhal_gpio_t data5,
cyhal_gpio_t data6,
cyhal_gpio_t data7,
cyhal_gpio_t cardDetect,
cyhal_gpio_t ioVoltSel,
cyhal_gpio_t cardIfPwrEn,
cyhal_gpio_t cardMechWriteProt,
cyhal_gpio_t ledCtrl,
cyhal_gpio_t cardEmmcReset);
cyhal_gpio_t card_detect,
cyhal_gpio_t io_volt_sel,
cyhal_gpio_t card_pwr_en,
cyhal_gpio_t card_mech_write_prot,
cyhal_gpio_t led_ctrl,
cyhal_gpio_t emmc_reset);
/** Release the SDHC peripheral, not currently invoked. It requires further
* resource management.
*
* @param[in,out] obj The SDHC object
* @param[in,out] obj The SDHC object
*/
void cyhal_sdhc_free(cyhal_sdhc_t *obj);
@ -220,12 +416,12 @@ void cyhal_sdhc_free(cyhal_sdhc_t *obj);
* pointed to by `data`, then return. The value pointed to by `length` will be
* updated to reflect the number of words that were actually read.
*
* See \ref subsection_sdhc_snippet_3
* See \ref subsection_sdhc_snippet_2
*
* @param[in] obj The SDHC object
* @param[in] address The address to read data from
* @param[out] data Pointer to the byte-array where data read from the device should be stored
* @param[in,out] length Number of 512 byte blocks to read, updated with the number actually read
* @param[in] obj The SDHC object
* @param[in] address The address to read data from
* @param[out] data Pointer to the byte-array where data read from the device should be stored
* @param[in,out] length Number of 512 byte blocks to read, updated with the number actually read
* @return The status of the read request
*/
cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *data, size_t *length);
@ -236,12 +432,12 @@ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *da
* The value pointed to by `length` will be updated to reflect the number of words
* that were actually read.
*
* See \ref subsection_sdhc_snippet_4
* See \ref subsection_sdhc_snippet_3
*
* @param[in] obj The SDHC object
* @param[in] address The address to write data to
* @param[in] data Pointer to the byte-array of data to write to the device
* @param[in,out] length Number of 512 byte blocks to write, updated with the number actually written
* @param[in] obj The SDHC object
* @param[in] address The address to write data to
* @param[in] data Pointer to the byte-array of data to write to the device
* @param[in,out] length Number of 512 byte blocks to write, updated with the number actually written
* @return The status of the write request
*
*/
@ -249,9 +445,9 @@ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint
/** Erases a block of data over the SDHC peripheral
*
* @param[in] obj The SDHC object
* @param[in] start_addr Is the address of the first byte to erase
* @param[in] length Number of 512 byte blocks (starting at start_addr) to erase
* @param[in] obj The SDHC object
* @param[in] start_addr Is the address of the first byte to erase
* @param[in] length Number of 512 byte blocks (starting at start_addr) to erase
* @return The status of the erase request
*
*/
@ -260,13 +456,13 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t start_addr, size_t
/** Start SDHC asynchronous read
*
* This will transfer `length` 512 byte blocks into the buffer pointed to by `data` in the background.
* When the requested quantity of data has been read, the @ref CYHAL_SDHC_ASYNC_READ_COMPLETE event will
* be raised. See @ref cyhal_sdhc_register_callback and @ref cyhal_sdhc_enable_event.
* When the requested quantity of data has been read, the \ref CYHAL_SDHC_XFER_COMPLETE event will
* be raised. See \ref cyhal_sdhc_register_callback and \ref cyhal_sdhc_enable_event.
*
* @param[in] obj The SDHC object that holds the transfer information
* @param[in] address The address to read data from
* @param[out] data The receive buffer
* @param[in,out] length Number of 512 byte blocks to read, updated with the number actually read
* @param[in] obj The SDHC object that holds the transfer information
* @param[in] address The address to read data from
* @param[out] data The receive buffer
* @param[in,out] length Number of 512 byte blocks to read, updated with the number actually read
* @return The status of the read_async request
*/
cy_rslt_t cyhal_sdhc_read_async(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *data, size_t *length);
@ -274,26 +470,27 @@ cy_rslt_t cyhal_sdhc_read_async(const cyhal_sdhc_t *obj, uint32_t address, uint8
/** Start asynchronous SDHC write
*
* This will transfer `length` 512 byte blocks from the buffer pointed to by `data` in the background.
* When the requested quantity of data has been written, the @ref CYHAL_SDHC_ASYNC_WRITE_COMPLETE event
* will be raised. See @ref cyhal_sdhc_register_callback and @ref cyhal_sdhc_enable_event.
* @param[in] obj The SDHC object that holds the transfer information
* @param[in] address The address to write data to
* @param[in] data The transmit buffer
* @param[in,out] length The number of 512 byte blocks to write, updated with the number actually written
* When the requested quantity of data has been written, the \ref CYHAL_SDHC_XFER_COMPLETE event
* will be raised. See \ref cyhal_sdhc_register_callback and \ref cyhal_sdhc_enable_event.
*
* @param[in] obj The SDHC object that holds the transfer information
* @param[in] address The address to write data to
* @param[in] data The transmit buffer
* @param[in,out] length The number of 512 byte blocks to write, updated with the number actually written
* @return The status of the write_async request
*/
cy_rslt_t cyhal_sdhc_write_async(const cyhal_sdhc_t *obj, uint32_t address, const uint8_t *data, size_t *length);
/** Checks if the specified SDHC peripheral is in use
*
* @param[in] obj The SDHC peripheral to check
* @param[in] obj The SDHC peripheral to check
* @return Indication of whether the SDHC is still transmitting
*/
bool cyhal_sdhc_is_busy(const cyhal_sdhc_t *obj);
/** Abort an SDHC transfer
*
* @param[in] obj The SDHC peripheral to stop
* @param[in] obj The SDHC peripheral to stop
* @return The status of the abort_async request
*/
cy_rslt_t cyhal_sdhc_abort_async(const cyhal_sdhc_t *obj);
@ -302,9 +499,9 @@ cy_rslt_t cyhal_sdhc_abort_async(const cyhal_sdhc_t *obj);
*
* This function will be called when one of the events enabled by \ref cyhal_sdhc_enable_event occurs.
*
* @param[in] obj The SDHC object
* @param[in] callback The callback handler which will be invoked when the event fires
* @param[in] callback_arg Generic argument that will be provided to the callback when called
* @param[in] obj The SDHC object
* @param[in] callback The callback handler which will be invoked when the event fires
* @param[in] callback_arg Generic argument that will be provided to the callback when called
*/
void cyhal_sdhc_register_callback(cyhal_sdhc_t *obj, cyhal_sdhc_event_callback_t callback, void *callback_arg);
@ -312,13 +509,178 @@ void cyhal_sdhc_register_callback(cyhal_sdhc_t *obj, cyhal_sdhc_event_callback_t
*
* When an enabled event occurs, the function specified by \ref cyhal_sdhc_register_callback will be called.
*
* @param[in] obj The SDHC object
* @param[in] event The SDHC event type
* @param[in] intr_priority The priority for NVIC interrupt events
* @param[in] enable True to turn on interrupts, False to turn off
* @param[in] obj The SDHC object
* @param[in] event The SDHC event type
* @param[in] intr_priority The priority for NVIC interrupt events
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_sdhc_enable_event(cyhal_sdhc_t *obj, cyhal_sdhc_event_t event, uint8_t intr_priority, bool enable);
/** Checks if SD card is inserted
*
* @param[in] obj The SDHC peripheral to check
* @return Indication of whether the card is inserted.
*/
bool cyhal_sdhc_is_card_inserted(const cyhal_sdhc_t *obj);
/** Checks if the inserted SD card is mechanically write protected
*
* @param[in] obj The SDHC peripheral to check
* @return Indication of whether the inserted SD card is mechanically write protected
*/
bool cyhal_sdhc_is_card_mech_write_protected(const cyhal_sdhc_t *obj);
/** Get block count of inserted SD card / eMMC
* \note SDHC driver should be initialized with \ref cyhal_sdhc_init prior to using this function.
*
* @param[in] obj The SDHC object
* @param[in] block_count Pointer to variable where block count will be stored
* @return The status of the operation
*/
cy_rslt_t cyhal_sdhc_get_block_count(cyhal_sdhc_t *obj, uint32_t *block_count);
/** Sets the SD bus frequency (frequency on which SD card / eMMC is accessed)
* \note Actual frequency may differ from the desired frequency due to available dividers and the frequency of source clock.
* Function will set the closest possible (but not greater than) frequency to what was requested.
* Use \ref cyhal_sdhc_get_frequency function to get actual frequency value that was achieved and set.
* \note If data timeout was configured by \ref cyhal_sdhc_set_data_read_timeout, it can be automaticaly recalculated
* according to new SD bus frequency. For details, please refer to \ref cyhal_sdhc_set_data_read_timeout function description.
*
* @param[in] obj The SDHC object
* @param[in] hz Desired SD bus frequency in Hz
* @param[in] negotiate Whether new frequency value needs to be negotiated with card or not. true is
* recommended and it means that new frequency will be negotiated.
* @return The status of the operation
*/
cy_rslt_t cyhal_sdhc_set_frequency(cyhal_sdhc_t *obj, uint32_t hz, bool negotiate);
/** Get the actual frequency that SD bus is configured for
*
* @param[in] obj The SDHC object
* @return Frequency in Hz
*/
uint32_t cyhal_sdhc_get_frequency(cyhal_sdhc_t *obj);
/** Sets the maximum time to wait for data from the card. The time is specified in number of card clock cycles.
* With SD bus frequency changed by \ref cyhal_sdhc_set_frequency, timeout can automaticaly be recalculated according
* to new clock frequency. This can be activated by 'auto_reconfigure' parameter.
*
* @param[in] obj The SDHC object
* @param[in] timeout Time to wait for data from the card.
* @param[in] auto_reconfigure Timeout value will be automaticaly reconfigured upon clock change
*
* @return The status of the operation
*/
cy_rslt_t cyhal_sdhc_set_data_read_timeout(cyhal_sdhc_t *obj, uint32_t timeout, bool auto_reconfigure);
/** Initializes the SD block and DMA for a data transfer. It does not start a transfer.
* \ref cyhal_sdhc_send_cmd needs to be called after this function in order to start data transfer.
*
* @param[in] obj The SDHC object
* @param[in] data_config Data transfer configuration
* @return The status of the operation
*/
cy_rslt_t cyhal_sdhc_config_data_transfer(cyhal_sdhc_t *obj, cyhal_sdhc_data_config_t *data_config);
/** Sends a command to the card and wait until it is sent. If the command assumes data transfer via data lines,
* \ref cyhal_sdhc_config_data_transfer function needs to be called prior to this one. The response of issued command
* can be retrieved by using \ref cyhal_sdhc_get_response function.
* \note Function does not wait until data (configured with \ref cyhal_sdhc_config_data_transfer) transfer complete.
* In order to do so, user can:
* - register \ref CYHAL_SDHC_XFER_COMPLETE and wait for it
* - wait until \ref cyhal_sdhc_is_busy return false
* - use \ref cyhal_sdhc_wait_transfer_complete function
*
* @param[in] obj The SDHC object
* @param[in] cmd_config Command configuration
* @return The status of the operation
*/
cy_rslt_t cyhal_sdhc_send_cmd(cyhal_sdhc_t *obj, cyhal_sdhc_cmd_config_t *cmd_config);
/** Returns a response of last issued by \ref cyhal_sdhc_send_cmd function command.
*
* @param[in] obj The SDHC object
* @param[in] response Pointer to array where response will be stored
* @param[in] large_response If true, the expected response is 136 bits, false - 48 bits, which corresponds to
* 120 and 32 bits of useful for application data respectively. So for large_response 4 uint32_t element array can be used
* while for not large_response 1 uint32_t value will be enough.
* @return The status of the operation
*/
cy_rslt_t cyhal_sdhc_get_response(cyhal_sdhc_t *obj, uint32_t *response, bool large_response);
/** Wait for asynchronous data transfer to complete. Such data transfer can be triggered by \ref cyhal_sdhc_write_async,
* \ref cyhal_sdhc_read_async or by \ref cyhal_sdhc_config_data_transfer + \ref cyhal_sdhc_send_cmd functions.
*
* @param[in] obj The SDHC object
* @return The status of the operation
*/
cy_rslt_t cyhal_sdhc_wait_transfer_complete(cyhal_sdhc_t *obj);
/** Sets the voltage level of the I/O lines.
* \note This function requires io_volt_sel and (for some cases) card_pwr_en pins to be assigned. Please refer to
* \ref cyhal_sdhc_init_hw for pin details.
* \note Switching from 1.8V to 3.3V can be done only via power cycle sequence (power down card, wait, power up card),
* which is supported by HAL driver and performed only if CYHAL_SDHC_IO_VOLT_ACTION_NEGOTIATE selected. card_pwr_en pin
* has to be assigned. Please refer to \ref cyhal_sdhc_init_hw for pin details.
*
* @param[in] obj The SDHC object
* @param[in] io_voltage I/O voltage to be set on lines
* @param[in] io_switch_type Defines how I/O voltage will be switched
* @return The status of the operation
*/
cy_rslt_t cyhal_sdhc_set_io_voltage(cyhal_sdhc_t *obj, cyhal_sdhc_io_voltage_t io_voltage, cyhal_sdhc_io_volt_action_type_t io_switch_type);
/** Returns the current voltage level of the I/O lines
*
* @param[in] obj The SDHC object
* @return Current I/O voltage setting value
*/
cyhal_sdhc_io_voltage_t cyhal_sdhc_get_io_voltage(cyhal_sdhc_t *obj);
/** Configures data bus width on host side and (optionally) informs the card about new width configuration.
*
* @param[in] obj The SDHC object
* @param[in] bus_width The desired bus width, 1-bit, 4-bit, 8-bit
* @param[in] configure_card Whether card needs to be configured with new bus width. true is recommended.
* @return The status of the operation
*/
cy_rslt_t cyhal_sdhc_set_bus_width(cyhal_sdhc_t *obj, uint8_t bus_width, bool configure_card);
/** Returns currently configured data bus width
*
* @param[in] obj The SDHC object
* @return Currently configured bus width, 1-bit, 4-bit, 8-bit
*/
uint8_t cyhal_sdhc_get_bus_width(cyhal_sdhc_t *obj);
/** Returns last issued SD operation error states. This function can be used for error checking after any of cmd / data
* transfer-related operations. For list of possible errors, that are being tracked, please refer to \ref cyhal_sdhc_error_type_t.
*
* @param[in] obj The SDHC object
* @return Errors occurred during last command
*/
cyhal_sdhc_error_type_t cyhal_sdhc_get_last_command_errors(cyhal_sdhc_t *obj);
/** Clears SDHC hardware error states. Error statuses are indicated by \ref cyhal_sdhc_get_last_command_errors function.
*
* @param[in] obj The SDHC object
*/
void cyhal_sdhc_clear_errors(cyhal_sdhc_t *obj);
/** Resets CMD and Data lines and corresponding circuits of SD Host.
*
* @param[in] obj The SDHC object
*/
void cyhal_sdhc_software_reset(cyhal_sdhc_t *obj);
/** Powers up / down the card based on provided parameter. This function uses card_pwr_en pin to change card power
* state. Please refer to \ref cyhal_sdhc_init_hw for pin description.
*
* @param[in] obj The SDHC peripheral to configure
* @param[in] enable Card is powered if true, not powered if false.
* @return The status of the operation
*/
cy_rslt_t cyhal_sdhc_enable_card_power(cyhal_sdhc_t *obj, bool enable);
#if defined(__cplusplus)
}

61
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -56,27 +56,27 @@
* \subsection subsection_sdio_use_case_1 Snippet1: Simple SDIO Initialization example
* The following snippet shows how to initialize the SDIO interface with a pre-defined configuration
*
* \snippet sdio.c snippet_cyhal_sdio_simple_init
* \snippet hal_sdio.c snippet_cyhal_sdio_simple_init
*
* \subsection subsection_sdio_use_case_2 Snippet2: Configure Interrupt
* The following snippet shows how to configure an interrupt and handle specific events. Refer \ref cyhal_sdio_event_t for different types of events.
*
* \snippet sdio.c snippet_cyhal_sdio_interrupt_callback
* \snippet hal_sdio.c snippet_cyhal_sdio_interrupt_callback
*
* \subsection subsection_sdio_use_case_3 Snippet3: Sending Commands
* The following snippet shows how to send a particular command. Some steps of the card initialization have been provided for reference. Refer \ref cyhal_sdio_command_t for different commands.
*
* \snippet sdio.c snippet_cyhal_sdio_send_command
* \snippet hal_sdio.c snippet_cyhal_sdio_send_command
*
* \subsection subsection_sdio_use_case_4 Snippet4: Bulk Data Transfer
* The following snippet shows how to start a bulk data transfer.
*
* \snippet sdio.c snippet_cyhal_sdio_bulk_transfer
* \snippet hal_sdio.c snippet_cyhal_sdio_bulk_transfer
*
* \subsection subsection_sdio_use_case_5 Snippet5: Async Data Transfer
*
* The following snippet shows how to start an async data transfer.
* \snippet sdio.c snippet_cyhal_sdio_async_transfer
* \snippet hal_sdio.c snippet_cyhal_sdio_async_transfer
*/
#pragma once
@ -94,23 +94,6 @@ extern "C" {
* Defines
*******************************************************************************/
#define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/
#define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/
#define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/
#define CYHAL_SDIO_RET_CMD_IDX_ERROR (0x04) /**< The index for the command didn't match*/
#define CYHAL_SDIO_RET_CMD_EB_ERROR (0x08) /**< There was an end bit error on the command*/
#define CYHAL_SDIO_RET_DAT_CRC_ERROR (0x10) /**< There was a data CRC Error*/
#define CYHAL_SDIO_RET_CMD_TIMEOUT (0x20) /**< The command didn't finish before the timeout period was over*/
#define CYHAL_SDIO_RET_DAT_TIMEOUT (0x40) /**< The data didn't finish before the timeout period was over*/
#define CYHAL_SDIO_RET_RESP_FLAG_ERROR (0x80) /**< There was an error in the resposne flag for command 53*/
#define CYHAL_SDIO_CLOCK_ERROR (0x100) /**< Failed to initial clock for SDIO */
#define CYHAL_SDIO_BAD_ARGUMENT (0x200) /**< Bad argument passed for SDIO */
#define CYHAL_SDIO_SEMA_NOT_INITED (0x400) /**< Semaphore is not initiated */
#define CYHAL_SDIO_FUNC_NOT_SUPPORTED (0x800) /**< Function is not supported */
#define CYHAL_SDIO_CANCELED (0x1000) /**< Operation canceled */
#define CYHAL_SDIO_PM_PENDING_ERROR (0x2000) /**< Transfer cannot be initiated after power mode transition allowed.*/
/* HAL return value defines */
/** \addtogroup group_hal_results_sdio SDIO HAL Results
@ -120,23 +103,23 @@ extern "C" {
*/
/** Incorrect parameter value define */
#define CYHAL_SDIO_RSLT_ERR_BAD_PARAM \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_BAD_ARGUMENT))
/** Clock initialization error define */
#define CYHAL_SDIO_RSLT_ERR_CLOCK \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CLOCK_ERROR))
/** Semaphore not initiated error define */
#define CYHAL_SDIO_RSLT_ERR_SEMA_NOT_INITED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_SEMA_NOT_INITED))
/** Error define based on SDIO lower function return value */
#define CYHAL_SDIO_RSLT_ERR_FUNC_RET(retVal) \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, ((uint16_t)retVal)))
#define CYHAL_SDIO_RSLT_ERR_BAD_PARAM \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, 0))
/** Define to indicate canceled operation */
#define CYHAL_SDIO_RSLT_CANCELED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_CANCELED))
#define CYHAL_SDIO_RSLT_CANCELED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, 1))
/** Transfers are not allowed after the SDIO block has allowed power mode transition. */
#define CYHAL_SDIO_RSLT_ERR_PM_PENDING \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, CYHAL_SDIO_PM_PENDING_ERROR))
#define CYHAL_SDIO_RSLT_ERR_PM_PENDING \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, 2))
/** Requested feature is not supported on this hardware. */
#define CYHAL_SDIO_RSLT_ERR_UNSUPPORTED \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, 3))
/** Failure in command send. */
#define CYHAL_SDIO_RSLT_ERR_COMMAND_SEND \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, 4))
/** SDIO Configuration error. */
#define CYHAL_SDIO_RSLT_ERR_CONFIG \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDIO, 5))
/**
* \}
@ -285,8 +268,6 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction
/** Performs a bulk asynchronous data transfer by issuing the \ref CYHAL_SDIO_CMD_IO_RW_EXTENDED command(CMD=53) to the SDIO block.
* After exiting this function the \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are not asserted.
*
* To complete the asynchronous transfer, call \ref cyhal_sdio_is_busy()
* until it returns false.
* The \ref CYHAL_SDIO_CMD_COMPLETE and \ref CYHAL_SDIO_XFER_COMPLETE events are enabled
* after the asynchronous transfer is complete and in the condition they were
* enabled in before the transfer operation started. Handle these events in the interrupt callback.

56
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -59,24 +59,24 @@
* \subsection subsection_spi_snippet_1 Snippet 1: SPI Master - Single byte transfer operation (Read and Write)
* The following code snippet initializes an SPI Master interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency().
* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv().
* \snippet spi.c snippet_cyhal_spi_master_byte_operation
* \snippet hal_spi.c snippet_cyhal_spi_master_byte_operation
*
* \subsection subsection_spi_snippet_2 Snippet 2: SPI Slave - Single byte transfer operation (Read and Write)
* The following code snippet initializes an SPI Slave interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency.
* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv.
* \snippet spi.c snippet_cyhal_spi_slave_byte_operation
* \snippet hal_spi.c snippet_cyhal_spi_slave_byte_operation
*
* \subsection subsection_spi_snippet_3 Snippet 3: SPI Block Data transfer
* The following snippet sends and receives an array of data in a single SPI transaction using \ref cyhal_spi_transfer(). The example
* uses SPI master to transmit 5 bytes of data and receive 5 bytes of data in a single transaction.
* \snippet spi.c snippet_cyhal_spi_block_data_transfer
* \snippet hal_spi.c snippet_cyhal_spi_block_data_transfer
*
* \subsection subsection_spi_snippet_4 Snippet 4: Interrupts on SPI events
* SPI interrupt events ( \ref cyhal_spi_event_t) can be mapped to an interrupt and assigned to a callback function.
* The callback function needs to be first registered and then the event needs to be enabled.
* The following snippet initialises a SPI master to perform a block transfer using \ref cyhal_spi_transfer_async(). This is a non-blocking function.
* A callback function is registered using \ref cyhal_spi_register_callback to notify whenever the SPI transfer is complete.
* \snippet spi.c snippet_cyhal_spi_interrupt_callback_events
* \snippet hal_spi.c snippet_cyhal_spi_interrupt_callback_events
* \section subsection_spi_moreinfor More Information
*
@ -190,6 +190,20 @@ typedef enum
CYHAL_SPI_MODE_11_LSB = CYHAL_SPI_MODE(1, 1, 1),
} cyhal_spi_mode_t;
/** SPI FIFO type */
typedef enum
{
CYHAL_SPI_FIFO_RX, //!< Set RX FIFO level
CYHAL_SPI_FIFO_TX, //!< Set TX FIFO level
} cyhal_spi_fifo_type_t;
/** Enum of possible output signals from an SPI */
typedef enum
{
CYHAL_SPI_OUTPUT_TRIGGER_RX_FIFO_LEVEL_REACHED, //!< Output the RX FIFO signal which is triggered when the receive FIFO has more entries than the configured level.
CYHAL_SPI_OUTPUT_TRIGGER_TX_FIFO_LEVEL_REACHED, //!< Output the TX FIFO signal which is triggered when the transmit FIFO has less entries than the configured level.
} cyhal_spi_output_t;
/** @brief Initial SPI configuration. */
typedef struct
{
@ -364,6 +378,38 @@ void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t ca
*/
void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intr_priority, bool enable);
/** Sets a threshold level for a FIFO that will generate an interrupt and a
* trigger output. The RX FIFO interrupt and trigger will be activated when
* the receive FIFO has more entries than the threshold. The TX FIFO interrupt
* and trigger will be activated when the transmit FIFO has less entries than
* the threshold.
*
* @param[in] obj The SPI object
* @param[in] type FIFO type to set level for
* @param[in] level Level threshold to set
* @return The status of the level set
* */
cy_rslt_t cyhal_spi_set_fifo_level(cyhal_spi_t *obj, cyhal_spi_fifo_type_t type, uint16_t level);
/** Enables the specified output signal from an SPI.
*
* @param[in] obj The SPI object
* @param[in] output Which output signal to enable
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. \p source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t cyhal_spi_enable_output(cyhal_spi_t *obj, cyhal_spi_output_t output, cyhal_source_t *source);
/** Disables the specified output signal from an SPI
*
* @param[in] obj The SPI object
* @param[in] output Which output signal to disable
* @return The status of the output disable
* */
cy_rslt_t cyhal_spi_disable_output(cyhal_spi_t *obj, cyhal_spi_output_t output);
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* not be used in new projects

16
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_syspm.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -132,17 +132,17 @@
* The following snippet shows how to use the deep sleep locking APIs to restrict
* when the device can enter deep sleep. In between the lock/unlock calls any
* attempt to change power modes will automatically be canceled.
* \snippet syspm.c snippet_cyhal_syspm_simple_locking
* \snippet hal_syspm.c snippet_cyhal_syspm_simple_locking
*
* \subsection subsection_syspm_snippet_2 Snippet 2: Calling different power state functions
* The following snippet shows the different functions that exist to change power states
* on the device and how they can each be called.
* \snippet syspm.c snippet_cyhal_syspm_power_transitions
* \snippet hal_syspm.c snippet_cyhal_syspm_power_transitions
*
* \subsection subsection_syspm_snippet_3 Snippet 3: Using callbacks for application power management
* The following snippet shows how to use the callback mechanisms to manage whether
* it is safe to enter low power modes.
* \snippet syspm.c snippet_cyhal_syspm_app_callback
* \snippet hal_syspm.c snippet_cyhal_syspm_app_callback
*/
#pragma once
@ -221,9 +221,9 @@ typedef enum
See device datasheet for specific pin. */
} cyhal_syspm_hibernate_source_t;
/** Supply voltages whose levels can be specified and queried via \ref cyhal_syspm_set_supply_voltage and
/** Supply voltages whose levels can be specified and queried via \ref cyhal_syspm_set_supply_voltage and
* \ref cyhal_syspm_get_supply_voltage, respectively.
*
*
* \note Not all supplies which are present are included here. This enum only contains the voltage supplies
* whose values are relevant to the operation of one or more HAL drivers.
*/
@ -304,7 +304,7 @@ cy_rslt_t cyhal_syspm_set_system_state(cyhal_syspm_system_state_t state);
* CYHAL_SYSPM_SYSTEM_NORMAL.
* @return Returns the current system-wide power state of the device.
*/
cyhal_syspm_system_state_t cyhal_syspm_get_system_state();
cyhal_syspm_system_state_t cyhal_syspm_get_system_state(void);
/** Register the specified handler with the power manager to be notified of power
* state changes. This is intended for application wide decisions. Peripherals handle
@ -398,7 +398,7 @@ cy_rslt_t cyhal_syspm_tickless_sleep(cyhal_lptimer_t *obj, uint32_t desired_ms,
* Once set, this value can be queried via \ref cyhal_syspm_get_supply_voltage.
*
* \note This only informs the system of the voltage level. It does not alter any of the device operating conditions.
*
*
* @param supply The supply whose voltage is being specified.
* @param mvolts The voltage level on the specified supply, in millivolts.
*/

11
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_syspm_impl.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -31,7 +31,7 @@
* \addtogroup group_hal_impl_syspm System Power Management
* \ingroup group_hal_impl
* \{
* The PSoC 6 Power Management has the following characteristics:
* The CAT1 (PSoC 6) Power Management has the following characteristics:
* \ref CYHAL_SYSPM_SYSTEM_NORMAL equates to the Low Power mode<br>
* \ref CYHAL_SYSPM_SYSTEM_LOW equates to the Ultra Low Power mode
*
@ -74,14 +74,15 @@ cy_rslt_t cyhal_syspm_tickless_sleep_deepsleep(cyhal_lptimer_t *obj, uint32_t de
#define cyhal_syspm_tickless_sleep(obj, desired_ms, actual_ms) cyhal_syspm_tickless_sleep_deepsleep(obj, desired_ms, actual_ms, false)
#if defined(COMPONENT_PSOC6HAL)
#if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
#define cyhal_syspm_sleep() Cy_SysPm_CpuEnterSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)
#define cyhal_syspm_deepsleep() Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)
#define cyhal_syspm_get_system_state() (Cy_SysPm_IsSystemUlp() ? CYHAL_SYSPM_SYSTEM_LOW : CYHAL_SYSPM_SYSTEM_NORMAL)
#else
#elif defined(COMPONENT_CAT2)
#define cyhal_syspm_sleep() Cy_SysPm_CpuEnterSleep()
#define cyhal_syspm_deepsleep() Cy_SysPm_CpuEnterDeepSleep()
#endif /* COMPONENT_PSOC6HAL */
#define cyhal_syspm_get_system_state() (CYHAL_SYSPM_SYSTEM_NORMAL)
#endif /* defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) */
/** \endcond */

6
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -55,13 +55,13 @@
* \ref cyhal_system_critical_section_enter returns the current state of interrupts
* which denote the active interrupts in the system. This must be passed as argument
* to \ref cyhal_system_critical_section_exit while exiting the critical section.
* \snippet system.c snippet_cyhal_system_critical_section
* \snippet hal_system.c snippet_cyhal_system_critical_section
*
* \subsection subsection_system_snippet2 Snippet 2: Reset reason
* \ref cyhal_system_get_reset_reason must be called at the beginning of the main to
* determine the reason for reset. The return parameters are present in \ref
* cyhal_reset_reason_t.
* \snippet system.c snippet_cyhal_system_reset_reason
* \snippet hal_system.c snippet_cyhal_system_reset_reason
*/
#pragma once

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system_impl.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

136
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2019-2020 Cypress Semiconductor Corporation
* Copyright 2019-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -35,6 +35,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "cyhal_hw_types.h"
#include "cyhal_interconnect.h"
#if defined(__cplusplus)
extern "C" {
@ -55,6 +56,87 @@ extern "C" {
#define _CYHAL_TCPWM_INSTANCES CY_IP_M0S8TCPWM_INSTANCES
#endif
// There are some number of input trigger indices (starting at 0) that are
// reserved for various purposes. Here we are dealing with inputs from the
// trigmux which start after the reserved inputs so we must always offset the
// trigger index after reservation. For all devices, indices 0 and 1 are
// reserved for constant signals 0 and 1 respectively (so offset by 2 to
// start). Depending on device, further offsetting may be needed as well. The
// number of trigmux tcpwm inputs (but not the total number of tcpwm trigger
// inputs) per tcpwm block is also defined here.
#if (CY_IP_MXTCPWM_VERSION == 1U)
#define _CYHAL_TCPWM_TRIGGER_INPUTS_IDX_OFFSET (2)
#define _CYHAL_TCPWM_TRIGGER_INPUTS_PER_BLOCK (16 - _CYHAL_TCPWM_TRIGGER_INPUTS_IDX_OFFSET)
#elif (CY_IP_MXTCPWM_VERSION == 2U)
// PSoC6 devices with trigmux vers2 also have a number of reserved input
// lines defined by TCPWM_TR_ONE_CNT_NR.
// Note: These devices also have support for up to 256 trigger lines total,
// but only 14 input triggers (on top of the 2 + TCPWM_TR_ONE_CNT_NR) are
// currently available.
#define _CYHAL_TCPWM_TRIGGER_INPUTS_IDX_OFFSET (2 + TCPWM_TR_ONE_CNT_NR)
#define _CYHAL_TCPWM_TRIGGER_INPUTS_PER_BLOCK (14)
#else // (CY_IP_M0S8TCPWM_VERSION == 2)
// PSoC4 devices have a number of reserved input lines coming directly from
// GPIO triggers (depending on exact architecture).
#if defined(CY_DEVICE_PSOC4AS1)
// 12 GPIO trigger lines reserved (but some may be unused, depending on
// pin package)
#define _CYHAL_TCPWM_TRIGGER_INPUTS_IDX_OFFSET (2 + 12)
#define _CYHAL_TCPWM_TRIGGER_INPUTS_PER_BLOCK (16 - _CYHAL_TCPWM_TRIGGER_INPUTS_IDX_OFFSET)
#else
// 7 GPIO trigger lines reserved (but some may be unused, depending on
// pin package)
#define _CYHAL_TCPWM_TRIGGER_INPUTS_IDX_OFFSET (2 + 7)
#define _CYHAL_TCPWM_TRIGGER_INPUTS_PER_BLOCK (16 - _CYHAL_TCPWM_TRIGGER_INPUTS_IDX_OFFSET)
#endif
#endif
/** \addtogroup group_hal_results_tcpwm TCPWM HAL Results
* TCPWM specific return codes
* \ingroup group_hal_results
* \{ *//**
*/
/** Bad argument. eg: null pointer */
#define CYHAL_TCPWM_RSLT_ERR_BAD_ARGUMENT \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_IMPL_TCPWM, 0))
/** Failed to find free input signal */
#define CYHAL_TCPWM_RSLT_ERR_NO_FREE_INPUT_SIGNALS \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_IMPL_TCPWM, 1))
/** Failed to find free output signal */
#define CYHAL_TCPWM_RSLT_ERR_NO_FREE_OUTPUT_SIGNALS \
(CYHAL_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_IMPL_TCPWM, 2))
/**
* \}
*/
/** TCPWM/counter input signal */
typedef enum
{
CYHAL_TCPWM_INPUT_START, //!< Start signal
CYHAL_TCPWM_INPUT_STOP, //!< Stop signal
CYHAL_TCPWM_INPUT_RELOAD, //!< Reload signal
CYHAL_TCPWM_INPUT_COUNT, //!< Count signal
CYHAL_TCPWM_INPUT_CAPTURE, //!< Capture signal
} cyhal_tcpwm_input_t;
/** The number of unique TCPWM inputs as defined by cyhal_tcpwm_input_t */
#define _CYHAL_TCPWM_INPUTS 5
/** TCPWM/counter output signal */
typedef enum
{
CYHAL_TCPWM_OUTPUT_OVERFLOW, //!< Overflow signal
CYHAL_TCPWM_OUTPUT_UNDERFLOW, //!< Underflow signal
CYHAL_TCPWM_OUTPUT_COMPARE_MATCH, //!< Compare match signal
CYHAL_TCPWM_OUTPUT_TERMINAL_COUNT, //!< Terminal count signal (logical OR of overflow and underflow signal)
CYHAL_TCPWM_OUTPUT_LINE_OUT, //!< Line out signal
} cyhal_tcpwm_output_t;
/** The number of unique TCPWM outputs as defined by cyhal_tcpwm_output_t */
#define _CYHAL_TCPWM_OUTPUTS 5
/** Handler for TCPWM interrupts */
typedef void(*_cyhal_tcpwm_event_callback_t)(void *callback_arg, int event);
@ -71,6 +153,15 @@ typedef struct {
/** Contains data about all of the TCPWMs */
extern const _cyhal_tcpwm_data_t _CYHAL_TCPWM_DATA[_CYHAL_TCPWM_INSTANCES];
/** Bitfield that contains in use data for all TCPWM input trigger lines */
extern uint32_t _CYHAL_INPUT_TRIGGERS_USED[_CYHAL_TCPWM_INSTANCES][(_CYHAL_TCPWM_TRIGGER_INPUTS_PER_BLOCK / 32) + 1];
#ifdef CY_DEVICE_PSOC6A256K
/** Contains bitfield of in use data for all TCPWM output trigger lines. There
* are 2 available output lines per counter */
extern uint8_t _CYHAL_OUTPUT_TRIGGERS_USED[TCPWM_GRP_NR0_GRP_GRP_CNT_NR + TCPWM_GRP_NR1_GRP_GRP_CNT_NR];
#endif
/**
* Free a timer/counter or a PWM object's shared data
*
@ -108,6 +199,49 @@ void _cyhal_tcpwm_enable_event(TCPWM_Type *type, cyhal_resource_inst_t *resource
*/
bool _cyhal_tcpwm_pm_transition_pending(void);
/** Connects a source signal and configures and enables a TCPWM event to be
* triggered from that signal. These TCPWM events can be configured
* independently and connect to the same or different source signals.
*
* @param[in] obj TCPWM HAL object
* @param[in] source Source signal obtained from another driver's cyhal_<PERIPH>_enable_output
* @param[in] signal The TCPWM input signal
* @param[in] type The TCPWM input signal edge type
* @return The status of the connection
* */
cy_rslt_t _cyhal_tcpwm_connect_digital(cyhal_tcpwm_t *obj, cyhal_source_t source, cyhal_tcpwm_input_t signal, cyhal_edge_type_t type);
/** Enables the specified output signal from a TCPWM that will be triggered
* when the corresponding event occurs. Multiple output signals can be
* configured simultaneously.
*
* @param[in] obj TCPWM HAL object
* @param[in] signal The TCPWM output signal
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t _cyhal_tcpwm_enable_output(cyhal_tcpwm_t *obj, cyhal_tcpwm_output_t signal, cyhal_source_t *source);
/** Disconnects a source signal and disables the corresponding input to a TCPWM
*
* @param[in] obj TCPWM HAL object
* @param[in] source Source signal from cyhal_<PERIPH>_enable_output to disable
* @param[in] signal The TCPWM input signal
* @return The status of the disconnection
* */
cy_rslt_t _cyhal_tcpwm_disconnect_digital(cyhal_tcpwm_t *obj, cyhal_source_t source, cyhal_tcpwm_input_t signal);
/** Disables the specified output signal from a TCPWM.
*
* @param[in] obj TCPWM HAL object
* @param[in] resource TCPWM resource
* @param[in] signal The TCPWM output signal
* @return The status of the output disable
* */
cy_rslt_t _cyhal_tcpwm_disable_output(cyhal_tcpwm_t *obj, cyhal_tcpwm_output_t signal);
#if defined(__cplusplus)
}
#endif /* __cplusplus */

67
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -69,12 +69,12 @@
* \subsection subsection_timer_snippet_1 Snippet 1: Measuring time of an operation
* The following snippet initializes a Timer and measures the time between two events.
* The <b>clk</b> need not be provided, in which case a clock resource is assigned.
* \snippet timer.c snippet_cyhal_timer_event_measure
* \snippet hal_timer.c snippet_cyhal_timer_event_measure
*
* \subsection subsection_timer_snippet_2 Snippet 2: Handling an event in a callback function
* The following snippet initializes a Timer and triggers an event after every one second.
* The <b>clk</b> need not be provided (NULL), in which case a clock resource is assigned.
* \snippet timer.c snippet_cyhal_timer_event_interrupt
* \snippet hal_timer.c snippet_cyhal_timer_event_interrupt
*
*/
@ -132,6 +132,25 @@ typedef enum {
CYHAL_TIMER_IRQ_ALL = (1 << 2) - 1, /**< Interrupt on terminal count and Compare/Capture values **/
} cyhal_timer_event_t;
/** Timer/counter input signal */
typedef enum
{
CYHAL_TIMER_INPUT_START, //!< Start signal
CYHAL_TIMER_INPUT_STOP, //!< Stop signal
CYHAL_TIMER_INPUT_RELOAD, //!< Reload signal
CYHAL_TIMER_INPUT_COUNT, //!< Count signal
CYHAL_TIMER_INPUT_CAPTURE, //!< Capture signal
} cyhal_timer_input_t;
/** Timer/counter output signal */
typedef enum
{
CYHAL_TIMER_OUTPUT_OVERFLOW, //!< Overflow signal
CYHAL_TIMER_OUTPUT_UNDERFLOW, //!< Underflow signal
CYHAL_TIMER_OUTPUT_COMPARE_MATCH, //!< Compare Match signal
CYHAL_TIMER_OUTPUT_TERMINAL_COUNT, //!< Terminal count signal (logical OR of overflow and underflow signal)
} cyhal_timer_output_t;
/*******************************************************************************
* Data Structures
*******************************************************************************/
@ -269,6 +288,48 @@ void cyhal_timer_register_callback(cyhal_timer_t *obj, cyhal_timer_event_callbac
*/
void cyhal_timer_enable_event(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intr_priority, bool enable);
/** Connects a source signal and configures and enables a timer event to be
* triggered from that signal. These timer events can be configured
* independently and connect to the same or different source signals.
*
* @param[in] obj Timer obj
* @param[in] source Source signal obtained from another driver's cyhal_<PERIPH>_enable_output
* @param[in] signal The timer input signal
* @param[in] type The timer input signal edge type
* @return The current status of the connection
* */
cy_rslt_t cyhal_timer_connect_digital(cyhal_timer_t *obj, cyhal_source_t source, cyhal_timer_input_t signal, cyhal_edge_type_t type);
/** Enables the specified output signal from a tcpwm that will be triggered
* when the corresponding event occurs. Multiple output signals can be
* configured simultaneously.
*
* @param[in] obj Timer obj
* @param[in] signal The timer output signal
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. \p source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The current status of the output enable
* */
cy_rslt_t cyhal_timer_enable_output(cyhal_timer_t *obj, cyhal_timer_output_t signal, cyhal_source_t *source);
/** Disconnects a source signal and disables the timer event.
*
* @param[in] obj Timer obj
* @param[in] source Source signal from cyhal_<PERIPH>_enable_output to disable
* @param[in] signal The timer input signal
* @return The status of the disconnection
* */
cy_rslt_t cyhal_timer_disconnect_digital(cyhal_timer_t *obj, cyhal_source_t source, cyhal_timer_input_t signal);
/** Disables the specified output signal from a timer.
*
* @param[in] obj Timer obj
* @param[in] signal The timer output signal
* @return The status of the output disable
* */
cy_rslt_t cyhal_timer_disable_output(cyhal_timer_t *obj, cyhal_timer_output_t signal);
#if defined(__cplusplus)
}
#endif

9
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2019-2020 Cypress Semiconductor Corporation
* Copyright 2019-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -34,6 +34,13 @@
* 100 Mhz) with a 16 bit Peripheral Clock divider. Because of this the frequency
* range that is supported by \ref cyhal_timer_set_frequency is: 1526 hz -
* 100 Mhz
* \section group_hal_impl_timer_interconnect Interconnect
* In PSoC Timer channels can configure multiple input and output triggers
* simultaneously. 1 or more input triggers can be configured to initiate
* different Timer actions (e.g start, stop, reload, etc) with configurable
* edge detection on that incoming signal. Output triggers are based on certain
* events (e.g overflow, cc_match, etc).
* Note: The terminal_count output trigger is only available for TCPWMv2.
* \} group_hal_impl_timer */
#include "cyhal_timer.h"

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_triggers.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

7
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -39,6 +39,9 @@
* * Generated sequences of numbers cannot be duplicated by running the process again
* * Uses polynomial generators with fixed and programmable polynomials
*
* \note This driver is not intended to be used as a security library. If a full security library
* is needed something like Mbed TLS should be used instead.
*
* \section subsection_trng_quickstart Quick Start
*
* \ref cyhal_trng_init initializes the TRNG and passes a pointer to the **TRNG** block through the **obj** object of type \ref cyhal_trng_t.
@ -48,7 +51,7 @@
* \subsection subsection_trng_use_case_1 Simple TRNG number generation example
* The following snippet initializes a TRNG and generates a true random number.
*
* \snippet trng.c snippet_cyhal_trng_simple_init
* \snippet hal_trng.c snippet_cyhal_trng_simple_init
*/
#pragma once

14
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h Normal file → Executable file
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@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -32,10 +32,20 @@
extern "C" {
#endif /* __cplusplus */
/* Initialization polynomial values for True Random Number Generator */
/**
* \addtogroup group_hal_impl_trng TRNG (True Random Number Generator)
* \ingroup group_hal_impl
* \{
* Initialization polynomial values for the True Random Number Generator.
*/
/** Galois ring oscillator value */
#define CYHAL_GARO31_INITSTATE (0x04c11db7UL)
/** Fibonacci ring oscillator value */
#define CYHAL_FIRO31_INITSTATE (0x04c11db7UL)
/** \} group_hal_impl_trng */
#define MAX_TRNG_BIT_SIZE (32UL)
// This helper function mirrors the definition of cyhal_trng_generate

53
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h Normal file → Executable file
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@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -76,14 +76,14 @@
*
* The snippet also shows how to use \ref cyhal_uart_write, \ref cyhal_uart_putc, \ref cyhal_uart_read API.
*
* \snippet uart.c snippet_cyhal_uart_init
* \snippet hal_uart.c snippet_cyhal_uart_init
*
* \subsection subsection_uart_snippet_2 Snippet 2: Interrupts on UART events
*
* In the following snippet, UART events are handled in a callback function.
* The callback function has to be registered and then the events have to be enabled.
*
* \snippet uart.c snippet_cyhal_uart_event
* \snippet hal_uart.c snippet_cyhal_uart_event
*
*/
@ -157,6 +157,20 @@ typedef enum
CYHAL_UART_IRQ_TX_EMPTY = 1 << 8, //!< The tx hardware buffer is empty
} cyhal_uart_event_t;
/** UART FIFO type */
typedef enum
{
CYHAL_UART_FIFO_RX, //!< Set RX FIFO level
CYHAL_UART_FIFO_TX, //!< Set TX FIFO level
} cyhal_uart_fifo_type_t;
/** Enum of possible output signals from a UART */
typedef enum
{
CYHAL_UART_OUTPUT_TRIGGER_RX_FIFO_LEVEL_REACHED, //!< Output the RX FIFO signal which is triggered when the receive FIFO has more entries than the configured level.
CYHAL_UART_OUTPUT_TRIGGER_TX_FIFO_LEVEL_REACHED, //!< Output the TX FIFO signal which is triggered when the transmit FIFO has less entries than the configured level.
} cyhal_uart_output_t;
/****************************************************************
* Typedef
*****************************************************************/
@ -369,6 +383,7 @@ cy_rslt_t cyhal_uart_read_abort(cyhal_uart_t *obj);
* @param[in] callback_arg Generic argument that will be provided to the callback when called
*/
void cyhal_uart_register_callback(cyhal_uart_t *obj, cyhal_uart_event_callback_t callback, void *callback_arg);
/** Enable or disable specified UART events.
*
* When an enabled event occurs, the function specified by \ref cyhal_uart_register_callback will be called.
@ -380,6 +395,38 @@ void cyhal_uart_register_callback(cyhal_uart_t *obj, cyhal_uart_event_callback_t
*/
void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_t intr_priority, bool enable);
/** Sets a threshold level for a FIFO that will generate an interrupt and a
* trigger output. The RX FIFO interrupt and trigger will be activated when
* the receive FIFO has more entries than the threshold. The TX FIFO interrupt
* and trigger will be activated when the transmit FIFO has less entries than
* the threshold.
*
* @param[in] obj The UART object
* @param[in] type FIFO type to set level for
* @param[in] level Level threshold to set
* @return The status of the level set
* */
cy_rslt_t cyhal_uart_set_fifo_level(cyhal_uart_t *obj, cyhal_uart_fifo_type_t type, uint16_t level);
/** Enables the specified output signal from a UART.
*
* @param[in] obj The UART object
* @param[in] output Which output signal to enable
* @param[out] source Pointer to user-allocated source signal object which
* will be initialized by enable_output. \p source should be passed to
* (dis)connect_digital functions to (dis)connect the associated endpoints.
* @return The status of the output enable
* */
cy_rslt_t cyhal_uart_enable_output(cyhal_uart_t *obj, cyhal_uart_output_t output, cyhal_source_t *source);
/** Disables the specified output signal from a UART
*
* @param[in] obj The UART object
* @param[in] output Which output signal to disable
* @return The status of the output disable
* */
cy_rslt_t cyhal_uart_disable_output(cyhal_uart_t *obj, cyhal_uart_output_t output);
#if defined(__cplusplus)
}
#endif

10
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h Normal file → Executable file
View File

@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2019-2020 Cypress Semiconductor Corporation
* Copyright 2019-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -60,7 +60,7 @@
* to generate and use an available clock resource with a default frequency. The device can be made
* physically visible to the USB Host by using \ref cyhal_usb_dev_connect
*
* \snippet usb_dev.c snippet_cyhal_usb_dev_init
* \snippet hal_usb_dev.c snippet_cyhal_usb_dev_init
*
*
* \subsection subsection_usb_dev_snippet_2 Snippet 2: Handling USB Event Completion
@ -68,14 +68,14 @@
* a callback function. The callback function needs to be first registered using
* \ref cyhal_usb_dev_register_event_callback. Use different callback functions to handle events individually.
*
* \snippet usb_dev.c snippet_cyhal_usb_dev_event
* \snippet hal_usb_dev.c snippet_cyhal_usb_dev_event
*
*
* \subsection subsection_usb_dev_snippet_3 Snippet 3: Custom USB Interrupt Handler
* The following section illustrates how to set up the IRQ interrupt handler for USB device. Inside the handler
* \ref cyhal_usb_dev_process_irq has been used to process the interrupts.
*
* \snippet usb_dev.c snippet_cyhal_usb_dev_irq
* \snippet hal_usb_dev.c snippet_cyhal_usb_dev_irq
*
*
* \subsection subsection_usb_dev_snippet_4 Snippet 4: Adding an Endpoint and Handling its Interrupts
@ -84,7 +84,7 @@
* callback function registered using \ref cyhal_usb_dev_register_endpoint_callback.
* The endpoint can also be configured using <a href="https://www.cypress.com/ModusToolboxUSBConfig">ModusToolbox USB Configurator</a>
*
* \snippet usb_dev.c snippet_cyhal_usb_dev_endpoint
* \snippet hal_usb_dev.c snippet_cyhal_usb_dev_endpoint
*/
#pragma once

111
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h Normal file → Executable file
View File

@ -2,11 +2,11 @@
* \file cyhal_utils.h
*
* \brief
* Provides utility functions for working with the PSoC 6 HAL implementation.
* Provides utility functions for working with the CAT1/CAT2 HAL implementation.
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -138,9 +138,9 @@ void _cyhal_utils_release_if_used(cyhal_gpio_t *pin);
*/
static inline uint32_t _cyhal_utils_divider_value(uint32_t frequency, uint32_t frac_bits)
{
#if defined(COMPONENT_PSOC6HAL)
#if defined(COMPONENT_CAT1A)
return ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + (frequency / 2)) / frequency;
#else /* COMPONENT_PSOC4HAL */
#elif defined(COMPONENT_CAT2)
return ((Cy_SysClk_ClkSysGetFrequency() * (1 << frac_bits)) + (frequency / 2)) / frequency;
#endif
}
@ -199,9 +199,9 @@ cyhal_syspm_callback_mode_t _cyhal_utils_convert_pdltohal_pm_mode(cy_en_syspm_ca
*/
static inline bool _cyhal_utils_is_new_clock_format(const cyhal_clock_t *clock)
{
#if defined(COMPONENT_PSOC6HAL)
#if defined(COMPONENT_CAT1A)
return (((cyhal_clock_block_t)clock->div_type == clock->block) && (clock->div_num == clock->channel));
#else /* COMPONENT_PSOC4HAL */
#else
CY_UNUSED_PARAMETER(clock);
return true;
#endif
@ -214,7 +214,7 @@ static inline bool _cyhal_utils_is_new_clock_format(const cyhal_clock_t *clock)
*/
static inline void _cyhal_utils_update_clock_format(cyhal_clock_t *clock)
{
#if defined(COMPONENT_PSOC6HAL)
#if defined(COMPONENT_CAT1A)
if(((cyhal_clock_block_t)clock->div_type != clock->block) || (clock->div_num != clock->channel))
{
clock->block = (cyhal_clock_block_t)clock->div_type;
@ -228,68 +228,95 @@ static inline void _cyhal_utils_update_clock_format(cyhal_clock_t *clock)
/** Gets the peripheral divider information from a provided clock instance. The clock can be using either
* the new or the old format for clocks.
*
* @param[in] clock The clock to get peripheral divider information from
* @param[out] div_type The divider type the clock instance represents
* @param[out] div_num The divider number the clock instance represents
* @param[in] clock The clock to get peripheral divider information from
* @param[out] div_type The divider type the clock instance represents
* @param[out] div_num The divider number the clock instance represents
*/
void _cyhal_utils_get_peri_clock_details(const cyhal_clock_t *clock, cy_en_divider_types_t *div_type, uint32_t *div_num);
/**
* Calculates clock tolerance in the specified units given a desired and actual frequency
*
* @param[in] type tolerance type
* @param[in] desired_hz desired clock frequency in hertz
* @param[in] actual_hz actual clock frequency in hertz
* @param[in] type tolerance type
* @param[in] desired_hz desired clock frequency in hertz
* @param[in] actual_hz actual clock frequency in hertz
* @return the computed tolerance
*/
int32_t _cyhal_utils_calculate_tolerance(cyhal_clock_tolerance_unit_t type, uint32_t desired_hz, uint32_t actual_hz);
#if defined(COMPONENT_PSOC6HAL)
/**
* Allocates a clock that can drive the specified instance.
*
* @param[out] clock The clock object to initialize
* @param[in] clocked_item The destination that the allocated clock must be able to drive
* @param[in] div The divider width that is required. This is ignored if the block is hard-wired to
* an HFCLK output
* @param[in] accept_larger If no dividers of the specified width are available, can a wider divider be
* substituted.
*/
cy_rslt_t _cyhal_utils_allocate_clock(cyhal_clock_t *clock, const cyhal_resource_inst_t *clocked_item,
cyhal_clock_block_t div, bool accept_larger);
#if defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B)
/** Function for finding most suitable divider for provided clock */
typedef cy_rslt_t (*_cyhal_utils_clk_div_func_t)(uint32_t hz_src, uint32_t desired_hz,
const cyhal_clock_tolerance_t *tolerance, bool only_below_desired, uint32_t *div);
/**
* Finds best divider for HF clock according to source and desired frequency data
*
* @param[in] hz_src clock source frequency in hertz
* @param[in] desired_hz desired clock frequency in hertz
* @param[in] tolerance desired clock tolerance to achieve. If NULL provided, all possible dividers will be checked
* and selected most suitable.
* @param[in] tolerance desired clock tolerance to achieve. If NULL provided, all possible dividers will
* be checked and selected most suitable.
* @param[in] only_below_desired resulting clock frequencies, that are above desired_hz will be skipped
* @param[out] div resulting divider
* @return CYHAL_CLOCK_RSLT_ERR_FREQ if divider is not found, CY_RSLT_SUCCESS in other situations
*/
cy_rslt_t _cyhal_utils_find_hf_clk_div(uint32_t hz_src, uint32_t desired_hz, const cyhal_clock_tolerance_t *tolerance,
bool only_below_desired, uint8_t *div);
bool only_below_desired, uint32_t *div);
/**
* Allocates a clock that can drive the specified instance.
* Attempts to set the clock to the specified frequency. This is similar to cyhal_clock_set_frequency,
* but it will also make an attempt to set the frequency for HFCLK outputs, which are not supported by the public
* API due to their limited range of supported dividers (1, 2, 4, 8)
*
* @param[out] clock The clock object to initialize
* @param[in] clocked_item The destination that the allocated clock must be able to drive
* @param[in] div The divider width that is required. This is ignored if the block is hard-wired to an HFCLK output
* @param[in] accept_larger If no dividers of the specified width are available, can a wider divider be substituted.
*/
cy_rslt_t _cyhal_utils_allocate_clock(cyhal_clock_t *clock, const cyhal_resource_inst_t *clocked_item, cyhal_clock_block_t div, bool accept_larger);
/**
* Attempts to set the clock to the specified frequency. This is similar to cyhal_clock_set_frequency, but it will also make
* an attempt to set the frequency for HFCLK outputs, which are not supported by the public API due to their limited range
* of supported dividers (1, 2, 4, 8)
*
* @param[in] clock The clock instance to set the frequency for.
* @param[in] hz The frequency, in hertz, to set the clock to.
* @param[in] tolerance The allowed tolerance from the desired hz that is acceptable, use NULL if no
* tolerance check is required.
* @param[in] clock The clock instance to set the frequency for.
* @param[in] hz The frequency, in hertz, to set the clock to.
* @param[in] tolerance The allowed tolerance from the desired hz that is acceptable, use NULL if no
* tolerance check is required.
*/
cy_rslt_t _cyhal_utils_set_clock_frequency(cyhal_clock_t* clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance);
/**
* Attempts to set the clock to the specified frequency. This is similar to cyhal_clock_set_frequency, but it will also make
* an attempt to set the frequency for HFCLK outputs. This is an enhancement beyond _cyhal_utils_set_clock_frequency as this
* will also attemt to adjust the source clock as well as change the divider.
* Finds for provided HF clock most suitable source to achieve target clock frequency and returns it with
* corresponding divider value. No clock configuration changed in this function.
*
* @param[in] clock The HFCLK clock instance to set the frequency for.
* @param[in] hz The maximum frequency, in hertz, to set the clock to. The clock will not exceed this value.
* @param[in] tolerance The allowed tolerance below the desired hz that is acceptable, use NULL if no
* tolerance check is required.
* @param[in] clock The HFCLK clock instance that needs clock configuration.
* @param[in] hz The maximum frequency, in hertz, that needs to be achieved. The clock will not exceed
* this value.
* @param[in] tolerance The allowed tolerance below the desired hz that is acceptable, use NULL if no
* tolerance check is required.
* @param[in] div_find_func Pointer to _cyhal_utils_clk_div_func_t - type function, that will find most suitable
* divider for provided clock.
* @param[out] hf_source Resulting HF source clock, switching to which, in combination with resulting divider,
* will provide frequency closest to desired.
* @param[out] div Resulting divider for resulting HF source clock.
*/
cy_rslt_t _cyhal_utils_find_hf_source_n_divider(cyhal_clock_t *clock, uint32_t hz,
const cyhal_clock_tolerance_t *tolerance, _cyhal_utils_clk_div_func_t div_find_func,
cyhal_clock_t *hf_source, uint32_t *div);
/**
* Attempts to set the clock to the specified frequency. This is similar to cyhal_clock_set_frequency, but it will also
* make an attempt to set the frequency for HFCLK outputs. This is an enhancement beyond _cyhal_utils_set_clock_frequency
* as this will also attemt to adjust the source clock as well as change the divider.
*
* @param[in] clock The HFCLK clock instance to set the frequency for.
* @param[in] hz The maximum frequency, in hertz, to set the clock to. The clock will not exceed this
* value.
* @param[in] tolerance The allowed tolerance below the desired hz that is acceptable, use NULL if no
* tolerance check is required.
*/
cy_rslt_t _cyhal_utils_set_clock_frequency2(cyhal_clock_t *clock, uint32_t hz, const cyhal_clock_tolerance_t *tolerance);
@ -300,7 +327,7 @@ cy_rslt_t _cyhal_utils_set_clock_frequency2(cyhal_clock_t *clock, uint32_t hz, c
#define CYHAL_SCB_BASE_ADDRESSES _CYHAL_SCB_BASE_ADDRESSES
#define CYHAL_TCPWM_DATA _CYHAL_TCPWM_DATA
#endif /* defined(COMPONENT_PSOC6HAL) */
#endif /* defined(COMPONENT_CAT1A) || defined(COMPONENT_CAT1B) */
#if defined(__cplusplus)
}

7
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h Normal file → Executable file
View File

@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2019-2020 Cypress Semiconductor Corporation
* Copyright 2019-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -52,7 +52,7 @@
* \subsection subsection_wdt_snippet1 Snippet 1: Initialize the WDT and kick periodically
* The following snippet initializes the WDT and illustrates how to reset the WDT within
* the timeout interval.
* \snippet wdt.c snippet_cyhal_wdt_init_and_reset
* \snippet hal_wdt.c snippet_cyhal_wdt_init_and_reset
*/
#pragma once
@ -101,9 +101,7 @@ cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms);
* cyhal_wdt_init().
*
* @param[inout] obj The WDT object
*
*/
void cyhal_wdt_free(cyhal_wdt_t *obj);
/** Resets the WDT
@ -113,7 +111,6 @@ void cyhal_wdt_free(cyhal_wdt_t *obj);
* See \ref subsection_wdt_snippet1
*
* @param[inout] obj The WDT object
*
*/
void cyhal_wdt_kick(cyhal_wdt_t *obj);

127
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt_impl.h Executable file
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@ -0,0 +1,127 @@
/***************************************************************************//**
* \file cyhal_wdt_impl.h
*
* \brief
* CAT1 specific implementation for WDT API.
*
********************************************************************************
* \copyright
* Copyright 2019-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
/**
* \addtogroup group_hal_impl_wdt WDT (Watchdog Timer)
* \ingroup group_hal_impl
* \{
* The CAT1 (PSoC 6) WDT is only capable of supporting certain timeout ranges below its maximum timeout.
* As a result, any unsupported timeouts given to the HAL WDT are rounded up to the nearest supported value.
* The following table describes the unsupported ranges and the timeout values they are rounded to.
*
* <table class="doxtable">
* <tr><th>Range (ms)</th><th>Rounded Timeout (ms)</th></tr>
* <tr>
* <td>3001 - 3999</td>
* <td>4000</td>
* </tr>
* <tr>
* <td>1501 - 1999</td>
* <td>2000</td>
* </tr>
* <tr>
* <td>751 - 999</td>
* <td>1000</td>
* </tr>
* <tr>
* <td>376 - 499</td>
* <td>500</td>
* </tr>
* <tr>
* <td>188 - 249</td>
* <td>250</td>
* </tr>
* <tr>
* <td>94 - 124</td>
* <td>125</td>
* </tr>
* <tr>
* <td>47 - 62</td>
* <td>63</td>
* </tr>
* <tr>
* <td>24 - 31</td>
* <td>32</td>
* </tr>
* <tr>
* <td>12 - 15</td>
* <td>16</td>
* </tr>
* <tr>
* <td>6 - 7</td>
* <td>8</td>
* </tr>
* <tr>
* <td>3 - 3</td>
* <td>4</td>
* </tr>
* </table>
* \} group_hal_impl_wdt
*/
#include "cyhal_wdt_impl_common.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/**
* \cond INTERNAL
*/
// ILO Frequency = 32768 Hz
// ILO Period = 1 / 32768 Hz = .030518 ms
// WDT Reset Period (timeout_ms) = .030518 ms * (2 * 2^(16 - ignore_bits) + match)
// ignore_bits range: 0 - 12
// match range: 0 - 2^(16 - ignore_bits)
static const _cyhal_wdt_ignore_bits_data_t _cyhal_wdt_ignore_data[] = {
{4000, 3001}, // 0 bit(s): min period: 4000ms, max period: 6000ms, round up from 3001+ms
{2000, 1501}, // 1 bit(s): min period: 2000ms, max period: 3000ms, round up from 1501+ms
{1000, 751}, // 2 bit(s): min period: 1000ms, max period: 1500ms, round up from 751+ms
{ 500, 376}, // 3 bit(s): min period: 500ms, max period: 750ms, round up from 376+ms
{ 250, 188}, // 4 bit(s): min period: 250ms, max period: 375ms, round up from 188+ms
{ 125, 94}, // 5 bit(s): min period: 125ms, max period: 187ms, round up from 94+ms
{ 63, 47}, // 6 bit(s): min period: 63ms, max period: 93ms, round up from 47+ms
{ 32, 24}, // 7 bit(s): min period: 32ms, max period: 46ms, round up from 24+ms
{ 16, 12}, // 8 bit(s): min period: 16ms, max period: 23ms, round up from 12+ms
{ 8, 6}, // 9 bit(s): min period: 8ms, max period: 11ms, round up from 6+ms
{ 4, 3}, // 10 bit(s): min period: 4ms, max period: 5ms, round up from 3+ms
{ 2, 2}, // 11 bit(s): min period: 2ms, max period: 2ms, round up from 2+ms
{ 1, 1}, // 12 bit(s): min period: 1ms, max period: 1ms, round up from 1+ms
};
// (2^16 * 3) * .030518 ms
/** Maximum WDT timeout in milliseconds */
#define _CYHAL_WDT_MAX_TIMEOUT_MS 6000
/** Maximum number of ignore bits */
#define _CYHAL_WDT_MAX_IGNORE_BITS 12
/** \endcond */
#if defined(__cplusplus)
}
#endif /* __cplusplus */

45
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt_impl_common.h Executable file
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@ -0,0 +1,45 @@
/***************************************************************************//**
* \file cyhal_wdt_impl_common.h
*
* \brief
* Common code for WDT API implementations.
*
********************************************************************************
* \copyright
* Copyright 2019-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/**
* \cond INTERNAL
*/
typedef struct {
uint16_t min_period_ms; // Minimum period in milliseconds that can be represented with this many ignored bits
uint16_t round_threshold_ms; // Timeout threshold in milliseconds from which to round up to the minimum period
// uint32_t pre_match_cycles; // The number of clock cycles in the first two full counter cycles (before the match value matters)
} _cyhal_wdt_ignore_bits_data_t;
/** \endcond */
#if defined(__cplusplus)
}
#endif /* __cplusplus */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -305,6 +305,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[1];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[22];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h Normal file → Executable file
View File

@ -5,11 +5,11 @@
* PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE-USB package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -307,6 +307,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[1];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[22];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_01 device GPIO HAL header for 116-BGA-BLE package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -313,6 +313,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[22];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_01 device GPIO HAL header for 116-BGA-USB package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -313,6 +313,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[22];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_01 device GPIO HAL header for 124-BGA package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -341,6 +341,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[28];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_01 device GPIO HAL header for 124-BGA-SIP package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -322,6 +322,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[22];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_01 device GPIO HAL header for 43-SMT package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -267,6 +267,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[1];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[11];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[4];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_01 device GPIO HAL header for 68-QFN-BLE package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -273,6 +273,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[1];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[2];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[14];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_01 device GPIO HAL header for 80-WLCSP package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -299,6 +299,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p1[1];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[4];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[20];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_02 device GPIO HAL header for 100-WLCSP package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -217,6 +217,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[24];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_02 device GPIO HAL header for 124-BGA package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -237,6 +237,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[28];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_02 device GPIO HAL header for 128-TQFP package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -239,6 +239,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[28];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_02 device GPIO HAL header for 68-QFN package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -187,6 +187,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[20];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_03 device GPIO HAL header for 100-TQFP package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -170,6 +170,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[26];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

21
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_03 device GPIO HAL header for 49-WLCSP package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -55,6 +55,7 @@ typedef enum {
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0
P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1
@ -137,6 +138,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[1];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[15];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[5];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */
@ -148,7 +157,7 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6];
/** Indicates that a pin map exists for scb_spi_m_clk*/
#define CYHAL_PIN_MAP_SCB_SPI_M_CLK
/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[8];
/** Indicates that a pin map exists for scb_spi_m_miso*/
#define CYHAL_PIN_MAP_SCB_SPI_M_MISO
/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */
@ -176,7 +185,7 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[1];
/** Indicates that a pin map exists for scb_spi_s_clk*/
#define CYHAL_PIN_MAP_SCB_SPI_S_CLK
/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[8];
/** Indicates that a pin map exists for scb_spi_s_miso*/
#define CYHAL_PIN_MAP_SCB_SPI_S_MISO
/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */
@ -208,7 +217,7 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6];
/** Indicates that a pin map exists for scb_uart_rts*/
#define CYHAL_PIN_MAP_SCB_UART_RTS
/** List of valid pin to peripheral connections for the scb_uart_rts signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7];
/** Indicates that a pin map exists for scb_uart_rx*/
#define CYHAL_PIN_MAP_SCB_UART_RX
/** List of valid pin to peripheral connections for the scb_uart_rx signal. */
@ -280,7 +289,7 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
/** Indicates that a pin map exists for tcpwm_line*/
#define CYHAL_PIN_MAP_TCPWM_LINE
/** List of valid pin to peripheral connections for the tcpwm_line signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[40];
/** Indicates that a pin map exists for tcpwm_line_compl*/
#define CYHAL_PIN_MAP_TCPWM_LINE_COMPL
/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_03 device GPIO HAL header for 68-QFN package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -159,6 +159,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[24];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_04_64_tqfp.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_04 device GPIO HAL header for 64-TQFP package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -173,6 +173,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p0[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[16];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[24];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_04_68_qfn.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_04 device GPIO HAL header for 68-QFN package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -175,6 +175,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p0[1];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[16];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[24];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

12
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_04_80_tqfp.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_04 device GPIO HAL header for 80-TQFP package
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -182,6 +182,14 @@ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_opamp_vin_p0[2];
#define CYHAL_PIN_MAP_PASS_SARMUX_PADS
/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[16];
/** Indicates that a pin map exists for peri_tr_io_input*/
#define CYHAL_PIN_MAP_PERI_TR_IO_INPUT
/** List of valid pin to peripheral connections for the peri_tr_io_input signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_input[24];
/** Indicates that a pin map exists for peri_tr_io_output*/
#define CYHAL_PIN_MAP_PERI_TR_IO_OUTPUT
/** List of valid pin to peripheral connections for the peri_tr_io_output signal. */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_peri_tr_io_output[6];
/** Indicates that a pin map exists for scb_i2c_scl*/
#define CYHAL_PIN_MAP_SCB_I2C_SCL
/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */

1274
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_01.h Normal file → Executable file
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File diff suppressed because it is too large Load Diff

486
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_02.h Normal file → Executable file
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@ -5,11 +5,11 @@
* PSoC6_02 family HAL triggers header
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -39,122 +39,390 @@
extern "C" {
#endif /* __cplusplus */
/** @brief Name of each input trigger. */
typedef enum
{
CYHAL_TRIGGER_CPUSS_ZERO = 0, //!< cpuss.zero
CYHAL_TRIGGER_AUDIOSS0_TR_I2S_RX_REQ = 1, //!< audioss[0].tr_i2s_rx_req
CYHAL_TRIGGER_AUDIOSS1_TR_I2S_RX_REQ = 2, //!< audioss[1].tr_i2s_rx_req
CYHAL_TRIGGER_AUDIOSS0_TR_I2S_TX_REQ = 3, //!< audioss[0].tr_i2s_tx_req
CYHAL_TRIGGER_AUDIOSS1_TR_I2S_TX_REQ = 4, //!< audioss[1].tr_i2s_tx_req
CYHAL_TRIGGER_AUDIOSS0_TR_PDM_RX_REQ = 5, //!< audioss[0].tr_pdm_rx_req
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = 6, //!< cpuss.cti_tr_out[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = 7, //!< cpuss.cti_tr_out[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = 8, //!< cpuss.dmac_tr_out[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = 9, //!< cpuss.dmac_tr_out[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT2 = 10, //!< cpuss.dmac_tr_out[2]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT3 = 11, //!< cpuss.dmac_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = 12, //!< cpuss.dw0_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = 13, //!< cpuss.dw0_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = 14, //!< cpuss.dw0_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = 15, //!< cpuss.dw0_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = 16, //!< cpuss.dw0_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = 17, //!< cpuss.dw0_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = 18, //!< cpuss.dw0_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = 19, //!< cpuss.dw0_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = 20, //!< cpuss.dw0_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = 21, //!< cpuss.dw0_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = 22, //!< cpuss.dw0_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = 23, //!< cpuss.dw0_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = 24, //!< cpuss.dw0_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = 25, //!< cpuss.dw0_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = 26, //!< cpuss.dw0_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = 27, //!< cpuss.dw0_tr_out[15]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = 28, //!< cpuss.dw0_tr_out[16]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = 29, //!< cpuss.dw0_tr_out[17]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = 30, //!< cpuss.dw0_tr_out[18]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = 31, //!< cpuss.dw0_tr_out[19]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = 32, //!< cpuss.dw0_tr_out[20]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = 33, //!< cpuss.dw0_tr_out[21]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = 34, //!< cpuss.dw0_tr_out[22]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = 35, //!< cpuss.dw0_tr_out[23]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = 36, //!< cpuss.dw0_tr_out[24]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = 37, //!< cpuss.dw0_tr_out[25]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = 38, //!< cpuss.dw0_tr_out[26]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = 39, //!< cpuss.dw0_tr_out[27]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = 40, //!< cpuss.dw0_tr_out[28]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = 41, //!< cpuss.dw1_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = 42, //!< cpuss.dw1_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = 43, //!< cpuss.dw1_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = 44, //!< cpuss.dw1_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = 45, //!< cpuss.dw1_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = 46, //!< cpuss.dw1_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = 47, //!< cpuss.dw1_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = 48, //!< cpuss.dw1_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = 49, //!< cpuss.dw1_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = 50, //!< cpuss.dw1_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = 51, //!< cpuss.dw1_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = 52, //!< cpuss.dw1_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = 53, //!< cpuss.dw1_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = 54, //!< cpuss.dw1_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = 55, //!< cpuss.dw1_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = 56, //!< cpuss.dw1_tr_out[15]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = 57, //!< cpuss.dw1_tr_out[16]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = 58, //!< cpuss.dw1_tr_out[17]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = 59, //!< cpuss.dw1_tr_out[18]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = 60, //!< cpuss.dw1_tr_out[19]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = 61, //!< cpuss.dw1_tr_out[20]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = 62, //!< cpuss.dw1_tr_out[21]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = 63, //!< cpuss.dw1_tr_out[22]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = 64, //!< cpuss.dw1_tr_out[23]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = 65, //!< cpuss.dw1_tr_out[24]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = 66, //!< cpuss.dw1_tr_out[25]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = 67, //!< cpuss.dw1_tr_out[26]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = 68, //!< cpuss.dw1_tr_out[27]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = 69, //!< cpuss.dw1_tr_out[28]
CYHAL_TRIGGER_CPUSS_TR_FAULT0 = 70, //!< cpuss.tr_fault[0]
CYHAL_TRIGGER_CPUSS_TR_FAULT1 = 71, //!< cpuss.tr_fault[1]
CYHAL_TRIGGER_CSD_DSI_SAMPLE_OUT = 72, //!< csd.dsi_sample_out
CYHAL_TRIGGER_CSD_DSI_SENSE_OUT = 73, //!< csd.dsi_sense_out
CYHAL_TRIGGER_CSD_TR_ADC_DONE = 74, //!< csd.tr_adc_done
CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = 75, //!< lpcomp.dsi_comp0
CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = 76, //!< lpcomp.dsi_comp1
CYHAL_TRIGGER_PASS_TR_SAR_OUT = 77, //!< pass.tr_sar_out
CYHAL_TRIGGER_PERI_TR_IO_INPUT0 = 78, //!< peri.tr_io_input[0]
CYHAL_TRIGGER_PERI_TR_IO_INPUT1 = 79, //!< peri.tr_io_input[1]
CYHAL_TRIGGER_PERI_TR_IO_INPUT2 = 80, //!< peri.tr_io_input[2]
CYHAL_TRIGGER_PERI_TR_IO_INPUT3 = 81, //!< peri.tr_io_input[3]
CYHAL_TRIGGER_PERI_TR_IO_INPUT4 = 82, //!< peri.tr_io_input[4]
CYHAL_TRIGGER_PERI_TR_IO_INPUT5 = 83, //!< peri.tr_io_input[5]
CYHAL_TRIGGER_PERI_TR_IO_INPUT6 = 84, //!< peri.tr_io_input[6]
CYHAL_TRIGGER_PERI_TR_IO_INPUT7 = 85, //!< peri.tr_io_input[7]
CYHAL_TRIGGER_PERI_TR_IO_INPUT8 = 86, //!< peri.tr_io_input[8]
CYHAL_TRIGGER_PERI_TR_IO_INPUT9 = 87, //!< peri.tr_io_input[9]
CYHAL_TRIGGER_PERI_TR_IO_INPUT10 = 88, //!< peri.tr_io_input[10]
CYHAL_TRIGGER_PERI_TR_IO_INPUT11 = 89, //!< peri.tr_io_input[11]
CYHAL_TRIGGER_PERI_TR_IO_INPUT12 = 90, //!< peri.tr_io_input[12]
CYHAL_TRIGGER_PERI_TR_IO_INPUT13 = 91, //!< peri.tr_io_input[13]
CYHAL_TRIGGER_PERI_TR_IO_INPUT14 = 92, //!< peri.tr_io_input[14]
CYHAL_TRIGGER_PERI_TR_IO_INPUT15 = 93, //!< peri.tr_io_input[15]
CYHAL_TRIGGER_PERI_TR_IO_INPUT16 = 94, //!< peri.tr_io_input[16]
CYHAL_TRIGGER_PERI_TR_IO_INPUT17 = 95, //!< peri.tr_io_input[17]
CYHAL_TRIGGER_PERI_TR_IO_INPUT18 = 96, //!< peri.tr_io_input[18]
CYHAL_TRIGGER_PERI_TR_IO_INPUT19 = 97, //!< peri.tr_io_input[19]
CYHAL_TRIGGER_PERI_TR_IO_INPUT20 = 98, //!< peri.tr_io_input[20]
CYHAL_TRIGGER_PERI_TR_IO_INPUT21 = 99, //!< peri.tr_io_input[21]
CYHAL_TRIGGER_PERI_TR_IO_INPUT22 = 100, //!< peri.tr_io_input[22]
CYHAL_TRIGGER_PERI_TR_IO_INPUT23 = 101, //!< peri.tr_io_input[23]
CYHAL_TRIGGER_PERI_TR_IO_INPUT24 = 102, //!< peri.tr_io_input[24]
CYHAL_TRIGGER_PERI_TR_IO_INPUT25 = 103, //!< peri.tr_io_input[25]
CYHAL_TRIGGER_PERI_TR_IO_INPUT26 = 104, //!< peri.tr_io_input[26]
CYHAL_TRIGGER_PERI_TR_IO_INPUT27 = 105, //!< peri.tr_io_input[27]
CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 106, //!< scb[0].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 107, //!< scb[1].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 108, //!< scb[2].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 109, //!< scb[3].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 110, //!< scb[4].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 111, //!< scb[5].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 112, //!< scb[6].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB7_TR_I2C_SCL_FILTERED = 113, //!< scb[7].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB8_TR_I2C_SCL_FILTERED = 114, //!< scb[8].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB9_TR_I2C_SCL_FILTERED = 115, //!< scb[9].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB10_TR_I2C_SCL_FILTERED = 116, //!< scb[10].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB11_TR_I2C_SCL_FILTERED = 117, //!< scb[11].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB12_TR_I2C_SCL_FILTERED = 118, //!< scb[12].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB0_TR_RX_REQ = 119, //!< scb[0].tr_rx_req
CYHAL_TRIGGER_SCB1_TR_RX_REQ = 120, //!< scb[1].tr_rx_req
CYHAL_TRIGGER_SCB2_TR_RX_REQ = 121, //!< scb[2].tr_rx_req
CYHAL_TRIGGER_SCB3_TR_RX_REQ = 122, //!< scb[3].tr_rx_req
CYHAL_TRIGGER_SCB4_TR_RX_REQ = 123, //!< scb[4].tr_rx_req
CYHAL_TRIGGER_SCB5_TR_RX_REQ = 124, //!< scb[5].tr_rx_req
CYHAL_TRIGGER_SCB6_TR_RX_REQ = 125, //!< scb[6].tr_rx_req
CYHAL_TRIGGER_SCB7_TR_RX_REQ = 126, //!< scb[7].tr_rx_req
CYHAL_TRIGGER_SCB8_TR_RX_REQ = 127, //!< scb[8].tr_rx_req
CYHAL_TRIGGER_SCB9_TR_RX_REQ = 128, //!< scb[9].tr_rx_req
CYHAL_TRIGGER_SCB10_TR_RX_REQ = 129, //!< scb[10].tr_rx_req
CYHAL_TRIGGER_SCB11_TR_RX_REQ = 130, //!< scb[11].tr_rx_req
CYHAL_TRIGGER_SCB12_TR_RX_REQ = 131, //!< scb[12].tr_rx_req
CYHAL_TRIGGER_SCB0_TR_TX_REQ = 132, //!< scb[0].tr_tx_req
CYHAL_TRIGGER_SCB1_TR_TX_REQ = 133, //!< scb[1].tr_tx_req
CYHAL_TRIGGER_SCB2_TR_TX_REQ = 134, //!< scb[2].tr_tx_req
CYHAL_TRIGGER_SCB3_TR_TX_REQ = 135, //!< scb[3].tr_tx_req
CYHAL_TRIGGER_SCB4_TR_TX_REQ = 136, //!< scb[4].tr_tx_req
CYHAL_TRIGGER_SCB5_TR_TX_REQ = 137, //!< scb[5].tr_tx_req
CYHAL_TRIGGER_SCB6_TR_TX_REQ = 138, //!< scb[6].tr_tx_req
CYHAL_TRIGGER_SCB7_TR_TX_REQ = 139, //!< scb[7].tr_tx_req
CYHAL_TRIGGER_SCB8_TR_TX_REQ = 140, //!< scb[8].tr_tx_req
CYHAL_TRIGGER_SCB9_TR_TX_REQ = 141, //!< scb[9].tr_tx_req
CYHAL_TRIGGER_SCB10_TR_TX_REQ = 142, //!< scb[10].tr_tx_req
CYHAL_TRIGGER_SCB11_TR_TX_REQ = 143, //!< scb[11].tr_tx_req
CYHAL_TRIGGER_SCB12_TR_TX_REQ = 144, //!< scb[12].tr_tx_req
CYHAL_TRIGGER_SMIF_TR_RX_REQ = 145, //!< smif.tr_rx_req
CYHAL_TRIGGER_SMIF_TR_TX_REQ = 146, //!< smif.tr_tx_req
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0 = 147, //!< tcpwm[0].tr_compare_match[0]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1 = 148, //!< tcpwm[0].tr_compare_match[1]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2 = 149, //!< tcpwm[0].tr_compare_match[2]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3 = 150, //!< tcpwm[0].tr_compare_match[3]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH4 = 151, //!< tcpwm[0].tr_compare_match[4]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH5 = 152, //!< tcpwm[0].tr_compare_match[5]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH6 = 153, //!< tcpwm[0].tr_compare_match[6]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH7 = 154, //!< tcpwm[0].tr_compare_match[7]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0 = 155, //!< tcpwm[1].tr_compare_match[0]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1 = 156, //!< tcpwm[1].tr_compare_match[1]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2 = 157, //!< tcpwm[1].tr_compare_match[2]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3 = 158, //!< tcpwm[1].tr_compare_match[3]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4 = 159, //!< tcpwm[1].tr_compare_match[4]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5 = 160, //!< tcpwm[1].tr_compare_match[5]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6 = 161, //!< tcpwm[1].tr_compare_match[6]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7 = 162, //!< tcpwm[1].tr_compare_match[7]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH8 = 163, //!< tcpwm[1].tr_compare_match[8]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH9 = 164, //!< tcpwm[1].tr_compare_match[9]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH10 = 165, //!< tcpwm[1].tr_compare_match[10]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH11 = 166, //!< tcpwm[1].tr_compare_match[11]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH12 = 167, //!< tcpwm[1].tr_compare_match[12]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH13 = 168, //!< tcpwm[1].tr_compare_match[13]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH14 = 169, //!< tcpwm[1].tr_compare_match[14]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH15 = 170, //!< tcpwm[1].tr_compare_match[15]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH16 = 171, //!< tcpwm[1].tr_compare_match[16]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH17 = 172, //!< tcpwm[1].tr_compare_match[17]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH18 = 173, //!< tcpwm[1].tr_compare_match[18]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH19 = 174, //!< tcpwm[1].tr_compare_match[19]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH20 = 175, //!< tcpwm[1].tr_compare_match[20]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH21 = 176, //!< tcpwm[1].tr_compare_match[21]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH22 = 177, //!< tcpwm[1].tr_compare_match[22]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH23 = 178, //!< tcpwm[1].tr_compare_match[23]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0 = 179, //!< tcpwm[0].tr_overflow[0]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1 = 180, //!< tcpwm[0].tr_overflow[1]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2 = 181, //!< tcpwm[0].tr_overflow[2]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3 = 182, //!< tcpwm[0].tr_overflow[3]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW4 = 183, //!< tcpwm[0].tr_overflow[4]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW5 = 184, //!< tcpwm[0].tr_overflow[5]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW6 = 185, //!< tcpwm[0].tr_overflow[6]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW7 = 186, //!< tcpwm[0].tr_overflow[7]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0 = 187, //!< tcpwm[1].tr_overflow[0]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1 = 188, //!< tcpwm[1].tr_overflow[1]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2 = 189, //!< tcpwm[1].tr_overflow[2]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3 = 190, //!< tcpwm[1].tr_overflow[3]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4 = 191, //!< tcpwm[1].tr_overflow[4]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5 = 192, //!< tcpwm[1].tr_overflow[5]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6 = 193, //!< tcpwm[1].tr_overflow[6]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7 = 194, //!< tcpwm[1].tr_overflow[7]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW8 = 195, //!< tcpwm[1].tr_overflow[8]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW9 = 196, //!< tcpwm[1].tr_overflow[9]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW10 = 197, //!< tcpwm[1].tr_overflow[10]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW11 = 198, //!< tcpwm[1].tr_overflow[11]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW12 = 199, //!< tcpwm[1].tr_overflow[12]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW13 = 200, //!< tcpwm[1].tr_overflow[13]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW14 = 201, //!< tcpwm[1].tr_overflow[14]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW15 = 202, //!< tcpwm[1].tr_overflow[15]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW16 = 203, //!< tcpwm[1].tr_overflow[16]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW17 = 204, //!< tcpwm[1].tr_overflow[17]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW18 = 205, //!< tcpwm[1].tr_overflow[18]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW19 = 206, //!< tcpwm[1].tr_overflow[19]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW20 = 207, //!< tcpwm[1].tr_overflow[20]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW21 = 208, //!< tcpwm[1].tr_overflow[21]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW22 = 209, //!< tcpwm[1].tr_overflow[22]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW23 = 210, //!< tcpwm[1].tr_overflow[23]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0 = 211, //!< tcpwm[0].tr_underflow[0]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1 = 212, //!< tcpwm[0].tr_underflow[1]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2 = 213, //!< tcpwm[0].tr_underflow[2]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3 = 214, //!< tcpwm[0].tr_underflow[3]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW4 = 215, //!< tcpwm[0].tr_underflow[4]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW5 = 216, //!< tcpwm[0].tr_underflow[5]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW6 = 217, //!< tcpwm[0].tr_underflow[6]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW7 = 218, //!< tcpwm[0].tr_underflow[7]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0 = 219, //!< tcpwm[1].tr_underflow[0]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1 = 220, //!< tcpwm[1].tr_underflow[1]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2 = 221, //!< tcpwm[1].tr_underflow[2]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3 = 222, //!< tcpwm[1].tr_underflow[3]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4 = 223, //!< tcpwm[1].tr_underflow[4]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5 = 224, //!< tcpwm[1].tr_underflow[5]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6 = 225, //!< tcpwm[1].tr_underflow[6]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7 = 226, //!< tcpwm[1].tr_underflow[7]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW8 = 227, //!< tcpwm[1].tr_underflow[8]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW9 = 228, //!< tcpwm[1].tr_underflow[9]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW10 = 229, //!< tcpwm[1].tr_underflow[10]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW11 = 230, //!< tcpwm[1].tr_underflow[11]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW12 = 231, //!< tcpwm[1].tr_underflow[12]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW13 = 232, //!< tcpwm[1].tr_underflow[13]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW14 = 233, //!< tcpwm[1].tr_underflow[14]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW15 = 234, //!< tcpwm[1].tr_underflow[15]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW16 = 235, //!< tcpwm[1].tr_underflow[16]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW17 = 236, //!< tcpwm[1].tr_underflow[17]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW18 = 237, //!< tcpwm[1].tr_underflow[18]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW19 = 238, //!< tcpwm[1].tr_underflow[19]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW20 = 239, //!< tcpwm[1].tr_underflow[20]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW21 = 240, //!< tcpwm[1].tr_underflow[21]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW22 = 241, //!< tcpwm[1].tr_underflow[22]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW23 = 242, //!< tcpwm[1].tr_underflow[23]
CYHAL_TRIGGER_USB_DMA_REQ0 = 243, //!< usb.dma_req[0]
CYHAL_TRIGGER_USB_DMA_REQ1 = 244, //!< usb.dma_req[1]
CYHAL_TRIGGER_USB_DMA_REQ2 = 245, //!< usb.dma_req[2]
CYHAL_TRIGGER_USB_DMA_REQ3 = 246, //!< usb.dma_req[3]
CYHAL_TRIGGER_USB_DMA_REQ4 = 247, //!< usb.dma_req[4]
CYHAL_TRIGGER_USB_DMA_REQ5 = 248, //!< usb.dma_req[5]
CYHAL_TRIGGER_USB_DMA_REQ6 = 249, //!< usb.dma_req[6]
CYHAL_TRIGGER_USB_DMA_REQ7 = 250, //!< usb.dma_req[7]
} cyhal_trigger_source_psoc6_02_t;
/** Typedef from device family specific trigger source to generic trigger source */
typedef cyhal_trigger_source_psoc6_02_t cyhal_source_t;
/** @brief Name of each output trigger. */
typedef enum
{
TRIGGER_CPUSS_CTI_TR_IN0 = 0, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[0]
TRIGGER_CPUSS_CTI_TR_IN1 = 1, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[1]
TRIGGER_CPUSS_DMAC_TR_IN0 = 2, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0]
TRIGGER_CPUSS_DMAC_TR_IN1 = 3, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1]
TRIGGER_CPUSS_DMAC_TR_IN2 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[2]
TRIGGER_CPUSS_DMAC_TR_IN3 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[3]
TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0]
TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1]
TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2]
TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3]
TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4]
TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5]
TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6]
TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7]
TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8]
TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9]
TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10]
TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11]
TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12]
TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13]
TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14]
TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15]
TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[16]
TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[17]
TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[18]
TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[19]
TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[20]
TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[21]
TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[22]
TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[23]
TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[24]
TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[25]
TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[26]
TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[27]
TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA0 direct connect - cpuss.dw0_tr_in[28]
TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0]
TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1]
TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2]
TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3]
TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4]
TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5]
TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6]
TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7]
TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8]
TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9]
TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10]
TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11]
TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12]
TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13]
TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14]
TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15]
TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16]
TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17]
TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18]
TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19]
TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20]
TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21]
TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22]
TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23]
TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[24]
TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[25]
TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[26]
TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[27]
TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[28]
TRIGGER_CSD_DSI_START = 64, //!< Capsense trigger multiplexer - csd.dsi_start
TRIGGER_PASS_TR_SAR_IN = 65, //!< ADC trigger multiplexer - pass.tr_sar_in
TRIGGER_PERI_TR_DBG_FREEZE = 66, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze
TRIGGER_PERI_TR_IO_OUTPUT0 = 67, //!< HSIOM trigger multiplexer - peri.tr_io_output[0]
TRIGGER_PERI_TR_IO_OUTPUT1 = 68, //!< HSIOM trigger multiplexer - peri.tr_io_output[1]
TRIGGER_PROFILE_TR_START = 69, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_start
TRIGGER_PROFILE_TR_STOP = 70, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_stop
TRIGGER_TCPWM0_TR_IN0 = 71, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0]
TRIGGER_TCPWM0_TR_IN1 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1]
TRIGGER_TCPWM0_TR_IN2 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2]
TRIGGER_TCPWM0_TR_IN3 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3]
TRIGGER_TCPWM0_TR_IN4 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4]
TRIGGER_TCPWM0_TR_IN5 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5]
TRIGGER_TCPWM0_TR_IN6 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6]
TRIGGER_TCPWM0_TR_IN7 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7]
TRIGGER_TCPWM0_TR_IN8 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8]
TRIGGER_TCPWM0_TR_IN9 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9]
TRIGGER_TCPWM0_TR_IN10 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10]
TRIGGER_TCPWM0_TR_IN11 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11]
TRIGGER_TCPWM0_TR_IN12 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12]
TRIGGER_TCPWM0_TR_IN13 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13]
TRIGGER_TCPWM1_TR_IN0 = 85, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0]
TRIGGER_TCPWM1_TR_IN1 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1]
TRIGGER_TCPWM1_TR_IN2 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2]
TRIGGER_TCPWM1_TR_IN3 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3]
TRIGGER_TCPWM1_TR_IN4 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4]
TRIGGER_TCPWM1_TR_IN5 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5]
TRIGGER_TCPWM1_TR_IN6 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6]
TRIGGER_TCPWM1_TR_IN7 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7]
TRIGGER_TCPWM1_TR_IN8 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8]
TRIGGER_TCPWM1_TR_IN9 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9]
TRIGGER_TCPWM1_TR_IN10 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10]
TRIGGER_TCPWM1_TR_IN11 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11]
TRIGGER_TCPWM1_TR_IN12 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12]
TRIGGER_TCPWM1_TR_IN13 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13]
TRIGGER_USB_DMA_BURSTEND0 = 99, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0]
TRIGGER_USB_DMA_BURSTEND1 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1]
TRIGGER_USB_DMA_BURSTEND2 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2]
TRIGGER_USB_DMA_BURSTEND3 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3]
TRIGGER_USB_DMA_BURSTEND4 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4]
TRIGGER_USB_DMA_BURSTEND5 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5]
TRIGGER_USB_DMA_BURSTEND6 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6]
TRIGGER_USB_DMA_BURSTEND7 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7]
CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 0, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 1, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 2, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 3, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN2 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[2]
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN3 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[16]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[17]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[18]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[19]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[20]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[21]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[22]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[23]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[24]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[25]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[26]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[27]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA0 direct connect - cpuss.dw0_tr_in[28]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[24]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[25]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[26]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[27]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[28]
CYHAL_TRIGGER_CSD_DSI_START = 64, //!< Capsense trigger multiplexer - csd.dsi_start
CYHAL_TRIGGER_PASS_TR_SAR_IN = 65, //!< ADC trigger multiplexer - pass.tr_sar_in
CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 66, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze
CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 67, //!< HSIOM trigger multiplexer - peri.tr_io_output[0]
CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 68, //!< HSIOM trigger multiplexer - peri.tr_io_output[1]
CYHAL_TRIGGER_PROFILE_TR_START = 69, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_start
CYHAL_TRIGGER_PROFILE_TR_STOP = 70, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_stop
CYHAL_TRIGGER_TCPWM0_TR_IN0 = 71, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0]
CYHAL_TRIGGER_TCPWM0_TR_IN1 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1]
CYHAL_TRIGGER_TCPWM0_TR_IN2 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2]
CYHAL_TRIGGER_TCPWM0_TR_IN3 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3]
CYHAL_TRIGGER_TCPWM0_TR_IN4 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4]
CYHAL_TRIGGER_TCPWM0_TR_IN5 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5]
CYHAL_TRIGGER_TCPWM0_TR_IN6 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6]
CYHAL_TRIGGER_TCPWM0_TR_IN7 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7]
CYHAL_TRIGGER_TCPWM0_TR_IN8 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8]
CYHAL_TRIGGER_TCPWM0_TR_IN9 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9]
CYHAL_TRIGGER_TCPWM0_TR_IN10 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10]
CYHAL_TRIGGER_TCPWM0_TR_IN11 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11]
CYHAL_TRIGGER_TCPWM0_TR_IN12 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12]
CYHAL_TRIGGER_TCPWM0_TR_IN13 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13]
CYHAL_TRIGGER_TCPWM1_TR_IN0 = 85, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0]
CYHAL_TRIGGER_TCPWM1_TR_IN1 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1]
CYHAL_TRIGGER_TCPWM1_TR_IN2 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2]
CYHAL_TRIGGER_TCPWM1_TR_IN3 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3]
CYHAL_TRIGGER_TCPWM1_TR_IN4 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4]
CYHAL_TRIGGER_TCPWM1_TR_IN5 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5]
CYHAL_TRIGGER_TCPWM1_TR_IN6 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6]
CYHAL_TRIGGER_TCPWM1_TR_IN7 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7]
CYHAL_TRIGGER_TCPWM1_TR_IN8 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8]
CYHAL_TRIGGER_TCPWM1_TR_IN9 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9]
CYHAL_TRIGGER_TCPWM1_TR_IN10 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10]
CYHAL_TRIGGER_TCPWM1_TR_IN11 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11]
CYHAL_TRIGGER_TCPWM1_TR_IN12 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12]
CYHAL_TRIGGER_TCPWM1_TR_IN13 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13]
CYHAL_TRIGGER_USB_DMA_BURSTEND0 = 99, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0]
CYHAL_TRIGGER_USB_DMA_BURSTEND1 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1]
CYHAL_TRIGGER_USB_DMA_BURSTEND2 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2]
CYHAL_TRIGGER_USB_DMA_BURSTEND3 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3]
CYHAL_TRIGGER_USB_DMA_BURSTEND4 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4]
CYHAL_TRIGGER_USB_DMA_BURSTEND5 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5]
CYHAL_TRIGGER_USB_DMA_BURSTEND6 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6]
CYHAL_TRIGGER_USB_DMA_BURSTEND7 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7]
} cyhal_trigger_dest_psoc6_02_t;
/** Typedef from device family specific trigger dest to generic trigger dest */
typedef cyhal_trigger_dest_psoc6_02_t cyhal_dest_t;
/** \cond INTERNAL */
/** Table of number of inputs to each mux. */
extern const uint16_t cyhal_sources_per_mux[17];
/** Table indicating whether mux is 1to1. */
extern const bool cyhal_is_mux_1to1[17];
/** Table pointing to each mux source table. The index of each source in the table is its mux input index. */
extern const cyhal_source_t* cyhal_mux_to_sources [17];
/** Maps each cyhal_destination_t to a mux index.
* If bit 8 of the mux index is set, this denotes that the trigger is a
* one to one trigger.

408
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_03.h Normal file → Executable file
View File

@ -5,11 +5,11 @@
* PSoC6_03 family HAL triggers header
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -39,123 +39,311 @@
extern "C" {
#endif /* __cplusplus */
/** @brief Name of each input trigger. */
typedef enum
{
CYHAL_TRIGGER_CPUSS_ZERO = 0, //!< cpuss.zero
CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = 1, //!< canfd[0].tr_dbg_dma_req[0]
CYHAL_TRIGGER_CANFD0_TR_FIFO00 = 2, //!< canfd[0].tr_fifo0[0]
CYHAL_TRIGGER_CANFD0_TR_FIFO10 = 3, //!< canfd[0].tr_fifo1[0]
CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = 4, //!< canfd[0].tr_tmp_rtp_out[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = 5, //!< cpuss.cti_tr_out[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = 6, //!< cpuss.cti_tr_out[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = 7, //!< cpuss.dmac_tr_out[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = 8, //!< cpuss.dmac_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = 9, //!< cpuss.dw0_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = 10, //!< cpuss.dw0_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = 11, //!< cpuss.dw0_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = 12, //!< cpuss.dw0_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = 13, //!< cpuss.dw0_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = 14, //!< cpuss.dw0_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = 15, //!< cpuss.dw0_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = 16, //!< cpuss.dw0_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = 17, //!< cpuss.dw0_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = 18, //!< cpuss.dw0_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = 19, //!< cpuss.dw0_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = 20, //!< cpuss.dw0_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = 21, //!< cpuss.dw0_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = 22, //!< cpuss.dw0_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = 23, //!< cpuss.dw0_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = 24, //!< cpuss.dw0_tr_out[15]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = 25, //!< cpuss.dw0_tr_out[16]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = 26, //!< cpuss.dw0_tr_out[17]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = 27, //!< cpuss.dw0_tr_out[18]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = 28, //!< cpuss.dw0_tr_out[19]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = 29, //!< cpuss.dw0_tr_out[20]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = 30, //!< cpuss.dw0_tr_out[21]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = 31, //!< cpuss.dw0_tr_out[22]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = 32, //!< cpuss.dw0_tr_out[23]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = 33, //!< cpuss.dw0_tr_out[24]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = 34, //!< cpuss.dw0_tr_out[25]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = 35, //!< cpuss.dw0_tr_out[26]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = 36, //!< cpuss.dw0_tr_out[27]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = 37, //!< cpuss.dw0_tr_out[28]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = 38, //!< cpuss.dw1_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = 39, //!< cpuss.dw1_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = 40, //!< cpuss.dw1_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = 41, //!< cpuss.dw1_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = 42, //!< cpuss.dw1_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = 43, //!< cpuss.dw1_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = 44, //!< cpuss.dw1_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = 45, //!< cpuss.dw1_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = 46, //!< cpuss.dw1_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = 47, //!< cpuss.dw1_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = 48, //!< cpuss.dw1_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = 49, //!< cpuss.dw1_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = 50, //!< cpuss.dw1_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = 51, //!< cpuss.dw1_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = 52, //!< cpuss.dw1_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = 53, //!< cpuss.dw1_tr_out[15]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = 54, //!< cpuss.dw1_tr_out[16]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = 55, //!< cpuss.dw1_tr_out[17]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = 56, //!< cpuss.dw1_tr_out[18]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = 57, //!< cpuss.dw1_tr_out[19]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = 58, //!< cpuss.dw1_tr_out[20]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = 59, //!< cpuss.dw1_tr_out[21]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = 60, //!< cpuss.dw1_tr_out[22]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = 61, //!< cpuss.dw1_tr_out[23]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = 62, //!< cpuss.dw1_tr_out[24]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = 63, //!< cpuss.dw1_tr_out[25]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = 64, //!< cpuss.dw1_tr_out[26]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = 65, //!< cpuss.dw1_tr_out[27]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = 66, //!< cpuss.dw1_tr_out[28]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = 67, //!< cpuss.dw1_tr_out[29]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = 68, //!< cpuss.dw1_tr_out[30]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = 69, //!< cpuss.dw1_tr_out[31]
CYHAL_TRIGGER_CPUSS_TR_FAULT0 = 70, //!< cpuss.tr_fault[0]
CYHAL_TRIGGER_CPUSS_TR_FAULT1 = 71, //!< cpuss.tr_fault[1]
CYHAL_TRIGGER_CSD_DSI_SAMPLE_OUT = 72, //!< csd.dsi_sample_out
CYHAL_TRIGGER_CSD_DSI_SENSE_OUT = 73, //!< csd.dsi_sense_out
CYHAL_TRIGGER_CSD_TR_ADC_DONE = 74, //!< csd.tr_adc_done
CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = 75, //!< lpcomp.dsi_comp0
CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = 76, //!< lpcomp.dsi_comp1
CYHAL_TRIGGER_PASS_TR_SAR_OUT = 77, //!< pass.tr_sar_out
CYHAL_TRIGGER_PERI_TR_IO_INPUT0 = 78, //!< peri.tr_io_input[0]
CYHAL_TRIGGER_PERI_TR_IO_INPUT1 = 79, //!< peri.tr_io_input[1]
CYHAL_TRIGGER_PERI_TR_IO_INPUT2 = 80, //!< peri.tr_io_input[2]
CYHAL_TRIGGER_PERI_TR_IO_INPUT3 = 81, //!< peri.tr_io_input[3]
CYHAL_TRIGGER_PERI_TR_IO_INPUT4 = 82, //!< peri.tr_io_input[4]
CYHAL_TRIGGER_PERI_TR_IO_INPUT5 = 83, //!< peri.tr_io_input[5]
CYHAL_TRIGGER_PERI_TR_IO_INPUT6 = 84, //!< peri.tr_io_input[6]
CYHAL_TRIGGER_PERI_TR_IO_INPUT7 = 85, //!< peri.tr_io_input[7]
CYHAL_TRIGGER_PERI_TR_IO_INPUT8 = 86, //!< peri.tr_io_input[8]
CYHAL_TRIGGER_PERI_TR_IO_INPUT9 = 87, //!< peri.tr_io_input[9]
CYHAL_TRIGGER_PERI_TR_IO_INPUT10 = 88, //!< peri.tr_io_input[10]
CYHAL_TRIGGER_PERI_TR_IO_INPUT11 = 89, //!< peri.tr_io_input[11]
CYHAL_TRIGGER_PERI_TR_IO_INPUT12 = 90, //!< peri.tr_io_input[12]
CYHAL_TRIGGER_PERI_TR_IO_INPUT13 = 91, //!< peri.tr_io_input[13]
CYHAL_TRIGGER_PERI_TR_IO_INPUT14 = 92, //!< peri.tr_io_input[14]
CYHAL_TRIGGER_PERI_TR_IO_INPUT15 = 93, //!< peri.tr_io_input[15]
CYHAL_TRIGGER_PERI_TR_IO_INPUT16 = 94, //!< peri.tr_io_input[16]
CYHAL_TRIGGER_PERI_TR_IO_INPUT17 = 95, //!< peri.tr_io_input[17]
CYHAL_TRIGGER_PERI_TR_IO_INPUT18 = 96, //!< peri.tr_io_input[18]
CYHAL_TRIGGER_PERI_TR_IO_INPUT19 = 97, //!< peri.tr_io_input[19]
CYHAL_TRIGGER_PERI_TR_IO_INPUT20 = 98, //!< peri.tr_io_input[20]
CYHAL_TRIGGER_PERI_TR_IO_INPUT21 = 99, //!< peri.tr_io_input[21]
CYHAL_TRIGGER_PERI_TR_IO_INPUT22 = 100, //!< peri.tr_io_input[22]
CYHAL_TRIGGER_PERI_TR_IO_INPUT23 = 101, //!< peri.tr_io_input[23]
CYHAL_TRIGGER_PERI_TR_IO_INPUT24 = 102, //!< peri.tr_io_input[24]
CYHAL_TRIGGER_PERI_TR_IO_INPUT25 = 103, //!< peri.tr_io_input[25]
CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 104, //!< scb[0].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 105, //!< scb[1].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 106, //!< scb[2].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB3_TR_I2C_SCL_FILTERED = 107, //!< scb[3].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 108, //!< scb[4].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 109, //!< scb[5].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 110, //!< scb[6].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB0_TR_RX_REQ = 111, //!< scb[0].tr_rx_req
CYHAL_TRIGGER_SCB1_TR_RX_REQ = 112, //!< scb[1].tr_rx_req
CYHAL_TRIGGER_SCB2_TR_RX_REQ = 113, //!< scb[2].tr_rx_req
CYHAL_TRIGGER_SCB3_TR_RX_REQ = 114, //!< scb[3].tr_rx_req
CYHAL_TRIGGER_SCB4_TR_RX_REQ = 115, //!< scb[4].tr_rx_req
CYHAL_TRIGGER_SCB5_TR_RX_REQ = 116, //!< scb[5].tr_rx_req
CYHAL_TRIGGER_SCB6_TR_RX_REQ = 117, //!< scb[6].tr_rx_req
CYHAL_TRIGGER_SCB0_TR_TX_REQ = 118, //!< scb[0].tr_tx_req
CYHAL_TRIGGER_SCB1_TR_TX_REQ = 119, //!< scb[1].tr_tx_req
CYHAL_TRIGGER_SCB2_TR_TX_REQ = 120, //!< scb[2].tr_tx_req
CYHAL_TRIGGER_SCB3_TR_TX_REQ = 121, //!< scb[3].tr_tx_req
CYHAL_TRIGGER_SCB4_TR_TX_REQ = 122, //!< scb[4].tr_tx_req
CYHAL_TRIGGER_SCB5_TR_TX_REQ = 123, //!< scb[5].tr_tx_req
CYHAL_TRIGGER_SCB6_TR_TX_REQ = 124, //!< scb[6].tr_tx_req
CYHAL_TRIGGER_SMIF_TR_RX_REQ = 125, //!< smif.tr_rx_req
CYHAL_TRIGGER_SMIF_TR_TX_REQ = 126, //!< smif.tr_tx_req
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH0 = 127, //!< tcpwm[0].tr_compare_match[0]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH1 = 128, //!< tcpwm[0].tr_compare_match[1]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH2 = 129, //!< tcpwm[0].tr_compare_match[2]
CYHAL_TRIGGER_TCPWM0_TR_COMPARE_MATCH3 = 130, //!< tcpwm[0].tr_compare_match[3]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH0 = 131, //!< tcpwm[1].tr_compare_match[0]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH1 = 132, //!< tcpwm[1].tr_compare_match[1]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH2 = 133, //!< tcpwm[1].tr_compare_match[2]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH3 = 134, //!< tcpwm[1].tr_compare_match[3]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH4 = 135, //!< tcpwm[1].tr_compare_match[4]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH5 = 136, //!< tcpwm[1].tr_compare_match[5]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH6 = 137, //!< tcpwm[1].tr_compare_match[6]
CYHAL_TRIGGER_TCPWM1_TR_COMPARE_MATCH7 = 138, //!< tcpwm[1].tr_compare_match[7]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW0 = 139, //!< tcpwm[0].tr_overflow[0]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW1 = 140, //!< tcpwm[0].tr_overflow[1]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW2 = 141, //!< tcpwm[0].tr_overflow[2]
CYHAL_TRIGGER_TCPWM0_TR_OVERFLOW3 = 142, //!< tcpwm[0].tr_overflow[3]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW0 = 143, //!< tcpwm[1].tr_overflow[0]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW1 = 144, //!< tcpwm[1].tr_overflow[1]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW2 = 145, //!< tcpwm[1].tr_overflow[2]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW3 = 146, //!< tcpwm[1].tr_overflow[3]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW4 = 147, //!< tcpwm[1].tr_overflow[4]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW5 = 148, //!< tcpwm[1].tr_overflow[5]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW6 = 149, //!< tcpwm[1].tr_overflow[6]
CYHAL_TRIGGER_TCPWM1_TR_OVERFLOW7 = 150, //!< tcpwm[1].tr_overflow[7]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW0 = 151, //!< tcpwm[0].tr_underflow[0]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW1 = 152, //!< tcpwm[0].tr_underflow[1]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW2 = 153, //!< tcpwm[0].tr_underflow[2]
CYHAL_TRIGGER_TCPWM0_TR_UNDERFLOW3 = 154, //!< tcpwm[0].tr_underflow[3]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW0 = 155, //!< tcpwm[1].tr_underflow[0]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW1 = 156, //!< tcpwm[1].tr_underflow[1]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW2 = 157, //!< tcpwm[1].tr_underflow[2]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW3 = 158, //!< tcpwm[1].tr_underflow[3]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW4 = 159, //!< tcpwm[1].tr_underflow[4]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW5 = 160, //!< tcpwm[1].tr_underflow[5]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW6 = 161, //!< tcpwm[1].tr_underflow[6]
CYHAL_TRIGGER_TCPWM1_TR_UNDERFLOW7 = 162, //!< tcpwm[1].tr_underflow[7]
CYHAL_TRIGGER_USB_DMA_REQ0 = 163, //!< usb.dma_req[0]
CYHAL_TRIGGER_USB_DMA_REQ1 = 164, //!< usb.dma_req[1]
CYHAL_TRIGGER_USB_DMA_REQ2 = 165, //!< usb.dma_req[2]
CYHAL_TRIGGER_USB_DMA_REQ3 = 166, //!< usb.dma_req[3]
CYHAL_TRIGGER_USB_DMA_REQ4 = 167, //!< usb.dma_req[4]
CYHAL_TRIGGER_USB_DMA_REQ5 = 168, //!< usb.dma_req[5]
CYHAL_TRIGGER_USB_DMA_REQ6 = 169, //!< usb.dma_req[6]
CYHAL_TRIGGER_USB_DMA_REQ7 = 170, //!< usb.dma_req[7]
} cyhal_trigger_source_psoc6_03_t;
/** Typedef from device family specific trigger source to generic trigger source */
typedef cyhal_trigger_source_psoc6_03_t cyhal_source_t;
/** @brief Name of each output trigger. */
typedef enum
{
TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0]
TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 1, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0]
TRIGGER_CPUSS_CTI_TR_IN0 = 2, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[0]
TRIGGER_CPUSS_CTI_TR_IN1 = 3, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[1]
TRIGGER_CPUSS_DMAC_TR_IN0 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0]
TRIGGER_CPUSS_DMAC_TR_IN1 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1]
TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[0]
TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[1]
TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[2]
TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[3]
TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[4]
TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[5]
TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[6]
TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[7]
TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8]
TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9]
TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10]
TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11]
TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12]
TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13]
TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14]
TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15]
TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[16]
TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[17]
TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[18]
TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[19]
TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[20]
TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[21]
TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[22]
TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[23]
TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[24]
TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[25]
TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[26]
TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[27]
TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA1 direct connect - cpuss.dw0_tr_in[28]
TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[0]
TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[1]
TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[2]
TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[3]
TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[4]
TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[5]
TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[6]
TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[7]
TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8]
TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9]
TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10]
TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11]
TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12]
TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13]
TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14]
TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15]
TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16]
TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17]
TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18]
TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19]
TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20]
TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21]
TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22]
TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23]
TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[24]
TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[25]
TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[26]
TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[27]
TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[28]
TRIGGER_CPUSS_DW1_TR_IN29 = 64, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[29]
TRIGGER_CPUSS_DW1_TR_IN30 = 65, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[30]
TRIGGER_CPUSS_DW1_TR_IN31 = 66, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[31]
TRIGGER_CSD_DSI_START = 67, //!< Capsense trigger multiplexer - csd.dsi_start
TRIGGER_PASS_TR_SAR_IN = 68, //!< ADC trigger multiplexer - pass.tr_sar_in
TRIGGER_PERI_TR_DBG_FREEZE = 69, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze
TRIGGER_PERI_TR_IO_OUTPUT0 = 70, //!< HSIOM trigger multiplexer - peri.tr_io_output[0]
TRIGGER_PERI_TR_IO_OUTPUT1 = 71, //!< HSIOM trigger multiplexer - peri.tr_io_output[1]
TRIGGER_TCPWM0_TR_IN0 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0]
TRIGGER_TCPWM0_TR_IN1 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1]
TRIGGER_TCPWM0_TR_IN2 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2]
TRIGGER_TCPWM0_TR_IN3 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3]
TRIGGER_TCPWM0_TR_IN4 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4]
TRIGGER_TCPWM0_TR_IN5 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5]
TRIGGER_TCPWM0_TR_IN6 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6]
TRIGGER_TCPWM0_TR_IN7 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7]
TRIGGER_TCPWM0_TR_IN8 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8]
TRIGGER_TCPWM0_TR_IN9 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9]
TRIGGER_TCPWM0_TR_IN10 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10]
TRIGGER_TCPWM0_TR_IN11 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11]
TRIGGER_TCPWM0_TR_IN12 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12]
TRIGGER_TCPWM0_TR_IN13 = 85, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13]
TRIGGER_TCPWM1_TR_IN0 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0]
TRIGGER_TCPWM1_TR_IN1 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1]
TRIGGER_TCPWM1_TR_IN2 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2]
TRIGGER_TCPWM1_TR_IN3 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3]
TRIGGER_TCPWM1_TR_IN4 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4]
TRIGGER_TCPWM1_TR_IN5 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5]
TRIGGER_TCPWM1_TR_IN6 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6]
TRIGGER_TCPWM1_TR_IN7 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7]
TRIGGER_TCPWM1_TR_IN8 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8]
TRIGGER_TCPWM1_TR_IN9 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9]
TRIGGER_TCPWM1_TR_IN10 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10]
TRIGGER_TCPWM1_TR_IN11 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11]
TRIGGER_TCPWM1_TR_IN12 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12]
TRIGGER_TCPWM1_TR_IN13 = 99, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13]
TRIGGER_USB_DMA_BURSTEND0 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0]
TRIGGER_USB_DMA_BURSTEND1 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1]
TRIGGER_USB_DMA_BURSTEND2 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2]
TRIGGER_USB_DMA_BURSTEND3 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3]
TRIGGER_USB_DMA_BURSTEND4 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4]
TRIGGER_USB_DMA_BURSTEND5 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5]
TRIGGER_USB_DMA_BURSTEND6 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6]
TRIGGER_USB_DMA_BURSTEND7 = 107, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7]
CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0]
CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 1, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 2, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 3, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[0]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[2]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[4]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[5]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[6]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[7]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[16]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[17]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[18]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[19]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[20]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[21]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[22]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[23]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[24]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[25]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[26]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[27]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA1 direct connect - cpuss.dw0_tr_in[28]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[0]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[1]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[2]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[3]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[4]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[5]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[6]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[7]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[24]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[25]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[26]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[27]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[28]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN29 = 64, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[29]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN30 = 65, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[30]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN31 = 66, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[31]
CYHAL_TRIGGER_CSD_DSI_START = 67, //!< Capsense trigger multiplexer - csd.dsi_start
CYHAL_TRIGGER_PASS_TR_SAR_IN = 68, //!< ADC trigger multiplexer - pass.tr_sar_in
CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 69, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze
CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 70, //!< HSIOM trigger multiplexer - peri.tr_io_output[0]
CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 71, //!< HSIOM trigger multiplexer - peri.tr_io_output[1]
CYHAL_TRIGGER_TCPWM0_TR_IN0 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0]
CYHAL_TRIGGER_TCPWM0_TR_IN1 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1]
CYHAL_TRIGGER_TCPWM0_TR_IN2 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2]
CYHAL_TRIGGER_TCPWM0_TR_IN3 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3]
CYHAL_TRIGGER_TCPWM0_TR_IN4 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4]
CYHAL_TRIGGER_TCPWM0_TR_IN5 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5]
CYHAL_TRIGGER_TCPWM0_TR_IN6 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6]
CYHAL_TRIGGER_TCPWM0_TR_IN7 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7]
CYHAL_TRIGGER_TCPWM0_TR_IN8 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8]
CYHAL_TRIGGER_TCPWM0_TR_IN9 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9]
CYHAL_TRIGGER_TCPWM0_TR_IN10 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10]
CYHAL_TRIGGER_TCPWM0_TR_IN11 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11]
CYHAL_TRIGGER_TCPWM0_TR_IN12 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12]
CYHAL_TRIGGER_TCPWM0_TR_IN13 = 85, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13]
CYHAL_TRIGGER_TCPWM1_TR_IN0 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0]
CYHAL_TRIGGER_TCPWM1_TR_IN1 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1]
CYHAL_TRIGGER_TCPWM1_TR_IN2 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2]
CYHAL_TRIGGER_TCPWM1_TR_IN3 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3]
CYHAL_TRIGGER_TCPWM1_TR_IN4 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4]
CYHAL_TRIGGER_TCPWM1_TR_IN5 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5]
CYHAL_TRIGGER_TCPWM1_TR_IN6 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6]
CYHAL_TRIGGER_TCPWM1_TR_IN7 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7]
CYHAL_TRIGGER_TCPWM1_TR_IN8 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8]
CYHAL_TRIGGER_TCPWM1_TR_IN9 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9]
CYHAL_TRIGGER_TCPWM1_TR_IN10 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10]
CYHAL_TRIGGER_TCPWM1_TR_IN11 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11]
CYHAL_TRIGGER_TCPWM1_TR_IN12 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12]
CYHAL_TRIGGER_TCPWM1_TR_IN13 = 99, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13]
CYHAL_TRIGGER_USB_DMA_BURSTEND0 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0]
CYHAL_TRIGGER_USB_DMA_BURSTEND1 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1]
CYHAL_TRIGGER_USB_DMA_BURSTEND2 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2]
CYHAL_TRIGGER_USB_DMA_BURSTEND3 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3]
CYHAL_TRIGGER_USB_DMA_BURSTEND4 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4]
CYHAL_TRIGGER_USB_DMA_BURSTEND5 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5]
CYHAL_TRIGGER_USB_DMA_BURSTEND6 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6]
CYHAL_TRIGGER_USB_DMA_BURSTEND7 = 107, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7]
} cyhal_trigger_dest_psoc6_03_t;
/** Typedef from device family specific trigger dest to generic trigger dest */
typedef cyhal_trigger_dest_psoc6_03_t cyhal_dest_t;
/** \cond INTERNAL */
/** Table of number of inputs to each mux. */
extern const uint16_t cyhal_sources_per_mux[19];
/** Table indicating whether mux is 1to1. */
extern const bool cyhal_is_mux_1to1[19];
/** Table pointing to each mux source table. The index of each source in the table is its mux input index. */
extern const cyhal_source_t* cyhal_mux_to_sources [19];
/** Maps each cyhal_destination_t to a mux index.
* If bit 8 of the mux index is set, this denotes that the trigger is a
* one to one trigger.

404
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_04.h Normal file → Executable file
View File

@ -5,11 +5,11 @@
* PSoC6_04 family HAL triggers header
*
* \note
* Generator version: 1.6.0.229
* Generator version: 1.6.0.453
*
********************************************************************************
* \copyright
* Copyright 2016-2020 Cypress Semiconductor Corporation
* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -39,127 +39,303 @@
extern "C" {
#endif /* __cplusplus */
/** @brief Name of each input trigger. */
typedef enum
{
CYHAL_TRIGGER_CPUSS_ZERO = 0, //!< cpuss.zero
CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_REQ0 = 1, //!< canfd[0].tr_dbg_dma_req[0]
CYHAL_TRIGGER_CANFD0_TR_FIFO00 = 2, //!< canfd[0].tr_fifo0[0]
CYHAL_TRIGGER_CANFD0_TR_FIFO10 = 3, //!< canfd[0].tr_fifo1[0]
CYHAL_TRIGGER_CANFD0_TR_TMP_RTP_OUT0 = 4, //!< canfd[0].tr_tmp_rtp_out[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT0 = 5, //!< cpuss.cti_tr_out[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_OUT1 = 6, //!< cpuss.cti_tr_out[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 = 7, //!< cpuss.dmac_tr_out[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT1 = 8, //!< cpuss.dmac_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 = 9, //!< cpuss.dw0_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT1 = 10, //!< cpuss.dw0_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT2 = 11, //!< cpuss.dw0_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT3 = 12, //!< cpuss.dw0_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT4 = 13, //!< cpuss.dw0_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT5 = 14, //!< cpuss.dw0_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT6 = 15, //!< cpuss.dw0_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT7 = 16, //!< cpuss.dw0_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT8 = 17, //!< cpuss.dw0_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT9 = 18, //!< cpuss.dw0_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT10 = 19, //!< cpuss.dw0_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT11 = 20, //!< cpuss.dw0_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT12 = 21, //!< cpuss.dw0_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT13 = 22, //!< cpuss.dw0_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT14 = 23, //!< cpuss.dw0_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT15 = 24, //!< cpuss.dw0_tr_out[15]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT16 = 25, //!< cpuss.dw0_tr_out[16]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT17 = 26, //!< cpuss.dw0_tr_out[17]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT18 = 27, //!< cpuss.dw0_tr_out[18]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT19 = 28, //!< cpuss.dw0_tr_out[19]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT20 = 29, //!< cpuss.dw0_tr_out[20]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT21 = 30, //!< cpuss.dw0_tr_out[21]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT22 = 31, //!< cpuss.dw0_tr_out[22]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT23 = 32, //!< cpuss.dw0_tr_out[23]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT24 = 33, //!< cpuss.dw0_tr_out[24]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT25 = 34, //!< cpuss.dw0_tr_out[25]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT26 = 35, //!< cpuss.dw0_tr_out[26]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT27 = 36, //!< cpuss.dw0_tr_out[27]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT28 = 37, //!< cpuss.dw0_tr_out[28]
CYHAL_TRIGGER_CPUSS_DW0_TR_OUT29 = 38, //!< cpuss.dw0_tr_out[29]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT0 = 39, //!< cpuss.dw1_tr_out[0]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT1 = 40, //!< cpuss.dw1_tr_out[1]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT2 = 41, //!< cpuss.dw1_tr_out[2]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT3 = 42, //!< cpuss.dw1_tr_out[3]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT4 = 43, //!< cpuss.dw1_tr_out[4]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT5 = 44, //!< cpuss.dw1_tr_out[5]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT6 = 45, //!< cpuss.dw1_tr_out[6]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT7 = 46, //!< cpuss.dw1_tr_out[7]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT8 = 47, //!< cpuss.dw1_tr_out[8]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT9 = 48, //!< cpuss.dw1_tr_out[9]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT10 = 49, //!< cpuss.dw1_tr_out[10]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT11 = 50, //!< cpuss.dw1_tr_out[11]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT12 = 51, //!< cpuss.dw1_tr_out[12]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT13 = 52, //!< cpuss.dw1_tr_out[13]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT14 = 53, //!< cpuss.dw1_tr_out[14]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT15 = 54, //!< cpuss.dw1_tr_out[15]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT16 = 55, //!< cpuss.dw1_tr_out[16]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT17 = 56, //!< cpuss.dw1_tr_out[17]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT18 = 57, //!< cpuss.dw1_tr_out[18]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT19 = 58, //!< cpuss.dw1_tr_out[19]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT20 = 59, //!< cpuss.dw1_tr_out[20]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT21 = 60, //!< cpuss.dw1_tr_out[21]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT22 = 61, //!< cpuss.dw1_tr_out[22]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT23 = 62, //!< cpuss.dw1_tr_out[23]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT24 = 63, //!< cpuss.dw1_tr_out[24]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT25 = 64, //!< cpuss.dw1_tr_out[25]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT26 = 65, //!< cpuss.dw1_tr_out[26]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT27 = 66, //!< cpuss.dw1_tr_out[27]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT28 = 67, //!< cpuss.dw1_tr_out[28]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT29 = 68, //!< cpuss.dw1_tr_out[29]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT30 = 69, //!< cpuss.dw1_tr_out[30]
CYHAL_TRIGGER_CPUSS_DW1_TR_OUT31 = 70, //!< cpuss.dw1_tr_out[31]
CYHAL_TRIGGER_CPUSS_TR_FAULT0 = 71, //!< cpuss.tr_fault[0]
CYHAL_TRIGGER_CPUSS_TR_FAULT1 = 72, //!< cpuss.tr_fault[1]
CYHAL_TRIGGER_CSD_DSI_SAMPLE_OUT = 73, //!< csd.dsi_sample_out
CYHAL_TRIGGER_CSD_DSI_SENSE_OUT = 74, //!< csd.dsi_sense_out
CYHAL_TRIGGER_CSD_TR_ADC_DONE = 75, //!< csd.tr_adc_done
CYHAL_TRIGGER_LPCOMP_DSI_COMP0 = 76, //!< lpcomp.dsi_comp0
CYHAL_TRIGGER_LPCOMP_DSI_COMP1 = 77, //!< lpcomp.dsi_comp1
CYHAL_TRIGGER_PASS_DSI_CTB_CMP0 = 78, //!< pass.dsi_ctb_cmp0
CYHAL_TRIGGER_PASS_DSI_CTB_CMP1 = 79, //!< pass.dsi_ctb_cmp1
CYHAL_TRIGGER_PASS_TR_CTDAC_EMPTY = 80, //!< pass.tr_ctdac_empty
CYHAL_TRIGGER_PASS_TR_SAR_OUT0 = 81, //!< pass.tr_sar_out[0]
CYHAL_TRIGGER_PASS_TR_SAR_OUT1 = 82, //!< pass.tr_sar_out[1]
CYHAL_TRIGGER_PERI_TR_IO_INPUT0 = 83, //!< peri.tr_io_input[0]
CYHAL_TRIGGER_PERI_TR_IO_INPUT1 = 84, //!< peri.tr_io_input[1]
CYHAL_TRIGGER_PERI_TR_IO_INPUT2 = 85, //!< peri.tr_io_input[2]
CYHAL_TRIGGER_PERI_TR_IO_INPUT3 = 86, //!< peri.tr_io_input[3]
CYHAL_TRIGGER_PERI_TR_IO_INPUT4 = 87, //!< peri.tr_io_input[4]
CYHAL_TRIGGER_PERI_TR_IO_INPUT5 = 88, //!< peri.tr_io_input[5]
CYHAL_TRIGGER_PERI_TR_IO_INPUT6 = 89, //!< peri.tr_io_input[6]
CYHAL_TRIGGER_PERI_TR_IO_INPUT7 = 90, //!< peri.tr_io_input[7]
CYHAL_TRIGGER_PERI_TR_IO_INPUT8 = 91, //!< peri.tr_io_input[8]
CYHAL_TRIGGER_PERI_TR_IO_INPUT9 = 92, //!< peri.tr_io_input[9]
CYHAL_TRIGGER_PERI_TR_IO_INPUT10 = 93, //!< peri.tr_io_input[10]
CYHAL_TRIGGER_PERI_TR_IO_INPUT11 = 94, //!< peri.tr_io_input[11]
CYHAL_TRIGGER_PERI_TR_IO_INPUT12 = 95, //!< peri.tr_io_input[12]
CYHAL_TRIGGER_PERI_TR_IO_INPUT13 = 96, //!< peri.tr_io_input[13]
CYHAL_TRIGGER_PERI_TR_IO_INPUT14 = 97, //!< peri.tr_io_input[14]
CYHAL_TRIGGER_PERI_TR_IO_INPUT15 = 98, //!< peri.tr_io_input[15]
CYHAL_TRIGGER_PERI_TR_IO_INPUT16 = 99, //!< peri.tr_io_input[16]
CYHAL_TRIGGER_PERI_TR_IO_INPUT17 = 100, //!< peri.tr_io_input[17]
CYHAL_TRIGGER_PERI_TR_IO_INPUT18 = 101, //!< peri.tr_io_input[18]
CYHAL_TRIGGER_PERI_TR_IO_INPUT19 = 102, //!< peri.tr_io_input[19]
CYHAL_TRIGGER_PERI_TR_IO_INPUT20 = 103, //!< peri.tr_io_input[20]
CYHAL_TRIGGER_PERI_TR_IO_INPUT21 = 104, //!< peri.tr_io_input[21]
CYHAL_TRIGGER_PERI_TR_IO_INPUT22 = 105, //!< peri.tr_io_input[22]
CYHAL_TRIGGER_PERI_TR_IO_INPUT23 = 106, //!< peri.tr_io_input[23]
CYHAL_TRIGGER_SCB0_TR_I2C_SCL_FILTERED = 107, //!< scb[0].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB1_TR_I2C_SCL_FILTERED = 108, //!< scb[1].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB2_TR_I2C_SCL_FILTERED = 109, //!< scb[2].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB4_TR_I2C_SCL_FILTERED = 110, //!< scb[4].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB5_TR_I2C_SCL_FILTERED = 111, //!< scb[5].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB6_TR_I2C_SCL_FILTERED = 112, //!< scb[6].tr_i2c_scl_filtered
CYHAL_TRIGGER_SCB0_TR_RX_REQ = 113, //!< scb[0].tr_rx_req
CYHAL_TRIGGER_SCB1_TR_RX_REQ = 114, //!< scb[1].tr_rx_req
CYHAL_TRIGGER_SCB2_TR_RX_REQ = 115, //!< scb[2].tr_rx_req
CYHAL_TRIGGER_SCB4_TR_RX_REQ = 116, //!< scb[4].tr_rx_req
CYHAL_TRIGGER_SCB5_TR_RX_REQ = 117, //!< scb[5].tr_rx_req
CYHAL_TRIGGER_SCB6_TR_RX_REQ = 118, //!< scb[6].tr_rx_req
CYHAL_TRIGGER_SCB0_TR_TX_REQ = 119, //!< scb[0].tr_tx_req
CYHAL_TRIGGER_SCB1_TR_TX_REQ = 120, //!< scb[1].tr_tx_req
CYHAL_TRIGGER_SCB2_TR_TX_REQ = 121, //!< scb[2].tr_tx_req
CYHAL_TRIGGER_SCB4_TR_TX_REQ = 122, //!< scb[4].tr_tx_req
CYHAL_TRIGGER_SCB5_TR_TX_REQ = 123, //!< scb[5].tr_tx_req
CYHAL_TRIGGER_SCB6_TR_TX_REQ = 124, //!< scb[6].tr_tx_req
CYHAL_TRIGGER_SMIF_TR_RX_REQ = 125, //!< smif.tr_rx_req
CYHAL_TRIGGER_SMIF_TR_TX_REQ = 126, //!< smif.tr_tx_req
CYHAL_TRIGGER_TCPWM0_TR_OUT00 = 127, //!< tcpwm[0].tr_out0[0]
CYHAL_TRIGGER_TCPWM0_TR_OUT01 = 128, //!< tcpwm[0].tr_out0[1]
CYHAL_TRIGGER_TCPWM0_TR_OUT02 = 129, //!< tcpwm[0].tr_out0[2]
CYHAL_TRIGGER_TCPWM0_TR_OUT03 = 130, //!< tcpwm[0].tr_out0[3]
CYHAL_TRIGGER_TCPWM0_TR_OUT0256 = 131, //!< tcpwm[0].tr_out0[256]
CYHAL_TRIGGER_TCPWM0_TR_OUT0257 = 132, //!< tcpwm[0].tr_out0[257]
CYHAL_TRIGGER_TCPWM0_TR_OUT0258 = 133, //!< tcpwm[0].tr_out0[258]
CYHAL_TRIGGER_TCPWM0_TR_OUT0259 = 134, //!< tcpwm[0].tr_out0[259]
CYHAL_TRIGGER_TCPWM0_TR_OUT0260 = 135, //!< tcpwm[0].tr_out0[260]
CYHAL_TRIGGER_TCPWM0_TR_OUT0261 = 136, //!< tcpwm[0].tr_out0[261]
CYHAL_TRIGGER_TCPWM0_TR_OUT0262 = 137, //!< tcpwm[0].tr_out0[262]
CYHAL_TRIGGER_TCPWM0_TR_OUT0263 = 138, //!< tcpwm[0].tr_out0[263]
CYHAL_TRIGGER_TCPWM0_TR_OUT10 = 139, //!< tcpwm[0].tr_out1[0]
CYHAL_TRIGGER_TCPWM0_TR_OUT11 = 140, //!< tcpwm[0].tr_out1[1]
CYHAL_TRIGGER_TCPWM0_TR_OUT12 = 141, //!< tcpwm[0].tr_out1[2]
CYHAL_TRIGGER_TCPWM0_TR_OUT13 = 142, //!< tcpwm[0].tr_out1[3]
CYHAL_TRIGGER_TCPWM0_TR_OUT1256 = 143, //!< tcpwm[0].tr_out1[256]
CYHAL_TRIGGER_TCPWM0_TR_OUT1257 = 144, //!< tcpwm[0].tr_out1[257]
CYHAL_TRIGGER_TCPWM0_TR_OUT1258 = 145, //!< tcpwm[0].tr_out1[258]
CYHAL_TRIGGER_TCPWM0_TR_OUT1259 = 146, //!< tcpwm[0].tr_out1[259]
CYHAL_TRIGGER_TCPWM0_TR_OUT1260 = 147, //!< tcpwm[0].tr_out1[260]
CYHAL_TRIGGER_TCPWM0_TR_OUT1261 = 148, //!< tcpwm[0].tr_out1[261]
CYHAL_TRIGGER_TCPWM0_TR_OUT1262 = 149, //!< tcpwm[0].tr_out1[262]
CYHAL_TRIGGER_TCPWM0_TR_OUT1263 = 150, //!< tcpwm[0].tr_out1[263]
CYHAL_TRIGGER_USB_DMA_REQ0 = 151, //!< usb.dma_req[0]
CYHAL_TRIGGER_USB_DMA_REQ1 = 152, //!< usb.dma_req[1]
CYHAL_TRIGGER_USB_DMA_REQ2 = 153, //!< usb.dma_req[2]
CYHAL_TRIGGER_USB_DMA_REQ3 = 154, //!< usb.dma_req[3]
CYHAL_TRIGGER_USB_DMA_REQ4 = 155, //!< usb.dma_req[4]
CYHAL_TRIGGER_USB_DMA_REQ5 = 156, //!< usb.dma_req[5]
CYHAL_TRIGGER_USB_DMA_REQ6 = 157, //!< usb.dma_req[6]
CYHAL_TRIGGER_USB_DMA_REQ7 = 158, //!< usb.dma_req[7]
} cyhal_trigger_source_psoc6_04_t;
/** Typedef from device family specific trigger source to generic trigger source */
typedef cyhal_trigger_source_psoc6_04_t cyhal_source_t;
/** @brief Name of each output trigger. */
typedef enum
{
TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0]
TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 1, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0]
TRIGGER_CPUSS_CTI_TR_IN0 = 2, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[0]
TRIGGER_CPUSS_CTI_TR_IN1 = 3, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[1]
TRIGGER_CPUSS_DMAC_TR_IN0 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0]
TRIGGER_CPUSS_DMAC_TR_IN1 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1]
TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[0]
TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[1]
TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[2]
TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[3]
TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[4]
TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[5]
TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[6]
TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[7]
TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8]
TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9]
TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10]
TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11]
TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12]
TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13]
TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14]
TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15]
TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[16]
TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[17]
TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[18]
TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[19]
TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[20]
TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[21]
TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[22]
TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[23]
TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[24]
TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[25]
TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[26]
TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[27]
TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR0 to PDMA1 direct connect - cpuss.dw0_tr_in[28]
TRIGGER_CPUSS_DW0_TR_IN29 = 35, //!< SAR1 to PDMA1 direct connect - cpuss.dw0_tr_in[29]
TRIGGER_CPUSS_DW1_TR_IN0 = 36, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[0]
TRIGGER_CPUSS_DW1_TR_IN1 = 37, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[1]
TRIGGER_CPUSS_DW1_TR_IN2 = 38, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[2]
TRIGGER_CPUSS_DW1_TR_IN3 = 39, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[3]
TRIGGER_CPUSS_DW1_TR_IN4 = 40, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[4]
TRIGGER_CPUSS_DW1_TR_IN5 = 41, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[5]
TRIGGER_CPUSS_DW1_TR_IN6 = 42, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[6]
TRIGGER_CPUSS_DW1_TR_IN7 = 43, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[7]
TRIGGER_CPUSS_DW1_TR_IN8 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8]
TRIGGER_CPUSS_DW1_TR_IN9 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9]
TRIGGER_CPUSS_DW1_TR_IN10 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10]
TRIGGER_CPUSS_DW1_TR_IN11 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11]
TRIGGER_CPUSS_DW1_TR_IN12 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12]
TRIGGER_CPUSS_DW1_TR_IN13 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13]
TRIGGER_CPUSS_DW1_TR_IN14 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14]
TRIGGER_CPUSS_DW1_TR_IN15 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15]
TRIGGER_CPUSS_DW1_TR_IN16 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16]
TRIGGER_CPUSS_DW1_TR_IN17 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17]
TRIGGER_CPUSS_DW1_TR_IN18 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18]
TRIGGER_CPUSS_DW1_TR_IN19 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19]
TRIGGER_CPUSS_DW1_TR_IN20 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20]
TRIGGER_CPUSS_DW1_TR_IN21 = 57, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21]
TRIGGER_CPUSS_DW1_TR_IN22 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22]
TRIGGER_CPUSS_DW1_TR_IN23 = 59, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23]
TRIGGER_CPUSS_DW1_TR_IN24 = 60, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[24]
TRIGGER_CPUSS_DW1_TR_IN25 = 61, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[25]
TRIGGER_CPUSS_DW1_TR_IN26 = 62, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[26]
TRIGGER_CPUSS_DW1_TR_IN27 = 63, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[27]
TRIGGER_CPUSS_DW1_TR_IN28 = 64, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[28]
TRIGGER_CPUSS_DW1_TR_IN29 = 65, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[29]
TRIGGER_CPUSS_DW1_TR_IN30 = 66, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[30]
TRIGGER_CPUSS_DW1_TR_IN31 = 67, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[31]
TRIGGER_CSD_DSI_START = 68, //!< Capsense trigger multiplexer - csd.dsi_start
TRIGGER_PASS_DSI_CTDAC_STROBE = 69, //!< CTDAC trigger multiplexer - pass.dsi_ctdac_strobe
TRIGGER_PASS_TR_SAR_IN0 = 70, //!< ADC trigger multiplexer - pass.tr_sar_in[0]
TRIGGER_PASS_TR_SAR_IN1 = 71, //!< ADC trigger multiplexer - pass.tr_sar_in[1]
TRIGGER_PERI_TR_DBG_FREEZE = 72, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze
TRIGGER_PERI_TR_IO_OUTPUT0 = 73, //!< HSIOM trigger multiplexer - peri.tr_io_output[0]
TRIGGER_PERI_TR_IO_OUTPUT1 = 74, //!< HSIOM trigger multiplexer - peri.tr_io_output[1]
TRIGGER_TCPWM0_TR_ALL_CNT_IN0 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[0]
TRIGGER_TCPWM0_TR_ALL_CNT_IN1 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[1]
TRIGGER_TCPWM0_TR_ALL_CNT_IN2 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[2]
TRIGGER_TCPWM0_TR_ALL_CNT_IN3 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[3]
TRIGGER_TCPWM0_TR_ALL_CNT_IN4 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[4]
TRIGGER_TCPWM0_TR_ALL_CNT_IN5 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[5]
TRIGGER_TCPWM0_TR_ALL_CNT_IN6 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[6]
TRIGGER_TCPWM0_TR_ALL_CNT_IN7 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[7]
TRIGGER_TCPWM0_TR_ALL_CNT_IN8 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[8]
TRIGGER_TCPWM0_TR_ALL_CNT_IN9 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[9]
TRIGGER_TCPWM0_TR_ALL_CNT_IN10 = 85, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[10]
TRIGGER_TCPWM0_TR_ALL_CNT_IN11 = 86, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[11]
TRIGGER_TCPWM0_TR_ALL_CNT_IN12 = 87, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[12]
TRIGGER_TCPWM0_TR_ALL_CNT_IN13 = 88, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[13]
TRIGGER_TCPWM0_TR_ALL_CNT_IN14 = 89, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[14]
TRIGGER_TCPWM0_TR_ALL_CNT_IN15 = 90, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[15]
TRIGGER_TCPWM0_TR_ALL_CNT_IN16 = 91, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[16]
TRIGGER_TCPWM0_TR_ALL_CNT_IN17 = 92, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[17]
TRIGGER_TCPWM0_TR_ALL_CNT_IN18 = 93, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[18]
TRIGGER_TCPWM0_TR_ALL_CNT_IN19 = 94, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[19]
TRIGGER_TCPWM0_TR_ALL_CNT_IN20 = 95, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[20]
TRIGGER_TCPWM0_TR_ALL_CNT_IN21 = 96, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[21]
TRIGGER_TCPWM0_TR_ALL_CNT_IN22 = 97, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[22]
TRIGGER_TCPWM0_TR_ALL_CNT_IN23 = 98, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[23]
TRIGGER_TCPWM0_TR_ALL_CNT_IN24 = 99, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[24]
TRIGGER_TCPWM0_TR_ALL_CNT_IN25 = 100, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[25]
TRIGGER_TCPWM0_TR_ALL_CNT_IN26 = 101, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[26]
TRIGGER_TCPWM0_TR_ALL_CNT_IN27 = 102, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[27]
TRIGGER_TCPWM0_TR_DEBUG_FREEZE = 103, //!< PERI Freeze trigger multiplexer - tcpwm[0].tr_debug_freeze
TRIGGER_USB_DMA_BURSTEND0 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0]
TRIGGER_USB_DMA_BURSTEND1 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1]
TRIGGER_USB_DMA_BURSTEND2 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2]
TRIGGER_USB_DMA_BURSTEND3 = 107, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3]
TRIGGER_USB_DMA_BURSTEND4 = 108, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4]
TRIGGER_USB_DMA_BURSTEND5 = 109, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5]
TRIGGER_USB_DMA_BURSTEND6 = 110, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6]
TRIGGER_USB_DMA_BURSTEND7 = 111, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7]
CYHAL_TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0]
CYHAL_TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 1, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_IN0 = 2, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[0]
CYHAL_TRIGGER_CPUSS_CTI_TR_IN1 = 3, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[1]
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0]
CYHAL_TRIGGER_CPUSS_DMAC_TR_IN1 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[0]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[1]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[2]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[3]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[4]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[5]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[6]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[7]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[16]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[17]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[18]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[19]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[20]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[21]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[22]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[23]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[24]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[25]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[26]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[27]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR0 to PDMA1 direct connect - cpuss.dw0_tr_in[28]
CYHAL_TRIGGER_CPUSS_DW0_TR_IN29 = 35, //!< SAR1 to PDMA1 direct connect - cpuss.dw0_tr_in[29]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN0 = 36, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[0]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN1 = 37, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[1]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN2 = 38, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[2]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN3 = 39, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[3]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN4 = 40, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[4]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN5 = 41, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[5]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN6 = 42, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[6]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN7 = 43, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[7]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN8 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN9 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN10 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN11 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN12 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN13 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN14 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN15 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN16 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN17 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN18 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN19 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN20 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN21 = 57, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN22 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN23 = 59, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN24 = 60, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[24]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN25 = 61, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[25]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN26 = 62, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[26]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN27 = 63, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[27]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN28 = 64, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[28]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN29 = 65, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[29]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN30 = 66, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[30]
CYHAL_TRIGGER_CPUSS_DW1_TR_IN31 = 67, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[31]
CYHAL_TRIGGER_CSD_DSI_START = 68, //!< Capsense trigger multiplexer - csd.dsi_start
CYHAL_TRIGGER_PASS_DSI_CTDAC_STROBE = 69, //!< CTDAC trigger multiplexer - pass.dsi_ctdac_strobe
CYHAL_TRIGGER_PASS_TR_SAR_IN0 = 70, //!< ADC trigger multiplexer - pass.tr_sar_in[0]
CYHAL_TRIGGER_PASS_TR_SAR_IN1 = 71, //!< ADC trigger multiplexer - pass.tr_sar_in[1]
CYHAL_TRIGGER_PERI_TR_DBG_FREEZE = 72, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze
CYHAL_TRIGGER_PERI_TR_IO_OUTPUT0 = 73, //!< HSIOM trigger multiplexer - peri.tr_io_output[0]
CYHAL_TRIGGER_PERI_TR_IO_OUTPUT1 = 74, //!< HSIOM trigger multiplexer - peri.tr_io_output[1]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN0 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[0]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN1 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[1]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN2 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[2]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN3 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[3]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN4 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[4]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN5 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[5]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN6 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[6]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN7 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[7]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN8 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[8]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN9 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[9]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN10 = 85, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[10]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN11 = 86, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[11]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN12 = 87, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[12]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN13 = 88, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_all_cnt_in[13]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN14 = 89, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[14]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN15 = 90, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[15]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN16 = 91, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[16]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN17 = 92, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[17]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN18 = 93, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[18]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN19 = 94, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[19]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN20 = 95, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[20]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN21 = 96, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[21]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN22 = 97, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[22]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN23 = 98, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[23]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN24 = 99, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[24]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN25 = 100, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[25]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN26 = 101, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[26]
CYHAL_TRIGGER_TCPWM0_TR_ALL_CNT_IN27 = 102, //!< TCPWM0 trigger multiplexer - 2nd - tcpwm[0].tr_all_cnt_in[27]
CYHAL_TRIGGER_TCPWM0_TR_DEBUG_FREEZE = 103, //!< PERI Freeze trigger multiplexer - tcpwm[0].tr_debug_freeze
CYHAL_TRIGGER_USB_DMA_BURSTEND0 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0]
CYHAL_TRIGGER_USB_DMA_BURSTEND1 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1]
CYHAL_TRIGGER_USB_DMA_BURSTEND2 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2]
CYHAL_TRIGGER_USB_DMA_BURSTEND3 = 107, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3]
CYHAL_TRIGGER_USB_DMA_BURSTEND4 = 108, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4]
CYHAL_TRIGGER_USB_DMA_BURSTEND5 = 109, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5]
CYHAL_TRIGGER_USB_DMA_BURSTEND6 = 110, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6]
CYHAL_TRIGGER_USB_DMA_BURSTEND7 = 111, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7]
} cyhal_trigger_dest_psoc6_04_t;
/** Typedef from device family specific trigger dest to generic trigger dest */
typedef cyhal_trigger_dest_psoc6_04_t cyhal_dest_t;
/** \cond INTERNAL */
/** Table of number of inputs to each mux. */
extern const uint16_t cyhal_sources_per_mux[21];
/** Table indicating whether mux is 1to1. */
extern const bool cyhal_is_mux_1to1[21];
/** Table pointing to each mux source table. The index of each source in the table is its mux input index. */
extern const cyhal_source_t* cyhal_mux_to_sources [21];
/** Maps each cyhal_destination_t to a mux index.
* If bit 8 of the mux index is set, this denotes that the trigger is a
* one to one trigger.

824
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c Normal file → Executable file
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File diff suppressed because it is too large Load Diff

18
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_analog_common.c Normal file → Executable file
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@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -26,19 +26,25 @@
#include "cy_pdl.h"
#include "cyhal_hw_types.h"
#include "cyhal_hwmgr.h"
#include "cy_ctb.h"
#include "cyhal_pin_package.h"
#include "cyhal_gpio.h"
#include "cyhal_system_impl.h"
#if defined(CY_IP_MXS40PASS_INSTANCES)
#include "cy_ctb.h"
#endif
#if defined(CY_IP_MXS40PASS_INSTANCES) || defined(CY_IP_M0S8PASS4A_INSTANCES)
#if defined(__cplusplus)
extern "C"
{
#endif
#if defined(CY_IP_MXS40PASS_INSTANCES)
static uint16_t cyhal_analog_ref_count = 0;
#endif
#ifdef CY_IP_MXS40PASS_CTB_INSTANCES
static uint16_t cyhal_analog_ctb_ref_count = 0;
@ -48,7 +54,7 @@ CTBM_Type *const _cyhal_ctb_base[] =
CTBM0,
#endif
/* All current PSoC 6 devices have only one CTB block */
/* All current CAT1/CAT2 devices have only one CTB block */
#if (CY_IP_MXS40PASS_CTB_INSTANCES > 1)
#error "Unhandled CTB instance count"
#endif
@ -59,6 +65,7 @@ CTBM_Type *const _cyhal_ctb_base[] =
void _cyhal_analog_init(void)
{
#if defined(CY_IP_MXS40PASS_INSTANCES)
uint32_t saved_intr = cyhal_system_critical_section_enter();
if(cyhal_analog_ref_count == 0)
{
@ -68,10 +75,12 @@ void _cyhal_analog_init(void)
++cyhal_analog_ref_count;
cyhal_system_critical_section_exit(saved_intr);
#endif
}
void _cyhal_analog_free(void)
{
#if defined(CY_IP_MXS40PASS_INSTANCES)
uint32_t saved_intr = cyhal_system_critical_section_enter();
CY_ASSERT(cyhal_analog_ref_count > 0);
--cyhal_analog_ref_count;
@ -81,6 +90,7 @@ void _cyhal_analog_free(void)
Cy_SysAnalog_DeInit();
}
cyhal_system_critical_section_exit(saved_intr);
#endif
}
#ifdef CY_IP_MXS40PASS_CTB_INSTANCES
@ -266,4 +276,4 @@ uint32 _cyhal_opamp_convert_power(cyhal_power_level_t hal_power)
}
#endif
#endif /* defined(CY_IP_MXS40PASS_INSTANCES) */
#endif /* defined(CY_IP_MXS40PASS_INSTANCES || defined(CY_IP_M0S8PASS4A_INSTANCES) */

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_clock.c Normal file → Executable file
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

11
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_comp.c Normal file → Executable file
View File

@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -35,7 +35,7 @@
/**
* \addtogroup group_hal_impl_comp COMP (Analog Comparator)
* \ingroup group_hal_impl
* On PSoC 6, the COMP driver can use either of two underlying hardware blocks:
* On CAT1 (PSoC 6), the COMP driver can use either of two underlying hardware blocks:
* - Opamp (configured as analog comparator)
* - LPComp (Low Power Comparator)
*
@ -58,7 +58,7 @@
cy_rslt_t cyhal_comp_init(cyhal_comp_t *obj, cyhal_gpio_t vin_p, cyhal_gpio_t vin_m, cyhal_gpio_t output, cyhal_comp_config_t *cfg)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
cy_rslt_t result = CYHAL_COMP_RSLT_ERR_BAD_ARGUMENT;
#if defined(CY_IP_MXLPCOMP_INSTANCES) && (CY_IP_MXLPCOMP_INSTANCES > 0)
result = _cyhal_comp_lp_init(obj, vin_p, vin_m, output, cfg);
#else
@ -68,13 +68,12 @@ cy_rslt_t cyhal_comp_init(cyhal_comp_t *obj, cyhal_gpio_t vin_p, cyhal_gpio_t vi
CY_UNUSED_PARAMETER(output);
CY_UNUSED_PARAMETER(cfg);
#endif
#if defined(CY_IP_MXS40PASS_CTB_INSTANCES) && (CY_IP_MXS40PASS_CTB_INSTANCES > 0)
if(CY_RSLT_SUCCESS != result)
{
result = CYHAL_COMP_RSLT_ERR_BAD_ARGUMENT;
#if defined(CY_IP_MXS40PASS_CTB_INSTANCES) && (CY_IP_MXS40PASS_CTB_INSTANCES > 0)
result = _cyhal_comp_ctb_init(obj, vin_p, vin_m, output, cfg);
#endif
}
#endif
return result;
}

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_comp_ctb.c Normal file → Executable file
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

9
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_comp_lp.c Normal file → Executable file
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -171,7 +171,7 @@ cy_rslt_t _cyhal_comp_lp_init(cyhal_comp_t *obj, cyhal_gpio_t vin_p, cyhal_gpio_
const cyhal_resource_pin_mapping_t *output_map = (NC != output) ? CY_UTILS_GET_RESOURCE(output, cyhal_pin_map_lpcomp_dsi_comp) : NULL;
/* Verify if mapping successful */
if((NULL == vin_p_map) || (NULL == vin_m_map) || ((NC != output) && (NULL == vin_m_map)))
if((NULL == vin_p_map) || (NULL == vin_m_map) || ((NC != output) && (NULL == output_map)))
{
result = CYHAL_COMP_RSLT_ERR_INVALID_PIN;
}
@ -270,7 +270,10 @@ void _cyhal_comp_lp_free(cyhal_comp_t *obj)
NVIC_DisableIRQ(_cyhal_lp_comp_irq_n[obj->resource.block_num / _CYHAL_COMP_PER_LP]);
}
Cy_LPComp_Disable(obj->base_lpcomp, (obj->resource.block_num % _CYHAL_COMP_PER_LP) ? CY_LPCOMP_CHANNEL_1 : CY_LPCOMP_CHANNEL_0);
if(NULL != obj->base_lpcomp)
{
Cy_LPComp_Disable(obj->base_lpcomp, (obj->resource.block_num % _CYHAL_COMP_PER_LP) ? CY_LPCOMP_CHANNEL_1 : CY_LPCOMP_CHANNEL_0);
}
cyhal_hwmgr_free(&(obj->resource));
obj->base_lpcomp = NULL;
obj->resource.type = CYHAL_RSC_INVALID;

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crc.c Normal file → Executable file
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crypto_common.c Normal file → Executable file
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

29
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dac.c Normal file → Executable file
View File

@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -160,12 +160,14 @@ static uint32_t _cyhal_dac_configure_oa0(cyhal_dac_t *obj, bool init)
result = Cy_CTB_OpampInit(obj->base_opamp, CY_CTB_OPAMP_0, &config);
Cy_CTB_SetAnalogSwitch(obj->base_opamp, CY_CTB_SWITCH_OA0_SW, CY_CTB_SW_OA0_NEG_OUT_MASK | CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK, CY_CTB_SWITCH_CLOSE);
Cy_CTB_SetAnalogSwitch(obj->base_opamp, CY_CTB_SWITCH_CTD_SW, CY_CTB_SW_CTD_OUT_CHOLD_MASK | CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK, CY_CTB_SWITCH_CLOSE);
cyhal_analog_ctb_init(obj->base_opamp);
}
else
{
/* Open switches OA0 if used */
Cy_CTB_SetAnalogSwitch(obj->base_opamp, CY_CTB_SWITCH_OA0_SW, CY_CTB_SW_OA0_NEG_OUT_MASK | CY_CTB_SW_OA0_OUT_SHORT_1X_10X_MASK, CY_CTB_SWITCH_OPEN);
Cy_CTB_SetAnalogSwitch(obj->base_opamp, CY_CTB_SWITCH_CTD_SW, CY_CTB_SW_CTD_OUT_CHOLD_MASK | CY_CTB_SW_CTD_CHOLD_OA0_POS_MASK, CY_CTB_SWITCH_OPEN);
cyhal_analog_ctb_free(obj->base_opamp);
}
return result;
}
@ -179,12 +181,14 @@ static uint32_t _cyhal_dac_configure_oa1(cyhal_dac_t *obj, bool init)
result = Cy_CTB_OpampInit(obj->base_opamp, CY_CTB_OPAMP_1, &cyhal_opamp_default_config);
Cy_CTB_SetAnalogSwitch(obj->base_opamp, CY_CTB_SWITCH_OA1_SW, CY_CTB_SW_OA1_NEG_OUT_MASK | CY_CTB_SW_OA1_POS_AREF_MASK, CY_CTB_SWITCH_CLOSE);
Cy_CTB_SetAnalogSwitch(obj->base_opamp, CY_CTB_SWITCH_CTD_SW, CY_CTB_SW_CTD_REF_OA1_OUT_MASK, CY_CTB_SWITCH_CLOSE);
cyhal_analog_ctb_init(obj->base_opamp);
}
else
{
/* Open switches OA1 if used */
Cy_CTB_SetAnalogSwitch(obj->base_opamp, CY_CTB_SWITCH_OA1_SW, CY_CTB_SW_OA1_NEG_OUT_MASK | CY_CTB_SW_OA1_POS_AREF_MASK, CY_CTB_SWITCH_OPEN);
Cy_CTB_SetAnalogSwitch(obj->base_opamp, CY_CTB_SWITCH_CTD_SW, CY_CTB_SW_CTD_REF_OA1_OUT_MASK, CY_CTB_SWITCH_OPEN);
cyhal_analog_ctb_free(obj->base_opamp);
}
return result;
}
@ -303,8 +307,7 @@ cy_rslt_t cyhal_dac_init(cyhal_dac_t *obj, cyhal_gpio_t pin)
if (CY_RSLT_SUCCESS == result)
{
(obj->resource_opamp.type != CYHAL_RSC_INVALID) ? cyhal_analog_ctb_init(obj->base_opamp)
: _cyhal_analog_init();
_cyhal_analog_init();
}
if (result == CY_RSLT_SUCCESS)
@ -337,21 +340,19 @@ void cyhal_dac_free(cyhal_dac_t *obj)
(void)_cyhal_dac_configure_oa0(obj, false);
}
/* Disable CTB block if used */
if ((obj->resource_aref_opamp.type != CYHAL_RSC_INVALID) || (obj->resource_opamp.type != CYHAL_RSC_INVALID))
{
cyhal_analog_ctb_free(obj->base_opamp);
}
else
{
_cyhal_analog_free();
}
_cyhal_analog_free();
Cy_CTDAC_Disable(obj->base_dac);
cyhal_hwmgr_free(&obj->resource_dac);
cyhal_hwmgr_free(&obj->resource_opamp);
cyhal_hwmgr_free(&obj->resource_aref_opamp);
if(CYHAL_RSC_INVALID != obj->resource_opamp.type)
{
cyhal_hwmgr_free(&obj->resource_opamp);
}
if(CYHAL_RSC_INVALID != obj->resource_aref_opamp.type)
{
cyhal_hwmgr_free(&obj->resource_aref_opamp);
}
_cyhal_utils_release_if_used(&(obj->pin));

2
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_deprecated.c Normal file → Executable file
View File

@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");

208
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma.c Normal file → Executable file
View File

@ -9,7 +9,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -25,91 +25,133 @@
* limitations under the License.
*******************************************************************************/
#include "cyhal_dma_dmac.h"
#include "cyhal_dma_dw.h"
#include "cyhal_dma.h"
#include "cyhal_system.h"
#include "cyhal_hwmgr.h"
#include "cyhal_interconnect.h"
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
#include "cyhal_dma_dmac.h"
#endif
#if defined(CY_IP_M4CPUSS_DMA)
#include "cyhal_dma_dw.h"
#endif
/**
* \addtogroup group_hal_dma DMA (Direct Memory Access)
* \ingroup group_hal
* \{
*/
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA)
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M0S8CPUSSV3_DMAC)
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction)
cy_rslt_t cyhal_dma_init_adv(
cyhal_dma_t *obj, cyhal_dma_src_t *src, cyhal_dma_dest_t *dest, cyhal_source_t *dest_source, uint8_t priority, cyhal_dma_direction_t direction)
{
CY_ASSERT(NULL != obj);
obj->direction = direction;
obj->callback_data.callback = NULL;
obj->callback_data.callback_arg = NULL;
obj->irq_cause = 0;
obj->source = CYHAL_TRIGGER_CPUSS_ZERO;
cy_rslt_t rslt;
cyhal_source_t *src_trigger = (NULL == src) ? NULL : &src->source;
cyhal_dest_t *dest_trigger = (NULL == dest) ? NULL : &dest->dest;
#if !defined(CY_IP_M4CPUSS_DMAC) && defined(CY_IP_M4CPUSS_DMA)
/* Only DW available. Ignore direction for purpose of choosing DMA type. */
CY_UNUSED_PARAMETER(direction);
return _cyhal_dma_dw_init(obj, priority);
#elif defined(CY_IP_M4CPUSS_DMAC) && !defined(CY_IP_M4CPUSS_DMA)
/* Only DMAC available. Ignore direction for purpose of choosing DMA type. */
CY_UNUSED_PARAMETER(direction);
return _cyhal_dma_dmac_init(obj, priority);
/* Only DW available. */
rslt = _cyhal_dma_dw_init(obj, src_trigger, dest_trigger, priority);
#elif (defined(CY_IP_M4CPUSS_DMAC) && !defined(CY_IP_M4CPUSS_DMA)) || defined(CY_IP_M0S8CPUSSV3_DMAC)
/* Only DMAC available. */
rslt = _cyhal_dma_dmac_init(obj, src_trigger, dest_trigger, priority);
#else
/* DMAC is designed with high memory bandwidth for memory to memory
* transfers so prefer it when direction is MEM2MEM. Otherwise prefer
* Datawire as it is designed for low latency memory to peripheral or
* peripheral to memory transfers. Note: Both DMA types can handle any
* direction value so using a non-ideal DMA type is ok.*/
cy_rslt_t rslt;
if(direction == CYHAL_DMA_DIRECTION_MEM2MEM)
{
rslt = _cyhal_dma_dmac_init(obj, priority);
rslt = _cyhal_dma_dmac_init(obj, src_trigger, dest_trigger, priority);
/* If no DMAC channels are available fall back on DW. */
if(CYHAL_HWMGR_RSLT_ERR_NONE_FREE == rslt)
rslt = _cyhal_dma_dw_init(obj, priority);
rslt = _cyhal_dma_dw_init(obj, src_trigger, dest_trigger, priority);
}
else
{
rslt = _cyhal_dma_dw_init(obj, priority);
rslt = _cyhal_dma_dw_init(obj, src_trigger, dest_trigger, priority);
/* If no DW channels are available fall back on DMAC. */
if(CYHAL_HWMGR_RSLT_ERR_NONE_FREE == rslt)
rslt = _cyhal_dma_dmac_init(obj, priority);
rslt = _cyhal_dma_dmac_init(obj, src_trigger, dest_trigger, priority);
}
return rslt;
#endif
if (CY_RSLT_SUCCESS == rslt)
{
if (NULL != src)
{
rslt = cyhal_dma_connect_digital(obj, src->source, src->input);
obj->source = src->source;
}
if (CY_RSLT_SUCCESS == rslt && NULL != dest)
{
rslt = cyhal_dma_enable_output(obj, dest->output, dest_source);
}
// If connection setup failed, free the resources.
if (CY_RSLT_SUCCESS != rslt)
{
cyhal_dma_free(obj);
}
}
return rslt;
}
void cyhal_dma_free(cyhal_dma_t *obj)
{
CY_ASSERT(NULL != obj);
CY_ASSERT(!cyhal_dma_is_busy(obj));
#ifdef CY_IP_M4CPUSS_DMAC
cy_rslt_t rslt;
// DMA signal enum values don't matter since they are actually the same connection
rslt = cyhal_dma_disable_output(obj, CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS);
CY_ASSERT(CY_RSLT_SUCCESS == rslt);
if (CYHAL_TRIGGER_CPUSS_ZERO != obj->source)
{
rslt = cyhal_dma_disconnect_digital(obj, obj->source, CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS);
CY_ASSERT(CY_RSLT_SUCCESS == rslt);
}
(void)rslt; // Disable compiler warning in release build
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
if(obj->resource.type == CYHAL_RSC_DMA)
{
_cyhal_dma_dmac_free(obj);
}
#endif
#ifdef CY_IP_M4CPUSS_DMA
#if defined(CY_IP_M4CPUSS_DMA)
if(obj->resource.type == CYHAL_RSC_DW)
{
_cyhal_dma_dw_free(obj);
}
#endif
cyhal_hwmgr_free(&obj->resource);
}
cy_rslt_t cyhal_dma_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg)
{
CY_ASSERT(NULL != obj);
#ifdef CY_IP_M4CPUSS_DMAC
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
if(obj->resource.type == CYHAL_RSC_DMA)
{
return _cyhal_dma_dmac_configure(obj, cfg);
}
#endif
#ifdef CY_IP_M4CPUSS_DMA
#if defined(CY_IP_M4CPUSS_DMA)
if(obj->resource.type == CYHAL_RSC_DW)
{
return _cyhal_dma_dw_configure(obj, cfg);
@ -126,13 +168,13 @@ cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj)
{
CY_ASSERT(NULL != obj);
#ifdef CY_IP_M4CPUSS_DMAC
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
if(obj->resource.type == CYHAL_RSC_DMA)
{
return _cyhal_dma_dmac_start_transfer(obj);
}
#endif
#ifdef CY_IP_M4CPUSS_DMA
#if defined(CY_IP_M4CPUSS_DMA)
if(obj->resource.type == CYHAL_RSC_DW)
{
return _cyhal_dma_dw_start_transfer(obj);
@ -149,13 +191,13 @@ bool cyhal_dma_is_busy(cyhal_dma_t *obj)
{
CY_ASSERT(NULL != obj);
#ifdef CY_IP_M4CPUSS_DMAC
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
if(obj->resource.type == CYHAL_RSC_DMA)
{
return _cyhal_dma_dmac_is_busy(obj);
}
#endif
#ifdef CY_IP_M4CPUSS_DMA
#if defined(CY_IP_M4CPUSS_DMA)
if(obj->resource.type == CYHAL_RSC_DW)
{
return _cyhal_dma_dw_is_busy(obj);
@ -182,13 +224,13 @@ void cyhal_dma_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t i
{
CY_ASSERT(NULL != obj);
#ifdef CY_IP_M4CPUSS_DMAC
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
if(obj->resource.type == CYHAL_RSC_DMA)
{
_cyhal_dma_dmac_enable_event(obj, event, intr_priority, enable);
}
#endif
#ifdef CY_IP_M4CPUSS_DMA
#if defined(CY_IP_M4CPUSS_DMA)
if(obj->resource.type == CYHAL_RSC_DW)
{
_cyhal_dma_dw_enable_event(obj, event, intr_priority, enable);
@ -196,10 +238,100 @@ void cyhal_dma_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t i
#endif
}
cy_rslt_t cyhal_dma_connect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input)
{
CY_ASSERT(NULL != obj);
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
if(obj->resource.type == CYHAL_RSC_DMA)
{
return _cyhal_dma_dmac_connect_digital(obj, source, input);
}
#endif
#ifdef CY_IP_M4CPUSS_DMA
if(obj->resource.type == CYHAL_RSC_DW)
{
return _cyhal_dma_dw_connect_digital(obj, source, input);
}
#endif
/* Control should never reach here but return value anyway to appease
* compilers */
CY_ASSERT(false);
return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE;
}
cy_rslt_t cyhal_dma_enable_output(cyhal_dma_t *obj, cyhal_dma_output_t output, cyhal_source_t *source)
{
CY_ASSERT(NULL != obj);
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
if(obj->resource.type == CYHAL_RSC_DMA)
{
return _cyhal_dma_dmac_enable_output(obj, output, source);
}
#endif
#ifdef CY_IP_M4CPUSS_DMA
if(obj->resource.type == CYHAL_RSC_DW)
{
return _cyhal_dma_dw_enable_output(obj, output, source);
}
#endif
/* Control should never reach here but return value anyway to appease
* compilers */
CY_ASSERT(false);
return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE;
}
cy_rslt_t cyhal_dma_disconnect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input)
{
CY_ASSERT(NULL != obj);
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
if(obj->resource.type == CYHAL_RSC_DMA)
{
return _cyhal_dma_dmac_disconnect_digital(obj, source, input);
}
#endif
#ifdef CY_IP_M4CPUSS_DMA
if(obj->resource.type == CYHAL_RSC_DW)
{
return _cyhal_dma_dw_disconnect_digital(obj, source, input);
}
#endif
/* Control should never reach here but return value anyway to appease
* compilers */
CY_ASSERT(false);
return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE;
}
cy_rslt_t cyhal_dma_disable_output(cyhal_dma_t *obj, cyhal_dma_output_t output)
{
CY_ASSERT(NULL != obj);
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
if(obj->resource.type == CYHAL_RSC_DMA)
{
return _cyhal_dma_dmac_disable_output(obj, output);
}
#endif
#ifdef CY_IP_M4CPUSS_DMA
if(obj->resource.type == CYHAL_RSC_DW)
{
return _cyhal_dma_dw_disable_output(obj, output);
}
#endif
/* Control should never reach here but return value anyway to appease
* compilers */
CY_ASSERT(false);
return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE;
}
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) */
/** \} group_hal_dma */
#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) || defined(CY_IP_M0S8CPUSSV3_DMAC) */

406
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dmac.c Normal file → Executable file
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -26,6 +26,8 @@
#include "cyhal_dma_dmac.h"
#include "cyhal_dma_impl.h"
#include "cyhal_hwmgr.h"
#include "cyhal_hwmgr_impl.h"
#include "cyhal_interconnect.h"
#include "cyhal_syspm.h"
#include "cyhal_utils.h"
#include "cyhal_triggers.h"
@ -34,25 +36,35 @@
extern "C" {
#endif
#ifdef CY_IP_M4CPUSS_DMAC
#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC)
#if defined(CY_IP_M4CPUSS_DMAC)
#define DMAC_IRQ_NUM (cpuss_interrupts_dmac_0_IRQn)
#define GET_RESOURCE_DATA(x) (x.dmac)
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
#define DMAC_IRQ_NUM (cpuss_interrupt_dma_IRQn)
#define GET_RESOURCE_DATA(x) (x)
#define CY_TRIGGER_TWO_CYCLES (2)
#endif
static cyhal_dma_t* _cyhal_dma_dmac_config_structs[CPUSS_DMAC_CH_NR];
/** Default dmac descriptor config */
static const cy_stc_dmac_descriptor_config_t _cyhal_dma_dmac_default_descriptor_config =
{
.srcAddress = 0,
.dstAddress = 0,
.dataSize = CY_DMAC_WORD,
.dstTransferSize = CY_DMAC_TRANSFER_SIZE_DATA,
.srcTransferSize = CY_DMAC_TRANSFER_SIZE_DATA,
.retrigger = CY_DMAC_RETRIG_IM,
#if defined(CY_IP_M4CPUSS_DMAC)
.interruptType = CY_DMAC_DESCR,
.triggerOutType = CY_DMAC_DESCR_CHAIN,
.channelState = CY_DMAC_CHANNEL_ENABLED,
.triggerInType = CY_DMAC_DESCR,
.dataPrefetch = false,
.dataSize = CY_DMAC_WORD,
.srcTransferSize = CY_DMAC_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMAC_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMAC_1D_TRANSFER,
.srcAddress = 0,
.dstAddress = 0,
.srcXincrement = 1U,
.dstXincrement = 1U,
.xCount = 1UL,
@ -60,15 +72,28 @@ static const cy_stc_dmac_descriptor_config_t _cyhal_dma_dmac_default_descriptor_
.dstYincrement = 0U,
.yCount = 1UL,
.nextDescriptor = 0,
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
.triggerType = CY_DMAC_SINGLE_DESCR,
.dataCount = 1,
.dstAddrIncrement = true,
.srcAddrIncrement = true,
.interrupt = true,
.preemptable = true,
.flipping = false,
#endif
};
/** Default dmac channel config */
static const cy_stc_dmac_channel_config_t _cyhal_dma_dmac_default_channel_config =
{
.descriptor = 0,
.priority = 1,
.enable = false,
#if defined(CY_IP_M4CPUSS_DMAC)
.bufferable = false,
.descriptor = 0,
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
.descriptor = CY_DMAC_DESCRIPTOR_PING,
#endif
};
static bool _cyhal_dma_dmac_pm_callback(cyhal_syspm_callback_state_t state, cyhal_syspm_callback_mode_t mode, void* callback_arg);
@ -97,14 +122,12 @@ static bool _cyhal_dma_dmac_pm_callback(cyhal_syspm_callback_state_t state, cyha
switch(mode)
{
case CYHAL_SYSPM_CHECK_READY:
for (uint8_t i = 0; i < CPUSS_DMAC_CH_NR && !block_transition; i++)
{
block_transition |= (_cyhal_dma_dmac_config_structs[i] != NULL) && _cyhal_dma_dmac_is_busy(_cyhal_dma_dmac_config_structs[i]);
}
_cyhal_dma_dmac_pm_transition_pending = !block_transition;
break;
case CYHAL_SYSPM_CHECK_FAIL:
case CYHAL_SYSPM_AFTER_TRANSITION:
_cyhal_dma_dmac_pm_transition_pending = false;
@ -141,25 +164,32 @@ static inline uint8_t _cyhal_dma_dmac_get_block_from_irqn(IRQn_Type irqn)
/* Since there is only one dmac block this function always returns 0. diff
* is calculated here only to verify that this was called from a valid
* IRQn. */
CY_ASSERT(irqn >= cpuss_interrupts_dmac_0_IRQn && irqn < cpuss_interrupts_dmac_0_IRQn + (IRQn_Type)CPUSS_DMAC_CH_NR);
#if defined(CY_IP_M4CPUSS_DMAC)
CY_ASSERT(irqn >= DMAC_IRQ_NUM && irqn < DMAC_IRQ_NUM + (IRQn_Type)CPUSS_DMAC_CH_NR);
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
CY_ASSERT(irqn >= DMAC_IRQ_NUM && irqn < DMAC_IRQ_NUM + ((int)CY_IP_M0S8CPUSSV3_DMAC_INSTANCES));
#endif
return 0;
}
#if defined(CY_IP_M4CPUSS_DMAC)
/** Gets the dmac channel number from irq number */
/** This should never be called from a non-dma IRQn */
static inline uint8_t _cyhal_dma_dmac_get_channel_from_irqn(IRQn_Type irqn)
{
uint8_t diff = irqn - cpuss_interrupts_dmac_0_IRQn;
uint8_t diff = irqn - DMAC_IRQ_NUM;
CY_ASSERT(diff < CPUSS_DMAC_CH_NR);
return diff;
}
#endif
/** Gets the irqn corresponding to a particular cyhal_dma_t config struct */
static inline IRQn_Type _cyhal_dma_dmac_get_irqn(cyhal_dma_t *obj)
{
return (IRQn_Type)((uint8_t)cpuss_interrupts_dmac_0_IRQn + (obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num));
return (IRQn_Type)((uint8_t)DMAC_IRQ_NUM + (obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num));
}
/** Gets the dmac base pointer from block number */
@ -177,7 +207,7 @@ static inline uint32_t _cyhal_dma_dmac_get_trigger_line(uint8_t block_num, uint8
/* cyhal_dest_t triggers are guaranteed to be sorted by trigger type, block
* num, then channel num, therefore, we can just directly find the proper
* trigger by calculating an offset. */
cyhal_dest_t trigger = (cyhal_dest_t)(TRIGGER_CPUSS_DMAC_TR_IN0 + (block_num * CPUSS_DMAC_CH_NR) + channel_num);
cyhal_dest_t trigger = (cyhal_dest_t)(CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 + (block_num * CPUSS_DMAC_CH_NR) + channel_num);
/* One to one triggers have bit 8 set in cyhal_dest_to_mux but
* Cy_TrigMux_SwTrigger wants the trigger group field to have bit 5 set to
@ -193,9 +223,14 @@ static inline uint32_t _cyhal_dma_dmac_get_trigger_line(uint8_t block_num, uint8
* Bits 30: Input/output bit. Set to 1 for output.
* Bits 12-8: Trigger group selection.
* Bits 7-0: Select the output trigger number in the trigger group. */
#if defined(CY_IP_M4CPUSS_DMAC)
return PERI_TR_CMD_OUT_SEL_Msk | trig_group << 8 | cyhal_mux_dest_index[trigger];
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
return PERI_TR_CTL_TR_OUT_Msk | trig_group << 8 | cyhal_mux_dest_index[trigger];
#endif
}
#if defined(CY_IP_M4CPUSS_DMAC)
/** Convert PDL interrupt cause to hal dma event */
static inline cyhal_dma_event_t _cyhal_dma_dmac_convert_interrupt_cause(uint32_t cause)
{
@ -221,17 +256,20 @@ static inline cyhal_dma_event_t _cyhal_dma_dmac_convert_interrupt_cause(uint32_t
return CYHAL_DMA_NO_INTR;
}
}
#endif
/** DMAC irq handler */
static void _cyhal_dma_dmac_irq_handler(void)
{
/* Use irqn to get appropriate config structure */
uint8_t block = _cyhal_dma_dmac_get_block_from_irqn(_CYHAL_UTILS_GET_CURRENT_IRQN());
DMAC_Type* base = _cyhal_dma_dmac_get_base(block);
#if defined(CY_IP_M4CPUSS_DMAC)
uint8_t channel = _cyhal_dma_dmac_get_channel_from_irqn(_CYHAL_UTILS_GET_CURRENT_IRQN());
cyhal_dma_t *obj = _cyhal_dma_dmac_get_obj(block, channel);
/* Get interrupt type and call users event callback if they have enabled that event */
uint32_t cause = Cy_DMAC_Channel_GetInterruptStatusMasked(_cyhal_dma_dmac_get_base(block), channel);
uint32_t cause = Cy_DMAC_Channel_GetInterruptStatusMasked(base, channel);
cyhal_dma_event_t event_type = _cyhal_dma_dmac_convert_interrupt_cause(cause);
uint32_t events_to_callback = event_type & obj->irq_cause;
if(obj->callback_data.callback != NULL && events_to_callback)
@ -240,10 +278,35 @@ static void _cyhal_dma_dmac_irq_handler(void)
}
/* Clear all interrupts */
Cy_DMAC_Channel_ClearInterrupt(_cyhal_dma_dmac_get_base(block), channel, CY_DMAC_INTR_MASK);
Cy_DMAC_Channel_ClearInterrupt(base, channel, CY_DMAC_INTR_MASK);
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
uint32_t channels = Cy_DMAC_GetInterruptStatusMasked(base);
for(int i = 0 ; ((uint32_t)(1 << i)) <= channels ; i++)
{
cyhal_dma_t *obj = _cyhal_dma_dmac_get_obj(block, i);
if (obj != NULL)
{
if ((channels & (1 << i)) != 0 && obj->callback_data.callback != NULL)
{
((cyhal_dma_event_callback_t)obj->callback_data.callback)(obj->callback_data.callback_arg, CYHAL_DMA_TRANSFER_COMPLETE);
}
}
}
Cy_DMAC_ClearInterrupt(_cyhal_dma_dmac_get_base(block), channels);
#endif
}
cy_rslt_t _cyhal_dma_dmac_init(cyhal_dma_t *obj, uint8_t priority)
static cyhal_source_t _cyhal_dma_dmac_get_src(uint8_t block_num, uint8_t channel_num)
{
return (cyhal_source_t)(CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 + (block_num * CPUSS_DMAC_CH_NR) + channel_num);
}
static cyhal_dest_t _cyhal_dma_dmac_get_dest(uint8_t block_num, uint8_t channel_num)
{
return (cyhal_dest_t)(CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 + (block_num * CPUSS_DMAC_CH_NR) + channel_num);
}
cy_rslt_t _cyhal_dma_dmac_init(cyhal_dma_t *obj, cyhal_source_t *src, cyhal_dest_t *dest, uint8_t priority)
{
if(!CY_DMAC_IS_PRIORITY_VALID(priority))
return CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY;
@ -253,19 +316,20 @@ cy_rslt_t _cyhal_dma_dmac_init(cyhal_dma_t *obj, uint8_t priority)
return CYHAL_SYSPM_RSLT_ERR_PM_PENDING;
}
cy_rslt_t rslt = cyhal_hwmgr_allocate(CYHAL_RSC_DMA, &obj->resource);
cy_rslt_t rslt = _cyhal_hwmgr_allocate_with_connection(
CYHAL_RSC_DMA, src, dest, _cyhal_dma_dmac_get_src, _cyhal_dma_dmac_get_dest, &obj->resource);
if(rslt != CY_RSLT_SUCCESS)
return rslt;
/* Setup descriptor and channel configs */
obj->descriptor_config.dmac = _cyhal_dma_dmac_default_descriptor_config;
obj->channel_config.dmac = _cyhal_dma_dmac_default_channel_config;
obj->channel_config.dmac.descriptor = &obj->descriptor.dmac;
obj->channel_config.dmac.priority = priority;
obj->callback_data.callback = NULL;
obj->callback_data.callback_arg = NULL;
obj->irq_cause = 0;
GET_RESOURCE_DATA(obj->descriptor_config) = _cyhal_dma_dmac_default_descriptor_config;
GET_RESOURCE_DATA(obj->channel_config) = _cyhal_dma_dmac_default_channel_config;
#if defined(CY_IP_M4CPUSS_DMAC)
GET_RESOURCE_DATA(obj->channel_config).descriptor = GET_RESOURCE_DATA(&obj->descriptor);
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
obj->descriptor = obj->channel_config.descriptor;
#endif
GET_RESOURCE_DATA(obj->channel_config).priority = priority;
if (!_cyhal_dma_dmac_has_enabled())
{
@ -279,8 +343,14 @@ cy_rslt_t _cyhal_dma_dmac_init(cyhal_dma_t *obj, uint8_t priority)
void _cyhal_dma_dmac_free(cyhal_dma_t *obj)
{
Cy_DMAC_Descriptor_DeInit(&obj->descriptor.dmac);
Cy_DMAC_Channel_DeInit(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num);
DMAC_Type* base = _cyhal_dma_dmac_get_base(obj->resource.block_num);
#if defined(CY_IP_M4CPUSS_DMAC)
Cy_DMAC_Descriptor_DeInit(GET_RESOURCE_DATA(&obj->descriptor));
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
Cy_DMAC_Descriptor_DeInit(base, obj->resource.channel_num, obj->descriptor);
#endif
Cy_DMAC_Channel_DeInit(base, obj->resource.channel_num);
NVIC_DisableIRQ(_cyhal_dma_dmac_get_irqn(obj));
@ -291,11 +361,9 @@ void _cyhal_dma_dmac_free(cyhal_dma_t *obj)
_cyhal_syspm_unregister_peripheral_callback(&_cyhal_dma_dmac_pm_callback_args);
_cyhal_dma_dmac_pm_transition_pending = false;
}
cyhal_hwmgr_free(&obj->resource);
}
/* Initalize descriptor, initialize channel, enable channel, enable channel
/* Initialize descriptor, initialize channel, enable channel, enable channel
* interrupt, and enable DMAC controller */
cy_rslt_t _cyhal_dma_dmac_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg)
{
@ -303,67 +371,102 @@ cy_rslt_t _cyhal_dma_dmac_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg
if(_cyhal_dma_dmac_is_busy(obj))
return CYHAL_DMA_RSLT_ERR_CHANNEL_BUSY;
obj->descriptor_config.dmac.srcAddress = (void*)cfg->src_addr;
obj->descriptor_config.dmac.dstAddress = (void*)cfg->dst_addr;
obj->descriptor_config.dmac.nextDescriptor = &obj->descriptor.dmac;
GET_RESOURCE_DATA(obj->descriptor_config).srcAddress = (void*)cfg->src_addr;
GET_RESOURCE_DATA(obj->descriptor_config).dstAddress = (void*)cfg->dst_addr;
if(cfg->transfer_width == 8)
obj->descriptor_config.dmac.dataSize = CY_DMAC_BYTE;
GET_RESOURCE_DATA(obj->descriptor_config).dataSize = CY_DMAC_BYTE;
else if(cfg->transfer_width == 16)
obj->descriptor_config.dmac.dataSize = CY_DMAC_HALFWORD;
GET_RESOURCE_DATA(obj->descriptor_config).dataSize = CY_DMAC_HALFWORD;
else if(cfg->transfer_width == 32)
obj->descriptor_config.dmac.dataSize = CY_DMAC_WORD;
GET_RESOURCE_DATA(obj->descriptor_config).dataSize = CY_DMAC_WORD;
else
return CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH;
/* Length must be a multiple of burst_size */
if(cfg->burst_size != 0 && cfg->length % cfg->burst_size != 0)
return CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE;
/* By default, transfer what the user set for dataSize. However, if transfering between memory
* and a peripheral, make sure the peripheral access is using words. */
GET_RESOURCE_DATA(obj->descriptor_config).srcTransferSize =
GET_RESOURCE_DATA(obj->descriptor_config).dstTransferSize = CY_DMAC_TRANSFER_SIZE_DATA;
if (obj->direction == CYHAL_DMA_DIRECTION_PERIPH2MEM)
GET_RESOURCE_DATA(obj->descriptor_config).srcTransferSize = CY_DMAC_TRANSFER_SIZE_WORD;
else if (obj->direction == CYHAL_DMA_DIRECTION_MEM2PERIPH)
GET_RESOURCE_DATA(obj->descriptor_config).dstTransferSize = CY_DMAC_TRANSFER_SIZE_WORD;
#if defined(CY_IP_M4CPUSS_DMAC)
GET_RESOURCE_DATA(obj->descriptor_config).nextDescriptor = GET_RESOURCE_DATA(&obj->descriptor);
/* Setup 2D transfer if burst_size is being used otherwise set up 1D
* transfer */
if(cfg->burst_size != 0)
{
obj->descriptor_config.dmac.descriptorType = CY_DMAC_2D_TRANSFER;
obj->descriptor_config.dmac.xCount = cfg->burst_size;
obj->descriptor_config.dmac.yCount = cfg->length / cfg->burst_size;
obj->descriptor_config.dmac.srcXincrement = cfg->src_increment;
obj->descriptor_config.dmac.dstXincrement = cfg->dst_increment;
obj->descriptor_config.dmac.srcYincrement = cfg->src_increment * cfg->burst_size;
obj->descriptor_config.dmac.dstYincrement = cfg->dst_increment * cfg->burst_size;
/* Length must be a multiple of burst_size */
if(cfg->length % cfg->burst_size != 0)
return CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE;
GET_RESOURCE_DATA(obj->descriptor_config).descriptorType = CY_DMAC_2D_TRANSFER;
GET_RESOURCE_DATA(obj->descriptor_config).xCount = cfg->burst_size;
GET_RESOURCE_DATA(obj->descriptor_config).yCount = cfg->length / cfg->burst_size;
GET_RESOURCE_DATA(obj->descriptor_config).srcXincrement = cfg->src_increment;
GET_RESOURCE_DATA(obj->descriptor_config).dstXincrement = cfg->dst_increment;
GET_RESOURCE_DATA(obj->descriptor_config).srcYincrement = cfg->src_increment * cfg->burst_size;
GET_RESOURCE_DATA(obj->descriptor_config).dstYincrement = cfg->dst_increment * cfg->burst_size;
/* If burst action, configure trigger and interrupt actions */
if(cfg->action == CYHAL_DMA_TRANSFER_BURST)
{
obj->descriptor_config.dmac.interruptType = CY_DMAC_X_LOOP;
obj->descriptor_config.dmac.triggerInType = CY_DMAC_X_LOOP;
GET_RESOURCE_DATA(obj->descriptor_config).interruptType = CY_DMAC_X_LOOP;
GET_RESOURCE_DATA(obj->descriptor_config).triggerInType = CY_DMAC_X_LOOP;
}
}
else
{
obj->descriptor_config.dmac.descriptorType = CY_DMAC_1D_TRANSFER;
obj->descriptor_config.dmac.xCount = cfg->length;
obj->descriptor_config.dmac.srcXincrement = cfg->src_increment;
obj->descriptor_config.dmac.dstXincrement = cfg->dst_increment;
GET_RESOURCE_DATA(obj->descriptor_config).descriptorType = CY_DMAC_1D_TRANSFER;
GET_RESOURCE_DATA(obj->descriptor_config).xCount = cfg->length;
GET_RESOURCE_DATA(obj->descriptor_config).srcXincrement = cfg->src_increment;
GET_RESOURCE_DATA(obj->descriptor_config).dstXincrement = cfg->dst_increment;
obj->descriptor_config.dmac.interruptType = CY_DMAC_DESCR;
obj->descriptor_config.dmac.triggerInType = CY_DMAC_DESCR;
GET_RESOURCE_DATA(obj->descriptor_config).interruptType = CY_DMAC_DESCR;
GET_RESOURCE_DATA(obj->descriptor_config).triggerInType = CY_DMAC_DESCR;
}
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
if(cfg->burst_size != 0)
{
return CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE;
}
else
{
GET_RESOURCE_DATA(obj->descriptor_config).dataCount = cfg->length;
GET_RESOURCE_DATA(obj->descriptor_config).srcAddrIncrement = cfg->src_increment;
GET_RESOURCE_DATA(obj->descriptor_config).dstAddrIncrement = cfg->dst_increment;
}
#endif
if(CY_DMAC_SUCCESS != Cy_DMAC_Descriptor_Init(&obj->descriptor.dmac, &obj->descriptor_config.dmac))
DMAC_Type* base = _cyhal_dma_dmac_get_base(obj->resource.block_num);
#if defined(CY_IP_M4CPUSS_DMAC)
cy_rslt_t rslt = Cy_DMAC_Descriptor_Init(GET_RESOURCE_DATA(&obj->descriptor), GET_RESOURCE_DATA(&obj->descriptor_config));
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
cy_rslt_t rslt = Cy_DMAC_Descriptor_Init(base, obj->resource.channel_num, obj->descriptor, GET_RESOURCE_DATA(&obj->descriptor_config));
#endif
if(CY_DMAC_SUCCESS != rslt)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
/* Setup channel and enable */
DMAC_Type* base = _cyhal_dma_dmac_get_base(obj->resource.block_num);
if(CY_DMAC_SUCCESS != Cy_DMAC_Channel_Init(base, obj->resource.channel_num, &obj->channel_config.dmac))
if(CY_DMAC_SUCCESS != Cy_DMAC_Channel_Init(base, obj->resource.channel_num, GET_RESOURCE_DATA(&obj->channel_config)))
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
Cy_DMAC_Channel_SetDescriptor(base, obj->resource.channel_num, &obj->descriptor.dmac);
Cy_DMAC_Channel_SetPriority(base, obj->resource.channel_num, obj->channel_config.dmac.priority);
#if defined(CY_IP_M4CPUSS_DMAC)
Cy_DMAC_Channel_SetDescriptor(base, obj->resource.channel_num, GET_RESOURCE_DATA(&obj->descriptor));
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
Cy_DMAC_Channel_SetCurrentDescriptor(base, obj->resource.channel_num, obj->descriptor);
#endif
Cy_DMAC_Channel_SetPriority(base, obj->resource.channel_num, GET_RESOURCE_DATA(obj->channel_config).priority);
Cy_DMAC_Channel_Enable(base, obj->resource.channel_num);
Cy_DMAC_Channel_SetInterruptMask (base, obj->resource.channel_num, CY_DMAC_INTR_MASK);
#if defined(CY_IP_M4CPUSS_DMAC)
Cy_DMAC_Channel_SetInterruptMask(base, obj->resource.channel_num, CY_DMAC_INTR_MASK);
#endif
Cy_DMAC_Enable(base);
#if defined(CY_IP_M4CPUSS_DMAC)
/* src_misal and dst_misal interrupts are triggered immediately on enable
* so return those errors here */
uint32_t status = Cy_DMAC_Channel_GetInterruptStatus(base, obj->resource.channel_num);
@ -374,6 +477,7 @@ cy_rslt_t _cyhal_dma_dmac_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg
Cy_DMAC_Channel_ClearInterrupt(base, obj->resource.channel_num, CY_DMAC_INTR_MASK);
return CYHAL_DMA_RSLT_ERR_INVALID_ALIGNMENT;
}
#endif
/* Enable interrupt for this channel */
cy_stc_sysint_t irqCfg = { _cyhal_dma_dmac_get_irqn(obj), CYHAL_ISR_PRIORITY_DEFAULT };
@ -406,21 +510,195 @@ cy_rslt_t _cyhal_dma_dmac_start_transfer(cyhal_dma_t *obj)
void _cyhal_dma_dmac_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intr_priority, bool enable)
{
#if defined (CY_IP_M0S8CPUSSV3_DMAC)
DMAC_Type *base = _cyhal_dma_dmac_get_base(obj->resource.block_num);
uint32_t mask = Cy_DMAC_GetInterruptMask(base);
#endif
if(enable)
{
#if defined (CY_IP_M0S8CPUSSV3_DMAC)
Cy_DMAC_SetInterruptMask(base, mask | (1 << obj->resource.channel_num));
#endif
obj->irq_cause |= event;
}
else
{
#if defined (CY_IP_M0S8CPUSSV3_DMAC)
Cy_DMAC_SetInterruptMask(base, mask & ~(1 << obj->resource.channel_num));
#endif
obj->irq_cause &= ~event;
}
NVIC_SetPriority(_cyhal_dma_dmac_get_irqn(obj), intr_priority);
}
bool _cyhal_dma_dmac_is_busy(cyhal_dma_t *obj)
{
/* The ACTIVE register is a bit field of all pending or active channels */
return _cyhal_dma_dmac_get_base(obj->resource.block_num)->ACTIVE & (1 << obj->resource.channel_num);
/* The value is a bit field of all pending or active channels */
return Cy_DMAC_GetActiveChannel(_cyhal_dma_dmac_get_base(obj->resource.block_num)) & (1 << obj->resource.channel_num);
}
#endif /* CY_IP_M4CPUSS_DMAC */
#if defined(CY_IP_M4CPUSS_DMAC)
static cy_en_dma_trigger_type_t _cyhal_convert_input_t(cyhal_dma_input_t input)
{
switch(input)
{
case CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT:
return CY_DMA_1ELEMENT;
case CYHAL_DMA_INPUT_TRIGGER_SINGLE_BURST:
return CY_DMA_X_LOOP;
case CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS:
return CY_DMA_DESCR;
}
// Should never reach here. Just silencing compiler warnings.
CY_ASSERT(false);
return CY_DMA_DESCR;
}
static cy_en_dma_trigger_type_t _cyhal_convert_output_t(cyhal_dma_output_t output)
{
switch(output)
{
case CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT:
return CY_DMA_1ELEMENT;
case CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_BURST:
return CY_DMA_X_LOOP;
case CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS:
return CY_DMA_DESCR;
}
// Should never reach here. Just silencing compiler warnings.
CY_ASSERT(false);
return CY_DMA_DESCR;
}
cy_rslt_t _cyhal_dma_dmac_connect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input)
{
if(input != CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT &&
input != CYHAL_DMA_INPUT_TRIGGER_SINGLE_BURST &&
input != CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
Cy_DMAC_Channel_Disable(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num);
obj->descriptor.dmac.ctl &= ~DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Msk;
obj->descriptor.dmac.ctl |= _VAL2FLD(DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE, _cyhal_convert_input_t(input));
Cy_DMAC_Channel_Enable(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num);
cyhal_dest_t dest = _cyhal_dma_dmac_get_dest(obj->resource.block_num, obj->resource.channel_num);
return _cyhal_connect_signal(source, dest, CYHAL_SIGNAL_TYPE_EDGE);
}
cy_rslt_t _cyhal_dma_dmac_enable_output(cyhal_dma_t *obj, cyhal_dma_output_t output, cyhal_source_t *source)
{
if(output != CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT &&
output != CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_BURST &&
output != CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
Cy_DMAC_Channel_Disable(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num);
obj->descriptor.dmac.ctl &= ~DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Msk;
obj->descriptor.dmac.ctl |= _VAL2FLD(DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE, _cyhal_convert_output_t(output));
Cy_DMAC_Channel_Enable(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num);
*source = _cyhal_dma_dmac_get_src(obj->resource.block_num, obj->resource.channel_num);
return CY_RSLT_SUCCESS;
}
cy_rslt_t _cyhal_dma_dmac_disconnect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input)
{
if(input != CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT &&
input != CYHAL_DMA_INPUT_TRIGGER_SINGLE_BURST &&
input != CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
Cy_DMAC_Channel_Disable(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num);
// There is no option to totally disable. Just reset to default.
obj->descriptor.dmac.ctl &= ~DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Msk;
obj->descriptor.dmac.ctl |= _VAL2FLD(DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE, _cyhal_dma_dmac_default_descriptor_config.triggerInType);
Cy_DMAC_Channel_Enable(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num);
cyhal_dest_t dest = _cyhal_dma_dmac_get_dest(obj->resource.block_num, obj->resource.channel_num);
return _cyhal_disconnect_signal(source, dest);
}
cy_rslt_t _cyhal_dma_dmac_disable_output(cyhal_dma_t *obj, cyhal_dma_output_t output)
{
if(output != CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT &&
output != CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_BURST &&
output != CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
Cy_DMAC_Channel_Disable(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num);
// There is no option to totally disable. Just reset to default.
obj->descriptor.dmac.ctl &= ~DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Msk;
obj->descriptor.dmac.ctl |= _VAL2FLD(DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE, _cyhal_dma_dmac_default_descriptor_config.triggerOutType);
Cy_DMAC_Channel_Enable(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num);
return CY_RSLT_SUCCESS;
}
#elif defined(CY_IP_M0S8CPUSSV3_DMAC)
cy_rslt_t _cyhal_dma_dmac_connect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input)
{
if(input != CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT &&
input != CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
Cy_DMAC_Channel_SetCurrentDescriptor(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num, obj->descriptor);
cyhal_dest_t dest = (cyhal_dest_t)(CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 + obj->resource.channel_num);
return _cyhal_connect_signal(source, dest, CYHAL_SIGNAL_TYPE_EDGE);
}
// M0S8 output triggers are always active. This is a noop except to return the source.
cy_rslt_t _cyhal_dma_dmac_enable_output(cyhal_dma_t *obj, cyhal_dma_output_t output, cyhal_source_t *source)
{
if(output != CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT &&
output != CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
*source = (cyhal_source_t)(CYHAL_TRIGGER_CPUSS_DMAC_TR_OUT0 + (obj->resource.block_num * CPUSS_DMAC_CH_NR) + obj->resource.channel_num);
return CY_RSLT_SUCCESS;
}
cy_rslt_t _cyhal_dma_dmac_disconnect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input)
{
if(input != CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT &&
input != CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
// Reset to default
Cy_DMAC_Channel_SetCurrentDescriptor(_cyhal_dma_dmac_get_base(obj->resource.block_num), obj->resource.channel_num, obj->descriptor);
cyhal_dest_t dest = (cyhal_dest_t)(CYHAL_TRIGGER_CPUSS_DMAC_TR_IN0 + obj->resource.channel_num);
return _cyhal_disconnect_signal(source, dest);
}
// M0S8 output triggers are always active. This is a noop.
cy_rslt_t _cyhal_dma_dmac_disable_output(cyhal_dma_t *obj, cyhal_dma_output_t output)
{
CY_UNUSED_PARAMETER(obj);
if(output != CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT &&
output != CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
return CY_RSLT_SUCCESS;
}
#endif
#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M0S8CPUSSV3_DMAC) */
#if defined(__cplusplus)
}

145
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dw.c Normal file → Executable file
View File

@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
* Copyright 2018-2020 Cypress Semiconductor Corporation
* Copyright 2018-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@ -26,6 +26,8 @@
#include "cyhal_dma_dw.h"
#include "cyhal_dma_impl.h"
#include "cyhal_hwmgr.h"
#include "cyhal_hwmgr_impl.h"
#include "cyhal_interconnect.h"
#include "cyhal_syspm.h"
#include "cyhal_utils.h"
#include "cyhal_triggers.h"
@ -191,7 +193,7 @@ static inline uint32_t _cyhal_dma_dw_get_trigger_line(uint8_t block_num, uint8_t
/* cyhal_dest_t triggers are guaranteed to be sorted by trigger type, block
* num, then channel num, therefore, we can just directly find the proper
* trigger by calculating an offset. */
cyhal_dest_t trigger = (cyhal_dest_t)(TRIGGER_CPUSS_DW0_TR_IN0 + (block_num * CPUSS_DW0_CH_NR) + channel_num);
cyhal_dest_t trigger = (cyhal_dest_t)(CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 + (block_num * CPUSS_DW0_CH_NR) + channel_num);
/* One to one triggers have bit 8 set in cyhal_dest_to_mux but
* Cy_TrigMux_SwTrigger wants the trigger group field to have bit 5 set to
@ -257,12 +259,23 @@ static void _cyhal_dma_dw_irq_handler(void)
Cy_DMA_Channel_ClearInterrupt(_cyhal_dma_dw_get_base(block), channel);
}
cy_rslt_t _cyhal_dma_dw_init(cyhal_dma_t *obj, uint8_t priority)
static cyhal_source_t _cyhal_dma_dw_get_src(uint8_t block_num, uint8_t channel_num)
{
return (cyhal_source_t)(CYHAL_TRIGGER_CPUSS_DW0_TR_OUT0 + (block_num * CPUSS_DW0_CH_NR) + channel_num);
}
static cyhal_dest_t _cyhal_dma_dw_get_dest(uint8_t block_num, uint8_t channel_num)
{
return (cyhal_dest_t)(CYHAL_TRIGGER_CPUSS_DW0_TR_IN0 + (block_num * CPUSS_DW0_CH_NR) + channel_num);
}
cy_rslt_t _cyhal_dma_dw_init(cyhal_dma_t *obj, cyhal_source_t *src, cyhal_dest_t *dest, uint8_t priority)
{
if(!CY_DMA_IS_PRIORITY_VALID(priority))
return CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY;
cy_rslt_t rslt = cyhal_hwmgr_allocate(CYHAL_RSC_DW, &obj->resource);
cy_rslt_t rslt = _cyhal_hwmgr_allocate_with_connection(
CYHAL_RSC_DW, src, dest, _cyhal_dma_dw_get_src, _cyhal_dma_dw_get_dest, &obj->resource);
if(rslt != CY_RSLT_SUCCESS)
return rslt;
@ -272,10 +285,6 @@ cy_rslt_t _cyhal_dma_dw_init(cyhal_dma_t *obj, uint8_t priority)
obj->channel_config.dw.descriptor = &obj->descriptor.dw;
obj->channel_config.dw.priority = priority;
obj->callback_data.callback = NULL;
obj->callback_data.callback_arg = NULL;
obj->irq_cause = 0;
if (!_cyhal_dma_dw_has_enabled())
{
_cyhal_syspm_register_peripheral_callback(&cyhal_dma_dw_pm_callback_args);
@ -300,11 +309,9 @@ void _cyhal_dma_dw_free(cyhal_dma_t *obj)
_cyhal_syspm_unregister_peripheral_callback(&cyhal_dma_dw_pm_callback_args);
_cyhal_dma_dw_pm_transition_pending = false;
}
cyhal_hwmgr_free(&obj->resource);
}
/* Initalize descriptor, initialize channel, enable channel, enable channel
/* Initialize descriptor, initialize channel, enable channel, enable channel
* interrupt, and enable DW controller */
cy_rslt_t _cyhal_dma_dw_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg)
{
@ -325,6 +332,15 @@ cy_rslt_t _cyhal_dma_dw_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg)
else
return CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH;
/* By default, transfer what the user set for dataSize. However, if transfering between memory
* and a peripheral, make sure the peripheral access is using words. */
obj->descriptor_config.dw.srcTransferSize =
obj->descriptor_config.dw.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA;
if (obj->direction == CYHAL_DMA_DIRECTION_PERIPH2MEM)
obj->descriptor_config.dw.srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD;
else if (obj->direction == CYHAL_DMA_DIRECTION_MEM2PERIPH)
obj->descriptor_config.dw.dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD;
/* Length must be a multiple of burst_size */
if(cfg->burst_size != 0 && cfg->length % cfg->burst_size != 0)
return CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE;
@ -440,6 +456,113 @@ bool _cyhal_dma_dw_is_busy(cyhal_dma_t *obj)
#endif
}
static cy_en_dma_trigger_type_t _cyhal_convert_input_t(cyhal_dma_input_t input)
{
switch(input)
{
case CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT:
return CY_DMA_1ELEMENT;
case CYHAL_DMA_INPUT_TRIGGER_SINGLE_BURST:
return CY_DMA_X_LOOP;
case CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS:
return CY_DMA_DESCR;
}
// Should never reach here. Just silencing compiler warnings.
CY_ASSERT(false);
return CY_DMA_DESCR;
}
static cy_en_dma_trigger_type_t _cyhal_convert_output_t(cyhal_dma_output_t output)
{
switch(output)
{
case CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT:
return CY_DMA_1ELEMENT;
case CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_BURST:
return CY_DMA_X_LOOP;
case CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS:
return CY_DMA_DESCR;
}
// Should never reach here. Just silencing compiler warnings.
CY_ASSERT(false);
return CY_DMA_DESCR;
}
cy_rslt_t _cyhal_dma_dw_connect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input)
{
if(input != CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT &&
input != CYHAL_DMA_INPUT_TRIGGER_SINGLE_BURST &&
input != CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
// Check that we are not overwriting an existing connection
CY_ASSERT(obj->source == CYHAL_TRIGGER_CPUSS_ZERO);
obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_IN_TYPE_Msk;
obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_IN_TYPE, _cyhal_convert_input_t(input));
cyhal_dest_t dest = _cyhal_dma_dw_get_dest(obj->resource.block_num, obj->resource.channel_num);
cy_rslt_t rslt = _cyhal_connect_signal(source, dest, CYHAL_SIGNAL_TYPE_EDGE);
if (CY_RSLT_SUCCESS == rslt)
{
obj->source = source;
}
return rslt;
}
cy_rslt_t _cyhal_dma_dw_enable_output(cyhal_dma_t *obj, cyhal_dma_output_t output, cyhal_source_t *source)
{
if(output != CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT &&
output != CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_BURST &&
output != CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_OUT_TYPE_Msk;
obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_OUT_TYPE, _cyhal_convert_output_t(output));
*source = _cyhal_dma_dw_get_src(obj->resource.block_num, obj->resource.channel_num);
return CY_RSLT_SUCCESS;
}
cy_rslt_t _cyhal_dma_dw_disconnect_digital(cyhal_dma_t *obj, cyhal_source_t source, cyhal_dma_input_t input)
{
if(input != CYHAL_DMA_INPUT_TRIGGER_SINGLE_ELEMENT &&
input != CYHAL_DMA_INPUT_TRIGGER_SINGLE_BURST &&
input != CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
CY_ASSERT(obj->source != CYHAL_TRIGGER_CPUSS_ZERO);
// There is no option to totally disable. Just reset to default.
obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_IN_TYPE_Msk;
obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_IN_TYPE, _cyhal_dma_dw_default_descriptor_config.triggerInType);
cyhal_dest_t dest = _cyhal_dma_dw_get_dest(obj->resource.block_num, obj->resource.channel_num);
cy_rslt_t rslt = _cyhal_disconnect_signal(source, dest);
if (CY_RSLT_SUCCESS == rslt)
{
obj->source = CYHAL_TRIGGER_CPUSS_ZERO;
}
return rslt;
}
cy_rslt_t _cyhal_dma_dw_disable_output(cyhal_dma_t *obj, cyhal_dma_output_t output)
{
if(output != CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_ELEMENT &&
output != CYHAL_DMA_OUTPUT_TRIGGER_SINGLE_BURST &&
output != CYHAL_DMA_OUTPUT_TRIGGER_ALL_ELEMENTS)
return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER;
// There is no option to totally disable. Just reset to default.
obj->descriptor.dw.ctl &= ~CY_DMA_CTL_TR_OUT_TYPE_Msk;
obj->descriptor.dw.ctl |= _VAL2FLD(CY_DMA_CTL_TR_OUT_TYPE, _cyhal_dma_dw_default_descriptor_config.triggerOutType);
return CY_RSLT_SUCCESS;
}
#endif /* CY_IP_M4CPUSS_DMA */
#if defined(__cplusplus)

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