diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S
deleted file mode 100644
index fbc2e00a8a..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S
+++ /dev/null
@@ -1,407 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f303xe.s
-;* Author : MCD Application Team
-;* Version : V2.1.0
-;* Date : 12-Sept-2014
-;* Description : STM32F303xE devices vector table for MDK-ARM_MICRO toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; Stack Configuration
-; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
- EXPORT __initial_sp
-
-Stack_Mem SPACE Stack_Size
-__initial_sp EQU 0x20004000 ; Top of RAM
-
-
-; Heap Configuration
-; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-;
-
-Heap_Size EQU 0x00000400
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
- EXPORT __heap_base
- EXPORT __heap_limit
-
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit EQU (__initial_sp - Stack_Size)
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 and ADC2
- DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
- DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
- DCD CAN_RX1_IRQHandler ; CAN RX1
- DCD CAN_SCE_IRQHandler ; CAN SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
- DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
- DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
- DCD TIM8_BRK_IRQHandler ; TIM8 Break
- DCD TIM8_UP_IRQHandler ; TIM8 Update
- DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD FMC_IRQHandler ; FMC
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
- DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
- DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
- DCD ADC4_IRQHandler ; ADC4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
- DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
- DCD COMP7_IRQHandler ; COMP7
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD USB_HP_IRQHandler ; USB High Priority remap
- DCD USB_LP_IRQHandler ; USB Low Priority remap
- DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
- DCD TIM20_BRK_IRQHandler ; TIM20 Break
- DCD TIM20_UP_IRQHandler ; TIM20 Update
- DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
- DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_TSC_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK]
- EXPORT CAN_RX1_IRQHandler [WEAK]
- EXPORT CAN_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TIM8_BRK_IRQHandler [WEAK]
- EXPORT TIM8_UP_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_IRQHandler [WEAK]
- EXPORT DMA2_Channel5_IRQHandler [WEAK]
- EXPORT ADC4_IRQHandler [WEAK]
- EXPORT COMP1_2_3_IRQHandler [WEAK]
- EXPORT COMP4_5_6_IRQHandler [WEAK]
- EXPORT COMP7_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
- EXPORT TIM20_BRK_IRQHandler [WEAK]
- EXPORT TIM20_UP_IRQHandler [WEAK]
- EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM20_CC_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_TSC_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN_TX_IRQHandler
-USB_LP_CAN_RX0_IRQHandler
-CAN_RX1_IRQHandler
-CAN_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM15_IRQHandler
-TIM1_UP_TIM16_IRQHandler
-TIM1_TRG_COM_TIM17_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-TIM8_BRK_IRQHandler
-TIM8_UP_IRQHandler
-TIM8_TRG_COM_IRQHandler
-TIM8_CC_IRQHandler
-ADC3_IRQHandler
-FMC_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-ADC4_IRQHandler
-COMP1_2_3_IRQHandler
-COMP4_5_6_IRQHandler
-COMP7_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-USBWakeUp_RMP_IRQHandler
-TIM20_BRK_IRQHandler
-TIM20_UP_IRQHandler
-TIM20_TRG_COM_IRQHandler
-TIM20_CC_IRQHandler
-FPU_IRQHandler
-SPI4_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct
deleted file mode 100644
index e861c23b2c..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct
+++ /dev/null
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-; this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-; this list of conditions and the following disclaimer in the documentation
-; and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-; may be used to endorse or promote products derived from this software
-; without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32F303RE: 512KB FLASH (0x80000) + 64KB SRAM (0x10000)
-LR_IROM1 0x08000000 0x80000 { ; load region size_region
-
- ER_IROM1 0x08000000 0x80000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ; 101 vectors = 404 bytes (0x194) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x194) (0x10000-0x194) { ; RW data
- .ANY (+RW +ZI)
- }
-
-}
-
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S
deleted file mode 100644
index 1314d2d4bd..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S
+++ /dev/null
@@ -1,380 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f303xe.s
-;* Author : MCD Application Team
-;* Version : V2.1.0
-;* Date : 12-Sept-2014
-;* Description : STM32F303xE devices vector table for MDK-ARM_STD toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*******************************************************************************
-
-__initial_sp EQU 0x20010000 ; Top of RAM
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; ADC1 and ADC2
- DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
- DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
- DCD CAN_RX1_IRQHandler ; CAN RX1
- DCD CAN_SCE_IRQHandler ; CAN SCE
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
- DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
- DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_IRQHandler ; USART3
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
- DCD TIM8_BRK_IRQHandler ; TIM8 Break
- DCD TIM8_UP_IRQHandler ; TIM8 Update
- DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
- DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
- DCD ADC3_IRQHandler ; ADC3
- DCD FMC_IRQHandler ; FMC
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI3_IRQHandler ; SPI3
- DCD UART4_IRQHandler ; UART4
- DCD UART5_IRQHandler ; UART5
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; TIM7
- DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
- DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
- DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
- DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
- DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
- DCD ADC4_IRQHandler ; ADC4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3
- DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6
- DCD COMP7_IRQHandler ; COMP7
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD I2C3_EV_IRQHandler ; I2C3 Event
- DCD I2C3_ER_IRQHandler ; I2C3 Error
- DCD USB_HP_IRQHandler ; USB High Priority remap
- DCD USB_LP_IRQHandler ; USB Low Priority remap
- DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
- DCD TIM20_BRK_IRQHandler ; TIM20 Break
- DCD TIM20_UP_IRQHandler ; TIM20 Update
- DCD TIM20_TRG_COM_IRQHandler ; TIM20 Trigger and Commutation
- DCD TIM20_CC_IRQHandler ; TIM20 Capture Compare
- DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT SystemInit
- IMPORT __main
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-MemManage_Handler\
- PROC
- EXPORT MemManage_Handler [WEAK]
- B .
- ENDP
-BusFault_Handler\
- PROC
- EXPORT BusFault_Handler [WEAK]
- B .
- ENDP
-UsageFault_Handler\
- PROC
- EXPORT UsageFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-DebugMon_Handler\
- PROC
- EXPORT DebugMon_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMP_STAMP_IRQHandler [WEAK]
- EXPORT RTC_WKUP_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_IRQHandler [WEAK]
- EXPORT EXTI1_IRQHandler [WEAK]
- EXPORT EXTI2_TSC_IRQHandler [WEAK]
- EXPORT EXTI3_IRQHandler [WEAK]
- EXPORT EXTI4_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_IRQHandler [WEAK]
- EXPORT DMA1_Channel3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_IRQHandler [WEAK]
- EXPORT DMA1_Channel5_IRQHandler [WEAK]
- EXPORT DMA1_Channel6_IRQHandler [WEAK]
- EXPORT DMA1_Channel7_IRQHandler [WEAK]
- EXPORT ADC1_2_IRQHandler [WEAK]
- EXPORT USB_HP_CAN_TX_IRQHandler [WEAK]
- EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK]
- EXPORT CAN_RX1_IRQHandler [WEAK]
- EXPORT CAN_SCE_IRQHandler [WEAK]
- EXPORT EXTI9_5_IRQHandler [WEAK]
- EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
- EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
- EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM4_IRQHandler [WEAK]
- EXPORT I2C1_EV_IRQHandler [WEAK]
- EXPORT I2C1_ER_IRQHandler [WEAK]
- EXPORT I2C2_EV_IRQHandler [WEAK]
- EXPORT I2C2_ER_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_IRQHandler [WEAK]
- EXPORT EXTI15_10_IRQHandler [WEAK]
- EXPORT RTC_Alarm_IRQHandler [WEAK]
- EXPORT USBWakeUp_IRQHandler [WEAK]
- EXPORT TIM8_BRK_IRQHandler [WEAK]
- EXPORT TIM8_UP_IRQHandler [WEAK]
- EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM8_CC_IRQHandler [WEAK]
- EXPORT ADC3_IRQHandler [WEAK]
- EXPORT FMC_IRQHandler [WEAK]
- EXPORT SPI3_IRQHandler [WEAK]
- EXPORT UART4_IRQHandler [WEAK]
- EXPORT UART5_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT DMA2_Channel1_IRQHandler [WEAK]
- EXPORT DMA2_Channel2_IRQHandler [WEAK]
- EXPORT DMA2_Channel3_IRQHandler [WEAK]
- EXPORT DMA2_Channel4_IRQHandler [WEAK]
- EXPORT DMA2_Channel5_IRQHandler [WEAK]
- EXPORT ADC4_IRQHandler [WEAK]
- EXPORT COMP1_2_3_IRQHandler [WEAK]
- EXPORT COMP4_5_6_IRQHandler [WEAK]
- EXPORT COMP7_IRQHandler [WEAK]
- EXPORT I2C3_EV_IRQHandler [WEAK]
- EXPORT I2C3_ER_IRQHandler [WEAK]
- EXPORT USB_HP_IRQHandler [WEAK]
- EXPORT USB_LP_IRQHandler [WEAK]
- EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
- EXPORT TIM20_BRK_IRQHandler [WEAK]
- EXPORT TIM20_UP_IRQHandler [WEAK]
- EXPORT TIM20_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM20_CC_IRQHandler [WEAK]
- EXPORT FPU_IRQHandler [WEAK]
- EXPORT SPI4_IRQHandler [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMP_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_TSC_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_2_IRQHandler
-USB_HP_CAN_TX_IRQHandler
-USB_LP_CAN_RX0_IRQHandler
-CAN_RX1_IRQHandler
-CAN_SCE_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_TIM15_IRQHandler
-TIM1_UP_TIM16_IRQHandler
-TIM1_TRG_COM_TIM17_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USBWakeUp_IRQHandler
-TIM8_BRK_IRQHandler
-TIM8_UP_IRQHandler
-TIM8_TRG_COM_IRQHandler
-TIM8_CC_IRQHandler
-ADC3_IRQHandler
-FMC_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-ADC4_IRQHandler
-COMP1_2_3_IRQHandler
-COMP4_5_6_IRQHandler
-COMP7_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-USBWakeUp_RMP_IRQHandler
-TIM20_BRK_IRQHandler
-TIM20_UP_IRQHandler
-TIM20_TRG_COM_IRQHandler
-TIM20_CC_IRQHandler
-FPU_IRQHandler
-SPI4_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_STD/stm32f303xe.sct b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_STD/stm32f303xe.sct
deleted file mode 100644
index e861c23b2c..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_STD/stm32f303xe.sct
+++ /dev/null
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-; this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-; this list of conditions and the following disclaimer in the documentation
-; and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-; may be used to endorse or promote products derived from this software
-; without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32F303RE: 512KB FLASH (0x80000) + 64KB SRAM (0x10000)
-LR_IROM1 0x08000000 0x80000 { ; load region size_region
-
- ER_IROM1 0x08000000 0x80000 { ; load address = execution address
- *.o (RESET, +First)
- *(InRoot$$Sections)
- .ANY (+RO)
- }
-
- ; 101 vectors = 404 bytes (0x194) to be reserved in RAM
- RW_IRAM1 (0x20000000+0x194) (0x10000-0x194) { ; RW data
- .ANY (+RW +ZI)
- }
-
-}
-
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_STD/sys.cpp
deleted file mode 100644
index bb665909b9..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_ARM_STD/sys.cpp
+++ /dev/null
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model,
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include
-#include
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
- uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
- uint32_t sp_limit = __current_sp();
-
- zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
-
- struct __initial_stackheap r;
- r.heap_base = zi_limit;
- r.heap_limit = sp_limit;
- return r;
-}
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_GCC_ARM/STM32F303XE.ld b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_GCC_ARM/STM32F303XE.ld
deleted file mode 100644
index a98a441f7d..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_GCC_ARM/STM32F303XE.ld
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
- CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 16K
- RAM (rwx) : ORIGIN = 0x20000194, LENGTH = 64K - 0x194
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- * Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- * __exidx_start
- * __exidx_end
- * __etext
- * __data_start__
- * __preinit_array_start
- * __preinit_array_end
- * __init_array_start
- * __init_array_end
- * __fini_array_start
- * __fini_array_end
- * __data_end__
- * __bss_start__
- * __bss_end__
- * __end__
- * end
- * __HeapLimit
- * __StackLimit
- * __StackTop
- * __stack
- * _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
- .text :
- {
- KEEP(*(.isr_vector))
- *(.text*)
- KEEP(*(.init))
- KEEP(*(.fini))
-
- /* .ctors */
- *crtbegin.o(.ctors)
- *crtbegin?.o(.ctors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
- *(SORT(.ctors.*))
- *(.ctors)
-
- /* .dtors */
- *crtbegin.o(.dtors)
- *crtbegin?.o(.dtors)
- *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
- *(SORT(.dtors.*))
- *(.dtors)
-
- *(.rodata*)
-
- KEEP(*(.eh_frame*))
- } > FLASH
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
-
- __exidx_start = .;
- .ARM.exidx :
- {
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
- __exidx_end = .;
-
- __etext = .;
- _sidata = .;
-
- .data : AT (__etext)
- {
- __data_start__ = .;
- _sdata = .;
- *(vtable)
- *(.data*)
-
- . = ALIGN(4);
- /* preinit data */
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
-
- . = ALIGN(4);
- /* init data */
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP(*(SORT(.init_array.*)))
- KEEP(*(.init_array))
- PROVIDE_HIDDEN (__init_array_end = .);
-
-
- . = ALIGN(4);
- /* finit data */
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP(*(SORT(.fini_array.*)))
- KEEP(*(.fini_array))
- PROVIDE_HIDDEN (__fini_array_end = .);
-
- KEEP(*(.jcr*))
- . = ALIGN(4);
- /* All data end */
- __data_end__ = .;
- _edata = .;
-
- } > RAM
-
- .bss :
- {
- . = ALIGN(4);
- __bss_start__ = .;
- _sbss = .;
- *(.bss*)
- *(COMMON)
- . = ALIGN(4);
- __bss_end__ = .;
- _ebss = .;
- } > RAM
-
- .heap (COPY):
- {
- __end__ = .;
- end = __end__;
- *(.heap*)
- __HeapLimit = .;
- } > RAM
-
- /* .stack_dummy section doesn't contains any symbols. It is only
- * used for linker to calculate size of stack sections, and assign
- * values to stack symbols later */
- .stack_dummy (COPY):
- {
- *(.stack*)
- } > RAM
-
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(RAM) + LENGTH(RAM);
- _estack = __StackTop;
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
- PROVIDE(__stack = __StackTop);
-
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}
-
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S
deleted file mode 100644
index 20412ac438..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S
+++ /dev/null
@@ -1,490 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f303xe.s
- * @author MCD Application Team
- * @version
- * @date 12-Sept-2014
- * @brief STM32F303xE devices vector table for Atollic
- * TrueSTUDIO toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address,
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M4 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2014 STMicroelectronics
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m4
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-
-.equ BootRAM, 0xF1E0F85F
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr sp, =_estack /* Atollic update: set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- //bl __libc_init_array
-/* Call the application's entry point.*/
- //bl main
-/**
- * Calling the crt0 'cold-start' entry point. There __libc_init_array is called
- * and when existing hardware_init_hook() and software_init_hook() before
- * starting main(). software_init_hook() is available and has to be called due
- * to initializsation when using rtos.
-*/
- bl _start
-
-LoopForever:
- b LoopForever
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex-M4. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word WWDG_IRQHandler
- .word PVD_IRQHandler
- .word TAMP_STAMP_IRQHandler
- .word RTC_WKUP_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_IRQHandler
- .word EXTI1_IRQHandler
- .word EXTI2_TSC_IRQHandler
- .word EXTI3_IRQHandler
- .word EXTI4_IRQHandler
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_IRQHandler
- .word DMA1_Channel3_IRQHandler
- .word DMA1_Channel4_IRQHandler
- .word DMA1_Channel5_IRQHandler
- .word DMA1_Channel6_IRQHandler
- .word DMA1_Channel7_IRQHandler
- .word ADC1_2_IRQHandler
- .word USB_HP_CAN_TX_IRQHandler
- .word USB_LP_CAN_RX0_IRQHandler
- .word CAN_RX1_IRQHandler
- .word CAN_SCE_IRQHandler
- .word EXTI9_5_IRQHandler
- .word TIM1_BRK_TIM15_IRQHandler
- .word TIM1_UP_TIM16_IRQHandler
- .word TIM1_TRG_COM_TIM17_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word TIM4_IRQHandler
- .word I2C1_EV_IRQHandler
- .word I2C1_ER_IRQHandler
- .word I2C2_EV_IRQHandler
- .word I2C2_ER_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word USART3_IRQHandler
- .word EXTI15_10_IRQHandler
- .word RTC_Alarm_IRQHandler
- .word USBWakeUp_IRQHandler
- .word TIM8_BRK_IRQHandler
- .word TIM8_UP_IRQHandler
- .word TIM8_TRG_COM_IRQHandler
- .word TIM8_CC_IRQHandler
- .word ADC3_IRQHandler
- .word FMC_IRQHandler
- .word 0
- .word 0
- .word SPI3_IRQHandler
- .word UART4_IRQHandler
- .word UART5_IRQHandler
- .word TIM6_DAC_IRQHandler
- .word TIM7_IRQHandler
- .word DMA2_Channel1_IRQHandler
- .word DMA2_Channel2_IRQHandler
- .word DMA2_Channel3_IRQHandler
- .word DMA2_Channel4_IRQHandler
- .word DMA2_Channel5_IRQHandler
- .word ADC4_IRQHandler
- .word 0
- .word 0
- .word COMP1_2_3_IRQHandler
- .word COMP4_5_6_IRQHandler
- .word COMP7_IRQHandler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word I2C3_EV_IRQHandler
- .word I2C3_ER_IRQHandler
- .word USB_HP_IRQHandler
- .word USB_LP_IRQHandler
- .word USBWakeUp_RMP_IRQHandler
- .word TIM20_BRK_IRQHandler
- .word TIM20_UP_IRQHandler
- .word TIM20_TRG_COM_IRQHandler
- .word TIM20_CC_IRQHandler
- .word FPU_IRQHandler
- .word 0
- .word 0
- .word SPI4_IRQHandler
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_TSC_IRQHandler
- .thumb_set EXTI2_TSC_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_IRQHandler
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
- .weak DMA1_Channel3_IRQHandler
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_IRQHandler
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
- .weak DMA1_Channel5_IRQHandler
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
- .weak DMA1_Channel6_IRQHandler
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
- .weak DMA1_Channel7_IRQHandler
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
- .weak ADC1_2_IRQHandler
- .thumb_set ADC1_2_IRQHandler,Default_Handler
-
- .weak USB_HP_CAN_TX_IRQHandler
- .thumb_set USB_HP_CAN_TX_IRQHandler,Default_Handler
-
- .weak USB_LP_CAN_RX0_IRQHandler
- .thumb_set USB_LP_CAN_RX0_IRQHandler,Default_Handler
-
- .weak CAN_RX1_IRQHandler
- .thumb_set CAN_RX1_IRQHandler,Default_Handler
-
- .weak CAN_SCE_IRQHandler
- .thumb_set CAN_SCE_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_TIM15_IRQHandler
- .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
-
- .weak TIM1_UP_TIM16_IRQHandler
- .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_TIM17_IRQHandler
- .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak USBWakeUp_IRQHandler
- .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
- .weak TIM8_BRK_IRQHandler
- .thumb_set TIM8_BRK_IRQHandler,Default_Handler
-
- .weak TIM8_UP_IRQHandler
- .thumb_set TIM8_UP_IRQHandler,Default_Handler
-
- .weak TIM8_TRG_COM_IRQHandler
- .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM8_CC_IRQHandler
- .thumb_set TIM8_CC_IRQHandler,Default_Handler
-
- .weak ADC3_IRQHandler
- .thumb_set ADC3_IRQHandler,Default_Handler
-
- .weak FMC_IRQHandler
- .thumb_set FMC_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak UART4_IRQHandler
- .thumb_set UART4_IRQHandler,Default_Handler
-
- .weak UART5_IRQHandler
- .thumb_set UART5_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak DMA2_Channel1_IRQHandler
- .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
- .weak DMA2_Channel2_IRQHandler
- .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
- .weak DMA2_Channel3_IRQHandler
- .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
- .weak DMA2_Channel4_IRQHandler
- .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
- .weak DMA2_Channel5_IRQHandler
- .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
- .weak ADC4_IRQHandler
- .thumb_set ADC4_IRQHandler,Default_Handler
-
- .weak COMP1_2_3_IRQHandler
- .thumb_set COMP1_2_3_IRQHandler,Default_Handler
-
- .weak COMP4_5_6_IRQHandler
- .thumb_set COMP4_5_6_IRQHandler,Default_Handler
-
- .weak COMP7_IRQHandler
- .thumb_set COMP7_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak USB_HP_IRQHandler
- .thumb_set USB_HP_IRQHandler,Default_Handler
-
- .weak USB_LP_IRQHandler
- .thumb_set USB_LP_IRQHandler,Default_Handler
-
- .weak USBWakeUp_RMP_IRQHandler
- .thumb_set USBWakeUp_RMP_IRQHandler,Default_Handler
-
- .weak TIM20_BRK_IRQHandler
- .thumb_set TIM20_BRK_IRQHandler,Default_Handler
-
- .weak TIM20_UP_IRQHandler
- .thumb_set TIM20_UP_IRQHandler,Default_Handler
-
- .weak TIM20_TRG_COM_IRQHandler
- .thumb_set TIM20_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM20_CC_IRQHandler
- .thumb_set TIM20_CC_IRQHandler,Default_Handler
-
- .weak FPU_IRQHandler
- .thumb_set FPU_IRQHandler,Default_Handler
-
- .weak SPI4_IRQHandler
- .thumb_set SPI4_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_IAR/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_IAR/startup_stm32f303xe.S
deleted file mode 100644
index e665a1bb6e..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_IAR/startup_stm32f303xe.S
+++ /dev/null
@@ -1,610 +0,0 @@
-;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f303xe.s
-;* Author : MCD Application Team
-;* Version : V2.1.0
-;* Date : 12-Sept-2014
-;* Description : STM32F303RE/STM32F303VE/STM32F303ZE devices vector table
-;* for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == _iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M4 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* © COPYRIGHT(c) 2014 STMicroelectronics
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;* 1. Redistributions of source code must retain the above copyright notice,
-;* this list of conditions and the following disclaimer.
-;* 2. Redistributions in binary form must reproduce the above copyright notice,
-;* this list of conditions and the following disclaimer in the documentation
-;* and/or other materials provided with the distribution.
-;* 3. Neither the name of STMicroelectronics nor the names of its contributors
-;* may be used to endorse or promote products derived from this software
-;* without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; 0: Window WatchDog
- DCD PVD_IRQHandler ; 1: PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; 2: Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; 3: RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; 4: FLASH
- DCD RCC_IRQHandler ; 5: RCC
- DCD EXTI0_IRQHandler ; 6: EXTI Line0
- DCD EXTI1_IRQHandler ; 7: EXTI Line1
- DCD EXTI2_TSC_IRQHandler ; 8: EXTI Line2 and Touch Sense controller
- DCD EXTI3_IRQHandler ; 9: EXTI Line3
- DCD EXTI4_IRQHandler ; 10: EXTI Line4
- DCD DMA1_Channel1_IRQHandler ; 11: DMA1 Channel 1
- DCD DMA1_Channel2_IRQHandler ; 12: DMA1 Channel 2
- DCD DMA1_Channel3_IRQHandler ; 13: DMA1 Channel 3
- DCD DMA1_Channel4_IRQHandler ; 14: DMA1 Channel 4
- DCD DMA1_Channel5_IRQHandler ; 15: DMA1 Channel 5
- DCD DMA1_Channel6_IRQHandler ; 16: DMA1 Channel 6
- DCD DMA1_Channel7_IRQHandler ; 17: DMA1 Channel 7
- DCD ADC1_2_IRQHandler ; 18: ADC1 and ADC2
- DCD USB_HP_CAN_TX_IRQHandler ; 19: USB Device High Priority or CAN TX
- DCD USB_LP_CAN_RX0_IRQHandler ; 20: USB Device Low Priority or CAN RX0
- DCD CAN_RX1_IRQHandler ; 21: CAN RX1
- DCD CAN_SCE_IRQHandler ; 22: CAN SCE
- DCD EXTI9_5_IRQHandler ; 23: External Line[9:5]s
- DCD TIM1_BRK_TIM15_IRQHandler ; 24: TIM1 Break and TIM15
- DCD TIM1_UP_TIM16_IRQHandler ; 25: TIM1 Update and TIM16
- DCD TIM1_TRG_COM_TIM17_IRQHandler ; 26: TIM1 Trigger and Commutation and TIM17
- DCD TIM1_CC_IRQHandler ; 27: TIM1 Capture Compare
- DCD TIM2_IRQHandler ; 28: TIM2
- DCD TIM3_IRQHandler ; 29: TIM3
- DCD TIM4_IRQHandler ; 30: TIM4
- DCD I2C1_EV_IRQHandler ; 31: I2C1 Event
- DCD I2C1_ER_IRQHandler ; 32: I2C1 Error
- DCD I2C2_EV_IRQHandler ; 33: I2C2 Event
- DCD I2C2_ER_IRQHandler ; 34: I2C2 Error
- DCD SPI1_IRQHandler ; 35: SPI1
- DCD SPI2_IRQHandler ; 36: SPI2
- DCD USART1_IRQHandler ; 37: USART1
- DCD USART2_IRQHandler ; 38: USART2
- DCD USART3_IRQHandler ; 39: USART3
- DCD EXTI15_10_IRQHandler ; 40: External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; 41: RTC Alarm (A and B) through EXTI Line
- DCD USBWakeUp_IRQHandler ; 42: USB Wakeup through EXTI line
- DCD TIM8_BRK_IRQHandler ; 43: TIM8 Break
- DCD TIM8_UP_IRQHandler ; 44: TIM8 Update
- DCD TIM8_TRG_COM_IRQHandler ; 45: TIM8 Trigger and Commutation
- DCD TIM8_CC_IRQHandler ; 46: TIM8 Capture Compare
- DCD ADC3_IRQHandler ; 47: ADC3
- DCD FMC_IRQHandler ; 48: FMC
- DCD 0 ; 49: Reserved
- DCD 0 ; 50: Reserved
- DCD SPI3_IRQHandler ; 51: SPI3
- DCD UART4_IRQHandler ; 52: UART4
- DCD UART5_IRQHandler ; 53: UART5
- DCD TIM6_DAC_IRQHandler ; 54: TIM6 and DAC1&2 underrun errors
- DCD TIM7_IRQHandler ; 55: TIM7
- DCD DMA2_Channel1_IRQHandler ; 56: DMA2 Channel 1
- DCD DMA2_Channel2_IRQHandler ; 57: DMA2 Channel 2
- DCD DMA2_Channel3_IRQHandler ; 58: DMA2 Channel 3
- DCD DMA2_Channel4_IRQHandler ; 59: DMA2 Channel 4
- DCD DMA2_Channel5_IRQHandler ; 60: DMA2 Channel 5
- DCD ADC4_IRQHandler ; 61: ADC4
- DCD 0 ; 62: Reserved
- DCD 0 ; 63: Reserved
- DCD COMP1_2_3_IRQHandler ; 64: COMP1, COMP2 and COMP3
- DCD COMP4_5_6_IRQHandler ; 65: COMP4, COMP5 and COMP6
- DCD COMP7_IRQHandler ; 66: COMP7
- DCD 0 ; 67: Reserved
- DCD 0 ; 68: Reserved
- DCD 0 ; 69: Reserved
- DCD 0 ; 70: Reserved
- DCD 0 ; 71: Reserved
- DCD I2C3_EV_IRQHandler ; 72: I2C3 Event
- DCD I2C3_ER_IRQHandler ; 73: I2C3 Error
- DCD USB_HP_IRQHandler ; 74: USB High Priority remap
- DCD USB_LP_IRQHandler ; 75: USB Low Priority remap
- DCD USBWakeUp_RMP_IRQHandler ; 76: USB Wakeup remap through EXTI
- DCD TIM20_BRK_IRQHandler ; 77: TIM20 Break
- DCD TIM20_UP_IRQHandler ; 78: TIM20 Update
- DCD TIM20_TRG_COM_IRQHandler ; 79: TIM20 Trigger and Commutation
- DCD TIM20_CC_IRQHandler ; 80: TIM20 Capture Compare
- DCD FPU_IRQHandler ; 81: FPU
- DCD 0 ; 82: Reserved
- DCD 0 ; 83: Reserved
- DCD SPI4_IRQHandler ; 84: SPI4
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-MemManage_Handler
- B MemManage_Handler
-
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-BusFault_Handler
- B BusFault_Handler
-
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UsageFault_Handler
- B UsageFault_Handler
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
- B DebugMon_Handler
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
- PUBWEAK TAMP_STAMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TAMP_STAMP_IRQHandler
- B TAMP_STAMP_IRQHandler
-
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
- PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_IRQHandler
- B EXTI0_IRQHandler
-
- PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_IRQHandler
- B EXTI1_IRQHandler
-
- PUBWEAK EXTI2_TSC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_TSC_IRQHandler
- B EXTI2_TSC_IRQHandler
-
- PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_IRQHandler
- B EXTI3_IRQHandler
-
- PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_IRQHandler
- B EXTI4_IRQHandler
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
- PUBWEAK DMA1_Channel2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_IRQHandler
- B DMA1_Channel2_IRQHandler
-
- PUBWEAK DMA1_Channel3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel3_IRQHandler
- B DMA1_Channel3_IRQHandler
-
- PUBWEAK DMA1_Channel4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_IRQHandler
- B DMA1_Channel4_IRQHandler
-
- PUBWEAK DMA1_Channel5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel5_IRQHandler
- B DMA1_Channel5_IRQHandler
-
- PUBWEAK DMA1_Channel6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel6_IRQHandler
- B DMA1_Channel6_IRQHandler
-
- PUBWEAK DMA1_Channel7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel7_IRQHandler
- B DMA1_Channel7_IRQHandler
-
- PUBWEAK ADC1_2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_2_IRQHandler
- B ADC1_2_IRQHandler
-
- PUBWEAK USB_HP_CAN_TX_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USB_HP_CAN_TX_IRQHandler
- B USB_HP_CAN_TX_IRQHandler
-
- PUBWEAK USB_LP_CAN_RX0_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USB_LP_CAN_RX0_IRQHandler
- B USB_LP_CAN_RX0_IRQHandler
-
- PUBWEAK CAN_RX1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CAN_RX1_IRQHandler
- B CAN_RX1_IRQHandler
-
- PUBWEAK CAN_SCE_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CAN_SCE_IRQHandler
- B CAN_SCE_IRQHandler
-
- PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI9_5_IRQHandler
- B EXTI9_5_IRQHandler
-
- PUBWEAK TIM1_BRK_TIM15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_TIM15_IRQHandler
- B TIM1_BRK_TIM15_IRQHandler
-
- PUBWEAK TIM1_UP_TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_UP_TIM16_IRQHandler
- B TIM1_UP_TIM16_IRQHandler
-
- PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_TRG_COM_TIM17_IRQHandler
- B TIM1_TRG_COM_TIM17_IRQHandler
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
- PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM4_IRQHandler
- B TIM4_IRQHandler
-
- PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_EV_IRQHandler
- B I2C1_EV_IRQHandler
-
- PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_ER_IRQHandler
- B I2C1_ER_IRQHandler
-
- PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_EV_IRQHandler
- B I2C2_EV_IRQHandler
-
- PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_ER_IRQHandler
- B I2C2_ER_IRQHandler
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- PUBWEAK USART3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART3_IRQHandler
- B USART3_IRQHandler
-
- PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_10_IRQHandler
- B EXTI15_10_IRQHandler
-
- PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_Alarm_IRQHandler
- B RTC_Alarm_IRQHandler
-
- PUBWEAK USBWakeUp_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USBWakeUp_IRQHandler
- B USBWakeUp_IRQHandler
-
- PUBWEAK TIM8_BRK_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_BRK_IRQHandler
- B TIM8_BRK_IRQHandler
-
- PUBWEAK TIM8_UP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_UP_IRQHandler
- B TIM8_UP_IRQHandler
-
- PUBWEAK TIM8_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_TRG_COM_IRQHandler
- B TIM8_TRG_COM_IRQHandler
-
- PUBWEAK TIM8_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM8_CC_IRQHandler
- B TIM8_CC_IRQHandler
-
- PUBWEAK ADC3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC3_IRQHandler
- B ADC3_IRQHandler
-
- PUBWEAK FMC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FMC_IRQHandler
- B FMC_IRQHandler
-
- PUBWEAK SPI3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI3_IRQHandler
- B SPI3_IRQHandler
-
- PUBWEAK UART4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART4_IRQHandler
- B UART4_IRQHandler
-
- PUBWEAK UART5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-UART5_IRQHandler
- B UART5_IRQHandler
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- PUBWEAK DMA2_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel1_IRQHandler
- B DMA2_Channel1_IRQHandler
-
- PUBWEAK DMA2_Channel2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel2_IRQHandler
- B DMA2_Channel2_IRQHandler
-
- PUBWEAK DMA2_Channel3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel3_IRQHandler
- B DMA2_Channel3_IRQHandler
-
- PUBWEAK DMA2_Channel4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel4_IRQHandler
- B DMA2_Channel4_IRQHandler
-
- PUBWEAK DMA2_Channel5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel5_IRQHandler
- B DMA2_Channel5_IRQHandler
-
-
- PUBWEAK ADC4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC4_IRQHandler
- B ADC4_IRQHandler
-
- PUBWEAK COMP1_2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-COMP1_2_3_IRQHandler
- B COMP1_2_3_IRQHandler
-
- PUBWEAK COMP4_5_6_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-COMP4_5_6_IRQHandler
- B COMP4_5_6_IRQHandler
-
- PUBWEAK COMP7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-COMP7_IRQHandler
- B COMP7_IRQHandler
-
- PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_EV_IRQHandler
- B I2C3_EV_IRQHandler
-
- PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_ER_IRQHandler
- B I2C3_ER_IRQHandler
-
- PUBWEAK USB_HP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USB_HP_IRQHandler
- B USB_HP_IRQHandler
-
- PUBWEAK USB_LP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USB_LP_IRQHandler
- B USB_LP_IRQHandler
-
- PUBWEAK USBWakeUp_RMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USBWakeUp_RMP_IRQHandler
- B USBWakeUp_RMP_IRQHandler
-
- PUBWEAK TIM20_BRK_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM20_BRK_IRQHandler
- B TIM20_BRK_IRQHandler
-
- PUBWEAK TIM20_UP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM20_UP_IRQHandler
- B TIM20_UP_IRQHandler
-
- PUBWEAK TIM20_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM20_TRG_COM_IRQHandler
- B TIM20_TRG_COM_IRQHandler
-
- PUBWEAK TIM20_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM20_CC_IRQHandler
- B TIM20_CC_IRQHandler
-
- PUBWEAK FPU_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FPU_IRQHandler
- B FPU_IRQHandler
-
- PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI4_IRQHandler
- B SPI4_IRQHandler
-
- END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_IAR/stm32f303xe.icf b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_IAR/stm32f303xe.icf
deleted file mode 100644
index 9b1f074c53..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/TOOLCHAIN_IAR/stm32f303xe.icf
+++ /dev/null
@@ -1,35 +0,0 @@
-/* [ROM = 512kb = 0x80000] */
-define symbol __intvec_start__ = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__ = 0x0807FFFF;
-
-define symbol __region_CCMRAM_start__ = 0x10000000;
-define symbol __region_CCMRAM_end__ = 0x10003FFF;
-
-/* [RAM = 64kb = 0x10000] Vector table dynamic copy: 101 vectors = 404 bytes (0x194) to be reserved in RAM */
-define symbol __NVIC_start__ = 0x20000000;
-define symbol __NVIC_end__ = 0x20000197; /* Add 4 more bytes to be aligned on 8 bytes */
-define symbol __region_RAM_start__ = 0x20000198;
-define symbol __region_RAM_end__ = 0x2000FFFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-define region CCMRAM_region = mem:[from __region_CCMRAM_start__ to __region_CCMRAM_end__];
-
-/* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
-define symbol __size_cstack__ = 0x2000;
-define symbol __size_heap__ = 0x4000;
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-
-place in ROM_region { readonly };
-place in RAM_region { readwrite, block STACKHEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/cmsis.h
deleted file mode 100644
index 8b9ba0fc38..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/cmsis.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* mbed Microcontroller Library
- * A generic CMSIS include header
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "stm32f3xx.h"
-#include "cmsis_nvic.h"
-
-#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/cmsis_nvic.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/cmsis_nvic.c
deleted file mode 100644
index 2da63fc9af..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/cmsis_nvic.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
- uint32_t *vectors = (uint32_t *)SCB->VTOR;
- uint32_t i;
-
- // Copy and switch to dynamic vectors if the first time called
- if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
- uint32_t *old_vectors = vectors;
- vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
- for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
- }
- vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
- uint32_t *vectors = (uint32_t*)SCB->VTOR;
- return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
-}
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/cmsis_nvic.h
deleted file mode 100644
index eb09b74d89..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/cmsis_nvic.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-// STM32F303RE
-// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
-// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to 0x193
-// Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
-#define NVIC_NUM_VECTORS 101
-#define NVIC_USER_IRQ_OFFSET 16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/hal_tick.h
deleted file mode 100644
index 18d268d133..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/hal_tick.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**
- ******************************************************************************
- * @file hal_tick.h
- * @author MCD Application Team
- * @brief Initialization of HAL tick
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2014 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#ifndef __HAL_TICK_H
-#define __HAL_TICK_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "stm32f3xx.h"
-#include "cmsis_nvic.h"
-
-#define TIM_MST TIM2
-#define TIM_MST_IRQ TIM2_IRQn
-#define TIM_MST_RCC __TIM2_CLK_ENABLE()
-
-#define TIM_MST_RESET_ON __TIM2_FORCE_RESET()
-#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET()
-
-#define TIM_MST_16BIT 0 // 1=16-bit timer, 0=32-bit timer
-
-#define TIM_MST_PCLK 1 // Select the peripheral clock number (1 or 2)
-
-#define HAL_TICK_DELAY (1000) // 1 ms
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __HAL_TICK_H
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/stm32f303xe.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/stm32f303xe.h
deleted file mode 100644
index 74a5c83f1a..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/stm32f303xe.h
+++ /dev/null
@@ -1,15245 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f303xe.h
- * @author MCD Application Team
- * @version V2.3.1
- * @date 16-December-2016
- * @brief CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
- *
- * This file contains:
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral’s registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS_Device
- * @{
- */
-
-/** @addtogroup stm32f303xe
- * @{
- */
-
-#ifndef __STM32F303xE_H
-#define __STM32F303xE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
- */
-#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
-#define __MPU_PRESENT 1U /*!< STM32F303xE devices provide an MPU */
-#define __NVIC_PRIO_BITS 4U /*!< STM32F303xE devices use 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT 1U /*!< STM32F303xE devices provide an FPU */
-#endif
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_interrupt_number_definition
- * @{
- */
-
-/**
- * @brief STM32F303xE devices Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-typedef enum
-{
-/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers **********************************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
- DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
- DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
- DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
- DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
- DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
- ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
- USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
- USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
- CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
- CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
- TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
- TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
- USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
- USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
- USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
- TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
- TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
- TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
- ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
- FMC_IRQn = 48, /*!< FMC global Interrupt */
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
- UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
- UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC underrun error Interrupt */
- TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
- DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
- DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
- DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
- DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
- DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
- ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
- COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
- COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
- COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
- I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
- USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt */
- USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt */
- USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
- TIM20_BRK_IRQn = 77, /*!< TIM20 Break Interrupt */
- TIM20_UP_IRQn = 78, /*!< TIM20 Update Interrupt */
- TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger and Commutation Interrupt */
- TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare Interrupt */
- FPU_IRQn = 81, /*!< Floating point Interrupt */
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f3xx.h" /* STM32F3xx System Header */
-#include
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
- __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
- __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
- uint32_t RESERVED0; /*!< Reserved, 0x010 */
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
- uint32_t RESERVED1; /*!< Reserved, 0x01C */
- __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
- __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
- __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
- uint32_t RESERVED2; /*!< Reserved, 0x02C */
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
- __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
- uint32_t RESERVED3; /*!< Reserved, 0x044 */
- uint32_t RESERVED4; /*!< Reserved, 0x048 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
- uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
- __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
- __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
- __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
- __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
- uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
- uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
- __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
- __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
- uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
- uint32_t RESERVED9; /*!< Reserved, 0x0AC */
- __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
- __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
-
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
- uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
- __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
- __IO uint32_t CDR; /*!< ADC common regular data register for dual
- AND triple modes, Address offset: ADC1/3 base address + 0x30C */
-} ADC_Common_TypeDef;
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-typedef struct
-{
- __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
- __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
- __IO uint32_t TDLR; /*!< CAN mailbox data low register */
- __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-typedef struct
-{
- __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
- __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
- __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
- __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-typedef struct
-{
- __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
- __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-typedef struct
-{
- __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
- __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
- __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
- __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
- __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
- __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
- __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
- uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
- CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
- uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
- __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
- __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
- uint32_t RESERVED2; /*!< Reserved, 0x208 */
- __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
- uint32_t RESERVED3; /*!< Reserved, 0x210 */
- __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
- uint32_t RESERVED4; /*!< Reserved, 0x218 */
- __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
- uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
- CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
-} CAN_TypeDef;
-
-/**
- * @brief Analog Comparators
- */
-typedef struct
-{
- __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, 0x05 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
- uint32_t RESERVED2; /*!< Reserved, 0x0C */
- __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
- __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
-} DAC_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
- __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA channel x configuration register */
- __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
- __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
- __IO uint32_t CMAR; /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
-} DMA_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR; /*!© COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f3xx
- * @{
- */
-
-#ifndef __STM32F3xx_H
-#define __STM32F3xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/**
- * @brief STM32 Family
- */
-#if !defined (STM32F3)
-#define STM32F3
-#endif /* STM32F3 */
-
-/* Uncomment the line below according to the target STM32 device used in your
- application
- */
-
-#if !defined (STM32F301x8) && !defined (STM32F302x8) && !defined (STM32F318xx) && \
- !defined (STM32F302xC) && !defined (STM32F303xC) && !defined (STM32F358xx) && \
- !defined (STM32F303x8) && !defined (STM32F334x8) && !defined (STM32F328xx) && \
- !defined (STM32F302xE) && !defined (STM32F303xE) && !defined (STM32F398xx) && \
- !defined (STM32F373xC) && !defined (STM32F378xx)
-
- /* #define STM32F301x8 */ /*!< STM32F301K6, STM32F301K8, STM32F301C6, STM32F301C8,
- STM32F301R6 and STM32F301R8 Devices */
- /* #define STM32F302x8 */ /*!< STM32F302K6, STM32F302K8, STM32F302C6, STM32F302C8,
- STM32F302R6 and STM32F302R8 Devices */
- /* #define STM32F302xC */ /*!< STM32F302CB, STM32F302CC, STM32F302RB, STM32F302RC,
- STM32F302VB and STM32F302VC Devices */
- /* #define STM32F302xE */ /*!< STM32F302RE, STM32F302VE, STM32F302ZE, STM32F302RD,
- STM32F302VD and STM32F302ZD Devices */
- /* #define STM32F303x8 */ /*!< STM32F303K6, STM32F303K8, STM32F303C6, STM32F303C8,
- STM32F303R6 and STM32F303R8 Devices */
- /* #define STM32F303xC */ /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC,
- STM32F303VB and STM32F303VC Devices */
-#define STM32F303xE /*!< STM32F303RE, STM32F303VE, STM32F303ZE, STM32F303RD,
- STM32F303VD and STM32F303ZD Devices */
- /* #define STM32F373xC */ /*!< STM32F373C8, STM32F373CB, STM32F373CC,
- STM32F373R8, STM32F373RB, STM32F373RC,
- STM32F373V8, STM32F373VB and STM32F373VC Devices */
- /* #define STM32F334x8 */ /*!< STM32F334K4, STM32F334K6, STM32F334K8,
- STM32F334C4, STM32F334C6, STM32F334C8,
- STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
- /* #define STM32F318xx */ /*!< STM32F318K8, STM32F318C8: STM32F301x8 with regulator off: STM32F318xx Devices */
- /* #define STM32F328xx */ /*!< STM32F328C8, STM32F328R8: STM32F334x8 with regulator off: STM32F328xx Devices */
- /* #define STM32F358xx */ /*!< STM32F358CC, STM32F358RC, STM32F358VC: STM32F303xC with regulator off: STM32F358xx Devices */
- /* #define STM32F378xx */ /*!< STM32F378CC, STM32F378RC, STM32F378VC: STM32F373xC with regulator off: STM32F378xx Devices */
- /* #define STM32F398xx */ /*!< STM32F398VE: STM32F303xE with regulator off: STM32F398xx Devices */
-#endif
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-#if !defined (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
- * @brief CMSIS Device version number V2.3.1
- */
-#define __STM32F3_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
-#define __STM32F3_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
-#define __STM32F3_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F3_CMSIS_VERSION ((__STM32F3_CMSIS_VERSION_MAIN << 24)\
- |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\
- |(__STM32F3_CMSIS_VERSION_SUB2 << 8 )\
- |(__STM32F3_CMSIS_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Device_Included
- * @{
- */
-
-#if defined(STM32F301x8)
- #include "stm32f301x8.h"
-#elif defined(STM32F302x8)
- #include "stm32f302x8.h"
-#elif defined(STM32F302xC)
- #include "stm32f302xc.h"
-#elif defined(STM32F302xE)
- #include "stm32f302xe.h"
-#elif defined(STM32F303x8)
- #include "stm32f303x8.h"
-#elif defined(STM32F303xC)
- #include "stm32f303xc.h"
-#elif defined(STM32F303xE)
- #include "stm32f303xe.h"
-#elif defined(STM32F373xC)
- #include "stm32f373xc.h"
-#elif defined(STM32F334x8)
- #include "stm32f334x8.h"
-#elif defined(STM32F318xx)
- #include "stm32f318xx.h"
-#elif defined(STM32F328xx)
- #include "stm32f328xx.h"
-#elif defined(STM32F358xx)
- #include "stm32f358xx.h"
-#elif defined(STM32F378xx)
- #include "stm32f378xx.h"
-#elif defined(STM32F398xx)
- #include "stm32f398xx.h"
-#else
- #error "Please select first the target STM32F3xx device used in your application (in stm32f3xx.h file)"
-#endif
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_types
- * @{
- */
-typedef enum
-{
- RESET = 0,
- SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum
-{
- DISABLE = 0,
- ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum
-{
- ERROR = 0,
- SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
- * @}
- */
-
-
-/** @addtogroup Exported_macros
- * @{
- */
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
-#define CLEAR_REG(REG) ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))
-
-#define READ_REG(REG) ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
-
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32f3xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F3xx_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.c
deleted file mode 100644
index 5b19e2b186..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.c
+++ /dev/null
@@ -1,459 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f3xx.c
- * @author MCD Application Team
- * @version V2.3.1
- * @date 16-December-2016
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f3xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. This file configures the system clock as follows:
- *-----------------------------------------------------------------------------
- * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
- * | (external 8 MHz clock) | (internal 8 MHz)
- * | 2- PLL_HSE_XTAL |
- * | (external 8 MHz xtal) |
- *-----------------------------------------------------------------------------
- * SYSCLK(MHz) | 72 | 64
- *-----------------------------------------------------------------------------
- * AHBCLK (MHz) | 72 | 64
- *-----------------------------------------------------------------------------
- * APB1CLK (MHz) | 36 | 32
- *-----------------------------------------------------------------------------
- * APB2CLK (MHz) | 72 | 64
- *-----------------------------------------------------------------------------
- * USB capable (48 MHz precise clock) | NO | NO
- *-----------------------------------------------------------------------------
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f3xx_system
- * @{
- */
-
-/** @addtogroup STM32F3xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f3xx.h"
-#include "hal_tick.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Defines
- * @{
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Macros
- * @{
- */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock there is no need to
- call the 2 first functions listed above, since SystemCoreClock variable is
- updated automatically.
- */
-uint32_t SystemCoreClock = 72000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
- * @{
- */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting, vector table location and the PLL configuration is reset.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
-
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= 0x00000001U;
-
- /* Reset CFGR register */
- RCC->CFGR &= 0xF87FC00CU;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= 0xFEF6FFFFU;
-
- /* Reset HSEBYP bit */
- RCC->CR &= 0xFFFBFFFFU;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
- RCC->CFGR &= 0xFF80FFFFU;
-
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= 0xFFFFFFF0U;
-
- /* Reset USARTSW[1:0], I2CSW and TIMs bits */
- RCC->CFGR3 &= 0xFF00FCCCU;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000U;
-
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
- /* Configure the Cube driver */
- SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
- HAL_Init();
-
- /* Configure the System clock source, PLL Multiplier and Divider factors,
- AHB/APBx prescalers and Flash settings */
- SetSysClock();
-
- /* Reset the timer to avoid issues after the RAM initialization */
- TIM_MST_RESET_ON;
- TIM_MST_RESET_OFF;
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- {
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
- }
- else
- {
- /* HSI oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
- }
-#else
- if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
- }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock source, PLL Multiplier and Divider factors,
- * AHB/APBx prescalers and Flash settings
- * @note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
-void SetSysClock(void)
-{
- /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
- if (SetSysClock_PLL_HSE(1) == 0)
-#endif
- {
- /* 2- If fail try to start with HSE and external xtal */
- #if USE_PLL_HSE_XTAL != 0
- if (SetSysClock_PLL_HSE(0) == 0)
- #endif
- {
- /* 3- If fail start with HSI clock */
- if (SetSysClock_PLL_HSI() == 0)
- {
- while(1)
- {
- // [TODO] Put something here to tell the user that a problem occured...
- }
- }
- }
- }
-
- /* Output clock on MCO1 pin(PA8) for debugging purpose */
- //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/* PLL (clocked by HSE) used as System clock source */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
-
- /* Enable HSE oscillator and activate PLL with HSE as source */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
- if (bypass == 0)
- {
- RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
- }
- else
- {
- RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
- }
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
- RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
- RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- {
- return 0; // FAIL
- }
-
- /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
- RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
- {
- return 0; // FAIL
- }
-
- /* Output clock on MCO1 pin(PA8) for debugging purpose */
- //if (bypass == 0)
- // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
- //else
- // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
-
- return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/* PLL (clocked by HSI) used as System clock source */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
- RCC_ClkInitTypeDef RCC_ClkInitStruct;
- RCC_OscInitTypeDef RCC_OscInitStruct;
-
- /* Enable HSI oscillator and activate PLL with HSI as source */
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
- RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
- RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
- RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
- if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- {
- return 0; // FAIL
- }
-
- /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
- RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
- RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
- RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
- RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
- if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
- {
- return 0; // FAIL
- }
-
- /* Output clock on MCO1 pin(PA8) for debugging purpose */
- //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
-
- return 1; // OK
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.h
deleted file mode 100644
index d124c3a69f..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/device/system_stm32f3xx.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f3xx.h
- * @author MCD Application Team
- * @version V2.3.1
- * @date 16-December-2016
- * @brief CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT(c) 2016 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f3xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32F3XX_H
-#define __SYSTEM_STM32F3XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F3xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F3xx_System_Exported_types
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 3) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) by calling HAL API function HAL_RCC_ClockConfig()
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
-extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F3XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h
deleted file mode 100644
index 39afece523..0000000000
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/objects.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
- IRQn_Type irq_n;
- uint32_t irq_index;
- uint32_t event;
- PinName pin;
-};
-
-struct port_s {
- PortName port;
- uint32_t mask;
- PinDirection direction;
- __IO uint32_t *reg_in;
- __IO uint32_t *reg_out;
-};
-
-struct analogin_s {
- ADCName adc;
- PinName pin;
- uint32_t channel;
-};
-
-struct dac_s {
- DACName dac;
- PinName pin;
- uint32_t channel;
-};
-
-struct can_s {
- CANName can;
- int index;
-};
-
-#include "common_objects.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralNames.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralPins.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PeripheralPins.c
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PeripheralPins.c
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/PinNames.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303RE/PinNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralNames.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralPins.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PeripheralPins.c
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PeripheralPins.c
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PinNames.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303ZE/PinNames.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/TARGET_NUCLEO_F303ZE/PinNames.h
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_MICRO/stm32f303xe.sct
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_ARM_STD/stm32f303xe.sct b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_STD/stm32f303xe.sct
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_ARM_STD/stm32f303xe.sct
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_STD/stm32f303xe.sct
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_STD/sys.cpp
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_ARM_STD/sys.cpp
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_STD/sys.cpp
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_GCC_ARM/STM32F303XE.ld b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_GCC_ARM/STM32F303XE.ld
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_GCC_ARM/STM32F303XE.ld
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_GCC_ARM/STM32F303XE.ld
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_IAR/startup_stm32f303xe.S b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_IAR/startup_stm32f303xe.S
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_IAR/startup_stm32f303xe.S
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_IAR/startup_stm32f303xe.S
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_IAR/stm32f303xe.icf b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_IAR/stm32f303xe.icf
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/TOOLCHAIN_IAR/stm32f303xe.icf
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_IAR/stm32f303xe.icf
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/cmsis.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/cmsis.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/cmsis.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/cmsis.h
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/cmsis_nvic.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/cmsis_nvic.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/cmsis_nvic.c
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/cmsis_nvic.c
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/cmsis_nvic.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/cmsis_nvic.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/cmsis_nvic.h
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/hal_tick.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/stm32f303xe.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/stm32f303xe.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/stm32f303xe.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/stm32f303xe.h
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/stm32f3xx.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/stm32f3xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/stm32f3xx.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/stm32f3xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/system_stm32f3xx.c b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/system_stm32f3xx.c
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/system_stm32f3xx.c
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/system_stm32f3xx.c
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/system_stm32f3xx.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/system_stm32f3xx.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/device/system_stm32f3xx.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/system_stm32f3xx.h
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h
similarity index 100%
rename from targets/TARGET_STM/TARGET_STM32F3/TARGET_NUCLEO_F303RE/objects.h
rename to targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/objects.h
diff --git a/targets/targets.json b/targets/targets.json
index c6c453a304..0c83b031a5 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -774,7 +774,7 @@
"supported_form_factors": ["ARDUINO", "MORPHO"],
"core": "Cortex-M4F",
"default_toolchain": "ARM",
- "extra_labels": ["STM", "STM32F3", "STM32F303RE"],
+ "extra_labels": ["STM", "STM32F3", "STM32F303xE", "STM32F303RE"],
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"inherits": ["Target"],
"detect_code": ["0745"],
@@ -787,7 +787,7 @@
"supported_form_factors": ["ARDUINO", "MORPHO"],
"core": "Cortex-M4F",
"default_toolchain": "ARM",
- "extra_labels": ["STM", "STM32F3", "STM32F303ZE"],
+ "extra_labels": ["STM", "STM32F3", "STM32F303xE", "STM32F303ZE"],
"supported_toolchains": ["ARM", "uARM", "IAR", "GCC_ARM"],
"inherits": ["Target"],
"detect_code": ["0747"],