ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #5032 from 0xc0170/fix_mts_debug 

mts targets: fix debug() usage
pull/5205/merge
Jimmy Brisson 2017-09-27 09:07:53 -05:00 committed by GitHub
parent 908a05b231 52f84810a7
commit c24fed135b
4 changed files with 10 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c
View File

@ -35,6 +35,7 @@
**/ **/
#include "stm32f4xx.h" #include "stm32f4xx.h"
#include "mbed_debug.h"
/*!< Uncomment the following line if you need to relocate your vector Table in /*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */ Internal SRAM. */
@ -240,8 +241,6 @@ uint8_t SetSysClock_PLL_HSI(void)
/******************************************************************************/ /******************************************************************************/
void HardFault_Handler(void) void HardFault_Handler(void)
{ {
#if !defined(NDEBUG) || NDEBUG == 0 debug("Hard Fault\n");
printf("Hard Fault\n");
#endif
NVIC_SystemReset(); NVIC_SystemReset();
} }

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c
View File

@ -35,7 +35,7 @@
**/ **/
#include "stm32f4xx.h" #include "stm32f4xx.h"
#include "mbed_debug.h"
/*!< Uncomment the following line if you need to relocate your vector Table in /*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */ Internal SRAM. */
@ -243,8 +243,6 @@ uint8_t SetSysClock_PLL_HSI(void)
/******************************************************************************/ /******************************************************************************/
void HardFault_Handler(void) void HardFault_Handler(void)
{ {
#if !defined(NDEBUG) || NDEBUG == 0 debug("Hard Fault\n");
printf("Hard Fault\n");
#endif
NVIC_SystemReset(); NVIC_SystemReset();
} }

5
targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c
View File

@ -37,6 +37,7 @@
#include "stm32l1xx.h" #include "stm32l1xx.h"
#include "stdio.h" #include "stdio.h"
#include "mbed_debug.h"
/*!< Uncomment the following line if you need to relocate your vector Table in /*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */ Internal SRAM. */
@ -253,9 +254,7 @@ uint8_t SetSysClock_PLL_HSI(void)
/******************************************************************************/ /******************************************************************************/
void HardFault_Handler(void) void HardFault_Handler(void)
{ {
#if !defined(NDEBUG) || NDEBUG == 0 debug("Hard Fault\n");
printf("Hard Fault\n");
#endif
NVIC_SystemReset(); NVIC_SystemReset();
} }

13
targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/xdot_low_power.c
View File

@ -30,12 +30,7 @@
#include "xdot_low_power.h" #include "xdot_low_power.h"
#include "stdio.h" #include "stdio.h"
#include "mbed_debug.h"
#if defined(NDEBUG) && NDEBUG == 1
#define xdot_lp_debug(...) do {} while(0)
#else
#define xdot_lp_debug(...) printf(__VA_ARGS__)
#endif
static uint32_t portA[6]; static uint32_t portA[6];
static uint32_t portB[6]; static uint32_t portB[6];
@ -236,7 +231,7 @@ void xdot_enter_stop_mode() {
HSERCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; HSERCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
HSERCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3; HSERCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
if (HAL_RCC_OscConfig(&HSERCC_OscInitStruct) != HAL_OK) { if (HAL_RCC_OscConfig(&HSERCC_OscInitStruct) != HAL_OK) {
xdot_lp_debug("OSC initialization failed - initiating soft reset\r\n"); debug("OSC initialization failed - initiating soft reset\r\n");
NVIC_SystemReset(); NVIC_SystemReset();
} }
@ -247,7 +242,7 @@ void xdot_enter_stop_mode() {
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
xdot_lp_debug("PLL initialization failed - initiating soft reset\r\n"); debug("PLL initialization failed - initiating soft reset\r\n");
NVIC_SystemReset(); NVIC_SystemReset();
} }
@ -260,7 +255,7 @@ void xdot_enter_stop_mode() {
HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; HSIRCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct); HAL_StatusTypeDef ret = HAL_RCC_OscConfig(&HSIRCC_OscInitStruct);
if ( ret != HAL_OK ) { if ( ret != HAL_OK ) {
xdot_lp_debug("HSI initialization failed - ADC will not function properly\r\n"); debug("HSI initialization failed - ADC will not function properly\r\n");
} }
} }