diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct new file mode 100644 index 0000000000..310aa82197 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/LPC824.sct @@ -0,0 +1,14 @@ + +LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k) + ER_IROM1 0x00000000 0x8000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 + ; 8KB - 0xC0 = 0x1F40 + RW_IRAM1 0x10000000+0xC0 0x2000-0xC0 { + .ANY (+RW +ZI) + } +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s new file mode 100644 index 0000000000..a90d8d290e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.s @@ -0,0 +1,218 @@ +;/***************************************************************************** +; * @file: startup_LPC8xx.s +; * @purpose: CMSIS Cortex-M0+ Core Device Startup File +; * for the NXP LPC8xx Device Series +; * @version: V1.0 +; * @date: 16. Aug. 2012 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +__initial_sp EQU 0x10002000 + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD SPI0_IRQHandler ; SPI0 controller + DCD SPI1_IRQHandler ; SPI1 controller + DCD 0 ; Reserved + DCD UART0_IRQHandler ; UART0 + DCD UART1_IRQHandler ; UART1 + DCD UART2_IRQHandler ; UART2 + DCD 0 ; Reserved + DCD I2C1_IRQHandler ; I2C1 controller + DCD I2C0_IRQHandler ; I2C0 controller + DCD SCT_IRQHandler ; Smart Counter Timer + DCD MRT_IRQHandler ; Multi-Rate Timer + DCD CMP_IRQHandler ; Comparator + DCD WDT_IRQHandler ; PIO1 (0:11) + DCD BOD_IRQHandler ; Brown Out Detect + DCD Flash_IRQHandler ; Flash interrupt + DCD WKT_IRQHandler ; Wakeup timer + DCD ADC_SEQA_IRQHandler ; ADC sequence A completion + DCD ADC_SEQB_IRQHandler ; ADC sequence B completion + DCD ADC_THCMP_IRQHandler ; ADC threshold compare + DCD ADC_OVR_IRQHandler ; ADC overrun + DCD DMA__RQHandler ; DMA interrupt + DCD I2C2_IRQHandler ; I2C2 controller + DCD I2C3_IRQHandler ; I2C3 controller + DCD 0 ; Reserved + DCD PININT0_IRQHandler ; PIO INT0 + DCD PININT1_IRQHandler ; PIO INT1 + DCD PININT2_IRQHandler ; PIO INT2 + DCD PININT3_IRQHandler ; PIO INT3 + DCD PININT4_IRQHandler ; PIO INT4 + DCD PININT5_IRQHandler ; PIO INT5 + DCD PININT6_IRQHandler ; PIO INT6 + DCD PININT7_IRQHandler ; PIO INT7 + + + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY +CRP_Key DCD 0xFFFFFFFF + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT NMI_Handler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT SCT_IRQHandler [WEAK] + EXPORT MRT_IRQHandler [WEAK] + EXPORT CMP_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT BOD_IRQHandler [WEAK] + EXPORT Flash_IRQHandler [WEAK] + EXPORT WKT_IRQHandler [WEAK] + EXPORT ADC_SEQA_IRQHandler [WEAK] + EXPORT ADC_SEQB_IRQHandler [WEAK] + EXPORT ADC_THCMP_IRQHandler [WEAK] + EXPORT ADC_OVR_IRQHandler [WEAK] + EXPORT DMA__RQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT I2C3_IRQHandler [WEAK] + EXPORT PININT0_IRQHandler [WEAK] + EXPORT PININT1_IRQHandler [WEAK] + EXPORT PININT2_IRQHandler [WEAK] + EXPORT PININT3_IRQHandler [WEAK] + EXPORT PININT4_IRQHandler [WEAK] + EXPORT PININT5_IRQHandler [WEAK] + EXPORT PININT6_IRQHandler [WEAK] + EXPORT PININT7_IRQHandler [WEAK] + +NMI_Handler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +I2C1_IRQHandler +I2C0_IRQHandler +SCT_IRQHandler +MRT_IRQHandler +CMP_IRQHandler +WDT_IRQHandler +BOD_IRQHandler +Flash_IRQHandler +WKT_IRQHandler +ADC_SEQA_IRQHandler +ADC_SEQB_IRQHandler +ADC_THCMP_IRQHandler +ADC_OVR_IRQHandler +DMA__RQHandler +I2C2_IRQHandler +I2C3_IRQHandler +PININT0_IRQHandler +PININT1_IRQHandler +PININT2_IRQHandler +PININT3_IRQHandler +PININT4_IRQHandler +PININT5_IRQHandler +PININT6_IRQHandler +PININT7_IRQHandler + + B . + + ENDP + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c new file mode 100644 index 0000000000..4050de7144 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/system_LPC8xx.c @@ -0,0 +1,389 @@ +/****************************************************************************** + * @file: system_LPC8xx.c + * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File + * for the NXP LPC8xx Device Series + * @version: V1.0 + * @date: 16. Aug. 2012 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#include +#include "LPC82x.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Clock Configuration ----------------------------------*/ +// +// Clock Configuration +#define CLOCK_SETUP 1 +// System Oscillator Control Register (SYSOSCCTRL) +// BYPASS: System Oscillator Bypass Enable +// If enabled then PLL input (sys_osc_clk) is fed +// directly from XTALIN and XTALOUT pins. +// FREQRANGE: System Oscillator Frequency Range +// Determines frequency range for Low-power oscillator. +// <0=> 1 - 20 MHz +// <1=> 15 - 25 MHz +// +#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 +// +// Watchdog Oscillator Control Register (WDTOSCCTRL) +// DIVSEL: Select Divider for Fclkana +// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) +// <0-31> +// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) +// <0=> Undefined +// <1=> 0.6 MHz +// <2=> 1.05 MHz +// <3=> 1.4 MHz +// <4=> 1.75 MHz +// <5=> 2.1 MHz +// <6=> 2.4 MHz +// <7=> 2.7 MHz +// <8=> 3.0 MHz +// <9=> 3.25 MHz +// <10=> 3.5 MHz +// <11=> 3.75 MHz +// <12=> 4.0 MHz +// <13=> 4.2 MHz +// <14=> 4.4 MHz +// <15=> 4.6 MHz +#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 +// +// System PLL Control Register (SYSPLLCTRL) +// F_clkout = M * F_clkin = F_CCO / (2 * P) +// F_clkin must be in the range of 10 MHz to 25 MHz +// F_CCO must be in the range of 156 MHz to 320 MHz +// MSEL: Feedback Divider Selection +// M = MSEL + 1 +// <0-31> +// PSEL: Post Divider Selection +// <0=> P = 1 +// <1=> P = 2 +// <2=> P = 4 +// <3=> P = 8 +// +#define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000 +// +// System PLL Clock Source Select Register (SYSPLLCLKSEL) +// SEL: System PLL Clock Source +// <0=> IRC +// <1=> Crystal Oscillator +// <2=> Reserved +// <3=> CLKIN. External clock input. +// +#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 +// +// Main Clock Source Select Register (MAINCLKSEL) +// SEL: Clock Source for Main Clock +// <0=> IRC Oscillator +// <1=> PLL input +// <2=> Watchdog Oscillator +// <3=> PLL output +// +#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 +// System AHB Clock Divider Register (SYSAHBCLKDIV) +// DIV: System AHB Clock Divider +// Divides main clock to provide system clock to core, memories, and peripherals. +// 0 = is disabled +// <0-255> +// +#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 +// + +//#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal: + +/* +#if (CLOCK_SETUP == 0) + #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 + #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000 + #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 + #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000 + #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000 + #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 +#elif (CLOCK_SETUP == 2) +// #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 + #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 + #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000 + #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 + #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 + #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 +#endif +*/ + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Clock Configuration -------------------------------------------------------*/ +#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) + #error "SYSOSCCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) + #error "WDTOSCCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) + #error "SYSPLLCLKSEL: Value out of range!" +#endif + +#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) + #error "SYSPLLCTRL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) + #error "MAINCLKSEL: Invalid values of reserved bits!" +#endif + +#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) + #error "SYSAHBCLKDIV: Value out of range!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define __XTAL (12000000UL) /* Oscillator frequency */ +#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ +#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ +#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */ + + +#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) +#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) + +#if (CLOCK_SETUP) /* Clock Setup */ + #if (__FREQSEL == 0) + #define __WDT_OSC_CLK ( 0) /* undefined */ + #elif (__FREQSEL == 1) + #define __WDT_OSC_CLK ( 500000 / __DIVSEL) + #elif (__FREQSEL == 2) + #define __WDT_OSC_CLK ( 800000 / __DIVSEL) + #elif (__FREQSEL == 3) + #define __WDT_OSC_CLK (1100000 / __DIVSEL) + #elif (__FREQSEL == 4) + #define __WDT_OSC_CLK (1400000 / __DIVSEL) + #elif (__FREQSEL == 5) + #define __WDT_OSC_CLK (1600000 / __DIVSEL) + #elif (__FREQSEL == 6) + #define __WDT_OSC_CLK (1800000 / __DIVSEL) + #elif (__FREQSEL == 7) + #define __WDT_OSC_CLK (2000000 / __DIVSEL) + #elif (__FREQSEL == 8) + #define __WDT_OSC_CLK (2200000 / __DIVSEL) + #elif (__FREQSEL == 9) + #define __WDT_OSC_CLK (2400000 / __DIVSEL) + #elif (__FREQSEL == 10) + #define __WDT_OSC_CLK (2600000 / __DIVSEL) + #elif (__FREQSEL == 11) + #define __WDT_OSC_CLK (2700000 / __DIVSEL) + #elif (__FREQSEL == 12) + #define __WDT_OSC_CLK (2900000 / __DIVSEL) + #elif (__FREQSEL == 13) + #define __WDT_OSC_CLK (3100000 / __DIVSEL) + #elif (__FREQSEL == 14) + #define __WDT_OSC_CLK (3200000 / __DIVSEL) + #else + #define __WDT_OSC_CLK (3400000 / __DIVSEL) + #endif + + /* sys_pllclkin calculation */ + #if ((SYSPLLCLKSEL_Val & 0x03) == 0) + #define __SYS_PLLCLKIN (__IRC_OSC_CLK) + #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) + #define __SYS_PLLCLKIN (__SYS_OSC_CLK) + #elif ((SYSPLLCLKSEL_Val & 0x03) == 3) + #define __SYS_PLLCLKIN (__CLKIN_CLK) + #else + #define __SYS_PLLCLKIN (0) + #endif + + #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) + + /* main clock calculation */ + #if ((MAINCLKSEL_Val & 0x03) == 0) + #define __MAIN_CLOCK (__IRC_OSC_CLK) + #elif ((MAINCLKSEL_Val & 0x03) == 1) + #define __MAIN_CLOCK (__SYS_PLLCLKIN) + #elif ((MAINCLKSEL_Val & 0x03) == 2) + #if (__FREQSEL == 0) + #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" + #else + #define __MAIN_CLOCK (__WDT_OSC_CLK) + #endif + #elif ((MAINCLKSEL_Val & 0x03) == 3) + #define __MAIN_CLOCK (__SYS_PLLCLKOUT) + #else + #define __MAIN_CLOCK (0) + #endif + + #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) + +#else + #define __SYSTEM_CLOCK (__IRC_OSC_CLK) +#endif // CLOCK_SETUP + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ +uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + uint32_t wdt_osc = 0; + + /* Determine clock frequency according to clock register values */ + switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { + case 0: wdt_osc = 0; break; + case 1: wdt_osc = 500000; break; + case 2: wdt_osc = 800000; break; + case 3: wdt_osc = 1100000; break; + case 4: wdt_osc = 1400000; break; + case 5: wdt_osc = 1600000; break; + case 6: wdt_osc = 1800000; break; + case 7: wdt_osc = 2000000; break; + case 8: wdt_osc = 2200000; break; + case 9: wdt_osc = 2400000; break; + case 10: wdt_osc = 2600000; break; + case 11: wdt_osc = 2700000; break; + case 12: wdt_osc = 2900000; break; + case 13: wdt_osc = 3100000; break; + case 14: wdt_osc = 3200000; break; + case 15: wdt_osc = 3400000; break; + } + wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; + + switch (LPC_SYSCON->MAINCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK; + break; + case 1: /* Input Clock to System PLL */ + switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK; + break; + case 1: /* System oscillator */ + SystemCoreClock = __SYS_OSC_CLK; + break; + case 2: /* Reserved */ + SystemCoreClock = 0; + break; + case 3: /* CLKIN pin */ + SystemCoreClock = __CLKIN_CLK; + break; + } + break; + case 2: /* WDT Oscillator */ + SystemCoreClock = wdt_osc; + break; + case 3: /* System PLL Clock Out */ + switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { + case 0: /* Internal RC oscillator */ + SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + break; + case 1: /* System oscillator */ + SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + break; + case 2: /* Reserved */ + SystemCoreClock = 0; + break; + case 3: /* CLKIN pin */ + SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); + break; + } + break; + } + + SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) { + volatile uint32_t i; + + /* System clock to the IOCON & the SWM need to be enabled or + most of the I/O related peripherals won't work. */ + LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) ); + +#if (CLOCK_SETUP) /* Clock Setup */ + +#if ((SYSPLLCLKSEL_Val & 0x03) == 1) + LPC_IOCON->PIO0_8 &= ~(0x3 << 3); + LPC_IOCON->PIO0_9 &= ~(0x3 << 3); + LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */ + LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */ + for (i = 0; i < 200; i++) __NOP(); + LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; +#endif + +#if ((SYSPLLCLKSEL_Val & 0x03) == 3) + LPC_IOCON->PIO0_1 &= ~(0x3 << 3); + LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */ + for (i = 0; i < 200; i++) __NOP(); +#endif + + LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */ + LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ + LPC_SYSCON->SYSPLLCLKUEN = 0; + LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */ + while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ + +#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ + LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; + LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */ + while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ +#endif + +#if (((MAINCLKSEL_Val & 0x03) == 2) ) + LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; + LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */ + for (i = 0; i < 200; i++) __NOP(); +#endif + + LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ + LPC_SYSCON->MAINCLKUEN = 0; + LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */ + while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ + + LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; +#endif +} diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h new file mode 100644 index 0000000000..2d39ea9959 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h @@ -0,0 +1,55 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Default peripherals + +// SPI: MOSI, MISO, CLK, SEL +#define MBED_SPI0 P0_26, P0_25, P0_24, P0_15 + +#define MBED_UART0 P0_7, P0_18 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C0 P0_10, P0_11 + +typedef enum { + ADC_0 = 0, + ADC_1, + ADC_2, + ADC_3, + ADC_4, + ADC_5, + ADC_6, + ADC_7, + ADC_8, + ADC_9, + ADC_10, + ADC_11, +} ADCName; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h new file mode 100644 index 0000000000..373c472927 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h @@ -0,0 +1,135 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PIN_SHIFT 8 + +typedef enum { +// LPC824 Pin Names (PIN[11:8] + IOCON offset[7:0]) + + P0_0 = ( 0 << PIN_SHIFT) | 0x44, + P0_1 = ( 1 << PIN_SHIFT) | 0x2C, + P0_2 = ( 2 << PIN_SHIFT) | 0x18, + P0_3 = ( 3 << PIN_SHIFT) | 0x14, + P0_4 = ( 4 << PIN_SHIFT) | 0x10, + P0_5 = ( 5 << PIN_SHIFT) | 0x0C, + P0_6 = ( 6 << PIN_SHIFT) | 0x40, + P0_7 = ( 7 << PIN_SHIFT) | 0x3C, + P0_8 = ( 8 << PIN_SHIFT) | 0x38, + P0_9 = ( 9 << PIN_SHIFT) | 0x34, + P0_10 = (10 << PIN_SHIFT) | 0x20, + P0_11 = (11 << PIN_SHIFT) | 0x1C, + P0_12 = (12 << PIN_SHIFT) | 0x08, + P0_13 = (13 << PIN_SHIFT) | 0x04, + P0_14 = (14 << PIN_SHIFT) | 0x48, + P0_15 = (15 << PIN_SHIFT) | 0x28, + P0_16 = (16 << PIN_SHIFT) | 0x24, + P0_17 = (17 << PIN_SHIFT) | 0x00, + P0_18 = (18 << PIN_SHIFT) | 0x78, + P0_19 = (19 << PIN_SHIFT) | 0x74, + P0_20 = (20 << PIN_SHIFT) | 0x70, + P0_21 = (21 << PIN_SHIFT) | 0x6C, + P0_22 = (22 << PIN_SHIFT) | 0x68, + P0_23 = (23 << PIN_SHIFT) | 0x64, + P0_24 = (24 << PIN_SHIFT) | 0x60, + P0_25 = (25 << PIN_SHIFT) | 0x5C, + P0_26 = (26 << PIN_SHIFT) | 0x58, + P0_27 = (27 << PIN_SHIFT) | 0x54, + P0_28 = (28 << PIN_SHIFT) | 0x50, + + dp2 = P0_4, + dp3 = P0_28, + dp4 = P0_11, + dp5 = P0_10, + dp6 = P0_16, + dp7 = P0_27, + dp8 = P0_26, + dp9 = P0_25, + dp10 = P0_24, + dp11 = P0_15, + dp12 = P0_1, + + dp15 = P0_6, + dp16 = P0_0, + dp17 = P0_14, + dp18 = P0_23, + dp19 = P0_22, + dp20 = P0_21, + dp21 = P0_20, + dp22 = P0_19, + dp23 = P0_17, + dp24 = P0_13, + dp25 = P0_12, + dp26 = P0_5, + + LED_RED = P0_20, + LED_GREEN = P0_21, + LED_BLUE = P0_22, + + // mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + LED4 = LED_BLUE, + + // Serial to USB pins + USBTX = P0_7, + USBRX = P0_18, + + // I2C pins + SDA = P0_10, + SCL = P0_11, + I2C_SDA = P0_10, + I2C_SCL = P0_11, + + // Not connected + NC = (int)0xFFFFFFFF, +} PinName; + +typedef enum { + PullUp = 2, + PullDown = 1, + PullNone = 0, + Repeater = 3, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + +typedef struct { + unsigned char n; + unsigned char offset; +} SWM_Map; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h new file mode 100644 index 0000000000..be5981dc85 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 0 +#define DEVICE_PORTOUT 0 +#define DEVICE_PORTINOUT 0 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 0 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 0 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 + +#define DEVICE_SLEEP 1 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_RED 1 + +#include "objects.h" + +#endif diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index f154edb189..5ed158bbc3 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -34,6 +34,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('LPC2368', ('ARM',)), ('LPC812', ('uARM',)), ('LPC824', ('uARM',)), + ('SSCI824', ('uARM',)), ('LPC1347', ('ARM',)), ('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR')), ('LPC1114', ('uARM','GCC_ARM')), diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 4a2e56d0fe..3dccf532c8 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -208,6 +208,14 @@ class LPC824(LPCTarget): self.supported_form_factors = ["ARDUINO"] self.is_disk_virtual = True +class SSCI824(LPCTarget): + def __init__(self): + LPCTarget.__init__(self) + self.core = "Cortex-M0+" + self.extra_labels = ['NXP', 'LPC82X'] + self.supported_toolchains = ["uARM"] + self.default_toolchain = "uARM" + self.is_disk_virtual = True class LPC4088(LPCTarget): def __init__(self): @@ -736,6 +744,7 @@ TARGETS = [ LPC812(), LPC810(), LPC824(), + SSCI824(), LPC4088(), LPC4330_M4(), LPC4337(),