diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/samd21g18a.ld b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/samd21g18a.ld index 218f7deedc..d80cded0c3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/samd21g18a.ld +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/samd21g18a.ld @@ -3,19 +3,17 @@ OUTPUT_ARCH(arm) SEARCH_DIR(.) /* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 -} +MEMORY { + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 + } -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + /* The stack size used by the application. NOTE: you need to adjust according to your application. */ + STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; -/* Section Definitions */ -SECTIONS -{ - .text : + /* Section Definitions */ + SECTIONS { +.text : { . = ALIGN(4); _sfixed = .; @@ -66,23 +64,24 @@ SECTIONS /* .ARM.exidx is sorted, so has to go in its own output section. */ PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : +.ARM.exidx : { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > rom PROVIDE_HIDDEN (__exidx_end = .); . = ALIGN(4); _etext = .; - - .dvectors (NOLOAD) : - { - _sdvectors = .; - . = . + 0xB0; - _edvectors = .; - } > ram - .relocate : AT (_etext) + .dvectors (NOLOAD) : + { + _sdvectors = .; + . = . + 0xB0; + _edvectors = .; + } > ram + +.relocate : + AT (_etext) { . = ALIGN(4); _srelocate = .; @@ -105,12 +104,12 @@ SECTIONS _ezero = .; } > ram - .heap (NOLOAD) : - { - . = ALIGN(4); - __end__ = . ; - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; - } > ram + .heap (NOLOAD) : + { + . = ALIGN(4); + __end__ = . ; + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + } > ram /* stack section */ .stack (NOLOAD): diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct new file mode 100644 index 0000000000..669d9fe7a7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct @@ -0,0 +1,19 @@ +;SAMR21G18A +;256KB FLASH (0x40000) @ 0x000000000 +;2KB RAM (0x8000) @ 0x20000000 + + +;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment + RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/startup_SAMR21.s b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/startup_SAMR21.s new file mode 100644 index 0000000000..a22e74af5f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/startup_SAMR21.s @@ -0,0 +1,166 @@ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/sys.cpp new file mode 100644 index 0000000000..c9ecd07cbc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/sys.cpp @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) +{ + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/SAMR21G18A.sct b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/SAMR21G18A.sct new file mode 100644 index 0000000000..669d9fe7a7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/SAMR21G18A.sct @@ -0,0 +1,19 @@ +;SAMR21G18A +;256KB FLASH (0x40000) @ 0x000000000 +;2KB RAM (0x8000) @ 0x20000000 + + +;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000) +LR_IROM1 0x00000000 0x40000 { ; load region size_region + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment + RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data + .ANY (+RW +ZI) + } + +} \ No newline at end of file diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/startup_SAMR21.s b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/startup_SAMR21.s new file mode 100644 index 0000000000..a22e74af5f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/startup_SAMR21.s @@ -0,0 +1,166 @@ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..c9ecd07cbc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2015 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) +{ + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld index d80cded0c3..21479a889e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld @@ -5,7 +5,7 @@ SEARCH_DIR(.) /* Memory Spaces Definitions */ MEMORY { rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 + ram (rwx) : ORIGIN = 0x20000000 + 0xB0, LENGTH = 0x00008000 - 0xB0 } /* The stack size used by the application. NOTE: you need to adjust according to your application. */ @@ -73,13 +73,6 @@ MEMORY { . = ALIGN(4); _etext = .; - .dvectors (NOLOAD) : - { - _sdvectors = .; - . = . + 0xB0; - _edvectors = .; - } > ram - .relocate : AT (_etext) { diff --git a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis_nvic.c b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis_nvic.c index 472279d186..c9e1799d28 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis_nvic.c +++ b/libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/cmsis_nvic.c @@ -30,8 +30,8 @@ */ #include "cmsis_nvic.h" -//#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM -extern uint32_t _sdvectors; +#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM +//extern uint32_t _sdvectors; #define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) @@ -42,11 +42,11 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) // Copy and switch to dynamic vectors if the first time called if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { uint32_t *old_vectors = vectors; - vectors = (uint32_t*)&_sdvectors; + vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; for (i=0; iVTOR = (uint32_t)&_sdvectors; + SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; } vectors[IRQn + 16] = vector; } diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py index 789dfe0f86..20134848fc 100644 --- a/workspace_tools/export/uvision4.py +++ b/workspace_tools/export/uvision4.py @@ -85,6 +85,9 @@ class Uvision4(Exporter): 'MAX32600MBED', 'MOTE_L152RC', 'NZ32SC151', + 'SAMR21G18A', + 'SAMD21J18A', + 'SAMD21G18A', ] USING_MICROLIB = [ @@ -121,6 +124,9 @@ class Uvision4(Exporter): 'LPC11U37H_401', 'MOTE_L152RC', 'NZ32SC151', + 'SAMR21G18A', + 'SAMD21J18A', + 'SAMD21G18A', ] FILE_TYPES = { diff --git a/workspace_tools/export/uvision4_samr21g18a.uvopt.tmpl b/workspace_tools/export/uvision4_samr21g18a.uvopt.tmpl new file mode 100644 index 0000000000..787d0cb50a --- /dev/null +++ b/workspace_tools/export/uvision4_samr21g18a.uvopt.tmpl @@ -0,0 +1,204 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed SAMR21G18A + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 14 + + + 0 + Data Sheet + DATASHTS\Freescale\K40PB.pdf + + + 1 + Technical Reference Manual + datashts\arm\cortex_m0p\r0p0\DDI0484B_CORTEX_M0P_R0P0_TRM.PDF + + + 2 + Generic User Guide + datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ULP2CM3 + -O2510 -S0 -C0 -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000) + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + + diff --git a/workspace_tools/export/uvision4_samr21g18a.uvproj.tmpl b/workspace_tools/export/uvision4_samr21g18a.uvproj.tmpl new file mode 100644 index 0000000000..c400145e37 --- /dev/null +++ b/workspace_tools/export/uvision4_samr21g18a.uvproj.tmpl @@ -0,0 +1,424 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + SAMR21G18A + 0x4 + ARM-ADS + + + SAMR21G18A + Atmel + IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0003FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") + + "Startup\Atmel\SAMR21\startup_SAMR21.s" ("Atmel SAMR21 Startup Code") + UL2CM3(-O207 -S9 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0ATSAMR21_256 -FS00 -FL040000) + 7537 + samr21.h + + + + + + + -D__SAMR21G18A__ + + + SFD\Atmel\SAMR21\ATSAMR21G18A.SFR + 0 + 0 + + + + Atmel\SAMR21\ + Atmel\SAMR21\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 0 + fromelf --bin -o build\{{name}}_SAMR21G18A.bin build\{{name}}.axf + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0+ + SARMCM3.DLL + + TARMCM1.DLL + -pCM0+ + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x20000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 48865fc720..76836c1079 100755 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -1632,8 +1632,8 @@ class SAMR21G18A(Target): self.core = "Cortex-M0+" self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMR21'] self.macros = ['__SAMR21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true'] - self.supported_toolchains = ["GCC_ARM"] - self.default_toolchain = "ARM" + self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"] + self.default_toolchain = "GCC_ARM" class SAMD21J18A(Target): def __init__(self): @@ -1641,8 +1641,8 @@ class SAMD21J18A(Target): self.core = "Cortex-M0+" self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMD21'] self.macros = ['__SAMD21J18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true'] - self.supported_toolchains = ["GCC_ARM"] - self.default_toolchain = "ARM" + self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"] + self.default_toolchain = "GCC_ARM" class SAMD21G18A(Target): def __init__(self): @@ -1650,8 +1650,8 @@ class SAMD21G18A(Target): self.core = "Cortex-M0+" self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMD21'] self.macros = ['__SAMD21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true'] - self.supported_toolchains = ["GCC_ARM"] - self.default_toolchain = "ARM" + self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"] + self.default_toolchain = "GCC_ARM" # Get a single instance for each target