mirror of https://github.com/ARMmbed/mbed-os.git
* Added Keil Compiler Supprot for SAMR21G18A
akhilpanayam
Karthik Purushothaman
parent
22ef412435
commit
c187bc952d
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@ -3,19 +3,17 @@ OUTPUT_ARCH(arm)
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SEARCH_DIR(.)
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/* Memory Spaces Definitions */
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MEMORY
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{
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rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
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ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
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}
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MEMORY {
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rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
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ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
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}
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/* The stack size used by the application. NOTE: you need to adjust according to your application. */
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STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
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/* The stack size used by the application. NOTE: you need to adjust according to your application. */
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STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
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/* Section Definitions */
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SECTIONS
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{
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.text :
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/* Section Definitions */
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SECTIONS {
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.text :
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{
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. = ALIGN(4);
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_sfixed = .;
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@ -66,23 +64,24 @@ SECTIONS
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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PROVIDE_HIDDEN (__exidx_start = .);
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.ARM.exidx :
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > rom
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PROVIDE_HIDDEN (__exidx_end = .);
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. = ALIGN(4);
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_etext = .;
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.dvectors (NOLOAD) :
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{
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_sdvectors = .;
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. = . + 0xB0;
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_edvectors = .;
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} > ram
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.relocate : AT (_etext)
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.dvectors (NOLOAD) :
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{
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_sdvectors = .;
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. = . + 0xB0;
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_edvectors = .;
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} > ram
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.relocate :
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AT (_etext)
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{
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. = ALIGN(4);
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_srelocate = .;
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@ -105,12 +104,12 @@ SECTIONS
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_ezero = .;
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} > ram
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.heap (NOLOAD) :
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{
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. = ALIGN(4);
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__end__ = . ;
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. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
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} > ram
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.heap (NOLOAD) :
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{
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. = ALIGN(4);
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__end__ = . ;
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. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
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} > ram
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/* stack section */
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.stack (NOLOAD):
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@ -0,0 +1,19 @@
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;SAMR21G18A
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;256KB FLASH (0x40000) @ 0x000000000
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;2KB RAM (0x8000) @ 0x20000000
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;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
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LR_IROM1 0x00000000 0x40000 { ; load region size_region
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ER_IROM1 0x00000000 0x40000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
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RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,166 @@
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__initial_sp EQU 0x20008000 ; Top of RAM
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD PM_Handler ; 0 Power Manager
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DCD SYSCTRL_Handler ; 1 System Control
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DCD WDT_Handler ; 2 Watchdog Timer
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DCD RTC_Handler ; 3 Real-Time Counter
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DCD EIC_Handler ; 4 External Interrupt Controller
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DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
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DCD DMAC_Handler ; 6 Direct Memory Access Controller
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DCD USB_Handler ; 7 Universal Serial Bus
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DCD EVSYS_Handler ; 8 Event System Interface
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DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
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DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
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DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
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DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
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DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
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DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
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DCD TCC0_Handler ; 15 Timer Counter Control 0
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DCD TCC1_Handler ; 16 Timer Counter Control 1
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DCD TCC2_Handler ; 17 Timer Counter Control 2
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DCD TC3_Handler ; 18 Basic Timer Counter 0
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DCD TC4_Handler ; 19 Basic Timer Counter 1
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DCD TC5_Handler ; 20 Basic Timer Counter 2
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DCD TC6_Handler ; 21 Basic Timer Counter 3
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DCD TC7_Handler ; 22 Basic Timer Counter 4
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DCD ADC_Handler ; 23 Analog Digital Converter
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DCD AC_Handler ; 24 Analog Comparators
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DCD DAC_Handler ; 25 Digital Analog Converter
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DCD PTC_Handler ; 26 Peripheral Touch Controller
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DCD I2S_Handler ; 27 Inter-IC Sound Interface
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT PM_Handler [WEAK]
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EXPORT SYSCTRL_Handler [WEAK]
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EXPORT WDT_Handler [WEAK]
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EXPORT RTC_Handler [WEAK]
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EXPORT EIC_Handler [WEAK]
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EXPORT NVMCTRL_Handler [WEAK]
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EXPORT DMAC_Handler [WEAK]
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EXPORT USB_Handler [WEAK]
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EXPORT EVSYS_Handler [WEAK]
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EXPORT SERCOM0_Handler [WEAK]
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EXPORT SERCOM1_Handler [WEAK]
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EXPORT SERCOM2_Handler [WEAK]
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EXPORT SERCOM3_Handler [WEAK]
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EXPORT SERCOM4_Handler [WEAK]
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EXPORT SERCOM5_Handler [WEAK]
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EXPORT TCC0_Handler [WEAK]
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EXPORT TCC1_Handler [WEAK]
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EXPORT TCC2_Handler [WEAK]
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EXPORT TC3_Handler [WEAK]
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EXPORT TC4_Handler [WEAK]
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EXPORT TC5_Handler [WEAK]
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EXPORT TC6_Handler [WEAK]
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EXPORT TC7_Handler [WEAK]
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EXPORT ADC_Handler [WEAK]
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EXPORT AC_Handler [WEAK]
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EXPORT DAC_Handler [WEAK]
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EXPORT PTC_Handler [WEAK]
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EXPORT I2S_Handler [WEAK]
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PM_Handler
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SYSCTRL_Handler
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WDT_Handler
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RTC_Handler
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EIC_Handler
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NVMCTRL_Handler
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DMAC_Handler
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USB_Handler
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EVSYS_Handler
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SERCOM0_Handler
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SERCOM1_Handler
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SERCOM2_Handler
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SERCOM3_Handler
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SERCOM4_Handler
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SERCOM5_Handler
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TCC0_Handler
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TCC1_Handler
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TCC2_Handler
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TC3_Handler
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TC4_Handler
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TC5_Handler
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TC6_Handler
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TC7_Handler
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ADC_Handler
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AC_Handler
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DAC_Handler
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PTC_Handler
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I2S_Handler
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B .
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ENDP
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ALIGN
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END
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@ -0,0 +1,41 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2015 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <rt_misc.h>
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#include <stdint.h>
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extern char Image$$RW_IRAM1$$ZI$$Limit[];
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extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
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{
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uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
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uint32_t sp_limit = __current_sp();
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zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
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struct __initial_stackheap r;
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r.heap_base = zi_limit;
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r.heap_limit = sp_limit;
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return r;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,19 @@
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;SAMR21G18A
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;256KB FLASH (0x40000) @ 0x000000000
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;2KB RAM (0x8000) @ 0x20000000
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;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
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LR_IROM1 0x00000000 0x40000 { ; load region size_region
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ER_IROM1 0x00000000 0x40000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
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RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@ -0,0 +1,166 @@
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__initial_sp EQU 0x20008000 ; Top of RAM
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD PM_Handler ; 0 Power Manager
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DCD SYSCTRL_Handler ; 1 System Control
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DCD WDT_Handler ; 2 Watchdog Timer
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DCD RTC_Handler ; 3 Real-Time Counter
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DCD EIC_Handler ; 4 External Interrupt Controller
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DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
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DCD DMAC_Handler ; 6 Direct Memory Access Controller
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DCD USB_Handler ; 7 Universal Serial Bus
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DCD EVSYS_Handler ; 8 Event System Interface
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DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
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DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
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DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
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DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
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DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
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DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
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DCD TCC0_Handler ; 15 Timer Counter Control 0
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DCD TCC1_Handler ; 16 Timer Counter Control 1
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DCD TCC2_Handler ; 17 Timer Counter Control 2
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DCD TC3_Handler ; 18 Basic Timer Counter 0
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DCD TC4_Handler ; 19 Basic Timer Counter 1
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DCD TC5_Handler ; 20 Basic Timer Counter 2
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DCD TC6_Handler ; 21 Basic Timer Counter 3
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DCD TC7_Handler ; 22 Basic Timer Counter 4
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DCD ADC_Handler ; 23 Analog Digital Converter
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DCD AC_Handler ; 24 Analog Comparators
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DCD DAC_Handler ; 25 Digital Analog Converter
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DCD PTC_Handler ; 26 Peripheral Touch Controller
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DCD I2S_Handler ; 27 Inter-IC Sound Interface
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT PM_Handler [WEAK]
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EXPORT SYSCTRL_Handler [WEAK]
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EXPORT WDT_Handler [WEAK]
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EXPORT RTC_Handler [WEAK]
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EXPORT EIC_Handler [WEAK]
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EXPORT NVMCTRL_Handler [WEAK]
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EXPORT DMAC_Handler [WEAK]
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EXPORT USB_Handler [WEAK]
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EXPORT EVSYS_Handler [WEAK]
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EXPORT SERCOM0_Handler [WEAK]
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EXPORT SERCOM1_Handler [WEAK]
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EXPORT SERCOM2_Handler [WEAK]
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EXPORT SERCOM3_Handler [WEAK]
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EXPORT SERCOM4_Handler [WEAK]
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EXPORT SERCOM5_Handler [WEAK]
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EXPORT TCC0_Handler [WEAK]
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EXPORT TCC1_Handler [WEAK]
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EXPORT TCC2_Handler [WEAK]
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EXPORT TC3_Handler [WEAK]
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EXPORT TC4_Handler [WEAK]
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EXPORT TC5_Handler [WEAK]
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EXPORT TC6_Handler [WEAK]
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EXPORT TC7_Handler [WEAK]
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EXPORT ADC_Handler [WEAK]
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EXPORT AC_Handler [WEAK]
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EXPORT DAC_Handler [WEAK]
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EXPORT PTC_Handler [WEAK]
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EXPORT I2S_Handler [WEAK]
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PM_Handler
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SYSCTRL_Handler
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WDT_Handler
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RTC_Handler
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EIC_Handler
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NVMCTRL_Handler
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DMAC_Handler
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USB_Handler
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EVSYS_Handler
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SERCOM0_Handler
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SERCOM1_Handler
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SERCOM2_Handler
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SERCOM3_Handler
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SERCOM4_Handler
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SERCOM5_Handler
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TCC0_Handler
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TCC1_Handler
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TCC2_Handler
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TC3_Handler
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TC4_Handler
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TC5_Handler
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TC6_Handler
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TC7_Handler
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ADC_Handler
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AC_Handler
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DAC_Handler
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PTC_Handler
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I2S_Handler
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B .
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ENDP
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ALIGN
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END
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|
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@ -0,0 +1,41 @@
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/* mbed Microcontroller Library
|
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* Copyright (c) 2006-2015 ARM Limited
|
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*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||
{
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -5,7 +5,7 @@ SEARCH_DIR(.)
|
|||
/* Memory Spaces Definitions */
|
||||
MEMORY {
|
||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
|
||||
ram (rwx) : ORIGIN = 0x20000000 + 0xB0, LENGTH = 0x00008000 - 0xB0
|
||||
}
|
||||
|
||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||
|
|
@ -73,13 +73,6 @@ MEMORY {
|
|||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
|
||||
.dvectors (NOLOAD) :
|
||||
{
|
||||
_sdvectors = .;
|
||||
. = . + 0xB0;
|
||||
_edvectors = .;
|
||||
} > ram
|
||||
|
||||
.relocate :
|
||||
AT (_etext)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -30,8 +30,8 @@
|
|||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
//#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||
extern uint32_t _sdvectors;
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||
//extern uint32_t _sdvectors;
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
|
|
@ -42,11 +42,11 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
|||
// Copy and switch to dynamic vectors if the first time called
|
||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||
uint32_t *old_vectors = vectors;
|
||||
vectors = (uint32_t*)&_sdvectors;
|
||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
|
||||
SCB->VTOR = (uint32_t)&_sdvectors;
|
||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||
}
|
||||
vectors[IRQn + 16] = vector;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -85,6 +85,9 @@ class Uvision4(Exporter):
|
|||
'MAX32600MBED',
|
||||
'MOTE_L152RC',
|
||||
'NZ32SC151',
|
||||
'SAMR21G18A',
|
||||
'SAMD21J18A',
|
||||
'SAMD21G18A',
|
||||
]
|
||||
|
||||
USING_MICROLIB = [
|
||||
|
|
@ -121,6 +124,9 @@ class Uvision4(Exporter):
|
|||
'LPC11U37H_401',
|
||||
'MOTE_L152RC',
|
||||
'NZ32SC151',
|
||||
'SAMR21G18A',
|
||||
'SAMD21J18A',
|
||||
'SAMD21G18A',
|
||||
]
|
||||
|
||||
FILE_TYPES = {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,204 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>mbed SAMR21G18A</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>8000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>1</RunSim>
|
||||
<RunTarget>0</RunTarget>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>14</CpuCode>
|
||||
<Books>
|
||||
<Book>
|
||||
<Number>0</Number>
|
||||
<Title>Data Sheet</Title>
|
||||
<Path>DATASHTS\Freescale\K40PB.pdf</Path>
|
||||
</Book>
|
||||
<Book>
|
||||
<Number>1</Number>
|
||||
<Title>Technical Reference Manual</Title>
|
||||
<Path>datashts\arm\cortex_m0p\r0p0\DDI0484B_CORTEX_M0P_R0P0_TRM.PDF</Path>
|
||||
</Book>
|
||||
<Book>
|
||||
<Number>2</Number>
|
||||
<Title>Generic User Guide</Title>
|
||||
<Path>datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF</Path>
|
||||
</Book>
|
||||
</Books>
|
||||
<DllOpt>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
|
||||
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
|
||||
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||
</DllOpt>
|
||||
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>14</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ULP2CM3</Key>
|
||||
<Name>-O2510 -S0 -C0 -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>src</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>8</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>0</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>1</TopLine>
|
||||
<CurrentLine>2</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>main.cpp</PathWithFileName>
|
||||
<FilenameWithoutPath>main.cpp</FilenameWithoutPath>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,424 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||
|
||||
<SchemaVersion>1.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>SAMR21G18A</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>SAMR21G18A</Device>
|
||||
<Vendor>Atmel</Vendor>
|
||||
<Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0003FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+")</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile>"Startup\Atmel\SAMR21\startup_SAMR21.s" ("Atmel SAMR21 Startup Code")</StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-O207 -S9 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0ATSAMR21_256 -FS00 -FL040000)</FlashDriverDll>
|
||||
<DeviceId>7537</DeviceId>
|
||||
<RegisterFile>samr21.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc>-D__SAMR21G18A__</SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>SFD\Atmel\SAMR21\ATSAMR21G18A.SFR</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath>Atmel\SAMR21\</RegisterFilePath>
|
||||
<DBRegisterFilePath>Atmel\SAMR21\</DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\</OutputDirectory>
|
||||
<OutputName>{{name}}</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>fromelf --bin -o build\{{name}}_SAMR21G18A.bin build\{{name}}.axf</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>14</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver>BIN\CMSIS_AGDI.dll</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4105</DriverSelection>
|
||||
</Flash1>
|
||||
<Flash2>BIN\CMSIS_AGDI.dll</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M0+"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x8000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<VariousControls>
|
||||
<MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
|
||||
<Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x20000000</DataAddressRange>
|
||||
<ScatterFile>{{scatter_file}}</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>
|
||||
{% for file in object_files %}
|
||||
{{file}}
|
||||
{% endfor %}
|
||||
</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
{% for group,files in source_files %}
|
||||
<Group>
|
||||
<GroupName>{{group}}</GroupName>
|
||||
<Files>
|
||||
{% for file in files %}
|
||||
<File>
|
||||
<FileName>{{file.name}}</FileName>
|
||||
<FileType>{{file.type}}</FileType>
|
||||
<FilePath>{{file.path}}</FilePath>
|
||||
{%if file.type == "1" %}
|
||||
<FileOption>
|
||||
<FileArmAds>
|
||||
<Cads>
|
||||
<VariousControls>
|
||||
<MiscControls>--c99</MiscControls>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
</FileArmAds>
|
||||
</FileOption>
|
||||
{% endif %}
|
||||
</File>
|
||||
{% endfor %}
|
||||
</Files>
|
||||
</Group>
|
||||
{% endfor %}
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
|
|
@ -1632,8 +1632,8 @@ class SAMR21G18A(Target):
|
|||
self.core = "Cortex-M0+"
|
||||
self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMR21']
|
||||
self.macros = ['__SAMR21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
|
||||
self.supported_toolchains = ["GCC_ARM"]
|
||||
self.default_toolchain = "ARM"
|
||||
self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"]
|
||||
self.default_toolchain = "GCC_ARM"
|
||||
|
||||
class SAMD21J18A(Target):
|
||||
def __init__(self):
|
||||
|
|
@ -1641,8 +1641,8 @@ class SAMD21J18A(Target):
|
|||
self.core = "Cortex-M0+"
|
||||
self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMD21']
|
||||
self.macros = ['__SAMD21J18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
|
||||
self.supported_toolchains = ["GCC_ARM"]
|
||||
self.default_toolchain = "ARM"
|
||||
self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"]
|
||||
self.default_toolchain = "GCC_ARM"
|
||||
|
||||
class SAMD21G18A(Target):
|
||||
def __init__(self):
|
||||
|
|
@ -1650,8 +1650,8 @@ class SAMD21G18A(Target):
|
|||
self.core = "Cortex-M0+"
|
||||
self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMD21']
|
||||
self.macros = ['__SAMD21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
|
||||
self.supported_toolchains = ["GCC_ARM"]
|
||||
self.default_toolchain = "ARM"
|
||||
self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"]
|
||||
self.default_toolchain = "GCC_ARM"
|
||||
|
||||
|
||||
# Get a single instance for each target
|
||||
|
|
|
|||
Loading…
Reference in New Issue