diff --git a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/serial_api.c b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/serial_api.c index 126b1169e7..b74e7b527c 100644 --- a/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC176X/serial_api.c @@ -76,7 +76,7 @@ serial_t stdio_uart; struct serial_global_data_s { uint32_t serial_irq_id; gpio_t sw_rts, sw_cts; - uint8_t rx_irq_set_flow, rx_irq_set_api; + uint8_t count, rx_irq_set_flow, rx_irq_set_api; }; static struct serial_global_data_s uart_data[UART_NUM]; @@ -100,7 +100,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { case UART_2: LPC_SC->PCONP |= 1 << 24; break; case UART_3: LPC_SC->PCONP |= 1 << 25; break; } - + // enable fifos and default rx trigger level obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled | 0 << 1 // Rx Fifo Reset @@ -357,6 +357,7 @@ int serial_getc(serial_t *obj) { void serial_putc(serial_t *obj, int c) { while (!serial_writable(obj)); obj->uart->THR = c; + uart_data[obj->index].count++; } int serial_readable(serial_t *obj) { @@ -364,10 +365,16 @@ int serial_readable(serial_t *obj) { } int serial_writable(serial_t *obj) { + int isWritable = 1; if (NC != uart_data[obj->index].sw_cts.pin) - return (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->LSR & 0x40); //If flow control: writable if CTS low + UART done - else - return obj->uart->LSR & 0x20; //No flow control: writable if space in holding register + isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->LSR & 0x40); //If flow control: writable if CTS low + UART done + else { + if (obj->uart->LSR & 0x20) + uart_data[obj->index].count = 0; + else if (uart_data[obj->index].count >= 16) + isWritable = 0; + } + return isWritable; } void serial_clear(serial_t *obj) {