diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf new file mode 100644 index 0000000000..a35fa893dc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf @@ -0,0 +1,40 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0002ffff; +define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe000; +define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x1000; +/**** End of ICF editor section. ###ICF###*/ + +define symbol __region_RAM2_start__ = 0x20000000; +define symbol __region_RAM2_end__ = 0x20005fff; + +define symbol __FlashConfig_start__ = 0x00000400; +define symbol __FlashConfig_end__ = 0x0000040f; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__]; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in FlashConfig_region {section FlashConfig}; + +place in ROM_region { readonly }; + +place in RAM_region { readwrite, block CSTACK, block HEAP }; diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.s b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.s new file mode 100644 index 0000000000..ae00df63cf --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.s @@ -0,0 +1,182 @@ +/************************************************** + * + * Copyright 2010 IAR Systems. All rights reserved. + * + * $Revision: 16 $ + * + **************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:ROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + ; External Interrupts + DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt + DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt + DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt + DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt + DCD 0 ; Reserved + DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt + DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning + DCD LLW_IRQHandler ; Low Leakage Wakeup + DCD I2C0_IRQHandler ; I2C0 interrupt + DCD I2C1_IRQHandler ; I2C0 interrupt 25 + DCD SPI0_IRQHandler ; SPI0 interrupt + DCD SPI1_IRQHandler ; SPI1 interrupt + DCD UART0_IRQHandler ; UART0 status/error interrupt + DCD UART1_IRQHandler ; UART1 status/error interrupt + DCD UART2_IRQHandler ; UART2 status/error interrupt + DCD ADC0_IRQHandler ; ADC0 interrupt + DCD CMP0_IRQHandler ; CMP0 interrupt + DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt + DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt + DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt + DCD RTC_IRQHandler ; RTC interrupt + DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt + DCD PIT_IRQHandler ; PIT timer interrupt + DCD I2S0_IRQHandler ; I2S0 transmit interrupt + DCD USB0_IRQHandler ; USB0 interrupt + DCD DAC0_IRQHandler ; DAC0 interrupt + DCD TSI0_IRQHandler ; TSI0 interrupt + DCD MCG_IRQHandler ; MCG interrupt + DCD LPTimer_IRQHandler ; LPTimer interrupt + DCD LCD_IRQHandler ; Segment LCD Interrupt + DCD PORTA_IRQHandler ; Port A interrupt + DCD PORTD_IRQHandler ; Port D interrupt + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + PUBWEAK HardFault_Handler + PUBWEAK SVC_Handler + PUBWEAK PendSV_Handler + PUBWEAK SysTick_Handler + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA3_IRQHandler + PUBWEAK Reserved20_IRQHandler + PUBWEAK FTFA_IRQHandler + PUBWEAK LVD_LVW_IRQHandler + PUBWEAK LLW_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK TPM0_IRQHandler + PUBWEAK TPM1_IRQHandler + PUBWEAK TPM2_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT_IRQHandler + PUBWEAK I2S0_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK TSI0_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPTimer_IRQHandler + PUBWEAK LCD_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTD_IRQHandler + + SECTION .text:CODE:REORDER:NOROOT(1) + THUMB +NMI_Handler +HardFault_Handler +SVC_Handler +PendSV_Handler +SysTick_Handler +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +LVD_LVW_IRQHandler +LLW_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +I2S0_IRQHandler +USB0_IRQHandler +DAC0_IRQHandler +TSI0_IRQHandler +MCG_IRQHandler +LPTimer_IRQHandler +LCD_IRQHandler +PORTA_IRQHandler +PORTD_IRQHandler +Default_Handler + + B Default_Handler + END diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 4521a215b9..0de0858249 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -48,7 +48,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('KL05Z', ('ARM', 'uARM', 'GCC_ARM', 'IAR')), ('KL25Z', ('ARM', 'GCC_ARM', 'IAR')), ('KL43Z', ('ARM', 'GCC_ARM')), - ('KL46Z', ('ARM', 'GCC_ARM')), + ('KL46Z', ('ARM', 'GCC_ARM', 'IAR')), ('K64F', ('ARM', 'GCC_ARM')), ('K22F', ('ARM', 'GCC_ARM')), ('K20D50M', ('ARM', 'GCC_ARM' , 'IAR')), diff --git a/workspace_tools/export/iar.py b/workspace_tools/export/iar.py index c7794e12b7..639a48c665 100644 --- a/workspace_tools/export/iar.py +++ b/workspace_tools/export/iar.py @@ -29,6 +29,7 @@ class IAREmbeddedWorkbench(Exporter): 'K20D50M', 'KL05Z', 'KL25Z', + 'KL46Z', 'NUCLEO_F302R8', 'NUCLEO_F401RE', 'NUCLEO_F411RE', diff --git a/workspace_tools/export/iar_kl46z.ewp.tmpl b/workspace_tools/export/iar_kl46z.ewp.tmpl new file mode 100644 index 0000000000..fac1b5c4e1 --- /dev/null +++ b/workspace_tools/export/iar_kl46z.ewp.tmpl @@ -0,0 +1,956 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 22 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 30 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 16 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + {% for files in source_files %} + + $PROJ_DIR$\{{files}} + + {% endfor %} + + + diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 5410096001..589ff4dad6 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -147,7 +147,7 @@ class KL46Z(Target): Target.__init__(self) self.core = "Cortex-M0+" self.extra_labels = ['Freescale', 'KLXX'] - self.supported_toolchains = ["GCC_ARM", "ARM"] + self.supported_toolchains = ["GCC_ARM", "ARM", "IAR"] self.supported_form_factors = ["ARDUINO"] self.is_disk_virtual = True self.detect_code = "0220"