diff --git a/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PeripheralPins.c
index 1c45d42743..cb55e8833a 100644
--- a/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PeripheralPins.c
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PeripheralPins.c
@@ -313,17 +313,20 @@ const PinMap PinMap_UART_CTS[] = {
 //*** SPI ***
 
 const PinMap PinMap_SPI_MOSI[] = {
+    {PA_0, SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI0},
     {PA_0, SPI_1, SYS_GPA_MFPL_PA0MFP_SPI1_MOSI},
     {PA_8, SPI_3, SYS_GPA_MFPH_PA8MFP_SPI3_MOSI},
     {PA_15, SPI_3, SYS_GPA_MFPH_PA15MFP_SPI3_MOSI},
     {PB_4, SPI_2, SYS_GPB_MFPL_PB4MFP_SPI2_MOSI},
     {PB_8, SPI_4, SYS_GPB_MFPH_PB8MFP_SPI4_MOSI},
     {PB_12, SPI_1, SYS_GPB_MFPH_PB12MFP_SPI1_MOSI},
+    {PC_0, SPI_0, SYS_GPC_MFPL_PC0MFP_SPI0_MOSI0},
     {PC_2, SPI_2, SYS_GPC_MFPL_PC2MFP_SPI2_MOSI},
     {PC_6, SPI_2, SYS_GPC_MFPL_PC6MFP_SPI2_MOSI},
     {PC_11, SPI_4, SYS_GPC_MFPH_PC11MFP_SPI4_MOSI},
     {PD_0, SPI_1, SYS_GPD_MFPL_PD0MFP_SPI1_MOSI},
     {PD_6, SPI_2, SYS_GPD_MFPL_PD6MFP_SPI2_MOSI},
+    {PE_0, SPI_0, SYS_GPE_MFPL_PE0MFP_SPI0_MOSI0},
     {PE_0, SPI_2, SYS_GPE_MFPL_PE0MFP_SPI2_MOSI},
     {PE_2, SPI_4, SYS_GPE_MFPL_PE2MFP_SPI4_MOSI},
     {PE_10, SPI_3, SYS_GPE_MFPH_PE10MFP_SPI3_MOSI},
@@ -334,19 +337,22 @@ const PinMap PinMap_SPI_MOSI[] = {
     
     {NC,    NC,    0}
 };
-
+    
 const PinMap PinMap_SPI_MISO[] = {
+    {PA_1, SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO0},
     {PA_1, SPI_1, SYS_GPA_MFPL_PA1MFP_SPI1_MISO},
     {PA_9, SPI_3, SYS_GPA_MFPH_PA9MFP_SPI3_MISO},
     {PA_14, SPI_3, SYS_GPA_MFPH_PA14MFP_SPI3_MISO},
     {PB_5, SPI_2, SYS_GPB_MFPL_PB5MFP_SPI2_MISO},
     {PB_9, SPI_4, SYS_GPB_MFPH_PB9MFP_SPI4_MISO},
     {PB_13, SPI_1, SYS_GPB_MFPH_PB13MFP_SPI1_MISO},
+    {PC_1, SPI_0, SYS_GPC_MFPL_PC1MFP_SPI0_MISO0},
     {PC_3, SPI_2, SYS_GPC_MFPL_PC3MFP_SPI2_MISO},
     {PC_7, SPI_2, SYS_GPC_MFPL_PC7MFP_SPI2_MISO},
     {PC_12, SPI_4, SYS_GPC_MFPH_PC12MFP_SPI4_MISO},
     {PD_1, SPI_1, SYS_GPD_MFPL_PD1MFP_SPI1_MISO},
     {PD_7, SPI_2, SYS_GPD_MFPL_PD7MFP_SPI2_MISO},
+    {PE_1, SPI_0, SYS_GPE_MFPL_PE1MFP_SPI0_MISO0},
     {PE_1, SPI_2, SYS_GPE_MFPL_PE1MFP_SPI2_MISO},
     {PE_3, SPI_4, SYS_GPE_MFPL_PE3MFP_SPI4_MISO},
     {PE_9, SPI_3, SYS_GPE_MFPH_PE9MFP_SPI3_MISO},