From bc84c03a37e10c819e55592aa1efcb621900460b Mon Sep 17 00:00:00 2001
From: "U-owner-PC\\owner" <Wayne Roberts>
Date: Mon, 16 Mar 2015 16:26:18 -0700
Subject: [PATCH] handle HSE-PLL enabled upone deepsleep wakeup

---
 .../TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c     | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
 mode change 100644 => 100755 libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c

diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c
old mode 100644
new mode 100755
index b5b3a8d48b..b0c277141a
--- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c
@@ -125,7 +125,7 @@
   */
 
 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
+#define USE_PLL_HSE_EXTC (0) /* Use external clock */
 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
 
 /**
@@ -485,6 +485,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
   RCC_ClkInitTypeDef RCC_ClkInitStruct;
   RCC_OscInitTypeDef RCC_OscInitStruct;
 
+  if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
+    return 1;   // already on HSE PLL, could occur from deepsleep waking
+
   /* Used to gain time after DeepSleep in case HSI is used */
   if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
   {