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Merge pull request #1936 from meriac/master 

Enabled uVisor secure mode for K64F
pull/1952/head
Sam Grove 2016-06-14 17:28:58 +01:00 committed by GitHub
parent ffa45c9935 fd6944f6e1
commit bbb50704af
22 changed files with 516 additions and 142 deletions
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8
features/FEATURE_UVISOR/AUTHORS.txt
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@ -1,7 +1,7 @@
519 Milosch Meriac
420 Alessandro Angelino
16 Niklas Hauser
15 Jaeden Amero
523 Milosch Meriac
422 Alessandro Angelino
17 Niklas Hauser
16 Jaeden Amero
3 Hugo Vincent
3 JaredCJR
3 Jim Huang

2
features/FEATURE_UVISOR/VERSION.txt
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@ -1 +1 @@
v0.9.14-alpha
v0.9.14-alpha-8-g1f0a4b9b181476c65d396838d61465ea5363e23b

33
features/FEATURE_UVISOR/includes/uvisor/api/inc/cmsis_nvic_virtual.h Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (c) 2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __UVISOR_API_NVIC_VIRTUAL_H__
#define __UVISOR_API_NVIC_VIRTUAL_H__
#include "api/inc/interrupts.h"
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ vIRQ_EnableIRQ
#define NVIC_DisableIRQ vIRQ_DisableIRQ
#define NVIC_GetPendingIRQ vIRQ_GetPendingIRQ
#define NVIC_SetPendingIRQ vIRQ_SetPendingIRQ
#define NVIC_ClearPendingIRQ vIRQ_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority vIRQ_SetPriority
#define NVIC_GetPriority vIRQ_GetPriority
#endif /* __UVISOR_API_NVIC_VIRTUAL_H__ */

25
features/FEATURE_UVISOR/includes/uvisor/api/inc/cmsis_vectab_virtual.h Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (c) 2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __UVISOR_API_VECTAB_VIRTUAL_H__
#define __UVISOR_API_VECTAB_VIRTUAL_H__
#include "api/inc/interrupts.h"
#define NVIC_SetVector vIRQ_SetVector
#define NVIC_GetVector vIRQ_GetVector
#endif /* __UVISOR_API_VECTAB_VIRTUAL_H__ */

58
features/FEATURE_UVISOR/includes/uvisor/api/inc/register_gateway.h
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@ -60,16 +60,17 @@
*
* @param box_name[in] The name of the source box as decalred in
* `UVISOR_BOX_CONFIG`.
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param addr[in] The address for the data access.
* @param operation[in] The operation to perform at the address for the read. It
* is chosen among the `UVISOR_RGW_OP_*` macros.
* @param shared[in] True if the gateway can be performed by any box. In this
* case, the box_name field does not guarantee exclusivity.
* @param mask[in] The mask to apply for the read operation.
* @returns The value read from address using the operation and mask provided
* (or their respective defaults if they have not been provided).
*/
#define uvisor_read(box_name, addr, op, shared, msk) \
#define uvisor_read(box_name, shared, addr, op, msk) \
({ \
/* Instanstiate the gateway. This gets resolved at link-time. */ \
__attribute__((aligned(4))) static TRegisterGateway const register_gateway = { \
@ -106,15 +107,16 @@
*
* @param box_name[in] The name of the source box as decalred in
* `UVISOR_BOX_CONFIG`.
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param addr[in] The address for the data access.
* @param val[in] The value to write at address.
* @param operation[in] The operation to perform at the address for the read. It
* is chosen among the `UVISOR_RGW_OP_*` macros.
* @param shared[in] True if the gateway can be performed by any box. In this
* case, the box_name field does not guarantee exclusivity.
* @param mask[in] The mask to apply for the write operation.
*/
#define uvisor_write(box_name, addr, val, op, shared, msk) \
#define uvisor_write(box_name, shared, addr, val, op, msk) \
{ \
/* Instanstiate the gateway. This gets resolved at link-time. */ \
__attribute__((aligned(4))) static TRegisterGateway const register_gateway = { \
@ -143,77 +145,95 @@
/** Get the selected bits at the target address.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @returns The value `*address & mask`.
*/
#define UVISOR_BITS_GET(box_name, address, mask) \
#define UVISOR_BITS_GET(box_name, shared, address, mask) \
/* Register gateway implementation:
* *address & mask */ \
uvisor_read(box_name, address, UVISOR_RGW_OP_READ_AND, false, mask)
uvisor_read(box_name, shared, address, UVISOR_RGW_OP_READ_AND, mask)
/** Check the selected bits at the target address.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Address at which to check the bits
* @param mask[in] Bits to select out of the target address
* @returns The value `(bool) (*address & mask) == mask)`.
* @returns The value `((*address & mask) == mask)`.
*/
#define UVISOR_BITS_CHECK(box_name, address, mask) \
((bool) (UVISOR_BITS_GET(box_name, address, mask) == mask))
#define UVISOR_BITS_CHECK(box_name, shared, address, mask) \
((UVISOR_BITS_GET(box_name, shared, address, mask)) == (mask))
/** Set the selected bits to 1 at the target address.
*
* Equivalent to: `*address |= mask`.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define UVISOR_BITS_SET(box_name, address, mask) \
#define UVISOR_BITS_SET(box_name, shared, address, mask) \
/* Register gateway implementation:
* *address |= (mask & mask) */ \
uvisor_write(box_name, address, mask, UVISOR_RGW_OP_WRITE_OR, false, mask)
uvisor_write(box_name, shared, address, mask, UVISOR_RGW_OP_WRITE_OR, mask)
/** Clear the selected bits at the target address.
*
* Equivalent to: `*address &= ~mask`.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define UVISOR_BITS_CLEAR(box_name, address, mask) \
#define UVISOR_BITS_CLEAR(box_name, shared, address, mask) \
/* Register gateway implementation:
* *address &= (0x00000000 | ~mask) */ \
uvisor_write(box_name, address, 0x00000000, UVISOR_RGW_OP_WRITE_AND, false, mask)
uvisor_write(box_name, shared, address, 0x00000000, UVISOR_RGW_OP_WRITE_AND, mask)
/** Set the selected bits at the target address to the given value.
*
* Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @param value[in] Value to write at the address location. Note: The value
* must be already shifted to the correct bit position
*/
#define UVISOR_BITS_SET_VALUE(box_name, address, mask, value) \
#define UVISOR_BITS_SET_VALUE(box_name, shared, address, mask, value) \
/* Register gateway implementation:
* *address = (*address & ~mask) | (value & mask) */ \
uvisor_write(box_name, address, value, UVISOR_RGW_OP_WRITE_REPLACE, false, mask)
uvisor_write(box_name, shared, address, value, UVISOR_RGW_OP_WRITE_REPLACE, mask)
/** Toggle the selected bits at the target address.
*
* Equivalent to: `*address ^= mask`.
* @param box_name[in] Box name as defined by the uVisor box configuration
* macro `UVISOR_BOX_CONFIG`
* @param shared[in] Whether the gateway can be shared with other boxes or
* not. Two values are available: UVISOR_RGW_SHARED,
* UVISOR_RGW_EXCLUSIVE.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define UVISOR_BITS_TOGGLE(box_name, address, mask) \
#define UVISOR_BITS_TOGGLE(box_name, shared, address, mask) \
/* Register gateway implementation:
* *address ^= (0xFFFFFFFF & mask) */ \
uvisor_write(box_name, address, 0xFFFFFFFF, UVISOR_RGW_OP_WRITE_XOR, false, mask)
uvisor_write(box_name, shared, address, 0xFFFFFFFF, UVISOR_RGW_OP_WRITE_XOR, mask)
#endif /* __UVISOR_API_REGISTER_GATEWAY_H__ */

4
features/FEATURE_UVISOR/includes/uvisor/api/inc/register_gateway_exports.h
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@ -79,6 +79,10 @@ typedef struct {
(((uint16_t) (width) << __UVISOR_RGW_OP_WIDTH_POS) & __UVISOR_RGW_OP_WIDTH_MASK) | \
(((uint16_t) (shared) << __UVISOR_RGW_OP_SHARED_POS) & __UVISOR_RGW_OP_SHARED_MASK)))
/** Register gateway operation - Shared */
#define UVISOR_RGW_SHARED 1
#define UVISOR_RGW_EXCLUSIVE 0
/** Register gateway operation - Type */
#define UVISOR_RGW_OP_READ 0 /**< value = *address */
#define UVISOR_RGW_OP_READ_AND 1 /**< value = *address & mask */

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features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_EFM32/TARGET_DEBUG/TARGET_M3/libconfiguration_efm32_m3_p1.a
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features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_EFM32/TARGET_DEBUG/TARGET_M4/libconfiguration_efm32_m4_p1.a
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features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_EFM32/TARGET_RELEASE/TARGET_M3/libconfiguration_efm32_m3_p1.a
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features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_MCU_K64F/TARGET_DEBUG/TARGET_M4/libconfiguration_kinetis_m4_0x1fff0000.a
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features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_MCU_K64F/TARGET_RELEASE/TARGET_M4/libconfiguration_kinetis_m4_0x1fff0000.a
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features/FEATURE_UVISOR/targets/TARGET_UVISOR_SUPPORTED/TARGET_STM32F4/TARGET_DEBUG/TARGET_M4/libconfiguration_stm32_m4_0x10000000_0x0.a
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10
hal/common/critical.c
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@ -53,9 +53,14 @@ void core_util_critical_section_enter()
are enabled, then something has gone badly wrong thus assert an error.
*/
MBED_ASSERT(interrupt_enable_counter < UINT32_MAX);
// FIXME
#ifndef FEATURE_UVISOR
if (interrupt_enable_counter > 0) {
MBED_ASSERT(interrupts_disabled & 0x1);
}
#else
#warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
#endif /* FEATURE_UVISOR */
interrupt_enable_counter++;
}
@ -64,9 +69,14 @@ void core_util_critical_section_exit()
/* If critical_section_enter has not previously been called, do nothing */
if (interrupt_enable_counter) {
// FIXME
#ifndef FEATURE_UVISOR
uint32_t interrupts_disabled = get_interrupts_disabled(); /* get the current interrupt disabled state */
MBED_ASSERT(interrupts_disabled & 0x1); /* Interrupts must be disabled on invoking an exit from a critical section */
#else
#warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
#endif /* FEATURE_UVISOR */
interrupt_enable_counter--;

8
hal/targets/cmsis/TARGET_Freescale/TARGET_K64F/TOOLCHAIN_GCC_ARM/MK64FN1M0xxx12.ld
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@ -90,7 +90,11 @@ SECTIONS
} > m_flash_config
/* The program code and other data goes into internal flash */
.text :
/* Note: The uVisor expects this section at a fixed location, as specified by
* the porting process configuration parameter: FLASH_OFFSET. */
__UVISOR_TEXT_OFFSET = 0x410;
__UVISOR_TEXT_START = ORIGIN(m_interrupts) + __UVISOR_TEXT_OFFSET;
.text __UVISOR_TEXT_START :
{
/* uVisor code and data */
. = ALIGN(4);
@ -200,7 +204,7 @@ SECTIONS
__UVISOR_BSS_START = ORIGIN(m_data) + __UVISOR_SRAM_OFFSET;
ASSERT(__interrupts_ram_end__ <= __UVISOR_BSS_START,
"The ISR relocation region overlaps with the uVisor BSS section.")
.uvisor.bss (NOLOAD):
.uvisor.bss __UVISOR_BSS_START (NOLOAD):
{
. = ALIGN(32);
__uvisor_bss_start = .;

4
hal/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis_nvic.c
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@ -32,11 +32,11 @@
extern void InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
InstallIRQHandler(IRQn, vector);
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t __NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + 16];
}

4
hal/targets/cmsis/TARGET_Freescale/TARGET_K64F/cmsis_nvic.h
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@ -41,8 +41,8 @@
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t __NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}

49
hal/targets/cmsis/core_cm4.h
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@ -1502,6 +1502,35 @@ typedef struct
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* CMSIS_VECTAB_VIRTUAL */
/** \brief Set Priority Grouping
The function sets the priority grouping field using the required unlock sequence.
@ -1512,7 +1541,7 @@ typedef struct
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
@ -1532,7 +1561,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
@ -1544,7 +1573,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@ -1556,7 +1585,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@ -1572,7 +1601,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@ -1584,7 +1613,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@ -1596,7 +1625,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@ -1611,7 +1640,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
\return 0 Interrupt status is not active.
\return 1 Interrupt status is active.
*/
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@ -1626,7 +1655,7 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if((int32_t)IRQn < 0) {
SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
@ -1648,7 +1677,7 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if((int32_t)IRQn < 0) {

201
hal/targets/cmsis/core_cmSecureAccess.h Normal file
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@ -0,0 +1,201 @@
/**************************************************************************//**
* @file core_cmSecureAccess.h
* @brief CMSIS Cortex-M Core Secure Access Header File
* @version XXX
* @date 10. June 2016
*
* @note
*
******************************************************************************/
/* Copyright (c) 2016 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CM_SECURE_ACCESS_H
#define __CORE_CM_SECURE_ACCESS_H
/* ########################### Core Secure Access ########################### */
#ifdef FEATURE_UVISOR
#include "uvisor-lib.h"
/* Secure uVisor implementation. */
/** Set the value at the target address.
*
* Equivalent to: `*address = value`.
* @param address[in] Target address
* @param value[in] Value to write at the address location.
*/
#define SECURE_WRITE(address, value) \
uvisor_write(main, UVISOR_RGW_SHARED, address, value, UVISOR_RGW_OP_WRITE, 0xFFFFFFFFUL)
/** Get the value at the target address.
*
* @param address[in] Target address
* @returns The value `*address`.
*/
#define SECURE_READ(address) \
uvisor_read(main, UVISOR_RGW_SHARED, address, UVISOR_RGW_OP_READ, 0xFFFFFFFFUL)
/** Get the selected bits at the target address.
*
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @returns The value `*address & mask`.
*/
#define SECURE_BITS_GET(address, mask) \
UVISOR_BITS_GET(main, UVISOR_RGW_SHARED, address, mask)
/** Check the selected bits at the target address.
*
* @param address[in] Address at which to check the bits
* @param mask[in] Bits to select out of the target address
* @returns The value `((*address & mask) == mask)`.
*/
#define SECURE_BITS_CHECK(address, mask) \
UVISOR_BITS_CHECK(main, UVISOR_RGW_SHARED, address, mask)
/** Set the selected bits to 1 at the target address.
*
* Equivalent to: `*address |= mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_SET(address, mask) \
UVISOR_BITS_SET(main, UVISOR_RGW_SHARED, address, mask)
/** Clear the selected bits at the target address.
*
* Equivalent to: `*address &= ~mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_CLEAR(address, mask) \
UVISOR_BITS_CLEAR(main, UVISOR_RGW_SHARED, address, mask)
/** Set the selected bits at the target address to the given value.
*
* Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @param value[in] Value to write at the address location. Note: The value
* must be already shifted to the correct bit position
*/
#define SECURE_BITS_SET_VALUE(address, mask, value) \
UVISOR_BITS_SET_VALUE(main, UVISOR_RGW_SHARED, address, mask, value)
/** Toggle the selected bits at the target address.
*
* Equivalent to: `*address ^= mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_TOGGLE(address, mask) \
UVISOR_BITS_TOGGLE(main, UVISOR_RGW_SHARED, address, mask)
#else
/* Insecure fallback implementation. */
/** Set the value at the target address.
*
* Equivalent to: `*address = value`.
* @param address[in] Target address
* @param value[in] Value to write at the address location.
*/
#define SECURE_WRITE(address, value) \
*(address) = (value)
/** Get the value at the target address.
*
* @param address[in] Target address
* @returns The value `*address`.
*/
#define SECURE_READ(address) \
(*(address))
/** Get the selected bits at the target address.
*
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @returns The value `*address & mask`.
*/
#define SECURE_BITS_GET(address, mask) \
(*(address) & (mask))
/** Check the selected bits at the target address.
*
* @param address[in] Address at which to check the bits
* @param mask[in] Bits to select out of the target address
* @returns The value `((*address & mask) == mask)`.
*/
#define SECURE_BITS_CHECK(address, mask) \
((*(address) & (mask)) == (mask))
/** Set the selected bits to 1 at the target address.
*
* Equivalent to: `*address |= mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_SET(address, mask) \
*(address) |= (mask)
/** Clear the selected bits at the target address.
*
* Equivalent to: `*address &= ~mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_CLEAR(address, mask) \
*(address) &= ~(mask)
/** Set the selected bits at the target address to the given value.
*
* Equivalent to: `*address = (*address & ~mask) | (value & mask)`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
* @param value[in] Value to write at the address location. Note: The value
* must be already shifted to the correct bit position
*/
#define SECURE_BITS_SET_VALUE(address, mask, value) \
*(address) = (*(address) & ~(mask)) | ((value) & (mask))
/** Toggle the selected bits at the target address.
*
* Equivalent to: `*address ^= mask`.
* @param address[in] Target address
* @param mask[in] Bits to select out of the target address
*/
#define SECURE_BITS_TOGGLE(address, mask) \
*(address) ^= (mask)
#endif
#endif /* __CORE_CM_SECURE_ACCESS_H */

173
hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.c
View File

@ -68,30 +68,30 @@
#define MCG_S_CLKST_VAL ((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
#define MCG_S_IREFST_VAL ((MCG->S & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
#define MCG_S_PLLST_VAL ((MCG->S & MCG_S_PLLST_MASK) >> MCG_S_PLLST_SHIFT)
#define MCG_C1_FRDIV_VAL ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
#define MCG_C2_LP_VAL ((MCG->C2 & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
#define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
#define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
#define MCG_C1_FRDIV_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
#define MCG_C2_LP_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
#define MCG_C2_RANGE_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
#define MCG_SC_FCRDIV_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
#define MCG_S2_PLLCST_VAL ((MCG->S2 & MCG_S2_PLLCST_MASK) >> MCG_S2_PLLCST_SHIFT)
#define MCG_C7_OSCSEL_VAL ((MCG->C7 & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
#define MCG_C7_OSCSEL_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C7) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
#define MCG_C4_DMX32_VAL ((MCG->C4 & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
#define MCG_C4_DRST_DRS_VAL ((MCG->C4 & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
#define MCG_C7_PLL32KREFSEL_VAL ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT)
#define MCG_C5_PLLREFSEL0_VAL ((MCG->C5 & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
#define MCG_C7_PLL32KREFSEL_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C7) & MCG_C7_PLL32KREFSEL_MASK) >> MCG_C7_PLL32KREFSEL_SHIFT)
#define MCG_C5_PLLREFSEL0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C5) & MCG_C5_PLLREFSEL0_MASK) >> MCG_C5_PLLREFSEL0_SHIFT)
#define MCG_C11_PLLREFSEL1_VAL ((MCG->C11 & MCG_C11_PLLREFSEL1_MASK) >> MCG_C11_PLLREFSEL1_SHIFT)
#define MCG_C11_PRDIV1_VAL ((MCG->C11 & MCG_C11_PRDIV1_MASK) >> MCG_C11_PRDIV1_SHIFT)
#define MCG_C12_VDIV1_VAL ((MCG->C12 & MCG_C12_VDIV1_MASK) >> MCG_C12_VDIV1_SHIFT)
#define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
#define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
#define MCG_C5_PRDIV0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C5) & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
#define MCG_C6_VDIV0_VAL ((__FSL_CLOCK_SECURE_READ(&MCG->C6) & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
#define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
#define SIM_CLKDIV1_OUTDIV1_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
#define SIM_CLKDIV1_OUTDIV2_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
#define SIM_CLKDIV1_OUTDIV3_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
#define SIM_CLKDIV1_OUTDIV4_VAL ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
#define SIM_SOPT1_OSC32KSEL_VAL ((SIM->SOPT1 & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
#define SIM_SOPT2_PLLFLLSEL_VAL ((SIM->SOPT2 & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
#define SIM_CLKDIV1_OUTDIV1_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
#define SIM_CLKDIV1_OUTDIV2_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV2_MASK) >> SIM_CLKDIV1_OUTDIV2_SHIFT)
#define SIM_CLKDIV1_OUTDIV3_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV3_MASK) >> SIM_CLKDIV1_OUTDIV3_SHIFT)
#define SIM_CLKDIV1_OUTDIV4_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->CLKDIV1) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
#define SIM_SOPT1_OSC32KSEL_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->SOPT1) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
#define SIM_SOPT2_PLLFLLSEL_VAL ((__FSL_CLOCK_SECURE_READ(&SIM->SOPT2) & SIM_SOPT2_PLLFLLSEL_MASK) >> SIM_SOPT2_PLLFLLSEL_SHIFT)
/* MCG_S_CLKST definition. */
enum _mcg_clkout_stat
@ -493,7 +493,8 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName)
void CLOCK_SetSimConfig(sim_clock_config_t const *config)
{
SIM->CLKDIV1 = config->clkdiv1;
__FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV1, config->clkdiv1);
CLOCK_SetPllFllSelClock(config->pllFllSel);
CLOCK_SetEr32kClock(config->er32kSrc);
}
@ -506,30 +507,30 @@ bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq)
if (kCLOCK_UsbSrcExt == src)
{
SIM->SOPT2 &= ~SIM_SOPT2_USBSRC_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&SIM->SOPT2, SIM_SOPT2_USBSRC_MASK);
}
else
{
switch (freq)
{
case 120000000U:
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1);
__FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC(1));
break;
case 96000000U:
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0);
__FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(1) | SIM_CLKDIV2_USBFRAC(0));
break;
case 72000000U:
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1);
__FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC(1));
break;
case 48000000U:
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0);
__FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV2, SIM_CLKDIV2_USBDIV(0) | SIM_CLKDIV2_USBFRAC(0));
break;
default:
ret = false;
break;
}
SIM->SOPT2 = ((SIM->SOPT2 & ~(SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK)) | (uint32_t)src);
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_PLLFLLSEL_MASK | SIM_SOPT2_USBSRC_MASK, (uint32_t)src);
}
CLOCK_EnableClock(kCLOCK_Usbfs0);
@ -576,7 +577,7 @@ uint32_t CLOCK_GetFllFreq(void)
uint32_t freq;
/* If FLL is not enabled currently, then return 0U. */
if ((MCG->C2 & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK))
if ((__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_LP_MASK) || (MCG->S & MCG_S_PLLST_MASK))
{
return 0U;
}
@ -597,7 +598,7 @@ uint32_t CLOCK_GetFllFreq(void)
uint32_t CLOCK_GetInternalRefClkFreq(void)
{
/* If MCGIRCLK is gated. */
if (!(MCG->C1 & MCG_C1_IRCLKEN_MASK))
if (!(__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_IRCLKEN_MASK))
{
return 0U;
}
@ -661,10 +662,10 @@ status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel)
needDelay = false;
}
MCG->C7 = (MCG->C7 & ~MCG_C7_OSCSEL_MASK) | MCG_C7_OSCSEL(oscsel);
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C7, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(oscsel));
if (kMCG_OscselOsc == oscsel)
{
if (MCG->C2 & MCG_C2_EREFS_MASK)
if (__FSL_CLOCK_SECURE_READ(&MCG->C2) & MCG_C2_EREFS_MASK)
{
while (!(MCG->S & MCG_S_OSCINIT0_MASK))
{
@ -707,20 +708,20 @@ status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs,
if (fcrdiv != curFcrdiv)
{
/* If fast IRC is in use currently, change to slow IRC. */
if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (MCG->C1 & MCG_C1_IRCLKEN_MASK)))
if ((kMCG_IrcFast == curIrcs) && ((mcgOutClkState == kMCG_ClkOutStatInt) || (__FSL_CLOCK_SECURE_READ(&MCG->C1) & MCG_C1_IRCLKEN_MASK)))
{
MCG->C2 = ((MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(kMCG_IrcSlow)));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, MCG_C2_IRCS_MASK, MCG_C2_IRCS(kMCG_IrcSlow));
while (MCG_S_IRCST_VAL != kMCG_IrcSlow)
{
}
}
/* Update FCRDIV. */
MCG->SC = (MCG->SC & ~(MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK)) | MCG_SC_FCRDIV(fcrdiv);
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->SC, MCG_SC_FCRDIV_MASK | MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK, MCG_SC_FCRDIV(fcrdiv));
}
/* Set internal reference clock selection. */
MCG->C2 = (MCG->C2 & ~MCG_C2_IRCS_MASK) | (MCG_C2_IRCS(ircs));
MCG->C1 = (MCG->C1 & ~(MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK)) | (uint8_t)enableMode;
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, MCG_C2_IRCS_MASK, MCG_C2_IRCS(ircs));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK, (uint8_t)enableMode);
/* If MCGIRCLK is used, need to wait for MCG_S_IRCST. */
if ((mcgOutClkState == kMCG_ClkOutStatInt) || (enableMode & kMCG_IrclkEnable))
@ -837,12 +838,12 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config)
uint8_t mcg_c5 = 0U;
mcg_c5 |= MCG_C5_PRDIV0(config->prdiv);
MCG->C5 = mcg_c5; /* Disable the PLL first. */
__FSL_CLOCK_SECURE_WRITE(&MCG->C5, mcg_c5); /* Disable the PLL first. */
MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv);
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C6, MCG_C6_VDIV0_MASK, MCG_C6_VDIV0(config->vdiv));
/* Set enable mode. */
MCG->C5 |= ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode);
__FSL_CLOCK_SECURE_BITS_SET(&MCG->C5, ((uint32_t)kMCG_PllEnableIndependent | (uint32_t)config->enableMode));
/* Wait for PLL lock. */
while (!(MCG->S & MCG_S_LOCK0_MASK))
@ -857,25 +858,25 @@ void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode)
if (kMCG_MonitorNone == mode)
{
MCG->C6 &= ~MCG_C6_CME0_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_CME0_MASK);
}
else
{
if (kMCG_MonitorInt == mode)
{
MCG->C2 &= ~MCG_C2_LOCRE0_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LOCRE0_MASK);
}
else
{
MCG->C2 |= MCG_C2_LOCRE0_MASK;
__FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LOCRE0_MASK);
}
MCG->C6 |= MCG_C6_CME0_MASK;
__FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_CME0_MASK);
}
}
void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
{
uint8_t mcg_c8 = MCG->C8;
uint8_t mcg_c8 = __FSL_CLOCK_SECURE_READ(&MCG->C8);
mcg_c8 &= ~(MCG_C8_CME1_MASK | MCG_C8_LOCRE1_MASK);
@ -887,7 +888,7 @@ void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode)
}
mcg_c8 |= MCG_C8_CME1_MASK;
}
MCG->C8 = mcg_c8;
__FSL_CLOCK_SECURE_WRITE(&MCG->C8, mcg_c8);
}
void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
@ -899,11 +900,11 @@ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
if (kMCG_MonitorNone == mode)
{
MCG->C6 &= ~MCG_C6_LOLIE0_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_LOLIE0_MASK);
}
else
{
mcg_c8 = MCG->C8;
mcg_c8 = __FSL_CLOCK_SECURE_READ(&MCG->C8);
mcg_c8 &= ~MCG_C8_LOCS1_MASK;
@ -915,8 +916,8 @@ void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode)
{
mcg_c8 |= MCG_C8_LOLRE_MASK;
}
MCG->C8 = mcg_c8;
MCG->C6 |= MCG_C6_LOLIE0_MASK;
__FSL_CLOCK_SECURE_WRITE(&MCG->C8, mcg_c8);
__FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_LOLIE0_MASK);
}
}
@ -925,7 +926,7 @@ uint32_t CLOCK_GetStatusFlags(void)
uint32_t ret = 0U;
uint8_t mcg_s = MCG->S;
if (MCG->SC & MCG_SC_LOCS0_MASK)
if (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_LOCS0_MASK)
{
ret |= kMCG_Osc0LostFlag;
}
@ -933,7 +934,7 @@ uint32_t CLOCK_GetStatusFlags(void)
{
ret |= kMCG_Osc0InitFlag;
}
if (MCG->C8 & MCG_C8_LOCS1_MASK)
if (__FSL_CLOCK_SECURE_READ(&MCG->C8) & MCG_C8_LOCS1_MASK)
{
ret |= kMCG_RtcOscLostFlag;
}
@ -958,8 +959,8 @@ void CLOCK_ClearStatusFlags(uint32_t mask)
}
if (mask & kMCG_RtcOscLostFlag)
{
reg = MCG->C8;
MCG->C8 = reg;
reg = __FSL_CLOCK_SECURE_READ(&MCG->C8);
__FSL_CLOCK_SECURE_WRITE(&MCG->C8, reg);
}
if (mask & kMCG_Pll0LostFlag)
{
@ -974,7 +975,7 @@ void CLOCK_InitOsc0(osc_config_t const *config)
OSC_SetCapLoad(OSC0, config->capLoad);
OSC_SetExtRefClkConfig(OSC0, &config->oscerConfig);
MCG->C2 = ((MCG->C2 & ~OSC_MODE_MASK) | MCG_C2_RANGE(range) | (uint8_t)config->workMode);
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C2, OSC_MODE_MASK, MCG_C2_RANGE(range) | (uint8_t)config->workMode);
if ((kOSC_ModeExt != config->workMode) && (OSC0->CR & OSC_CR_ERCLKEN_MASK))
{
@ -988,7 +989,7 @@ void CLOCK_InitOsc0(osc_config_t const *config)
void CLOCK_DeinitOsc0(void)
{
OSC0->CR = 0U;
MCG->C2 &= ~OSC_MODE_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, OSC_MODE_MASK);
}
status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms)
@ -1035,21 +1036,21 @@ status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_
MCG->ATCVL = (uint8_t)actv;
MCG->ATCVH = (uint8_t)(actv >> 8U);
mcg_sc = MCG->SC;
mcg_sc = __FSL_CLOCK_SECURE_READ(&MCG->SC);
mcg_sc &= ~(MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK);
mcg_sc |= (MCG_SC_ATMF_MASK | MCG_SC_ATMS(atms));
MCG->SC = (mcg_sc | MCG_SC_ATME_MASK);
__FSL_CLOCK_SECURE_WRITE(&MCG->SC, (mcg_sc | MCG_SC_ATME_MASK));
/* Wait for finished. */
while (MCG->SC & MCG_SC_ATME_MASK)
while (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_ATME_MASK)
{
}
/* Error occurs? */
if (MCG->SC & MCG_SC_ATMF_MASK)
if (__FSL_CLOCK_SECURE_READ(&MCG->SC) & MCG_SC_ATMF_MASK)
{
/* Clear the failed flag. */
MCG->SC = mcg_sc;
__FSL_CLOCK_SECURE_WRITE(&MCG->SC, mcg_sc);
return kStatus_MCG_AtmHardwareFail;
}
@ -1196,7 +1197,7 @@ status_t CLOCK_SetFeiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
/* Set CLKS and IREFS. */
MCG->C1 =
((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
((__FSL_CLOCK_SECURE_READ(&MCG->C1) & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK))) | (MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
| MCG_C1_IREFS(kMCG_FllSrcInternal)); /* IREFS = 1 */
/* Wait and check status. */
@ -1255,7 +1256,7 @@ status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void
}
/* Set CLKS and IREFS. */
MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK,
(MCG_C1_CLKS(kMCG_ClkOutSrcOut) /* CLKS = 0 */
| MCG_C1_FRDIV(frdiv) /* FRDIV */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
@ -1312,7 +1313,7 @@ status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
mcg_c4 = MCG->C4;
MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */
/*
Errata: ERR007993
@ -1328,9 +1329,9 @@ status_t CLOCK_SetFbiMode(mcg_drs_t drs, void (*fllStableDelay)(void))
}
/* Set CLKS and IREFS. */
MCG->C1 =
((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */
| MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK,
(MCG_C1_CLKS(kMCG_ClkOutSrcInternal) /* CLKS = 1 */
| MCG_C1_IREFS(kMCG_FllSrcInternal))); /* IREFS = 1 */
/* Wait and check status. */
while (kMCG_FllSrcInternal != MCG_S_IREFST_VAL)
@ -1373,13 +1374,13 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void
#endif
/* Change to FLL mode. */
MCG->C6 &= ~MCG_C6_PLLS_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK);
while (MCG->S & MCG_S_PLLST_MASK)
{
}
/* Set LP bit to enable the FLL */
MCG->C2 &= ~MCG_C2_LP_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
mcg_c4 = MCG->C4;
@ -1397,7 +1398,7 @@ status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void
}
/* Set CLKS and IREFS. */
MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK)) |
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK,
(MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_FRDIV(frdiv) /* FRDIV = frdiv */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
@ -1440,7 +1441,7 @@ status_t CLOCK_SetBlpiMode(void)
#endif /* MCG_CONFIG_CHECK_PARAM */
/* Set LP. */
MCG->C2 |= MCG_C2_LP_MASK;
__FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
return kStatus_Success;
}
@ -1455,7 +1456,7 @@ status_t CLOCK_SetBlpeMode(void)
#endif
/* Set LP bit to enter BLPE mode. */
MCG->C2 |= MCG_C2_LP_MASK;
__FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
return kStatus_Success;
}
@ -1466,10 +1467,10 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co
This function is designed to change MCG to PBE mode from PEE/BLPE/FBE,
but with this workflow, the source mode could be all modes except PEI/PBI.
*/
MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */
/* Change to use external clock first. */
MCG->C1 = ((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
/* Wait for CLKST clock status bits to show clock source is ext ref clk */
while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
@ -1478,7 +1479,7 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co
}
/* Disable PLL first, then configure PLL. */
MCG->C6 &= ~MCG_C6_PLLS_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK);
while (MCG->S & MCG_S_PLLST_MASK)
{
}
@ -1489,7 +1490,7 @@ status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *co
}
/* Change to PLL mode. */
MCG->C6 |= MCG_C6_PLLS_MASK;
__FSL_CLOCK_SECURE_BITS_SET(&MCG->C6, MCG_C6_PLLS_MASK);
while (!(MCG->S & MCG_S_PLLST_MASK))
{
}
@ -1508,7 +1509,7 @@ status_t CLOCK_SetPeeMode(void)
#endif
/* Change to use PLL/FLL output clock first. */
MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcOut));
/* Wait for clock status bits to update */
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
@ -1528,15 +1529,15 @@ status_t CLOCK_ExternalModeToFbeModeQuick(void)
#endif /* MCG_CONFIG_CHECK_PARAM */
/* Disable low power */
MCG->C2 &= ~MCG_C2_LP_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
{
}
/* Disable PLL. */
MCG->C6 &= ~MCG_C6_PLLS_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C6, MCG_C6_PLLS_MASK);
while (MCG->S & MCG_S_PLLST_MASK)
{
}
@ -1554,9 +1555,9 @@ status_t CLOCK_InternalModeToFbiModeQuick(void)
#endif
/* Disable low power */
MCG->C2 &= ~MCG_C2_LP_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
{
}
@ -1583,13 +1584,13 @@ status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEn
CLOCK_SetInternalRefClkConfig(ircEnableMode, ircs, fcrdiv);
/* If reset mode is not BLPI, first enter FBI mode. */
MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcInternal);
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcInternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatInt)
{
}
/* Enter BLPI mode. */
MCG->C2 |= MCG_C2_LP_MASK;
__FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
return kStatus_Success;
}
@ -1599,9 +1600,9 @@ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
CLOCK_SetExternalRefClkConfig(oscsel);
/* Set to FBE mode. */
MCG->C1 =
((MCG->C1 & ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK)) | (MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK,
(MCG_C1_CLKS(kMCG_ClkOutSrcExternal) /* CLKS = 2 */
| MCG_C1_IREFS(kMCG_FllSrcExternal))); /* IREFS = 0 */
/* Wait for MCG_S[CLKST] and MCG_S[IREFST]. */
while ((MCG->S & (MCG_S_IREFST_MASK | MCG_S_CLKST_MASK)) !=
@ -1610,7 +1611,7 @@ status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel)
}
/* In FBE now, start to enter BLPE. */
MCG->C2 |= MCG_C2_LP_MASK;
__FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
return kStatus_Success;
}
@ -1624,7 +1625,7 @@ status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mc
CLOCK_SetPbeMode(pllcs, config);
/* Change to use PLL output clock. */
MCG->C1 = (MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcOut);
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcOut));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatPll)
{
}
@ -1684,7 +1685,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
/* Re-configure MCGIRCLK, if MCGIRCLK is used as system clock source, then change to FEI/PEI first. */
if (MCG_S_CLKST_VAL == kMCG_ClkOutStatInt)
{
MCG->C2 &= ~MCG_C2_LP_MASK; /* Disable lowpower. */
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK); /* Disable lowpower. */
{
CLOCK_SetFeiMode(config->drs, CLOCK_FllStableDelay);
@ -1730,7 +1731,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
}
else
{
MCG->C1 = ((MCG->C1 & ~MCG_C1_CLKS_MASK) | MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&MCG->C1, MCG_C1_CLKS_MASK, MCG_C1_CLKS(kMCG_ClkOutSrcExternal));
while (MCG_S_CLKST_VAL != kMCG_ClkOutStatExt)
{
}
@ -1754,7 +1755,7 @@ status_t CLOCK_SetMcgConfig(const mcg_config_t *config)
}
else
{
MCG->C5 &= ~(uint32_t)kMCG_PllEnableIndependent;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C5, (uint32_t)kMCG_PllEnableIndependent);
}
return kStatus_Success;
}

79
hal/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_clock.h
View File

@ -31,11 +31,55 @@
#ifndef _FSL_CLOCK_H_
#define _FSL_CLOCK_H_
#include "core_cmSecureAccess.h"
#include "fsl_device_registers.h"
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#ifdef FEATURE_UVISOR
/* We cannot use the register gateway to secure this access,
* since some accesses use dynamically computed addresses and
* values, which are not supported by the register gateway.
* Therefore, these accesses are implemented using the uVisor
* secure access.
*/
#define __FSL_CLOCK_SECURE_WRITE(addr, val) \
ADDRESS_WRITE(*addr, addr, val)
#define __FSL_CLOCK_SECURE_READ(addr) \
ADDRESS_READ(*addr, addr)
#define __FSL_CLOCK_SECURE_BITS_SET(addr, mask) \
__FSL_CLOCK_SECURE_WRITE(addr, __FSL_CLOCK_SECURE_READ(addr) | (mask))
#define __FSL_CLOCK_SECURE_BITS_CLEAR(addr, mask) \
__FSL_CLOCK_SECURE_WRITE(addr, __FSL_CLOCK_SECURE_READ(addr) & ~(mask))
#define __FSL_CLOCK_SECURE_BITS_SET_VALUE(addr, mask, val) \
__FSL_CLOCK_SECURE_WRITE(addr, (__FSL_CLOCK_SECURE_READ(addr) & ~(mask)) | ((val) & (mask)))
#else
/* Fallback implementation. */
#define __FSL_CLOCK_SECURE_WRITE(addr, val) \
SECURE_WRITE(addr, val)
#define __FSL_CLOCK_SECURE_READ(addr) \
SECURE_READ(addr)
#define __FSL_CLOCK_SECURE_BITS_SET(addr, mask) \
SECURE_BITS_SET(addr, mask)
#define __FSL_CLOCK_SECURE_BITS_CLEAR(addr, mask) \
SECURE_BITS_CLEAR(addr, mask)
#define __FSL_CLOCK_SECURE_BITS_SET_VALUE(addr, mask, val) \
SECURE_BITS_SET_VALUE(addr, mask, val)
#endif
/*! @addtogroup clock */
/*! @{ */
@ -675,7 +719,7 @@ static inline void CLOCK_SetXtal32Freq(uint32_t freq)
static inline void CLOCK_EnableClock(clock_ip_name_t name)
{
uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
(*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
__FSL_CLOCK_SECURE_BITS_SET((uint32_t *) regAddr, (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)));
}
/*!
@ -686,7 +730,7 @@ static inline void CLOCK_EnableClock(clock_ip_name_t name)
static inline void CLOCK_DisableClock(clock_ip_name_t name)
{
uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
(*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
__FSL_CLOCK_SECURE_BITS_CLEAR((uint32_t *) regAddr, (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name)));
}
/*!
@ -696,7 +740,7 @@ static inline void CLOCK_DisableClock(clock_ip_name_t name)
*/
static inline void CLOCK_SetEr32kClock(uint32_t src)
{
SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT1, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(src));
}
/*!
@ -706,7 +750,7 @@ static inline void CLOCK_SetEr32kClock(uint32_t src)
*/
static inline void CLOCK_SetSdhc0Clock(uint32_t src)
{
SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_SDHCSRC_MASK, SIM_SOPT2_SDHCSRC(src));
}
/*!
@ -716,7 +760,7 @@ static inline void CLOCK_SetSdhc0Clock(uint32_t src)
*/
static inline void CLOCK_SetEnetTime0Clock(uint32_t src)
{
SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TIMESRC_MASK) | SIM_SOPT2_TIMESRC(src));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_TIMESRC_MASK, SIM_SOPT2_TIMESRC(src));
}
/*!
@ -726,7 +770,7 @@ static inline void CLOCK_SetEnetTime0Clock(uint32_t src)
*/
static inline void CLOCK_SetRmii0Clock(uint32_t src)
{
SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) | SIM_SOPT2_RMIISRC(src));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_RMIISRC_MASK, SIM_SOPT2_RMIISRC(src));
}
/*!
@ -736,7 +780,7 @@ static inline void CLOCK_SetRmii0Clock(uint32_t src)
*/
static inline void CLOCK_SetTraceClock(uint32_t src)
{
SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_TRACECLKSEL_MASK, SIM_SOPT2_TRACECLKSEL(src));
}
/*!
@ -746,7 +790,7 @@ static inline void CLOCK_SetTraceClock(uint32_t src)
*/
static inline void CLOCK_SetPllFllSelClock(uint32_t src)
{
SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_PLLFLLSEL_MASK, SIM_SOPT2_PLLFLLSEL(src));
}
/*!
@ -756,7 +800,7 @@ static inline void CLOCK_SetPllFllSelClock(uint32_t src)
*/
static inline void CLOCK_SetClkOutClock(uint32_t src)
{
SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(src));
}
/*!
@ -766,7 +810,7 @@ static inline void CLOCK_SetClkOutClock(uint32_t src)
*/
static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
{
SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
__FSL_CLOCK_SECURE_BITS_SET_VALUE(&SIM->SOPT2, SIM_SOPT2_RTCCLKOUTSEL_MASK, SIM_SOPT2_RTCCLKOUTSEL(src));
}
/*! @brief Enable USB FS clock.
@ -802,8 +846,11 @@ static inline void CLOCK_DisableUsbfs0Clock(void)
*/
static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
{
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
SIM_CLKDIV1_OUTDIV4(outdiv4);
__FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV1,
SIM_CLKDIV1_OUTDIV1(outdiv1) |
SIM_CLKDIV1_OUTDIV2(outdiv2) |
SIM_CLKDIV1_OUTDIV3(outdiv3) |
SIM_CLKDIV1_OUTDIV4(outdiv4));
}
/*!
@ -896,7 +943,7 @@ void CLOCK_SetSimConfig(sim_clock_config_t const *config);
*/
static inline void CLOCK_SetSimSafeDivs(void)
{
SIM->CLKDIV1 = 0x01240000U;
__FSL_CLOCK_SECURE_WRITE(&SIM->CLKDIV1, 0x01240000UL);
}
/*! @name MCG frequency functions. */
@ -972,11 +1019,11 @@ static inline void CLOCK_SetLowPowerEnable(bool enable)
{
if (enable)
{
MCG->C2 |= MCG_C2_LP_MASK;
__FSL_CLOCK_SECURE_BITS_SET(&MCG->C2, MCG_C2_LP_MASK);
}
else
{
MCG->C2 &= ~MCG_C2_LP_MASK;
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C2, MCG_C2_LP_MASK);
}
}
@ -1031,7 +1078,7 @@ void CLOCK_EnablePll0(mcg_pll_config_t const *config);
*/
static inline void CLOCK_DisablePll0(void)
{
MCG->C5 &= ~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK);
__FSL_CLOCK_SECURE_BITS_CLEAR(&MCG->C5, MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK);
}
/*!