diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f4xx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f4xx.h index d3beea922e..ffedae725a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f4xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f4xx.h @@ -8,8 +8,8 @@ * is using in the C source code, usually in main.c. This file contains: * - Configuration section that allows to select: * - The STM32F4xx device used in the target application - * - To use or not the peripheral’s drivers in application code(i.e. - * code will be based on direct access to peripheral’s registers + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers * rather than drivers API), this option is controlled by * "#define USE_HAL_DRIVER" * diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c index efb64e596a..23fb46ed0a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c @@ -470,7 +470,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) } #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ - /* Set the key size(This bit field is don’t care in the DES or TDES modes) data type and Algorithm */ + /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */ #if defined (CRYP) MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, @@ -589,7 +589,7 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; - /* Set the key size(This bit field is don’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/ + /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/ #if defined (CRYP) MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c index 43b238a13b..b3af317f02 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c @@ -177,7 +177,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Select final phase */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - /*ALGODIR bit must be set to ‘0’.*/ + /*ALGODIR bit must be set to '0'.*/ hcryp->Instance->CR &= ~CRYP_CR_ALGODIR; /* Enable the CRYP peripheral */ @@ -395,7 +395,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u /* Disable CRYP to start the final phase */ __HAL_CRYP_DISABLE(hcryp); - /* Select final phase & ALGODIR bit must be set to ‘0’. */ + /* Select final phase & ALGODIR bit must be set to '0'. */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT); /* Enable the CRYP peripheral */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c index d1e2fa071e..e853ba2d11 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c @@ -40,7 +40,7 @@ (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 42MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 97.52µs + max timeout before reset: approximately 97.52us (++) Counter max (T[5;0] = 0x3F) at 42MHz (PCLK1) with prescaler dividing by 8: max timeout before reset: approximately 49.93ms