mirror of https://github.com/ARMmbed/mbed-os.git
NUCLEO_F401RE: Change system clock to 84 MHz using HSI + PLL
Update also HSE_VALUE and SPI prescaler value.pull/215/head
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f285e44f05
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bb57ddc0c3
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@ -99,7 +99,8 @@
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* (when HSE is used as system clock source, directly or through the PLL).
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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/* MBED: Put here the value of the Xtal you use */
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#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSE_STARTUP_TIMEOUT)
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@ -64,6 +64,7 @@
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*/
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#include "stm32f4xx_hal.h"
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#include "error.h" /* [ADDED FOR MBED] */
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/**
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* @}
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@ -113,7 +114,7 @@
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 16000000;
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uint32_t SystemCoreClock = 84000000; /* [CHANGED FOR MBED] */
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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@ -124,6 +125,9 @@
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* @{
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*/
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/* [ADDED FOR MBED] */
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static void SystemClock_Config(void);
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/**
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* @}
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*/
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@ -171,21 +175,9 @@ void SystemInit(void)
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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// [ADDED FOR MBED]
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/* [ADDED FOR MBED] */
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HAL_Init();
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 16 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 16 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 8 MHz for the SPI
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
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}
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// [ADDED FOR MBED]
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void SysTick_Handler(void)
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{
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HAL_IncTick();
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SystemClock_Config();
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}
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/**
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@ -272,6 +264,64 @@ void SystemCoreClockUpdate(void)
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SystemCoreClock >>= tmp;
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}
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/* [ADDED FOR MBED]
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Configure the System clock to 84 MHz (max value) using the internal HSI 16 MHz clock */
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static void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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/* The voltage scaling allows optimizing the power consumption when the device is
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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__PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
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/* Enable HSI Oscillator and activate PLL with HSI as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
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RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
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RCC_OscInitStruct.HSICalibrationValue = 16;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 16;
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RCC_OscInitStruct.PLL.PLLN = 336;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
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RCC_OscInitStruct.PLL.PLLQ = 7;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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error("System clock initialization failed.");
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}
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz (SPI1 clock...)
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
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{
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error("System clock initialization failed.");
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}
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/* Update the SystemCoreClock variable
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- Not needed because the variable is already set on top of this file.
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- Warning: this function call is removed by the compiler with -O3/-Otime options. */
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//SystemCoreClockUpdate();
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/* Output SYSCLK on MCO2 pin(PC9) for debugging purpose */
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//HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 84 MHz / 4 = 21 MHz
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}
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/* [ADDED FOR MBED]
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Used for the different timeouts in the HAL */
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void SysTick_Handler(void)
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{
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HAL_IncTick();
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}
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/**
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* @}
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*/
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@ -112,7 +112,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
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obj->bits = SPI_DATASIZE_8BIT;
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obj->cpol = SPI_POLARITY_LOW;
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obj->cpha = SPI_PHASE_1EDGE;
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obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 1MHz (with HSI=16MHz and APB2CLKDivider=2)
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obj->br_presc = SPI_BAUDRATEPRESCALER_256;
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if (ssel == NC) { // Master
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obj->mode = SPI_MODE_MASTER;
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@ -173,26 +173,31 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
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}
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void spi_frequency(spi_t *obj, int hz) {
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// Get SPI clock frequency
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uint32_t PCLK = SystemCoreClock >> 1;
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// Choose the baud rate divisor (between 2 and 256)
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uint32_t divisor = PCLK / hz;
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// Find the nearest power-of-2
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divisor = (divisor > 0 ? divisor-1 : 0);
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divisor |= divisor >> 1;
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divisor |= divisor >> 2;
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divisor |= divisor >> 4;
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divisor |= divisor >> 8;
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divisor |= divisor >> 16;
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divisor++;
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uint32_t baud_rate = __builtin_ffs(divisor) - 2;
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// Save new value
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obj->br_presc = ((baud_rate > 7) ? (7 << 3) : (baud_rate << 3));
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// Note: The frequencies are obtained with SPI1 clock = 84 MHz (APB2 clock)
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if (hz < 500000) {
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obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 331 kHz
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}
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else if ((hz >= 500000) && (hz < 1000000)) {
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obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 663 kHz
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}
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else if ((hz >= 1000000) && (hz < 2000000)) {
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obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 1.3 MHz
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}
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else if ((hz >= 2000000) && (hz < 5000000)) {
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obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 2.65 MHz
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}
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else if ((hz >= 5000000) && (hz < 10000000)) {
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obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 5.3 MHz
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}
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else if ((hz >= 10000000) && (hz < 20000000)) {
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obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 10.6 MHz
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}
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else if ((hz >= 20000000) && (hz < 40000000)) {
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obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 21.2 MHz
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}
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else { // >= 40000000
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obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 42 MHz
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}
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init_spi(obj);
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}
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