From bb25e8660dfb5f8abd81b810f90ca7b74c1c7fbe Mon Sep 17 00:00:00 2001 From: Deepika Date: Fri, 18 Jan 2019 17:18:43 -0600 Subject: [PATCH] Reverted 4 CMSIS/RTX commits for Assembly files 1. Revert "CMSIS/RTX: __FPU_USED to be set based on HW FPU support" This reverts commit b4f5bed7e75c21927c954a50d40422b81a1de5a0. 2. Revert "CMSIS/RTX: Update Armv8M IAR 8.x assembly files - add END" This reverts commit b228cd9db0b7ed79d99f1d9be15d512791f367cc. 3. Revert "CMSIS/RTX: Pre-processor defines used for assembly" This reverts commit 287121ffdc4c9c19f9ce8872e4edd941862daca1. 4. Revert "CMSIS/RTX: Patch RTX so irq_cm4f.s files work with no FPU targets" This reverts commit cc2e0517e1c6440abf88f2815b8e1501a55cdd4d. --- .../Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S | 6 +++--- .../Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S | 12 +++++++----- .../TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S | 7 ------- .../Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S | 4 ++-- .../Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S | 8 ++++---- .../TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S | 7 ------- .../TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S | 2 -- .../TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S | 2 -- .../TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S | 7 ------- 9 files changed, 16 insertions(+), 39 deletions(-) diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S index 4caf963634..5a0d1f081b 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M23/irq_armv8mbl.S @@ -24,9 +24,9 @@ ; */ -#ifndef DOMAIN_NS -DOMAIN_NS EQU 0 -#endif + IF :LNOT::DEF:DOMAIN_NS +DOMAIN_NS EQU 0 + ENDIF I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SM_OFS EQU 48 ; TCB.stack_mem offset diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S index 75a068349c..b0c88f956c 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S @@ -24,13 +24,15 @@ ; */ -#ifndef DOMAIN_NS -DOMAIN_NS EQU 0 -#endif + IF :LNOT::DEF:DOMAIN_NS +DOMAIN_NS EQU 0 + ENDIF -#ifndef __FPU_USED + IF ({FPU}="FPv5-SP") || ({FPU}="FPv5_D16") +__FPU_USED EQU 1 + ELSE __FPU_USED EQU 0 -#endif + ENDIF I_T_RUN_OFS EQU 20 ; osRtxInfo.thread.run offset TCB_SM_OFS EQU 48 ; TCB.stack_mem offset diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S index 803c7c378c..7d405b7e4e 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -74,22 +74,17 @@ SVC_Context CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted TST LR,#0x10 ; Check if extended stack frame BNE SVC_ContextSwitch -#ifdef __FPU_PRESENT LDR R1,=0xE000EF34 ; FPCCR Address LDR R0,[R1] ; Load FPCCR BIC R0,R0,#1 ; Clear LSPACT (Lazy state) STR R0,[R1] ; Store FPCCR B SVC_ContextSwitch -#endif SVC_ContextSave STMDB R12!,{R4-R11} ; Save R4..R11 -#ifdef __FPU_PRESENT TST LR,#0x10 ; Check if extended stack frame IT EQ VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 -#endif - STR R12,[R1,#TCB_SP_OFS] ; Store SP STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information @@ -108,11 +103,9 @@ SVC_ContextRestore LDR R0,[R2,#TCB_SP_OFS] ; Load SP ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN -#ifdef __FPU_PRESENT TST LR,#0x10 ; Check if extended stack frame IT EQ VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 -#endif LDMIA R0!,{R4-R11} ; Restore R4..R11 MSR PSP,R0 ; Set PSP diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S index bbd071f51a..56b486d5ce 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M23/irq_armv8mbl.S @@ -27,9 +27,9 @@ .file "irq_armv8mbl.S" .syntax unified -#ifndef DOMAIN_NS + .ifndef DOMAIN_NS .equ DOMAIN_NS, 0 -#endif + .endif .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset .equ TCB_SM_OFS, 48 // TCB.stack_mem offset diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S index a727728202..c9c497c02c 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S @@ -27,13 +27,13 @@ .file "irq_armv8mml.S" .syntax unified -#ifndef DOMAIN_NS + .ifndef DOMAIN_NS .equ DOMAIN_NS, 0 -#endif + .endif -#ifndef __FPU_USED + .ifndef __FPU_USED .equ __FPU_USED, 0 -#endif + .endif .equ I_T_RUN_OFS, 20 // osRtxInfo.thread.run offset .equ TCB_SM_OFS, 48 // TCB.stack_mem offset diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S index cd59935afb..568419a33c 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -74,22 +74,17 @@ SVC_Context: CBNZ R1,SVC_ContextSave // Branch if running thread is not deleted TST LR,#0x10 // Check if extended stack frame BNE SVC_ContextSwitch -#ifdef __FPU_PRESENT LDR R1,=0xE000EF34 // FPCCR Address LDR R0,[R1] // Load FPCCR BIC R0,R0,#1 // Clear LSPACT (Lazy state) STR R0,[R1] // Store FPCCR B SVC_ContextSwitch -#endif SVC_ContextSave: STMDB R12!,{R4-R11} // Save R4..R11 -#ifdef __FPU_PRESENT TST LR,#0x10 // Check if extended stack frame IT EQ VSTMDBEQ R12!,{S16-S31} // Save VFP S16.S31 -#endif - STR R12,[R1,#TCB_SP_OFS] // Store SP STRB LR, [R1,#TCB_SF_OFS] // Store stack frame information @@ -101,11 +96,9 @@ SVC_ContextRestore: LDR R0,[R2,#TCB_SP_OFS] // Load SP ORR LR,R1,#0xFFFFFF00 // Set EXC_RETURN -#ifdef __FPU_PRESENT TST LR,#0x10 // Check if extended stack frame IT EQ VLDMIAEQ R0!,{S16-S31} // Restore VFP S16..S31 -#endif LDMIA R0!,{R4-R11} // Restore R4..R11 MSR PSP,R0 // Set PSP diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S index 3249a947a7..ec38438d0c 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M23/irq_armv8mbl_common.S @@ -297,5 +297,3 @@ Sys_ContextRestore2 Sys_ContextExit BX LR ; Exit from handler - - END diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S index 755cde63d4..629bfe93fb 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_M33/irq_armv8mml_common.S @@ -270,5 +270,3 @@ Sys_ContextRestore2 Sys_ContextExit BX LR ; Exit from handler - - END diff --git a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S index 4f8f3d4c8f..5a956481e8 100644 --- a/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S +++ b/rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_RTOS_M4_M7/irq_cm4f.S @@ -74,22 +74,17 @@ SVC_Context CBNZ R1,SVC_ContextSave ; Branch if running thread is not deleted TST LR,#0x10 ; Check if extended stack frame BNE SVC_ContextSwitch -#ifdef __FPU_PRESENT LDR R1,=0xE000EF34 ; FPCCR Address LDR R0,[R1] ; Load FPCCR BIC R0,R0,#1 ; Clear LSPACT (Lazy state) STR R0,[R1] ; Store FPCCR B SVC_ContextSwitch -#endif SVC_ContextSave STMDB R12!,{R4-R11} ; Save R4..R11 -#ifdef __FPU_PRESENT TST LR,#0x10 ; Check if extended stack frame IT EQ VSTMDBEQ R12!,{S16-S31} ; Save VFP S16.S31 -#endif - STR R12,[R1,#TCB_SP_OFS] ; Store SP STRB LR, [R1,#TCB_SF_OFS] ; Store stack frame information @@ -101,11 +96,9 @@ SVC_ContextRestore LDR R0,[R2,#TCB_SP_OFS] ; Load SP ORR LR,R1,#0xFFFFFF00 ; Set EXC_RETURN -#ifdef __FPU_PRESENT TST LR,#0x10 ; Check if extended stack frame IT EQ VLDMIAEQ R0!,{S16-S31} ; Restore VFP S16..S31 -#endif LDMIA R0!,{R4-R11} ; Restore R4..R11 MSR PSP,R0 ; Set PSP