From baf7a121bb0c5194f16ea9fc3303919d588f7ff5 Mon Sep 17 00:00:00 2001 From: Laurent Meunier Date: Thu, 10 Jan 2019 10:27:59 +0100 Subject: [PATCH] NUCLEO_WB55RG: IAR, ARM and GCC linker files alignment Align all scatter BLE shared memory declarations. --- .../TOOLCHAIN_ARM_MICRO/stm32wb55xx.sct | 62 ++++++++++++++----- .../device/TOOLCHAIN_ARM_STD/stm32wb55xx.sct | 58 ++++++++++++----- .../device/TOOLCHAIN_GCC_ARM/stm32wb55xx.ld | 29 +++++++-- .../device/TOOLCHAIN_IAR/stm32wb55xx.icf | 14 +++-- 4 files changed, 122 insertions(+), 41 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_ARM_MICRO/stm32wb55xx.sct b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_ARM_MICRO/stm32wb55xx.sct index f3a3607337..22f1fb61a5 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_ARM_MICRO/stm32wb55xx.sct +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_ARM_MICRO/stm32wb55xx.sct @@ -1,29 +1,49 @@ #! armcc -E +; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; mbed Microcontroller Library -; Copyright (c) 2006-2013 ARM Limited +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. ; -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: ; -; http://www.apache.org/licenses/LICENSE-2.0 +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. ; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + #if !defined(MBED_APP_START) - #define MBED_APP_START 0x08000000 +#define MBED_APP_START 0x08000000 #endif #if !defined(MBED_APP_SIZE) ; 512KB FLASH - #define MBED_APP_SIZE 0x80000 +#define MBED_APP_SIZE 0x80000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define Stack_Size MBED_BOOT_STACK_SIZE + +; 512KB FLASH (0x80000) + 192KB SRAM (0x30000) + Shared mem LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address @@ -32,11 +52,19 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region .ANY (+RO) } - ; SRAM1 192KB (0x30000) ; Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM - RW_IRAM1 (0x20000000+0x13C) (0x30000-0x13C) { ; RW data - .ANY (+RW +ZI) + RW_IRAM1 (0x20000000+0x13C) (0x30000-0x13C-Stack_Size) { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_STACK (0x20000000+0x30000) EMPTY -Stack_Size { ; stack } + ; SRAM2 - Shared memory + RW_IRAM2a 0x20030000 0x00002800 { ; RW data + *(MAPPING_TABLE, +First) + *(MB_MEM1) + } + RW_IRAM2b 0x20038000 0x00005000 { ; RW data + *(MB_MEM2) + } } - diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_ARM_STD/stm32wb55xx.sct b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_ARM_STD/stm32wb55xx.sct index 1d83d584b2..22f1fb61a5 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_ARM_STD/stm32wb55xx.sct +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_ARM_STD/stm32wb55xx.sct @@ -1,20 +1,33 @@ #! armcc -E +; Scatter-Loading Description File ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -; mbed Microcontroller Library -; Copyright (c) 2006-2013 ARM Limited +; Copyright (c) 2015, STMicroelectronics +; All rights reserved. ; -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: ; -; http://www.apache.org/licenses/LICENSE-2.0 +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; 3. Neither the name of STMicroelectronics nor the names of its contributors +; may be used to endorse or promote products derived from this software +; without specific prior written permission. ; -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + #if !defined(MBED_APP_START) #define MBED_APP_START 0x08000000 #endif @@ -24,6 +37,13 @@ #define MBED_APP_SIZE 0x80000 #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +#define Stack_Size MBED_BOOT_STACK_SIZE + +; 512KB FLASH (0x80000) + 192KB SRAM (0x30000) + Shared mem LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address @@ -32,11 +52,19 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region .ANY (+RO) } - ; SRAM1 192KB (0x30000) ; Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM - RW_IRAM1 (0x20000000+0x13C) (0x30000-0x13C) { ; RW data - .ANY (+RW +ZI) + RW_IRAM1 (0x20000000+0x13C) (0x30000-0x13C-Stack_Size) { ; RW data + .ANY (+RW +ZI) + } + ARM_LIB_STACK (0x20000000+0x30000) EMPTY -Stack_Size { ; stack } + ; SRAM2 - Shared memory + RW_IRAM2a 0x20030000 0x00002800 { ; RW data + *(MAPPING_TABLE, +First) + *(MB_MEM1) + } + RW_IRAM2b 0x20038000 0x00005000 { ; RW data + *(MB_MEM2) + } } - diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_GCC_ARM/stm32wb55xx.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_GCC_ARM/stm32wb55xx.ld index 6b22672c40..4e0406384b 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_GCC_ARM/stm32wb55xx.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_GCC_ARM/stm32wb55xx.ld @@ -6,12 +6,20 @@ #define MBED_APP_SIZE 512K #endif +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +STACK_SIZE = MBED_BOOT_STACK_SIZE; + /* Linker script to configure memory regions. */ /* Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM1 (192K) */ MEMORY { FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE RAM1 (rwx) : ORIGIN = 0x2000013C, LENGTH = 192K - 0x13C + RAM2a (rw) : ORIGIN = 0x20030000, LENGTH = 10K + RAM2b (rw) : ORIGIN = 0x20038000, LENGTH = 20K } /* Linker script to place sections and symbol values. Should be used together @@ -93,20 +101,20 @@ SECTIONS *(vtable) *(.data*) - . = ALIGN(4); + . = ALIGN(8); /* preinit data */ PROVIDE_HIDDEN (__preinit_array_start = .); KEEP(*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* init data */ PROVIDE_HIDDEN (__init_array_start = .); KEEP(*(SORT(.init_array.*))) KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); + . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); KEEP(*(SORT(.fini_array.*))) @@ -114,7 +122,7 @@ SECTIONS PROVIDE_HIDDEN (__fini_array_end = .); KEEP(*(.jcr*)) - . = ALIGN(4); + . = ALIGN(8); /* All data end */ __data_end__ = .; _edata = .; @@ -149,11 +157,22 @@ SECTIONS *(.stack*) } > RAM1 + .ble_stby_mem (NOLOAD) : + { + *(MAPPING_TABLE); + *(MB_MEM1); + } >RAM2a + + .ble_shared_no_ret (NOLOAD) : + { + *(MB_MEM2); + } >RAM2b + /* Set stack top to end of RAM1, and stack limit move down by * size of stack_dummy section */ __StackTop = ORIGIN(RAM1) + LENGTH(RAM1); _estack = __StackTop; - __StackLimit = __StackTop - SIZEOF(.stack_dummy); + __StackLimit = __StackTop - STACK_SIZE; PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM1 limit */ diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_IAR/stm32wb55xx.icf b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_IAR/stm32wb55xx.icf index 7f018647e0..d2b7fbed93 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_IAR/stm32wb55xx.icf +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/TOOLCHAIN_IAR/stm32wb55xx.icf @@ -4,7 +4,7 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x80000; } /* [ROM = 512kb = 0x80000] */ define symbol __intvec_start__ = MBED_APP_START; define symbol __region_ROM_start__ = MBED_APP_START; -define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE; +define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; /* [RAM1 = 192kb = 0x30000] */ /* Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM */ @@ -26,8 +26,12 @@ define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__] define region RAM2aRet_SHARED_region = mem:[from __ICFEDIT_region_RAM2aRet_SHARED_start__ to __ICFEDIT_region_RAM2aRet_SHARED_end__]; define region RAM2b_SHARED_region = mem:[from __ICFEDIT_region_RAM2b_SHARED_start__ to __ICFEDIT_region_RAM2b_SHARED_end__]; +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; +} + /* Stack and Heap */ -define symbol __size_cstack__ = 0x8000; +define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE; define symbol __size_heap__ = 0x10000; define block CSTACK with alignment = 8, size = __size_cstack__ { }; define block HEAP with alignment = 8, size = __size_heap__ { }; @@ -36,7 +40,9 @@ define block STACKHEAP with fixed order { block HEAP, block CSTACK }; initialize by copy with packing = zeros { readwrite }; do not initialize { section .noinit, section MAPPING_TABLE, - section MB_MEM1 }; + section MB_MEM1, + section MB_MEM2 + }; place at address mem:__intvec_start__ { readonly section .intvec }; @@ -45,4 +51,4 @@ place in RAM_region { readwrite, block STACKHEAP }; place in RAM2aRet_SHARED_region { first section MAPPING_TABLE}; place in RAM2aRet_SHARED_region { section MB_MEM1}; -place in RAM2b_SHARED_region { section MB_MEM2}; +place in RAM2b_SHARED_region { section MB_MEM2};