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PSOC6: cleanup DEVICE_QSPI mappings 

Note: device_has: "QSPI" is still disabled for TARGET_PSOC6
(QSPI HAL implementation is incomplete).
pull/10692/head
Volodymyr Medvid 2019-07-11 10:20:20 +01:00
parent 2524a67c38
commit bab34cb467
7 changed files with 74 additions and 87 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
targets/TARGET_Cypress/TARGET_PSOC6/PeripheralPins.h
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@ -24,7 +24,7 @@
#include "PeripheralNames.h" #include "PeripheralNames.h"
// //*** I2C *** //*** I2C ***
#if DEVICE_I2C #if DEVICE_I2C
extern const PinMap PinMap_I2C_SDA[]; extern const PinMap PinMap_I2C_SDA[];
extern const PinMap PinMap_I2C_SCL[]; extern const PinMap PinMap_I2C_SCL[];
@ -51,13 +51,6 @@ extern const PinMap PinMap_SPI_SCLK[];
extern const PinMap PinMap_SPI_SSEL[]; extern const PinMap PinMap_SPI_SSEL[];
#endif #endif
//*** QSPI ***
#if DEVICE_QSPI
extern const PinMap PinMap_QSPI_SCLK[];
extern const PinMap PinMap_QSPI_DATA[];
extern const PinMap PinMap_QSPI_SSEL[];
#endif
//*** ADC *** //*** ADC ***
#if DEVICE_ANALOGIN #if DEVICE_ANALOGIN
extern const PinMap PinMap_ADC[]; extern const PinMap PinMap_ADC[];
@ -68,6 +61,7 @@ extern const PinMap PinMap_ADC[];
extern const PinMap PinMap_DAC[]; extern const PinMap PinMap_DAC[];
#endif #endif
//*** QSPI ***
#if DEVICE_QSPI #if DEVICE_QSPI
extern const PinMap PinMap_QSPI_SCLK[]; extern const PinMap PinMap_QSPI_SCLK[];
extern const PinMap PinMap_QSPI_SSEL[]; extern const PinMap PinMap_QSPI_SSEL[];

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralNames.h
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@ -108,8 +108,8 @@ typedef enum {
} DACName; } DACName;
typedef enum { typedef enum {
SMIF_0 = (int)SMIF0_BASE, QSPI_0,
} SMIFName; } QSPIName;
#ifdef __cplusplus #ifdef __cplusplus
} }

46
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/PeripheralPins.c
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@ -366,30 +366,28 @@ const PinMap PinMap_DAC[] = {
#endif // DEVICE_ANALOGIN #endif // DEVICE_ANALOGIN
#if DEVICE_QSPI #if DEVICE_QSPI
const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2 const PinMap PinMap_QSPI_SCLK[] = {
{P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)}, {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
{NC, NC, 0} {NC, NC, 0},
}; };
const PinMap PinMap_QSPI_SSEL[] = {
// Ensure that the spi_data pins are defined in the order 0 to 7 {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2 {NC, NC, 0},
{P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0 };
{P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1 const PinMap PinMap_QSPI_DATA0[] = {
{P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2 {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
{P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3 {NC, NC, 0},
{P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4 };
{P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5 const PinMap PinMap_QSPI_DATA1[] = {
{P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6 {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
{P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7 {NC, NC, 0},
{NC, NC, 0} };
}; const PinMap PinMap_QSPI_DATA2[] = {
{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
// Ensure that the spi_select pins are defined in the order 0 to 3 {NC, NC, 0},
const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2 };
{P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0 const PinMap PinMap_QSPI_DATA3[] = {
{P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1 {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
{P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2 {NC, NC, 0},
{P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3
{NC, NC, 0}
}; };
#endif // DEVICE_QSPI #endif // DEVICE_QSPI

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralNames.h
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@ -114,8 +114,8 @@ typedef enum {
} ADCName; } ADCName;
typedef enum { typedef enum {
SMIF_0 = (int)SMIF0_BASE, QSPI_0,
} SMIFName; } QSPIName;
#ifdef __cplusplus #ifdef __cplusplus
} }

47
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c
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@ -464,31 +464,28 @@ const PinMap PinMap_ADC[] = {
#endif // DEVICE_ANALOGIN #endif // DEVICE_ANALOGIN
#if DEVICE_QSPI #if DEVICE_QSPI
const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2 const PinMap PinMap_QSPI_SCLK[] = {
{P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)}, {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
{NC, NC, 0} {NC, NC, 0},
}; };
const PinMap PinMap_QSPI_SSEL[] = {
// Ensure that the spi_data pins are defined in the order 0 to 7 {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2 {NC, NC, 0},
{P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0 };
{P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1 const PinMap PinMap_QSPI_DATA0[] = {
{P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2 {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
{P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3 {NC, NC, 0},
{P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4 };
{P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5 const PinMap PinMap_QSPI_DATA1[] = {
{P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6 {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
{P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7 {NC, NC, 0},
{NC, NC, 0} };
}; const PinMap PinMap_QSPI_DATA2[] = {
{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
// Ensure that the spi_select pins are defined in the order 0 to 3 {NC, NC, 0},
const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2 };
{P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0 const PinMap PinMap_QSPI_DATA3[] = {
{P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1 {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
{P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2 {NC, NC, 0},
{P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3
{NC, NC, 0}
}; };
#endif // DEVICE_QSPI #endif // DEVICE_QSPI

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PeripheralNames.h
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@ -108,8 +108,8 @@ typedef enum {
} DACName; } DACName;
typedef enum { typedef enum {
SMIF_0 = (int)SMIF0_BASE, QSPI_0,
} SMIFName; } QSPIName;
#ifdef __cplusplus #ifdef __cplusplus
} }

46
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/PeripheralPins.c
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@ -436,30 +436,28 @@ const PinMap PinMap_DAC[] = {
#endif // DEVICE_ANALOGIN #endif // DEVICE_ANALOGIN
#if DEVICE_QSPI #if DEVICE_QSPI
const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2 const PinMap PinMap_QSPI_SCLK[] = {
{P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)}, {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
{NC, NC, 0} {NC, NC, 0},
}; };
const PinMap PinMap_QSPI_SSEL[] = {
// Ensure that the spi_data pins are defined in the order 0 to 7 {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2 {NC, NC, 0},
{P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0 };
{P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1 const PinMap PinMap_QSPI_DATA0[] = {
{P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2 {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
{P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3 {NC, NC, 0},
{P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4 };
{P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5 const PinMap PinMap_QSPI_DATA1[] = {
{P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6 {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
{P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7 {NC, NC, 0},
{NC, NC, 0} };
}; const PinMap PinMap_QSPI_DATA2[] = {
{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
// Ensure that the spi_select pins are defined in the order 0 to 3 {NC, NC, 0},
const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2 };
{P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0 const PinMap PinMap_QSPI_DATA3[] = {
{P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1 {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
{P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2 {NC, NC, 0},
{P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3
{NC, NC, 0}
}; };
#endif // DEVICE_QSPI #endif // DEVICE_QSPI