mirror of https://github.com/ARMmbed/mbed-os.git
Merge remote-tracking branch 'refs/remotes/mbedmicro/master' into dev_disco_f469ni
dbestm
commit
ba14dee242
|
|
@ -16,7 +16,7 @@
|
||||||
#ifndef MBED_H
|
#ifndef MBED_H
|
||||||
#define MBED_H
|
#define MBED_H
|
||||||
|
|
||||||
#define MBED_LIBRARY_VERSION 108
|
#define MBED_LIBRARY_VERSION 109
|
||||||
|
|
||||||
#include "platform.h"
|
#include "platform.h"
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,19 @@
|
||||||
|
;SAMD21G18A
|
||||||
|
;256KB FLASH (0x40000) @ 0x000000000
|
||||||
|
;2KB RAM (0x8000) @ 0x20000000
|
||||||
|
|
||||||
|
|
||||||
|
;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||||
|
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||||
|
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
|
||||||
|
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,190 @@
|
||||||
|
;/*****************************************************************************
|
||||||
|
; * @file startup_SAMD21.s
|
||||||
|
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||||
|
; * Atmel SAMD21 Device Series
|
||||||
|
; * @version V1.00
|
||||||
|
; * @date 24. February 2014
|
||||||
|
; *
|
||||||
|
; * @note
|
||||||
|
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
; * processor based microcontrollers. This file can be freely distributed
|
||||||
|
; * within development tools that are supporting such ARM based processors.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
; *
|
||||||
|
; ******************************************************************************/
|
||||||
|
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD PM_Handler ; 0 Power Manager
|
||||||
|
DCD SYSCTRL_Handler ; 1 System Control
|
||||||
|
DCD WDT_Handler ; 2 Watchdog Timer
|
||||||
|
DCD RTC_Handler ; 3 Real-Time Counter
|
||||||
|
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||||
|
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||||
|
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||||
|
DCD USB_Handler ; 7 Universal Serial Bus
|
||||||
|
DCD EVSYS_Handler ; 8 Event System Interface
|
||||||
|
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||||
|
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||||
|
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||||
|
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||||
|
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||||
|
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||||
|
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||||
|
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||||
|
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||||
|
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||||
|
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||||
|
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||||
|
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||||
|
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||||
|
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||||
|
DCD AC_Handler ; 24 Analog Comparators
|
||||||
|
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||||
|
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||||
|
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
|
||||||
|
; Reset Handler
|
||||||
|
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT SYSCTRL_Handler [WEAK]
|
||||||
|
EXPORT WDT_Handler [WEAK]
|
||||||
|
EXPORT RTC_Handler [WEAK]
|
||||||
|
EXPORT EIC_Handler [WEAK]
|
||||||
|
EXPORT NVMCTRL_Handler [WEAK]
|
||||||
|
EXPORT DMAC_Handler [WEAK]
|
||||||
|
EXPORT USB_Handler [WEAK]
|
||||||
|
EXPORT EVSYS_Handler [WEAK]
|
||||||
|
EXPORT SERCOM0_Handler [WEAK]
|
||||||
|
EXPORT SERCOM1_Handler [WEAK]
|
||||||
|
EXPORT SERCOM2_Handler [WEAK]
|
||||||
|
EXPORT SERCOM3_Handler [WEAK]
|
||||||
|
EXPORT SERCOM4_Handler [WEAK]
|
||||||
|
EXPORT SERCOM5_Handler [WEAK]
|
||||||
|
EXPORT TCC0_Handler [WEAK]
|
||||||
|
EXPORT TCC1_Handler [WEAK]
|
||||||
|
EXPORT TCC2_Handler [WEAK]
|
||||||
|
EXPORT TC3_Handler [WEAK]
|
||||||
|
EXPORT TC4_Handler [WEAK]
|
||||||
|
EXPORT TC5_Handler [WEAK]
|
||||||
|
EXPORT TC6_Handler [WEAK]
|
||||||
|
EXPORT TC7_Handler [WEAK]
|
||||||
|
EXPORT ADC_Handler [WEAK]
|
||||||
|
EXPORT AC_Handler [WEAK]
|
||||||
|
EXPORT DAC_Handler [WEAK]
|
||||||
|
EXPORT PTC_Handler [WEAK]
|
||||||
|
EXPORT I2S_Handler [WEAK]
|
||||||
|
|
||||||
|
PM_Handler
|
||||||
|
SYSCTRL_Handler
|
||||||
|
WDT_Handler
|
||||||
|
RTC_Handler
|
||||||
|
EIC_Handler
|
||||||
|
NVMCTRL_Handler
|
||||||
|
DMAC_Handler
|
||||||
|
USB_Handler
|
||||||
|
EVSYS_Handler
|
||||||
|
SERCOM0_Handler
|
||||||
|
SERCOM1_Handler
|
||||||
|
SERCOM2_Handler
|
||||||
|
SERCOM3_Handler
|
||||||
|
SERCOM4_Handler
|
||||||
|
SERCOM5_Handler
|
||||||
|
TCC0_Handler
|
||||||
|
TCC1_Handler
|
||||||
|
TCC2_Handler
|
||||||
|
TC3_Handler
|
||||||
|
TC4_Handler
|
||||||
|
TC5_Handler
|
||||||
|
TC6_Handler
|
||||||
|
TC7_Handler
|
||||||
|
ADC_Handler
|
||||||
|
AC_Handler
|
||||||
|
DAC_Handler
|
||||||
|
PTC_Handler
|
||||||
|
I2S_Handler
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2015 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||||
|
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||||
|
{
|
||||||
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = zi_limit;
|
||||||
|
r.heap_limit = sp_limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,19 @@
|
||||||
|
;SAMD21G18A
|
||||||
|
;256KB FLASH (0x40000) @ 0x000000000
|
||||||
|
;2KB RAM (0x8000) @ 0x20000000
|
||||||
|
|
||||||
|
|
||||||
|
;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||||
|
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||||
|
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
|
||||||
|
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,190 @@
|
||||||
|
;/*****************************************************************************
|
||||||
|
; * @file startup_SAMD21.s
|
||||||
|
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||||
|
; * Atmel SAMD21 Device Series
|
||||||
|
; * @version V1.00
|
||||||
|
; * @date 24. February 2014
|
||||||
|
; *
|
||||||
|
; * @note
|
||||||
|
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
; * processor based microcontrollers. This file can be freely distributed
|
||||||
|
; * within development tools that are supporting such ARM based processors.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
; *
|
||||||
|
; ******************************************************************************/
|
||||||
|
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD PM_Handler ; 0 Power Manager
|
||||||
|
DCD SYSCTRL_Handler ; 1 System Control
|
||||||
|
DCD WDT_Handler ; 2 Watchdog Timer
|
||||||
|
DCD RTC_Handler ; 3 Real-Time Counter
|
||||||
|
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||||
|
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||||
|
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||||
|
DCD USB_Handler ; 7 Universal Serial Bus
|
||||||
|
DCD EVSYS_Handler ; 8 Event System Interface
|
||||||
|
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||||
|
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||||
|
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||||
|
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||||
|
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||||
|
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||||
|
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||||
|
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||||
|
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||||
|
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||||
|
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||||
|
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||||
|
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||||
|
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||||
|
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||||
|
DCD AC_Handler ; 24 Analog Comparators
|
||||||
|
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||||
|
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||||
|
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
|
||||||
|
; Reset Handler
|
||||||
|
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT SYSCTRL_Handler [WEAK]
|
||||||
|
EXPORT WDT_Handler [WEAK]
|
||||||
|
EXPORT RTC_Handler [WEAK]
|
||||||
|
EXPORT EIC_Handler [WEAK]
|
||||||
|
EXPORT NVMCTRL_Handler [WEAK]
|
||||||
|
EXPORT DMAC_Handler [WEAK]
|
||||||
|
EXPORT USB_Handler [WEAK]
|
||||||
|
EXPORT EVSYS_Handler [WEAK]
|
||||||
|
EXPORT SERCOM0_Handler [WEAK]
|
||||||
|
EXPORT SERCOM1_Handler [WEAK]
|
||||||
|
EXPORT SERCOM2_Handler [WEAK]
|
||||||
|
EXPORT SERCOM3_Handler [WEAK]
|
||||||
|
EXPORT SERCOM4_Handler [WEAK]
|
||||||
|
EXPORT SERCOM5_Handler [WEAK]
|
||||||
|
EXPORT TCC0_Handler [WEAK]
|
||||||
|
EXPORT TCC1_Handler [WEAK]
|
||||||
|
EXPORT TCC2_Handler [WEAK]
|
||||||
|
EXPORT TC3_Handler [WEAK]
|
||||||
|
EXPORT TC4_Handler [WEAK]
|
||||||
|
EXPORT TC5_Handler [WEAK]
|
||||||
|
EXPORT TC6_Handler [WEAK]
|
||||||
|
EXPORT TC7_Handler [WEAK]
|
||||||
|
EXPORT ADC_Handler [WEAK]
|
||||||
|
EXPORT AC_Handler [WEAK]
|
||||||
|
EXPORT DAC_Handler [WEAK]
|
||||||
|
EXPORT PTC_Handler [WEAK]
|
||||||
|
EXPORT I2S_Handler [WEAK]
|
||||||
|
|
||||||
|
PM_Handler
|
||||||
|
SYSCTRL_Handler
|
||||||
|
WDT_Handler
|
||||||
|
RTC_Handler
|
||||||
|
EIC_Handler
|
||||||
|
NVMCTRL_Handler
|
||||||
|
DMAC_Handler
|
||||||
|
USB_Handler
|
||||||
|
EVSYS_Handler
|
||||||
|
SERCOM0_Handler
|
||||||
|
SERCOM1_Handler
|
||||||
|
SERCOM2_Handler
|
||||||
|
SERCOM3_Handler
|
||||||
|
SERCOM4_Handler
|
||||||
|
SERCOM5_Handler
|
||||||
|
TCC0_Handler
|
||||||
|
TCC1_Handler
|
||||||
|
TCC2_Handler
|
||||||
|
TC3_Handler
|
||||||
|
TC4_Handler
|
||||||
|
TC5_Handler
|
||||||
|
TC6_Handler
|
||||||
|
TC7_Handler
|
||||||
|
ADC_Handler
|
||||||
|
AC_Handler
|
||||||
|
DAC_Handler
|
||||||
|
PTC_Handler
|
||||||
|
I2S_Handler
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2015 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||||
|
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||||
|
{
|
||||||
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = zi_limit;
|
||||||
|
r.heap_limit = sp_limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -3,18 +3,16 @@ OUTPUT_ARCH(arm)
|
||||||
SEARCH_DIR(.)
|
SEARCH_DIR(.)
|
||||||
|
|
||||||
/* Memory Spaces Definitions */
|
/* Memory Spaces Definitions */
|
||||||
MEMORY
|
MEMORY {
|
||||||
{
|
|
||||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
||||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
|
ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4
|
||||||
}
|
}
|
||||||
|
|
||||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||||
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
|
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
|
||||||
|
|
||||||
/* Section Definitions */
|
/* Section Definitions */
|
||||||
SECTIONS
|
SECTIONS {
|
||||||
{
|
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
|
|
@ -75,14 +73,8 @@ SECTIONS
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
_etext = .;
|
_etext = .;
|
||||||
|
|
||||||
.dvectors (NOLOAD) :
|
.relocate :
|
||||||
{
|
AT (_etext)
|
||||||
_sdvectors = .;
|
|
||||||
. = . + 0xB0;
|
|
||||||
_edvectors = .;
|
|
||||||
} > ram
|
|
||||||
|
|
||||||
.relocate : AT (_etext)
|
|
||||||
{
|
{
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
_srelocate = .;
|
_srelocate = .;
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,19 @@
|
||||||
|
;SAMD21J18A
|
||||||
|
;256KB FLASH (0x40000) @ 0x000000000
|
||||||
|
;2KB RAM (0x8000) @ 0x20000000
|
||||||
|
|
||||||
|
|
||||||
|
;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||||
|
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||||
|
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
|
||||||
|
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,190 @@
|
||||||
|
;/*****************************************************************************
|
||||||
|
; * @file startup_SAMD21.s
|
||||||
|
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||||
|
; * Atmel SAMD21 Device Series
|
||||||
|
; * @version V1.00
|
||||||
|
; * @date 24. February 2014
|
||||||
|
; *
|
||||||
|
; * @note
|
||||||
|
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
; * processor based microcontrollers. This file can be freely distributed
|
||||||
|
; * within development tools that are supporting such ARM based processors.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
; *
|
||||||
|
; ******************************************************************************/
|
||||||
|
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD PM_Handler ; 0 Power Manager
|
||||||
|
DCD SYSCTRL_Handler ; 1 System Control
|
||||||
|
DCD WDT_Handler ; 2 Watchdog Timer
|
||||||
|
DCD RTC_Handler ; 3 Real-Time Counter
|
||||||
|
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||||
|
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||||
|
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||||
|
DCD USB_Handler ; 7 Universal Serial Bus
|
||||||
|
DCD EVSYS_Handler ; 8 Event System Interface
|
||||||
|
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||||
|
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||||
|
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||||
|
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||||
|
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||||
|
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||||
|
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||||
|
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||||
|
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||||
|
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||||
|
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||||
|
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||||
|
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||||
|
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||||
|
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||||
|
DCD AC_Handler ; 24 Analog Comparators
|
||||||
|
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||||
|
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||||
|
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
|
||||||
|
; Reset Handler
|
||||||
|
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT SYSCTRL_Handler [WEAK]
|
||||||
|
EXPORT WDT_Handler [WEAK]
|
||||||
|
EXPORT RTC_Handler [WEAK]
|
||||||
|
EXPORT EIC_Handler [WEAK]
|
||||||
|
EXPORT NVMCTRL_Handler [WEAK]
|
||||||
|
EXPORT DMAC_Handler [WEAK]
|
||||||
|
EXPORT USB_Handler [WEAK]
|
||||||
|
EXPORT EVSYS_Handler [WEAK]
|
||||||
|
EXPORT SERCOM0_Handler [WEAK]
|
||||||
|
EXPORT SERCOM1_Handler [WEAK]
|
||||||
|
EXPORT SERCOM2_Handler [WEAK]
|
||||||
|
EXPORT SERCOM3_Handler [WEAK]
|
||||||
|
EXPORT SERCOM4_Handler [WEAK]
|
||||||
|
EXPORT SERCOM5_Handler [WEAK]
|
||||||
|
EXPORT TCC0_Handler [WEAK]
|
||||||
|
EXPORT TCC1_Handler [WEAK]
|
||||||
|
EXPORT TCC2_Handler [WEAK]
|
||||||
|
EXPORT TC3_Handler [WEAK]
|
||||||
|
EXPORT TC4_Handler [WEAK]
|
||||||
|
EXPORT TC5_Handler [WEAK]
|
||||||
|
EXPORT TC6_Handler [WEAK]
|
||||||
|
EXPORT TC7_Handler [WEAK]
|
||||||
|
EXPORT ADC_Handler [WEAK]
|
||||||
|
EXPORT AC_Handler [WEAK]
|
||||||
|
EXPORT DAC_Handler [WEAK]
|
||||||
|
EXPORT PTC_Handler [WEAK]
|
||||||
|
EXPORT I2S_Handler [WEAK]
|
||||||
|
|
||||||
|
PM_Handler
|
||||||
|
SYSCTRL_Handler
|
||||||
|
WDT_Handler
|
||||||
|
RTC_Handler
|
||||||
|
EIC_Handler
|
||||||
|
NVMCTRL_Handler
|
||||||
|
DMAC_Handler
|
||||||
|
USB_Handler
|
||||||
|
EVSYS_Handler
|
||||||
|
SERCOM0_Handler
|
||||||
|
SERCOM1_Handler
|
||||||
|
SERCOM2_Handler
|
||||||
|
SERCOM3_Handler
|
||||||
|
SERCOM4_Handler
|
||||||
|
SERCOM5_Handler
|
||||||
|
TCC0_Handler
|
||||||
|
TCC1_Handler
|
||||||
|
TCC2_Handler
|
||||||
|
TC3_Handler
|
||||||
|
TC4_Handler
|
||||||
|
TC5_Handler
|
||||||
|
TC6_Handler
|
||||||
|
TC7_Handler
|
||||||
|
ADC_Handler
|
||||||
|
AC_Handler
|
||||||
|
DAC_Handler
|
||||||
|
PTC_Handler
|
||||||
|
I2S_Handler
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2015 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||||
|
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||||
|
{
|
||||||
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = zi_limit;
|
||||||
|
r.heap_limit = sp_limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,19 @@
|
||||||
|
;SAMD21J18A
|
||||||
|
;256KB FLASH (0x40000) @ 0x000000000
|
||||||
|
;2KB RAM (0x8000) @ 0x20000000
|
||||||
|
|
||||||
|
|
||||||
|
;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||||
|
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||||
|
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
|
||||||
|
RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4) { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,190 @@
|
||||||
|
;/*****************************************************************************
|
||||||
|
; * @file startup_SAMD21.s
|
||||||
|
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||||
|
; * Atmel SAMD21 Device Series
|
||||||
|
; * @version V1.00
|
||||||
|
; * @date 24. February 2014
|
||||||
|
; *
|
||||||
|
; * @note
|
||||||
|
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
; * processor based microcontrollers. This file can be freely distributed
|
||||||
|
; * within development tools that are supporting such ARM based processors.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
; *
|
||||||
|
; ******************************************************************************/
|
||||||
|
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD PM_Handler ; 0 Power Manager
|
||||||
|
DCD SYSCTRL_Handler ; 1 System Control
|
||||||
|
DCD WDT_Handler ; 2 Watchdog Timer
|
||||||
|
DCD RTC_Handler ; 3 Real-Time Counter
|
||||||
|
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||||
|
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||||
|
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||||
|
DCD USB_Handler ; 7 Universal Serial Bus
|
||||||
|
DCD EVSYS_Handler ; 8 Event System Interface
|
||||||
|
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||||
|
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||||
|
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||||
|
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||||
|
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||||
|
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||||
|
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||||
|
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||||
|
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||||
|
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||||
|
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||||
|
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||||
|
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||||
|
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||||
|
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||||
|
DCD AC_Handler ; 24 Analog Comparators
|
||||||
|
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||||
|
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||||
|
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
|
||||||
|
; Reset Handler
|
||||||
|
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT SYSCTRL_Handler [WEAK]
|
||||||
|
EXPORT WDT_Handler [WEAK]
|
||||||
|
EXPORT RTC_Handler [WEAK]
|
||||||
|
EXPORT EIC_Handler [WEAK]
|
||||||
|
EXPORT NVMCTRL_Handler [WEAK]
|
||||||
|
EXPORT DMAC_Handler [WEAK]
|
||||||
|
EXPORT USB_Handler [WEAK]
|
||||||
|
EXPORT EVSYS_Handler [WEAK]
|
||||||
|
EXPORT SERCOM0_Handler [WEAK]
|
||||||
|
EXPORT SERCOM1_Handler [WEAK]
|
||||||
|
EXPORT SERCOM2_Handler [WEAK]
|
||||||
|
EXPORT SERCOM3_Handler [WEAK]
|
||||||
|
EXPORT SERCOM4_Handler [WEAK]
|
||||||
|
EXPORT SERCOM5_Handler [WEAK]
|
||||||
|
EXPORT TCC0_Handler [WEAK]
|
||||||
|
EXPORT TCC1_Handler [WEAK]
|
||||||
|
EXPORT TCC2_Handler [WEAK]
|
||||||
|
EXPORT TC3_Handler [WEAK]
|
||||||
|
EXPORT TC4_Handler [WEAK]
|
||||||
|
EXPORT TC5_Handler [WEAK]
|
||||||
|
EXPORT TC6_Handler [WEAK]
|
||||||
|
EXPORT TC7_Handler [WEAK]
|
||||||
|
EXPORT ADC_Handler [WEAK]
|
||||||
|
EXPORT AC_Handler [WEAK]
|
||||||
|
EXPORT DAC_Handler [WEAK]
|
||||||
|
EXPORT PTC_Handler [WEAK]
|
||||||
|
EXPORT I2S_Handler [WEAK]
|
||||||
|
|
||||||
|
PM_Handler
|
||||||
|
SYSCTRL_Handler
|
||||||
|
WDT_Handler
|
||||||
|
RTC_Handler
|
||||||
|
EIC_Handler
|
||||||
|
NVMCTRL_Handler
|
||||||
|
DMAC_Handler
|
||||||
|
USB_Handler
|
||||||
|
EVSYS_Handler
|
||||||
|
SERCOM0_Handler
|
||||||
|
SERCOM1_Handler
|
||||||
|
SERCOM2_Handler
|
||||||
|
SERCOM3_Handler
|
||||||
|
SERCOM4_Handler
|
||||||
|
SERCOM5_Handler
|
||||||
|
TCC0_Handler
|
||||||
|
TCC1_Handler
|
||||||
|
TCC2_Handler
|
||||||
|
TC3_Handler
|
||||||
|
TC4_Handler
|
||||||
|
TC5_Handler
|
||||||
|
TC6_Handler
|
||||||
|
TC7_Handler
|
||||||
|
ADC_Handler
|
||||||
|
AC_Handler
|
||||||
|
DAC_Handler
|
||||||
|
PTC_Handler
|
||||||
|
I2S_Handler
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2015 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||||
|
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||||
|
{
|
||||||
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = zi_limit;
|
||||||
|
r.heap_limit = sp_limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -5,7 +5,7 @@ SEARCH_DIR(.)
|
||||||
/* Memory Spaces Definitions */
|
/* Memory Spaces Definitions */
|
||||||
MEMORY {
|
MEMORY {
|
||||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
||||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
|
ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4
|
||||||
}
|
}
|
||||||
|
|
||||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||||
|
|
@ -73,13 +73,6 @@ MEMORY {
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
_etext = .;
|
_etext = .;
|
||||||
|
|
||||||
.dvectors (NOLOAD) :
|
|
||||||
{
|
|
||||||
_sdvectors = .;
|
|
||||||
. = . + 0xB0;
|
|
||||||
_edvectors = .;
|
|
||||||
} > ram
|
|
||||||
|
|
||||||
.relocate :
|
.relocate :
|
||||||
AT (_etext)
|
AT (_etext)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,19 @@
|
||||||
|
;SAMR21G18A
|
||||||
|
;256KB FLASH (0x40000) @ 0x000000000
|
||||||
|
;2KB RAM (0x8000) @ 0x20000000
|
||||||
|
|
||||||
|
|
||||||
|
;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||||
|
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||||
|
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
|
||||||
|
RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,189 @@
|
||||||
|
;/*****************************************************************************
|
||||||
|
; * @file startup_SAMR21.s
|
||||||
|
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||||
|
; * Atmel SAMR21 Device Series
|
||||||
|
; * @version V1.00
|
||||||
|
; * @date 24. February 2014
|
||||||
|
; *
|
||||||
|
; * @note
|
||||||
|
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
; * processor based microcontrollers. This file can be freely distributed
|
||||||
|
; * within development tools that are supporting such ARM based processors.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
; *
|
||||||
|
; ******************************************************************************/
|
||||||
|
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD PM_Handler ; 0 Power Manager
|
||||||
|
DCD SYSCTRL_Handler ; 1 System Control
|
||||||
|
DCD WDT_Handler ; 2 Watchdog Timer
|
||||||
|
DCD RTC_Handler ; 3 Real-Time Counter
|
||||||
|
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||||
|
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||||
|
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||||
|
DCD USB_Handler ; 7 Universal Serial Bus
|
||||||
|
DCD EVSYS_Handler ; 8 Event System Interface
|
||||||
|
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||||
|
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||||
|
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||||
|
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||||
|
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||||
|
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||||
|
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||||
|
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||||
|
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||||
|
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||||
|
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||||
|
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||||
|
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||||
|
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||||
|
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||||
|
DCD AC_Handler ; 24 Analog Comparators
|
||||||
|
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||||
|
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||||
|
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
|
||||||
|
; Reset Handler
|
||||||
|
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT SYSCTRL_Handler [WEAK]
|
||||||
|
EXPORT WDT_Handler [WEAK]
|
||||||
|
EXPORT RTC_Handler [WEAK]
|
||||||
|
EXPORT EIC_Handler [WEAK]
|
||||||
|
EXPORT NVMCTRL_Handler [WEAK]
|
||||||
|
EXPORT DMAC_Handler [WEAK]
|
||||||
|
EXPORT USB_Handler [WEAK]
|
||||||
|
EXPORT EVSYS_Handler [WEAK]
|
||||||
|
EXPORT SERCOM0_Handler [WEAK]
|
||||||
|
EXPORT SERCOM1_Handler [WEAK]
|
||||||
|
EXPORT SERCOM2_Handler [WEAK]
|
||||||
|
EXPORT SERCOM3_Handler [WEAK]
|
||||||
|
EXPORT SERCOM4_Handler [WEAK]
|
||||||
|
EXPORT SERCOM5_Handler [WEAK]
|
||||||
|
EXPORT TCC0_Handler [WEAK]
|
||||||
|
EXPORT TCC1_Handler [WEAK]
|
||||||
|
EXPORT TCC2_Handler [WEAK]
|
||||||
|
EXPORT TC3_Handler [WEAK]
|
||||||
|
EXPORT TC4_Handler [WEAK]
|
||||||
|
EXPORT TC5_Handler [WEAK]
|
||||||
|
EXPORT TC6_Handler [WEAK]
|
||||||
|
EXPORT TC7_Handler [WEAK]
|
||||||
|
EXPORT ADC_Handler [WEAK]
|
||||||
|
EXPORT AC_Handler [WEAK]
|
||||||
|
EXPORT DAC_Handler [WEAK]
|
||||||
|
EXPORT PTC_Handler [WEAK]
|
||||||
|
EXPORT I2S_Handler [WEAK]
|
||||||
|
|
||||||
|
PM_Handler
|
||||||
|
SYSCTRL_Handler
|
||||||
|
WDT_Handler
|
||||||
|
RTC_Handler
|
||||||
|
EIC_Handler
|
||||||
|
NVMCTRL_Handler
|
||||||
|
DMAC_Handler
|
||||||
|
USB_Handler
|
||||||
|
EVSYS_Handler
|
||||||
|
SERCOM0_Handler
|
||||||
|
SERCOM1_Handler
|
||||||
|
SERCOM2_Handler
|
||||||
|
SERCOM3_Handler
|
||||||
|
SERCOM4_Handler
|
||||||
|
SERCOM5_Handler
|
||||||
|
TCC0_Handler
|
||||||
|
TCC1_Handler
|
||||||
|
TCC2_Handler
|
||||||
|
TC3_Handler
|
||||||
|
TC4_Handler
|
||||||
|
TC5_Handler
|
||||||
|
TC6_Handler
|
||||||
|
TC7_Handler
|
||||||
|
ADC_Handler
|
||||||
|
AC_Handler
|
||||||
|
DAC_Handler
|
||||||
|
PTC_Handler
|
||||||
|
I2S_Handler
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2015 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||||
|
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||||
|
{
|
||||||
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = zi_limit;
|
||||||
|
r.heap_limit = sp_limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,19 @@
|
||||||
|
;SAMR21G18A
|
||||||
|
;256KB FLASH (0x40000) @ 0x000000000
|
||||||
|
;2KB RAM (0x8000) @ 0x20000000
|
||||||
|
|
||||||
|
|
||||||
|
;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
|
||||||
|
LR_IROM1 0x00000000 0x40000 { ; load region size_region
|
||||||
|
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||||
|
*.o (RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
|
||||||
|
RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,189 @@
|
||||||
|
;/*****************************************************************************
|
||||||
|
; * @file startup_SAMR21.s
|
||||||
|
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||||
|
; * Atmel SAMR21 Device Series
|
||||||
|
; * @version V1.00
|
||||||
|
; * @date 24. February 2014
|
||||||
|
; *
|
||||||
|
; * @note
|
||||||
|
; * Copyright (C) 2014 ARM Limited. All rights reserved.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
; * processor based microcontrollers. This file can be freely distributed
|
||||||
|
; * within development tools that are supporting such ARM based processors.
|
||||||
|
; *
|
||||||
|
; * @par
|
||||||
|
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
; *
|
||||||
|
; ******************************************************************************/
|
||||||
|
__initial_sp EQU 0x20008000 ; Top of RAM
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
|
||||||
|
; Vector Table Mapped to Address 0 at Reset
|
||||||
|
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD PM_Handler ; 0 Power Manager
|
||||||
|
DCD SYSCTRL_Handler ; 1 System Control
|
||||||
|
DCD WDT_Handler ; 2 Watchdog Timer
|
||||||
|
DCD RTC_Handler ; 3 Real-Time Counter
|
||||||
|
DCD EIC_Handler ; 4 External Interrupt Controller
|
||||||
|
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
|
||||||
|
DCD DMAC_Handler ; 6 Direct Memory Access Controller
|
||||||
|
DCD USB_Handler ; 7 Universal Serial Bus
|
||||||
|
DCD EVSYS_Handler ; 8 Event System Interface
|
||||||
|
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
|
||||||
|
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
|
||||||
|
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
|
||||||
|
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
|
||||||
|
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
|
||||||
|
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
|
||||||
|
DCD TCC0_Handler ; 15 Timer Counter Control 0
|
||||||
|
DCD TCC1_Handler ; 16 Timer Counter Control 1
|
||||||
|
DCD TCC2_Handler ; 17 Timer Counter Control 2
|
||||||
|
DCD TC3_Handler ; 18 Basic Timer Counter 0
|
||||||
|
DCD TC4_Handler ; 19 Basic Timer Counter 1
|
||||||
|
DCD TC5_Handler ; 20 Basic Timer Counter 2
|
||||||
|
DCD TC6_Handler ; 21 Basic Timer Counter 3
|
||||||
|
DCD TC7_Handler ; 22 Basic Timer Counter 4
|
||||||
|
DCD ADC_Handler ; 23 Analog Digital Converter
|
||||||
|
DCD AC_Handler ; 24 Analog Comparators
|
||||||
|
DCD DAC_Handler ; 25 Digital Analog Converter
|
||||||
|
DCD PTC_Handler ; 26 Peripheral Touch Controller
|
||||||
|
DCD I2S_Handler ; 27 Inter-IC Sound Interface
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
|
||||||
|
; Reset Handler
|
||||||
|
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||||
|
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
EXPORT PM_Handler [WEAK]
|
||||||
|
EXPORT SYSCTRL_Handler [WEAK]
|
||||||
|
EXPORT WDT_Handler [WEAK]
|
||||||
|
EXPORT RTC_Handler [WEAK]
|
||||||
|
EXPORT EIC_Handler [WEAK]
|
||||||
|
EXPORT NVMCTRL_Handler [WEAK]
|
||||||
|
EXPORT DMAC_Handler [WEAK]
|
||||||
|
EXPORT USB_Handler [WEAK]
|
||||||
|
EXPORT EVSYS_Handler [WEAK]
|
||||||
|
EXPORT SERCOM0_Handler [WEAK]
|
||||||
|
EXPORT SERCOM1_Handler [WEAK]
|
||||||
|
EXPORT SERCOM2_Handler [WEAK]
|
||||||
|
EXPORT SERCOM3_Handler [WEAK]
|
||||||
|
EXPORT SERCOM4_Handler [WEAK]
|
||||||
|
EXPORT SERCOM5_Handler [WEAK]
|
||||||
|
EXPORT TCC0_Handler [WEAK]
|
||||||
|
EXPORT TCC1_Handler [WEAK]
|
||||||
|
EXPORT TCC2_Handler [WEAK]
|
||||||
|
EXPORT TC3_Handler [WEAK]
|
||||||
|
EXPORT TC4_Handler [WEAK]
|
||||||
|
EXPORT TC5_Handler [WEAK]
|
||||||
|
EXPORT TC6_Handler [WEAK]
|
||||||
|
EXPORT TC7_Handler [WEAK]
|
||||||
|
EXPORT ADC_Handler [WEAK]
|
||||||
|
EXPORT AC_Handler [WEAK]
|
||||||
|
EXPORT DAC_Handler [WEAK]
|
||||||
|
EXPORT PTC_Handler [WEAK]
|
||||||
|
EXPORT I2S_Handler [WEAK]
|
||||||
|
|
||||||
|
PM_Handler
|
||||||
|
SYSCTRL_Handler
|
||||||
|
WDT_Handler
|
||||||
|
RTC_Handler
|
||||||
|
EIC_Handler
|
||||||
|
NVMCTRL_Handler
|
||||||
|
DMAC_Handler
|
||||||
|
USB_Handler
|
||||||
|
EVSYS_Handler
|
||||||
|
SERCOM0_Handler
|
||||||
|
SERCOM1_Handler
|
||||||
|
SERCOM2_Handler
|
||||||
|
SERCOM3_Handler
|
||||||
|
SERCOM4_Handler
|
||||||
|
SERCOM5_Handler
|
||||||
|
TCC0_Handler
|
||||||
|
TCC1_Handler
|
||||||
|
TCC2_Handler
|
||||||
|
TC3_Handler
|
||||||
|
TC4_Handler
|
||||||
|
TC5_Handler
|
||||||
|
TC6_Handler
|
||||||
|
TC7_Handler
|
||||||
|
ADC_Handler
|
||||||
|
AC_Handler
|
||||||
|
DAC_Handler
|
||||||
|
PTC_Handler
|
||||||
|
I2S_Handler
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
|
@ -0,0 +1,41 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2006-2015 ARM Limited
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||||
|
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
|
||||||
|
{
|
||||||
|
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||||
|
uint32_t sp_limit = __current_sp();
|
||||||
|
|
||||||
|
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = zi_limit;
|
||||||
|
r.heap_limit = sp_limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -5,7 +5,7 @@ SEARCH_DIR(.)
|
||||||
/* Memory Spaces Definitions */
|
/* Memory Spaces Definitions */
|
||||||
MEMORY {
|
MEMORY {
|
||||||
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
|
||||||
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
|
ram (rwx) : ORIGIN = 0x20000000 + 0xB0, LENGTH = 0x00008000 - 0xB0
|
||||||
}
|
}
|
||||||
|
|
||||||
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
|
||||||
|
|
@ -73,13 +73,6 @@ MEMORY {
|
||||||
. = ALIGN(4);
|
. = ALIGN(4);
|
||||||
_etext = .;
|
_etext = .;
|
||||||
|
|
||||||
.dvectors (NOLOAD) :
|
|
||||||
{
|
|
||||||
_sdvectors = .;
|
|
||||||
. = . + 0xB0;
|
|
||||||
_edvectors = .;
|
|
||||||
} > ram
|
|
||||||
|
|
||||||
.relocate :
|
.relocate :
|
||||||
AT (_etext)
|
AT (_etext)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -30,8 +30,8 @@
|
||||||
*/
|
*/
|
||||||
#include "cmsis_nvic.h"
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
//#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||||
extern uint32_t _sdvectors;
|
//extern uint32_t _sdvectors;
|
||||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
||||||
|
|
||||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
|
@ -42,11 +42,11 @@ void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
// Copy and switch to dynamic vectors if the first time called
|
// Copy and switch to dynamic vectors if the first time called
|
||||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||||
uint32_t *old_vectors = vectors;
|
uint32_t *old_vectors = vectors;
|
||||||
vectors = (uint32_t*)&_sdvectors;
|
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||||
vectors[i] = old_vectors[i];
|
vectors[i] = old_vectors[i];
|
||||||
}
|
}
|
||||||
SCB->VTOR = (uint32_t)&_sdvectors;
|
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||||
}
|
}
|
||||||
vectors[IRQn + 16] = vector;
|
vectors[IRQn + 16] = vector;
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -118,7 +118,7 @@
|
||||||
|
|
||||||
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
|
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
|
||||||
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
|
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
|
||||||
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
|
#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
|
@ -420,6 +420,7 @@ uint8_t SetSysClock_PLL_HSI(void)
|
||||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
|
||||||
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
|
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
|
||||||
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
|
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
|
||||||
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||||
return 0; // FAIL
|
return 0; // FAIL
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -118,7 +118,7 @@
|
||||||
|
|
||||||
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
|
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
|
||||||
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
|
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
|
||||||
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
|
#define USE_PLL_HSE_XTAL (0) /* Use external xtal */
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
|
|
@ -413,13 +413,14 @@ uint8_t SetSysClock_PLL_HSI(void)
|
||||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||||
|
|
||||||
// Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
|
// Select PLLCLK = 48 MHz ((HSI 8 MHz) * 6)
|
||||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
||||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
||||||
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
|
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
|
||||||
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
|
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
|
||||||
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||||
return 0; // FAIL
|
return 0; // FAIL
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -147,7 +147,7 @@
|
||||||
#endif /* LSE_VALUE */
|
#endif /* LSE_VALUE */
|
||||||
|
|
||||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||||
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
|
#define LSE_STARTUP_TIMEOUT ((uint32_t)500) /*!< Time out for LSE start up, in ms */
|
||||||
#endif /* HSE_STARTUP_TIMEOUT */
|
#endif /* HSE_STARTUP_TIMEOUT */
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -29,8 +29,10 @@ static const PinMap PinMap_ADC[] = {
|
||||||
{p4, ADC0_0, 32},
|
{p4, ADC0_0, 32},
|
||||||
{p5, ADC0_0, 64},
|
{p5, ADC0_0, 64},
|
||||||
{p6, ADC0_0, 128},
|
{p6, ADC0_0, 128},
|
||||||
|
#ifndef TARGET_NRF51_DONGLE
|
||||||
{p26, ADC0_0, 1},
|
{p26, ADC0_0, 1},
|
||||||
{p27, ADC0_0, 2},
|
{p27, ADC0_0, 2},
|
||||||
|
#endif
|
||||||
{NC, NC, 0}
|
{NC, NC, 0}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -100,7 +100,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
|
||||||
|
|
||||||
void i2c_frequency(i2c_t *obj, int hz)
|
void i2c_frequency(i2c_t *obj, int hz)
|
||||||
{
|
{
|
||||||
MBED_ASSERT((hz != 0) && (hz <= 400000));
|
MBED_ASSERT((hz > 0) && (hz <= 400000));
|
||||||
I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
|
I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
|
||||||
int timeout;
|
int timeout;
|
||||||
|
|
||||||
|
|
@ -135,8 +135,8 @@ inline int i2c_start(i2c_t *obj)
|
||||||
// Clear Acknowledge failure flag
|
// Clear Acknowledge failure flag
|
||||||
__HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
|
__HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
|
||||||
|
|
||||||
// Generate the START condition
|
// Generate the START condition and remove an eventual pending STOP bit
|
||||||
i2c->CR1 |= I2C_CR1_START;
|
i2c->CR1 = ((i2c->CR1 & ~I2C_CR1_STOP) | I2C_CR1_START);
|
||||||
|
|
||||||
// Wait the START condition has been correctly sent
|
// Wait the START condition has been correctly sent
|
||||||
timeout = FLAG_TIMEOUT;
|
timeout = FLAG_TIMEOUT;
|
||||||
|
|
|
||||||
|
|
@ -61,6 +61,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
|
||||||
('TEENSY3_1', ('ARM', 'GCC_ARM')),
|
('TEENSY3_1', ('ARM', 'GCC_ARM')),
|
||||||
|
|
||||||
('NUCLEO_F030R8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
|
('NUCLEO_F030R8', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
|
||||||
|
('NUCLEO_F031K6', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
|
||||||
('NUCLEO_F042K6', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
|
('NUCLEO_F042K6', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
|
||||||
('NUCLEO_F070RB', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
|
('NUCLEO_F070RB', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
|
||||||
('NUCLEO_F072RB', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
|
('NUCLEO_F072RB', ('ARM', 'uARM', 'IAR', 'GCC_ARM')),
|
||||||
|
|
|
||||||
|
|
@ -86,6 +86,9 @@ class Uvision4(Exporter):
|
||||||
'MAX32600MBED',
|
'MAX32600MBED',
|
||||||
'MOTE_L152RC',
|
'MOTE_L152RC',
|
||||||
'NZ32SC151',
|
'NZ32SC151',
|
||||||
|
'SAMR21G18A',
|
||||||
|
'SAMD21J18A',
|
||||||
|
'SAMD21G18A',
|
||||||
]
|
]
|
||||||
|
|
||||||
USING_MICROLIB = [
|
USING_MICROLIB = [
|
||||||
|
|
@ -123,6 +126,9 @@ class Uvision4(Exporter):
|
||||||
'LPC11U37H_401',
|
'LPC11U37H_401',
|
||||||
'MOTE_L152RC',
|
'MOTE_L152RC',
|
||||||
'NZ32SC151',
|
'NZ32SC151',
|
||||||
|
'SAMR21G18A',
|
||||||
|
'SAMD21J18A',
|
||||||
|
'SAMD21G18A',
|
||||||
]
|
]
|
||||||
|
|
||||||
FILE_TYPES = {
|
FILE_TYPES = {
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,204 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.0</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Extensions>
|
||||||
|
<cExt>*.c</cExt>
|
||||||
|
<aExt>*.s*; *.src; *.a*</aExt>
|
||||||
|
<oExt>*.obj</oExt>
|
||||||
|
<lExt>*.lib</lExt>
|
||||||
|
<tExt>*.txt; *.h; *.inc</tExt>
|
||||||
|
<pExt>*.plm</pExt>
|
||||||
|
<CppX>*.cpp</CppX>
|
||||||
|
</Extensions>
|
||||||
|
|
||||||
|
<DaveTm>
|
||||||
|
<dwLowDateTime>0</dwLowDateTime>
|
||||||
|
<dwHighDateTime>0</dwHighDateTime>
|
||||||
|
</DaveTm>
|
||||||
|
|
||||||
|
<Target>
|
||||||
|
<TargetName>mbed SAMD21J18A</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<CLKADS>8000000</CLKADS>
|
||||||
|
<OPTTT>
|
||||||
|
<gFlags>1</gFlags>
|
||||||
|
<BeepAtEnd>1</BeepAtEnd>
|
||||||
|
<RunSim>1</RunSim>
|
||||||
|
<RunTarget>0</RunTarget>
|
||||||
|
</OPTTT>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<FlashByte>65535</FlashByte>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
</OPTHX>
|
||||||
|
<OPTLEX>
|
||||||
|
<PageWidth>79</PageWidth>
|
||||||
|
<PageLength>66</PageLength>
|
||||||
|
<TabStop>8</TabStop>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
</OPTLEX>
|
||||||
|
<ListingPage>
|
||||||
|
<CreateCListing>1</CreateCListing>
|
||||||
|
<CreateAListing>1</CreateAListing>
|
||||||
|
<CreateLListing>1</CreateLListing>
|
||||||
|
<CreateIListing>0</CreateIListing>
|
||||||
|
<AsmCond>1</AsmCond>
|
||||||
|
<AsmSymb>1</AsmSymb>
|
||||||
|
<AsmXref>0</AsmXref>
|
||||||
|
<CCond>1</CCond>
|
||||||
|
<CCode>0</CCode>
|
||||||
|
<CListInc>0</CListInc>
|
||||||
|
<CSymb>0</CSymb>
|
||||||
|
<LinkerCodeListing>0</LinkerCodeListing>
|
||||||
|
</ListingPage>
|
||||||
|
<OPTXL>
|
||||||
|
<LMap>1</LMap>
|
||||||
|
<LComments>1</LComments>
|
||||||
|
<LGenerateSymbols>1</LGenerateSymbols>
|
||||||
|
<LLibSym>1</LLibSym>
|
||||||
|
<LLines>1</LLines>
|
||||||
|
<LLocSym>1</LLocSym>
|
||||||
|
<LPubSym>1</LPubSym>
|
||||||
|
<LXref>0</LXref>
|
||||||
|
<LExpSel>0</LExpSel>
|
||||||
|
</OPTXL>
|
||||||
|
<OPTFL>
|
||||||
|
<tvExp>1</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<IsCurrentTarget>1</IsCurrentTarget>
|
||||||
|
</OPTFL>
|
||||||
|
<CpuCode>14</CpuCode>
|
||||||
|
<Books>
|
||||||
|
<Book>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Title>Datasheet</Title>
|
||||||
|
<Path>datashts\Atmel\SAMD21\NotYetAvailable.pdf</Path>
|
||||||
|
</Book>
|
||||||
|
<Book>
|
||||||
|
<Number>1</Number>
|
||||||
|
<Title>Technical Reference Manual</Title>
|
||||||
|
<Path>datashts\arm\cortex_m0p\r0p0\DDI0484B_CORTEX_M0P_R0P0_TRM.PDF</Path>
|
||||||
|
</Book>
|
||||||
|
<Book>
|
||||||
|
<Number>2</Number>
|
||||||
|
<Title>Generic User Guide</Title>
|
||||||
|
<Path>datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF</Path>
|
||||||
|
</Book>
|
||||||
|
</Books>
|
||||||
|
<DllOpt>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments></SimDllArguments>
|
||||||
|
<SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
|
||||||
|
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments></TargetDllArguments>
|
||||||
|
<TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
|
||||||
|
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||||
|
</DllOpt>
|
||||||
|
|
||||||
|
<DebugOpt>
|
||||||
|
<uSim>0</uSim>
|
||||||
|
<uTrg>1</uTrg>
|
||||||
|
<sLdApp>1</sLdApp>
|
||||||
|
<sGomain>1</sGomain>
|
||||||
|
<sRbreak>1</sRbreak>
|
||||||
|
<sRwatch>1</sRwatch>
|
||||||
|
<sRmem>1</sRmem>
|
||||||
|
<sRfunc>1</sRfunc>
|
||||||
|
<sRbox>1</sRbox>
|
||||||
|
<tLdApp>1</tLdApp>
|
||||||
|
<tGomain>1</tGomain>
|
||||||
|
<tRbreak>1</tRbreak>
|
||||||
|
<tRwatch>1</tRwatch>
|
||||||
|
<tRmem>1</tRmem>
|
||||||
|
<tRfunc>0</tRfunc>
|
||||||
|
<tRbox>1</tRbox>
|
||||||
|
<sRunDeb>0</sRunDeb>
|
||||||
|
<sLrtime>0</sLrtime>
|
||||||
|
<nTsel>14</nTsel>
|
||||||
|
<sDll></sDll>
|
||||||
|
<sDllPa></sDllPa>
|
||||||
|
<sDlgDll></sDlgDll>
|
||||||
|
<sDlgPa></sDlgPa>
|
||||||
|
<sIfile></sIfile>
|
||||||
|
<tDll></tDll>
|
||||||
|
<tDllPa></tDllPa>
|
||||||
|
<tDlgDll></tDlgDll>
|
||||||
|
<tDlgPa></tDlgPa>
|
||||||
|
<tIfile></tIfile>
|
||||||
|
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||||
|
</DebugOpt>
|
||||||
|
<TargetDriverDllRegistry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>UL2CM3</Key>
|
||||||
|
<Name>UL2CM3(-O207 -O207 -S9 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0ATSAMD21_256 -FL040000 -FS00</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>CMSIS_AGDI</Key>
|
||||||
|
<Name>-X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
</TargetDriverDllRegistry>
|
||||||
|
<Breakpoint/>
|
||||||
|
<DebugFlag>
|
||||||
|
<trace>0</trace>
|
||||||
|
<periodic>0</periodic>
|
||||||
|
<aLwin>0</aLwin>
|
||||||
|
<aCover>0</aCover>
|
||||||
|
<aSer1>0</aSer1>
|
||||||
|
<aSer2>0</aSer2>
|
||||||
|
<aPa>0</aPa>
|
||||||
|
<viewmode>0</viewmode>
|
||||||
|
<vrSel>0</vrSel>
|
||||||
|
<aSym>0</aSym>
|
||||||
|
<aTbox>0</aTbox>
|
||||||
|
<AscS1>0</AscS1>
|
||||||
|
<AscS2>0</AscS2>
|
||||||
|
<AscS3>0</AscS3>
|
||||||
|
<aSer3>0</aSer3>
|
||||||
|
<eProf>0</eProf>
|
||||||
|
<aLa>0</aLa>
|
||||||
|
<aPa1>0</aPa1>
|
||||||
|
<AscS4>0</AscS4>
|
||||||
|
<aSer4>0</aSer4>
|
||||||
|
<StkLoc>0</StkLoc>
|
||||||
|
<TrcWin>0</TrcWin>
|
||||||
|
<newCpu>0</newCpu>
|
||||||
|
<uProt>0</uProt>
|
||||||
|
</DebugFlag>
|
||||||
|
<LintExecutable></LintExecutable>
|
||||||
|
<LintConfigFile></LintConfigFile>
|
||||||
|
</TargetOption>
|
||||||
|
</Target>
|
||||||
|
|
||||||
|
<Group>
|
||||||
|
<GroupName>src</GroupName>
|
||||||
|
<tvExp>1</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<cbSel>0</cbSel>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>1</GroupNumber>
|
||||||
|
<FileNumber>1</FileNumber>
|
||||||
|
<FileType>8</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<TopLine>1</TopLine>
|
||||||
|
<CurrentLine>2</CurrentLine>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>main.cpp</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>main.cpp</FilenameWithoutPath>
|
||||||
|
</File>
|
||||||
|
</Group>
|
||||||
|
|
||||||
|
</ProjectOpt>
|
||||||
|
|
@ -0,0 +1,424 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.1</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Targets>
|
||||||
|
<Target>
|
||||||
|
<TargetName>SAMD21G18A</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<TargetCommonOption>
|
||||||
|
<Device>SAMR21G18A</Device>
|
||||||
|
<Vendor>Atmel</Vendor>
|
||||||
|
<Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0003FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+")</Cpu>
|
||||||
|
<FlashUtilSpec></FlashUtilSpec>
|
||||||
|
<StartupFile>"Startup\Atmel\SAMD21\startup_SAMD21.s" ("Atmel SAMD21 Startup Code")</StartupFile>
|
||||||
|
<FlashDriverDll>UL2CM3(-O207 -S9 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0ATSAMD21_256 -FS00 -FL040000)</FlashDriverDll>
|
||||||
|
<DeviceId>7341</DeviceId>
|
||||||
|
<RegisterFile>samd21.h</RegisterFile>
|
||||||
|
<MemoryEnv></MemoryEnv>
|
||||||
|
<Cmp></Cmp>
|
||||||
|
<Asm></Asm>
|
||||||
|
<Linker></Linker>
|
||||||
|
<OHString></OHString>
|
||||||
|
<InfinionOptionDll></InfinionOptionDll>
|
||||||
|
<SLE66CMisc>-D__SAMD21G18A__</SLE66CMisc>
|
||||||
|
<SLE66AMisc></SLE66AMisc>
|
||||||
|
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||||
|
<SFDFile>SFD\Atmel\SAMD21\ATSAMD21G18A.SFR</SFDFile>
|
||||||
|
<bCustSvd>0</bCustSvd>
|
||||||
|
<UseEnv>0</UseEnv>
|
||||||
|
<BinPath></BinPath>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
<LibPath></LibPath>
|
||||||
|
<RegisterFilePath>Atmel\SAMD21\</RegisterFilePath>
|
||||||
|
<DBRegisterFilePath>Atmel\SAMD21\</DBRegisterFilePath>
|
||||||
|
<TargetStatus>
|
||||||
|
<Error>0</Error>
|
||||||
|
<ExitCodeStop>0</ExitCodeStop>
|
||||||
|
<ButtonStop>0</ButtonStop>
|
||||||
|
<NotGenerated>0</NotGenerated>
|
||||||
|
<InvalidFlash>1</InvalidFlash>
|
||||||
|
</TargetStatus>
|
||||||
|
<OutputDirectory>.\build\</OutputDirectory>
|
||||||
|
<OutputName>{{name}}</OutputName>
|
||||||
|
<CreateExecutable>1</CreateExecutable>
|
||||||
|
<CreateLib>0</CreateLib>
|
||||||
|
<CreateHexFile>0</CreateHexFile>
|
||||||
|
<DebugInformation>1</DebugInformation>
|
||||||
|
<BrowseInformation>1</BrowseInformation>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
<HexFormatSelection>1</HexFormatSelection>
|
||||||
|
<Merge32K>0</Merge32K>
|
||||||
|
<CreateBatchFile>0</CreateBatchFile>
|
||||||
|
<BeforeCompile>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopU1X>0</nStopU1X>
|
||||||
|
<nStopU2X>0</nStopU2X>
|
||||||
|
</BeforeCompile>
|
||||||
|
<BeforeMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
</BeforeMake>
|
||||||
|
<AfterMake>
|
||||||
|
<RunUserProg1>1</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name>fromelf --bin -o build\{{name}}_SAMD21G18A.bin build\{{name}}.axf</UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
</AfterMake>
|
||||||
|
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||||
|
<SVCSIdString></SVCSIdString>
|
||||||
|
</TargetCommonOption>
|
||||||
|
<CommonProperty>
|
||||||
|
<UseCPPCompiler>0</UseCPPCompiler>
|
||||||
|
<RVCTCodeConst>0</RVCTCodeConst>
|
||||||
|
<RVCTZI>0</RVCTZI>
|
||||||
|
<RVCTOtherData>0</RVCTOtherData>
|
||||||
|
<ModuleSelection>0</ModuleSelection>
|
||||||
|
<IncludeInBuild>1</IncludeInBuild>
|
||||||
|
<AlwaysBuild>0</AlwaysBuild>
|
||||||
|
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||||
|
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||||
|
<PublicsOnly>0</PublicsOnly>
|
||||||
|
<StopOnExitCode>3</StopOnExitCode>
|
||||||
|
<CustomArgument></CustomArgument>
|
||||||
|
<IncludeLibraryModules></IncludeLibraryModules>
|
||||||
|
</CommonProperty>
|
||||||
|
<DllOption>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments></SimDllArguments>
|
||||||
|
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
|
||||||
|
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments></TargetDllArguments>
|
||||||
|
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
|
||||||
|
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||||
|
</DllOption>
|
||||||
|
<DebugOption>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
<Oh166RecLen>16</Oh166RecLen>
|
||||||
|
</OPTHX>
|
||||||
|
<Simulator>
|
||||||
|
<UseSimulator>0</UseSimulator>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>1</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||||
|
</Simulator>
|
||||||
|
<Target>
|
||||||
|
<UseTarget>1</UseTarget>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>0</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
</Target>
|
||||||
|
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||||
|
<TargetSelection>14</TargetSelection>
|
||||||
|
<SimDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
</SimDlls>
|
||||||
|
<TargetDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
<Driver>BIN\CMSIS_AGDI.dll</Driver>
|
||||||
|
</TargetDlls>
|
||||||
|
</DebugOption>
|
||||||
|
<Utilities>
|
||||||
|
<Flash1>
|
||||||
|
<UseTargetDll>1</UseTargetDll>
|
||||||
|
<UseExternalTool>0</UseExternalTool>
|
||||||
|
<RunIndependent>0</RunIndependent>
|
||||||
|
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||||
|
<Capability>1</Capability>
|
||||||
|
<DriverSelection>4105</DriverSelection>
|
||||||
|
</Flash1>
|
||||||
|
<Flash2>BIN\CMSIS_AGDI.dll</Flash2>
|
||||||
|
<Flash3>"" ()</Flash3>
|
||||||
|
<Flash4></Flash4>
|
||||||
|
</Utilities>
|
||||||
|
<TargetArmAds>
|
||||||
|
<ArmAdsMisc>
|
||||||
|
<GenerateListings>0</GenerateListings>
|
||||||
|
<asHll>1</asHll>
|
||||||
|
<asAsm>1</asAsm>
|
||||||
|
<asMacX>1</asMacX>
|
||||||
|
<asSyms>1</asSyms>
|
||||||
|
<asFals>1</asFals>
|
||||||
|
<asDbgD>1</asDbgD>
|
||||||
|
<asForm>1</asForm>
|
||||||
|
<ldLst>0</ldLst>
|
||||||
|
<ldmm>1</ldmm>
|
||||||
|
<ldXref>1</ldXref>
|
||||||
|
<BigEnd>0</BigEnd>
|
||||||
|
<AdsALst>1</AdsALst>
|
||||||
|
<AdsACrf>1</AdsACrf>
|
||||||
|
<AdsANop>0</AdsANop>
|
||||||
|
<AdsANot>0</AdsANot>
|
||||||
|
<AdsLLst>1</AdsLLst>
|
||||||
|
<AdsLmap>1</AdsLmap>
|
||||||
|
<AdsLcgr>1</AdsLcgr>
|
||||||
|
<AdsLsym>1</AdsLsym>
|
||||||
|
<AdsLszi>1</AdsLszi>
|
||||||
|
<AdsLtoi>1</AdsLtoi>
|
||||||
|
<AdsLsun>1</AdsLsun>
|
||||||
|
<AdsLven>1</AdsLven>
|
||||||
|
<AdsLsxf>1</AdsLsxf>
|
||||||
|
<RvctClst>0</RvctClst>
|
||||||
|
<GenPPlst>0</GenPPlst>
|
||||||
|
<AdsCpuType>"Cortex-M0+"</AdsCpuType>
|
||||||
|
<RvctDeviceName></RvctDeviceName>
|
||||||
|
<mOS>0</mOS>
|
||||||
|
<uocRom>0</uocRom>
|
||||||
|
<uocRam>0</uocRam>
|
||||||
|
<hadIROM>1</hadIROM>
|
||||||
|
<hadIRAM>1</hadIRAM>
|
||||||
|
<hadXRAM>0</hadXRAM>
|
||||||
|
<uocXRam>0</uocXRam>
|
||||||
|
<RvdsVP>0</RvdsVP>
|
||||||
|
<hadIRAM2>1</hadIRAM2>
|
||||||
|
<hadIROM2>0</hadIROM2>
|
||||||
|
<StupSel>8</StupSel>
|
||||||
|
<useUlib>0</useUlib>
|
||||||
|
<EndSel>0</EndSel>
|
||||||
|
<uLtcg>0</uLtcg>
|
||||||
|
<RoSelD>3</RoSelD>
|
||||||
|
<RwSelD>3</RwSelD>
|
||||||
|
<CodeSel>0</CodeSel>
|
||||||
|
<OptFeed>0</OptFeed>
|
||||||
|
<NoZi1>0</NoZi1>
|
||||||
|
<NoZi2>0</NoZi2>
|
||||||
|
<NoZi3>0</NoZi3>
|
||||||
|
<NoZi4>0</NoZi4>
|
||||||
|
<NoZi5>0</NoZi5>
|
||||||
|
<Ro1Chk>0</Ro1Chk>
|
||||||
|
<Ro2Chk>0</Ro2Chk>
|
||||||
|
<Ro3Chk>0</Ro3Chk>
|
||||||
|
<Ir1Chk>1</Ir1Chk>
|
||||||
|
<Ir2Chk>0</Ir2Chk>
|
||||||
|
<Ra1Chk>0</Ra1Chk>
|
||||||
|
<Ra2Chk>0</Ra2Chk>
|
||||||
|
<Ra3Chk>0</Ra3Chk>
|
||||||
|
<Im1Chk>1</Im1Chk>
|
||||||
|
<Im2Chk>0</Im2Chk>
|
||||||
|
<OnChipMemories>
|
||||||
|
<Ocm1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm1>
|
||||||
|
<Ocm2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm2>
|
||||||
|
<Ocm3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm3>
|
||||||
|
<Ocm4>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm4>
|
||||||
|
<Ocm5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm5>
|
||||||
|
<Ocm6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm6>
|
||||||
|
<IRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x8000</Size>
|
||||||
|
</IRAM>
|
||||||
|
<IROM>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x40000</Size>
|
||||||
|
</IROM>
|
||||||
|
<XRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</XRAM>
|
||||||
|
<OCR_RVCT1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT1>
|
||||||
|
<OCR_RVCT2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT2>
|
||||||
|
<OCR_RVCT3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT3>
|
||||||
|
<OCR_RVCT4>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x40000</Size>
|
||||||
|
</OCR_RVCT4>
|
||||||
|
<OCR_RVCT5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT5>
|
||||||
|
<OCR_RVCT6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT6>
|
||||||
|
<OCR_RVCT7>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT7>
|
||||||
|
<OCR_RVCT8>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT8>
|
||||||
|
<OCR_RVCT9>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x8000</Size>
|
||||||
|
</OCR_RVCT9>
|
||||||
|
<OCR_RVCT10>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT10>
|
||||||
|
</OnChipMemories>
|
||||||
|
<RvctStartVector></RvctStartVector>
|
||||||
|
</ArmAdsMisc>
|
||||||
|
<Cads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Optim>1</Optim>
|
||||||
|
<oTime>0</oTime>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<OneElfS>0</OneElfS>
|
||||||
|
<Strict>0</Strict>
|
||||||
|
<EnumInt>0</EnumInt>
|
||||||
|
<PlainCh>0</PlainCh>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<wLevel>0</wLevel>
|
||||||
|
<uThumb>0</uThumb>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
|
||||||
|
<Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
<Aads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<thumb>0</thumb>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<SwStkChk>0</SwStkChk>
|
||||||
|
<NoWarn>0</NoWarn>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Aads>
|
||||||
|
<LDads>
|
||||||
|
<umfTarg>0</umfTarg>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<noStLib>0</noStLib>
|
||||||
|
<RepFail>1</RepFail>
|
||||||
|
<useFile>0</useFile>
|
||||||
|
<TextAddressRange>0x00000000</TextAddressRange>
|
||||||
|
<DataAddressRange>0x20000000</DataAddressRange>
|
||||||
|
<ScatterFile>{{scatter_file}}</ScatterFile>
|
||||||
|
<IncludeLibs></IncludeLibs>
|
||||||
|
<IncludeLibsPath></IncludeLibsPath>
|
||||||
|
<Misc>
|
||||||
|
{% for file in object_files %}
|
||||||
|
{{file}}
|
||||||
|
{% endfor %}
|
||||||
|
</Misc>
|
||||||
|
<LinkerInputFile></LinkerInputFile>
|
||||||
|
<DisabledWarnings></DisabledWarnings>
|
||||||
|
</LDads>
|
||||||
|
</TargetArmAds>
|
||||||
|
</TargetOption>
|
||||||
|
<Groups>
|
||||||
|
{% for group,files in source_files %}
|
||||||
|
<Group>
|
||||||
|
<GroupName>{{group}}</GroupName>
|
||||||
|
<Files>
|
||||||
|
{% for file in files %}
|
||||||
|
<File>
|
||||||
|
<FileName>{{file.name}}</FileName>
|
||||||
|
<FileType>{{file.type}}</FileType>
|
||||||
|
<FilePath>{{file.path}}</FilePath>
|
||||||
|
{%if file.type == "1" %}
|
||||||
|
<FileOption>
|
||||||
|
<FileArmAds>
|
||||||
|
<Cads>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls>--c99</MiscControls>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
</FileArmAds>
|
||||||
|
</FileOption>
|
||||||
|
{% endif %}
|
||||||
|
</File>
|
||||||
|
{% endfor %}
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
{% endfor %}
|
||||||
|
</Groups>
|
||||||
|
</Target>
|
||||||
|
</Targets>
|
||||||
|
|
||||||
|
</Project>
|
||||||
|
|
@ -0,0 +1,204 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.0</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Extensions>
|
||||||
|
<cExt>*.c</cExt>
|
||||||
|
<aExt>*.s*; *.src; *.a*</aExt>
|
||||||
|
<oExt>*.obj</oExt>
|
||||||
|
<lExt>*.lib</lExt>
|
||||||
|
<tExt>*.txt; *.h; *.inc</tExt>
|
||||||
|
<pExt>*.plm</pExt>
|
||||||
|
<CppX>*.cpp</CppX>
|
||||||
|
</Extensions>
|
||||||
|
|
||||||
|
<DaveTm>
|
||||||
|
<dwLowDateTime>0</dwLowDateTime>
|
||||||
|
<dwHighDateTime>0</dwHighDateTime>
|
||||||
|
</DaveTm>
|
||||||
|
|
||||||
|
<Target>
|
||||||
|
<TargetName>mbed SAMD21G18A</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<CLKADS>8000000</CLKADS>
|
||||||
|
<OPTTT>
|
||||||
|
<gFlags>1</gFlags>
|
||||||
|
<BeepAtEnd>1</BeepAtEnd>
|
||||||
|
<RunSim>1</RunSim>
|
||||||
|
<RunTarget>0</RunTarget>
|
||||||
|
</OPTTT>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<FlashByte>65535</FlashByte>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
</OPTHX>
|
||||||
|
<OPTLEX>
|
||||||
|
<PageWidth>79</PageWidth>
|
||||||
|
<PageLength>66</PageLength>
|
||||||
|
<TabStop>8</TabStop>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
</OPTLEX>
|
||||||
|
<ListingPage>
|
||||||
|
<CreateCListing>1</CreateCListing>
|
||||||
|
<CreateAListing>1</CreateAListing>
|
||||||
|
<CreateLListing>1</CreateLListing>
|
||||||
|
<CreateIListing>0</CreateIListing>
|
||||||
|
<AsmCond>1</AsmCond>
|
||||||
|
<AsmSymb>1</AsmSymb>
|
||||||
|
<AsmXref>0</AsmXref>
|
||||||
|
<CCond>1</CCond>
|
||||||
|
<CCode>0</CCode>
|
||||||
|
<CListInc>0</CListInc>
|
||||||
|
<CSymb>0</CSymb>
|
||||||
|
<LinkerCodeListing>0</LinkerCodeListing>
|
||||||
|
</ListingPage>
|
||||||
|
<OPTXL>
|
||||||
|
<LMap>1</LMap>
|
||||||
|
<LComments>1</LComments>
|
||||||
|
<LGenerateSymbols>1</LGenerateSymbols>
|
||||||
|
<LLibSym>1</LLibSym>
|
||||||
|
<LLines>1</LLines>
|
||||||
|
<LLocSym>1</LLocSym>
|
||||||
|
<LPubSym>1</LPubSym>
|
||||||
|
<LXref>0</LXref>
|
||||||
|
<LExpSel>0</LExpSel>
|
||||||
|
</OPTXL>
|
||||||
|
<OPTFL>
|
||||||
|
<tvExp>1</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<IsCurrentTarget>1</IsCurrentTarget>
|
||||||
|
</OPTFL>
|
||||||
|
<CpuCode>16</CpuCode>
|
||||||
|
<Books>
|
||||||
|
<Book>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Title>Datasheet</Title>
|
||||||
|
<Path>datashts\Atmel\SAMD21\NotYetAvailable.pdf</Path>
|
||||||
|
</Book>
|
||||||
|
<Book>
|
||||||
|
<Number>1</Number>
|
||||||
|
<Title>Technical Reference Manual</Title>
|
||||||
|
<Path>datashts\arm\cortex_m0p\r0p0\DDI0484B_CORTEX_M0P_R0P0_TRM.PDF</Path>
|
||||||
|
</Book>
|
||||||
|
<Book>
|
||||||
|
<Number>2</Number>
|
||||||
|
<Title>Generic User Guide</Title>
|
||||||
|
<Path>datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF</Path>
|
||||||
|
</Book>
|
||||||
|
</Books>
|
||||||
|
<DllOpt>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments></SimDllArguments>
|
||||||
|
<SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
|
||||||
|
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments></TargetDllArguments>
|
||||||
|
<TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
|
||||||
|
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||||
|
</DllOpt>
|
||||||
|
|
||||||
|
<DebugOpt>
|
||||||
|
<uSim>0</uSim>
|
||||||
|
<uTrg>1</uTrg>
|
||||||
|
<sLdApp>1</sLdApp>
|
||||||
|
<sGomain>1</sGomain>
|
||||||
|
<sRbreak>1</sRbreak>
|
||||||
|
<sRwatch>1</sRwatch>
|
||||||
|
<sRmem>1</sRmem>
|
||||||
|
<sRfunc>1</sRfunc>
|
||||||
|
<sRbox>1</sRbox>
|
||||||
|
<tLdApp>1</tLdApp>
|
||||||
|
<tGomain>1</tGomain>
|
||||||
|
<tRbreak>1</tRbreak>
|
||||||
|
<tRwatch>1</tRwatch>
|
||||||
|
<tRmem>1</tRmem>
|
||||||
|
<tRfunc>0</tRfunc>
|
||||||
|
<tRbox>1</tRbox>
|
||||||
|
<sRunDeb>0</sRunDeb>
|
||||||
|
<sLrtime>0</sLrtime>
|
||||||
|
<nTsel>14</nTsel>
|
||||||
|
<sDll></sDll>
|
||||||
|
<sDllPa></sDllPa>
|
||||||
|
<sDlgDll></sDlgDll>
|
||||||
|
<sDlgPa></sDlgPa>
|
||||||
|
<sIfile></sIfile>
|
||||||
|
<tDll></tDll>
|
||||||
|
<tDllPa></tDllPa>
|
||||||
|
<tDlgDll></tDlgDll>
|
||||||
|
<tDlgPa></tDlgPa>
|
||||||
|
<tIfile></tIfile>
|
||||||
|
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||||
|
</DebugOpt>
|
||||||
|
<TargetDriverDllRegistry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>UL2CM3</Key>
|
||||||
|
<Name>UL2CM3(-O207 -O207 -S9 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0ATSAMD21_256 -FL040000 -FS00</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>CMSIS_AGDI</Key>
|
||||||
|
<Name>-X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
</TargetDriverDllRegistry>
|
||||||
|
<Breakpoint/>
|
||||||
|
<DebugFlag>
|
||||||
|
<trace>0</trace>
|
||||||
|
<periodic>0</periodic>
|
||||||
|
<aLwin>0</aLwin>
|
||||||
|
<aCover>0</aCover>
|
||||||
|
<aSer1>0</aSer1>
|
||||||
|
<aSer2>0</aSer2>
|
||||||
|
<aPa>0</aPa>
|
||||||
|
<viewmode>0</viewmode>
|
||||||
|
<vrSel>0</vrSel>
|
||||||
|
<aSym>0</aSym>
|
||||||
|
<aTbox>0</aTbox>
|
||||||
|
<AscS1>0</AscS1>
|
||||||
|
<AscS2>0</AscS2>
|
||||||
|
<AscS3>0</AscS3>
|
||||||
|
<aSer3>0</aSer3>
|
||||||
|
<eProf>0</eProf>
|
||||||
|
<aLa>0</aLa>
|
||||||
|
<aPa1>0</aPa1>
|
||||||
|
<AscS4>0</AscS4>
|
||||||
|
<aSer4>0</aSer4>
|
||||||
|
<StkLoc>0</StkLoc>
|
||||||
|
<TrcWin>0</TrcWin>
|
||||||
|
<newCpu>0</newCpu>
|
||||||
|
<uProt>0</uProt>
|
||||||
|
</DebugFlag>
|
||||||
|
<LintExecutable></LintExecutable>
|
||||||
|
<LintConfigFile></LintConfigFile>
|
||||||
|
</TargetOption>
|
||||||
|
</Target>
|
||||||
|
|
||||||
|
<Group>
|
||||||
|
<GroupName>src</GroupName>
|
||||||
|
<tvExp>1</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<cbSel>0</cbSel>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>1</GroupNumber>
|
||||||
|
<FileNumber>1</FileNumber>
|
||||||
|
<FileType>8</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<TopLine>1</TopLine>
|
||||||
|
<CurrentLine>2</CurrentLine>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>main.cpp</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>main.cpp</FilenameWithoutPath>
|
||||||
|
</File>
|
||||||
|
</Group>
|
||||||
|
|
||||||
|
</ProjectOpt>
|
||||||
|
|
@ -0,0 +1,424 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.1</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Targets>
|
||||||
|
<Target>
|
||||||
|
<TargetName>SAMD21G18A</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<TargetCommonOption>
|
||||||
|
<Device>SAMD21J18A</Device>
|
||||||
|
<Vendor>Atmel</Vendor>
|
||||||
|
<Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0003FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+")</Cpu>
|
||||||
|
<FlashUtilSpec></FlashUtilSpec>
|
||||||
|
<StartupFile>"Startup\Atmel\SAMD21\startup_SAMD21.s" ("Atmel SAMD21 Startup Code")</StartupFile>
|
||||||
|
<FlashDriverDll>UL2CM3(-O207 -S9 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0ATSAMD21_256 -FS00 -FL040000)</FlashDriverDll>
|
||||||
|
<DeviceId>7346</DeviceId>
|
||||||
|
<RegisterFile>samd21.h</RegisterFile>
|
||||||
|
<MemoryEnv></MemoryEnv>
|
||||||
|
<Cmp></Cmp>
|
||||||
|
<Asm></Asm>
|
||||||
|
<Linker></Linker>
|
||||||
|
<OHString></OHString>
|
||||||
|
<InfinionOptionDll></InfinionOptionDll>
|
||||||
|
<SLE66CMisc>-D__SAMD21J18A__</SLE66CMisc>
|
||||||
|
<SLE66AMisc></SLE66AMisc>
|
||||||
|
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||||
|
<SFDFile>SFD\Atmel\SAMD21\ATSAMD21J18A.SFR</SFDFile>
|
||||||
|
<bCustSvd>0</bCustSvd>
|
||||||
|
<UseEnv>0</UseEnv>
|
||||||
|
<BinPath></BinPath>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
<LibPath></LibPath>
|
||||||
|
<RegisterFilePath>Atmel\SAMD21\</RegisterFilePath>
|
||||||
|
<DBRegisterFilePath>Atmel\SAMD21\</DBRegisterFilePath>
|
||||||
|
<TargetStatus>
|
||||||
|
<Error>0</Error>
|
||||||
|
<ExitCodeStop>0</ExitCodeStop>
|
||||||
|
<ButtonStop>0</ButtonStop>
|
||||||
|
<NotGenerated>0</NotGenerated>
|
||||||
|
<InvalidFlash>1</InvalidFlash>
|
||||||
|
</TargetStatus>
|
||||||
|
<OutputDirectory>.\build\</OutputDirectory>
|
||||||
|
<OutputName>{{name}}</OutputName>
|
||||||
|
<CreateExecutable>1</CreateExecutable>
|
||||||
|
<CreateLib>0</CreateLib>
|
||||||
|
<CreateHexFile>0</CreateHexFile>
|
||||||
|
<DebugInformation>1</DebugInformation>
|
||||||
|
<BrowseInformation>1</BrowseInformation>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
<HexFormatSelection>1</HexFormatSelection>
|
||||||
|
<Merge32K>0</Merge32K>
|
||||||
|
<CreateBatchFile>0</CreateBatchFile>
|
||||||
|
<BeforeCompile>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopU1X>0</nStopU1X>
|
||||||
|
<nStopU2X>0</nStopU2X>
|
||||||
|
</BeforeCompile>
|
||||||
|
<BeforeMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
</BeforeMake>
|
||||||
|
<AfterMake>
|
||||||
|
<RunUserProg1>1</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name>fromelf --bin -o build\{{name}}_SAMD21G18A.bin build\{{name}}.axf</UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
</AfterMake>
|
||||||
|
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||||
|
<SVCSIdString></SVCSIdString>
|
||||||
|
</TargetCommonOption>
|
||||||
|
<CommonProperty>
|
||||||
|
<UseCPPCompiler>0</UseCPPCompiler>
|
||||||
|
<RVCTCodeConst>0</RVCTCodeConst>
|
||||||
|
<RVCTZI>0</RVCTZI>
|
||||||
|
<RVCTOtherData>0</RVCTOtherData>
|
||||||
|
<ModuleSelection>0</ModuleSelection>
|
||||||
|
<IncludeInBuild>1</IncludeInBuild>
|
||||||
|
<AlwaysBuild>0</AlwaysBuild>
|
||||||
|
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||||
|
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||||
|
<PublicsOnly>0</PublicsOnly>
|
||||||
|
<StopOnExitCode>3</StopOnExitCode>
|
||||||
|
<CustomArgument></CustomArgument>
|
||||||
|
<IncludeLibraryModules></IncludeLibraryModules>
|
||||||
|
</CommonProperty>
|
||||||
|
<DllOption>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments></SimDllArguments>
|
||||||
|
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
|
||||||
|
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments></TargetDllArguments>
|
||||||
|
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
|
||||||
|
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||||
|
</DllOption>
|
||||||
|
<DebugOption>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
<Oh166RecLen>16</Oh166RecLen>
|
||||||
|
</OPTHX>
|
||||||
|
<Simulator>
|
||||||
|
<UseSimulator>0</UseSimulator>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>1</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||||
|
</Simulator>
|
||||||
|
<Target>
|
||||||
|
<UseTarget>1</UseTarget>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>0</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
</Target>
|
||||||
|
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||||
|
<TargetSelection>14</TargetSelection>
|
||||||
|
<SimDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
</SimDlls>
|
||||||
|
<TargetDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
<Driver>BIN\CMSIS_AGDI.dll</Driver>
|
||||||
|
</TargetDlls>
|
||||||
|
</DebugOption>
|
||||||
|
<Utilities>
|
||||||
|
<Flash1>
|
||||||
|
<UseTargetDll>1</UseTargetDll>
|
||||||
|
<UseExternalTool>0</UseExternalTool>
|
||||||
|
<RunIndependent>0</RunIndependent>
|
||||||
|
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||||
|
<Capability>1</Capability>
|
||||||
|
<DriverSelection>4105</DriverSelection>
|
||||||
|
</Flash1>
|
||||||
|
<Flash2>BIN\CMSIS_AGDI.dll</Flash2>
|
||||||
|
<Flash3>"" ()</Flash3>
|
||||||
|
<Flash4></Flash4>
|
||||||
|
</Utilities>
|
||||||
|
<TargetArmAds>
|
||||||
|
<ArmAdsMisc>
|
||||||
|
<GenerateListings>0</GenerateListings>
|
||||||
|
<asHll>1</asHll>
|
||||||
|
<asAsm>1</asAsm>
|
||||||
|
<asMacX>1</asMacX>
|
||||||
|
<asSyms>1</asSyms>
|
||||||
|
<asFals>1</asFals>
|
||||||
|
<asDbgD>1</asDbgD>
|
||||||
|
<asForm>1</asForm>
|
||||||
|
<ldLst>0</ldLst>
|
||||||
|
<ldmm>1</ldmm>
|
||||||
|
<ldXref>1</ldXref>
|
||||||
|
<BigEnd>0</BigEnd>
|
||||||
|
<AdsALst>1</AdsALst>
|
||||||
|
<AdsACrf>1</AdsACrf>
|
||||||
|
<AdsANop>0</AdsANop>
|
||||||
|
<AdsANot>0</AdsANot>
|
||||||
|
<AdsLLst>1</AdsLLst>
|
||||||
|
<AdsLmap>1</AdsLmap>
|
||||||
|
<AdsLcgr>1</AdsLcgr>
|
||||||
|
<AdsLsym>1</AdsLsym>
|
||||||
|
<AdsLszi>1</AdsLszi>
|
||||||
|
<AdsLtoi>1</AdsLtoi>
|
||||||
|
<AdsLsun>1</AdsLsun>
|
||||||
|
<AdsLven>1</AdsLven>
|
||||||
|
<AdsLsxf>1</AdsLsxf>
|
||||||
|
<RvctClst>0</RvctClst>
|
||||||
|
<GenPPlst>0</GenPPlst>
|
||||||
|
<AdsCpuType>"Cortex-M0+"</AdsCpuType>
|
||||||
|
<RvctDeviceName></RvctDeviceName>
|
||||||
|
<mOS>0</mOS>
|
||||||
|
<uocRom>0</uocRom>
|
||||||
|
<uocRam>0</uocRam>
|
||||||
|
<hadIROM>1</hadIROM>
|
||||||
|
<hadIRAM>1</hadIRAM>
|
||||||
|
<hadXRAM>0</hadXRAM>
|
||||||
|
<uocXRam>0</uocXRam>
|
||||||
|
<RvdsVP>0</RvdsVP>
|
||||||
|
<hadIRAM2>1</hadIRAM2>
|
||||||
|
<hadIROM2>0</hadIROM2>
|
||||||
|
<StupSel>8</StupSel>
|
||||||
|
<useUlib>0</useUlib>
|
||||||
|
<EndSel>0</EndSel>
|
||||||
|
<uLtcg>0</uLtcg>
|
||||||
|
<RoSelD>3</RoSelD>
|
||||||
|
<RwSelD>3</RwSelD>
|
||||||
|
<CodeSel>0</CodeSel>
|
||||||
|
<OptFeed>0</OptFeed>
|
||||||
|
<NoZi1>0</NoZi1>
|
||||||
|
<NoZi2>0</NoZi2>
|
||||||
|
<NoZi3>0</NoZi3>
|
||||||
|
<NoZi4>0</NoZi4>
|
||||||
|
<NoZi5>0</NoZi5>
|
||||||
|
<Ro1Chk>0</Ro1Chk>
|
||||||
|
<Ro2Chk>0</Ro2Chk>
|
||||||
|
<Ro3Chk>0</Ro3Chk>
|
||||||
|
<Ir1Chk>1</Ir1Chk>
|
||||||
|
<Ir2Chk>0</Ir2Chk>
|
||||||
|
<Ra1Chk>0</Ra1Chk>
|
||||||
|
<Ra2Chk>0</Ra2Chk>
|
||||||
|
<Ra3Chk>0</Ra3Chk>
|
||||||
|
<Im1Chk>1</Im1Chk>
|
||||||
|
<Im2Chk>0</Im2Chk>
|
||||||
|
<OnChipMemories>
|
||||||
|
<Ocm1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm1>
|
||||||
|
<Ocm2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm2>
|
||||||
|
<Ocm3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm3>
|
||||||
|
<Ocm4>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm4>
|
||||||
|
<Ocm5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm5>
|
||||||
|
<Ocm6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm6>
|
||||||
|
<IRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x8000</Size>
|
||||||
|
</IRAM>
|
||||||
|
<IROM>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x40000</Size>
|
||||||
|
</IROM>
|
||||||
|
<XRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</XRAM>
|
||||||
|
<OCR_RVCT1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT1>
|
||||||
|
<OCR_RVCT2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT2>
|
||||||
|
<OCR_RVCT3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT3>
|
||||||
|
<OCR_RVCT4>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x40000</Size>
|
||||||
|
</OCR_RVCT4>
|
||||||
|
<OCR_RVCT5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT5>
|
||||||
|
<OCR_RVCT6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT6>
|
||||||
|
<OCR_RVCT7>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT7>
|
||||||
|
<OCR_RVCT8>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT8>
|
||||||
|
<OCR_RVCT9>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x8000</Size>
|
||||||
|
</OCR_RVCT9>
|
||||||
|
<OCR_RVCT10>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT10>
|
||||||
|
</OnChipMemories>
|
||||||
|
<RvctStartVector></RvctStartVector>
|
||||||
|
</ArmAdsMisc>
|
||||||
|
<Cads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Optim>1</Optim>
|
||||||
|
<oTime>0</oTime>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<OneElfS>0</OneElfS>
|
||||||
|
<Strict>0</Strict>
|
||||||
|
<EnumInt>0</EnumInt>
|
||||||
|
<PlainCh>0</PlainCh>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<wLevel>0</wLevel>
|
||||||
|
<uThumb>0</uThumb>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
|
||||||
|
<Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
<Aads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<thumb>0</thumb>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<SwStkChk>0</SwStkChk>
|
||||||
|
<NoWarn>0</NoWarn>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Aads>
|
||||||
|
<LDads>
|
||||||
|
<umfTarg>0</umfTarg>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<noStLib>0</noStLib>
|
||||||
|
<RepFail>1</RepFail>
|
||||||
|
<useFile>0</useFile>
|
||||||
|
<TextAddressRange>0x00000000</TextAddressRange>
|
||||||
|
<DataAddressRange>0x20000000</DataAddressRange>
|
||||||
|
<ScatterFile>{{scatter_file}}</ScatterFile>
|
||||||
|
<IncludeLibs></IncludeLibs>
|
||||||
|
<IncludeLibsPath></IncludeLibsPath>
|
||||||
|
<Misc>
|
||||||
|
{% for file in object_files %}
|
||||||
|
{{file}}
|
||||||
|
{% endfor %}
|
||||||
|
</Misc>
|
||||||
|
<LinkerInputFile></LinkerInputFile>
|
||||||
|
<DisabledWarnings></DisabledWarnings>
|
||||||
|
</LDads>
|
||||||
|
</TargetArmAds>
|
||||||
|
</TargetOption>
|
||||||
|
<Groups>
|
||||||
|
{% for group,files in source_files %}
|
||||||
|
<Group>
|
||||||
|
<GroupName>{{group}}</GroupName>
|
||||||
|
<Files>
|
||||||
|
{% for file in files %}
|
||||||
|
<File>
|
||||||
|
<FileName>{{file.name}}</FileName>
|
||||||
|
<FileType>{{file.type}}</FileType>
|
||||||
|
<FilePath>{{file.path}}</FilePath>
|
||||||
|
{%if file.type == "1" %}
|
||||||
|
<FileOption>
|
||||||
|
<FileArmAds>
|
||||||
|
<Cads>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls>--c99</MiscControls>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
</FileArmAds>
|
||||||
|
</FileOption>
|
||||||
|
{% endif %}
|
||||||
|
</File>
|
||||||
|
{% endfor %}
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
{% endfor %}
|
||||||
|
</Groups>
|
||||||
|
</Target>
|
||||||
|
</Targets>
|
||||||
|
|
||||||
|
</Project>
|
||||||
|
|
@ -0,0 +1,204 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.0</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Extensions>
|
||||||
|
<cExt>*.c</cExt>
|
||||||
|
<aExt>*.s*; *.src; *.a*</aExt>
|
||||||
|
<oExt>*.obj</oExt>
|
||||||
|
<lExt>*.lib</lExt>
|
||||||
|
<tExt>*.txt; *.h; *.inc</tExt>
|
||||||
|
<pExt>*.plm</pExt>
|
||||||
|
<CppX>*.cpp</CppX>
|
||||||
|
</Extensions>
|
||||||
|
|
||||||
|
<DaveTm>
|
||||||
|
<dwLowDateTime>0</dwLowDateTime>
|
||||||
|
<dwHighDateTime>0</dwHighDateTime>
|
||||||
|
</DaveTm>
|
||||||
|
|
||||||
|
<Target>
|
||||||
|
<TargetName>mbed SAMR21G18A</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<CLKADS>8000000</CLKADS>
|
||||||
|
<OPTTT>
|
||||||
|
<gFlags>1</gFlags>
|
||||||
|
<BeepAtEnd>1</BeepAtEnd>
|
||||||
|
<RunSim>1</RunSim>
|
||||||
|
<RunTarget>0</RunTarget>
|
||||||
|
</OPTTT>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<FlashByte>65535</FlashByte>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
</OPTHX>
|
||||||
|
<OPTLEX>
|
||||||
|
<PageWidth>79</PageWidth>
|
||||||
|
<PageLength>66</PageLength>
|
||||||
|
<TabStop>8</TabStop>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
</OPTLEX>
|
||||||
|
<ListingPage>
|
||||||
|
<CreateCListing>1</CreateCListing>
|
||||||
|
<CreateAListing>1</CreateAListing>
|
||||||
|
<CreateLListing>1</CreateLListing>
|
||||||
|
<CreateIListing>0</CreateIListing>
|
||||||
|
<AsmCond>1</AsmCond>
|
||||||
|
<AsmSymb>1</AsmSymb>
|
||||||
|
<AsmXref>0</AsmXref>
|
||||||
|
<CCond>1</CCond>
|
||||||
|
<CCode>0</CCode>
|
||||||
|
<CListInc>0</CListInc>
|
||||||
|
<CSymb>0</CSymb>
|
||||||
|
<LinkerCodeListing>0</LinkerCodeListing>
|
||||||
|
</ListingPage>
|
||||||
|
<OPTXL>
|
||||||
|
<LMap>1</LMap>
|
||||||
|
<LComments>1</LComments>
|
||||||
|
<LGenerateSymbols>1</LGenerateSymbols>
|
||||||
|
<LLibSym>1</LLibSym>
|
||||||
|
<LLines>1</LLines>
|
||||||
|
<LLocSym>1</LLocSym>
|
||||||
|
<LPubSym>1</LPubSym>
|
||||||
|
<LXref>0</LXref>
|
||||||
|
<LExpSel>0</LExpSel>
|
||||||
|
</OPTXL>
|
||||||
|
<OPTFL>
|
||||||
|
<tvExp>1</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<IsCurrentTarget>1</IsCurrentTarget>
|
||||||
|
</OPTFL>
|
||||||
|
<CpuCode>14</CpuCode>
|
||||||
|
<Books>
|
||||||
|
<Book>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Title>Datasheet</Title>
|
||||||
|
<Path>datashts\Atmel\SAMD21\NotYetAvailable.pdf</Path>
|
||||||
|
</Book>
|
||||||
|
<Book>
|
||||||
|
<Number>1</Number>
|
||||||
|
<Title>Technical Reference Manual</Title>
|
||||||
|
<Path>datashts\arm\cortex_m0p\r0p0\DDI0484B_CORTEX_M0P_R0P0_TRM.PDF</Path>
|
||||||
|
</Book>
|
||||||
|
<Book>
|
||||||
|
<Number>2</Number>
|
||||||
|
<Title>Generic User Guide</Title>
|
||||||
|
<Path>datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF</Path>
|
||||||
|
</Book>
|
||||||
|
</Books>
|
||||||
|
<DllOpt>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments></SimDllArguments>
|
||||||
|
<SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
|
||||||
|
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments></TargetDllArguments>
|
||||||
|
<TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
|
||||||
|
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||||
|
</DllOpt>
|
||||||
|
|
||||||
|
<DebugOpt>
|
||||||
|
<uSim>0</uSim>
|
||||||
|
<uTrg>1</uTrg>
|
||||||
|
<sLdApp>1</sLdApp>
|
||||||
|
<sGomain>1</sGomain>
|
||||||
|
<sRbreak>1</sRbreak>
|
||||||
|
<sRwatch>1</sRwatch>
|
||||||
|
<sRmem>1</sRmem>
|
||||||
|
<sRfunc>1</sRfunc>
|
||||||
|
<sRbox>1</sRbox>
|
||||||
|
<tLdApp>1</tLdApp>
|
||||||
|
<tGomain>1</tGomain>
|
||||||
|
<tRbreak>1</tRbreak>
|
||||||
|
<tRwatch>1</tRwatch>
|
||||||
|
<tRmem>1</tRmem>
|
||||||
|
<tRfunc>0</tRfunc>
|
||||||
|
<tRbox>1</tRbox>
|
||||||
|
<sRunDeb>0</sRunDeb>
|
||||||
|
<sLrtime>0</sLrtime>
|
||||||
|
<nTsel>14</nTsel>
|
||||||
|
<sDll></sDll>
|
||||||
|
<sDllPa></sDllPa>
|
||||||
|
<sDlgDll></sDlgDll>
|
||||||
|
<sDlgPa></sDlgPa>
|
||||||
|
<sIfile></sIfile>
|
||||||
|
<tDll></tDll>
|
||||||
|
<tDllPa></tDllPa>
|
||||||
|
<tDlgDll></tDlgDll>
|
||||||
|
<tDlgPa></tDlgPa>
|
||||||
|
<tIfile></tIfile>
|
||||||
|
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||||
|
</DebugOpt>
|
||||||
|
<TargetDriverDllRegistry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>ULP2CM3</Key>
|
||||||
|
<Name>-O207 -O207 -S9 -C0 -FO7 -FN1 -FC800 -FD20000000 -FF0ATSAMR21_256 -FL040000 -FS00</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
<SetRegEntry>
|
||||||
|
<Number>0</Number>
|
||||||
|
<Key>CMSIS_AGDI</Key>
|
||||||
|
<Name>-X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000</Name>
|
||||||
|
</SetRegEntry>
|
||||||
|
</TargetDriverDllRegistry>
|
||||||
|
<Breakpoint/>
|
||||||
|
<DebugFlag>
|
||||||
|
<trace>0</trace>
|
||||||
|
<periodic>0</periodic>
|
||||||
|
<aLwin>0</aLwin>
|
||||||
|
<aCover>0</aCover>
|
||||||
|
<aSer1>0</aSer1>
|
||||||
|
<aSer2>0</aSer2>
|
||||||
|
<aPa>0</aPa>
|
||||||
|
<viewmode>0</viewmode>
|
||||||
|
<vrSel>0</vrSel>
|
||||||
|
<aSym>0</aSym>
|
||||||
|
<aTbox>0</aTbox>
|
||||||
|
<AscS1>0</AscS1>
|
||||||
|
<AscS2>0</AscS2>
|
||||||
|
<AscS3>0</AscS3>
|
||||||
|
<aSer3>0</aSer3>
|
||||||
|
<eProf>0</eProf>
|
||||||
|
<aLa>0</aLa>
|
||||||
|
<aPa1>0</aPa1>
|
||||||
|
<AscS4>0</AscS4>
|
||||||
|
<aSer4>0</aSer4>
|
||||||
|
<StkLoc>0</StkLoc>
|
||||||
|
<TrcWin>0</TrcWin>
|
||||||
|
<newCpu>0</newCpu>
|
||||||
|
<uProt>0</uProt>
|
||||||
|
</DebugFlag>
|
||||||
|
<LintExecutable></LintExecutable>
|
||||||
|
<LintConfigFile></LintConfigFile>
|
||||||
|
</TargetOption>
|
||||||
|
</Target>
|
||||||
|
|
||||||
|
<Group>
|
||||||
|
<GroupName>src</GroupName>
|
||||||
|
<tvExp>1</tvExp>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<cbSel>0</cbSel>
|
||||||
|
<File>
|
||||||
|
<GroupNumber>1</GroupNumber>
|
||||||
|
<FileNumber>1</FileNumber>
|
||||||
|
<FileType>8</FileType>
|
||||||
|
<tvExp>0</tvExp>
|
||||||
|
<Focus>0</Focus>
|
||||||
|
<ColumnNumber>0</ColumnNumber>
|
||||||
|
<tvExpOptDlg>0</tvExpOptDlg>
|
||||||
|
<TopLine>1</TopLine>
|
||||||
|
<CurrentLine>2</CurrentLine>
|
||||||
|
<bDave2>0</bDave2>
|
||||||
|
<PathWithFileName>main.cpp</PathWithFileName>
|
||||||
|
<FilenameWithoutPath>main.cpp</FilenameWithoutPath>
|
||||||
|
</File>
|
||||||
|
</Group>
|
||||||
|
|
||||||
|
</ProjectOpt>
|
||||||
|
|
@ -0,0 +1,424 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||||
|
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||||
|
|
||||||
|
<SchemaVersion>1.1</SchemaVersion>
|
||||||
|
|
||||||
|
<Header>### uVision Project, (C) Keil Software</Header>
|
||||||
|
|
||||||
|
<Targets>
|
||||||
|
<Target>
|
||||||
|
<TargetName>SAMR21G18A</TargetName>
|
||||||
|
<ToolsetNumber>0x4</ToolsetNumber>
|
||||||
|
<ToolsetName>ARM-ADS</ToolsetName>
|
||||||
|
<TargetOption>
|
||||||
|
<TargetCommonOption>
|
||||||
|
<Device>SAMR21G18A</Device>
|
||||||
|
<Vendor>Atmel</Vendor>
|
||||||
|
<Cpu>IRAM(0x20000000-0x20007FFF) IROM(0x00000000-0x0003FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+")</Cpu>
|
||||||
|
<FlashUtilSpec></FlashUtilSpec>
|
||||||
|
<StartupFile>"Startup\Atmel\SAMR21\startup_SAMR21.s" ("Atmel SAMR21 Startup Code")</StartupFile>
|
||||||
|
<FlashDriverDll>UL2CM3(-O207 -S9 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0ATSAMR21_256 -FS00 -FL040000)</FlashDriverDll>
|
||||||
|
<DeviceId>7537</DeviceId>
|
||||||
|
<RegisterFile>samr21.h</RegisterFile>
|
||||||
|
<MemoryEnv></MemoryEnv>
|
||||||
|
<Cmp></Cmp>
|
||||||
|
<Asm></Asm>
|
||||||
|
<Linker></Linker>
|
||||||
|
<OHString></OHString>
|
||||||
|
<InfinionOptionDll></InfinionOptionDll>
|
||||||
|
<SLE66CMisc>-D__SAMR21G18A__</SLE66CMisc>
|
||||||
|
<SLE66AMisc></SLE66AMisc>
|
||||||
|
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||||
|
<SFDFile>SFD\Atmel\SAMR21\ATSAMR21G18A.SFR</SFDFile>
|
||||||
|
<bCustSvd>0</bCustSvd>
|
||||||
|
<UseEnv>0</UseEnv>
|
||||||
|
<BinPath></BinPath>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
<LibPath></LibPath>
|
||||||
|
<RegisterFilePath>Atmel\SAMR21\</RegisterFilePath>
|
||||||
|
<DBRegisterFilePath>Atmel\SAMR21\</DBRegisterFilePath>
|
||||||
|
<TargetStatus>
|
||||||
|
<Error>0</Error>
|
||||||
|
<ExitCodeStop>0</ExitCodeStop>
|
||||||
|
<ButtonStop>0</ButtonStop>
|
||||||
|
<NotGenerated>0</NotGenerated>
|
||||||
|
<InvalidFlash>1</InvalidFlash>
|
||||||
|
</TargetStatus>
|
||||||
|
<OutputDirectory>.\build\</OutputDirectory>
|
||||||
|
<OutputName>{{name}}</OutputName>
|
||||||
|
<CreateExecutable>1</CreateExecutable>
|
||||||
|
<CreateLib>0</CreateLib>
|
||||||
|
<CreateHexFile>0</CreateHexFile>
|
||||||
|
<DebugInformation>1</DebugInformation>
|
||||||
|
<BrowseInformation>1</BrowseInformation>
|
||||||
|
<ListingPath>.\build\</ListingPath>
|
||||||
|
<HexFormatSelection>1</HexFormatSelection>
|
||||||
|
<Merge32K>0</Merge32K>
|
||||||
|
<CreateBatchFile>0</CreateBatchFile>
|
||||||
|
<BeforeCompile>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
<nStopU1X>0</nStopU1X>
|
||||||
|
<nStopU2X>0</nStopU2X>
|
||||||
|
</BeforeCompile>
|
||||||
|
<BeforeMake>
|
||||||
|
<RunUserProg1>0</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name></UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
</BeforeMake>
|
||||||
|
<AfterMake>
|
||||||
|
<RunUserProg1>1</RunUserProg1>
|
||||||
|
<RunUserProg2>0</RunUserProg2>
|
||||||
|
<UserProg1Name>fromelf --bin -o build\{{name}}_SAMR21G18A.bin build\{{name}}.axf</UserProg1Name>
|
||||||
|
<UserProg2Name></UserProg2Name>
|
||||||
|
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||||
|
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||||
|
</AfterMake>
|
||||||
|
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||||
|
<SVCSIdString></SVCSIdString>
|
||||||
|
</TargetCommonOption>
|
||||||
|
<CommonProperty>
|
||||||
|
<UseCPPCompiler>0</UseCPPCompiler>
|
||||||
|
<RVCTCodeConst>0</RVCTCodeConst>
|
||||||
|
<RVCTZI>0</RVCTZI>
|
||||||
|
<RVCTOtherData>0</RVCTOtherData>
|
||||||
|
<ModuleSelection>0</ModuleSelection>
|
||||||
|
<IncludeInBuild>1</IncludeInBuild>
|
||||||
|
<AlwaysBuild>0</AlwaysBuild>
|
||||||
|
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||||
|
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||||
|
<PublicsOnly>0</PublicsOnly>
|
||||||
|
<StopOnExitCode>3</StopOnExitCode>
|
||||||
|
<CustomArgument></CustomArgument>
|
||||||
|
<IncludeLibraryModules></IncludeLibraryModules>
|
||||||
|
</CommonProperty>
|
||||||
|
<DllOption>
|
||||||
|
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||||
|
<SimDllArguments></SimDllArguments>
|
||||||
|
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
|
||||||
|
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||||
|
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||||
|
<TargetDllArguments></TargetDllArguments>
|
||||||
|
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
|
||||||
|
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||||
|
</DllOption>
|
||||||
|
<DebugOption>
|
||||||
|
<OPTHX>
|
||||||
|
<HexSelection>1</HexSelection>
|
||||||
|
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||||
|
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||||
|
<HexOffset>0</HexOffset>
|
||||||
|
<Oh166RecLen>16</Oh166RecLen>
|
||||||
|
</OPTHX>
|
||||||
|
<Simulator>
|
||||||
|
<UseSimulator>0</UseSimulator>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>1</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||||
|
</Simulator>
|
||||||
|
<Target>
|
||||||
|
<UseTarget>1</UseTarget>
|
||||||
|
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||||
|
<RunToMain>1</RunToMain>
|
||||||
|
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||||
|
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||||
|
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||||
|
<RestoreFunctions>0</RestoreFunctions>
|
||||||
|
<RestoreToolbox>1</RestoreToolbox>
|
||||||
|
</Target>
|
||||||
|
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||||
|
<TargetSelection>14</TargetSelection>
|
||||||
|
<SimDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
</SimDlls>
|
||||||
|
<TargetDlls>
|
||||||
|
<CpuDll></CpuDll>
|
||||||
|
<CpuDllArguments></CpuDllArguments>
|
||||||
|
<PeripheralDll></PeripheralDll>
|
||||||
|
<PeripheralDllArguments></PeripheralDllArguments>
|
||||||
|
<InitializationFile></InitializationFile>
|
||||||
|
<Driver>BIN\CMSIS_AGDI.dll</Driver>
|
||||||
|
</TargetDlls>
|
||||||
|
</DebugOption>
|
||||||
|
<Utilities>
|
||||||
|
<Flash1>
|
||||||
|
<UseTargetDll>1</UseTargetDll>
|
||||||
|
<UseExternalTool>0</UseExternalTool>
|
||||||
|
<RunIndependent>0</RunIndependent>
|
||||||
|
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||||
|
<Capability>1</Capability>
|
||||||
|
<DriverSelection>4105</DriverSelection>
|
||||||
|
</Flash1>
|
||||||
|
<Flash2>BIN\CMSIS_AGDI.dll</Flash2>
|
||||||
|
<Flash3>"" ()</Flash3>
|
||||||
|
<Flash4></Flash4>
|
||||||
|
</Utilities>
|
||||||
|
<TargetArmAds>
|
||||||
|
<ArmAdsMisc>
|
||||||
|
<GenerateListings>0</GenerateListings>
|
||||||
|
<asHll>1</asHll>
|
||||||
|
<asAsm>1</asAsm>
|
||||||
|
<asMacX>1</asMacX>
|
||||||
|
<asSyms>1</asSyms>
|
||||||
|
<asFals>1</asFals>
|
||||||
|
<asDbgD>1</asDbgD>
|
||||||
|
<asForm>1</asForm>
|
||||||
|
<ldLst>0</ldLst>
|
||||||
|
<ldmm>1</ldmm>
|
||||||
|
<ldXref>1</ldXref>
|
||||||
|
<BigEnd>0</BigEnd>
|
||||||
|
<AdsALst>1</AdsALst>
|
||||||
|
<AdsACrf>1</AdsACrf>
|
||||||
|
<AdsANop>0</AdsANop>
|
||||||
|
<AdsANot>0</AdsANot>
|
||||||
|
<AdsLLst>1</AdsLLst>
|
||||||
|
<AdsLmap>1</AdsLmap>
|
||||||
|
<AdsLcgr>1</AdsLcgr>
|
||||||
|
<AdsLsym>1</AdsLsym>
|
||||||
|
<AdsLszi>1</AdsLszi>
|
||||||
|
<AdsLtoi>1</AdsLtoi>
|
||||||
|
<AdsLsun>1</AdsLsun>
|
||||||
|
<AdsLven>1</AdsLven>
|
||||||
|
<AdsLsxf>1</AdsLsxf>
|
||||||
|
<RvctClst>0</RvctClst>
|
||||||
|
<GenPPlst>0</GenPPlst>
|
||||||
|
<AdsCpuType>"Cortex-M0+"</AdsCpuType>
|
||||||
|
<RvctDeviceName></RvctDeviceName>
|
||||||
|
<mOS>0</mOS>
|
||||||
|
<uocRom>0</uocRom>
|
||||||
|
<uocRam>0</uocRam>
|
||||||
|
<hadIROM>1</hadIROM>
|
||||||
|
<hadIRAM>1</hadIRAM>
|
||||||
|
<hadXRAM>0</hadXRAM>
|
||||||
|
<uocXRam>0</uocXRam>
|
||||||
|
<RvdsVP>0</RvdsVP>
|
||||||
|
<hadIRAM2>1</hadIRAM2>
|
||||||
|
<hadIROM2>0</hadIROM2>
|
||||||
|
<StupSel>8</StupSel>
|
||||||
|
<useUlib>0</useUlib>
|
||||||
|
<EndSel>0</EndSel>
|
||||||
|
<uLtcg>0</uLtcg>
|
||||||
|
<RoSelD>3</RoSelD>
|
||||||
|
<RwSelD>3</RwSelD>
|
||||||
|
<CodeSel>0</CodeSel>
|
||||||
|
<OptFeed>0</OptFeed>
|
||||||
|
<NoZi1>0</NoZi1>
|
||||||
|
<NoZi2>0</NoZi2>
|
||||||
|
<NoZi3>0</NoZi3>
|
||||||
|
<NoZi4>0</NoZi4>
|
||||||
|
<NoZi5>0</NoZi5>
|
||||||
|
<Ro1Chk>0</Ro1Chk>
|
||||||
|
<Ro2Chk>0</Ro2Chk>
|
||||||
|
<Ro3Chk>0</Ro3Chk>
|
||||||
|
<Ir1Chk>1</Ir1Chk>
|
||||||
|
<Ir2Chk>0</Ir2Chk>
|
||||||
|
<Ra1Chk>0</Ra1Chk>
|
||||||
|
<Ra2Chk>0</Ra2Chk>
|
||||||
|
<Ra3Chk>0</Ra3Chk>
|
||||||
|
<Im1Chk>1</Im1Chk>
|
||||||
|
<Im2Chk>0</Im2Chk>
|
||||||
|
<OnChipMemories>
|
||||||
|
<Ocm1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm1>
|
||||||
|
<Ocm2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm2>
|
||||||
|
<Ocm3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm3>
|
||||||
|
<Ocm4>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm4>
|
||||||
|
<Ocm5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm5>
|
||||||
|
<Ocm6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</Ocm6>
|
||||||
|
<IRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x8000</Size>
|
||||||
|
</IRAM>
|
||||||
|
<IROM>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x40000</Size>
|
||||||
|
</IROM>
|
||||||
|
<XRAM>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</XRAM>
|
||||||
|
<OCR_RVCT1>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT1>
|
||||||
|
<OCR_RVCT2>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT2>
|
||||||
|
<OCR_RVCT3>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT3>
|
||||||
|
<OCR_RVCT4>
|
||||||
|
<Type>1</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x40000</Size>
|
||||||
|
</OCR_RVCT4>
|
||||||
|
<OCR_RVCT5>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT5>
|
||||||
|
<OCR_RVCT6>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT6>
|
||||||
|
<OCR_RVCT7>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT7>
|
||||||
|
<OCR_RVCT8>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT8>
|
||||||
|
<OCR_RVCT9>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x20000000</StartAddress>
|
||||||
|
<Size>0x8000</Size>
|
||||||
|
</OCR_RVCT9>
|
||||||
|
<OCR_RVCT10>
|
||||||
|
<Type>0</Type>
|
||||||
|
<StartAddress>0x0</StartAddress>
|
||||||
|
<Size>0x0</Size>
|
||||||
|
</OCR_RVCT10>
|
||||||
|
</OnChipMemories>
|
||||||
|
<RvctStartVector></RvctStartVector>
|
||||||
|
</ArmAdsMisc>
|
||||||
|
<Cads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Optim>1</Optim>
|
||||||
|
<oTime>0</oTime>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<OneElfS>0</OneElfS>
|
||||||
|
<Strict>0</Strict>
|
||||||
|
<EnumInt>0</EnumInt>
|
||||||
|
<PlainCh>0</PlainCh>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<wLevel>0</wLevel>
|
||||||
|
<uThumb>0</uThumb>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
|
||||||
|
<Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
<Aads>
|
||||||
|
<interw>1</interw>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<thumb>0</thumb>
|
||||||
|
<SplitLS>0</SplitLS>
|
||||||
|
<SwStkChk>0</SwStkChk>
|
||||||
|
<NoWarn>0</NoWarn>
|
||||||
|
<uSurpInc>0</uSurpInc>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls></MiscControls>
|
||||||
|
<Define></Define>
|
||||||
|
<Undefine></Undefine>
|
||||||
|
<IncludePath></IncludePath>
|
||||||
|
</VariousControls>
|
||||||
|
</Aads>
|
||||||
|
<LDads>
|
||||||
|
<umfTarg>0</umfTarg>
|
||||||
|
<Ropi>0</Ropi>
|
||||||
|
<Rwpi>0</Rwpi>
|
||||||
|
<noStLib>0</noStLib>
|
||||||
|
<RepFail>1</RepFail>
|
||||||
|
<useFile>0</useFile>
|
||||||
|
<TextAddressRange>0x00000000</TextAddressRange>
|
||||||
|
<DataAddressRange>0x20000000</DataAddressRange>
|
||||||
|
<ScatterFile>{{scatter_file}}</ScatterFile>
|
||||||
|
<IncludeLibs></IncludeLibs>
|
||||||
|
<IncludeLibsPath></IncludeLibsPath>
|
||||||
|
<Misc>
|
||||||
|
{% for file in object_files %}
|
||||||
|
{{file}}
|
||||||
|
{% endfor %}
|
||||||
|
</Misc>
|
||||||
|
<LinkerInputFile></LinkerInputFile>
|
||||||
|
<DisabledWarnings></DisabledWarnings>
|
||||||
|
</LDads>
|
||||||
|
</TargetArmAds>
|
||||||
|
</TargetOption>
|
||||||
|
<Groups>
|
||||||
|
{% for group,files in source_files %}
|
||||||
|
<Group>
|
||||||
|
<GroupName>{{group}}</GroupName>
|
||||||
|
<Files>
|
||||||
|
{% for file in files %}
|
||||||
|
<File>
|
||||||
|
<FileName>{{file.name}}</FileName>
|
||||||
|
<FileType>{{file.type}}</FileType>
|
||||||
|
<FilePath>{{file.path}}</FilePath>
|
||||||
|
{%if file.type == "1" %}
|
||||||
|
<FileOption>
|
||||||
|
<FileArmAds>
|
||||||
|
<Cads>
|
||||||
|
<VariousControls>
|
||||||
|
<MiscControls>--c99</MiscControls>
|
||||||
|
</VariousControls>
|
||||||
|
</Cads>
|
||||||
|
</FileArmAds>
|
||||||
|
</FileOption>
|
||||||
|
{% endif %}
|
||||||
|
</File>
|
||||||
|
{% endfor %}
|
||||||
|
</Files>
|
||||||
|
</Group>
|
||||||
|
{% endfor %}
|
||||||
|
</Groups>
|
||||||
|
</Target>
|
||||||
|
</Targets>
|
||||||
|
|
||||||
|
</Project>
|
||||||
|
|
@ -1642,7 +1642,7 @@ class SAMR21G18A(Target):
|
||||||
self.core = "Cortex-M0+"
|
self.core = "Cortex-M0+"
|
||||||
self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMR21']
|
self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMR21']
|
||||||
self.macros = ['__SAMR21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
|
self.macros = ['__SAMR21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
|
||||||
self.supported_toolchains = ["GCC_ARM"]
|
self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"]
|
||||||
self.default_toolchain = "ARM"
|
self.default_toolchain = "ARM"
|
||||||
|
|
||||||
class SAMD21J18A(Target):
|
class SAMD21J18A(Target):
|
||||||
|
|
@ -1651,7 +1651,7 @@ class SAMD21J18A(Target):
|
||||||
self.core = "Cortex-M0+"
|
self.core = "Cortex-M0+"
|
||||||
self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMD21']
|
self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMD21']
|
||||||
self.macros = ['__SAMD21J18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
|
self.macros = ['__SAMD21J18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
|
||||||
self.supported_toolchains = ["GCC_ARM"]
|
self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"]
|
||||||
self.default_toolchain = "ARM"
|
self.default_toolchain = "ARM"
|
||||||
|
|
||||||
class SAMD21G18A(Target):
|
class SAMD21G18A(Target):
|
||||||
|
|
@ -1660,7 +1660,7 @@ class SAMD21G18A(Target):
|
||||||
self.core = "Cortex-M0+"
|
self.core = "Cortex-M0+"
|
||||||
self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMD21']
|
self.extra_labels = ['Atmel', 'SAM_CortexM0+', 'SAMD21']
|
||||||
self.macros = ['__SAMD21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
|
self.macros = ['__SAMD21G18A__', 'I2C_MASTER_CALLBACK_MODE=true', 'EXTINT_CALLBACK_MODE=true', 'USART_CALLBACK_MODE=true', 'TC_ASYNC=true']
|
||||||
self.supported_toolchains = ["GCC_ARM"]
|
self.supported_toolchains = ["GCC_ARM", "ARM", "uARM"]
|
||||||
self.default_toolchain = "ARM"
|
self.default_toolchain = "ARM"
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue