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M263: delete 2 redundant files

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cyliangtw 2019-06-13 15:31:59 +08:00
parent e46cf83850
commit b9a2e06a1a
2 changed files with 0 additions and 1202 deletions
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600
targets/TARGET_NUVOTON/TARGET_M261/device/Reg/M261.h
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/**************************************************************************//**
* @file M261.h
* @version V1.0
* @brief Peripheral Access Layer Header File
*
* @note
* Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
/**
\mainpage Introduction
*
*
* This user manual describes the usage of M261 device driver
*
* <b>Disclaimer</b>
*
* The Software is furnished "AS IS", without warranty as to performance or results, and
* the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
* warranties, express, implied or otherwise, with regard to the Software, its use, or
* operation, including without limitation any and all warranties of merchantability, fitness
* for a particular purpose, and non-infringement of intellectual property rights.
*
* <b>Copyright Notice</b>
*
* Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*/
#ifndef __M261_H__
#define __M261_H__
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup CMSIS_Device CMSIS Definitions
Configuration of the Cortex-M23 Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
/**
* @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
*/
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M23 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M23 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M23 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M23 System Tick Interrupt */
/****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/
BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
IRC_IRQn = 1, /*!< Internal RC Interrupt */
PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */
CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */
ISP_IRQn = 5, /*!< FMC ISP Interrupt */
RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */
WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */
EINT0_IRQn = 10, /*!< External Input 0 Interrupt */
EINT1_IRQn = 11, /*!< External Input 1 Interrupt */
EINT2_IRQn = 12, /*!< External Input 2 Interrupt */
EINT3_IRQn = 13, /*!< External Input 3 Interrupt */
EINT4_IRQn = 14, /*!< External Input 4 Interrupt */
EINT5_IRQn = 15, /*!< External Input 5 Interrupt */
GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */
SPI0_IRQn = 23, /*!< SPI0 Interrupt */
BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */
EPWM0_P0_IRQn = 25, /*!< EPWM0P0 Interrupt */
EPWM0_P1_IRQn = 26, /*!< EPWM0P1 Interrupt */
EPWM0_P2_IRQn = 27, /*!< EPWM0P2 Interrupt */
BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */
EPWM1_P0_IRQn = 29, /*!< EPWM1P0 Interrupt */
EPWM1_P1_IRQn = 30, /*!< EPWM1P1 Interrupt */
EPWM1_P2_IRQn = 31, /*!< EPWM1P2 Interrupt */
TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
UART0_IRQn = 36, /*!< UART 0 Interrupt */
UART1_IRQn = 37, /*!< UART 1 Interrupt */
I2C0_IRQn = 38, /*!< I2C 0 Interrupt */
I2C1_IRQn = 39, /*!< I2C 1 Interrupt */
PDMA0_IRQn = 40, /*!< Peripheral DMA 0 Interrupt */
DAC_IRQn = 41, /*!< DAC Interrupt */
EADC0_IRQn = 42, /*!< EADC Source 0 Interrupt */
EADC1_IRQn = 43, /*!< EADC Source 1 Interrupt */
ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */
EADC2_IRQn = 46, /*!< EADC Source 2 Interrupt */
EADC3_IRQn = 47, /*!< EADC Source 3 Interrupt */
UART2_IRQn = 48, /*!< UART2 Interrupt */
UART3_IRQn = 49, /*!< UART3 Interrupt */
SPI1_IRQn = 51, /*!< SPI1 Interrupt */
SPI2_IRQn = 52, /*!< SPI2 Interrupt */
USBD_IRQn = 53, /*!< USB device Interrupt */
USBH_IRQn = 54, /*!< USB host Interrupt */
USBOTG_IRQn = 55, /*!< USB OTG Interrupt */
CAN0_IRQn = 56, /*!< CAN0 Interrupt */
SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */
SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */
SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */
SPI3_IRQn = 62, /*!< SPI3 Interrupt */
SDH0_IRQn = 64, /*!< SDH0 Interrupt */
I2S0_IRQn = 68, /*!< I2S0 Interrupt */
CRPT_IRQn = 71, /*!< CRPT Interrupt */
GPG_IRQn = 72, /*!< GPIO Port G Interrupt */
EINT6_IRQn = 73, /*!< External Input 6 Interrupt */
UART4_IRQn = 74, /*!< UART4 Interrupt */
UART5_IRQn = 75, /*!< UART5 Interrupt */
USCI0_IRQn = 76, /*!< USCI0 Interrupt */
USCI1_IRQn = 77, /*!< USCI1 Interrupt */
BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */
BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */
I2C2_IRQn = 82, /*!< I2C2 Interrupt */
QEI0_IRQn = 84, /*!< QEI0 Interrupt */
QEI1_IRQn = 85, /*!< QEI1 Interrupt */
ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */
ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */
GPH_IRQn = 88, /*!< GPIO Port H Interrupt */
EINT7_IRQn = 89, /*!< External Input 7 Interrupt */
PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */
SCU_IRQn = 99, /*!< SCU Interrupt */
TRNG_IRQn = 101 /*!< TRNG interrupt */
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ------- Start of section using anonymous unions and disabling warnings ------- */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */
#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */
#define __SAU_PRESENT 1U /* SAU present */
#define __SAUREGION_PRESENT 1U /* SAU present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define USE_ASSERT 0U /* Define to use Assert function or not */
/*@}*/ /* end of group CMSIS */
#include "core_armv8mbl.h" /* Processor and core peripherals */
#include "system_M261.h" /* System Header */
/**
* Initialize the system clock
*
* @param none
* @return none
*
* @brief Setup the micro controller system
* Initialize the PLL and update the SystemFrequency variable
*/
extern void SystemInit(void);
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
#include "acmp_reg.h"
#include "bpwm_reg.h"
#include "can_reg.h"
#include "clk_reg.h"
#include "crc_reg.h"
#include "dac_reg.h"
#include "eadc_reg.h"
#include "ebi_reg.h"
#include "ecap_reg.h"
#include "fmc_reg.h"
#include "gpio_reg.h"
#include "hdiv_reg.h"
#include "i2c_reg.h"
#include "i2s_reg.h"
#include "pdma_reg.h"
#include "epwm_reg.h"
#include "qei_reg.h"
#include "rtc_reg.h"
#include "sc_reg.h"
#include "scu_reg.h"
#include "sdh_reg.h"
#include "qspi_reg.h"
#include "spi_reg.h"
#include "sys_reg.h"
#include "timer_reg.h"
#include "trng_reg.h"
#include "uart_reg.h"
#include "ui2c_reg.h"
#include "usbh_reg.h"
#include "usbd_reg.h"
#include "otg_reg.h"
#include "crpt_reg.h"
#include "uspi_reg.h"
#include "uuart_reg.h"
#include "wdt_reg.h"
#include "wwdt_reg.h"
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/** @addtogroup PERIPHERAL_BASE Peripheral Memory Base
Memory Mapped Structure for Series Peripheral
@{
*/
/* Peripheral and SRAM base address */
#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
/* Peripheral memory map */
#define AHBPERIPH_BASE PERIPH_BASE
#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000UL)
/*!< AHB peripherals */
#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL)
#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL)
#define INT_BASE (AHBPERIPH_BASE + 0x00300UL)
#define GPIO_BASE (AHBPERIPH_BASE + 0x04000UL)
#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL)
#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL)
#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL)
#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL)
#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL)
#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL)
#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL)
#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)
#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000UL)
#define PDMA1_BASE (AHBPERIPH_BASE + 0x18000UL)
#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL)
#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL)
#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)
#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)
#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
#define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL)
#define SCU_BASE (AHBPERIPH_BASE + 0x2F000UL)
/*!< APB peripherals */
#define WDT_BASE (APBPERIPH_BASE + 0x00000UL)
#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
#define RTC_BASE (APBPERIPH_BASE + 0x01000UL)
#define EADC_BASE (APBPERIPH_BASE + 0x03000UL)
#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)
#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL)
#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL)
#define I2S0_BASE (APBPERIPH_BASE + 0x08000UL)
#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL)
#define TMR01_BASE (APBPERIPH_BASE + 0x10000UL)
#define TMR23_BASE (APBPERIPH_BASE + 0x11000UL)
#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL)
#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)
#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL)
#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL)
#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL)
#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL)
#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL)
#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL)
#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL)
#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
#define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
#define UART1_BASE (APBPERIPH_BASE + 0x31000UL)
#define UART2_BASE (APBPERIPH_BASE + 0x32000UL)
#define UART3_BASE (APBPERIPH_BASE + 0x33000UL)
#define UART4_BASE (APBPERIPH_BASE + 0x34000UL)
#define UART5_BASE (APBPERIPH_BASE + 0x35000UL)
#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL)
#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL)
#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL)
#define SC0_BASE (APBPERIPH_BASE + 0x50000UL)
#define SC1_BASE (APBPERIPH_BASE + 0x51000UL)
#define SC2_BASE (APBPERIPH_BASE + 0x52000UL)
#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL)
#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL)
#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL)
#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)
#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)
#define TRNG_BASE (APBPERIPH_BASE + 0x79000UL)
#define USBD_BASE (APBPERIPH_BASE + 0x80000UL)
#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL)
/**@}*/ /* PERIPHERAL */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
/** @addtogroup PMODULE Peripheral Pointer
The Declaration of Peripheral Pointer
@{
*/
#define PA ((GPIO_T *) GPIOA_BASE) /*!< GPIO PORTA Pointer */
#define PB ((GPIO_T *) GPIOB_BASE) /*!< GPIO PORTB Pointer */
#define PC ((GPIO_T *) GPIOC_BASE) /*!< GPIO PORTC Pointer */
#define PD ((GPIO_T *) GPIOD_BASE) /*!< GPIO PORTD Pointer */
#define PE ((GPIO_T *) GPIOE_BASE) /*!< GPIO PORTE Pointer */
#define PF ((GPIO_T *) GPIOF_BASE) /*!< GPIO PORTF Pointer */
#define PG ((GPIO_T *) GPIOG_BASE) /*!< GPIO PORTG Pointer */
#define PH ((GPIO_T *) GPIOH_BASE) /*!< GPIO PORTH Pointer */
#define UART0 ((UART_T *) UART0_BASE) /*!< UART0 Pointer */
#define UART1 ((UART_T *) UART1_BASE) /*!< UART1 Pointer */
#define UART2 ((UART_T *) UART2_BASE) /*!< UART2 Pointer */
#define UART3 ((UART_T *) UART3_BASE) /*!< UART3 Pointer */
#define UART4 ((UART_T *) UART4_BASE) /*!< UART4 Pointer */
#define UART5 ((UART_T *) UART5_BASE) /*!< UART5 Pointer */
#define TIMER0 ((TIMER_T *) TMR01_BASE) /*!< TIMER0 Pointer */
#define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x100UL)) /*!< TIMER1 Pointer */
#define TIMER2 ((TIMER_T *) TMR23_BASE) /*!< TIMER2 Pointer */
#define TIMER3 ((TIMER_T *) (TMR23_BASE + 0x100UL)) /*!< TIMER3 Pointer */
#define WDT ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Pointer */
#define WWDT ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Pointer */
#define QSPI0 ((QSPI_T *) QSPI0_BASE) /*!< QSPI0 Pointer */
#define SPI0 ((SPI_T *) SPI0_BASE) /*!< SPI0 Pointer */
#define SPI1 ((SPI_T *) SPI1_BASE) /*!< SPI1 Pointer */
#define SPI2 ((SPI_T *) SPI2_BASE) /*!< SPI2 Pointer */
#define SPI3 ((SPI_T *) SPI3_BASE) /*!< SPI3 Pointer */
#define I2S0 ((I2S_T *) I2S0_BASE) /*!< I2S0 Pointer */
#define I2C0 ((I2C_T *) I2C0_BASE) /*!< I2C0 Pointer */
#define I2C1 ((I2C_T *) I2C1_BASE) /*!< I2C1 Pointer */
#define I2C2 ((I2C_T *) I2C2_BASE) /*!< I2C1 Pointer */
#define QEI0 ((QEI_T *) QEI0_BASE) /*!< QEI0 Pointer */
#define QEI1 ((QEI_T *) QEI1_BASE) /*!< QEI1 Pointer */
#define RTC ((RTC_T *) RTC_BASE) /*!< RTC Pointer */
#define ACMP01 ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Pointer */
#define CLK ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */
#define DAC0 ((DAC_T *) DAC0_BASE) /*!< DAC0 Pointer */
#define DAC1 ((DAC_T *) DAC1_BASE) /*!< DAC1 Pointer */
#define EADC ((EADC_T *) EADC_BASE) /*!< EADC Pointer */
#define SYS ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */
#define SYSINT ((SYS_INT_T *) INT_BASE) /*!< Interrupt Source Controller Pointer */
#define FMC ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */
#define SDH0 ((SDH_T *) SDH0_BASE)
#define CRPT ((CRPT_T *) CRPT_BASE) /*!< Crypto Accelerator Pointer */
#define TRNG ((TRNG_T *)TRNG_BASE) /*!< True Random Number Pointer */
#define BPWM0 ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Pointer */
#define BPWM1 ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Pointer */
#define EPWM0 ((EPWM_T *) EPWM0_BASE) /*!< EPWM0 Pointer */
#define EPWM1 ((EPWM_T *) EPWM1_BASE) /*!< EPWM1 Pointer */
#define SC0 ((SC_T *) SC0_BASE) /*!< SC0 Pointer */
#define SC1 ((SC_T *) SC1_BASE) /*!< SC1 Pointer */
#define SC2 ((SC_T *) SC2_BASE) /*!< SC2 Pointer */
#define EBI ((EBI_T *) EBI_BASE) /*!< EBI Pointer */
#define CRC ((CRC_T *) CRC_BASE) /*!< CRC Pointer */
#define USBD ((USBD_T *) USBD_BASE) /*!< USB Device Pointer */
#define USBH ((USBH_T *) USBH_BASE) /*!< USBH Pointer */
#define OTG ((OTG_T *) OTG_BASE) /*!< OTG Pointer */
#define PDMA0 ((PDMA_T *) PDMA0_BASE) /*!< PDMA0 Pointer */
#define PDMA1 ((PDMA_T *) PDMA1_BASE) /*!< PDMA1 Pointer */
#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Pointer */
#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Pointer */
#define UI2C2 ((UI2C_T *) USCI2_BASE) /*!< UI2C2 Pointer */
#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Pointer */
#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Pointer */
#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Pointer */
#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Pointer */
#define SCU ((SCU_T *) SCU_BASE) /*!< SCU Pointer */
#define ECAP0 ((ECAP_T *) ECAP0_BASE) /*!< ECAP0 Pointer */
#define ECAP1 ((ECAP_T *) ECAP1_BASE) /*!< ECAP1 Pointer */
#define CAN0 ((CAN_T *)CAN0_BASE) /*!< CAN0 Pointer */
/**@}*/ /* end of group PMODULE */
/* -------------------- End of section using anonymous unions ------------------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
#ifdef __cplusplus
}
#endif
/*=============================================================================*/
typedef volatile unsigned char vu8;
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
#define M8(adr) (*((vu8 *) (adr)))
#define M16(adr) (*((vu16 *) (adr)))
#define M32(adr) (*((vu32 *) (adr)))
#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
#define inpw(port) ((*((volatile unsigned int *)(port))))
#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
#define inpb(port) ((*((volatile unsigned char *)(port))))
#define outps(port,value) (*((volatile unsigned short *)(port))=(value))
#define inps(port) ((*((volatile unsigned short *)(port))))
#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
#define inp32(port) ((*((volatile unsigned int *)(port))))
#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
#define inp8(port) ((*((volatile unsigned char *)(port))))
#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
#define inp16(port) ((*((volatile unsigned short *)(port))))
#define E_SUCCESS 0
#define TRUE (1L)
#define FALSE (0L)
#define ENABLE 1
#define DISABLE 0
/* Bit Mask Definitions */
#define BIT0 0x00000001UL
#define BIT1 0x00000002UL
#define BIT2 0x00000004UL
#define BIT3 0x00000008UL
#define BIT4 0x00000010UL
#define BIT5 0x00000020UL
#define BIT6 0x00000040UL
#define BIT7 0x00000080UL
#define BIT8 0x00000100UL
#define BIT9 0x00000200UL
#define BIT10 0x00000400UL
#define BIT11 0x00000800UL
#define BIT12 0x00001000UL
#define BIT13 0x00002000UL
#define BIT14 0x00004000UL
#define BIT15 0x00008000UL
#define BIT16 0x00010000UL
#define BIT17 0x00020000UL
#define BIT18 0x00040000UL
#define BIT19 0x00080000UL
#define BIT20 0x00100000UL
#define BIT21 0x00200000UL
#define BIT22 0x00400000UL
#define BIT23 0x00800000UL
#define BIT24 0x01000000UL
#define BIT25 0x02000000UL
#define BIT26 0x04000000UL
#define BIT27 0x08000000UL
#define BIT28 0x10000000UL
#define BIT29 0x20000000UL
#define BIT30 0x40000000UL
#define BIT31 0x80000000UL
/* Byte Mask Definitions */
#define BYTE0_Msk (0x000000FFUL)
#define BYTE1_Msk (0x0000FF00UL)
#define BYTE2_Msk (0x00FF0000UL)
#define BYTE3_Msk (0xFF000000UL)
#define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
#define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8UL) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
#define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16UL) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
#define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24UL) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
/******************************************************************************/
/* Peripheral header files */
/******************************************************************************/
#include "sys.h"
#include "clk.h"
#include "dac.h"
#include "eadc.h"
#include "ebi.h"
#include "ecap.h"
#include "fmc.h"
#include "gpio.h"
#include "i2c.h"
#include "i2s.h"
#include "bpwm.h"
#include "epwm.h"
#include "qspi.h"
#include "spi.h"
#include "timer.h"
#include "timer_pwm.h"
#include "wdt.h"
#include "wwdt.h"
#include "rtc.h"
#include "uart.h"
#include "acmp.h"
#include "crc.h"
#include "usbd.h"
#include "otg.h"
#include "pdma.h"
#include "ebi.h"
#include "crypto.h"
#include "sc.h"
#include "scuart.h"
#include "usci_spi.h"
#include "usci_uart.h"
#include "usci_i2c.h"
#include "sdh.h"
#include "qei.h"
#include "can.h"
#include "scu.h"
#include "mkromlib.h"
#endif /* __M261_H__ */
/* Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. */

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targets/TARGET_NUVOTON/TARGET_M261/device/StdDriver/m261_retarget.c
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/**************************************************************************//**
* @file retarget.c
* @version V3.00
* @brief Debug Port and Semihost Setting Source File
*
* @note
* Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include "NuMicro.h"
#if defined (__ICCARM__)
# pragma diag_suppress=Pm150
#endif
#if defined ( __CC_ARM )
#if (__ARMCC_VERSION < 400000)
#else
/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */
#pragma import _printf_widthprec
#endif
#endif
/*---------------------------------------------------------------------------------------------------------*/
/* Global variables */
/*---------------------------------------------------------------------------------------------------------*/
#if !(defined(__ICCARM__) && (__VER__ >= 6010000))
# if (__ARMCC_VERSION < 6040000)
struct __FILE
{
int handle; /* Add whatever you need here */
};
# endif
#elif(__VER__ >= 8000000)
struct __FILE
{
int handle; /* Add whatever you need here */
};
#endif
FILE __stdout;
FILE __stdin;
#if (defined(__ARMCC_VERSION) || defined(__ICCARM__))
extern int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0);
#if defined( __ICCARM__ )
__WEAK
#else
__attribute__((weak))
#endif
uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp);
#endif
int kbhit(void);
int IsDebugFifoEmpty(void);
void _ttywrch(int ch);
int fputc(int ch, FILE *stream);
#if (defined(__ARMCC_VERSION) || defined(__ICCARM__))
int fgetc(FILE *stream);
int ferror(FILE *stream);
#endif
char GetChar(void);
void SendChar_ToUART(int ch);
void SendChar(int ch);
#if defined(DEBUG_ENABLE_SEMIHOST)
#if (defined(__ARMCC_VERSION) || defined(__ICCARM__))
/* The static buffer is used to speed up the semihost */
static char g_buf[16];
static char g_buf_len = 0;
static volatile int32_t g_ICE_Conneced = 1;
/**
* @brief This function is called by Hardfault handler.
* @param None
* @returns None
* @details This function is called by Hardfault handler and check if it is caused by __BKPT or not.
*
*/
uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp)
{
uint32_t *sp;
uint32_t inst;
/* Check the used stack */
if(lr & 0x40)
{
/* Secure stack used */
if(lr & 4)
sp = (uint32_t *)psp;
else
sp = (uint32_t *)msp;
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
else
{
/* Non-secure stack used */
if(lr & 4)
sp = (uint32_t *)__TZ_get_PSP_NS();
else
sp = (uint32_t *)__TZ_get_MSP_NS();
}
#endif
/* Get the instruction caused the hardfault */
inst = M16(sp[6]);
if(inst == 0xBEAB)
{
/*
If the instruction is 0xBEAB, it means it is caused by BKPT without ICE connected.
We still return for output/input message to UART.
*/
g_ICE_Conneced = 0; // Set a flag for ICE offline
sp[6] += 2; // return to next instruction
return lr; // Keep lr in R0
}
/* It is casued by hardfault (Not semihost). Just process the hard fault here. */
/* TODO: Implement your hardfault handle code here */
/*
printf(" HardFault!\n\n");
printf("r0 = 0x%x\n", sp[0]);
printf("r1 = 0x%x\n", sp[1]);
printf("r2 = 0x%x\n", sp[2]);
printf("r3 = 0x%x\n", sp[3]);
printf("r12 = 0x%x\n", sp[4]);
printf("lr = 0x%x\n", sp[5]);
printf("pc = 0x%x\n", sp[6]);
printf("psr = 0x%x\n", sp[7]);
*/
while(1){}
}
/**
*
* @brief The function to process semihosted command
* @param[in] n32In_R0 : semihost register 0
* @param[in] n32In_R1 : semihost register 1
* @param[out] pn32Out_R0: semihost register 0
* @retval 0: No ICE debug
* @retval 1: ICE debug
*
*/
int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
{
if(g_ICE_Conneced)
{
if(pn32Out_R0)
*pn32Out_R0 = n32In_R0;
return 1;
}
return 0;
}
#endif
#else // defined(DEBUG_ENABLE_SEMIHOST)
int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0);
#if defined( __ICCARM__ )
__WEAK
#else
__attribute__((weak))
#endif
uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp)
{
uint32_t *sp;
/* It is casued by hardfault. Just process the hard fault */
/* TODO: Implement your hardfault handle code here */
/* Check the used stack */
if(lr & 0x40UL)
{
/* Secure stack used */
if(lr & 4UL)
{
sp = (uint32_t *)psp;
}
else
{
sp = (uint32_t *)msp;
}
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)
else
{
/* Non-secure stack used */
if(lr & 4)
sp = (uint32_t *)__TZ_get_PSP_NS();
else
sp = (uint32_t *)__TZ_get_MSP_NS();
}
#endif
/*
printf(" HardFault!\n\n");
printf("r0 = 0x%x\n", sp[0]);
printf("r1 = 0x%x\n", sp[1]);
printf("r2 = 0x%x\n", sp[2]);
printf("r3 = 0x%x\n", sp[3]);
printf("r12 = 0x%x\n", sp[4]);
printf("lr = 0x%x\n", sp[5]);
printf("pc = 0x%x\n", sp[6]);
printf("psr = 0x%x\n", sp[7]);
*/
/* Or *sp to remove compiler warning */
while(1U|*sp){}
return lr;
}
int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
{
return 0;
}
#endif /* defined(DEBUG_ENABLE_SEMIHOST) */
/**
* @brief Routine to send a char
*
* @param[in] ch A character data writes to debug port
*
* @returns Send value from UART debug port
*
* @details Send a target char to UART debug port .
*/
#ifndef NONBLOCK_PRINTF
void SendChar_ToUART(int ch)
{
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk){}
DEBUG_PORT->DAT = (uint32_t)ch;
if((char)ch == '\n')
{
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk){}
DEBUG_PORT->DAT = '\r';
}
}
#else
/* Non-block implement of send char */
# define BUF_SIZE 512
void SendChar_ToUART(int ch)
{
static uint8_t u8Buf[BUF_SIZE] = {0};
static int32_t i32Head = 0;
static int32_t i32Tail = 0;
int32_t i32Tmp;
/* Only flush the data in buffer to UART when ch == 0 */
if(ch)
{
// Push char
i32Tmp = i32Head+1;
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
if(i32Tmp != i32Tail)
{
u8Buf[i32Head] = ch;
i32Head = i32Tmp;
}
if(ch == '\n')
{
i32Tmp = i32Head+1;
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
if(i32Tmp != i32Tail)
{
u8Buf[i32Head] = '\r';
i32Head = i32Tmp;
}
}
}
else
{
if(i32Tail == i32Head)
return;
}
// pop char
do
{
i32Tmp = i32Tail + 1;
if(i32Tmp > BUF_SIZE) i32Tmp = 0;
if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) == 0)
{
DEBUG_PORT->DAT = u8Buf[i32Tail];
i32Tail = i32Tmp;
}
else
break; // FIFO full
}while(i32Tail != i32Head);
}
#endif
/**
* @brief Routine to send a char
*
* @param[in] ch A character data writes to debug port
*
* @returns Send value from UART debug port or semihost
*
* @details Send a target char to UART debug port or semihost.
*/
void SendChar(int ch)
{
#if defined(DEBUG_ENABLE_SEMIHOST)
g_buf[g_buf_len++] = ch;
g_buf[g_buf_len] = '\0';
if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0')
{
/* Send the char */
if(g_ICE_Conneced)
{
if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0)
{
g_buf_len = 0;
return;
}
}
else
{
# if (DEBUG_ENABLE_SEMIHOST == 2) // Re-direct to UART Debug Port only when DEBUG_ENABLE_SEMIHOST=2
int i;
for(i = 0; i < g_buf_len; i++)
SendChar_ToUART(g_buf[i]);
g_buf_len = 0;
# endif
}
}
#else
SendChar_ToUART(ch);
#endif
}
/**
* @brief Routine to get a char
*
* @param None
*
* @returns Get value from UART debug port or semihost
*
* @details Wait UART debug port or semihost to input a char.
*/
char GetChar(void)
{
#ifdef DEBUG_ENABLE_SEMIHOST
# if defined (__ICCARM__)
int nRet;
while(SH_DoCommand(0x7, 0, &nRet) != 0)
{
if(nRet != 0)
return (char)nRet;
}
# else
int nRet;
while(SH_DoCommand(0x101, 0, &nRet) != 0)
{
if(nRet != 0)
{
SH_DoCommand(0x07, 0, &nRet);
return (char)nRet;
}
}
# if (DEBUG_ENABLE_SEMIHOST == 2) // Re-direct to UART Debug Port only when DEBUG_ENABLE_SEMIHOST=2
/* Use debug port when ICE is not connected at semihost mode */
while(!g_ICE_Conneced)
{
if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0)
{
return (DEBUG_PORT->DAT);
}
}
# endif
# endif
return (0);
#else
while(1)
{
if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0U)
{
return ((char)DEBUG_PORT->DAT);
}
}
#endif
}
/**
* @brief Check any char input from UART
*
* @param None
*
* @retval 1: No any char input
* @retval 0: Have some char input
*
* @details Check UART RSR RX EMPTY or not to determine if any char input from UART
*/
int kbhit(void)
{
return !((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0U);
}
/**
* @brief Check if debug message finished
*
* @param None
*
* @retval 1: Message is finished
* @retval 0: Message is transmitting.
*
* @details Check if message finished (FIFO empty of debug port)
*/
int IsDebugFifoEmpty(void)
{
return ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) != 0U);
}
/**
* @brief C library retargetting
*
* @param[in] ch Write a character data
*
* @returns None
*
* @details Check if message finished (FIFO empty of debug port)
*/
void _ttywrch(int ch)
{
SendChar(ch);
return;
}
/**
* @brief Write character to stream
*
* @param[in] ch Character to be written. The character is passed as its int promotion.
* @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written.
*
* @returns If there are no errors, the same character that has been written is returned.
* If an error occurs, EOF is returned and the error indicator is set (see ferror).
*
* @details Writes a character to the stream and advances the position indicator.\n
* The character is written at the current position of the stream as indicated \n
* by the internal position indicator, which is then advanced one character.
*
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/.
*
*
*/
int fputc(int ch, FILE *stream)
{
SendChar(ch);
return ch;
}
#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))
#if !defined(OS_USE_SEMIHOSTING)
int _write (int fd, char *ptr, int len)
{
int i = len;
while(i--) {
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
DEBUG_PORT->DAT = *ptr++;
if(*ptr == '\n') {
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
DEBUG_PORT->DAT = '\r';
}
}
return len;
}
int _read (int fd, char *ptr, int len)
{
while((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) != 0);
*ptr = DEBUG_PORT->DAT;
return 1;
}
#endif
#else
/**
* @brief Get character from UART debug port or semihosting input
*
* @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed.
*
* @returns The character read from UART debug port or semihosting
*
* @details For get message from debug port or semihosting.
*
*/
int fgetc(FILE *stream)
{
return ((int)GetChar());
}
/**
* @brief Check error indicator
*
* @param[in] stream Pointer to a FILE object that identifies the stream.
*
* @returns If the error indicator associated with the stream was set, the function returns a nonzero value.
* Otherwise, it returns a zero value.
*
* @details Checks if the error indicator associated with stream is set, returning a value different
* from zero if it is. This indicator is generally set by a previous operation on the stream that failed.
*
* @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/.
*
*/
int ferror(FILE *stream)
{
return EOF;
}
#endif
#ifdef DEBUG_ENABLE_SEMIHOST
# ifdef __ICCARM__
void __exit(int return_code)
{
/* Check if link with ICE */
if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
{
/* Make sure all message is print out */
while(IsDebugFifoEmpty() == 0);
}
label:
goto label; /* endless loop */
}
# else
void _sys_exit(int return_code)
{
/* Check if link with ICE */
if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
{
/* Make sure all message is print out */
while(IsDebugFifoEmpty() == 0);
}
label:
goto label; /* endless loop */
}
# endif
#endif
/*** (C) COPYRIGHT 2019 Nuvoton Technology Corp. ***/