From b943c4474a22449e9ccfe8809e9129603946a469 Mon Sep 17 00:00:00 2001
From: jeromecoutant <jerome.coutant@st.com>
Date: Fri, 19 Mar 2021 11:33:33 +0100
Subject: [PATCH] FPGA SPI : decrease test frequency for ASYNC test cases

---
 hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp b/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp
index f933b250bb..6fe963a987 100644
--- a/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp
+++ b/hal/tests/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp
@@ -415,8 +415,8 @@ Case cases[] = {
     Case("SPI - hardware ss handling", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, true, false> >),
     Case("SPI - hardware ss handling(block)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ, BUFFERS_COMMON, true, false> >),
 #if DEVICE_SPI_ASYNCH
-    Case("SPI - async mode (sw ss)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_1_MHZ, BUFFERS_COMMON, false, false> >),
-    Case("SPI - async mode (hw ss)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_1_MHZ, BUFFERS_COMMON, true, false> >)
+    Case("SPI - async mode (sw ss)", one_peripheral<SPINoCSPort, DefaultFormFactor, fpga_spi_test_common_no_ss<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_500_KHZ, BUFFERS_COMMON, false, false> >),
+    Case("SPI - async mode (hw ss)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_500_KHZ, BUFFERS_COMMON, true, false> >)
 #endif
 };