From 7e4c435c45b7f5ef8c4bb0d62af7540791c384cf Mon Sep 17 00:00:00 2001 From: Devaraj Ranganna Date: Thu, 4 Jul 2019 16:44:19 +0300 Subject: [PATCH 01/37] Include mbedtls/config.h before evaluating MBEDTLS_PSA_CRYPTO_C Signed-off-by: Devaraj Ranganna --- TESTS/mbed-crypto/sanity/main.cpp | 6 ++++++ TESTS/psa/attestation/main.cpp | 6 ++++++ TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp | 6 ++++++ TESTS/psa/crypto_init/main.cpp | 6 ++++++ 4 files changed, 24 insertions(+) diff --git a/TESTS/mbed-crypto/sanity/main.cpp b/TESTS/mbed-crypto/sanity/main.cpp index d71563dbcb..b7d1c49608 100644 --- a/TESTS/mbed-crypto/sanity/main.cpp +++ b/TESTS/mbed-crypto/sanity/main.cpp @@ -15,6 +15,12 @@ * limitations under the License. */ +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) #error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. #endif diff --git a/TESTS/psa/attestation/main.cpp b/TESTS/psa/attestation/main.cpp index 391c0a289f..34bc7cd712 100755 --- a/TESTS/psa/attestation/main.cpp +++ b/TESTS/psa/attestation/main.cpp @@ -16,6 +16,12 @@ * limitations under the License. */ +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) #error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. #endif // TARGET_PSA diff --git a/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp b/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp index 41b4de5ce0..86c4a49a66 100644 --- a/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp +++ b/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp @@ -15,6 +15,12 @@ * limitations under the License. */ +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C)) || (!defined(COMPONENT_PSA_SRV_IPC))) #error [NOT_SUPPORTED] These tests can run only on SPM-enabled targets and where Mbed Crypto is ON - skipping. #endif diff --git a/TESTS/psa/crypto_init/main.cpp b/TESTS/psa/crypto_init/main.cpp index cad0258d2a..53ad5fe139 100644 --- a/TESTS/psa/crypto_init/main.cpp +++ b/TESTS/psa/crypto_init/main.cpp @@ -16,6 +16,12 @@ * limitations under the License. */ +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) #error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. #endif // TARGET_PSA From efb94025d8acabdf1698ace23567dd055e1fdaff Mon Sep 17 00:00:00 2001 From: Devaraj Ranganna Date: Mon, 8 Jul 2019 16:28:58 +0100 Subject: [PATCH 02/37] Include psa/crypto.h instead of mbedtls/config.h. Signed-off-by: Devaraj Ranganna --- TESTS/mbed-crypto/sanity/main.cpp | 7 +------ TESTS/psa/attestation/main.cpp | 6 +----- TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp | 7 +------ TESTS/psa/crypto_init/main.cpp | 7 +------ 4 files changed, 4 insertions(+), 23 deletions(-) diff --git a/TESTS/mbed-crypto/sanity/main.cpp b/TESTS/mbed-crypto/sanity/main.cpp index b7d1c49608..73d5eb0b6f 100644 --- a/TESTS/mbed-crypto/sanity/main.cpp +++ b/TESTS/mbed-crypto/sanity/main.cpp @@ -15,11 +15,7 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "psa/crypto.h" #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) #error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. @@ -30,7 +26,6 @@ #include "greentea-client/test_env.h" #include "unity.h" #include "utest.h" -#include "psa/crypto.h" #include "entropy.h" #include "entropy_poll.h" diff --git a/TESTS/psa/attestation/main.cpp b/TESTS/psa/attestation/main.cpp index 34bc7cd712..90113daa1f 100755 --- a/TESTS/psa/attestation/main.cpp +++ b/TESTS/psa/attestation/main.cpp @@ -16,11 +16,7 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "psa/crypto.h" #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) #error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. diff --git a/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp b/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp index 86c4a49a66..ca848e85af 100644 --- a/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp +++ b/TESTS/psa/crypto_access_control/COMPONENT_NSPE/main.cpp @@ -15,11 +15,7 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "psa/crypto.h" #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C)) || (!defined(COMPONENT_PSA_SRV_IPC))) #error [NOT_SUPPORTED] These tests can run only on SPM-enabled targets and where Mbed Crypto is ON - skipping. @@ -30,7 +26,6 @@ #include "greentea-client/test_env.h" #include "unity.h" #include "utest.h" -#include "psa/crypto.h" #include "entropy.h" #include "entropy_poll.h" #include "test_partition_proxy.h" diff --git a/TESTS/psa/crypto_init/main.cpp b/TESTS/psa/crypto_init/main.cpp index 53ad5fe139..b057cd501e 100644 --- a/TESTS/psa/crypto_init/main.cpp +++ b/TESTS/psa/crypto_init/main.cpp @@ -16,11 +16,7 @@ * limitations under the License. */ -#if !defined(MBEDTLS_CONFIG_FILE) -#include "mbedtls/config.h" -#else -#include MBEDTLS_CONFIG_FILE -#endif +#include "psa/crypto.h" #if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) #error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. @@ -29,7 +25,6 @@ #include "greentea-client/test_env.h" #include "unity/unity.h" #include "utest/utest.h" -#include "crypto.h" #include "entropy.h" #include "entropy_poll.h" From 333ed3e85a56e92b3da7df85e1b036e56e5849f8 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 10 Jul 2019 00:27:06 +0200 Subject: [PATCH 03/37] FPGA SPI: ASYNC issue --- TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp index 8081c84193..9ebc2e100d 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/spi/main.cpp @@ -55,7 +55,7 @@ void spi_async_handler() { int event = spi_irq_handler_asynch(&spi); - if (event == SPI_EVENT_COMPLETE) { + if (event & SPI_EVENT_COMPLETE) { async_trasfer_done = true; } } @@ -136,7 +136,7 @@ void spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPI async_trasfer_done = false; - spi_master_transfer(&spi, tx_buf, TRANSFER_COUNT, rx_buf, TRANSFER_COUNT, 8, (uint32_t)spi_async_handler, 0, DMA_USAGE_NEVER); + spi_master_transfer(&spi, tx_buf, TRANSFER_COUNT, rx_buf, TRANSFER_COUNT, 8, (uint32_t)spi_async_handler, SPI_EVENT_COMPLETE, DMA_USAGE_NEVER); while (!async_trasfer_done); for (int i = 0; i < TRANSFER_COUNT; i++) { From 1bbc2d770aba38f12e5dd9df5ce8b82ea2d7dd5f Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 9 Jul 2019 15:32:35 -0500 Subject: [PATCH 04/37] LPC MCUXpresso: Remove extra I2C transaction on byte write An extra start signal was observed on the bus which was discovered by the FPGA test shield. This is because the hardware sends out a transaction as soon as a write to the START bit. Hence the write to the START bit is delayed by using a flag. Signed-off-by: Mahesh Mahadevan --- .../TARGET_LPC/i2c_api.c | 37 +++++++++---------- .../TARGET_LPC/objects.h | 1 + 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/i2c_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/i2c_api.c index acfa4488e1..38b4780e98 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/i2c_api.c @@ -32,6 +32,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); obj->instance = pinmap_merge(i2c_sda, i2c_scl); obj->next_repeated_start = 0; + obj->issue_start = 0; MBED_ASSERT((int)obj->instance != NC); i2c_master_config_t master_config; @@ -92,23 +93,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) int i2c_start(i2c_t *obj) { - I2C_Type *base = i2c_addrs[obj->instance]; - uint32_t status; - - do { - status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); - - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); - - /* Start the transfer */ - base->MSTDAT = 0; - base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - - do { - status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); + obj->issue_start = 1; return 0; } @@ -131,6 +116,8 @@ int i2c_stop(i2c_t *obj) status = I2C_GetStatusFlags(base); } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); + obj->issue_start = 0; + return 0; } @@ -236,12 +223,24 @@ int i2c_byte_write(i2c_t *obj, int data) // write the data base->MSTDAT = data; - base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - do { status = I2C_GetStatusFlags(base); } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); + /* Clear controller state. */ + I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + + if (obj->issue_start) { + base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; + /* Clear the flag */ + obj->issue_start = 0; + } else { + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + } + + do { + status = I2C_GetStatusFlags(base); + } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); /* Check if arbitration lost */ if (status & I2C_STAT_MSTARBLOSS_MASK) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h index 23a50cd072..2eb11fa8e2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h @@ -52,6 +52,7 @@ struct analogin_s { struct i2c_s { uint32_t instance; uint8_t next_repeated_start; + uint8_t issue_start; }; struct spi_s { From c19397da8d150f7205dd3b2e55affea403d73da7 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 9 Jul 2019 17:55:41 +0800 Subject: [PATCH 05/37] Fix mbed_drivers-watchdog failing with OOM This is to fix OOM error on targets with just 16KiB RAM. --- TESTS/mbed_drivers/watchdog/main.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTS/mbed_drivers/watchdog/main.cpp b/TESTS/mbed_drivers/watchdog/main.cpp index e476191906..e89fe282fb 100644 --- a/TESTS/mbed_drivers/watchdog/main.cpp +++ b/TESTS/mbed_drivers/watchdog/main.cpp @@ -68,7 +68,7 @@ using utest::v1::Harness; using namespace mbed; -Thread wdg_kicking_thread; +Thread wdg_kicking_thread(osPriorityNormal, 768); Semaphore kick_wdg_during_test_teardown(0, 1); void wdg_kicking_thread_fun() From 67edba468c51dff44040dac75f7c8f22d6ef5847 Mon Sep 17 00:00:00 2001 From: Chun-Chieh Li Date: Tue, 9 Jul 2019 17:59:03 +0800 Subject: [PATCH 06/37] Fix mbed_hal-watchdog failing with OOM This is to fix OOM error on targets with just 16KiB RAM. --- TESTS/mbed_hal/watchdog/main.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/TESTS/mbed_hal/watchdog/main.cpp b/TESTS/mbed_hal/watchdog/main.cpp index 58cf5be088..2b8d58b4af 100644 --- a/TESTS/mbed_hal/watchdog/main.cpp +++ b/TESTS/mbed_hal/watchdog/main.cpp @@ -69,7 +69,7 @@ using utest::v1::Harness; const watchdog_config_t WDG_CONFIG_DEFAULT = { .timeout_ms = WDG_TIMEOUT_MS }; -Thread wdg_kicking_thread; +Thread wdg_kicking_thread(osPriorityNormal, 768); Semaphore kick_wdg_during_test_teardown(0, 1); void wdg_kicking_thread_fun() From a5cb9d47acbb91604f25030526afa1c9c7c673a2 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Wed, 10 Jul 2019 11:27:29 +0100 Subject: [PATCH 07/37] Fix wrongly declared ADC pinout for EFM32GG11 STK3701A --- .../TARGET_EFM32GG11/PeripheralPins.c | 99 +++++++++++++------ 1 file changed, 68 insertions(+), 31 deletions(-) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/PeripheralPins.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/PeripheralPins.c index 96f40fdaab..dd60ff4c80 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/PeripheralPins.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32GG11/PeripheralPins.c @@ -29,41 +29,78 @@ #if DEVICE_ANALOGIN MBED_WEAK const PinMap PinMap_ADC[] = { #if ADC0_BASE - {PA0, ADC_0, adcPosSelAPORT3XCH8}, - {PA1, ADC_0, adcPosSelAPORT4XCH9}, - {PA2, ADC_0, adcPosSelAPORT3XCH10}, - {PA3, ADC_0, adcPosSelAPORT4XCH11}, - {PA4, ADC_0, adcPosSelAPORT3XCH12}, - {PA5, ADC_0, adcPosSelAPORT4XCH13}, + {PA0, ADC_0, adcPosSelAPORT1XCH0}, + {PA1, ADC_0, adcPosSelAPORT2XCH1}, + {PA2, ADC_0, adcPosSelAPORT1XCH2}, + {PA3, ADC_0, adcPosSelAPORT2XCH3}, + {PA4, ADC_0, adcPosSelAPORT1XCH4}, + {PA5, ADC_0, adcPosSelAPORT2XCH5}, + {PA6, ADC_0, adcPosSelAPORT1XCH6}, + {PA7, ADC_0, adcPosSelAPORT2XCH7}, + {PA8, ADC_0, adcPosSelAPORT1XCH8}, + {PA9, ADC_0, adcPosSelAPORT2XCH9}, + {PA10, ADC_0, adcPosSelAPORT1XCH10}, + {PA11, ADC_0, adcPosSelAPORT2XCH11}, + {PA12, ADC_0, adcPosSelAPORT1XCH12}, + {PA13, ADC_0, adcPosSelAPORT2XCH13}, + {PA14, ADC_0, adcPosSelAPORT1XCH14}, + {PA15, ADC_0, adcPosSelAPORT2XCH15}, - {PB11, ADC_0, adcPosSelAPORT4XCH27}, - {PB12, ADC_0, adcPosSelAPORT3XCH28}, - {PB14, ADC_0, adcPosSelAPORT3XCH30}, - {PB15, ADC_0, adcPosSelAPORT4XCH31}, + {PB0, ADC_0, adcPosSelAPORT1XCH16}, + {PB1, ADC_0, adcPosSelAPORT2XCH17}, + {PB2, ADC_0, adcPosSelAPORT1XCH18}, + {PB3, ADC_0, adcPosSelAPORT2XCH19}, + {PB4, ADC_0, adcPosSelAPORT1XCH20}, + {PB5, ADC_0, adcPosSelAPORT2XCH21}, + {PB6, ADC_0, adcPosSelAPORT1XCH22}, - {PC6, ADC_0, adcPosSelAPORT1XCH6}, - {PC7, ADC_0, adcPosSelAPORT2XCH7}, - {PC8, ADC_0, adcPosSelAPORT1XCH8}, - {PC9, ADC_0, adcPosSelAPORT2XCH9}, - {PC10, ADC_0, adcPosSelAPORT1XCH10}, - {PC11, ADC_0, adcPosSelAPORT2XCH11}, + {PB9, ADC_0, adcPosSelAPORT2XCH25}, + {PB10, ADC_0, adcPosSelAPORT1XCH26}, + {PB11, ADC_0, adcPosSelAPORT2XCH27}, + {PB12, ADC_0, adcPosSelAPORT1XCH28}, + {PB14, ADC_0, adcPosSelAPORT1XCH30}, + {PB15, ADC_0, adcPosSelAPORT2XCH31}, - {PD9, ADC_0, adcPosSelAPORT4XCH1}, - {PD10, ADC_0, adcPosSelAPORT3XCH2}, - {PD11, ADC_0, adcPosSelAPORT3YCH3}, - {PD12, ADC_0, adcPosSelAPORT3XCH4}, - {PD13, ADC_0, adcPosSelAPORT3YCH5}, - {PD14, ADC_0, adcPosSelAPORT3XCH6}, - {PD15, ADC_0, adcPosSelAPORT4XCH7}, + {PD0, ADC_0, adcPosSelAPORT0XCH0}, + {PD1, ADC_0, adcPosSelAPORT0XCH1}, + {PD2, ADC_0, adcPosSelAPORT0XCH2}, + {PD3, ADC_0, adcPosSelAPORT0XCH3}, + {PD4, ADC_0, adcPosSelAPORT0XCH4}, + {PD5, ADC_0, adcPosSelAPORT0XCH5}, + {PD6, ADC_0, adcPosSelAPORT0XCH6}, + {PD7, ADC_0, adcPosSelAPORT0XCH7}, - {PF0, ADC_0, adcPosSelAPORT1XCH16}, - {PF1, ADC_0, adcPosSelAPORT2XCH17}, - {PF2, ADC_0, adcPosSelAPORT1XCH18}, - {PF3, ADC_0, adcPosSelAPORT2XCH19}, - {PF4, ADC_0, adcPosSelAPORT1XCH20}, - {PF5, ADC_0, adcPosSelAPORT2XCH21}, - {PF6, ADC_0, adcPosSelAPORT1XCH22}, - {PF7, ADC_0, adcPosSelAPORT2XCH23}, + {PE0, ADC_0, adcPosSelAPORT3XCH0}, + {PE1, ADC_0, adcPosSelAPORT4XCH1}, + {PE4, ADC_0, adcPosSelAPORT3XCH4}, + {PE5, ADC_0, adcPosSelAPORT4XCH5}, + {PE6, ADC_0, adcPosSelAPORT3XCH6}, + {PE7, ADC_0, adcPosSelAPORT4XCH7}, + {PE8, ADC_0, adcPosSelAPORT3XCH8}, + {PE9, ADC_0, adcPosSelAPORT4XCH9}, + {PE10, ADC_0, adcPosSelAPORT3XCH10}, + {PE11, ADC_0, adcPosSelAPORT4XCH11}, + {PE12, ADC_0, adcPosSelAPORT3XCH12}, + {PE13, ADC_0, adcPosSelAPORT4XCH13}, + {PE14, ADC_0, adcPosSelAPORT3XCH14}, + {PE15, ADC_0, adcPosSelAPORT4XCH15}, + + {PF0, ADC_0, adcPosSelAPORT3XCH16}, + {PF1, ADC_0, adcPosSelAPORT4XCH17}, + {PF2, ADC_0, adcPosSelAPORT3XCH18}, + {PF3, ADC_0, adcPosSelAPORT4XCH19}, + {PF4, ADC_0, adcPosSelAPORT3XCH20}, + {PF5, ADC_0, adcPosSelAPORT4XCH21}, + {PF6, ADC_0, adcPosSelAPORT3XCH22}, + {PF7, ADC_0, adcPosSelAPORT4XCH23}, + {PF8, ADC_0, adcPosSelAPORT3XCH24}, + {PF9, ADC_0, adcPosSelAPORT4XCH25}, + {PF10, ADC_0, adcPosSelAPORT3XCH26}, + {PF11, ADC_0, adcPosSelAPORT4XCH27}, + {PF12, ADC_0, adcPosSelAPORT3XCH28}, + {PF13, ADC_0, adcPosSelAPORT4XCH31}, + {PF14, ADC_0, adcPosSelAPORT3XCH30}, + {PF15, ADC_0, adcPosSelAPORT4XCH31}, #endif {NC , NC , NC} }; From ace88aa8808d323f47287c158a8ce277f723ce1f Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Tue, 9 Jul 2019 22:48:37 +0100 Subject: [PATCH 08/37] Avoid the FPGA tester using hardware CS which is not supported Also implement rudimentary spi_free... --- targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c index 0b0e2de7a4..c7a2b76d09 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c @@ -274,6 +274,12 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName clk, PinName cs) spi_enable(obj, true); } +void spi_free(spi_t *obj) +{ + spi_enable(obj, false); + USART_Reset(obj->spi.spi); +} + void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable) { if(enable) obj->spi.event |= event; @@ -1434,7 +1440,9 @@ const PinMap *spi_master_miso_pinmap() const PinMap *spi_master_clk_pinmap() { - return PinMap_SPI_CLK; + // We don't currently support hardware CS in master mode. + static const PinMap PinMap_SPI_CLK_mod[] = {NC , NC , NC}; + return PinMap_SPI_CLK_mod; } const PinMap *spi_master_cs_pinmap() From da1a749ab6af7927191ce38418626ce3ad46cd84 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Tue, 9 Jul 2019 22:38:53 +0100 Subject: [PATCH 09/37] Fix for PWM output found by testing against FPGA shield Two issues: * Downcasting too early * Potential for a uint32_t overflow in an intermediate calculation Passing test requires #11005 to be merged. --- targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c index eaeac2ad57..a733f875d4 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c @@ -342,13 +342,13 @@ void pwmout_pulsewidth(pwmout_t *obj, float seconds) void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) { - uint16_t width_cycles = (uint16_t) ((REFERENCE_FREQUENCY >> pwm_prescaler_div) * ms) / 1000; + uint16_t width_cycles = (uint16_t) (((REFERENCE_FREQUENCY >> pwm_prescaler_div) * ms) / 1000); TIMER_CompareBufSet(PWM_TIMER, obj->channel, width_cycles); } void pwmout_pulsewidth_us(pwmout_t *obj, int us) { - uint16_t width_cycles = (uint16_t) ((REFERENCE_FREQUENCY >> pwm_prescaler_div) * us) / 1000000; + uint16_t width_cycles = (uint16_t) (((uint64_t)(REFERENCE_FREQUENCY >> pwm_prescaler_div) * (uint64_t)us) / 1000000UL); TIMER_CompareBufSet(PWM_TIMER, obj->channel, width_cycles); } From eb4b323e2e91dd382f8f44fa68e2acea16ca815b Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 9 Jul 2019 22:34:15 +0200 Subject: [PATCH 10/37] FPGA PWM: wait 1 period before measurement --- TESTS/mbed_hal_fpga_ci_test_shield/pwm/main.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/pwm/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/pwm/main.cpp index 31bf5a7915..2ec859cc3b 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/pwm/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/pwm/main.cpp @@ -122,6 +122,8 @@ void pwm_period_fill_test(PinName pin, uint32_t period_ms, uint32_t fill_prc, pw break; } + wait(PERIOD_FLOAT(period_ms)); + tester.io_metrics_start(); wait(NUM_OF_PERIODS * PERIOD_FLOAT(period_ms)); From e42de1f05503a9e0a0fc8c617c8c826d9fbf3fb6 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 9 Jul 2019 22:33:03 +0200 Subject: [PATCH 11/37] FPFA I2C: correct init bloc number --- TESTS/mbed_hal_fpga_ci_test_shield/i2c/main.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/i2c/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/i2c/main.cpp index 99fcec499a..4c07a3afc9 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/i2c/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/i2c/main.cpp @@ -366,6 +366,7 @@ void i2c_test_byte_read(PinName sda, PinName scl) // Reset tester stats and select I2C tester.peripherals_reset(); tester.select_peripheral(MbedTester::PeripheralI2C); + tester.set_next_from_slave(0); for (int i = 0; i < TRANSFER_COUNT; i++) { data_in[i] = 0; } @@ -413,7 +414,7 @@ void i2c_test_byte_read(PinName sda, PinName scl) TEST_ASSERT_EQUAL(num_nacks, tester.num_nacks()); TEST_ASSERT_EQUAL(checksum, tester.get_send_checksum()); TEST_ASSERT_EQUAL(0, tester.state_num()); - TEST_ASSERT_EQUAL(((TRANSFER_COUNT + 2) & 0xFF), tester.get_next_from_slave()); + TEST_ASSERT_EQUAL(((TRANSFER_COUNT) & 0xFF), tester.get_next_from_slave()); TEST_ASSERT_EQUAL(num_writes, tester.num_writes()); TEST_ASSERT_EQUAL(num_reads, tester.num_reads()); From 0648cf471c969c9148ba4242baf9e57a322dc202 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 9 Jul 2019 10:53:08 +0200 Subject: [PATCH 12/37] HAL: Serial: Add DEVICE_SERIAL_FC guards Functions related to serial flow control should not be exposed if DEVICE_SERIAL_FC is not defined * serial_set_flow_control, * serial_cts_pinmap, * serial_rts_pinmap. --- hal/serial_api.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hal/serial_api.h b/hal/serial_api.h index 68ed74a139..32eb362fb3 100644 --- a/hal/serial_api.h +++ b/hal/serial_api.h @@ -211,6 +211,7 @@ void serial_break_clear(serial_t *obj); */ void serial_pinout_tx(PinName tx); +#if DEVICE_SERIAL_FC /** Configure the serial for the flow control. It sets flow control in the hardware * if a serial peripheral supports it, otherwise software emulation is used. * @@ -220,6 +221,7 @@ void serial_pinout_tx(PinName tx); * @param txflow The RX pin name */ void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow); +#endif /** Get the pins that support Serial TX * @@ -239,6 +241,7 @@ const PinMap *serial_tx_pinmap(void); */ const PinMap *serial_rx_pinmap(void); +#if DEVICE_SERIAL_FC /** Get the pins that support Serial CTS * * Return a PinMap array of pins that support Serial CTS. The @@ -256,6 +259,7 @@ const PinMap *serial_cts_pinmap(void); * @return PinMap array */ const PinMap *serial_rts_pinmap(void); +#endif #if DEVICE_SERIAL_ASYNCH From a8cdabceeed05e22113dd93e4e80e6cfc0f7ffad Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 9 Jul 2019 13:21:42 +0200 Subject: [PATCH 13/37] Test: HAL: serial: Add DEVICE_SERIAL_FC guards Fix undefined references to serial_set_flow_control. --- .../uart/main.cpp | 26 ++++++++++++++----- .../test_utils.h | 2 ++ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp index 6b81a7652f..c83ebb48d7 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp @@ -118,11 +118,13 @@ static void uart_test_common(int baudrate, int data_bits, SerialParity parity, i serial_init(&serial, tx, rx); serial_baud(&serial, baudrate); serial_format(&serial, data_bits, parity, stop_bits); +#if DEVICE_SERIAL_FC if (use_flow_control) { serial_set_flow_control(&serial, FlowControlRTSCTS, rts, cts); } else { serial_set_flow_control(&serial, FlowControlNone, NC, NC); } +#endif // Reset tester stats and select UART tester.peripherals_reset(); @@ -277,9 +279,11 @@ void test_init_free(PinName tx, PinName rx, PinName cts = NC, PinName rts = NC) serial_init(&serial, tx, rx); serial_baud(&serial, 9600); serial_format(&serial, 8, ParityNone, 1); +#if DEVICE_SERIAL_FC if (use_flow_control) { serial_set_flow_control(&serial, FlowControlRTSCTS, rts, cts); } +#endif serial_free(&serial); } @@ -302,28 +306,38 @@ void test_common_no_fc(PinName tx, PinName rx) Case cases[] = { // Every set of pins from every peripheral. - Case("init/free, FC on", all_ports), Case("init/free, FC off", all_ports), // One set of pins from every peripheral. - Case("basic, 9600, 8N1, FC on", all_peripherals >), Case("basic, 9600, 8N1, FC off", all_peripherals >), // One set of pins from one peripheral. // baudrate - Case("19200, 8N1, FC on", one_peripheral >), Case("19200, 8N1, FC off", one_peripheral >), - Case("38400, 8N1, FC on", one_peripheral >), Case("38400, 8N1, FC off", one_peripheral >), - Case("115200, 8N1, FC on", one_peripheral >), Case("115200, 8N1, FC off", one_peripheral >), + // stop bits + Case("9600, 8N2, FC off", one_peripheral >), + +#if DEVICE_SERIAL_FC + // Every set of pins from every peripheral. + Case("init/free, FC on", all_ports), + + // One set of pins from every peripheral. + Case("basic, 9600, 8N1, FC on", all_peripherals >), + + // One set of pins from one peripheral. + // baudrate + Case("19200, 8N1, FC on", one_peripheral >), + Case("38400, 8N1, FC on", one_peripheral >), + Case("115200, 8N1, FC on", one_peripheral >), // data bits: not tested (some platforms support 8 bits only) // parity Case("9600, 8O1, FC on", one_peripheral >), Case("9600, 8E1, FC on", one_peripheral >), // stop bits Case("9600, 8N2, FC on", one_peripheral >), - Case("9600, 8N2, FC off", one_peripheral >), +#endif }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) diff --git a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/test_utils.h b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/test_utils.h index e439a45064..d97739d7f9 100644 --- a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/test_utils.h +++ b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/test_utils.h @@ -511,6 +511,7 @@ typedef Port<1, AnalogoutMaps, DefaultFormFactor, TF1> AnalogoutPort; #endif #if DEVICE_SERIAL +#if DEVICE_SERIAL_FC struct UARTMaps { static const PinMap *maps[]; static const char *const pin_type_names[]; @@ -520,6 +521,7 @@ const PinMap *UARTMaps::maps[] = { serial_tx_pinmap(), serial_rx_pinmap(), seria const char *const UARTMaps::pin_type_names[] = { "TX", "RX", "CLS", "RTS" }; const char *const UARTMaps::name = "UART"; typedef Port<4, UARTMaps, DefaultFormFactor, TF4> UARTPort; +#endif struct UARTNoFCMaps { static const PinMap *maps[]; From 26343e960e9276feaa3291481b12fa375bc605a3 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 9 Jul 2019 16:05:04 +0200 Subject: [PATCH 14/37] FVP_MPS2: Fix serial_init when FC is not used After adding DEVICE_SERIAL_FC guards to serial_api.h serial_set_flow_control is not available. In case of this implementation, this function is a no-op and may be safely removed. --- targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c index 567fcd22ad..cda22d420d 100644 --- a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c +++ b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/serial_api.c @@ -153,7 +153,6 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) } uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_cts.pin = NC; - serial_set_flow_control(obj, FlowControlNone, NC, NC); is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); From 81fd20a07f4fff0b04d666a6e5a76ae6b76ee4e0 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 9 Jul 2019 16:12:32 +0200 Subject: [PATCH 15/37] MPS2: Fix serial_init when FC is not used After adding DEVICE_SERIAL_FC guards to serial_api.h serial_set_flow_control is not available. In case of this implementation, this function is a no-op and may be safely removed. --- targets/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c | 1 - 1 file changed, 1 deletion(-) diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c b/targets/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c index 619033ca5d..a9511b00eb 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/serial_api.c @@ -157,7 +157,6 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { } uart_data[obj->index].sw_rts.pin = NC; uart_data[obj->index].sw_cts.pin = NC; - serial_set_flow_control(obj, FlowControlNone, NC, NC); is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); From e5abb9f7706f6aef0f875c52f6b4155c46523680 Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 9 Jul 2019 16:30:12 +0200 Subject: [PATCH 16/37] RDA5981X: Add SERIAL_FC According to comment in the implementation this target supports the hardware flow control on UART1 peripheral. This patch fixes build errors after adding DEVICE_SERIAL_FC guards to hal/serial_api.h. --- targets/targets.json | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/targets.json b/targets/targets.json index ecbd61a6db..1a6b9a1f89 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -8556,6 +8556,7 @@ "INTERRUPTIN", "EMAC", "SERIAL", + "SERIAL_FC", "STDIO_MESSAGES", "PWMOUT", "SPI", From 622dbe722c0440122b93c516e78d2e5e2ae905bd Mon Sep 17 00:00:00 2001 From: Seppo Takalo Date: Mon, 15 Jul 2019 14:56:22 +0300 Subject: [PATCH 17/37] Normalize line endings for IM880B startup files. --- .gitattributes | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitattributes b/.gitattributes index 05491d6302..15a24c1368 100644 --- a/.gitattributes +++ b/.gitattributes @@ -2,6 +2,7 @@ *.cpp text *.h text *.s text +*.S text *.sct text *.ld text *.txt text From 54de9fa1dfea072b24c86934335f76194b68fd6b Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Wed, 10 Jul 2019 11:35:05 +0100 Subject: [PATCH 18/37] Increase ADC test tolerance to 5% During the SiP workshop, we discovered that 3% is too narrow due to a combination of: Voltage rail differences between target and FPGA Extension of lesser-resolution ADC's to 16-bit results --- TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp index 0add62b502..981ffff4d0 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp @@ -36,8 +36,8 @@ using namespace utest::v1; #define analogin_debug_printf(...) -#define DELTA_FLOAT 0.03f // 3% -#define DELTA_U16 1965 // 3% +#define DELTA_FLOAT 0.05f // 5% +#define DELTA_U16 3277 // 5% const PinList *form_factor = pinmap_ff_default_pins(); const PinList *restricted = pinmap_restricted_pins(); From 87cb6c70382bc7827cece985fc79973107aaa20a Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Thu, 11 Jul 2019 15:24:08 +0100 Subject: [PATCH 19/37] Add a restricted peripheral list Allow peripherals to be excluded from testing. --- .../test_utils.h | 5 +++ hal/mbed_pinmap_common.c | 9 +++++ hal/mbed_pinmap_default.c | 9 +++++ hal/pinmap.h | 39 +++++++++++++++++++ 4 files changed, 62 insertions(+) diff --git a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/test_utils.h b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/test_utils.h index d97739d7f9..14857549b7 100644 --- a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/test_utils.h +++ b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/test_utils.h @@ -115,6 +115,11 @@ void find_ports(std::list &matched_ports, std::list ¬_mat FormFactorType::pin_to_string(port.pins[i]), port.pins[i]); continue; } + if (pinmap_list_has_peripheral(pinmap_restricted_peripherals(), port.peripheral)) { + utest_printf("Skipping %s peripheral %i with pin %s (%i)\r\n", pin_type, + port.peripheral, FormFactorType::pin_to_string(port.pins[i]), port.pins[i]); + continue; + } // skipp pin searching if single pin port type if (PortType::pin_count > 1) { find_port_pins(port); diff --git a/hal/mbed_pinmap_common.c b/hal/mbed_pinmap_common.c index aff140ea4d..2c2643e031 100644 --- a/hal/mbed_pinmap_common.c +++ b/hal/mbed_pinmap_common.c @@ -178,3 +178,12 @@ bool pinmap_list_has_pin(const PinList *list, PinName pin) return false; } +bool pinmap_list_has_peripheral(const PeripheralList *list, int peripheral) +{ + for (uint32_t i = 0; i < list->count; i++) { + if (list->peripheral[i] == peripheral) { + return true; + } + } + return false; +} diff --git a/hal/mbed_pinmap_default.c b/hal/mbed_pinmap_default.c index 780bb68252..dabfabc0ca 100644 --- a/hal/mbed_pinmap_default.c +++ b/hal/mbed_pinmap_default.c @@ -77,3 +77,12 @@ MBED_WEAK const PinList *pinmap_restricted_pins() return &pin_list; } +//*** Default restricted peripherals *** +MBED_WEAK const PeripheralList *pinmap_restricted_peripherals() +{ + static const PeripheralList peripheral_list = { + 0, + 0 + }; + return &peripheral_list; +} diff --git a/hal/pinmap.h b/hal/pinmap.h index b61183a169..b2a8d560f0 100644 --- a/hal/pinmap.h +++ b/hal/pinmap.h @@ -38,6 +38,11 @@ typedef struct { const PinName *pins; } PinList; +typedef struct { + uint32_t count; + const int *peripheral; +} PeripheralList; + void pin_function(PinName pin, int function); void pin_mode(PinName pin, PinMode mode); @@ -123,6 +128,15 @@ bool pinmap_find_peripheral_pins(const PinList *whitelist, const PinList *blackl */ bool pinmap_list_has_pin(const PinList *list, PinName pin); +/** + * Check if the peripheral is in the list + * + * @param list peripheral list to check + * @param peripheral peripheral to check for in the list + * @return true if the peripheral is in the list, false otherwise + */ +bool pinmap_list_has_peripheral(const PeripheralList *list, int peripheral); + /** * Get the pin list of pins to avoid during testing * @@ -139,6 +153,31 @@ bool pinmap_list_has_pin(const PinList *list, PinName pin); */ const PinList *pinmap_restricted_pins(void); +/** + * Get the pin list of peripherals to avoid during testing + * + * The restricted peripheral list is used to indicate to testing + * that a peripheral should be skipped due to some caveat about it. + * For example, using the USB serial port during tests will interfere + * with the test runner and should be avoided. + * + * Targets should override the weak implementation of this + * function if they have peripherals which should be + * skipped during testing. + * + * @note Some targets use the same value for multiple + * different types of peripherals. For example SPI 0 + * and UART 0 may both be identified by the peripheral + * value 0. If your target does this then do not + * use this function to skip peripherals, as this will + * unintentionally cause all peripherals with that value + * to be skipped. Instead these entries should be removed + * from the peripheral PinMap itself. + * + * @return Pointer to a peripheral list of peripheral to avoid + */ +const PeripheralList *pinmap_restricted_peripherals(void); + #ifdef TARGET_FF_ARDUINO /** From 07e858535888534aecd176ecd226315f1898093b Mon Sep 17 00:00:00 2001 From: Russ Butler Date: Thu, 11 Jul 2019 16:13:54 +0100 Subject: [PATCH 20/37] Fix FPGA CI Test Shield warnings Fix warnings due to unused variables, comparison between signed and unsigned. This patch also re-enables I2C asserts that were disabled during early development. --- .../COMPONENT_FPGA_CI_TEST_SHIELD/MbedTester.cpp | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/MbedTester.cpp b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/MbedTester.cpp index fe7d4c8089..f84c505afa 100644 --- a/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/MbedTester.cpp +++ b/components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/MbedTester.cpp @@ -536,8 +536,6 @@ static bool _firmware_header_valid(BlockDevice &flash, bool &valid) static bool _firmware_get_active_bank(BlockDevice &flash, bool &second_bank_active) { uint8_t buf[sizeof(SYNC_WORD)]; - size_t pos = 0; - size_t read_size; if (flash.read(buf, FLASH_SECTOR_SIZE - sizeof(SYNC_WORD), sizeof(SYNC_WORD)) != BD_ERROR_OK) { return false; @@ -708,7 +706,7 @@ bool MbedTester::firmware_dump(mbed::FileHandle *dest, mbed::Callbackwrite(buf, read_size); - if (write_size != read_size) { + if ((uint32_t)write_size != read_size) { sys_pin_mode_disabled(); return false; } @@ -761,7 +759,7 @@ bool MbedTester::firmware_dump_all(mbed::FileHandle *dest, mbed::Callbackwrite(buf, read_size); - if (write_size != read_size) { + if ((uint32_t)write_size != read_size) { sys_pin_mode_disabled(); return false; } @@ -1154,7 +1152,7 @@ uint8_t MbedTester::io_expander_read_index(int index, IOExpanderReg reg_type) } int read_success = io_expander_i2c_read(i2c_index, dev_addr, reg, read_byte, 1); - // MBED_ASSERT(read_success == 0); + MBED_ASSERT(read_success == 0); uint8_t bit = (read_byte[0] & (1 << reg_bit)) >> reg_bit; return bit; } @@ -1489,7 +1487,7 @@ uint8_t MbedTester::io_expander_read_bb(PinName pin, IOExpanderReg reg_type) } int read_success = io_expander_i2c_read_bb(sda, scl, dev_addr, reg, read_byte, 1); - // MBED_ASSERT(read_success == 0); + MBED_ASSERT(read_success == 0); uint8_t bit = (read_byte[0] & (1 << reg_bit)) >> reg_bit; return bit; } From 06193b6601670ce04c98b63c250df4c6df83d3d9 Mon Sep 17 00:00:00 2001 From: Yuan Cao Date: Sat, 13 Jul 2019 00:05:25 -0400 Subject: [PATCH 21/37] Fixed serial_device IRQ infinite loop bug due to uint8_t overflowing --- targets/TARGET_STM/TARGET_STM32F0/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32F1/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32F2/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32F3/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32F4/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32F7/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32H7/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32L0/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32L1/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32L4/serial_device.c | 2 +- targets/TARGET_STM/TARGET_STM32WB/serial_device.c | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c index f6954a2968..5dc1ac9dbc 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F0/serial_device.c @@ -605,7 +605,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c index 3675668b07..d351e6838c 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F1/serial_device.c @@ -476,7 +476,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c index 9ed602867e..4853f3d825 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F2/serial_device.c @@ -559,7 +559,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c index 81f2c8aa25..a9fa18498d 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F3/serial_device.c @@ -522,7 +522,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c index 79a76bf689..e2f076641f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F4/serial_device.c @@ -604,7 +604,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c index 3668ce7ce1..66ba5c0369 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32F7/serial_device.c @@ -560,7 +560,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32H7/serial_device.c b/targets/TARGET_STM/TARGET_STM32H7/serial_device.c index f3f9c7ee9d..c9eeb4e37a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/serial_device.c @@ -573,7 +573,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c index 012fcebe5a..d57bb96804 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L0/serial_device.c @@ -500,7 +500,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c index 3b84db9d63..3b807fc949 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L1/serial_device.c @@ -512,7 +512,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c index 1e5d505a77..bb1bc5e4de 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/serial_device.c @@ -536,7 +536,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32WB/serial_device.c b/targets/TARGET_STM/TARGET_STM32WB/serial_device.c index c0262aac1f..2e9ec5df51 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32WB/serial_device.c @@ -461,7 +461,7 @@ int serial_irq_handler_asynch(serial_t *obj) volatile int return_event = 0; uint8_t *buf = (uint8_t *)(obj->rx_buff.buffer); - uint8_t i = 0; + size_t i = 0; // TX PART: if (__HAL_UART_GET_FLAG(huart, UART_FLAG_TC) != RESET) { From 1ad10d72c74030cf257fe89db50e7d4c6468bea0 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 21 Jun 2019 10:34:00 -0500 Subject: [PATCH 22/37] LPC546XX: Update the ADC SDK driver Signed-off-by: Mahesh Mahadevan --- .../device/LPC54628_features.h | 605 ++------ .../TARGET_MCU_LPC546XX/drivers/fsl_adc.c | 308 +++- .../TARGET_MCU_LPC546XX/drivers/fsl_adc.h | 218 ++- .../TARGET_MCU_LPC546XX/drivers/fsl_clock.c | 1373 ++++++++++++----- .../TARGET_MCU_LPC546XX/drivers/fsl_clock.h | 941 +++++------ 5 files changed, 2075 insertions(+), 1370 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/LPC54628_features.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/LPC54628_features.h index 47e7aa8aed..6f91cf5080 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/LPC54628_features.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/device/LPC54628_features.h @@ -1,37 +1,16 @@ /* ** ################################################################### ** Version: rev. 1.2, 2017-06-08 -** Build: b170609 +** Build: b190225 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** Copyright 2016-2019 NXP +** All rights reserved. ** -** 1. Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** 2. Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** 3. Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -55,502 +34,105 @@ /* SOC module features */ -/* @brief ACMP availability on the SoC. */ -#define FSL_FEATURE_SOC_ACMP_COUNT (0) /* @brief ADC availability on the SoC. */ #define FSL_FEATURE_SOC_ADC_COUNT (1) -/* @brief ADC12 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC12_COUNT (0) -/* @brief ADC16 availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC16_COUNT (0) -/* @brief ADC_5HC availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0) -/* @brief AES availability on the SoC. */ -#define FSL_FEATURE_SOC_AES_COUNT (0) -/* @brief AFE availability on the SoC. */ -#define FSL_FEATURE_SOC_AFE_COUNT (0) -/* @brief AGC availability on the SoC. */ -#define FSL_FEATURE_SOC_AGC_COUNT (0) -/* @brief AIPS availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPS_COUNT (0) -/* @brief AIPSTZ availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPSTZ_COUNT (0) -/* @brief ANATOP availability on the SoC. */ -#define FSL_FEATURE_SOC_ANATOP_COUNT (0) -/* @brief AOI availability on the SoC. */ -#define FSL_FEATURE_SOC_AOI_COUNT (0) -/* @brief APBH availability on the SoC. */ -#define FSL_FEATURE_SOC_APBH_COUNT (0) -/* @brief ASMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASMC_COUNT (0) -/* @brief ASRC availability on the SoC. */ -#define FSL_FEATURE_SOC_ASRC_COUNT (0) /* @brief ASYNC_SYSCON availability on the SoC. */ #define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) -/* @brief ATX availability on the SoC. */ -#define FSL_FEATURE_SOC_ATX_COUNT (0) -/* @brief AXBS availability on the SoC. */ -#define FSL_FEATURE_SOC_AXBS_COUNT (0) -/* @brief BCH availability on the SoC. */ -#define FSL_FEATURE_SOC_BCH_COUNT (0) -/* @brief BLEDP availability on the SoC. */ -#define FSL_FEATURE_SOC_BLEDP_COUNT (0) -/* @brief BOD availability on the SoC. */ -#define FSL_FEATURE_SOC_BOD_COUNT (0) -/* @brief CAAM availability on the SoC. */ -#define FSL_FEATURE_SOC_CAAM_COUNT (0) -/* @brief CADC availability on the SoC. */ -#define FSL_FEATURE_SOC_CADC_COUNT (0) -/* @brief CALIB availability on the SoC. */ -#define FSL_FEATURE_SOC_CALIB_COUNT (0) /* @brief CAN availability on the SoC. */ #define FSL_FEATURE_SOC_LPC_CAN_COUNT (2) -/* @brief CAU availability on the SoC. */ -#define FSL_FEATURE_SOC_CAU_COUNT (0) -/* @brief CAU3 availability on the SoC. */ -#define FSL_FEATURE_SOC_CAU3_COUNT (0) -/* @brief CCM availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_COUNT (0) -/* @brief CCM_ANALOG availability on the SoC. */ -#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (0) -/* @brief CHRG availability on the SoC. */ -#define FSL_FEATURE_SOC_CHRG_COUNT (0) -/* @brief CMP availability on the SoC. */ -#define FSL_FEATURE_SOC_CMP_COUNT (0) -/* @brief CMT availability on the SoC. */ -#define FSL_FEATURE_SOC_CMT_COUNT (0) -/* @brief CNC availability on the SoC. */ -#define FSL_FEATURE_SOC_CNC_COUNT (0) -/* @brief COP availability on the SoC. */ -#define FSL_FEATURE_SOC_COP_COUNT (0) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief CS availability on the SoC. */ -#define FSL_FEATURE_SOC_CS_COUNT (0) -/* @brief CSI availability on the SoC. */ -#define FSL_FEATURE_SOC_CSI_COUNT (0) -/* @brief CT32B availability on the SoC. */ -#define FSL_FEATURE_SOC_CT32B_COUNT (0) -/* @brief CTI availability on the SoC. */ -#define FSL_FEATURE_SOC_CTI_COUNT (0) /* @brief CTIMER availability on the SoC. */ #define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief DAC availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC_COUNT (0) -/* @brief DAC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_DAC32_COUNT (0) -/* @brief DCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_DCDC_COUNT (0) -/* @brief DCP availability on the SoC. */ -#define FSL_FEATURE_SOC_DCP_COUNT (0) -/* @brief DDR availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_COUNT (0) -/* @brief DDRC availability on the SoC. */ -#define FSL_FEATURE_SOC_DDRC_COUNT (0) -/* @brief DDRC_MP availability on the SoC. */ -#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0) -/* @brief DDR_PHY availability on the SoC. */ -#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0) /* @brief DMA availability on the SoC. */ #define FSL_FEATURE_SOC_DMA_COUNT (1) -/* @brief DMAMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_DMAMUX_COUNT (0) /* @brief DMIC availability on the SoC. */ #define FSL_FEATURE_SOC_DMIC_COUNT (1) -/* @brief DRY availability on the SoC. */ -#define FSL_FEATURE_SOC_DRY_COUNT (0) -/* @brief DSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_DSPI_COUNT (0) -/* @brief ECSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_ECSPI_COUNT (0) -/* @brief EDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_EDMA_COUNT (0) /* @brief EEPROM availability on the SoC. */ #define FSL_FEATURE_SOC_EEPROM_COUNT (1) -/* @brief EIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EIM_COUNT (0) /* @brief EMC availability on the SoC. */ #define FSL_FEATURE_SOC_EMC_COUNT (1) -/* @brief EMVSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) -/* @brief ENC availability on the SoC. */ -#define FSL_FEATURE_SOC_ENC_COUNT (0) /* @brief ENET availability on the SoC. */ #define FSL_FEATURE_SOC_LPC_ENET_COUNT (1) -/* @brief EPDC availability on the SoC. */ -#define FSL_FEATURE_SOC_EPDC_COUNT (0) -/* @brief EPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_EPIT_COUNT (0) -/* @brief ESAI availability on the SoC. */ -#define FSL_FEATURE_SOC_ESAI_COUNT (0) -/* @brief EWM availability on the SoC. */ -#define FSL_FEATURE_SOC_EWM_COUNT (0) -/* @brief FB availability on the SoC. */ -#define FSL_FEATURE_SOC_FB_COUNT (0) -/* @brief FGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FGPIO_COUNT (0) -/* @brief FLASH availability on the SoC. */ -#define FSL_FEATURE_SOC_FLASH_COUNT (0) -/* @brief FLEXCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) /* @brief FLEXCOMM availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10) -/* @brief FLEXIO availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) -/* @brief FLEXRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXRAM_COUNT (0) -/* @brief FLEXSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXSPI_COUNT (0) /* @brief FMC availability on the SoC. */ #define FSL_FEATURE_SOC_FMC_COUNT (1) -/* @brief FSKDT availability on the SoC. */ -#define FSL_FEATURE_SOC_FSKDT_COUNT (0) -/* @brief FSP availability on the SoC. */ -#define FSL_FEATURE_SOC_FSP_COUNT (0) -/* @brief FTFA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFA_COUNT (0) -/* @brief FTFE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFE_COUNT (0) -/* @brief FTFL availability on the SoC. */ -#define FSL_FEATURE_SOC_FTFL_COUNT (0) -/* @brief FTM availability on the SoC. */ -#define FSL_FEATURE_SOC_FTM_COUNT (0) -/* @brief FTMRA availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRA_COUNT (0) -/* @brief FTMRE availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRE_COUNT (0) -/* @brief FTMRH availability on the SoC. */ -#define FSL_FEATURE_SOC_FTMRH_COUNT (0) /* @brief GINT availability on the SoC. */ #define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPC availability on the SoC. */ -#define FSL_FEATURE_SOC_GPC_COUNT (0) -/* @brief GPC_PGC availability on the SoC. */ -#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0) /* @brief GPIO availability on the SoC. */ #define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief GPMI availability on the SoC. */ -#define FSL_FEATURE_SOC_GPMI_COUNT (0) -/* @brief GPT availability on the SoC. */ -#define FSL_FEATURE_SOC_GPT_COUNT (0) -/* @brief HSADC availability on the SoC. */ -#define FSL_FEATURE_SOC_HSADC_COUNT (0) /* @brief I2C availability on the SoC. */ #define FSL_FEATURE_SOC_I2C_COUNT (10) /* @brief I2S availability on the SoC. */ #define FSL_FEATURE_SOC_I2S_COUNT (2) -/* @brief ICS availability on the SoC. */ -#define FSL_FEATURE_SOC_ICS_COUNT (0) -/* @brief IEE availability on the SoC. */ -#define FSL_FEATURE_SOC_IEE_COUNT (0) -/* @brief IEER availability on the SoC. */ -#define FSL_FEATURE_SOC_IEER_COUNT (0) -/* @brief IGPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_IGPIO_COUNT (0) -/* @brief II2C availability on the SoC. */ -#define FSL_FEATURE_SOC_II2C_COUNT (0) /* @brief INPUTMUX availability on the SoC. */ #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief INTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INTMUX_COUNT (0) /* @brief IOCON availability on the SoC. */ #define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief IOMUXC availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_COUNT (0) -/* @brief IOMUXC_GPR availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (0) -/* @brief IOMUXC_LPSR availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0) -/* @brief IOMUXC_LPSR_GPR availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0) -/* @brief IOMUXC_SNVS availability on the SoC. */ -#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (0) -/* @brief IPWM availability on the SoC. */ -#define FSL_FEATURE_SOC_IPWM_COUNT (0) -/* @brief IRQ availability on the SoC. */ -#define FSL_FEATURE_SOC_IRQ_COUNT (0) -/* @brief IUART availability on the SoC. */ -#define FSL_FEATURE_SOC_IUART_COUNT (0) -/* @brief KBI availability on the SoC. */ -#define FSL_FEATURE_SOC_KBI_COUNT (0) -/* @brief KPP availability on the SoC. */ -#define FSL_FEATURE_SOC_KPP_COUNT (0) -/* @brief L2CACHEC availability on the SoC. */ -#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0) /* @brief LCD availability on the SoC. */ #define FSL_FEATURE_SOC_LCD_COUNT (1) -/* @brief LCDC availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDC_COUNT (0) -/* @brief LCDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_LCDIF_COUNT (0) -/* @brief LDO availability on the SoC. */ -#define FSL_FEATURE_SOC_LDO_COUNT (0) -/* @brief LLWU availability on the SoC. */ -#define FSL_FEATURE_SOC_LLWU_COUNT (0) -/* @brief LMEM availability on the SoC. */ -#define FSL_FEATURE_SOC_LMEM_COUNT (0) -/* @brief LPADC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPADC_COUNT (0) -/* @brief LPCMP availability on the SoC. */ -#define FSL_FEATURE_SOC_LPCMP_COUNT (0) -/* @brief LPDAC availability on the SoC. */ -#define FSL_FEATURE_SOC_LPDAC_COUNT (0) -/* @brief LPI2C availability on the SoC. */ -#define FSL_FEATURE_SOC_LPI2C_COUNT (0) -/* @brief LPIT availability on the SoC. */ -#define FSL_FEATURE_SOC_LPIT_COUNT (0) -/* @brief LPSCI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSCI_COUNT (0) -/* @brief LPSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_LPSPI_COUNT (0) -/* @brief LPTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTMR_COUNT (0) -/* @brief LPTPM availability on the SoC. */ -#define FSL_FEATURE_SOC_LPTPM_COUNT (0) -/* @brief LPUART availability on the SoC. */ -#define FSL_FEATURE_SOC_LPUART_COUNT (0) -/* @brief LTC availability on the SoC. */ -#define FSL_FEATURE_SOC_LTC_COUNT (0) -/* @brief MAILBOX availability on the SoC. */ -#define FSL_FEATURE_SOC_MAILBOX_COUNT (0) -/* @brief MC availability on the SoC. */ -#define FSL_FEATURE_SOC_MC_COUNT (0) -/* @brief MCG availability on the SoC. */ -#define FSL_FEATURE_SOC_MCG_COUNT (0) -/* @brief MCGLITE availability on the SoC. */ -#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) -/* @brief MCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MCM_COUNT (0) -/* @brief MIPI_CSI2 availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0) -/* @brief MIPI_DSI availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0) -/* @brief MIPI_DSI_HOST availability on the SoC. */ -#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0) -/* @brief MMAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMAU_COUNT (0) -/* @brief MMCAU availability on the SoC. */ -#define FSL_FEATURE_SOC_MMCAU_COUNT (0) -/* @brief MMDC availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDC_COUNT (0) -/* @brief MMDVSQ availability on the SoC. */ -#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) -/* @brief MPU availability on the SoC. */ -#define FSL_FEATURE_SOC_MPU_COUNT (0) /* @brief MRT availability on the SoC. */ #define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief MSCAN availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCAN_COUNT (0) -/* @brief MSCM availability on the SoC. */ -#define FSL_FEATURE_SOC_MSCM_COUNT (0) -/* @brief MTB availability on the SoC. */ -#define FSL_FEATURE_SOC_MTB_COUNT (0) -/* @brief MTBDWT availability on the SoC. */ -#define FSL_FEATURE_SOC_MTBDWT_COUNT (0) -/* @brief MU availability on the SoC. */ -#define FSL_FEATURE_SOC_MU_COUNT (0) -/* @brief NFC availability on the SoC. */ -#define FSL_FEATURE_SOC_NFC_COUNT (0) -/* @brief OCOTP availability on the SoC. */ -#define FSL_FEATURE_SOC_OCOTP_COUNT (0) -/* @brief OPAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_OPAMP_COUNT (0) -/* @brief OSC availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC_COUNT (0) -/* @brief OSC32 availability on the SoC. */ -#define FSL_FEATURE_SOC_OSC32_COUNT (0) -/* @brief OTFAD availability on the SoC. */ -#define FSL_FEATURE_SOC_OTFAD_COUNT (0) -/* @brief PCC availability on the SoC. */ -#define FSL_FEATURE_SOC_PCC_COUNT (0) -/* @brief PCIE_PHY_CMN availability on the SoC. */ -#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0) -/* @brief PCIE_PHY_TRSV availability on the SoC. */ -#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0) -/* @brief PDB availability on the SoC. */ -#define FSL_FEATURE_SOC_PDB_COUNT (0) -/* @brief PGA availability on the SoC. */ -#define FSL_FEATURE_SOC_PGA_COUNT (0) /* @brief PINT availability on the SoC. */ #define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief PIT availability on the SoC. */ -#define FSL_FEATURE_SOC_PIT_COUNT (0) -/* @brief PMC availability on the SoC. */ -#define FSL_FEATURE_SOC_PMC_COUNT (0) -/* @brief PMU availability on the SoC. */ -#define FSL_FEATURE_SOC_PMU_COUNT (0) -/* @brief PORT availability on the SoC. */ -#define FSL_FEATURE_SOC_PORT_COUNT (0) -/* @brief PROP availability on the SoC. */ -#define FSL_FEATURE_SOC_PROP_COUNT (0) -/* @brief PWM availability on the SoC. */ -#define FSL_FEATURE_SOC_PWM_COUNT (0) -/* @brief PWT availability on the SoC. */ -#define FSL_FEATURE_SOC_PWT_COUNT (0) -/* @brief PXP availability on the SoC. */ -#define FSL_FEATURE_SOC_PXP_COUNT (0) -/* @brief QDEC availability on the SoC. */ -#define FSL_FEATURE_SOC_QDEC_COUNT (0) -/* @brief QuadSPI availability on the SoC. */ -#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) -/* @brief RCM availability on the SoC. */ -#define FSL_FEATURE_SOC_RCM_COUNT (0) -/* @brief RDC availability on the SoC. */ -#define FSL_FEATURE_SOC_RDC_COUNT (0) -/* @brief RDC_SEMAPHORE availability on the SoC. */ -#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0) -/* @brief RFSYS availability on the SoC. */ -#define FSL_FEATURE_SOC_RFSYS_COUNT (0) -/* @brief RFVBAT availability on the SoC. */ -#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) /* @brief RIT availability on the SoC. */ #define FSL_FEATURE_SOC_RIT_COUNT (1) /* @brief RNG availability on the SoC. */ #define FSL_FEATURE_SOC_LPC_RNG_COUNT (1) -/* @brief RNGB availability on the SoC. */ -#define FSL_FEATURE_SOC_RNGB_COUNT (0) -/* @brief ROM availability on the SoC. */ -#define FSL_FEATURE_SOC_ROM_COUNT (0) -/* @brief ROMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ROMC_COUNT (0) -/* @brief RSIM availability on the SoC. */ -#define FSL_FEATURE_SOC_RSIM_COUNT (0) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCG availability on the SoC. */ -#define FSL_FEATURE_SOC_SCG_COUNT (0) -/* @brief SCI availability on the SoC. */ -#define FSL_FEATURE_SOC_SCI_COUNT (0) /* @brief SCT availability on the SoC. */ #define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_SDHC_COUNT (0) /* @brief SDIF availability on the SoC. */ #define FSL_FEATURE_SOC_SDIF_COUNT (1) -/* @brief SDIO availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIO_COUNT (0) -/* @brief SDMA availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMA_COUNT (0) -/* @brief SDMAARM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMAARM_COUNT (0) -/* @brief SDMABP availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMABP_COUNT (0) -/* @brief SDMACORE availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMACORE_COUNT (0) -/* @brief SDMCORE availability on the SoC. */ -#define FSL_FEATURE_SOC_SDMCORE_COUNT (0) -/* @brief SDRAM availability on the SoC. */ -#define FSL_FEATURE_SOC_SDRAM_COUNT (0) -/* @brief SEMA4 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA4_COUNT (0) -/* @brief SEMA42 availability on the SoC. */ -#define FSL_FEATURE_SOC_SEMA42_COUNT (0) /* @brief SHA availability on the SoC. */ #define FSL_FEATURE_SOC_SHA_COUNT (1) -/* @brief SIM availability on the SoC. */ -#define FSL_FEATURE_SOC_SIM_COUNT (0) -/* @brief SJC availability on the SoC. */ -#define FSL_FEATURE_SOC_SJC_COUNT (0) -/* @brief SLCD availability on the SoC. */ -#define FSL_FEATURE_SOC_SLCD_COUNT (0) /* @brief SMARTCARD availability on the SoC. */ #define FSL_FEATURE_SOC_SMARTCARD_COUNT (2) -/* @brief SMC availability on the SoC. */ -#define FSL_FEATURE_SOC_SMC_COUNT (0) -/* @brief SNVS availability on the SoC. */ -#define FSL_FEATURE_SOC_SNVS_COUNT (0) -/* @brief SPBA availability on the SoC. */ -#define FSL_FEATURE_SOC_SPBA_COUNT (0) -/* @brief SPDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SPDIF_COUNT (0) /* @brief SPI availability on the SoC. */ #define FSL_FEATURE_SOC_SPI_COUNT (10) /* @brief SPIFI availability on the SoC. */ #define FSL_FEATURE_SOC_SPIFI_COUNT (1) -/* @brief SPM availability on the SoC. */ -#define FSL_FEATURE_SOC_SPM_COUNT (0) -/* @brief SRC availability on the SoC. */ -#define FSL_FEATURE_SOC_SRC_COUNT (0) /* @brief SYSCON availability on the SoC. */ #define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief TEMPMON availability on the SoC. */ -#define FSL_FEATURE_SOC_TEMPMON_COUNT (0) -/* @brief TMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TMR_COUNT (0) -/* @brief TPM availability on the SoC. */ -#define FSL_FEATURE_SOC_TPM_COUNT (0) -/* @brief TRGMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) -/* @brief TRIAMP availability on the SoC. */ -#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) -/* @brief TRNG availability on the SoC. */ -#define FSL_FEATURE_SOC_TRNG_COUNT (0) -/* @brief TSC availability on the SoC. */ -#define FSL_FEATURE_SOC_TSC_COUNT (0) -/* @brief TSI availability on the SoC. */ -#define FSL_FEATURE_SOC_TSI_COUNT (0) -/* @brief TSTMR availability on the SoC. */ -#define FSL_FEATURE_SOC_TSTMR_COUNT (0) -/* @brief UART availability on the SoC. */ -#define FSL_FEATURE_SOC_UART_COUNT (0) /* @brief USART availability on the SoC. */ #define FSL_FEATURE_SOC_USART_COUNT (10) /* @brief USB availability on the SoC. */ #define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief USBHS availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHS_COUNT (0) -/* @brief USBDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBDCD_COUNT (0) /* @brief USBFSH availability on the SoC. */ #define FSL_FEATURE_SOC_USBFSH_COUNT (1) /* @brief USBHSD availability on the SoC. */ #define FSL_FEATURE_SOC_USBHSD_COUNT (1) -/* @brief USBHSDCD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) /* @brief USBHSH availability on the SoC. */ #define FSL_FEATURE_SOC_USBHSH_COUNT (1) -/* @brief USBNC availability on the SoC. */ -#define FSL_FEATURE_SOC_USBNC_COUNT (0) -/* @brief USBPHY availability on the SoC. */ -#define FSL_FEATURE_SOC_USBPHY_COUNT (0) -/* @brief USB_HSIC availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0) -/* @brief USB_OTG availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_OTG_COUNT (0) -/* @brief USBVREG availability on the SoC. */ -#define FSL_FEATURE_SOC_USBVREG_COUNT (0) -/* @brief USDHC availability on the SoC. */ -#define FSL_FEATURE_SOC_USDHC_COUNT (0) /* @brief UTICK availability on the SoC. */ #define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief VIU availability on the SoC. */ -#define FSL_FEATURE_SOC_VIU_COUNT (0) -/* @brief VREF availability on the SoC. */ -#define FSL_FEATURE_SOC_VREF_COUNT (0) -/* @brief VFIFO availability on the SoC. */ -#define FSL_FEATURE_SOC_VFIFO_COUNT (0) -/* @brief WDOG availability on the SoC. */ -#define FSL_FEATURE_SOC_WDOG_COUNT (0) -/* @brief WKPU availability on the SoC. */ -#define FSL_FEATURE_SOC_WKPU_COUNT (0) /* @brief WWDT availability on the SoC. */ #define FSL_FEATURE_SOC_WWDT_COUNT (1) -/* @brief XBAR availability on the SoC. */ -#define FSL_FEATURE_SOC_XBAR_COUNT (0) -/* @brief XBARA availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARA_COUNT (0) -/* @brief XBARB availability on the SoC. */ -#define FSL_FEATURE_SOC_XBARB_COUNT (0) -/* @brief XCVR availability on the SoC. */ -#define FSL_FEATURE_SOC_XCVR_COUNT (0) -/* @brief XRDC availability on the SoC. */ -#define FSL_FEATURE_SOC_XRDC_COUNT (0) -/* @brief XTALOSC availability on the SoC. */ -#define FSL_FEATURE_SOC_XTALOSC_COUNT (0) -/* @brief XTALOSC24M availability on the SoC. */ -#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (0) -/* @brief ZLL availability on the SoC. */ -#define FSL_FEATURE_SOC_ZLL_COUNT (0) + +/* ADC module features */ + +/* @brief Do not has input select (register INSEL). */ +#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) +/* @brief Has startup register. */ +#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) +/* @brief Has ADTrim register */ +#define FSL_FEATURE_ADC_HAS_TRIM_REG (0) +/* @brief Has Calibration register. */ +#define FSL_FEATURE_ADC_HAS_CALIB_REG (1) /* CAN module features */ @@ -561,6 +143,10 @@ /* @brief Number of channels */ #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) /* EEPROM module features */ @@ -575,16 +161,124 @@ /* @brief EEPROM internal clock freqency */ #define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000) +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM7 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) +/* @brief FLEXCOMM4 USART INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_USART_INDEX (8) +/* @brief FLEXCOMM4 SPI INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) +/* @brief FLEXCOMM4 I2C INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_I2C_INDEX (8) +/* @brief FLEXCOMM5 USART INDEX 9 */ +#define FSL_FEATURE_FLEXCOMM9_USART_INDEX (9) +/* @brief FLEXCOMM5 SPI INDEX 9 */ +#define FSL_FEATURE_FLEXCOMM9_SPI_INDEX (9) +/* @brief FLEXCOMM5 I2C INDEX 9 */ +#define FSL_FEATURE_FLEXCOMM9_I2C_INDEX (9) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ + (((x) == FLEXCOMM0) ? (0) : \ + (((x) == FLEXCOMM1) ? (0) : \ + (((x) == FLEXCOMM2) ? (0) : \ + (((x) == FLEXCOMM3) ? (0) : \ + (((x) == FLEXCOMM4) ? (0) : \ + (((x) == FLEXCOMM5) ? (0) : \ + (((x) == FLEXCOMM6) ? (0) : \ + (((x) == FLEXCOMM7) ? (1) : \ + (((x) == FLEXCOMM8) ? (0) : \ + (((x) == FLEXCOMM9) ? (0) : (-1))))))))))) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) + /* IOCON module features */ /* @brief Func bit field width */ #define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) + /* PINT module features */ /* @brief Number of connected outputs */ #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* RIT module features */ + +/* @brief RIT has no reset control */ +#define FSL_FEATURE_RIT_HAS_NO_RESET (1) + +/* RTC module features */ + +/* @brief RTC has no reset control */ +#define FSL_FEATURE_RTC_HAS_NO_RESET (1) + /* SCT module features */ /* @brief Number of events */ @@ -593,6 +287,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) /* @brief Number of match capture */ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10) /* SDIF module features */ @@ -620,6 +316,21 @@ #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) /* @brief Flash size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) +/* @brief IAP has Flash read & write function */ +#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) +/* @brief IAP has EEPROM read & write function */ +#define FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION (1) +/* @brief IAP has read Flash signature function */ +#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (0) +/* @brief IAP has read extended Flash signature function */ +#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (1) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) /* USB module features */ @@ -627,6 +338,8 @@ #define FSL_FEATURE_USB_USB_RAM (0x00002000) /* @brief Base address of the USB dedicated RAM */ #define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) /* USBFSH module features */ @@ -641,6 +354,8 @@ #define FSL_FEATURE_USBHSD_USB_RAM (0x00002000) /* @brief Base address of the USB dedicated RAM */ #define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBHSD_EP_NUM (6) /* USBHSH module features */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_adc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_adc.c index 6b23b903fb..9dda535e6f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_adc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_adc.c @@ -1,45 +1,26 @@ /* - * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2019 NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_adc.h" #include "fsl_clock.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_adc" +#endif + static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#define FREQUENCY_1MHZ (1000000U) + static uint32_t ADC_GetInstance(ADC_Type *base) { uint32_t instance; @@ -58,6 +39,12 @@ static uint32_t ADC_GetInstance(ADC_Type *base) return instance; } +/*! + * brief Initialize the ADC module. + * + * param base ADC peripheral base address. + * param config Pointer to configuration structure, see to #adc_config_t. + */ void ADC_Init(ADC_Type *base, const adc_config_t *config) { assert(config != NULL); @@ -75,6 +62,7 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config) /* Configure the ADC block. */ tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber); +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE /* Async or Sync clock mode. */ switch (config->clockMode) { @@ -84,31 +72,112 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config) default: /* kADC_ClockSynchronousMode */ break; } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL /* Resolution. */ - tmp32 |= ADC_CTRL_RESOL(config->resolution); + tmp32 |= ADC_CTRL_RESOL(config->resolution); +#endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL /* Bypass calibration. */ if (config->enableBypassCalibration) { tmp32 |= ADC_CTRL_BYPASSCAL_MASK; } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ - /* Sample time clock count. */ - tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber); +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP +/* Sample time clock count. */ +#if (defined(FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL) && FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL) + if (config->clockMode == kADC_ClockAsynchronousMode) + { +#endif /* FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL */ + tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber); +#if (defined(FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL) && FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL) + } +#endif /* FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + if (config->enableLowPowerMode) + { + tmp32 |= ADC_CTRL_LPWRMODE_MASK; + } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ base->CTRL = tmp32; + +#if defined(FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN) && FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN + base->GPADC_CTRL0 |= ADC_GPADC_CTRL0_LDO_POWER_EN_MASK; + if (config->clockMode == kADC_ClockSynchronousMode) + { + base->GPADC_CTRL0 |= ADC_GPADC_CTRL0_PASS_ENABLE(config->sampleTimeNumber); + } +#endif /* FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN */ + +#if defined(FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL) && FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL + tmp32 = *(uint32_t *)FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL; + if (tmp32 & FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID) + { + base->GPADC_CTRL1 = (tmp32 >> 1); + } +#if !(defined(FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT) && FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT) + base->STARTUP = ADC_STARTUP_ADC_ENA_MASK; /* Set the ADC Start bit */ +#endif /* FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL */ +#endif /* FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL */ + +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + base->TRM &= ~ADC_TRM_VRANGE_MASK; + base->TRM |= ADC_TRM_VRANGE(config->voltageRange); +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ } +/*! + * brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the initial configuration structure with an available settings. The default values are: + * code + * config->clockMode = kADC_ClockSynchronousMode; + * config->clockDividerNumber = 0U; + * config->resolution = kADC_Resolution12bit; + * config->enableBypassCalibration = false; + * config->sampleTimeNumber = 0U; + * endcode + * param config Pointer to configuration structure. + */ void ADC_GetDefaultConfig(adc_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + config->clockMode = kADC_ClockSynchronousMode; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ + config->clockDividerNumber = 0U; +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL config->resolution = kADC_Resolution12bit; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL config->enableBypassCalibration = false; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP config->sampleTimeNumber = 0U; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + config->enableLowPowerMode = false; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + config->voltageRange = kADC_HighVoltageRange; +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ } +/*! + * brief Deinitialize the ADC module. + * + * param base ADC peripheral base address. + */ void ADC_Deinit(ADC_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -117,53 +186,122 @@ void ADC_Deinit(ADC_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) +#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) & FSL_FEATURE_ADC_HAS_CALIB_REG +/*! + * brief Do the self calibration. To calibrate the ADC, set the ADC clock to 1 mHz. + * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, + * following every chip reset before initiating normal ADC operation. + * + * param base ADC peripheral base address. + * retval true Calibration succeed. + * retval false Calibration failed. + */ bool ADC_DoSelfCalibration(ADC_Type *base) { - uint32_t i; + uint32_t frequency = 0U; + uint32_t delayUs = 0U; /* Enable the converter. */ /* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down. This bit should be set after at least 10 ms after the ADC is powered on. */ base->STARTUP = ADC_STARTUP_ADC_ENA_MASK; - for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */ - { - __ASM("NOP"); - } + SDK_DelayAtLeastUs(1U); if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK)) { return false; /* ADC is not powered up. */ } + /* Get the ADC clock frequency in synchronous mode. */ + frequency = CLOCK_GetFreq(kCLOCK_BusClk) / (((base->CTRL & ADC_CTRL_CLKDIV_MASK) >> ADC_CTRL_CLKDIV_SHIFT) + 1); + base->CTRL |= ADC_CTRL_CLKDIV((frequency / 1000000U) - 1U); + frequency = 1000000U; +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) && FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + /* Get the ADC clock frequency in asynchronous mode. */ + if (ADC_CTRL_ASYNMODE_MASK == (base->CTRL & ADC_CTRL_ASYNMODE_MASK)) + { + frequency = CLOCK_GetAdcClkFreq(); + } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE */ + assert(0U != frequency); + /* If not in by-pass mode, do the calibration. */ if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) && (0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK))) { + /* A calibration cycle requires approximately 81 ADC clocks to complete. */ + delayUs = (120 * FREQUENCY_1MHZ) / frequency + 1; /* Calibration is needed, do it now. */ base->CALIB = ADC_CALIB_CALIB_MASK; - i = 0xF0000; - while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i)) - { - } - if (i == 0U) + SDK_DelayAtLeastUs(delayUs); + if (ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) { return false; /* Calibration timeout. */ } } - /* A dummy conversion cycle will be performed. */ + /* A “dummy” conversion cycle requires approximately 6 ADC clocks */ + delayUs = (10 * FREQUENCY_1MHZ) / frequency + 1; base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK; - i = 0x7FFFF; - while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i)) - { - } - if (i == 0U) + SDK_DelayAtLeastUs(delayUs); + if (ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) { return false; } return true; } +#else +/*! + * brief Do the self calibration. To calibrate the ADC, set the ADC clock to 1 mHz. + * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, + * following every chip reset before initiating normal ADC operation. + * + * param base ADC peripheral base address. + * param frequency The ststem clock frequency to ADC. + * retval true Calibration succeed. + * retval false Calibration failed. + */ +bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency) +{ + uint32_t tmp32; + /* Store the current contents of the ADC CTRL register. */ + tmp32 = base->CTRL; + + /* Start ADC self-calibration. */ + base->CTRL |= ADC_CTRL_CALMODE_MASK; + + /* Divide the system clock to yield an ADC clock of about 1 mHz. */ + base->CTRL &= ~ADC_CTRL_CLKDIV_MASK; + base->CTRL |= ADC_CTRL_CLKDIV((frequency / 1000000U) - 1U); + + /* Clear the LPWR bit. */ + base->CTRL &= ~ADC_CTRL_LPWRMODE_MASK; + /* Delay for 120 uSec @ 1 mHz ADC clock */ + SDK_DelayAtLeastUs(120U); + + /* Check the completion of calibration. */ + if (ADC_CTRL_CALMODE_MASK == (base->CTRL & ADC_CTRL_CALMODE_MASK)) + { + /* Restore the contents of the ADC CTRL register. */ + base->CTRL = tmp32; + return false; /* Calibration timeout. */ + } + /* Restore the contents of the ADC CTRL register. */ + base->CTRL = tmp32; + + return true; +} +#endif /* FSL_FEATURE_ADC_HAS_CALIB_REG */ +#endif /* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC*/ + +/*! + * brief Configure the conversion sequence A. + * + * param base ADC peripheral base address. + * param config Pointer to configuration structure, see to #adc_conv_seq_config_t. + */ void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config) { assert(config != NULL); @@ -208,6 +346,12 @@ void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config) base->SEQ_CTRL[0] = tmp32; } +/*! + * brief Configure the conversion sequence B. + * + * param base ADC peripheral base address. + * param config Pointer to configuration structure, see to #adc_conv_seq_config_t. + */ void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config) { assert(config != NULL); @@ -252,6 +396,14 @@ void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config) base->SEQ_CTRL[1] = tmp32; } +/*! + * brief Get the global ADC conversion infomation of sequence A. + * + * param base ADC peripheral base address. + * param info Pointer to information structure, see to #adc_result_info_t; + * retval true The conversion result is ready. + * retval false The conversion result is not ready yet. + */ bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) { assert(info != NULL); @@ -269,11 +421,19 @@ bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *in info->thresholdCorssingStatus = (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT); info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT; - info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); + info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); return true; } +/*! + * brief Get the global ADC conversion infomation of sequence B. + * + * param base ADC peripheral base address. + * param info Pointer to information structure, see to #adc_result_info_t; + * retval true The conversion result is ready. + * retval false The conversion result is not ready yet. + */ bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) { assert(info != NULL); @@ -291,11 +451,20 @@ bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *in info->thresholdCorssingStatus = (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT); info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT; - info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); + info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); return true; } +/*! + * brief Get the channel's ADC conversion completed under each conversion sequence. + * + * param base ADC peripheral base address. + * param channel The indicated channel number. + * param info Pointer to information structure, see to #adc_result_info_t; + * retval true The conversion result is ready. + * retval false The conversion result is not ready yet. + */ bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info) { assert(info != NULL); @@ -309,12 +478,51 @@ bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result } info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT; +#if (defined(FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT) && FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT) + switch ((base->CTRL & ADC_CTRL_RESOL_MASK) >> ADC_CTRL_RESOL_SHIFT) + { + case kADC_Resolution10bit: + info->result >>= kADC_Resolution10bitInfoResultShift; + break; + case kADC_Resolution8bit: + info->result >>= kADC_Resolution8bitInfoResultShift; + break; + case kADC_Resolution6bit: + info->result >>= kADC_Resolution6bitInfoResultShift; + break; + default: + break; + } +#endif info->thresholdCompareStatus = (adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT); info->thresholdCorssingStatus = (adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT); info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT; - info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK); + info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK); return true; } +#if defined(FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP) && (FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP) +void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) +{ + if (enable) + { + SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE_MASK; + ASYNC_SYSCON->TEMPSENSORCTRL = kADC_NoOffsetAdded; + ASYNC_SYSCON->TEMPSENSORCTRL |= ASYNC_SYSCON_TEMPSENSORCTRL_ENABLE_MASK; + base->GPADC_CTRL0 |= (kADC_ADCInUnityGainMode | kADC_Impedance87kOhm); + } + else + { + /* if the temperature sensor is not turned on then ASYNCAPBCTRL is likely to be zero + * and accessing the registers will cause a memory access error. Test for this */ + if (SYSCON->ASYNCAPBCTRL == SYSCON_ASYNCAPBCTRL_ENABLE_MASK) + { + ASYNC_SYSCON->TEMPSENSORCTRL = 0x0; + base->GPADC_CTRL0 &= ~(kADC_ADCInUnityGainMode | kADC_Impedance87kOhm); + base->GPADC_CTRL0 |= kADC_Impedance55kOhm; + } + } +} +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_adc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_adc.h index f5a416e9d5..e1679580bd 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_adc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_adc.h @@ -1,35 +1,9 @@ /* - * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2019 NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef __FSL_ADC_H__ @@ -50,25 +24,26 @@ /*! @name Driver version */ /*@{*/ -/*! @brief ADC driver version 2.1.0. */ -#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @brief ADC driver version 2.3.1. */ +#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*@}*/ /*! * @brief Flags */ + enum _adc_status_flags { - kADC_ThresholdCompareFlagOnChn0 = 1U << 0U, /*!< Threshold comparison event on Channel 0. */ - kADC_ThresholdCompareFlagOnChn1 = 1U << 1U, /*!< Threshold comparison event on Channel 1. */ - kADC_ThresholdCompareFlagOnChn2 = 1U << 2U, /*!< Threshold comparison event on Channel 2. */ - kADC_ThresholdCompareFlagOnChn3 = 1U << 3U, /*!< Threshold comparison event on Channel 3. */ - kADC_ThresholdCompareFlagOnChn4 = 1U << 4U, /*!< Threshold comparison event on Channel 4. */ - kADC_ThresholdCompareFlagOnChn5 = 1U << 5U, /*!< Threshold comparison event on Channel 5. */ - kADC_ThresholdCompareFlagOnChn6 = 1U << 6U, /*!< Threshold comparison event on Channel 6. */ - kADC_ThresholdCompareFlagOnChn7 = 1U << 7U, /*!< Threshold comparison event on Channel 7. */ - kADC_ThresholdCompareFlagOnChn8 = 1U << 8U, /*!< Threshold comparison event on Channel 8. */ - kADC_ThresholdCompareFlagOnChn9 = 1U << 9U, /*!< Threshold comparison event on Channel 9. */ + kADC_ThresholdCompareFlagOnChn0 = 1U << 0U, /*!< Threshold comparison event on Channel 0. */ + kADC_ThresholdCompareFlagOnChn1 = 1U << 1U, /*!< Threshold comparison event on Channel 1. */ + kADC_ThresholdCompareFlagOnChn2 = 1U << 2U, /*!< Threshold comparison event on Channel 2. */ + kADC_ThresholdCompareFlagOnChn3 = 1U << 3U, /*!< Threshold comparison event on Channel 3. */ + kADC_ThresholdCompareFlagOnChn4 = 1U << 4U, /*!< Threshold comparison event on Channel 4. */ + kADC_ThresholdCompareFlagOnChn5 = 1U << 5U, /*!< Threshold comparison event on Channel 5. */ + kADC_ThresholdCompareFlagOnChn6 = 1U << 6U, /*!< Threshold comparison event on Channel 6. */ + kADC_ThresholdCompareFlagOnChn7 = 1U << 7U, /*!< Threshold comparison event on Channel 7. */ + kADC_ThresholdCompareFlagOnChn8 = 1U << 8U, /*!< Threshold comparison event on Channel 8. */ + kADC_ThresholdCompareFlagOnChn9 = 1U << 9U, /*!< Threshold comparison event on Channel 9. */ kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */ kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */ kADC_OverrunFlagForChn0 = @@ -97,10 +72,10 @@ enum _adc_status_flags 1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */ kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */ kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */ - kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */ - kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */ - kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */ - kADC_OverrunInterruptFlag = 1U << 31U, /*!< Overrun interrupt flag. */ + kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */ + kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */ + kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */ + kADC_OverrunInterruptFlag = (int)(1U << 31U), /*!< Overrun interrupt flag. */ }; /*! @@ -114,10 +89,11 @@ enum _adc_interrupt_enable kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual conversion in sequence B, or entire sequence. */ kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of - the channel data registers will cause an overrun - interrupt/DMA trigger. */ + the channel data registers will cause an overrun + interrupt/DMA trigger. */ }; +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE /*! * @brief Define selection of clock mode. */ @@ -127,17 +103,44 @@ typedef enum _adc_clock_mode 0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */ kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */ } adc_clock_mode_t; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ +#if defined(FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT) && (FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT) /*! * @brief Define selection of resolution. */ typedef enum _adc_resolution { - kADC_Resolution6bit = 0U, /*!< 6-bit resolution. */ - kADC_Resolution8bit = 1U, /*!< 8-bit resolution. */ + kADC_Resolution6bit = 3U, + /*!< 6-bit resolution. */ /* This is a HW issue that the ADC resolution enum configure not align with HW implement, + ES2 chip already fixed the issue, Currently, update ADC enum define as a workaround */ + kADC_Resolution8bit = 2U, /*!< 8-bit resolution. */ + kADC_Resolution10bit = 1U, /*!< 10-bit resolution. */ + kADC_Resolution12bit = 0U, /*!< 12-bit resolution. */ +} adc_resolution_t; +#elif defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL +/*! + * @brief Define selection of resolution. + */ +typedef enum _adc_resolution +{ + kADC_Resolution6bit = 0U, /*!< 6-bit resolution. */ + kADC_Resolution8bit = 1U, /*!< 8-bit resolution. */ kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */ kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */ } adc_resolution_t; +#endif + +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG +/*! + * @brief Definfe range of the analog supply voltage VDDA. + */ +typedef enum _adc_voltage_range +{ + kADC_HighVoltageRange = 0U, /* High voltage. VDD = 2.7 V to 3.6 V. */ + kADC_LowVoltageRange = 1U, /* Low voltage. VDD = 2.4 V to 2.7 V. */ +} adc_vdda_range_t; +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ /*! * @brief Define selection of polarity of selected input trigger for conversion sequence. @@ -153,7 +156,7 @@ typedef enum _adc_trigger_polarity */ typedef enum _adc_priority { - kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */ + kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */ kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when it is started. */ } adc_priority_t; @@ -173,7 +176,7 @@ typedef enum _adc_seq_interrupt_mode */ typedef enum _adc_threshold_compare_status { - kADC_ThresholdCompareInRange = 0U, /*!< LOW threshold <= conversion value <= HIGH threshold. */ + kADC_ThresholdCompareInRange = 0U, /*!< LOW threshold <= conversion value <= HIGH threshold. */ kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */ kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */ } adc_threshold_compare_status_t; @@ -203,27 +206,84 @@ typedef enum _adc_threshold_crossing_status */ typedef enum _adc_threshold_interrupt_mode { - kADC_ThresholdInterruptDisabled = 0U, /*!< Threshold comparison interrupt is disabled. */ - kADC_ThresholdInterruptOnOutside = 1U, /*!< Threshold comparison interrupt is enabled on outside threshold. */ + kADC_ThresholdInterruptDisabled = 0U, /*!< Threshold comparison interrupt is disabled. */ + kADC_ThresholdInterruptOnOutside = 1U, /*!< Threshold comparison interrupt is enabled on outside threshold. */ kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */ } adc_threshold_interrupt_mode_t; +/*! + * @brief Define the info result mode of different resolution. + */ +typedef enum _adc_inforesultshift +{ + kADC_Resolution12bitInfoResultShift = 0U, /*!< Info result shift of Resolution12bit. */ + kADC_Resolution10bitInfoResultShift = 2U, /*!< Info result shift of Resolution10bit. */ + kADC_Resolution8bitInfoResultShift = 4U, /*!< Info result shift of Resolution8bit. */ + kADC_Resolution6bitInfoResultShift = 6U, /*!< Info result shift of Resolution6bit. */ +} adc_inforesult_t; + +/*! + * @brief Define common modes for Temerature sensor. + */ +typedef enum _adc_tempsensor_common_mode +{ + kADC_HighNegativeOffsetAdded = 0x0U, /*!< Temerature sensor common mode: high negative offset added. */ + kADC_IntermediateNegativeOffsetAdded = + 0x4U, /*!< Temerature sensor common mode: intermediate negative offset added. */ + kADC_NoOffsetAdded = 0x8U, /*!< Temerature sensor common mode: no offset added. */ + kADC_LowPositiveOffsetAdded = 0xcU, /*!< Temerature sensor common mode: low positive offset added. */ +} adc_tempsensor_common_mode_t; + +/*! + * @brief Define source impedance modes for GPADC control. + */ +typedef enum _adc_second_control +{ + kADC_Impedance621Ohm = 0x1U << 9U, /*!< Extand ADC sampling time according to source impedance 1: 0.621 kOhm. */ + kADC_Impedance55kOhm = + 0x14U << 9U, /*!< Extand ADC sampling time according to source impedance 20 (default): 55 kOhm. */ + kADC_Impedance87kOhm = 0x1fU << 9U, /*!< Extand ADC sampling time according to source impedance 31: 87 kOhm. */ + + kADC_NormalFunctionalMode = 0x0U << 14U, /*!< TEST mode: Normal functional mode. */ + kADC_MultiplexeTestMode = 0x1U << 14U, /*!< TEST mode: Multiplexer test mode. */ + kADC_ADCInUnityGainMode = 0x2U << 14U, /*!< TEST mode: ADC in unity gain mode. */ +} adc_second_control_t; + /*! * @brief Define structure for configuring the block. */ typedef struct _adc_config { - adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */ - uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode" - field. The divider would be plused by 1 based on the value in this field. The - available range is in 8 bits. */ - adc_resolution_t resolution; /*!< Select the conversion bits. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ + uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode" + field. The divider would be plused by 1 based on the value in this field. The + available range is in 8 bits. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL + adc_resolution_t resolution; /*!< Select the conversion bits. */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is powered-up. Re-calibration may be warranted periodically - especially if operating conditions have changed. To enable this option would avoid the need to calibrate if offset error is not a concern in the application. */ - uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then, - to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP + uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then, + to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + bool enableLowPowerMode; /*!< If disable low-power mode, ADC remains activated even when no conversions are + requested. + If enable low-power mode, The ADC is automatically powered-down when no conversions are + taking place. */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + adc_vdda_range_t + voltageRange; /*!< Configure the ADC for the appropriate operating range of the analog supply voltage VDDA. + Failure to set the area correctly causes the ADC to return incorrect conversion results. */ +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ } adc_config_t; /*! @@ -232,17 +292,17 @@ typedef struct _adc_config typedef struct _adc_conv_seq_config { uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this - sequence is launched. The masked channels would be involved in current conversion - sequence, beginning with the lowest-order. The available range is in 12-bit. */ + sequence is launched. The masked channels would be involved in current conversion + sequence, beginning with the lowest-order. The available range is in 12-bit. */ uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this - conversion sequence to be initiated. The available range is 6-bit.*/ + conversion sequence to be initiated. The available range is 6-bit.*/ adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */ bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization - flip-flop stages and therefore shorten the time between the trigger input signal and the - start of a conversion. */ + flip-flop stages and therefore shorten the time between the trigger input signal and the + start of a conversion. */ bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next - channel in the sequence instead of the default response of launching an entire sequence - of conversions. */ + channel in the sequence instead of the default response of launching an entire sequence + of conversions. */ adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */ } adc_conv_seq_config_t; @@ -302,6 +362,8 @@ void ADC_Deinit(ADC_Type *base); */ void ADC_GetDefaultConfig(adc_config_t *config); +#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) +#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) && FSL_FEATURE_ADC_HAS_CALIB_REG /*! * @brief Do the self hardware calibration. * @@ -310,6 +372,20 @@ void ADC_GetDefaultConfig(adc_config_t *config); * @retval false Calibration failed. */ bool ADC_DoSelfCalibration(ADC_Type *base); +#else +/*! + * @brief Do the self calibration. To calibrate the ADC, set the ADC clock to 500 kHz. + * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, + * following every chip reset before initiating normal ADC operation. + * + * @param base ADC peripheral base address. + * @param frequency The ststem clock frequency to ADC. + * @retval true Calibration succeed. + * @retval false Calibration failed. + */ +bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency); +#endif /* FSL_FEATURE_ADC_HAS_CALIB_REG */ +#endif /* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC */ #if !(defined(FSL_FEATURE_ADC_HAS_NO_INSEL) && FSL_FEATURE_ADC_HAS_NO_INSEL) /*! @@ -321,6 +397,9 @@ bool ADC_DoSelfCalibration(ADC_Type *base); * @param base ADC peripheral base address. * @param enable Switcher to enable the feature or not. */ +#if defined(FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP) && (FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP) +void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable); +#else static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) { if (enable) @@ -332,8 +411,9 @@ static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0); } } +#endif /* FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP. */ #endif /* FSL_FEATURE_ADC_HAS_NO_INSEL. */ -/* @} */ + /* @} */ /*! * @name Control conversion sequence A. @@ -547,7 +627,7 @@ bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result */ static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue) { - base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue); + base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue); base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue); } @@ -560,7 +640,7 @@ static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint */ static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue) { - base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue); + base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue); base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue); } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_clock.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_clock.c index de2e2971da..0e5be34153 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_clock.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_clock.c @@ -1,44 +1,21 @@ /* - * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP + * Copyright 2016 - 2019 , NXP * All rights reserved. * * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ -#include "fsl_common.h" #include "fsl_clock.h" #include "fsl_power.h" /******************************************************************************* * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif #define NVALMAX (0x100U) #define PVALMAX (0x20U) #define MVALMAX (0x8000U) @@ -50,22 +27,16 @@ #define PLL_MAX_N_DIV 0x100U #define USB_PLL_MAX_N_DIV 0x100U -#define INDEX_SECTOR_TRIM48 ((uint32_t *)0x01000448U) -#define INDEX_SECTOR_TRIM96 ((uint32_t *)0x0100044CU) -/*-------------------------------------------------------------------------- -!!! If required these #defines can be moved to chip library file -----------------------------------------------------------------------------*/ - -#define PLL_MDEC_VAL_P (0U) /*!< MDEC is in bits 16 downto 0 */ -#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P) /*!< NDEC is in bits 9 downto 0 */ -#define PLL_NDEC_VAL_P (0U) /*!< NDEC is in bits 9:0 */ +#define PLL_MDEC_VAL_P (0U) /*!< MDEC is in bits 16 downto 0 */ +#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P) /*!< NDEC is in bits 9 downto 0 */ +#define PLL_NDEC_VAL_P (0U) /*!< NDEC is in bits 9:0 */ #define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ #define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) #define PLL_MIN_CCO_FREQ_MHZ (275000000U) #define PLL_MAX_CCO_FREQ_MHZ (550000000U) -#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */ +#define PLL_LOWER_IN_LIMIT (4000U) /*!< Minimum PLL input rate */ #define PLL_MIN_IN_SSMODE (2000000U) #define PLL_MAX_IN_SSMODE (4000000U) @@ -78,18 +49,15 @@ /*!< USB PLL CCO MAX AND MIN FREQ */ #define USB_PLL_MIN_CCO_FREQ_MHZ (156000000U) #define USB_PLL_MAX_CCO_FREQ_MHZ (320000000U) -#define USB_PLL_LOWER_IN_LIMIT (1000000U) /*!< Minimum PLL input rate */ +#define USB_PLL_LOWER_IN_LIMIT (1000000U) /*!< Minimum PLL input rate */ -#define USB_PLL_MSEL_VAL_P (0U) /*!< MSEL is in bits 7 downto 0 */ +#define USB_PLL_MSEL_VAL_P (0U) /*!< MSEL is in bits 7 downto 0 */ #define USB_PLL_MSEL_VAL_M (0xFFU) -#define USB_PLL_PSEL_VAL_P (8U) /*!< PDEC is in bits 9:8 */ +#define USB_PLL_PSEL_VAL_P (8U) /*!< PDEC is in bits 9:8 */ #define USB_PLL_PSEL_VAL_M (0x3U) -#define USB_PLL_NSEL_VAL_P (10U) /*!< NDEC is in bits 11:10 */ +#define USB_PLL_NSEL_VAL_P (10U) /*!< NDEC is in bits 11:10 */ #define USB_PLL_NSEL_VAL_M (0x3U) -/*!< SWITCH USB POSTDIVIDER FOR REGITSER WRITING */ -#define SWITCH_USB_PSEL(x) ((x==0x0U) ? 0x1U : (x==0x1U) ? 0x02U : (x==0x2U) ? 0x4U : (x==3U) ? 0x8U : 0U) - /*!< SYS PLL NDEC reg */ #define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) /*!< SYS PLL PDEC reg */ @@ -98,11 +66,11 @@ #define PLL_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_MDEC_VAL_P) & PLL_MDEC_VAL_M) /*!< SYS PLL NSEL reg */ -#define USB_PLL_NSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_NSEL_VAL_M) << USB_PLL_NSEL_VAL_P) +#define USB_PLL_NSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_NSEL_VAL_M) << USB_PLL_NSEL_VAL_P) /*!< SYS PLL PSEL reg */ -#define USB_PLL_PSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_PSEL_VAL_M) << USB_PLL_PSEL_VAL_P) +#define USB_PLL_PSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_PSEL_VAL_M) << USB_PLL_PSEL_VAL_P) /*!< SYS PLL MSEL reg */ -#define USB_PLL_MSEL_VAL_SET(value) (((unsigned long)(value) & USB_PLL_MSEL_VAL_M) << USB_PLL_MSEL_VAL_P) +#define USB_PLL_MSEL_VAL_SET(value) (((unsigned long)(value)&USB_PLL_MSEL_VAL_M) << USB_PLL_MSEL_VAL_P) /*!< FRAC control */ #define AUDIO_PLL_FRACT_MD_P (0U) @@ -119,13 +87,12 @@ static uint32_t s_Pll_Freq; static uint32_t s_Usb_Pll_Freq; static uint32_t s_Audio_Pll_Freq; - /** External clock rate on the CLKIN pin in Hz. If not used, set this to 0. Otherwise, set it to the exact rate in Hz this pin is being driven at. */ -const uint32_t g_I2S_Mclk_Freq = 0U; -const uint32_t g_Ext_Clk_Freq = 12000000U; -const uint32_t g_Lcd_Clk_In_Freq = 0U; +static const uint32_t s_I2S_Mclk_Freq = 0U; +static const uint32_t s_Ext_Clk_Freq = 12000000U; +static const uint32_t s_Lcd_Clk_In_Freq = 0U; /******************************************************************************* * Variables @@ -156,60 +123,124 @@ static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg); static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg); /* Convert the binary to fractional part */ static double Binary2Fractional(uint32_t binaryPart); -/* Calculate the powerTimes' power of 2 */ -static uint32_t power2Cal(uint32_t powerTimes); /* Get the greatest common divisor */ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n); /* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPllConfig( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup); +static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup); /* Update local PLL rate variable */ static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup); static void CLOCK_GetAudioPLLOutFromSetupUpdate(pll_setup_t *pSetup); -static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46, - 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; +static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, + 42, 44, 45, 46, 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61}; /******************************************************************************* * Code ******************************************************************************/ /* Clock Selection for IP */ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ void CLOCK_AttachClk(clock_attach_id_t connection) { - bool final_descriptor = false; uint8_t mux; - uint8_t pos; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; uint32_t i; volatile uint32_t *pClkSel; pClkSel = &(SYSCON->MAINCLKSELA); - for (i = 0U; (i <= 2U) && (!final_descriptor); i++) + if (kNONE_to_NONE != connection) { - connection = (clock_attach_id_t)(connection >> (i * 12U)); /*!< pick up next descriptor */ - mux = (uint8_t)connection; - if (connection) + for (i = 0U; i < 2U; i++) { - pos = ((connection & 0xf00U) >> 8U) - 1U; - if (mux == CM_ASYNCAPB) + if (tmp32 == 0U) { - SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1); - ASYNC_SYSCON->ASYNCAPBCLKSELA = pos; + break; } - else + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item) { - pClkSel[mux] = pos; + mux = GET_ID_ITEM_MUX(item); + sel = GET_ID_ITEM_SEL(item); + if (mux == CM_ASYNCAPB) + { + SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1); + ASYNC_SYSCON->ASYNCAPBCLKSELA = sel; + } + else + { + pClkSel[mux] = sel; + } } - } - else - { - final_descriptor = true; + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ } } } +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint8_t mux; + uint8_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->MAINCLKSELA); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = GET_ID_ITEM_MUX(tmp32); + if (tmp32) + { + if (mux == CM_ASYNCAPB) + { + actualSel = ASYNC_SYSCON->ASYNCAPBCLKSELA; + } + else + { + actualSel = pClkSel[mux]; + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + /* Set IP Clock Divider */ +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * param reset : Whether to reset the divider counter. + * return Nothing + */ void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) { volatile uint32_t *pClkDiv; @@ -230,6 +261,13 @@ void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool } /* Set FRO Clocking */ +/** + * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) + * return returns success or fail status. + */ status_t CLOCK_SetupFROClocking(uint32_t iFreq) { uint32_t usb_adj; @@ -241,19 +279,20 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq) POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /* back up the value of whether USB adj is selected, in which case we will have a value of 1 else 0 */ usb_adj = ((SYSCON->FROCTRL) & SYSCON_FROCTRL_USBCLKADJ_MASK) >> SYSCON_FROCTRL_USBCLKADJ_SHIFT; + if (iFreq > 12000000U) { + /* Call ROM API to set FRO */ + set_fro_frequency(iFreq); if (iFreq == 96000000U) { - SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM96) | - SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | - SYSCON_FROCTRL_HSPDCLK(1); + SYSCON->FROCTRL |= (SYSCON_FROCTRL_SEL(1) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | + SYSCON_FROCTRL_HSPDCLK(1)); } else { - SYSCON->FROCTRL = ((SYSCON_FROCTRL_TRIM_MASK | SYSCON_FROCTRL_FREQTRIM_MASK) & *INDEX_SECTOR_TRIM48) | - SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | - SYSCON_FROCTRL_HSPDCLK(1); + SYSCON->FROCTRL |= (SYSCON_FROCTRL_SEL(0) | SYSCON_FROCTRL_WRTRIM(1) | SYSCON_FROCTRL_USBCLKADJ(usb_adj) | + SYSCON_FROCTRL_HSPDCLK(1)); } } else @@ -265,115 +304,336 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq) } /* Get CLOCK OUT Clk */ +/*! brief Return Frequency of ClockOut + * return Frequency of ClockOut + */ uint32_t CLOCK_GetClockOutClkFreq(void) { - return (SYSCON->CLKOUTSELA == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->CLKOUTSELA == 1U) ? CLOCK_GetExtClkFreq(): - (SYSCON->CLKOUTSELA == 2U) ? CLOCK_GetWdtOscFreq(): - (SYSCON->CLKOUTSELA == 3U) ? CLOCK_GetFroHfFreq(): - (SYSCON->CLKOUTSELA == 4U) ? CLOCK_GetPllOutFreq(): - (SYSCON->CLKOUTSELA == 5U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->CLKOUTSELA == 6U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->CLKOUTSELA == 7U) ? CLOCK_GetOsc32KFreq():0U; + uint32_t freq = 0U; + + switch (SYSCON->CLKOUTSELA) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + + case 1U: + freq = CLOCK_GetExtClkFreq(); + break; + + case 2U: + freq = CLOCK_GetWdtOscFreq(); + break; + + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + case 4U: + freq = CLOCK_GetPllOutFreq(); + break; + + case 5U: + freq = CLOCK_GetUsbPllOutFreq(); + break; + + case 6U: + freq = CLOCK_GetAudioPllOutFreq(); + break; + + case 7U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + break; + } + return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); } /* Get SPIFI Clk */ +/*! brief Return Frequency of Spifi Clock + * return Frequency of Spifi. + */ uint32_t CLOCK_GetSpifiClkFreq(void) { - return (SYSCON->SPIFICLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->SPIFICLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->SPIFICLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->SPIFICLKSEL == 3U) ? CLOCK_GetFroHfFreq(): - (SYSCON->SPIFICLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->SPIFICLKSEL == 7U) ? 0U:0U; + uint32_t freq = 0U; + + switch (SYSCON->SPIFICLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetUsbPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetAudioPllOutFreq(); + break; + case 7U: + freq = 0U; + break; + default: + break; + } + + return freq / ((SYSCON->SPIFICLKDIV & 0xffU) + 1U); } /* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc Clock. + */ uint32_t CLOCK_GetAdcClkFreq(void) { - return (SYSCON->ADCCLKSEL == 0U) ? CLOCK_GetFroHfFreq(): - (SYSCON->ADCCLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->ADCCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->ADCCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->ADCCLKSEL == 7U) ? 0U:0U; + uint32_t freq = 0U; + + switch (SYSCON->ADCCLKSEL) + { + case 0U: + freq = CLOCK_GetFroHfFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetUsbPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetAudioPllOutFreq(); + break; + case 7U: + freq = 0U; + break; + default: + break; + } + + return freq / ((SYSCON->ADCCLKDIV & 0xffU) + 1U); } /* Get USB0 Clk */ +/*! brief Return Frequency of Usb0 Clock + * return Frequency of Usb0 Clock. + */ uint32_t CLOCK_GetUsb0ClkFreq(void) { - return (SYSCON->USB0CLKSEL == 0U) ? CLOCK_GetFroHfFreq(): - (SYSCON->USB0CLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->USB0CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->USB0CLKSEL == 7U) ? 0U:0U; + uint32_t freq = 0U; + + switch (SYSCON->USB0CLKSEL) + { + case 0U: + freq = CLOCK_GetFroHfFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetUsbPllOutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq / ((SYSCON->USB0CLKDIV & 0xffU) + 1U); } /* Get USB1 Clk */ +/*! brief Return Frequency of Usb1 Clock + * return Frequency of Usb1 Clock. + */ uint32_t CLOCK_GetUsb1ClkFreq(void) { + uint32_t freq = 0U; - return (SYSCON->USB1CLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->USB1CLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->USB1CLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->USB1CLKSEL == 7U) ? 0U:0U; + switch (SYSCON->USB1CLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetUsbPllOutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq / ((SYSCON->USB1CLKDIV & 0xffU) + 1U); } /* Get MCLK Clk */ +/*! brief Return Frequency of MClk Clock + * return Frequency of MClk Clock. + */ uint32_t CLOCK_GetMclkClkFreq(void) { - return (SYSCON->MCLKCLKSEL == 0U) ? CLOCK_GetFroHfFreq() / ((SYSCON->FROHFCLKDIV & 0xffu) + 1U): - (SYSCON->MCLKCLKSEL == 1U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->MCLKCLKSEL == 7U) ? 0U:0U; + uint32_t freq = 0U; + + switch (SYSCON->MCLKCLKSEL) + { + case 0U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFCLKDIV & 0xffu) + 1U); + break; + case 1U: + freq = CLOCK_GetAudioPllOutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq / ((SYSCON->MCLKDIV & 0xffU) + 1U); } /* Get SCTIMER Clk */ +/*! brief Return Frequency of SCTimer Clock + * return Frequency of SCTimer Clock. + */ uint32_t CLOCK_GetSctClkFreq(void) { - return (SYSCON->SCTCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->SCTCLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->SCTCLKSEL == 2U) ? CLOCK_GetFroHfFreq(): - (SYSCON->SCTCLKSEL == 3U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->SCTCLKSEL == 7U) ? 0U:0U; + uint32_t freq = 0U; + + switch (SYSCON->SCTCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = CLOCK_GetAudioPllOutFreq(); + break; + case 7U: + freq = 0U; + break; + + default: + break; + } + + return freq / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); } /* Get SDIO Clk */ +/*! brief Return Frequency of SDIO Clock + * return Frequency of SDIO Clock. + */ uint32_t CLOCK_GetSdioClkFreq(void) { - return (SYSCON->SDIOCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->SDIOCLKSEL == 1U) ? CLOCK_GetPllOutFreq(): - (SYSCON->SDIOCLKSEL == 2U) ? CLOCK_GetUsbPllOutFreq(): - (SYSCON->SDIOCLKSEL == 3U) ? CLOCK_GetFroHfFreq(): - (SYSCON->SDIOCLKSEL == 4U) ? CLOCK_GetAudioPllOutFreq(): - (SYSCON->SDIOCLKSEL == 7U) ? 0U:0U; + uint32_t freq = 0U; + + switch (SYSCON->SDIOCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetUsbPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + case 4U: + freq = CLOCK_GetAudioPllOutFreq(); + break; + case 7U: + freq = 0U; + break; + default: + break; + } + + return freq / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); } /* Get LCD Clk */ +/*! brief Return Frequency of LCD Clock + * return Frequency of LCD Clock. + */ uint32_t CLOCK_GetLcdClkFreq(void) { - return (SYSCON->LCDCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq(): - (SYSCON->LCDCLKSEL == 1U) ? CLOCK_GetLcdClkIn(): - (SYSCON->LCDCLKSEL == 2U) ? CLOCK_GetFroHfFreq(): - (SYSCON->LCDCLKSEL == 3U) ? 0U:0U; + uint32_t freq = 0U; + + switch (SYSCON->LCDCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetLcdClkIn(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 3U: + freq = 0U; + break; + + default: + break; + } + + return freq / ((SYSCON->LCDCLKDIV & 0xffU) + 1U); } /* Get LCD CLK IN Clk */ +/*! brief Return Frequency of LCD CLKIN Clock + * return Frequency of LCD CLKIN Clock. + */ uint32_t CLOCK_GetLcdClkIn(void) { - return g_Lcd_Clk_In_Freq; + return s_Lcd_Clk_In_Freq; } /* Get FRO 12M Clk */ +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ uint32_t CLOCK_GetFro12MFreq(void) { return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U; } /* Get EXT OSC Clk */ +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ uint32_t CLOCK_GetExtClkFreq(void) { - return g_Ext_Clk_Freq; + return s_Ext_Clk_Freq; } /* Get WATCH DOG Clk */ +/*! brief Return Frequency of Watchdog Oscillator + * return Frequency of Watchdog Oscillator + */ uint32_t CLOCK_GetWdtOscFreq(void) { uint8_t freq_sel, div_sel; @@ -384,61 +644,128 @@ uint32_t CLOCK_GetWdtOscFreq(void) else { div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1; - freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; - return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel); + freq_sel = + wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)]; + return ((uint32_t)freq_sel * 50000U) / ((uint32_t)div_sel); } } /* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ uint32_t CLOCK_GetFroHfFreq(void) { - return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0 : - !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? 0 : - (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? 96000000U : 48000000U; + if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) || (!(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK))) + { + return 0U; + } + + if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) + { + return 96000000U; + } + else + { + return 48000000U; + } } /* Get SYSTEM PLL Clk */ +/*! brief Return Frequency of PLL + * return Frequency of PLL + */ uint32_t CLOCK_GetPllOutFreq(void) { return s_Pll_Freq; } /* Get AUDIO PLL Clk */ +/*! brief Return Frequency of AUDIO PLL + * return Frequency of PLL + */ uint32_t CLOCK_GetAudioPllOutFreq(void) { return s_Audio_Pll_Freq; } /* Get USB PLL Clk */ +/*! brief Return Frequency of USB PLL + * return Frequency of PLL + */ uint32_t CLOCK_GetUsbPllOutFreq(void) { return s_Usb_Pll_Freq; } /* Get RTC OSC Clk */ +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ uint32_t CLOCK_GetOsc32KFreq(void) { - return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */ + return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */ } /* Get MAIN Clk */ +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ uint32_t CLOCK_GetCoreSysClkFreq(void) { - return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ? CLOCK_GetFro12MFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ? CLOCK_GetExtClkFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ? CLOCK_GetWdtOscFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ? CLOCK_GetFroHfFreq() : - (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() : - (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U; + uint32_t freq = 0U; + + switch (SYSCON->MAINCLKSELB) + { + case 0U: + if (SYSCON->MAINCLKSELA == 0U) + { + freq = CLOCK_GetFro12MFreq(); + } + else if (SYSCON->MAINCLKSELA == 1U) + { + freq = CLOCK_GetExtClkFreq(); + } + else if (SYSCON->MAINCLKSELA == 2U) + { + freq = CLOCK_GetWdtOscFreq(); + } + else if (SYSCON->MAINCLKSELA == 3U) + { + freq = CLOCK_GetFroHfFreq(); + } + else + { + } + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + + case 3U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + break; + } + + return freq; } /* Get I2S MCLK Clk */ +/*! brief Return Frequency of I2S MCLK Clock + * return Frequency of I2S MCLK Clock + */ uint32_t CLOCK_GetI2SMClkFreq(void) { - return g_I2S_Mclk_Freq; + return s_I2S_Mclk_Freq; } /* Get ASYNC APB Clk */ +/*! brief Return Frequency of Asynchronous APB Clock + * return Frequency of Asynchronous APB Clock Clock + */ uint32_t CLOCK_GetAsyncApbClkFreq(void) { async_clock_src_t clkSrc; @@ -462,28 +789,161 @@ uint32_t CLOCK_GetAsyncApbClkFreq(void) return clkRate; } +/* Get MCAN Clk */ +/*! brief Return Frequency of MCAN Clock + * param MCanSel : 0U: MCAN0; 1U: MCAN1 + * return Frequency of MCAN Clock + */ +uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel) +{ + uint32_t freq = 0U; + switch (MCanSel) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN0CLKDIV & 0xffU) + 1U); + break; + case 1U: + freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN1CLKDIV & 0xffU) + 1U); + break; + + default: + break; + } + + return freq; +} + /* Get FLEXCOMM Clk */ +/*! brief Return Frequency of Flexcomm functional Clock + * return Frequency of Flexcomm functional Clock + */ uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) { - return (SYSCON->FCLKSEL[id] == 0U) ? CLOCK_GetFro12MFreq() : - (SYSCON->FCLKSEL[id] == 1U) ? CLOCK_GetFroHfFreq() : - (SYSCON->FCLKSEL[id] == 2U) ? CLOCK_GetPllOutFreq() : - (SYSCON->FCLKSEL[id] == 3U) ? CLOCK_GetI2SMClkFreq() : - (SYSCON->FCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U; + uint32_t freq = 0U; + + switch (SYSCON->FCLKSEL[id]) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq() / ((SYSCON->FROHFCLKDIV & SYSCON_FROHFCLKDIV_DIV_MASK) + 1U); + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 4U: + freq = CLOCK_GetFrgClkFreq(); + break; + + default: + break; + } + + return freq; } /* Get FRG Clk */ +/*! brief Return Frequency of FRG input clock + * return Frequency value + */ uint32_t CLOCK_GetFRGInputClock(void) { - return (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : - (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() : - (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : - (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U; + uint32_t freq = 0U; + + switch (SYSCON->FRGCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + default: + break; + } + + return freq; +} + +/* Get FRG Clk */ +/*! brief Return Frequency of frg + * return Frequency of FRG + */ +uint32_t CLOCK_GetFrgClkFreq(void) +{ + uint32_t freq = 0U; + + if ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) + { + freq = ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) / + ((SYSCON_FRGCTRL_DIV_MASK + 1) + + ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)); + } + else + { + freq = 0U; + } + + return freq; +} + +/* Get DMIC Clk */ +/*! brief Return Frequency of dmic + * return Frequency of DMIC + */ +uint32_t CLOCK_GetDmicClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->DMICCLKSEL) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 4U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 5U: + freq = CLOCK_GetWdtOscFreq(); + break; + default: + break; + } + + return freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U); } /* Set FRG Clk */ +/** + * brief Set the frg output frequency. + * param freq : output frequency + * return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ uint32_t CLOCK_SetFRGClock(uint32_t freq) { + assert(freq); + uint32_t input = CLOCK_GetFRGInputClock(); uint32_t mul; @@ -494,13 +954,16 @@ uint32_t CLOCK_SetFRGClock(uint32_t freq) } else { - mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); + mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK; return 1; } } /* Set IP Clk */ +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ uint32_t CLOCK_GetFreq(clock_name_t clockName) { uint32_t freq; @@ -513,22 +976,22 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U); break; case kCLOCK_ClockOut: - freq = CLOCK_GetClockOutClkFreq() / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); + freq = CLOCK_GetClockOutClkFreq(); break; case kCLOCK_SpiFi: - freq = CLOCK_GetSpifiClkFreq() / ((SYSCON->SPIFICLKDIV & 0xffU) + 1U ); + freq = CLOCK_GetSpifiClkFreq(); break; case kCLOCK_Adc: - freq = CLOCK_GetAdcClkFreq() / ((SYSCON->ADCCLKDIV & 0xffU) + 1U ); + freq = CLOCK_GetAdcClkFreq(); break; case kCLOCK_Usb0: - freq = CLOCK_GetUsb0ClkFreq() / ((SYSCON->USB0CLKDIV & 0xffU) + 1U ); + freq = CLOCK_GetUsb0ClkFreq(); break; case kCLOCK_Usb1: - freq = CLOCK_GetUsb1ClkFreq() / ((SYSCON->USB1CLKDIV & 0xffU) + 1U ); + freq = CLOCK_GetUsb1ClkFreq(); break; case kCLOCK_Mclk: - freq = CLOCK_GetMclkClkFreq() / ((SYSCON->MCLKDIV & 0xffU) + 1U ); + freq = CLOCK_GetMclkClkFreq(); break; case kCLOCK_FroHf: freq = CLOCK_GetFroHfFreq(); @@ -542,39 +1005,29 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) case kCLOCK_PllOut: freq = CLOCK_GetPllOutFreq(); break; - case kClock_WdtOsc: + case kCLOCK_WdtOsc: freq = CLOCK_GetWdtOscFreq(); break; case kCLOCK_Frg: - freq = (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : - (SYSCON->FRGCLKSEL == 1U) ? CLOCK_GetPllOutFreq() : - (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : - (SYSCON->FRGCLKSEL == 3U) ? CLOCK_GetFroHfFreq() : 0U; + freq = CLOCK_GetFrgClkFreq(); break; case kCLOCK_Dmic: - freq = (SYSCON->DMICCLKSEL == 0U) ? CLOCK_GetFro12MFreq() : - (SYSCON->DMICCLKSEL == 1U) ? CLOCK_GetFroHfFreq() : - (SYSCON->DMICCLKSEL == 2U) ? CLOCK_GetPllOutFreq() : - (SYSCON->DMICCLKSEL == 3U) ? CLOCK_GetI2SMClkFreq() : - (SYSCON->DMICCLKSEL == 4U) ? CLOCK_GetCoreSysClkFreq() : - (SYSCON->DMICCLKSEL == 5U) ? CLOCK_GetWdtOscFreq() : 0U; - freq = freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U); + freq = CLOCK_GetDmicClkFreq(); break; - case kCLOCK_AsyncApbClk: freq = CLOCK_GetAsyncApbClkFreq(); break; case kCLOCK_Sct: - freq = CLOCK_GetSctClkFreq() / ((SYSCON->SCTCLKDIV & 0xffU) + 1U); + freq = CLOCK_GetSctClkFreq(); break; case kCLOCK_SDio: - freq = CLOCK_GetSdioClkFreq() / ((SYSCON->SDIOCLKDIV & 0xffU) + 1U); + freq = CLOCK_GetSdioClkFreq(); break; case kCLOCK_EMC: freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U) / ((SYSCON->EMCCLKDIV & 0xffU) + 1U); break; case kCLOCK_LCD: - freq = CLOCK_GetLcdClkFreq() / ((SYSCON->LCDCLKDIV & 0xffU) + 1U); + freq = CLOCK_GetLcdClkFreq(); break; case kCLOCK_MCAN0: freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->CAN0CLKDIV & 0xffU) + 1U); @@ -624,6 +1077,11 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) } /* Set the FLASH wait states for the passed frequency */ +/** + * brief Set the flash wait states for the input freuqency. + * param iFreq : Input frequency + * return Nothing + */ void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) { if (iFreq <= 12000000U) @@ -977,21 +1435,13 @@ static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) return mMult; } -/* Calculate the powerTimes' power of 2 */ -static uint32_t power2Cal(uint32_t powerTimes) -{ - if (powerTimes == 0) - return 1; - return 2 * power2Cal(powerTimes - 1); -} - /* Convert the binary to fractional part */ static double Binary2Fractional(uint32_t binaryPart) { double fractional = 0; for (uint32_t i = 0; i <= 14; i++) { - fractional += (double)((binaryPart >> i) & 0x1U) / (double)power2Cal(15 - i); + fractional += (double)((binaryPart >> i) & 0x1U) / (double)(1 << (15 - i)); } return fractional; } @@ -1004,8 +1454,8 @@ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) while (n != 0U) { tmp = n; - n = m % n; - m = tmp; + n = m % n; + m = tmp; } return m; @@ -1017,8 +1467,7 @@ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. */ -static pll_error_t CLOCK_GetPllConfigInternal( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup) +static pll_error_t CLOCK_GetPllConfigInternal(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup) { uint32_t nDivOutHz, fccoHz, multFccoDiv; uint32_t pllPreDivider, pllMultiplier, pllPostDivider; @@ -1026,10 +1475,10 @@ static pll_error_t CLOCK_GetPllConfigInternal( uint32_t pllSelP, pllSelI, pllSelR, uplimoff; /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 0U; /* 0 implies post-divider will be disabled */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 0U; /* 0 implies post-divider will be disabled */ pllDirectOutput = 1U; - multFccoDiv = 2U; + multFccoDiv = 2U; /* Verify output rate parameter */ if (foutHz > PLL_MAX_CCO_FREQ_MHZ) @@ -1066,7 +1515,7 @@ static pll_error_t CLOCK_GetPllConfigInternal( } /* Target CCO goes up, PLL output goes down */ - fccoHz = foutHz * (pllPostDivider * 2U); + fccoHz = foutHz * (pllPostDivider * 2U); pllDirectOutput = 0U; } @@ -1096,7 +1545,7 @@ static pll_error_t CLOCK_GetPllConfigInternal( } /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); + nDivOutHz = (finHz / pllPreDivider); pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv; /* Find optimal values for filter */ @@ -1111,38 +1560,36 @@ static pll_error_t CLOCK_GetPllConfigInternal( uplimoff = 0U; /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->pllmdec = - PLL_MDEC_VAL_SET(pllEncodeM(pllMultiplier)) ; + pSetup->pllmdec = PLL_MDEC_VAL_SET(pllEncodeM(pllMultiplier)); /* Get encoded values for N (prediv) and P (postdiv) */ pSetup->pllndec = PLL_NDEC_VAL_SET(pllEncodeN(pllPreDivider)); pSetup->pllpdec = PLL_PDEC_VAL_SET(pllEncodeP(pllPostDivider)); /* PLL control */ - pSetup->pllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) | /* Filter coefficient */ - (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) | /* Filter coefficient */ - (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) | /* Filter coefficient */ - (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) | /* PLL bypass mode disabled */ - (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) | /* SS/fractional mode disabled */ - (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */ - (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */ + pSetup->pllctrl = (pllSelR << SYSCON_SYSPLLCTRL_SELR_SHIFT) | /* Filter coefficient */ + (pllSelI << SYSCON_SYSPLLCTRL_SELI_SHIFT) | /* Filter coefficient */ + (pllSelP << SYSCON_SYSPLLCTRL_SELP_SHIFT) | /* Filter coefficient */ + (0 << SYSCON_SYSPLLCTRL_BYPASS_SHIFT) | /* PLL bypass mode disabled */ + (uplimoff << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT) | /* SS/fractional mode disabled */ + (pllDirectInput << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT) | /* Bypass pre-divider? */ + (pllDirectOutput << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT); /* Bypass post-divider? */ return kStatus_PLL_Success; } #if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) /* Alloct the static buffer for cache. */ -pll_setup_t gPllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; -uint32_t gFinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -uint32_t gFoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; -uint32_t gPllSetupCacheIdx = 0U; +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_PllSetupCacheIdx = 0U; #endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ /* * Calculate the PLL setting values from input clock freq to output freq. */ -static pll_error_t CLOCK_GetPllConfig( - uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup) +static pll_error_t CLOCK_GetPllConfig(uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup) { pll_error_t retErr; #if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) @@ -1150,14 +1597,15 @@ static pll_error_t CLOCK_GetPllConfig( for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) { - if ( (finHz == gFinHzCache[i]) && (foutHz == gFoutHzCache[i]) ) + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i])) { /* Hit the target in cache buffer. */ - pSetup->pllctrl = gPllSetupCacheStruct[i].pllctrl; - pSetup->pllndec = gPllSetupCacheStruct[i].pllndec; - pSetup->pllpdec = gPllSetupCacheStruct[i].pllpdec; - pSetup->pllmdec = gPllSetupCacheStruct[i].pllmdec; - retErr = kStatus_PLL_Success; + pSetup->pllctrl = s_PllSetupCacheStruct[i].pllctrl; + pSetup->pllndec = s_PllSetupCacheStruct[i].pllndec; + pSetup->pllpdec = s_PllSetupCacheStruct[i].pllpdec; + pSetup->pllmdec = s_PllSetupCacheStruct[i].pllmdec; + retErr = kStatus_PLL_Success; + break; } } @@ -1174,15 +1622,15 @@ static pll_error_t CLOCK_GetPllConfig( if (kStatus_PLL_Success == retErr) { /* Cache the most recent calulation result into buffer. */ - gFinHzCache[gPllSetupCacheIdx] = finHz; - gFoutHzCache[gPllSetupCacheIdx] = foutHz; - - gPllSetupCacheStruct[gPllSetupCacheIdx].pllctrl = pSetup->pllctrl; - gPllSetupCacheStruct[gPllSetupCacheIdx].pllndec = pSetup->pllndec; - gPllSetupCacheStruct[gPllSetupCacheIdx].pllpdec = pSetup->pllpdec; - gPllSetupCacheStruct[gPllSetupCacheIdx].pllmdec = pSetup->pllmdec; + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllctrl = pSetup->pllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllndec = pSetup->pllndec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllpdec = pSetup->pllpdec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].pllmdec = pSetup->pllmdec; /* Update the index for next available buffer. */ - gPllSetupCacheIdx = (gPllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; } #endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ @@ -1214,6 +1662,9 @@ static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup) } /* Return System PLL input clock rate */ +/*! brief Return System PLL input clock rate + * return System PLL input clock rate + */ uint32_t CLOCK_GetSystemPLLInClockRate(void) { uint32_t clkRate = 0U; @@ -1245,6 +1696,9 @@ uint32_t CLOCK_GetSystemPLLInClockRate(void) } /* Return Audio PLL input clock rate */ +/*! brief Return Audio PLL input clock rate + * return Audio PLL input clock rate + */ uint32_t CLOCK_GetAudioPLLInClockRate(void) { uint32_t clkRate = 0U; @@ -1258,7 +1712,7 @@ uint32_t CLOCK_GetAudioPLLInClockRate(void) case 0x01U: clkRate = CLOCK_GetExtClkFreq(); break; - + default: clkRate = 0U; break; @@ -1268,6 +1722,10 @@ uint32_t CLOCK_GetAudioPLLInClockRate(void) } /* Return System PLL output clock rate from setup structure */ +/*! brief Return System PLL output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return System PLL output clock rate the setup structure will generate + */ uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) { uint32_t prediv, postdiv, mMult, inPllRate; @@ -1300,18 +1758,17 @@ uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) } else { - postdiv = 1U; /* The post-divider is bypassed. */ + postdiv = 1U; /* The post-divider is bypassed. */ } /* Adjust input clock */ inPllRate = inPllRate / prediv; /* MDEC used for rate */ - mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec); + mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec); workRate = (uint64_t)inPllRate * (uint64_t)mMult; workRate = workRate / ((uint64_t)postdiv); workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/ - } else { @@ -1323,30 +1780,38 @@ uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) } /* Return Usb PLL output clock rate from setup structure */ +/*! brief Return System USB PLL output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return System PLL output clock rate the setup structure will generate + */ uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup) { uint32_t nsel, psel, msel, inPllRate; uint64_t workRate; inPllRate = CLOCK_GetExtClkFreq(); - msel = pSetup->msel; - psel = pSetup->psel; - nsel = pSetup->nsel; + msel = pSetup->msel; + psel = pSetup->psel; + nsel = pSetup->nsel; if (pSetup->fbsel == 1U) - { - /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */ - workRate = (inPllRate) * (msel + 1U) / (nsel + 1U); - } - else - { - /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */ - workRate = (inPllRate / (nsel + 1U)) * (msel + 1U) / (2U * SWITCH_USB_PSEL(psel)); - } - + { + /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */ + workRate = (uint64_t)(inPllRate) * (msel + 1U) / (nsel + 1U); + } + else + { + /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */ + workRate = (uint64_t)(inPllRate / (nsel + 1U)) * (msel + 1U) / (2U * (1U << (psel & 3U))); + } + return (uint32_t)workRate; } /* Return Audio PLL output clock rate from setup structure */ +/*! brief Return System AUDIO PLL output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return System PLL output clock rate the setup structure will generate + */ uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup) { uint32_t prediv, postdiv, mMult, inPllRate; @@ -1378,13 +1843,13 @@ uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup) } else { - postdiv = 1U; /* The post-divider is bypassed. */ + postdiv = 1U; /* The post-divider is bypassed. */ } /* Adjust input clock */ inPllRate = inPllRate / prediv; /* MDEC used for rate */ - mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec); + mMult = findPllMMult(pSetup->pllctrl, pSetup->pllmdec); workRate = (uint64_t)inPllRate * (uint64_t)mMult; workRate = workRate / ((uint64_t)postdiv); @@ -1400,6 +1865,10 @@ uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup) } /* Return Audio PLL output clock rate from audio fractioanl setup structure */ +/*! brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure + * param pSetup : Pointer to a PLL setup structure + * return System PLL output clock rate the setup structure will generate + */ uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup) { uint32_t prediv, postdiv, inPllRate; @@ -1431,13 +1900,13 @@ uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup) } else { - postdiv = 1U; /* The post-divider is bypassed. */ + postdiv = 1U; /* The post-divider is bypassed. */ } /* Adjust input clock */ inPllRate = inPllRate / prediv; mMultFactional = (double)(pSetup->audpllfrac >> 15) + (double)Binary2Fractional(pSetup->audpllfrac & 0x7FFFU); - workRate = (double)inPllRate * (double)mMultFactional; + workRate = (double)inPllRate * (double)mMultFactional; workRate = workRate / ((double)postdiv); workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/ @@ -1452,24 +1921,43 @@ uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup) } /* Set the current PLL Rate */ +/*! brief Store the current PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ void CLOCK_SetStoredPLLClockRate(uint32_t rate) { s_Pll_Freq = rate; } /* Set the current Audio PLL Rate */ +/*! brief Store the current AUDIO PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate) { s_Audio_Pll_Freq = rate; } /* Set the current Usb PLL Rate */ +/*! brief Set USB PLL output frequency + * param rate : frequency value + * + */ void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate) { s_Usb_Pll_Freq = rate; } /* Return System PLL output clock rate */ +/*! brief Return System PLL output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return System PLL output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) { pll_setup_t Setup; @@ -1491,6 +1979,13 @@ uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) } /* Return AUDIO PLL output clock rate */ +/*! brief Return System AUDIO PLL output clock rate + * param recompute : Forces a AUDIO PLL rate recomputation if true + * return System AUDIO PLL output clock rate + * note The AUDIO PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute) { pll_setup_t Setup; @@ -1511,6 +2006,13 @@ uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute) } /* Return USB PLL output clock rate */ +/*! brief Return System USB PLL output clock rate + * param recompute : Forces a USB PLL rate recomputation if true + * return System USB PLL output clock rate + * note The USB PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute) { usb_pll_setup_t Setup; @@ -1518,12 +2020,12 @@ uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute) if ((recompute) || (s_Usb_Pll_Freq == 0U)) { - Setup.msel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_MSEL_SHIFT) & SYSCON_USBPLLCTRL_MSEL_MASK; - Setup.psel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_PSEL_SHIFT) & SYSCON_USBPLLCTRL_PSEL_MASK; - Setup.nsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_NSEL_SHIFT) & SYSCON_USBPLLCTRL_NSEL_MASK; - Setup.fbsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_FBSEL_SHIFT) & SYSCON_USBPLLCTRL_FBSEL_MASK; + Setup.msel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_MSEL_SHIFT) & SYSCON_USBPLLCTRL_MSEL_MASK; + Setup.psel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_PSEL_SHIFT) & SYSCON_USBPLLCTRL_PSEL_MASK; + Setup.nsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_NSEL_SHIFT) & SYSCON_USBPLLCTRL_NSEL_MASK; + Setup.fbsel = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_FBSEL_SHIFT) & SYSCON_USBPLLCTRL_FBSEL_MASK; Setup.bypass = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_BYPASS_SHIFT) & SYSCON_USBPLLCTRL_BYPASS_MASK; - Setup.direct = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_DIRECT_SHIFT) & SYSCON_USBPLLCTRL_DIRECT_MASK; + Setup.direct = (SYSCON->USBPLLCTRL >> SYSCON_USBPLLCTRL_DIRECT_SHIFT) & SYSCON_USBPLLCTRL_DIRECT_MASK; CLOCK_GetUsbPLLOutFromSetupUpdate(&Setup); } @@ -1532,6 +2034,13 @@ uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute) } /* Set PLL output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) { uint32_t inRate; @@ -1548,18 +2057,28 @@ pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) } /* PLL flag options */ - pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup); + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup); pSetup->pllRate = pControl->desiredRate; return pllError; } /* Set PLL output from PLL setup structure */ +/*! brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) { if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U) { - /* Turn on the ext clock if system pll input select clk_in */ - CLOCK_Enable_SysOsc(true); + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); } /* Enable power for PLLs */ POWER_SetPLL(); @@ -1583,7 +2102,7 @@ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) { /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U); /* Initialize and power up PLL */ @@ -1626,14 +2145,23 @@ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) return kStatus_PLL_Success; } - /* Set AUDIO PLL output from AUDIO PLL setup structure */ +/*! brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock, + * and adjust system voltages to the new AUDIOPLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL, + * so these should be setup prior to and after exiting the function. + */ pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) { if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U) { - /* Turn on the ext clock if system pll input select clk_in */ - CLOCK_Enable_SysOsc(true); + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); } /* Enable power VD3 for PLLs */ POWER_SetPLL(); @@ -1650,14 +2178,14 @@ pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ SYSCON->AUDPLLMDEC = pSetup->pllmdec; SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_SYSPLLMDEC_MREQ_SHIFT); /* latch */ - SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */ + SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */ /* Flags for lock or power on */ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U) { /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ uint32_t curSSCTRL = SYSCON->AUDPLLMDEC & ~(1U << 17U); /* Initialize and power up PLL */ @@ -1695,12 +2223,23 @@ pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) } /* Set AUDIO PLL output from AUDIO PLL fractional setup structure */ +/*! brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise + * frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock, + * and adjust system voltages to the new AUDIOPLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL, + * so these should be setup prior to and after exiting the function. + */ pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg) { if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U) { - /* Turn on the ext clock if system pll input select clk_in */ - CLOCK_Enable_SysOsc(true); + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); } /* Enable power VD3 for PLLs */ POWER_SetPLL(); @@ -1737,6 +2276,13 @@ pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg) } /* Set Audio PLL output based on the passed Audio PLL setup data */ +/*! brief Set AUDIO PLL output based on the passed AUDIO PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup) { uint32_t inRate; @@ -1753,20 +2299,28 @@ pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup) } /* PLL flag options */ - pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup); + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup); pSetup->pllRate = pControl->desiredRate; return pllError; } - - /* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) { if ((SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK) == 0x01U) { - /* Turn on the ext clock if system pll input select clk_in */ - CLOCK_Enable_SysOsc(true); + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); } /* Enable power VD3 for PLLs */ POWER_SetPLL(); @@ -1787,7 +2341,7 @@ pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) { /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U); /* Initialize and power up PLL */ @@ -1825,12 +2379,22 @@ pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) } /* Setup Audio PLL Frequency from pre-calculated value */ +/** + * brief Set Audio PLL output from Audio PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or Audio PLL setup error code + * note This function will power off the PLL, setup the Audio PLL with the + * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the Audio PLL, + * so these should be setup prior to and after exiting the function. + */ pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup) { if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U) { - /* Turn on the ext clock if system pll input select clk_in */ - CLOCK_Enable_SysOsc(true); + /* Turn on the ext clock if system pll input select clk_in */ + CLOCK_Enable_SysOsc(true); } /* Enable power VD3 for PLLs */ POWER_SetPLL(); @@ -1840,21 +2404,21 @@ pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup) /* Write Audio PLL setup data */ SYSCON->AUDPLLCTRL = pSetup->pllctrl; SYSCON->AUDPLLFRAC = pSetup->audpllfrac; - SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1U << SYSCON_AUDPLLFRAC_REQ_SHIFT); /* latch */ + SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1U << SYSCON_AUDPLLFRAC_REQ_SHIFT); /* latch */ SYSCON->AUDPLLNDEC = pSetup->pllndec; - SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_AUDPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_AUDPLLNDEC_NREQ_SHIFT); /* latch */ SYSCON->AUDPLLPDEC = pSetup->pllpdec; - SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_AUDPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_AUDPLLPDEC_PREQ_SHIFT); /* latch */ SYSCON->AUDPLLMDEC = pSetup->pllmdec; - SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_AUDPLLMDEC_MREQ_SHIFT); /* latch */ - SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */ + SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1U << SYSCON_AUDPLLMDEC_MREQ_SHIFT); /* latch */ + SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */ /* Flags for lock or power on */ if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0) { /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1U << 17U); /* Initialize and power up PLL */ @@ -1892,39 +2456,49 @@ pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup) } /* Setup USB PLL Frequency from pre-calculated value */ +/** + * brief Set USB PLL output from USB PLL setup structure (precise frequency) + * param pSetup : Pointer to populated USB PLL setup structure + * return kStatus_PLL_Success on success, or USB PLL setup error code + * note This function will power off the USB PLL, setup the PLL with the + * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock, + * and adjust system voltages to the new USB PLL rate. The function will not + * alter any source clocks (ie, usb pll clock) that may use the USB PLL, + * so these should be setup prior to and after exiting the function. + */ pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup) -{ +{ uint32_t usbpllctrl, fccoHz; uint8_t msel, psel, nsel; bool pllDirectInput, pllDirectOutput, pllfbsel; volatile uint32_t delayX; - msel = pSetup->msel; - psel = pSetup->psel; - nsel = pSetup->nsel; - pllDirectInput = pSetup->direct; - pllDirectOutput = pSetup->bypass; - pllfbsel = pSetup->fbsel; - + msel = pSetup->msel; + psel = pSetup->psel; + nsel = pSetup->nsel; + pllDirectOutput = pSetup->direct; + pllDirectInput = pSetup->bypass; + pllfbsel = pSetup->fbsel; + /* Input clock into the PLL cannot be lower than this */ - if (pSetup->inputRate < USB_PLL_LOWER_IN_LIMIT ) + if (pSetup->inputRate < USB_PLL_LOWER_IN_LIMIT) { return kStatus_PLL_InputTooLow; } - + if (pllfbsel == 1U) - { + { /*integer_mode: Fout = M*(Fin/N), Fcco = 2*P*M*(Fin/N) */ - fccoHz = (pSetup->inputRate / (nsel + 1U)) * 2 * (msel + 1U) * SWITCH_USB_PSEL(psel) ; - - /* USB PLL CCO out rate cannot be lower than this */ + fccoHz = (pSetup->inputRate / (nsel + 1U)) * 2 * (msel + 1U) * (1U << (psel & 3U)); + + /* USB PLL CCO out rate cannot be lower than this */ if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ) - { + { return kStatus_PLL_CCOTooLow; } /* USB PLL CCO out rate cannot be Higher than this */ if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ) - { + { return kStatus_PLL_CCOTooHigh; } } @@ -1932,62 +2506,75 @@ pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup) { /* non integer_mode: Fout = M*(Fin/N)/(2*P), Fcco = M * (Fin/N) */ fccoHz = pSetup->inputRate / (nsel + 1U) * (msel + 1U); - - /* USB PLL CCO out rate cannot be lower than this */ + + /* USB PLL CCO out rate cannot be lower than this */ if (fccoHz < USB_PLL_MIN_CCO_FREQ_MHZ) - { + { return kStatus_PLL_CCOTooLow; } /* USB PLL CCO out rate cannot be Higher than this */ if (fccoHz > USB_PLL_MAX_CCO_FREQ_MHZ) - { + { return kStatus_PLL_CCOTooHigh; - } + } } - - /* If configure the USB HOST clock, VD5 power for USB PHY should be enable + + /* If configure the USB HOST clock, VD5 power for USB PHY should be enable before the PLL is working */ /* Turn on the ext clock for usb pll input */ CLOCK_Enable_SysOsc(true); - + /* Enable power VD3 for PLLs */ POWER_SetPLL(); - - /* Power on the VD5 for USB PHY */ + + /* Power on the VD5 for USB PHY */ POWER_SetUsbPhy(); /* Power off USB PLL during setup changes */ POWER_EnablePD(kPDRUNCFG_PD_USB_PLL); - + /* Write USB PLL setup data */ - usbpllctrl = USB_PLL_NSEL_VAL_SET(nsel) | /* NSEL VALUE */ - USB_PLL_PSEL_VAL_SET(psel) | /* PSEL VALUE */ - USB_PLL_MSEL_VAL_SET(msel) | /* MSEL VALUE */ - (uint32_t)pllDirectInput << SYSCON_USBPLLCTRL_BYPASS_SHIFT | /* BYPASS DISABLE */ - (uint32_t)pllDirectOutput << SYSCON_USBPLLCTRL_DIRECT_SHIFT | /* DIRECTO DISABLE */ - (uint32_t)pllfbsel << SYSCON_USBPLLCTRL_FBSEL_SHIFT; /* FBSEL SELECT */ - + usbpllctrl = USB_PLL_NSEL_VAL_SET(nsel) | /* NSEL VALUE */ + USB_PLL_PSEL_VAL_SET(psel) | /* PSEL VALUE */ + USB_PLL_MSEL_VAL_SET(msel) | /* MSEL VALUE */ + (uint32_t)pllDirectInput << SYSCON_USBPLLCTRL_BYPASS_SHIFT | /* BYPASS DISABLE */ + (uint32_t)pllDirectOutput << SYSCON_USBPLLCTRL_DIRECT_SHIFT | /* DIRECTO DISABLE */ + (uint32_t)pllfbsel << SYSCON_USBPLLCTRL_FBSEL_SHIFT; /* FBSEL SELECT */ + SYSCON->USBPLLCTRL = usbpllctrl; - + POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); - + /* Delay for 72 uSec @ 12Mhz for the usb pll to lock */ for (delayX = 0U; delayX < 172U; ++delayX) { } - - while (CLOCK_IsUsbPLLLocked() == false) + if (false == pllDirectInput) { + while (CLOCK_IsUsbPLLLocked() == false) + { + } } CLOCK_GetUsbPLLOutFromSetupUpdate(pSetup); return kStatus_PLL_Success; } /* Set System PLL clock based on the input frequency and multiplier */ +/*! brief Set PLL output based on the multiplier and input frequency + * param multiply_by : multiplier + * param input_freq : Clock input frequency of the PLL + * return Nothing + * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) { uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; + uint32_t pdec = 1U; uint32_t selr; uint32_t seli; uint32_t selp; @@ -2034,9 +2621,9 @@ void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) if (pdec > 1U) { - directo = 0U; /* use post divider */ - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ + directo = 0U; /* use post divider */ + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ switch (pdec) { case 1U: @@ -2066,8 +2653,7 @@ void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) mdec = PLL_MDEC_VAL_SET(pllEncodeM(multiply_by)); ndec = 0x302U; /* pre divide by 1 (hardcoded) */ - SYSCON->SYSPLLCTRL = directo | - (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) | + SYSCON->SYSPLLCTRL = directo | (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) | (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT); SYSCON->SYSPLLPDEC = pdec | (1U << 7U); /* set Pdec value and assert preq */ SYSCON->SYSPLLNDEC = ndec | (1U << 10U); /* set Pdec value and assert preq */ @@ -2075,6 +2661,11 @@ void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) } /* Enable USB DEVICE FULL SPEED clock */ +/*! brief Enable USB Device FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB Device Full Speed clock. + */ bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq) { bool ret = true; @@ -2088,11 +2679,11 @@ bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq) case 96000000U: CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ break; - + case 48000000U: CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ break; - + default: ret = false; break; @@ -2107,25 +2698,30 @@ bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq) { /*Set the USB PLL as the Usb0 CLK*/ POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); - - usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; + + usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U}; CLOCK_SetUsbPLLFreq(&pll_setup); - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false); + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK); uint32_t delay = 100000; - while (delay --) + while (delay--) { - __asm("nop"); + __ASM("nop"); } } CLOCK_EnableClock(kCLOCK_Usbd0); CLOCK_EnableClock(kCLOCK_UsbRam1); - + return ret; } /* Enable USB HOST FULL SPEED clock */ +/*! brief Enable USB HOST FS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB HOST Full Speed clock. + */ bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq) { bool ret = true; @@ -2140,11 +2736,11 @@ bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq) case 96000000U: CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ break; - + case 48000000U: CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ break; - + default: ret = false; break; @@ -2159,32 +2755,37 @@ bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq) { /*Set the USB PLL as the Usb0 CLK*/ POWER_DisablePD(kPDRUNCFG_PD_USB_PLL); - - usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; + + usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U}; CLOCK_SetUsbPLLFreq(&pll_setup); - CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk,1U, false); + CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); CLOCK_AttachClk(kUSB_PLL_to_USB0_CLK); uint32_t delay = 100000; - while (delay --) + while (delay--) { - __asm("nop"); + __ASM("nop"); } } CLOCK_EnableClock(kCLOCK_Usbhmr0); CLOCK_EnableClock(kCLOCK_Usbhsl0); - CLOCK_EnableClock(kCLOCK_UsbRam1); + CLOCK_EnableClock(kCLOCK_UsbRam1); return ret; } /* Enable USB DEVICE HIGH SPEED clock */ +/*! brief Enable USB Device HS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB Device High Speed clock. + */ bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq) { bool ret = true; uint32_t delay; CLOCK_DisableClock(kCLOCK_Usbd1); - /* Power on the VD5 for USB PHY */ + /* Power on the VD5 for USB PHY */ POWER_SetUsbPhy(); if (kCLOCK_UsbSrcFro == src) { @@ -2193,11 +2794,11 @@ bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq) case 96000000U: CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ break; - + case 48000000U: CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ break; - + default: ret = false; break; @@ -2209,41 +2810,45 @@ bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq) CLOCK_AttachClk(kFRO_HF_to_USB1_CLK); } else - { + { delay = 100000; - while (delay --) + while (delay--) { - __asm("nop"); - } - usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; - + __ASM("nop"); + } + usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U}; + CLOCK_SetUsbPLLFreq(&pll_setup); - + /* Select USB PLL output as USB clock src */ - CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false); - CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK); + CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); + CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK); } delay = 100000; - while (delay --) + while (delay--) { - __asm("nop"); + __ASM("nop"); } /* Enable USB1D and USB1RAM */ CLOCK_EnableClock(kCLOCK_Usbd1); - CLOCK_EnableClock(kCLOCK_UsbRam1); + CLOCK_EnableClock(kCLOCK_UsbRam1); POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */ return ret; } - /* Enable USB HOST HIGH SPEED clock */ +/*! brief Enable USB HOST HS clock. + * param src : clock source + * param freq: clock frequency + * Enable USB HOST High Speed clock. + */ bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq) { bool ret = true; uint32_t delay; CLOCK_DisableClock(kCLOCK_Usbh1); - /* Power on the VD5 for USB PHY */ + /* Power on the VD5 for USB PHY */ POWER_SetUsbPhy(); if (kCLOCK_UsbSrcFro == src) { @@ -2252,11 +2857,11 @@ bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq) case 96000000U: CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 2, false); /*!< Div by 2 to get 48MHz, no divider reset */ break; - + case 48000000U: CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1, false); /*!< Div by 1 to get 48MHz, no divider reset */ break; - + default: ret = false; break; @@ -2270,27 +2875,75 @@ bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq) else { delay = 100000; - while (delay --) + while (delay--) { - __asm("nop"); - } - usb_pll_setup_t pll_setup = { 0x3FU, 0x01U, 0x03U, false, false, false, 12000000U }; + __ASM("nop"); + } + usb_pll_setup_t pll_setup = {0x3FU, 0x01U, 0x03U, false, false, false, 12000000U}; CLOCK_SetUsbPLLFreq(&pll_setup); - + /* Select USB PLL output as USB clock src */ - CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk,1U, false); + CLOCK_SetClkDiv(kCLOCK_DivUsb1Clk, 1U, false); CLOCK_AttachClk(kUSB_PLL_to_USB1_CLK); } delay = 100000; - while (delay --) + while (delay--) { - __asm("nop"); + __ASM("nop"); } /* Enable USBh1 and USB1RAM */ CLOCK_EnableClock(kCLOCK_Usbh1); - CLOCK_EnableClock(kCLOCK_UsbRam1); + CLOCK_EnableClock(kCLOCK_UsbRam1); POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); /* Turn on power for USB PHY */ return ret; } + +/*! + * brief Use DWT to delay at least for some time. + * Please note that, this API will calculate the microsecond period with the maximum devices + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * param delay_us Delay time in unit of microsecond. + */ +__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us) +{ + assert(0U != delay_us); + uint64_t count = 0U; + uint32_t period = SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 1000000; + + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* If CYCCENT has already been enabled, read directly, otherwise, need enable it. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } + + /* Calculate the count ticks. */ + count = DWT->CYCCNT; + count += (uint64_t)period * delay_us; + + if (count > 0xFFFFFFFFUL) + { + count -= 0xFFFFFFFFUL; + /* wait for cyccnt overflow. */ + while (count < DWT->CYCCNT) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > DWT->CYCCNT) + { + } +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_clock.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_clock.h index b21e9e43f5..f8dbb8ef9b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_clock.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/drivers/fsl_clock.h @@ -1,45 +1,16 @@ /* - * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright (c) 2016 - 2017 , NXP + * Copyright 2016 - 2019 , NXP * All rights reserved. * * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name ofcopyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CLOCK_H_ #define _FSL_CLOCK_H_ -#include "fsl_device_registers.h" -#include -#include -#include +#include "fsl_common.h" /*! @addtogroup clock */ /*! @{ */ @@ -52,15 +23,15 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.0.0. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief CLOCK driver version 2.2.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*@}*/ /*! @brief Configure whether driver controls clock * * When set to 0, peripheral drivers will enable clock in initialize function * and disable clock in de-initialize function. When set to 1, peripheral - * driver will not control the clock, application could contol the clock out of + * driver will not control the clock, application could control the clock out of * the driver. * * @note All drivers share this feature switcher. If it is set to 1, application @@ -78,12 +49,29 @@ * right settings. */ #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT -#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U #endif +/*! @brief FROHF clock setting API address in ROM. */ +#define CLOCK_FROHF_SETTING_API_ROM_ADDRESS (0x030091DFU) + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (220000000UL) +#endif + +/** + * Initialize the Core clock to given frequency (12, 48 or 96 MHz), this API is implememnt in ROM code. + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed + * output is enabled. + * Usage: set_fro_frequency(frequency), (frequency must be one of 12, 48 or 96 MHz) + */ + +#define set_fro_frequency(iFreq) (*((void (*)(uint32_t iFreq))(CLOCK_FROHF_SETTING_API_ROM_ADDRESS)))(iFreq) + /*! @brief Clock ip name array for ROM. */ -#define ADC_CLOCKS \ - { \ +#define ADC_CLOCKS \ + { \ kCLOCK_Adc0 \ } /*! @brief Clock ip name array for ROM. */ @@ -92,8 +80,8 @@ kCLOCK_Rom \ } /*! @brief Clock ip name array for SRAM. */ -#define SRAM_CLOCKS \ - { \ +#define SRAM_CLOCKS \ + { \ kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \ } /*! @brief Clock ip name array for FLASH. */ @@ -107,121 +95,120 @@ kCLOCK_Fmc \ } /*! @brief Clock ip name array for EEPROM. */ -#define EEPROM_CLOCKS \ - { \ - kCLOCK_Eeprom \ +#define EEPROM_CLOCKS \ + { \ + kCLOCK_Eeprom \ } /*! @brief Clock ip name array for SPIFI. */ -#define SPIFI_CLOCKS \ - { \ - kCLOCK_Spifi \ +#define SPIFI_CLOCKS \ + { \ + kCLOCK_Spifi \ } /*! @brief Clock ip name array for INPUTMUX. */ -#define INPUTMUX_CLOCKS \ - { \ - kCLOCK_InputMux \ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux \ } /*! @brief Clock ip name array for IOCON. */ -#define IOCON_CLOCKS \ - { \ - kCLOCK_Iocon \ +#define IOCON_CLOCKS \ + { \ + kCLOCK_Iocon \ } /*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0,kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ } /*! @brief Clock ip name array for PINT. */ -#define PINT_CLOCKS \ - { \ - kCLOCK_Pint \ +#define PINT_CLOCKS \ + { \ + kCLOCK_Pint \ } /*! @brief Clock ip name array for GINT. */ -#define GINT_CLOCKS \ - { \ - kCLOCK_Gint, kCLOCK_Gint \ +#define GINT_CLOCKS \ + { \ + kCLOCK_Gint, kCLOCK_Gint \ } /*! @brief Clock ip name array for DMA. */ -#define DMA_CLOCKS \ - { \ - kCLOCK_Dma \ +#define DMA_CLOCKS \ + { \ + kCLOCK_Dma \ } /*! @brief Clock ip name array for CRC. */ -#define CRC_CLOCKS \ - { \ - kCLOCK_Crc \ +#define CRC_CLOCKS \ + { \ + kCLOCK_Crc \ } /*! @brief Clock ip name array for WWDT. */ -#define WWDT_CLOCKS \ - { \ - kCLOCK_Wwdt \ +#define WWDT_CLOCKS \ + { \ + kCLOCK_Wwdt \ } /*! @brief Clock ip name array for RTC. */ -#define RTC_CLOCKS \ - { \ - kCLOCK_Rtc \ +#define RTC_CLOCKS \ + { \ + kCLOCK_Rtc \ } /*! @brief Clock ip name array for ADC0. */ -#define ADC0_CLOCKS \ - { \ - kCLOCK_Adc0 \ +#define ADC0_CLOCKS \ + { \ + kCLOCK_Adc0 \ } /*! @brief Clock ip name array for MRT. */ -#define MRT_CLOCKS \ - { \ - kCLOCK_Mrt \ +#define MRT_CLOCKS \ + { \ + kCLOCK_Mrt \ } /*! @brief Clock ip name array for RIT. */ -#define RIT_CLOCKS \ - { \ - kCLOCK_Rit \ +#define RIT_CLOCKS \ + { \ + kCLOCK_Rit \ } /*! @brief Clock ip name array for SCT0. */ -#define SCT_CLOCKS \ - { \ - kCLOCK_Sct0 \ +#define SCT_CLOCKS \ + { \ + kCLOCK_Sct0 \ } /*! @brief Clock ip name array for MCAN. */ -#define MCAN_CLOCKS \ - { \ - kCLOCK_Mcan0, kCLOCK_Mcan1 \ +#define MCAN_CLOCKS \ + { \ + kCLOCK_Mcan0, kCLOCK_Mcan1 \ } /*! @brief Clock ip name array for UTICK. */ -#define UTICK_CLOCKS \ - { \ - kCLOCK_Utick \ +#define UTICK_CLOCKS \ + { \ + kCLOCK_Utick \ } /*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, \ - kCLOCK_FlexComm4, kCLOCK_FlexComm5, kCLOCK_FlexComm6, kCLOCK_FlexComm7, \ - kCLOCK_FlexComm8, kCLOCK_FlexComm9 \ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ + kCLOCK_FlexComm6, kCLOCK_FlexComm7, kCLOCK_FlexComm8, kCLOCK_FlexComm9 \ } /*! @brief Clock ip name array for LPUART. */ #define LPUART_CLOCKS \ { \ kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \ - kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8,kCLOCK_MinUart9 \ + kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8, kCLOCK_MinUart9 \ } /*! @brief Clock ip name array for BI2C. */ -#define BI2C_CLOCKS \ - { \ - kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7, \ - kCLOCK_BI2c8, kCLOCK_BI2c9 \ +#define BI2C_CLOCKS \ + { \ + kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, \ + kCLOCK_BI2c7, kCLOCK_BI2c8, kCLOCK_BI2c9 \ } /*! @brief Clock ip name array for LSPI. */ -#define LPSI_CLOCKS \ - { \ - kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7, \ - kCLOCK_LSpi8, kCLOCK_LSpi9 \ +#define LPSI_CLOCKS \ + { \ + kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, \ + kCLOCK_LSpi7, kCLOCK_LSpi8, kCLOCK_LSpi9 \ } /*! @brief Clock ip name array for FLEXI2S. */ #define FLEXI2S_CLOCKS \ { \ kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ - kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \ + kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \ } /*! @brief Clock ip name array for DMIC. */ #define DMIC_CLOCKS \ @@ -229,73 +216,73 @@ kCLOCK_DMic \ } /*! @brief Clock ip name array for CT32B. */ -#define CTIMER_CLOCKS \ - { \ - kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \ +#define CTIMER_CLOCKS \ + { \ + kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \ } /*! @brief Clock ip name array for LCD. */ -#define LCD_CLOCKS \ - { \ - kCLOCK_Lcd \ +#define LCD_CLOCKS \ + { \ + kCLOCK_Lcd \ } /*! @brief Clock ip name array for SDIO. */ -#define SDIO_CLOCKS \ - { \ - kCLOCK_Sdio \ +#define SDIO_CLOCKS \ + { \ + kCLOCK_Sdio \ } /*! @brief Clock ip name array for USBRAM. */ -#define USBRAM_CLOCKS \ - { \ - kCLOCK_UsbRam1 \ +#define USBRAM_CLOCKS \ + { \ + kCLOCK_UsbRam1 \ } /*! @brief Clock ip name array for EMC. */ -#define EMC_CLOCKS \ - { \ - kCLOCK_Emc \ +#define EMC_CLOCKS \ + { \ + kCLOCK_Emc \ } /*! @brief Clock ip name array for ETH. */ -#define ETH_CLOCKS \ - { \ - kCLOCK_Eth \ +#define ETH_CLOCKS \ + { \ + kCLOCK_Eth \ } /*! @brief Clock ip name array for AES. */ -#define AES_CLOCKS \ - { \ - kCLOCK_Aes \ +#define AES_CLOCKS \ + { \ + kCLOCK_Aes \ } /*! @brief Clock ip name array for OTP. */ -#define OTP_CLOCKS \ - { \ - kCLOCK_Otp \ +#define OTP_CLOCKS \ + { \ + kCLOCK_Otp \ } /*! @brief Clock ip name array for RNG. */ -#define RNG_CLOCKS \ - { \ - kCLOCK_Rng \ +#define RNG_CLOCKS \ + { \ + kCLOCK_Rng \ } /*! @brief Clock ip name array for USBHMR0. */ -#define USBHMR0_CLOCKS \ - { \ - kCLOCK_Usbhmr0 \ +#define USBHMR0_CLOCKS \ + { \ + kCLOCK_Usbhmr0 \ } /*! @brief Clock ip name array for USBHSL0. */ -#define USBHSL0_CLOCKS \ - { \ - kCLOCK_Usbhsl0 \ +#define USBHSL0_CLOCKS \ + { \ + kCLOCK_Usbhsl0 \ } /*! @brief Clock ip name array for SHA0. */ -#define SHA0_CLOCKS \ - { \ - kCLOCK_Sha0 \ +#define SHA0_CLOCKS \ + { \ + kCLOCK_Sha0 \ } /*! @brief Clock ip name array for SMARTCARD. */ -#define SMARTCARD_CLOCKS \ - { \ +#define SMARTCARD_CLOCKS \ + { \ kCLOCK_SmartCard0, kCLOCK_SmartCard1 \ } /*! @brief Clock ip name array for USBD. */ -#define USBD_CLOCKS \ - { \ +#define USBD_CLOCKS \ + { \ kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \ } /*! @brief Clock ip name array for USBH. */ @@ -328,106 +315,106 @@ /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ typedef enum _clock_ip_name { - kCLOCK_IpInvalid = 0U, - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), - kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), - kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), - kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), - kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), - kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), - kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), - kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), - kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), - kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8), - kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), - kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), - kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), - kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), - kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), - kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), - kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), - kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), - kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), - kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), - kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), - kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), - kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2,8), - kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9), - kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10), - kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), - kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12), - kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), - kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), - kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), - kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), + kCLOCK_IpInvalid = 0U, + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), + kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9), + kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10), + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), + kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), + kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), + kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7), + kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8), + kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), + kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), + kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), + kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), + kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), + kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), + kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), + kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), + kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), + kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), + kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), + kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), + kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), + kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9), + kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10), + kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11), + kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12), + kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), + kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), + kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), + kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), + kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), + kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), @@ -458,7 +445,7 @@ typedef enum _clock_name kCLOCK_ExtClk, /*!< External Clock */ kCLOCK_PllOut, /*!< PLL Output */ kCLOCK_UsbClk, /*!< USB input */ - kClock_WdtOsc, /*!< Watchdog Oscillator */ + kCLOCK_WdtOsc, /*!< Watchdog Oscillator */ kCLOCK_Frg, /*!< Frg Clock */ kCLOCK_Dmic, /*!< Digital Mic clock */ kCLOCK_AsyncApbClk, /*!< Async APB clock */ @@ -489,18 +476,22 @@ typedef enum _async_clock_src } async_clock_src_t; /*! @brief Clock Mux Switches -* The encoding is as follows each connection identified is 64bits wide -* starting from LSB upwards -* -* [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]* -* -*/ + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ -#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8)) -#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20)) -#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32)) -#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44)) -#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56)) +#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) +#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU) +#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) #define CM_MAINCLKSELA 0 #define CM_MAINCLKSELB 1 @@ -524,8 +515,8 @@ typedef enum _async_clock_src #define CM_MCLKCLKSEL 24 #define CM_FRGCLKSEL 26 #define CM_DMICCLKSEL 27 -#define CM_SCTCLKSEL 28 -#define CM_LCDCLKSEL 29 +#define CM_SCTCLKSEL 28 +#define CM_LCDCLKSEL 29 #define CM_SDIOCLKSEL 30 #define CM_ASYNCAPB 31 @@ -533,189 +524,189 @@ typedef enum _async_clock_src typedef enum _clock_attach_id { - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0), - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0), - kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0), - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0), - kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2), - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3), + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), + kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), + kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), - kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), - kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), - kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), - kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), + kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), + kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), + kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), + kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), - kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), + kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), - kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), - kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), + kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), + kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), - kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0), + kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0), kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1), - kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7), + kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7), - kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0), - kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), - kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2), - kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), + kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0), + kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), + kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2), + kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4), - kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), + kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), - kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), - kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), + kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), + kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), - kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), + kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2), - kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), + kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), - kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0), + kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0), kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1), kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2), - kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7), + kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7), - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), - kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), + kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), - kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), + kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), - kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), + kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), - kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), + kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), - kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), + kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), - kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), + kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), - kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), + kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), - kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), + kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), - kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), + kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), - kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), + kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), - kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), + kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), - kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), + kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), - kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), + kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), - kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), + kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), - kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), + kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), - kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), + kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), - kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0), - kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1), + kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0), + kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1), kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2), - kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3), - kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4), - kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7), + kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3), + kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4), + kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7), - kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0), - kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1), + kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0), + kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1), kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2), - kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3), - kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4), - kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7), + kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3), + kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4), + kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7), - kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), + kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), - kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), + kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), - kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), - kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), - kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), - kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), + kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), + kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), + kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), + kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), - kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), + kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1), - kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), - kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), - kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), + kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), + kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), + kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), - kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), - kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), - kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), + kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), + kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), + kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), - kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), + kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), - kMCLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), - kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), - kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2), - kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), + kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), + kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), + kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2), + kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4), - kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), - - kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0), + kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), + + kMAIN_CLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0), kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1), - kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2), - kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3), - - kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), - kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), - kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2), + kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2), + kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3), + + kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), + kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), + kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2), kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3), - kNONE_to_NONE = 0x80000000U, + kNONE_to_NONE = (int)0x80000000U, } clock_attach_id_t; /* Clock dividers */ typedef enum _clock_div_name { - kCLOCK_DivSystickClk = 0, - kCLOCK_DivArmTrClkDiv = 1, - kCLOCK_DivCan0Clk = 2, - kCLOCK_DivCan1Clk = 3, + kCLOCK_DivSystickClk = 0, + kCLOCK_DivArmTrClkDiv = 1, + kCLOCK_DivCan0Clk = 2, + kCLOCK_DivCan1Clk = 3, kCLOCK_DivSmartCard0Clk = 4, kCLOCK_DivSmartCard1Clk = 5, - kCLOCK_DivAhbClk = 32, - kCLOCK_DivClkOut = 33, - kCLOCK_DivFrohfClk = 34, - kCLOCK_DivSpifiClk = 36, - kCLOCK_DivAdcAsyncClk = 37, - kCLOCK_DivUsb0Clk = 38, - kCLOCK_DivUsb1Clk = 39, - kCLOCK_DivFrg = 40, - kCLOCK_DivDmicClk = 42, - kCLOCK_DivMClk = 43, - kCLOCK_DivLcdClk = 44, - kCLOCK_DivSctClk = 45, - kCLOCK_DivEmcClk = 46, - kCLOCK_DivSdioClk = 47 + kCLOCK_DivAhbClk = 32, + kCLOCK_DivClkOut = 33, + kCLOCK_DivFrohfClk = 34, + kCLOCK_DivSpifiClk = 36, + kCLOCK_DivAdcAsyncClk = 37, + kCLOCK_DivUsb0Clk = 38, + kCLOCK_DivUsb1Clk = 39, + kCLOCK_DivFrg = 40, + kCLOCK_DivDmicClk = 42, + kCLOCK_DivMClk = 43, + kCLOCK_DivLcdClk = 44, + kCLOCK_DivSctClk = 45, + kCLOCK_DivEmcClk = 46, + kCLOCK_DivSdioClk = 47 } clock_div_name_t; /******************************************************************************* @@ -735,7 +726,7 @@ static inline void CLOCK_EnableClock(clock_ip_name_t clk) } else { - SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1); + SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1); ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); } } @@ -750,8 +741,7 @@ static inline void CLOCK_DisableClock(clock_ip_name_t clk) else { ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); - SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0); - + SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0); } } /** @@ -799,6 +789,14 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq); * @return Nothing */ void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); /** * @brief Setup peripheral clock dividers. * @param div_name : Clock divider name @@ -813,6 +811,20 @@ void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool * @return Nothing */ void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq); + +/** + * @brief Set the frg output frequency. + * @param freq : output frequency + * @return 0 : the frequency range is out of range. + * 1 : switch successfully. + */ +uint32_t CLOCK_SetFRGClock(uint32_t freq); + +/*! @brief Return Frequency of FRG input clock + * @return Frequency value + */ +uint32_t CLOCK_GetFRGInputClock(void); + /*! @brief Return Frequency of selected clock * @return Frequency of selected clock */ @@ -833,6 +845,11 @@ uint32_t CLOCK_GetSpifiClkFreq(void); * @return Frequency of Adc Clock. */ uint32_t CLOCK_GetAdcClkFreq(void); +/*! brief Return Frequency of MCAN Clock + * param MCanSel : 0U: MCAN0; 1U: MCAN1 + * return Frequency of MCAN Clock + */ +uint32_t CLOCK_GetMCanClkFreq(uint32_t MCanSel); /*! @brief Return Frequency of Usb0 Clock * @return Frequency of Usb0 Clock. */ @@ -873,6 +890,14 @@ uint32_t CLOCK_GetWdtOscFreq(void); * @return Frequency of High-Freq output of FRO */ uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of frg + * @return Frequency of FRG + */ +uint32_t CLOCK_GetFrgClkFreq(void); +/*! @brief Return Frequency of dmic + * @return Frequency of DMIC + */ +uint32_t CLOCK_GetDmicClkFreq(void); /*! @brief Return Frequency of PLL * @return Frequency of PLL */ @@ -912,6 +937,13 @@ __STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void) * @return Frequency of Asynchronous APB Clock Clock */ uint32_t CLOCK_GetAsyncApbClkFreq(void); +/*! @brief Return EMC source + * @return EMC source + */ +__STATIC_INLINE uint32_t CLOCK_GetEmcClkFreq(void) +{ + return CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U) / ((SYSCON->EMCCLKDIV & 0xffU) + 1U); +} /*! @brief Return Audio PLL input clock rate * @return Audio PLL input clock rate */ @@ -946,7 +978,7 @@ uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute); * the rate computation function can take some time to perform. It * is recommended to use 'false' with the 'recompute' parameter. */ -uint32_t CLOCK_GetUSbPLLOutClockRate(bool recompute); +uint32_t CLOCK_GetUsbPLLOutClockRate(bool recompute); /*! @brief Enables and disables PLL bypass mode * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass @@ -990,20 +1022,19 @@ __STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void) /*! @brief Enables and disables SYS OSC * @brief enable : true to enable SYS OSC, false to disable SYS OSC -*/ -__STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable) + */ +__STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable) { - if(enable) + if (enable) { SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK; SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK; } - + else { - SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK; + SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK; SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK; - } } @@ -1035,12 +1066,13 @@ void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate); */ #define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ #define PLL_CONFIGFLAG_FORCENOFRACT \ - (1 \ - << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \ - \ \ \ \ - \ \ \ \ \ \ - \ \ \ \ \ \ \ \ - hardware */ + (1 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ + \ \ \ + \ \ \ \ \ + \ \ \ \ \ \ \ + \ \ \ \ \ \ \ \ \ + \ \ \ \ \ \ \ \ \ \ \ + hardware */ /*! @brief PLL configuration structure * @@ -1056,53 +1088,54 @@ typedef struct _pll_config } pll_config_t; /*! @brief PLL setup structure flags for 'flags' field -* These flags control how the PLL setup function sets up the PLL -*/ + * These flags control how the PLL setup function sets up the PLL + */ #define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ #define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ #define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ /*! @brief PLL setup structure -* This structure can be used to pre-build a PLL setup configuration -* at run-time and quickly set the PLL to the configuration. It can be -* populated with the PLL setup function. If powering up or waiting -* for PLL lock, the PLL input clock source should be configured prior -* to PLL setup. -*/ + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ typedef struct _pll_setup { - uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */ - uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */ - uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */ - uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */ - uint32_t pllRate; /*!< Acutal PLL rate */ - uint32_t audpllfrac; /*!< only aduio PLL has this function*/ - uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ + uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */ + uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */ + uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */ + uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */ + uint32_t pllRate; /*!< Acutal PLL rate */ + uint32_t audpllfrac; /*!< only aduio PLL has this function*/ + uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */ } pll_setup_t; /*! @brief PLL status definitions */ typedef enum _pll_error { - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */ - kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ - kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */ + kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */ } pll_error_t; /*! @brief USB clock source definition. */ typedef enum _clock_usb_src { - kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */ + kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */ kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */ kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ - kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */ + kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */ - kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(7) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */ + kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL( + 7) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */ } clock_usb_src_t; /*! @brief USB PDEL Divider. */ @@ -1112,24 +1145,24 @@ typedef enum _usb_pll_psel pSel_Divide_2, pSel_Divide_4, pSel_Divide_8 -}usb_pll_psel; +} usb_pll_psel; /*! @brief PLL setup structure -* This structure can be used to pre-build a USB PLL setup configuration -* at run-time and quickly set the usb PLL to the configuration. It can be -* populated with the USB PLL setup function. If powering up or waiting -* for USB PLL lock, the PLL input clock source should be configured prior -* to USB PLL setup. -*/ + * This structure can be used to pre-build a USB PLL setup configuration + * at run-time and quickly set the usb PLL to the configuration. It can be + * populated with the USB PLL setup function. If powering up or waiting + * for USB PLL lock, the PLL input clock source should be configured prior + * to USB PLL setup. + */ typedef struct _usb_pll_setup { - uint8_t msel; /*!< USB PLL control register msel:1U-256U */ - uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */ - uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */ - bool direct; /*!< USB PLL CCO output control */ - bool bypass; /*!< USB PLL inout clock bypass control */ - bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/ - uint32_t inputRate; /*!< USB PLL input rate */ + uint8_t msel; /*!< USB PLL control register msel:1U-256U */ + uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */ + uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */ + bool direct; /*!< USB PLL CCO output control */ + bool bypass; /*!< USB PLL inout clock bypass control */ + bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/ + uint32_t inputRate; /*!< USB PLL input rate */ } usb_pll_setup_t; /*! @brief Return System PLL output clock rate from setup structure @@ -1156,6 +1189,11 @@ uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup); */ uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup); +/*! @brief Set USB PLL output frequency + * @param rate : frequency value + * + */ +void CLOCK_SetStoredUsbPLLClockRate(uint32_t rate); /*! @brief Set PLL output based on the passed PLL setup data * @param pControl : Pointer to populated PLL control structure to generate setup with * @param pSetup : Pointer to PLL setup structure to be filled @@ -1176,7 +1214,7 @@ pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup) /*! @brief Set PLL output from PLL setup structure (precise frequency) * @param pSetup : Pointer to populated PLL setup structure -* @param flagcfg : Flag configuration for PLL config structure + * @param flagcfg : Flag configuration for PLL config structure * @return PLL_ERROR_SUCCESS on success, or PLL setup error code * @note This function will power off the PLL, setup the PLL with the * new setup data, and then optionally powerup the PLL, wait for PLL lock, @@ -1188,7 +1226,7 @@ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); /*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency) * @param pSetup : Pointer to populated PLL setup structure -* @param flagcfg : Flag configuration for PLL config structure + * @param flagcfg : Flag configuration for PLL config structure * @return PLL_ERROR_SUCCESS on success, or PLL setup error code * @note This function will power off the PLL, setup the PLL with the * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock, @@ -1198,9 +1236,10 @@ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); */ pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg); -/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise frequency) +/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise + * frequency) * @param pSetup : Pointer to populated PLL setup structure -* @param flagcfg : Flag configuration for PLL config structure + * @param flagcfg : Flag configuration for PLL config structure * @return PLL_ERROR_SUCCESS on success, or PLL setup error code * @note This function will power off the PLL, setup the PLL with the * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock, @@ -1296,6 +1335,16 @@ bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq); */ bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq); +/*! + * @brief Use DWT to delay at least for some time. + * Please note that, this API will calculate the microsecond period with the maximum + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * @param delay_us Delay time in unit of microsecond. + */ +void SDK_DelayAtLeastUs(uint32_t delay_us); + #if defined(__cplusplus) } #endif /* __cplusplus */ From dc5ff9ecd644c17425f1f501b4c0fbdfba00c19f Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 21 Jun 2019 11:08:19 -0500 Subject: [PATCH 23/37] LPC54114: Update the ADC SDK driver Signed-off-by: Mahesh Mahadevan --- .../LPC54114_cm4_features.h | 181 +++- .../TARGET_LPC54114/drivers/fsl_adc.c | 314 +++++-- .../TARGET_LPC54114/drivers/fsl_adc.h | 236 +++-- .../TARGET_LPC54114/drivers/fsl_clock.c | 811 ++++++++++++++---- .../TARGET_LPC54114/drivers/fsl_clock.h | 515 ++++++----- 5 files changed, 1525 insertions(+), 532 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/LPC54114_cm4_features.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/LPC54114_cm4_features.h index b1cf887ac7..42ef5ab1f2 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/LPC54114_cm4_features.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/device/TARGET_LPC54114_M4/LPC54114_cm4_features.h @@ -1,41 +1,19 @@ /* ** ################################################################### ** Version: rev. 1.0, 2016-05-09 -** Build: b160802 +** Build: b190225 ** ** Abstract: ** Chip specific module features. ** -** Copyright (c) 2016 Freescale Semiconductor, Inc. +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2019 NXP ** All rights reserved. ** -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: +** SPDX-License-Identifier: BSD-3-Clause ** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of Freescale Semiconductor, Inc. nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.freescale.com -** mail: support@freescale.com +** http: www.nxp.com +** mail: support@nxp.com ** ** Revisions: ** - rev. 1.0 (2016-05-09) @@ -55,6 +33,8 @@ #define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) /* @brief CRC availability on the SoC. */ #define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) /* @brief DMA availability on the SoC. */ #define FSL_FEATURE_SOC_DMA_COUNT (1) /* @brief DMIC availability on the SoC. */ @@ -89,8 +69,6 @@ #define FSL_FEATURE_SOC_SPIFI_COUNT (1) /* @brief SYSCON availability on the SoC. */ #define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) /* @brief USART availability on the SoC. */ #define FSL_FEATURE_SOC_USART_COUNT (8) /* @brief USB availability on the SoC. */ @@ -100,16 +78,139 @@ /* @brief WWDT availability on the SoC. */ #define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* ADC module features */ + +/* @brief Do not has input select (register INSEL). */ +#define FSL_FEATURE_ADC_HAS_NO_INSEL (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0) +/* @brief Has ASYNMODE bitfile in CTRL reigster. */ +#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0) +/* @brief Has startup register. */ +#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1) +/* @brief Has ADTrim register */ +#define FSL_FEATURE_ADC_HAS_TRIM_REG (0) +/* @brief Has Calibration register. */ +#define FSL_FEATURE_ADC_HAS_CALIB_REG (1) + /* DMA module features */ /* @brief Number of channels */ #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (20) +/* @brief Align size of DMA descriptor */ +#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) +/* @brief DMA head link descriptor table align size */ +#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) + +/* FLEXCOMM module features */ + +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM7 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (0) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (1) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \ + (((x) == FLEXCOMM0) ? (0) : \ + (((x) == FLEXCOMM1) ? (0) : \ + (((x) == FLEXCOMM2) ? (0) : \ + (((x) == FLEXCOMM3) ? (0) : \ + (((x) == FLEXCOMM4) ? (0) : \ + (((x) == FLEXCOMM5) ? (0) : \ + (((x) == FLEXCOMM6) ? (0) : \ + (((x) == FLEXCOMM7) ? (1) : (-1))))))))) + +/* I2S module features */ + +/* @brief I2S support dual channel transfer */ +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (1) + +/* MAILBOX module features */ + +/* @brief Mailbox side for current core */ +#define FSL_FEATURE_MAILBOX_SIDE_A (1) +/* @brief Mailbox has no reset control */ +#define FSL_FEATURE_MAILBOX_HAS_NO_RESET (1) + +/* MRT module features */ + +/* @brief number of channels. */ +#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4) + +/* interrupt module features */ + +/* @brief Lowest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) +/* @brief Highest interrupt request number. */ +#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105) /* PINT module features */ /* @brief Number of connected outputs */ #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* RTC module features */ + +/* @brief RTC has no reset control */ +#define FSL_FEATURE_RTC_HAS_NO_RESET (1) + /* SCT module features */ /* @brief Number of events */ @@ -118,6 +219,8 @@ #define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) /* @brief Number of match capture */ #define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) +/* @brief Number of outputs */ +#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (8) /* SYSCON module features */ @@ -129,6 +232,24 @@ #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) /* @brief Flash size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144) +/* @brief IAP has Flash read & write function */ +#define FSL_FEATURE_IAP_HAS_FLASH_FUNCTION (1) +/* @brief IAP has read Flash signature function */ +#define FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ (1) +/* @brief IAP has read extended Flash signature function */ +#define FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ (0) + +/* SysTick module features */ + +/* @brief Systick has external reference clock. */ +#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) +/* @brief Systick external reference clock is core clock divided by this value. */ +#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) + +/* USB module features */ + +/* @brief Number of the endpoint in USB FS */ +#define FSL_FEATURE_USB_EP_NUM (5) #endif /* _LPC54114_cm4_FEATURES_H_ */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_adc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_adc.c index 2bdd60d72f..9dda535e6f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_adc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_adc.c @@ -1,45 +1,32 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_adc.h" #include "fsl_clock.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.lpc_adc" +#endif + static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#define FREQUENCY_1MHZ (1000000U) static uint32_t ADC_GetInstance(ADC_Type *base) { uint32_t instance; /* Find the instance index from base address mappings. */ - for (instance = 0; instance < FSL_FEATURE_SOC_ADC_COUNT; instance++) + for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++) { if (s_adcBases[instance] == base) { @@ -47,19 +34,27 @@ static uint32_t ADC_GetInstance(ADC_Type *base) } } - assert(instance < FSL_FEATURE_SOC_ADC_COUNT); + assert(instance < ARRAY_SIZE(s_adcBases)); return instance; } +/*! + * brief Initialize the ADC module. + * + * param base ADC peripheral base address. + * param config Pointer to configuration structure, see to #adc_config_t. + */ void ADC_Init(ADC_Type *base, const adc_config_t *config) { assert(config != NULL); uint32_t tmp32 = 0U; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable clock. */ CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Disable the interrupts. */ base->INTEN = 0U; /* Quickly disable all the interrupts. */ @@ -67,6 +62,7 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config) /* Configure the ADC block. */ tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber); +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE /* Async or Sync clock mode. */ switch (config->clockMode) { @@ -76,84 +72,236 @@ void ADC_Init(ADC_Type *base, const adc_config_t *config) default: /* kADC_ClockSynchronousMode */ break; } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL /* Resolution. */ - tmp32 |= ADC_CTRL_RESOL(config->resolution); + tmp32 |= ADC_CTRL_RESOL(config->resolution); +#endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL /* Bypass calibration. */ if (config->enableBypassCalibration) { tmp32 |= ADC_CTRL_BYPASSCAL_MASK; } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ - /* Sample time clock count. */ - tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber); +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP +/* Sample time clock count. */ +#if (defined(FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL) && FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL) + if (config->clockMode == kADC_ClockAsynchronousMode) + { +#endif /* FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL */ + tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber); +#if (defined(FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL) && FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL) + } +#endif /* FSL_FEATURE_ADC_SYNCHRONOUS_USE_GPADC_CTRL */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + if (config->enableLowPowerMode) + { + tmp32 |= ADC_CTRL_LPWRMODE_MASK; + } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ base->CTRL = tmp32; + +#if defined(FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN) && FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN + base->GPADC_CTRL0 |= ADC_GPADC_CTRL0_LDO_POWER_EN_MASK; + if (config->clockMode == kADC_ClockSynchronousMode) + { + base->GPADC_CTRL0 |= ADC_GPADC_CTRL0_PASS_ENABLE(config->sampleTimeNumber); + } +#endif /* FSL_FEATURE_ADC_HAS_GPADC_CTRL0_LDO_POWER_EN */ + +#if defined(FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL) && FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL + tmp32 = *(uint32_t *)FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL; + if (tmp32 & FSL_FEATURE_FLASH_ADDR_OF_TEMP_CAL_VALID) + { + base->GPADC_CTRL1 = (tmp32 >> 1); + } +#if !(defined(FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT) && FSL_FEATURE_ADC_HAS_STARTUP_ADC_INIT) + base->STARTUP = ADC_STARTUP_ADC_ENA_MASK; /* Set the ADC Start bit */ +#endif /* FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL */ +#endif /* FSL_FEATURE_ADC_HAS_GPADC_CTRL1_OFFSET_CAL */ + +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + base->TRM &= ~ADC_TRM_VRANGE_MASK; + base->TRM |= ADC_TRM_VRANGE(config->voltageRange); +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ } +/*! + * brief Gets an available pre-defined settings for initial configuration. + * + * This function initializes the initial configuration structure with an available settings. The default values are: + * code + * config->clockMode = kADC_ClockSynchronousMode; + * config->clockDividerNumber = 0U; + * config->resolution = kADC_Resolution12bit; + * config->enableBypassCalibration = false; + * config->sampleTimeNumber = 0U; + * endcode + * param config Pointer to configuration structure. + */ void ADC_GetDefaultConfig(adc_config_t *config) { + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + config->clockMode = kADC_ClockSynchronousMode; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ + config->clockDividerNumber = 0U; +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL config->resolution = kADC_Resolution12bit; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL config->enableBypassCalibration = false; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP config->sampleTimeNumber = 0U; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + config->enableLowPowerMode = false; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + config->voltageRange = kADC_HighVoltageRange; +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ } +/*! + * brief Deinitialize the ADC module. + * + * param base ADC peripheral base address. + */ void ADC_Deinit(ADC_Type *base) { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disable the clock. */ CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } +#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) +#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) & FSL_FEATURE_ADC_HAS_CALIB_REG +/*! + * brief Do the self calibration. To calibrate the ADC, set the ADC clock to 1 mHz. + * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, + * following every chip reset before initiating normal ADC operation. + * + * param base ADC peripheral base address. + * retval true Calibration succeed. + * retval false Calibration failed. + */ bool ADC_DoSelfCalibration(ADC_Type *base) { - uint32_t i; + uint32_t frequency = 0U; + uint32_t delayUs = 0U; /* Enable the converter. */ /* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down. This bit should be set after at least 10 ms after the ADC is powered on. */ base->STARTUP = ADC_STARTUP_ADC_ENA_MASK; - for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */ - { - __ASM("NOP"); - } + SDK_DelayAtLeastUs(1U); if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK)) { return false; /* ADC is not powered up. */ } + /* Get the ADC clock frequency in synchronous mode. */ + frequency = CLOCK_GetFreq(kCLOCK_BusClk) / (((base->CTRL & ADC_CTRL_CLKDIV_MASK) >> ADC_CTRL_CLKDIV_SHIFT) + 1); + base->CTRL |= ADC_CTRL_CLKDIV((frequency / 1000000U) - 1U); + frequency = 1000000U; +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) && FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + /* Get the ADC clock frequency in asynchronous mode. */ + if (ADC_CTRL_ASYNMODE_MASK == (base->CTRL & ADC_CTRL_ASYNMODE_MASK)) + { + frequency = CLOCK_GetAdcClkFreq(); + } +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE */ + assert(0U != frequency); + /* If not in by-pass mode, do the calibration. */ if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) && (0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK))) { + /* A calibration cycle requires approximately 81 ADC clocks to complete. */ + delayUs = (120 * FREQUENCY_1MHZ) / frequency + 1; /* Calibration is needed, do it now. */ base->CALIB = ADC_CALIB_CALIB_MASK; - i = 0xF0000; - while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i)) - { - } - if (i == 0U) + SDK_DelayAtLeastUs(delayUs); + if (ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) { return false; /* Calibration timeout. */ } } - /* A dummy conversion cycle will be performed. */ + /* A “dummy” conversion cycle requires approximately 6 ADC clocks */ + delayUs = (10 * FREQUENCY_1MHZ) / frequency + 1; base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK; - i = 0x7FFFF; - while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i)) - { - } - if (i == 0U) + SDK_DelayAtLeastUs(delayUs); + if (ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) { return false; } return true; } +#else +/*! + * brief Do the self calibration. To calibrate the ADC, set the ADC clock to 1 mHz. + * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, + * following every chip reset before initiating normal ADC operation. + * + * param base ADC peripheral base address. + * param frequency The ststem clock frequency to ADC. + * retval true Calibration succeed. + * retval false Calibration failed. + */ +bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency) +{ + uint32_t tmp32; + /* Store the current contents of the ADC CTRL register. */ + tmp32 = base->CTRL; + + /* Start ADC self-calibration. */ + base->CTRL |= ADC_CTRL_CALMODE_MASK; + + /* Divide the system clock to yield an ADC clock of about 1 mHz. */ + base->CTRL &= ~ADC_CTRL_CLKDIV_MASK; + base->CTRL |= ADC_CTRL_CLKDIV((frequency / 1000000U) - 1U); + + /* Clear the LPWR bit. */ + base->CTRL &= ~ADC_CTRL_LPWRMODE_MASK; + /* Delay for 120 uSec @ 1 mHz ADC clock */ + SDK_DelayAtLeastUs(120U); + + /* Check the completion of calibration. */ + if (ADC_CTRL_CALMODE_MASK == (base->CTRL & ADC_CTRL_CALMODE_MASK)) + { + /* Restore the contents of the ADC CTRL register. */ + base->CTRL = tmp32; + return false; /* Calibration timeout. */ + } + /* Restore the contents of the ADC CTRL register. */ + base->CTRL = tmp32; + + return true; +} +#endif /* FSL_FEATURE_ADC_HAS_CALIB_REG */ +#endif /* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC*/ + +/*! + * brief Configure the conversion sequence A. + * + * param base ADC peripheral base address. + * param config Pointer to configuration structure, see to #adc_conv_seq_config_t. + */ void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config) { assert(config != NULL); @@ -198,6 +346,12 @@ void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config) base->SEQ_CTRL[0] = tmp32; } +/*! + * brief Configure the conversion sequence B. + * + * param base ADC peripheral base address. + * param config Pointer to configuration structure, see to #adc_conv_seq_config_t. + */ void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config) { assert(config != NULL); @@ -242,6 +396,14 @@ void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config) base->SEQ_CTRL[1] = tmp32; } +/*! + * brief Get the global ADC conversion infomation of sequence A. + * + * param base ADC peripheral base address. + * param info Pointer to information structure, see to #adc_result_info_t; + * retval true The conversion result is ready. + * retval false The conversion result is not ready yet. + */ bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) { assert(info != NULL); @@ -259,11 +421,19 @@ bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *in info->thresholdCorssingStatus = (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT); info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT; - info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); + info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); return true; } +/*! + * brief Get the global ADC conversion infomation of sequence B. + * + * param base ADC peripheral base address. + * param info Pointer to information structure, see to #adc_result_info_t; + * retval true The conversion result is ready. + * retval false The conversion result is not ready yet. + */ bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info) { assert(info != NULL); @@ -281,11 +451,20 @@ bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *in info->thresholdCorssingStatus = (adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT); info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT; - info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); + info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK); return true; } +/*! + * brief Get the channel's ADC conversion completed under each conversion sequence. + * + * param base ADC peripheral base address. + * param channel The indicated channel number. + * param info Pointer to information structure, see to #adc_result_info_t; + * retval true The conversion result is ready. + * retval false The conversion result is not ready yet. + */ bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info) { assert(info != NULL); @@ -299,12 +478,51 @@ bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result } info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT; +#if (defined(FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT) && FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT) + switch ((base->CTRL & ADC_CTRL_RESOL_MASK) >> ADC_CTRL_RESOL_SHIFT) + { + case kADC_Resolution10bit: + info->result >>= kADC_Resolution10bitInfoResultShift; + break; + case kADC_Resolution8bit: + info->result >>= kADC_Resolution8bitInfoResultShift; + break; + case kADC_Resolution6bit: + info->result >>= kADC_Resolution6bitInfoResultShift; + break; + default: + break; + } +#endif info->thresholdCompareStatus = (adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT); info->thresholdCorssingStatus = (adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT); info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT; - info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK); + info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK); return true; } +#if defined(FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP) && (FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP) +void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) +{ + if (enable) + { + SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE_MASK; + ASYNC_SYSCON->TEMPSENSORCTRL = kADC_NoOffsetAdded; + ASYNC_SYSCON->TEMPSENSORCTRL |= ASYNC_SYSCON_TEMPSENSORCTRL_ENABLE_MASK; + base->GPADC_CTRL0 |= (kADC_ADCInUnityGainMode | kADC_Impedance87kOhm); + } + else + { + /* if the temperature sensor is not turned on then ASYNCAPBCTRL is likely to be zero + * and accessing the registers will cause a memory access error. Test for this */ + if (SYSCON->ASYNCAPBCTRL == SYSCON_ASYNCAPBCTRL_ENABLE_MASK) + { + ASYNC_SYSCON->TEMPSENSORCTRL = 0x0; + base->GPADC_CTRL0 &= ~(kADC_ADCInUnityGainMode | kADC_Impedance87kOhm); + base->GPADC_CTRL0 |= kADC_Impedance55kOhm; + } + } +} +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_adc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_adc.h index 23dcf68d77..e1679580bd 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_adc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_adc.h @@ -1,31 +1,9 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef __FSL_ADC_H__ @@ -46,25 +24,26 @@ /*! @name Driver version */ /*@{*/ -/*! @brief ADC driver version 1.0.0. */ -#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief ADC driver version 2.3.1. */ +#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*@}*/ /*! * @brief Flags */ + enum _adc_status_flags { - kADC_ThresholdCompareFlagOnChn0 = 1U << 0U, /*!< Threshold comparison event on Channel 0. */ - kADC_ThresholdCompareFlagOnChn1 = 1U << 1U, /*!< Threshold comparison event on Channel 1. */ - kADC_ThresholdCompareFlagOnChn2 = 1U << 2U, /*!< Threshold comparison event on Channel 2. */ - kADC_ThresholdCompareFlagOnChn3 = 1U << 3U, /*!< Threshold comparison event on Channel 3. */ - kADC_ThresholdCompareFlagOnChn4 = 1U << 4U, /*!< Threshold comparison event on Channel 4. */ - kADC_ThresholdCompareFlagOnChn5 = 1U << 5U, /*!< Threshold comparison event on Channel 5. */ - kADC_ThresholdCompareFlagOnChn6 = 1U << 6U, /*!< Threshold comparison event on Channel 6. */ - kADC_ThresholdCompareFlagOnChn7 = 1U << 7U, /*!< Threshold comparison event on Channel 7. */ - kADC_ThresholdCompareFlagOnChn8 = 1U << 8U, /*!< Threshold comparison event on Channel 8. */ - kADC_ThresholdCompareFlagOnChn9 = 1U << 9U, /*!< Threshold comparison event on Channel 9. */ + kADC_ThresholdCompareFlagOnChn0 = 1U << 0U, /*!< Threshold comparison event on Channel 0. */ + kADC_ThresholdCompareFlagOnChn1 = 1U << 1U, /*!< Threshold comparison event on Channel 1. */ + kADC_ThresholdCompareFlagOnChn2 = 1U << 2U, /*!< Threshold comparison event on Channel 2. */ + kADC_ThresholdCompareFlagOnChn3 = 1U << 3U, /*!< Threshold comparison event on Channel 3. */ + kADC_ThresholdCompareFlagOnChn4 = 1U << 4U, /*!< Threshold comparison event on Channel 4. */ + kADC_ThresholdCompareFlagOnChn5 = 1U << 5U, /*!< Threshold comparison event on Channel 5. */ + kADC_ThresholdCompareFlagOnChn6 = 1U << 6U, /*!< Threshold comparison event on Channel 6. */ + kADC_ThresholdCompareFlagOnChn7 = 1U << 7U, /*!< Threshold comparison event on Channel 7. */ + kADC_ThresholdCompareFlagOnChn8 = 1U << 8U, /*!< Threshold comparison event on Channel 8. */ + kADC_ThresholdCompareFlagOnChn9 = 1U << 9U, /*!< Threshold comparison event on Channel 9. */ kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */ kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */ kADC_OverrunFlagForChn0 = @@ -93,10 +72,10 @@ enum _adc_status_flags 1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */ kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */ kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */ - kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */ - kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */ - kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */ - kADC_OverrunInterruptFlag = 1U << 31U, /*!< Overrun interrupt flag. */ + kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */ + kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */ + kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */ + kADC_OverrunInterruptFlag = (int)(1U << 31U), /*!< Overrun interrupt flag. */ }; /*! @@ -110,10 +89,11 @@ enum _adc_interrupt_enable kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual conversion in sequence B, or entire sequence. */ kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of - the channel data registers will cause an overrun - interrupt/DMA trigger. */ + the channel data registers will cause an overrun + interrupt/DMA trigger. */ }; +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE /*! * @brief Define selection of clock mode. */ @@ -123,17 +103,44 @@ typedef enum _adc_clock_mode 0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */ kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */ } adc_clock_mode_t; +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ +#if defined(FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT) && (FSL_FEATURE_ADC_DAT_OF_HIGH_ALIGNMENT) /*! * @brief Define selection of resolution. */ typedef enum _adc_resolution { - kADC_Resolution6bit = 0U, /*!< 6-bit resolution. */ - kADC_Resolution8bit = 1U, /*!< 8-bit resolution. */ + kADC_Resolution6bit = 3U, + /*!< 6-bit resolution. */ /* This is a HW issue that the ADC resolution enum configure not align with HW implement, + ES2 chip already fixed the issue, Currently, update ADC enum define as a workaround */ + kADC_Resolution8bit = 2U, /*!< 8-bit resolution. */ + kADC_Resolution10bit = 1U, /*!< 10-bit resolution. */ + kADC_Resolution12bit = 0U, /*!< 12-bit resolution. */ +} adc_resolution_t; +#elif defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL +/*! + * @brief Define selection of resolution. + */ +typedef enum _adc_resolution +{ + kADC_Resolution6bit = 0U, /*!< 6-bit resolution. */ + kADC_Resolution8bit = 1U, /*!< 8-bit resolution. */ kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */ kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */ } adc_resolution_t; +#endif + +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG +/*! + * @brief Definfe range of the analog supply voltage VDDA. + */ +typedef enum _adc_voltage_range +{ + kADC_HighVoltageRange = 0U, /* High voltage. VDD = 2.7 V to 3.6 V. */ + kADC_LowVoltageRange = 1U, /* Low voltage. VDD = 2.4 V to 2.7 V. */ +} adc_vdda_range_t; +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ /*! * @brief Define selection of polarity of selected input trigger for conversion sequence. @@ -149,8 +156,8 @@ typedef enum _adc_trigger_polarity */ typedef enum _adc_priority { - kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */ - kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when is is started. */ + kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */ + kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when it is started. */ } adc_priority_t; /*! @@ -169,7 +176,7 @@ typedef enum _adc_seq_interrupt_mode */ typedef enum _adc_threshold_compare_status { - kADC_ThresholdCompareInRange = 0U, /*!< LOW threshold <= conversion value <= HIGH threshold. */ + kADC_ThresholdCompareInRange = 0U, /*!< LOW threshold <= conversion value <= HIGH threshold. */ kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */ kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */ } adc_threshold_compare_status_t; @@ -199,27 +206,84 @@ typedef enum _adc_threshold_crossing_status */ typedef enum _adc_threshold_interrupt_mode { - kADC_ThresholdInterruptDisabled = 0U, /*!< Threshold comparison interrupt is disabled. */ - kADC_ThresholdInterruptOnOutside = 1U, /*!< Threshold comparison interrupt is enabled on outside threshold. */ + kADC_ThresholdInterruptDisabled = 0U, /*!< Threshold comparison interrupt is disabled. */ + kADC_ThresholdInterruptOnOutside = 1U, /*!< Threshold comparison interrupt is enabled on outside threshold. */ kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */ } adc_threshold_interrupt_mode_t; +/*! + * @brief Define the info result mode of different resolution. + */ +typedef enum _adc_inforesultshift +{ + kADC_Resolution12bitInfoResultShift = 0U, /*!< Info result shift of Resolution12bit. */ + kADC_Resolution10bitInfoResultShift = 2U, /*!< Info result shift of Resolution10bit. */ + kADC_Resolution8bitInfoResultShift = 4U, /*!< Info result shift of Resolution8bit. */ + kADC_Resolution6bitInfoResultShift = 6U, /*!< Info result shift of Resolution6bit. */ +} adc_inforesult_t; + +/*! + * @brief Define common modes for Temerature sensor. + */ +typedef enum _adc_tempsensor_common_mode +{ + kADC_HighNegativeOffsetAdded = 0x0U, /*!< Temerature sensor common mode: high negative offset added. */ + kADC_IntermediateNegativeOffsetAdded = + 0x4U, /*!< Temerature sensor common mode: intermediate negative offset added. */ + kADC_NoOffsetAdded = 0x8U, /*!< Temerature sensor common mode: no offset added. */ + kADC_LowPositiveOffsetAdded = 0xcU, /*!< Temerature sensor common mode: low positive offset added. */ +} adc_tempsensor_common_mode_t; + +/*! + * @brief Define source impedance modes for GPADC control. + */ +typedef enum _adc_second_control +{ + kADC_Impedance621Ohm = 0x1U << 9U, /*!< Extand ADC sampling time according to source impedance 1: 0.621 kOhm. */ + kADC_Impedance55kOhm = + 0x14U << 9U, /*!< Extand ADC sampling time according to source impedance 20 (default): 55 kOhm. */ + kADC_Impedance87kOhm = 0x1fU << 9U, /*!< Extand ADC sampling time according to source impedance 31: 87 kOhm. */ + + kADC_NormalFunctionalMode = 0x0U << 14U, /*!< TEST mode: Normal functional mode. */ + kADC_MultiplexeTestMode = 0x1U << 14U, /*!< TEST mode: Multiplexer test mode. */ + kADC_ADCInUnityGainMode = 0x2U << 14U, /*!< TEST mode: ADC in unity gain mode. */ +} adc_second_control_t; + /*! * @brief Define structure for configuring the block. */ typedef struct _adc_config { - adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */ - uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode" - field. The divider would be plused by 1 based on the value in this field. The - available range is in 8 bits. */ - adc_resolution_t resolution; /*!< Select the conversion bits. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE) & FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE + adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE. */ + uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode" + field. The divider would be plused by 1 based on the value in this field. The + available range is in 8 bits. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_RESOL) & FSL_FEATURE_ADC_HAS_CTRL_RESOL + adc_resolution_t resolution; /*!< Select the conversion bits. */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_RESOL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL) & FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is powered-up. Re-calibration may be warranted periodically - especially if operating conditions have changed. To enable this option would avoid the need to calibrate if offset error is not a concern in the application. */ - uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then, - to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_TSAMP) & FSL_FEATURE_ADC_HAS_CTRL_TSAMP + uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then, + to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_TSAMP. */ +#if defined(FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE) & FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE + bool enableLowPowerMode; /*!< If disable low-power mode, ADC remains activated even when no conversions are + requested. + If enable low-power mode, The ADC is automatically powered-down when no conversions are + taking place. */ +#endif /* FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE. */ +#if defined(FSL_FEATURE_ADC_HAS_TRIM_REG) & FSL_FEATURE_ADC_HAS_TRIM_REG + adc_vdda_range_t + voltageRange; /*!< Configure the ADC for the appropriate operating range of the analog supply voltage VDDA. + Failure to set the area correctly causes the ADC to return incorrect conversion results. */ +#endif /* FSL_FEATURE_ADC_HAS_TRIM_REG. */ } adc_config_t; /*! @@ -228,17 +292,17 @@ typedef struct _adc_config typedef struct _adc_conv_seq_config { uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this - sequence is launched. The masked channels would be involved in current conversion - sequence, beginning with the lowest-order. The available range is in 12-bit. */ + sequence is launched. The masked channels would be involved in current conversion + sequence, beginning with the lowest-order. The available range is in 12-bit. */ uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this - conversion sequence to be initiated. The available range is 6-bit.*/ + conversion sequence to be initiated. The available range is 6-bit.*/ adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */ bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization - flip-flop stages and therefore shorten the time between the trigger input signal and the - start of a conversion. */ + flip-flop stages and therefore shorten the time between the trigger input signal and the + start of a conversion. */ bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next - channel in the sequence instead of the default response of launching an entire sequence - of conversions. */ + channel in the sequence instead of the default response of launching an entire sequence + of conversions. */ adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */ } adc_conv_seq_config_t; @@ -247,7 +311,7 @@ typedef struct _adc_conv_seq_config */ typedef struct _adc_result_info { - uint32_t result; /*!< Keey the conversion data value. */ + uint32_t result; /*!< Keep the conversion data value. */ adc_threshold_compare_status_t thresholdCompareStatus; /*!< Keep the threshold compare status. */ adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */ uint32_t channelNumber; /*!< Keep the channel number for this conversion. */ @@ -298,6 +362,8 @@ void ADC_Deinit(ADC_Type *base); */ void ADC_GetDefaultConfig(adc_config_t *config); +#if !(defined(FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) && FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC) +#if defined(FSL_FEATURE_ADC_HAS_CALIB_REG) && FSL_FEATURE_ADC_HAS_CALIB_REG /*! * @brief Do the self hardware calibration. * @@ -306,7 +372,22 @@ void ADC_GetDefaultConfig(adc_config_t *config); * @retval false Calibration failed. */ bool ADC_DoSelfCalibration(ADC_Type *base); +#else +/*! + * @brief Do the self calibration. To calibrate the ADC, set the ADC clock to 500 kHz. + * In order to achieve the specified ADC accuracy, the A/D converter must be recalibrated, at a minimum, + * following every chip reset before initiating normal ADC operation. + * + * @param base ADC peripheral base address. + * @param frequency The ststem clock frequency to ADC. + * @retval true Calibration succeed. + * @retval false Calibration failed. + */ +bool ADC_DoSelfCalibration(ADC_Type *base, uint32_t frequency); +#endif /* FSL_FEATURE_ADC_HAS_CALIB_REG */ +#endif /* FSL_FEATURE_ADC_HAS_NO_CALIB_FUNC */ +#if !(defined(FSL_FEATURE_ADC_HAS_NO_INSEL) && FSL_FEATURE_ADC_HAS_NO_INSEL) /*! * @brief Enable the internal temperature sensor measurement. * @@ -316,6 +397,9 @@ bool ADC_DoSelfCalibration(ADC_Type *base); * @param base ADC peripheral base address. * @param enable Switcher to enable the feature or not. */ +#if defined(FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP) && (FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP) +void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable); +#else static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) { if (enable) @@ -327,8 +411,9 @@ static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable) base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0); } } - -/* @} */ +#endif /* FSL_FEATURE_ADC_ASYNC_SYSCON_TEMP. */ +#endif /* FSL_FEATURE_ADC_HAS_NO_INSEL. */ + /* @} */ /*! * @name Control conversion sequence A. @@ -542,7 +627,7 @@ bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result */ static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue) { - base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue); + base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue); base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue); } @@ -555,7 +640,7 @@ static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint */ static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue) { - base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue); + base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue); base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue); } @@ -611,13 +696,24 @@ static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask) } /*! - * @brief Enable the interrupt of shreshold compare event for each channel. + * @brief Enable the interrupt of threshold compare event for each channel. + * @deprecated Do not use this function. It has been superceded by @ADC_EnableThresholdCompareInterrupt + */ +static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base, + uint32_t channel, + adc_threshold_interrupt_mode_t mode) +{ + base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U)); +} + +/*! + * @brief Enable the interrupt of threshold compare event for each channel. * * @param base ADC peripheral base address. * @param channel Channel number. * @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t. */ -static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base, +static inline void ADC_EnableThresholdCompareInterrupt(ADC_Type *base, uint32_t channel, adc_threshold_interrupt_mode_t mode) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_clock.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_clock.c index 84398ccbab..d00bc2a1f9 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_clock.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_clock.c @@ -1,39 +1,21 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2019 , NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ -#include "fsl_common.h" #include "fsl_clock.h" #include "fsl_power.h" /******************************************************************************* * Definitions ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif #define NVALMAX (0x100U) #define PVALMAX (0x20U) #define MVALMAX (0x8000U) @@ -51,7 +33,7 @@ #define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ #define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P) #define PLL_PDEC_VAL_P (0U) /* PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x3FFUL << PLL_PDEC_VAL_P) +#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P) #define PLL_MIN_CCO_FREQ_MHZ (75000000U) #define PLL_MAX_CCO_FREQ_MHZ (150000000U) @@ -85,12 +67,13 @@ computation on each call to retrive the PLL rate. */ static uint32_t s_Pll_Freq; -uint32_t g_I2S_Mclk_Freq = 0U; +/* I2S mclk. */ +static uint32_t s_I2S_Mclk_Freq = 0U; /** External clock rate on the CLKIN pin in Hz. If not used, set this to 0. Otherwise, set it to the exact rate in Hz this pin is being driven at. */ -const uint32_t g_Ext_Clk_Freq = 0U; +static const uint32_t s_Ext_Clk_Freq = 0U; /******************************************************************************* * Variables @@ -133,39 +116,106 @@ static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30 * Code ******************************************************************************/ +/** + * brief Configure the clock selection muxes. + * param connection : Clock to be configured. + * return Nothing + */ void CLOCK_AttachClk(clock_attach_id_t connection) { - bool final_descriptor = false; uint8_t mux; - uint8_t pos; + uint8_t sel; + uint16_t item; + uint32_t tmp32 = (uint32_t)connection; uint32_t i; volatile uint32_t *pClkSel; pClkSel = &(SYSCON->MAINCLKSELA); - for (i = 0U; (i <= 2U) && (!final_descriptor); i++) + if (kNONE_to_NONE != connection) { - connection = (clock_attach_id_t)(connection >> (i * 12U)); /* pick up next descriptor */ - mux = (uint8_t)connection; - if (connection) + for (i = 0U; i < 2U; i++) { - pos = ((connection & 0xf00U) >> 8U) - 1U; - if (mux == CM_ASYNCAPB) + if (tmp32 == 0U) { - ASYNC_SYSCON->ASYNCAPBCLKSELA = pos; + break; } - else + item = (uint16_t)GET_ID_ITEM(tmp32); + if (item) { - pClkSel[mux] = pos; + mux = GET_ID_ITEM_MUX(item); + sel = GET_ID_ITEM_SEL(item); + if (mux == CM_ASYNCAPB) + { + ASYNC_SYSCON->ASYNCAPBCLKSELA = sel; + } + else + { + pClkSel[mux] = sel; + } } - } - else - { - final_descriptor = true; + tmp32 = GET_ID_NEXT_ITEM(tmp32); /* pick up next descriptor */ } } } +/* Return the actual clock attach id */ +/** + * brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * param attachId : Clock attach id to get. + * return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) +{ + uint8_t mux; + uint8_t actualSel; + uint32_t tmp32 = (uint32_t)attachId; + uint32_t i; + uint32_t actualAttachId = 0U; + uint32_t selector = GET_ID_SELECTOR(tmp32); + volatile uint32_t *pClkSel; + + pClkSel = &(SYSCON->MAINCLKSELA); + + if (kNONE_to_NONE == attachId) + { + return kNONE_to_NONE; + } + + for (i = 0U; i < 2U; i++) + { + mux = GET_ID_ITEM_MUX(tmp32); + if (tmp32) + { + if (mux == CM_ASYNCAPB) + { + actualSel = ASYNC_SYSCON->ASYNCAPBCLKSELA; + } + else + { + actualSel = pClkSel[mux]; + } + + /* Consider the combination of two registers */ + actualAttachId |= CLK_ATTACH_ID(mux, actualSel, i); + } + tmp32 = GET_ID_NEXT_ITEM(tmp32); /*!< pick up next descriptor */ + } + + actualAttachId |= selector; + + return (clock_attach_id_t)actualAttachId; +} + +/** + * brief Setup peripheral clock dividers. + * param div_name : Clock divider name + * param divided_by_value: Value to be divided + * param reset : Whether to reset the divider counter. + * return Nothing + */ void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset) { volatile uint32_t *pClkDiv; @@ -186,6 +236,13 @@ void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool } /* Set FRO Clocking */ +/** + * brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). + * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is + * enabled. + * param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) + * return returns success or fail status. + */ status_t CLOCK_SetupFROClocking(uint32_t iFreq) { uint32_t usb_adj; @@ -220,19 +277,28 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq) return 0U; } +/*! brief Return Frequency of FRO 12MHz + * return Frequency of FRO 12MHz + */ uint32_t CLOCK_GetFro12MFreq(void) { return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0U : 12000000U; } +/*! brief Return Frequency of External Clock + * return Frequency of External Clock. If no external clock is used returns 0. + */ uint32_t CLOCK_GetExtClkFreq(void) { - return (g_Ext_Clk_Freq); + return (s_Ext_Clk_Freq); } +/*! brief Return Frequency of Watchdog Oscillator + * return Frequency of Watchdog Oscillator + */ uint32_t CLOCK_GetWdtOscFreq(void) { uint8_t freq_sel, div_sel; - if (SYSCON->PDRUNCFG[kPDRUNCFG_PD_WDT_OSC >> 8UL] & (1UL << (kPDRUNCFG_PD_WDT_OSC & 0xffU)) ) + if (SYSCON->PDRUNCFG[kPDRUNCFG_PD_WDT_OSC >> 8UL] & (1UL << (kPDRUNCFG_PD_WDT_OSC & 0xffU))) { return 0U; } @@ -245,41 +311,97 @@ uint32_t CLOCK_GetWdtOscFreq(void) } } +/* Get HF FRO Clk */ +/*! brief Return Frequency of High-Freq output of FRO + * return Frequency of High-Freq output of FRO + */ uint32_t CLOCK_GetFroHfFreq(void) { - return (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) ? 0 : !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK) ? - 0 : - (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) ? 96000000U : - 48000000U; + if ((SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_FRO_MASK) || !(SYSCON->FROCTRL & SYSCON_FROCTRL_HSPDCLK_MASK)) + { + return 0U; + } + + if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) + { + return 96000000U; + } + else + { + return 48000000U; + } } +/*! brief Return Frequency of PLL + * return Frequency of PLL + */ uint32_t CLOCK_GetPllOutFreq(void) { return s_Pll_Freq; } +/*! brief Return Frequency of 32kHz osc + * return Frequency of 32kHz osc + */ uint32_t CLOCK_GetOsc32KFreq(void) { return CLK_RTC_32K_CLK; /* Needs to be corrected to check that RTC Clock is enabled */ } +/*! brief Return Frequency of Core System + * return Frequency of Core System + */ uint32_t CLOCK_GetCoreSysClkFreq(void) { - return ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 0U)) ? - CLOCK_GetFro12MFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 1U)) ? - CLOCK_GetExtClkFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 2U)) ? - CLOCK_GetWdtOscFreq() : - ((SYSCON->MAINCLKSELB == 0U) && (SYSCON->MAINCLKSELA == 3U)) ? - CLOCK_GetFroHfFreq() : - (SYSCON->MAINCLKSELB == 2U) ? CLOCK_GetPllOutFreq() : - (SYSCON->MAINCLKSELB == 3U) ? CLOCK_GetOsc32KFreq() : 0U; + uint32_t freq = 0U; + + switch (SYSCON->MAINCLKSELB) + { + case 0U: + if (SYSCON->MAINCLKSELA == 0U) + { + freq = CLOCK_GetFro12MFreq(); + } + else if (SYSCON->MAINCLKSELA == 1U) + { + freq = CLOCK_GetExtClkFreq(); + } + else if (SYSCON->MAINCLKSELA == 2U) + { + freq = CLOCK_GetWdtOscFreq(); + } + else if (SYSCON->MAINCLKSELA == 3U) + { + freq = CLOCK_GetFroHfFreq(); + } + else + { + } + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + + case 3U: + freq = CLOCK_GetOsc32KFreq(); + break; + + default: + break; + } + + return freq; } +/*! brief Return Frequency of I2S MCLK Clock + * return Frequency of I2S MCLK Clock + */ uint32_t CLOCK_GetI2SMClkFreq(void) { - return g_I2S_Mclk_Freq; + return s_I2S_Mclk_Freq; } +/*! brief Return Frequency of Asynchronous APB Clock + * return Frequency of Asynchronous APB Clock Clock + */ uint32_t CLOCK_GetAsyncApbClkFreq(void) { async_clock_src_t clkSrc; @@ -303,26 +425,138 @@ uint32_t CLOCK_GetAsyncApbClkFreq(void) return clkRate; } +/* Get FLEXCOMM Clk */ +/*! brief Return Frequency of Flexcomm functional Clock + * return Frequency of Flexcomm functional Clock + */ uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) { - return (SYSCON->FXCOMCLKSEL[id] == 0U) ? CLOCK_GetFro12MFreq() : (SYSCON->FXCOMCLKSEL[id] == 1U) ? - CLOCK_GetFroHfFreq() : - (SYSCON->FXCOMCLKSEL[id] == 2U) ? - CLOCK_GetPllOutFreq() : - (SYSCON->FXCOMCLKSEL[id] == 3U) ? - CLOCK_GetI2SMClkFreq() : - (SYSCON->FXCOMCLKSEL[id] == 4U) ? CLOCK_GetFreq(kCLOCK_Frg) : 0U; + uint32_t freq = 0U; + + switch (SYSCON->FXCOMCLKSEL[id]) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 4U: + freq = CLOCK_GetFrgClkFreq(); + break; + + default: + break; + } + + return freq; } +/* Get ADC Clk */ +/*! brief Return Frequency of Adc Clock + * return Frequency of Adc Clock. + */ +uint32_t CLOCK_GetAdcClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->ADCCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetFroHfFreq(); + break; + case 7U: + freq = 0U; + break; + default: + break; + } + + return freq / ((SYSCON->ADCCLKDIV & 0xffU) + 1U); +} + +/* Get FRG Clk */ +/*! brief Return Input frequency for the Fractional baud rate generator + * return Input Frequency for FRG + */ uint32_t CLOCK_GetFRGInputClock(void) { - return (SYSCON->FRGCLKSEL == 0U) ? CLOCK_GetCoreSysClkFreq() : (SYSCON->FRGCLKSEL == 1U) ? - CLOCK_GetPllOutFreq() : - (SYSCON->FRGCLKSEL == 2U) ? CLOCK_GetFro12MFreq() : (SYSCON->FRGCLKSEL == 3U) ? - CLOCK_GetFroHfFreq() : - 0U; + uint32_t freq = 0U; + + switch (SYSCON->FRGCLKSEL) + { + case 0U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 1U: + freq = CLOCK_GetPllOutFreq(); + break; + case 2U: + freq = CLOCK_GetFro12MFreq(); + break; + case 3U: + freq = CLOCK_GetFroHfFreq(); + break; + + default: + break; + } + + return freq; } +/* Get DMIC Clk */ +/*! brief Return Input frequency for the DMIC + * return Input Frequency for DMIC + */ +uint32_t CLOCK_GetDmicClkFreq(void) +{ + uint32_t freq = 0U; + + switch (SYSCON->DMICCLKSEL) + { + case 0U: + freq = CLOCK_GetFro12MFreq(); + break; + case 1U: + freq = CLOCK_GetFroHfFreq(); + break; + case 2U: + freq = CLOCK_GetPllOutFreq(); + break; + case 3U: + freq = CLOCK_GetI2SMClkFreq(); + break; + case 4U: + freq = CLOCK_GetCoreSysClkFreq(); + break; + case 5U: + freq = CLOCK_GetWdtOscFreq(); + break; + default: + break; + } + + return freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U); + ; +} + +/*! brief Set output of the Fractional baud rate generator + * param freq : Desired output frequency + * return Error Code 0 - fail 1 - success + */ uint32_t CLOCK_SetFRGClock(uint32_t freq) { uint32_t input = CLOCK_GetFRGInputClock(); @@ -335,12 +569,59 @@ uint32_t CLOCK_SetFRGClock(uint32_t freq) } else { - mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); + mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); SYSCON->FRGCTRL = (mul << SYSCON_FRGCTRL_MULT_SHIFT) | SYSCON_FRGCTRL_DIV_MASK; return 1; } } +/* Get FRG Clk */ +/*! brief Return Input frequency for the FRG + * return Input Frequency for FRG + */ +uint32_t CLOCK_GetFrgClkFreq(void) +{ + uint32_t freq = 0U; + + if ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) + { + freq = ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) / + ((SYSCON_FRGCTRL_DIV_MASK + 1) + + ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)); + } + else + { + freq = 0U; + } + + return freq; +} + +/*! brief Return Frequency of USB + * return Frequency of USB + */ +uint32_t CLOCK_GetUsbClkFreq(void) +{ + uint32_t freq = 0U; + + if (SYSCON->USBCLKSEL == 0U) + { + freq = CLOCK_GetFroHfFreq(); + } + else if (SYSCON->USBCLKSEL == 1) + { + freq = CLOCK_GetPllOutFreq(); + } + else + { + } + + return freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U); +} + +/*! brief Return Frequency of selected clock + * return Frequency of selected clock + */ uint32_t CLOCK_GetFreq(clock_name_t clockName) { uint32_t freq; @@ -362,31 +643,16 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) freq = CLOCK_GetPllOutFreq(); break; case kCLOCK_UsbClk: - freq = (SYSCON->USBCLKSEL == 0U) ? CLOCK_GetFroHfFreq() : (SYSCON->USBCLKSEL == 1) ? CLOCK_GetPllOutFreq() : - 0U; - freq = freq / ((SYSCON->USBCLKDIV & 0xffU) + 1U); + freq = CLOCK_GetUsbClkFreq(); break; - case kClock_WdtOsc: + case kCLOCK_WdtOsc: freq = CLOCK_GetWdtOscFreq(); break; case kCLOCK_Frg: - freq = ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_DIV_MASK) == SYSCON_FRGCTRL_DIV_MASK) ? - ((uint64_t)CLOCK_GetFRGInputClock() * (SYSCON_FRGCTRL_DIV_MASK + 1)) / - ((SYSCON_FRGCTRL_DIV_MASK + 1) + - ((SYSCON->FRGCTRL & SYSCON_FRGCTRL_MULT_MASK) >> SYSCON_FRGCTRL_MULT_SHIFT)) : - 0; + freq = CLOCK_GetFrgClkFreq(); break; case kCLOCK_Dmic: - freq = (SYSCON->DMICCLKSEL == 0U) ? CLOCK_GetFro12MFreq() : (SYSCON->DMICCLKSEL == 1U) ? - CLOCK_GetFroHfFreq() : - (SYSCON->DMICCLKSEL == 2U) ? - CLOCK_GetPllOutFreq() : - (SYSCON->DMICCLKSEL == 3U) ? - CLOCK_GetI2SMClkFreq() : - (SYSCON->DMICCLKSEL == 4U) ? - CLOCK_GetCoreSysClkFreq() : - (SYSCON->DMICCLKSEL == 5U) ? CLOCK_GetWdtOscFreq() : 0U; - freq = freq / ((SYSCON->DMICCLKDIV & 0xffU) + 1U); + freq = CLOCK_GetDmicClkFreq(); break; case kCLOCK_AsyncApbClk: @@ -430,28 +696,37 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) } /* Set the FLASH wait states for the passed frequency */ +/** + * brief Set the flash wait states for the input freuqency. + * param iFreq : Input frequency + * return Nothing + */ void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) { if (iFreq <= 12000000U) { CLOCK_SetFLASHAccessCycles(kCLOCK_Flash1Cycle); } - else if (iFreq <= 30000000U) + else if (iFreq <= 24000000U) { CLOCK_SetFLASHAccessCycles(kCLOCK_Flash2Cycle); } - else if (iFreq <= 60000000U) + else if (iFreq <= 48000000U) { CLOCK_SetFLASHAccessCycles(kCLOCK_Flash3Cycle); } - else if (iFreq <= 85000000U) + else if (iFreq <= 72000000U) { CLOCK_SetFLASHAccessCycles(kCLOCK_Flash4Cycle); } - else + else if (iFreq <= 84000000U) { CLOCK_SetFLASHAccessCycles(kCLOCK_Flash5Cycle); } + else + { + CLOCK_SetFLASHAccessCycles(kCLOCK_Flash6Cycle); + } } /* Find encoded NDEC value for raw N value, max N = NVALMAX */ @@ -463,7 +738,7 @@ static uint32_t pllEncodeN(uint32_t N) switch (N) { case 0U: - x = 0xFFFU; + x = 0x3FFU; break; case 1U: @@ -494,7 +769,7 @@ static uint32_t pllDecodeN(uint32_t NDEC) /* Find NDec */ switch (NDEC) { - case 0xFFFU: + case 0x3FFU: n = 0U; break; @@ -533,7 +808,7 @@ static uint32_t pllEncodeP(uint32_t P) switch (P) { case 0U: - x = 0xFFU; + x = 0x7FU; break; case 1U: @@ -564,7 +839,7 @@ static uint32_t pllDecodeP(uint32_t PDEC) /* Find PDec */ switch (PDEC) { - case 0xFFU: + case 0x7FU: p = 0U; break; @@ -603,7 +878,7 @@ static uint32_t pllEncodeM(uint32_t M) switch (M) { case 0U: - x = 0xFFFFFU; + x = 0x1FFFFU; break; case 1U: @@ -634,7 +909,7 @@ static uint32_t pllDecodeM(uint32_t MDEC) /* Find MDec */ switch (MDEC) { - case 0xFFFFFU: + case 0x1FFFFU: m = 0U; break; @@ -737,7 +1012,7 @@ static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg) uint32_t postDiv = 1U; /* Direct input is not used? */ - if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_SHIFT) == 0U) + if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0U) { /* Decode PDEC value to get (P) post divider */ postDiv = 2U * pllDecodeP(pDecReg & 0x7FU); @@ -760,7 +1035,7 @@ static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg) mMult = pllDecodeM(mDecReg & 0x1FFFFU); /* Extra multiply by 2 needed? */ - if ((ctrlReg & (1UL << SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT)) == 0U) + if ((ctrlReg & (SYSCON_SYSPLLCTRL_BYPASSCCODIV2_MASK)) == 0U) { mMult = mMult << 1U; } @@ -780,15 +1055,20 @@ static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n) while (n != 0U) { tmp = n; - n = m % n; - m = tmp; + n = m % n; + m = tmp; } return m; } -/* Set PLL output based on desired output rate */ -static pll_error_t CLOCK_GetPllConfig( +/* + * Set PLL output based on desired output rate. + * In this function, the it calculates the PLL setting for output frequency from input clock + * frequency. The calculation would cost a few time. So it is not recommaned to use it frequently. + * the "pllctrl", "pllndec", "pllpdec", "pllmdec" would updated in this function. + */ +static pll_error_t CLOCK_GetPllConfigInternal( uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) { uint32_t nDivOutHz, fccoHz, multFccoDiv; @@ -797,8 +1077,8 @@ static pll_error_t CLOCK_GetPllConfig( uint32_t pllSelP, pllSelI, pllSelR, bandsel, uplimoff; /* Baseline parameters (no input or output dividers) */ - pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ - pllPostDivider = 0U; /* 0 implies post-divider will be disabled */ + pllPreDivider = 1U; /* 1 implies pre-divider will be disabled */ + pllPostDivider = 0U; /* 0 implies post-divider will be disabled */ pllDirectOutput = 1U; if (useFeedbackDiv2) { @@ -865,7 +1145,7 @@ static pll_error_t CLOCK_GetPllConfig( } /* Target CCO goes up, PLL output goes down */ - fccoHz = foutHz * (pllPostDivider * 2U); + fccoHz = foutHz * (pllPostDivider * 2U); pllDirectOutput = 0U; } @@ -895,7 +1175,7 @@ static pll_error_t CLOCK_GetPllConfig( } /* Determine PLL multipler */ - nDivOutHz = (finHz / pllPreDivider); + nDivOutHz = (finHz / pllPreDivider); pllMultiplier = (fccoHz / nDivOutHz) / multFccoDiv; /* Find optimal values for filter */ @@ -909,7 +1189,7 @@ static pll_error_t CLOCK_GetPllConfig( /* Setup filtering */ pllFindSel(pllMultiplier, pllBypassFBDIV2, &pllSelP, &pllSelI, &pllSelR); - bandsel = 1U; + bandsel = 1U; uplimoff = 0U; /* Get encoded value for M (mult) and use manual filter, disable SS mode */ @@ -925,8 +1205,8 @@ static pll_error_t CLOCK_GetPllConfig( /* Filtering will be handled by SSC */ pllSelR = pllSelI = pllSelP = 0U; - bandsel = 0U; - uplimoff = 1U; + bandsel = 0U; + uplimoff = 1U; /* The PLL multiplier will get very close and slightly under the desired target frequency. A small fractional component can be @@ -958,6 +1238,69 @@ static pll_error_t CLOCK_GetPllConfig( return kStatus_PLL_Success; } +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) +/* Alloct the static buffer for cache. */ +static pll_setup_t s_PllSetupCacheStruct[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT]; +static uint32_t s_FinHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static uint32_t s_FoutHzCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {0}; +static bool s_UseFeedbackDiv2Cache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static bool s_UseSSCache[CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT] = {false}; +static uint32_t s_PllSetupCacheIdx = 0U; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + +/* + * Calculate the PLL setting values from input clock freq to output freq. + */ +static pll_error_t CLOCK_GetPllConfig( + uint32_t finHz, uint32_t foutHz, pll_setup_t *pSetup, bool useFeedbackDiv2, bool useSS) +{ + pll_error_t retErr; +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + uint32_t i; + + for (i = 0U; i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; i++) + { + if ((finHz == s_FinHzCache[i]) && (foutHz == s_FoutHzCache[i]) && + (useFeedbackDiv2 == s_UseFeedbackDiv2Cache[i]) && (useSS == s_UseSSCache[i])) + { + /* Hit the target in cache buffer. */ + pSetup->syspllctrl = s_PllSetupCacheStruct[i].syspllctrl; + pSetup->syspllndec = s_PllSetupCacheStruct[i].syspllndec; + pSetup->syspllpdec = s_PllSetupCacheStruct[i].syspllpdec; + pSetup->syspllssctrl[0] = s_PllSetupCacheStruct[i].syspllssctrl[0]; + pSetup->syspllssctrl[1] = s_PllSetupCacheStruct[i].syspllssctrl[1]; + retErr = kStatus_PLL_Success; + break; + } + } + + if (i < CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + { + return retErr; + } +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + retErr = CLOCK_GetPllConfigInternal(finHz, foutHz, pSetup, useFeedbackDiv2, useSS); + +#if (defined(CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) && CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT) + /* Cache the most recent calulation result into buffer. */ + s_FinHzCache[s_PllSetupCacheIdx] = finHz; + s_FoutHzCache[s_PllSetupCacheIdx] = foutHz; + s_UseFeedbackDiv2Cache[s_PllSetupCacheIdx] = useFeedbackDiv2; + s_UseSSCache[s_PllSetupCacheIdx] = useSS; + + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllctrl = pSetup->syspllctrl; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllndec = pSetup->syspllndec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllpdec = pSetup->syspllpdec; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllssctrl[0] = pSetup->syspllssctrl[0]; + s_PllSetupCacheStruct[s_PllSetupCacheIdx].syspllssctrl[1] = pSetup->syspllssctrl[1]; + /* Update the index for next available buffer. */ + s_PllSetupCacheIdx = (s_PllSetupCacheIdx + 1U) % CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT; +#endif /* CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT */ + + return retErr; +} + /* Update local PLL rate variable */ static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) { @@ -965,6 +1308,9 @@ static void CLOCK_GetSystemPLLOutFromSetupUpdate(pll_setup_t *pSetup) } /* Return System PLL input clock rate */ +/*! brief Return System PLL input clock rate + * return System PLL input clock rate + */ uint32_t CLOCK_GetSystemPLLInClockRate(void) { uint32_t clkRate = 0U; @@ -996,26 +1342,47 @@ uint32_t CLOCK_GetSystemPLLInClockRate(void) } /* Return System PLL output clock rate from setup structure */ +/*! brief Return System PLL output clock rate from setup structure + * param pSetup : Pointer to a PLL setup structure + * return System PLL output clock rate calculated from the setup structure + */ uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) { uint32_t prediv, postdiv, mMult, inPllRate; uint64_t workRate; + /* Get the input clock frequency of PLL. */ inPllRate = CLOCK_GetSystemPLLInClockRate(); - if ((pSetup->syspllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U) - { - /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ - prediv = findPllPreDiv(pSetup->syspllctrl, pSetup->syspllndec); - postdiv = findPllPostDiv(pSetup->syspllctrl, pSetup->syspllpdec); + /* + * If the PLL is bypassed, PLL would not be used and the output of PLL module would just be the input clock. + */ + if ((pSetup->syspllctrl & (SYSCON_SYSPLLCTRL_BYPASS_MASK)) == 0U) + { + /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */ + /* + * 1. Pre-divider + * Pre-divider is only available when the DIRECTI is disabled. + */ + if (0U == (pSetup->syspllctrl & SYSCON_SYSPLLCTRL_DIRECTI_MASK)) + { + prediv = findPllPreDiv(pSetup->syspllctrl, pSetup->syspllndec); + } + else + { + prediv = 1U; /* The pre-divider is bypassed. */ + } /* Adjust input clock */ inPllRate = inPllRate / prediv; - /* If using the SS, use the multiplier */ - if (pSetup->syspllssctrl[1] & (1U << SYSCON_SYSPLLSSCTRL1_PD_SHIFT)) + /* + * 2. M divider + * If using the SS, use the multiplier. + */ + if (pSetup->syspllssctrl[1] & (SYSCON_SYSPLLSSCTRL1_PD_MASK)) { /* MDEC used for rate */ - mMult = findPllMMult(pSetup->syspllctrl, pSetup->syspllssctrl[0]); + mMult = findPllMMult(pSetup->syspllctrl, pSetup->syspllssctrl[0]); workRate = (uint64_t)inPllRate * (uint64_t)mMult; } else @@ -1023,14 +1390,26 @@ uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) uint64_t fract; /* SS multipler used for rate */ - mMult = (pSetup->syspllssctrl[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P; + mMult = (pSetup->syspllssctrl[1] & PLL_SSCG1_MD_INT_M) >> PLL_SSCG1_MD_INT_P; workRate = (uint64_t)inPllRate * (uint64_t)mMult; /* Adjust by fractional */ - fract = (uint64_t)(pSetup->syspllssctrl[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P; + fract = (uint64_t)(pSetup->syspllssctrl[1] & PLL_SSCG1_MD_FRACT_M) >> PLL_SSCG1_MD_FRACT_P; workRate = workRate + ((inPllRate * fract) / 0x800U); } + /* + * 3. Post-divider + * Post-divider is only available when the DIRECTO is disabled. + */ + if (0U == (pSetup->syspllctrl & SYSCON_SYSPLLCTRL_DIRECTO_MASK)) + { + postdiv = findPllPostDiv(pSetup->syspllctrl, pSetup->syspllpdec); + } + else + { + postdiv = 1U; /* The post-divider is bypassed. */ + } workRate = workRate / ((uint64_t)postdiv); } else @@ -1043,12 +1422,23 @@ uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup) } /* Set the current PLL Rate */ +/*! brief Store the current PLL rate + * param rate: Current rate of the PLL + * return Nothing + **/ void CLOCK_SetStoredPLLClockRate(uint32_t rate) { s_Pll_Freq = rate; } /* Return System PLL output clock rate */ +/*! brief Return System PLL output clock rate + * param recompute : Forces a PLL rate recomputation if true + * return System PLL output clock rate + * note The PLL rate is cached in the driver in a variable as + * the rate computation function can take some time to perform. It + * is recommended to use 'false' with the 'recompute' parameter. + */ uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) { pll_setup_t Setup; @@ -1056,9 +1446,9 @@ uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) if ((recompute) || (s_Pll_Freq == 0U)) { - Setup.syspllctrl = SYSCON->SYSPLLCTRL; - Setup.syspllndec = SYSCON->SYSPLLNDEC; - Setup.syspllpdec = SYSCON->SYSPLLPDEC; + Setup.syspllctrl = SYSCON->SYSPLLCTRL; + Setup.syspllndec = SYSCON->SYSPLLNDEC; + Setup.syspllpdec = SYSCON->SYSPLLPDEC; Setup.syspllssctrl[0] = SYSCON->SYSPLLSSCTRL0; Setup.syspllssctrl[1] = SYSCON->SYSPLLSSCTRL1; @@ -1071,10 +1461,19 @@ uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute) } /* Set PLL output based on the passed PLL setup data */ +/*! brief Set PLL output based on the passed PLL setup data + * param pControl : Pointer to populated PLL control structure to generate setup with + * param pSetup : Pointer to PLL setup structure to be filled + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note Actual frequency for setup may vary from the desired frequency based on the + * accuracy of input clocks, rounding, non-fractional PLL mode, etc. + */ pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) { uint32_t inRate; bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); + bool useFbDiv2; + pll_error_t pllError; /* Determine input rate for the PLL */ @@ -1087,8 +1486,17 @@ pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) inRate = CLOCK_GetSystemPLLInClockRate(); } + if ((pSetup->flags & PLL_SETUPFLAG_USEFEEDBACKDIV2) != 0U) + { + useFbDiv2 = true; + } + else + { + useFbDiv2 = false; + } + /* PLL flag options */ - pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, false, useSS); + pllError = CLOCK_GetPllConfig(inRate, pControl->desiredRate, pSetup, useFbDiv2, useSS); if ((useSS) && (pllError == kStatus_PLL_Success)) { /* If using SS mode, then some tweaks are made to the generated setup */ @@ -1103,6 +1511,16 @@ pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup) } /* Set PLL output from PLL setup structure */ +/*! brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * param flagcfg : Flag configuration for PLL config structure + * return PLL_ERROR_SUCCESS on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) { /* Power off PLL during setup changes */ @@ -1111,11 +1529,11 @@ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) pSetup->flags = flagcfg; /* Write PLL setup data */ - SYSCON->SYSPLLCTRL = pSetup->syspllctrl; - SYSCON->SYSPLLNDEC = pSetup->syspllndec; - SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ - SYSCON->SYSPLLPDEC = pSetup->syspllpdec; - SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->SYSPLLCTRL = pSetup->syspllctrl; + SYSCON->SYSPLLNDEC = pSetup->syspllndec; + SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->SYSPLLPDEC = pSetup->syspllpdec; + SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0]; SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */ SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1]; @@ -1126,7 +1544,7 @@ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) { /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U); /* Initialize and power up PLL */ @@ -1170,17 +1588,27 @@ pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg) } /* Setup PLL Frequency from pre-calculated value */ +/** + * brief Set PLL output from PLL setup structure (precise frequency) + * param pSetup : Pointer to populated PLL setup structure + * return kStatus_PLL_Success on success, or PLL setup error code + * note This function will power off the PLL, setup the PLL with the + * new setup data, and then optionally powerup the PLL, wait for PLL lock, + * and adjust system voltages to the new PLL rate. The function will not + * alter any source clocks (ie, main systen clock) that may use the PLL, + * so these should be setup prior to and after exiting the function. + */ pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) { /* Power off PLL during setup changes */ POWER_EnablePD(kPDRUNCFG_PD_SYS_PLL0); /* Write PLL setup data */ - SYSCON->SYSPLLCTRL = pSetup->syspllctrl; - SYSCON->SYSPLLNDEC = pSetup->syspllndec; - SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ - SYSCON->SYSPLLPDEC = pSetup->syspllpdec; - SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ + SYSCON->SYSPLLCTRL = pSetup->syspllctrl; + SYSCON->SYSPLLNDEC = pSetup->syspllndec; + SYSCON->SYSPLLNDEC = pSetup->syspllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */ + SYSCON->SYSPLLPDEC = pSetup->syspllpdec; + SYSCON->SYSPLLPDEC = pSetup->syspllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */ SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0]; SYSCON->SYSPLLSSCTRL0 = pSetup->syspllssctrl[0] | (1U << SYSCON_SYSPLLSSCTRL0_MREQ_SHIFT); /* latch */ SYSCON->SYSPLLSSCTRL1 = pSetup->syspllssctrl[1]; @@ -1191,12 +1619,12 @@ pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) { /* If turning the PLL back on, perform the following sequence to accelerate PLL lock */ volatile uint32_t delayX; - uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ + uint32_t maxCCO = (1U << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/ uint32_t curSSCTRL = SYSCON->SYSPLLSSCTRL0 & ~(1U << 17U); /* Initialize and power up PLL */ SYSCON->SYSPLLSSCTRL0 = maxCCO; - SYSCON->PDRUNCFGCLR[0] = SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK; + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); /* Set mreq to activate */ SYSCON->SYSPLLSSCTRL0 = maxCCO | (1U << 17U); @@ -1213,7 +1641,7 @@ pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) SYSCON->SYSPLLSSCTRL0 = curSSCTRL | (1U << 17U); /* Enable peripheral states by setting low */ - SYSCON->PDRUNCFGCLR[0] = SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK; + POWER_DisablePD(kPDRUNCFG_PD_SYS_PLL0); } if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) { @@ -1229,16 +1657,27 @@ pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup) } /* Set System PLL clock based on the input frequency and multiplier */ +/*! brief Set PLL output based on the multiplier and input frequency + * param multiply_by : multiplier + * param input_freq : Clock input frequency of the PLL + * return Nothing + * note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this + * function does not disable or enable PLL power, wait for PLL lock, + * or adjust system voltages. These must be done in the application. + * The function will not alter any source clocks (ie, main systen clock) + * that may use the PLL, so these should be setup prior to and after + * exiting the function. + */ void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) { uint32_t cco_freq = input_freq * multiply_by; - uint32_t pdec = 1U; + uint32_t pdec = 1U; uint32_t selr; uint32_t seli; uint32_t selp; uint32_t mdec, ndec; - uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO_SHIFT; + uint32_t directo = SYSCON_SYSPLLCTRL_DIRECTO(1); while (cco_freq < 75000000U) { @@ -1279,9 +1718,9 @@ void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) if (pdec > 1U) { - directo = 0U; /* use post divider */ - pdec = pdec / 2U; /* Account for minus 1 encoding */ - /* Translate P value */ + directo = 0U; /* use post divider */ + pdec = pdec / 2U; /* Account for minus 1 encoding */ + /* Translate P value */ switch (pdec) { case 1U: @@ -1311,7 +1750,7 @@ void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq) mdec = PLL_SSCG0_MDEC_VAL_SET(pllEncodeM(multiply_by)); ndec = 0x302U; /* pre divide by 1 (hardcoded) */ - SYSCON->SYSPLLCTRL = SYSCON_SYSPLLCTRL_BANDSEL_SHIFT | directo | SYSCON_SYSPLLCTRL_BYPASSCCODIV2_SHIFT | + SYSCON->SYSPLLCTRL = SYSCON_SYSPLLCTRL_BANDSEL(1) | directo | SYSCON_SYSPLLCTRL_BYPASSCCODIV2(1) | (selr << SYSCON_SYSPLLCTRL_SELR_SHIFT) | (seli << SYSCON_SYSPLLCTRL_SELI_SHIFT) | (selp << SYSCON_SYSPLLCTRL_SELP_SHIFT); SYSCON->SYSPLLPDEC = pdec | (1U << 7U); /* set Pdec value and assert preq */ @@ -1355,3 +1794,79 @@ bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq) return ret; } + +#if (defined(__CORTEX_M) && (__CORTEX_M == 0U)) +/*! + * brief Delay at least for several microseconds. + * Please note that, this API will calculate the microsecond period with the maximum devices + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * param delay_us Delay time in unit of microsecond. + */ +__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us) +{ + assert(0U != delay_us); + + uint32_t count = (uint32_t)USEC_TO_COUNT(delay_us, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* + * Calculate the real delay count depend on the excute instructions cycles, + * users can change the divider value to adapt to the real IDE optimise level. + */ + count = (count / 4U); + + for (; count > 0UL; count--) + { + __NOP(); + } +} +#else +/*! + * brief Use DWT to delay at least for some time. + * Please note that, this API will calculate the microsecond period with the maximum devices + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * param delay_us Delay time in unit of microsecond. + */ +__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us) +{ + assert(0U != delay_us); + uint64_t count = 0U; + uint32_t period = SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 1000000; + + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* If CYCCENT has already been enabled, read directly, otherwise, need enable it. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } + + /* Calculate the count ticks. */ + count = DWT->CYCCNT; + count += (uint64_t)period * delay_us; + + if (count > 0xFFFFFFFFUL) + { + count -= 0xFFFFFFFFUL; + /* wait for cyccnt overflow. */ + while (count < DWT->CYCCNT) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > DWT->CYCCNT) + { + } +} +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_clock.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_clock.h index f41754098d..15ca58bb42 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_clock.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_clock.h @@ -1,40 +1,16 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2019 , NXP * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of Freescale Semiconductor, Inc. nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * SPDX-License-Identifier: BSD-3-Clause */ #ifndef _FSL_CLOCK_H_ #define _FSL_CLOCK_H_ -#include "fsl_device_registers.h" -#include -#include -#include +#include "fsl_common.h" /*! @addtogroup clock */ /*! @{ */ @@ -44,11 +20,34 @@ /******************************************************************************* * Definitions *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version 2.2.0. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*@}*/ + +/*! + * @brief User-defined the size of cache for CLOCK_PllGetConfig() function. + * + * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function + * would cache the recent calulation and accelerate the execution to get the + * right settings. + */ +#ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT +#define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U +#endif + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (96000000UL) +#endif + /*! @brief Clock ip name array for FLEXCOMM. */ -#define FLEXCOMM_CLOCKS \ - { \ - kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, \ - kCLOCK_FlexComm4, kCLOCK_FlexComm5, kCLOCK_FlexComm6, kCLOCK_FlexComm7 \ +#define FLEXCOMM_CLOCKS \ + { \ + kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, kCLOCK_FlexComm4, kCLOCK_FlexComm5, \ + kCLOCK_FlexComm6, kCLOCK_FlexComm7 \ } /*! @brief Clock ip name array for LPUART. */ #define LPUART_CLOCKS \ @@ -166,31 +165,31 @@ typedef enum _clock_ip_name { kCLOCK_IpInvalid = 0U, - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), - kCLOCK_Regfile = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), - kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), - kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */ - kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), + kCLOCK_Regfile = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */ + kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), kCLOCK_SctIpu0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), - kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), @@ -198,45 +197,45 @@ typedef enum _clock_ip_name kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), - kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), - kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), - kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), - kCLOCK_Pvtvf0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), - kCLOCK_Pvtvf1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), + kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19), + kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), + kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), + kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), + kCLOCK_Pvtvf0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), + kCLOCK_Pvtvf1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29), kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), @@ -254,7 +253,7 @@ typedef enum _clock_name kCLOCK_ExtClk, /*!< External Clock */ kCLOCK_PllOut, /*!< PLL Output */ kCLOCK_UsbClk, /*!< USB input */ - kClock_WdtOsc, /*!< Watchdog Oscillator */ + kCLOCK_WdtOsc, /*!< Watchdog Oscillator */ kCLOCK_Frg, /*!< Frg Clock */ kCLOCK_Dmic, /*!< Digital Mic clock */ kCLOCK_AsyncApbClk, /*!< Async APB clock */ @@ -279,18 +278,22 @@ typedef enum _async_clock_src } async_clock_src_t; /*! @brief Clock Mux Switches -* The encoding is as follows each connection identified is 64bits wide -* starting from LSB upwards -* -* [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]* -* -*/ + * The encoding is as follows each connection identified is 32bits wide while 24bits are valuable + * starting from LSB upwards + * + * [4 bits for choice, 0 means invalid choice] [8 bits mux ID]* + * + */ -#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8)) -#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20)) -#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32)) -#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44)) -#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56)) +#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U)) + +#define GET_ID_ITEM(connection) ((connection)&0xFFFU) +#define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) +#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU) +#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) #define CM_MAINCLKSELA 0 #define CM_MAINCLKSELB 1 @@ -326,134 +329,136 @@ typedef enum _async_clock_src typedef enum _clock_attach_id { - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0), - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0), - kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0), - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0), - kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2), - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3), + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), + kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), + kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), - kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), + kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0), kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1), kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2), - kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), - kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), + kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3), + kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7), kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0), - kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), + kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1), kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), - kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), + kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0), - kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), - kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), - kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), + kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1), + kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3), + kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7), - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), - kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), + kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), - kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), + kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), - kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), + kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), - kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), + kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), - kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), + kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), - kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), + kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), - kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), + kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), - kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), + kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), - kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), + kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), - kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), + kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), - kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), + kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), - kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), + kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), - kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), + kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), - kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), + kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), - kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), + kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), - kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), + kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0), - kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), - kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), - kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), - kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), + kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1), + kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2), + kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3), + kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7), - kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0), - kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1), - kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7), + kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0), + kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1), + kMAIN_CLK_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 2), + kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7), - kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), - kFRO_HF_to_DMIC = MUX_A(CM_DMICCLKSEL, 1), - kSYS_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), - kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), + kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0), + kFRO_HF_to_DMIC = MUX_A(CM_DMICCLKSEL, 1), + kSYS_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2), + kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3), kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4), - kWDT_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 5), - kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), + kWDT_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 5), + kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7), - kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0), - kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1), - kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7), + kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0), + kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1), + kMAIN_CLK_to_USB_CLK = MUX_A(CM_USBCLKSEL, 2), + kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7), kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0), - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), - kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), - kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), - kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), - kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), - kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), - kNONE_to_NONE = 0x80000000U, + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1), + kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2), + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3), + kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4), + kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5), + kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6), + kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7), + kNONE_to_NONE = (int)0x80000000U, } clock_attach_id_t; /* Clock dividers */ typedef enum _clock_div_name { - kCLOCK_DivSystickClk = 0, - kCLOCK_DivTraceClk = 1, - kCLOCK_DivAhbClk = 32, - kCLOCK_DivClkOut = 33, - kCLOCK_DivSpifiClk = 36, + kCLOCK_DivSystickClk = 0, + kCLOCK_DivTraceClk = 1, + kCLOCK_DivAhbClk = 32, + kCLOCK_DivClkOut = 33, + kCLOCK_DivSpifiClk = 36, kCLOCK_DivAdcAsyncClk = 37, - kCLOCK_DivUsbClk = 38, - kCLOCK_DivFrg = 40, - kCLOCK_DivDmicClk = 42, - kCLOCK_DivFxI2s0MClk = 43 + kCLOCK_DivUsbClk = 38, + kCLOCK_DivFrg = 40, + kCLOCK_DivDmicClk = 42, + kCLOCK_DivFxI2s0MClk = 43 } clock_div_name_t; /******************************************************************************* @@ -500,8 +505,6 @@ typedef enum _clock_flashtim kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */ kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */ kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */ - kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */ - kCLOCK_Flash8Cycle /*!< Flash accesses use 8 CPU clocks */ } clock_flashtim_t; /** @@ -533,6 +536,14 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq); * @return Nothing */ void CLOCK_AttachClk(clock_attach_id_t connection); +/** + * @brief Get the actual clock attach id. + * This fuction uses the offset in input attach id, then it reads the actual source value in + * the register and combine the offset to obtain an actual attach id. + * @param attachId : Clock attach id to get. + * @return Clock source value. + */ +clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId); /** * @brief Setup peripheral clock dividers. * @param div_name : Clock divider name @@ -556,13 +567,23 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName); * @return Input Frequency for FRG */ uint32_t CLOCK_GetFRGInputClock(void); - + +/*! @brief Return Input frequency for the DMIC + * @return Input Frequency for DMIC + */ +uint32_t CLOCK_GetDmicClkFreq(void); + +/*! @brief Return Input frequency for the FRG + * @return Input Frequency for FRG + */ +uint32_t CLOCK_GetFrgClkFreq(void); + /*! @brief Set output of the Fractional baud rate generator * @param freq : Desired output frequency * @return Error Code 0 - fail 1 - success */ uint32_t CLOCK_SetFRGClock(uint32_t freq); - + /*! @brief Return Frequency of FRO 12MHz * @return Frequency of FRO 12MHz */ @@ -579,6 +600,10 @@ uint32_t CLOCK_GetWdtOscFreq(void); * @return Frequency of High-Freq output of FRO */ uint32_t CLOCK_GetFroHfFreq(void); +/*! @brief Return Frequency of USB + * @return Frequency of USB + */ +uint32_t CLOCK_GetUsbClkFreq(void); /*! @brief Return Frequency of PLL * @return Frequency of PLL */ @@ -599,6 +624,10 @@ uint32_t CLOCK_GetI2SMClkFreq(void); * @return Frequency of Flexcomm functional Clock */ uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); +/*! @brief Return Frequency of Adc Clock + * @return Frequency of Adc Clock. + */ +uint32_t CLOCK_GetAdcClkFreq(void); /*! @brief Return Asynchronous APB Clock source * @return Asynchronous APB CLock source */ @@ -670,12 +699,14 @@ void CLOCK_SetStoredPLLClockRate(uint32_t rate); */ #define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ #define PLL_CONFIGFLAG_FORCENOFRACT \ - (1 \ - << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \ - \ \ \ \ - \ \ \ \ \ \ - \ \ \ \ \ \ \ \ - hardware */ + (1 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ + \ \ \ + \ \ \ \ \ + \ \ \ \ \ \ \ + \ \ \ \ \ \ \ \ \ + \ \ \ \ \ \ \ \ \ \ \ + \ \ \ \ \ \ \ \ \ \ \ \ \ + hardware */ /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency * See (MF) field in the SYSPLLSSCTRL1 register in the UM. @@ -686,10 +717,10 @@ typedef enum _ss_progmodfm kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */ kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */ kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */ - kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ - kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ - kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ - kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ + kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */ + kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */ + kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */ + kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */ } ss_progmodfm_t; /*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth @@ -697,14 +728,14 @@ typedef enum _ss_progmodfm */ typedef enum _ss_progmoddp { - kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ - kSS_MR_K1 = (1 << 23), /*!< k = 1 */ + kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */ + kSS_MR_K1 = (1 << 23), /*!< k = 1 */ kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */ - kSS_MR_K2 = (3 << 23), /*!< k = 2 */ - kSS_MR_K3 = (4 << 23), /*!< k = 3 */ - kSS_MR_K4 = (5 << 23), /*!< k = 4 */ - kSS_MR_K6 = (6 << 23), /*!< k = 6 */ - kSS_MR_K8 = (7 << 23) /*!< k = 8 */ + kSS_MR_K2 = (3 << 23), /*!< k = 2 */ + kSS_MR_K3 = (4 << 23), /*!< k = 3 */ + kSS_MR_K4 = (5 << 23), /*!< k = 4 */ + kSS_MR_K6 = (6 << 23), /*!< k = 6 */ + kSS_MR_K8 = (7 << 23) /*!< k = 8 */ } ss_progmoddp_t; /*! @brief PLL Spread Spectrum (SS) Modulation waveform control @@ -714,7 +745,7 @@ typedef enum _ss_progmoddp */ typedef enum _ss_modwvctrl { - kSS_MC_NOC = (0 << 26), /*!< no compensation */ + kSS_MC_NOC = (0 << 26), /*!< no compensation */ kSS_MC_RECC = (2 << 26), /*!< recommended setting */ kSS_MC_MAXC = (3 << 26), /*!< max. compensation */ } ss_modwvctrl_t; @@ -742,19 +773,20 @@ typedef struct _pll_config } pll_config_t; /*! @brief PLL setup structure flags for 'flags' field -* These flags control how the PLL setup function sets up the PLL -*/ -#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ + * These flags control how the PLL setup function sets up the PLL + */ +#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ +#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */ /*! @brief PLL setup structure -* This structure can be used to pre-build a PLL setup configuration -* at run-time and quickly set the PLL to the configuration. It can be -* populated with the PLL setup function. If powering up or waiting -* for PLL lock, the PLL input clock source should be configured prior -* to PLL setup. -*/ + * This structure can be used to pre-build a PLL setup configuration + * at run-time and quickly set the PLL to the configuration. It can be + * populated with the PLL setup function. If powering up or waiting + * for PLL lock, the PLL input clock source should be configured prior + * to PLL setup. + */ typedef struct _pll_setup { uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */ @@ -769,21 +801,21 @@ typedef struct _pll_setup */ typedef enum _pll_error { - kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ - kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ - kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ - kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ - kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ - kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */ + kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */ + kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */ + kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */ + kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */ + kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */ + kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */ } pll_error_t; /*! @brief USB clock source definition. */ typedef enum _clock_usb_src { - kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */ + kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */ kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */ kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */ - kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL( + kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL( 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */ } clock_usb_src_t; @@ -804,7 +836,7 @@ pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup); /*! @brief Set PLL output from PLL setup structure (precise frequency) * @param pSetup : Pointer to populated PLL setup structure -* @param flagcfg : Flag configuration for PLL config structure + * @param flagcfg : Flag configuration for PLL config structure * @return PLL_ERROR_SUCCESS on success, or PLL setup error code * @note This function will power off the PLL, setup the PLL with the * new setup data, and then optionally powerup the PLL, wait for PLL lock, @@ -848,6 +880,17 @@ static inline void CLOCK_DisableUsbfs0Clock(void) CLOCK_DisableClock(kCLOCK_Usbd0); } bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! + * @brief Use DWT to delay at least for some time. + * Please note that, this API will calculate the microsecond period with the maximum + * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise + * delay count was needed, please implement a new timer count to achieve this function. + * + * @param delay_us Delay time in unit of microsecond. + */ +void SDK_DelayAtLeastUs(uint32_t delay_us); + #if defined(__cplusplus) } #endif /* __cplusplus */ From df8cf2808466c55b83d818a632d6be1266c2da8a Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 21 Jun 2019 12:31:45 -0500 Subject: [PATCH 24/37] MCUXpresso: Update the Analogin driver for LPC devices 1. Update the clock divider setting 2. ADC resolution is 12-bits, update the API return value to return 16-bit result 3. Update IOMUX setup Signed-off-by: Mahesh Mahadevan --- .../TARGET_LPC/analogin_api.c | 16 +++++++++------- .../TARGET_LPCXpresso/mbed_overrides.c | 1 + 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/analogin_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/analogin_api.c index 417f841930..618a4ff6c0 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/analogin_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/analogin_api.c @@ -49,7 +49,7 @@ void analogin_init(analogin_t *obj, PinName pin) ADC_ClockPower_Configuration(); /* Ensure the ADC clock derived from the system clock is less than 80MHz */ - clkval = CLOCK_GetFreq(kCLOCK_CoreSysClk); + clkval = CLOCK_GetFreq(kCLOCK_BusClk); while ((clkval / clkdiv) > MAX_ADC_CLOCK) { clkdiv++; } @@ -61,20 +61,20 @@ void analogin_init(analogin_t *obj, PinName pin) } ADC_GetDefaultConfig(&adc_config); - adc_config.clockDividerNumber = clkdiv; + adc_config.clockDividerNumber = (clkdiv - 1); ADC_Init(adc_addrs[instance], &adc_config); pinmap_pinout(pin, PinMap_ADC); - /* Clear the DIGIMODE bit */ - reg = IOCON->PIO[port_number][pin_number] & ~IOCON_PIO_DIGIMODE_MASK; + /* Clear the DIGIMODE & MODE bits */ + reg = IOCON->PIO[port_number][pin_number] & ~(IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_MODE_MASK); IOCON->PIO[port_number][pin_number] = reg; } uint16_t analogin_read_u16(analogin_t *obj) { uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; - uint32_t channel = obj->adc & 0xF; + uint32_t channel = obj->adc & 0xFF; adc_conv_seq_config_t adcConvSeqConfigStruct; adc_result_info_t adcResultInfoStruct; @@ -93,13 +93,15 @@ uint16_t analogin_read_u16(analogin_t *obj) while (!ADC_GetChannelConversionResult(adc_addrs[instance], channel, &adcResultInfoStruct)) { } - return adcResultInfoStruct.result; + /* The ADC has 12 bit resolution. We shift in 4 0s */ + /* from the right to make it a 16 bit number as expected */ + return adcResultInfoStruct.result << 4; } float analogin_read(analogin_t *obj) { uint16_t value = analogin_read_u16(obj); - return (float)value * (1.0f / (float)0xFFFF); + return (float)value * (1.0f / (float)0xFFF0); } const PinMap *analogin_pinmap() diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c index 44e5bc81fd..dd95c1aded 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c @@ -135,6 +135,7 @@ void ADC_ClockPower_Configuration(void) * The divider would be set when configuring the converter. */ CLOCK_EnableClock(kCLOCK_Adc0); /* SYSCON->AHBCLKCTRL[0] |= SYSCON_AHBCLKCTRL_ADC0_MASK; */ + RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); } /* Initialize the external memory. */ From ccb8f25872e9e3f480b3c15081ed04c66982d092 Mon Sep 17 00:00:00 2001 From: Jaeden Amero Date: Fri, 12 Jul 2019 10:59:41 +0100 Subject: [PATCH 25/37] mbedtls: Update to Mbed TLS 2.18.1 Update to Mbed TLS 2.18.1 and Mbed Crypto 1.1.1. --- features/mbedtls/VERSION.txt | 2 +- features/mbedtls/importer/Makefile | 2 +- features/mbedtls/inc/mbedtls/platform.h | 1 + features/mbedtls/inc/mbedtls/version.h | 8 ++++---- features/mbedtls/mbed-crypto/VERSION.txt | 2 +- features/mbedtls/mbed-crypto/importer/Makefile | 2 +- features/mbedtls/mbed-crypto/src/ecp.c | 2 ++ features/mbedtls/src/Makefile | 4 ++-- 8 files changed, 13 insertions(+), 10 deletions(-) diff --git a/features/mbedtls/VERSION.txt b/features/mbedtls/VERSION.txt index 59b0f61b1a..2597119e09 100644 --- a/features/mbedtls/VERSION.txt +++ b/features/mbedtls/VERSION.txt @@ -1 +1 @@ -mbedtls-2.18.0-rc3 +mbedtls-2.18.1 diff --git a/features/mbedtls/importer/Makefile b/features/mbedtls/importer/Makefile index 8aae98e3ee..e3033eada0 100644 --- a/features/mbedtls/importer/Makefile +++ b/features/mbedtls/importer/Makefile @@ -27,7 +27,7 @@ # # Set the mbed TLS release to import (this can/should be edited before import) -MBED_TLS_RELEASE ?= mbedtls-2.18.0-rc3 +MBED_TLS_RELEASE ?= mbedtls-2.18.1 MBED_TLS_REPO_URL ?= git@github.com:ARMmbed/mbedtls-restricted.git # Translate between mbed TLS namespace and mbed namespace diff --git a/features/mbedtls/inc/mbedtls/platform.h b/features/mbedtls/inc/mbedtls/platform.h index 801a948bc5..363d6b3db2 100644 --- a/features/mbedtls/inc/mbedtls/platform.h +++ b/features/mbedtls/inc/mbedtls/platform.h @@ -256,6 +256,7 @@ int mbedtls_platform_set_snprintf( int (*snprintf_func)( char * s, size_t n, * the destination buffer is too short. */ #if defined(MBEDTLS_PLATFORM_HAS_NON_CONFORMING_VSNPRINTF) +#include /* For Older Windows (inc. MSYS2), we provide our own fixed implementation */ int mbedtls_platform_win32_vsnprintf( char *s, size_t n, const char *fmt, va_list arg ); #endif diff --git a/features/mbedtls/inc/mbedtls/version.h b/features/mbedtls/inc/mbedtls/version.h index 79b42b26c2..de67db39de 100644 --- a/features/mbedtls/inc/mbedtls/version.h +++ b/features/mbedtls/inc/mbedtls/version.h @@ -39,7 +39,7 @@ * Major, Minor, Patchlevel */ #define MBEDTLS_VERSION_MAJOR 2 -#define MBEDTLS_VERSION_MINOR 17 +#define MBEDTLS_VERSION_MINOR 18 #define MBEDTLS_VERSION_PATCH 0 /** @@ -47,9 +47,9 @@ * MMNNPP00 * Major version | Minor version | Patch version */ -#define MBEDTLS_VERSION_NUMBER 0x02110000 -#define MBEDTLS_VERSION_STRING "2.17.0" -#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.17.0" +#define MBEDTLS_VERSION_NUMBER 0x02120000 +#define MBEDTLS_VERSION_STRING "2.18.0" +#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.18.0" #if defined(MBEDTLS_VERSION_C) diff --git a/features/mbedtls/mbed-crypto/VERSION.txt b/features/mbedtls/mbed-crypto/VERSION.txt index bf56729412..3a47cda133 100644 --- a/features/mbedtls/mbed-crypto/VERSION.txt +++ b/features/mbedtls/mbed-crypto/VERSION.txt @@ -1 +1 @@ -mbedcrypto-1.1.0d2 +mbedcrypto-1.1.1 diff --git a/features/mbedtls/mbed-crypto/importer/Makefile b/features/mbedtls/mbed-crypto/importer/Makefile index 8d5ea91ccf..3184bd7472 100644 --- a/features/mbedtls/mbed-crypto/importer/Makefile +++ b/features/mbedtls/mbed-crypto/importer/Makefile @@ -29,7 +29,7 @@ # Set the Mbed Crypto release to import (this can/should be edited before # import) -CRYPTO_RELEASE ?= mbedcrypto-1.1.0d2 +CRYPTO_RELEASE ?= mbedcrypto-1.1.1 CRYPTO_REPO_URL ?= git@github.com:ARMmbed/mbed-crypto.git # Translate between Mbed Crypto namespace and Mbed OS namespace diff --git a/features/mbedtls/mbed-crypto/src/ecp.c b/features/mbedtls/mbed-crypto/src/ecp.c index 03f5fefd4d..ccc0788c20 100644 --- a/features/mbedtls/mbed-crypto/src/ecp.c +++ b/features/mbedtls/mbed-crypto/src/ecp.c @@ -2004,8 +2004,10 @@ static unsigned char ecp_pick_window_size( const mbedtls_ecp_group *grp, * Make sure w is within bounds. * (The last test is useful only for very small curves in the test suite.) */ +#if( MBEDTLS_ECP_WINDOW_SIZE < 6 ) if( w > MBEDTLS_ECP_WINDOW_SIZE ) w = MBEDTLS_ECP_WINDOW_SIZE; +#endif if( w >= grp->nbits ) w = 2; diff --git a/features/mbedtls/src/Makefile b/features/mbedtls/src/Makefile index 60f3ae0d34..89c41281ac 100644 --- a/features/mbedtls/src/Makefile +++ b/features/mbedtls/src/Makefile @@ -35,8 +35,8 @@ LOCAL_CFLAGS += -fPIC -fpic endif endif -SOEXT_TLS=so.12 -SOEXT_X509=so.0 +SOEXT_TLS=so.13 +SOEXT_X509=so.1 SOEXT_CRYPTO=so.3 # Set AR_DASH= (empty string) to use an ar implementation that does not accept From e019d7a64f154c8c82be5aad6eef9f9e05ea4b12 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 16 Jul 2019 12:10:34 -0500 Subject: [PATCH 26/37] MCUXpresso: Update LPC SPI HAL driver Add support for different slave selects Signed-off-by: Mahesh Mahadevan --- .../TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h | 1 + targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/pinmap.c | 2 +- .../TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/spi_api.c | 3 +++ .../TARGET_LPC54114/TARGET_LPCXpresso/PeripheralNames.h | 2 +- .../TARGET_LPC54114/TARGET_LPCXpresso/PeripheralPins.c | 4 ++-- .../TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralNames.h | 1 + .../TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPins.c | 4 ++-- .../TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h | 1 + .../TARGET_MCU_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h | 1 + .../TARGET_MCU_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c | 2 +- 10 files changed, 14 insertions(+), 7 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h index 2eb11fa8e2..f71ba17944 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h @@ -58,6 +58,7 @@ struct i2c_s { struct spi_s { uint32_t instance; uint8_t bits; + uint8_t ssel_num; }; #if DEVICE_FLASH && !defined(TARGET_FLASH_CMSIS_ALGO) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/pinmap.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/pinmap.c index a822d0ac20..a0100daf69 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/pinmap.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/pinmap.c @@ -33,7 +33,7 @@ void pin_function(PinName pin, int function) IOCON->PIO[port_number][pin_number] |= IOCON_PIO_DIGIMODE_MASK; reg = IOCON->PIO[port_number][pin_number]; - reg = (reg & ~0x7) | (function & IOCON_PIO_FUNC_MASK); + reg = (reg & ~IOCON_PIO_FUNC_MASK) | (function & IOCON_PIO_FUNC_MASK); IOCON->PIO[port_number][pin_number] = reg; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/spi_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/spi_api.c index 80984b5eae..e2054f6fec 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/spi_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/spi_api.c @@ -42,6 +42,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel obj->instance = pinmap_merge(spi_data, spi_cntl); MBED_ASSERT((int)obj->instance != NC); + obj->ssel_num = 0; switch (obj->instance) { case 0: @@ -96,6 +97,7 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel pinmap_pinout(sclk, PinMap_SPI_SCLK); if (ssel != NC) { pinmap_pinout(ssel, PinMap_SPI_SSEL); + obj->ssel_num = pinmap_function(ssel, PinMap_SPI_SSEL) >> SSELNUM_SHIFT; } } @@ -128,6 +130,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) master_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh; master_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge; master_config.direction = kSPI_MsbFirst; + master_config.sselNum = obj->ssel_num; if (baud_rate > 0) { master_config.baudRate_Bps = baud_rate; } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PeripheralNames.h index b1fb1ce339..c92261c088 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PeripheralNames.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PeripheralNames.h @@ -94,7 +94,7 @@ typedef enum { ADC0_SE11 = 11, } ADCName; - +#define SSELNUM_SHIFT 16 typedef enum { SPI_0 = Flexcomm3, SPI_1 = Flexcomm5 diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PeripheralPins.c index dc222f2af9..b07d90f9ea 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PeripheralPins.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/PeripheralPins.c @@ -90,8 +90,8 @@ const PinMap PinMap_SPI_MISO[] = { const PinMap PinMap_SPI_SSEL[] = { {P0_14, SPI_0, 1}, - {P1_1, SPI_1, 4}, - {P1_2, SPI_1, 4}, + {P1_1, SPI_1, ((2 << SSELNUM_SHIFT) | 4)}, + {P1_2, SPI_1, ((3 << SSELNUM_SHIFT) | 4)}, {NC , NC , 0} }; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralNames.h index 65280c3729..5a7fff1298 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralNames.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralNames.h @@ -104,6 +104,7 @@ typedef enum { CAN_1 = 1 } CANName; +#define SSELNUM_SHIFT 16 typedef enum { SPI_0 = Flexcomm3, SPI_1 = Flexcomm7, diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPins.c index 2ccdba694b..f49cdb6f26 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPins.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_LPCXpresso/PeripheralPins.c @@ -113,8 +113,8 @@ const PinMap PinMap_SPI_MISO[] = { const PinMap PinMap_SPI_SSEL[] = { {P0_4, SPI_0, 8}, - {P1_20, SPI_1, 1}, - {P1_1, SPI_2, 5}, + {P1_20, SPI_1, ((1 << SSELNUM_SHIFT) | 1)}, + {P1_1, SPI_2, ((1 << SSELNUM_SHIFT) | 5)}, {NC , NC , 0} }; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h index 7efa1e5c20..bfa92505e9 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_FF_LPC546XX/PeripheralNames.h @@ -100,6 +100,7 @@ typedef enum { CAN_1 = 1 } CANName; +#define SSELNUM_SHIFT 16 typedef enum { SPI_0 = Flexcomm0, SPI_2 = Flexcomm2, diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h index 5eacd5d1d9..0eaf69c994 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/PeripheralNames.h @@ -100,6 +100,7 @@ typedef enum { CAN_1 = 1 } CANName; +#define SSELNUM_SHIFT 16 typedef enum { SPI_0 = Flexcomm3, SPI_1 = Flexcomm9 diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c index 59702621e6..75aea9ab6f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MCU_LPC546XX/TARGET_LPCXpresso/PeripheralPins.c @@ -107,7 +107,7 @@ const PinMap PinMap_SPI_MISO[] = { const PinMap PinMap_SPI_SSEL[] = { {P0_1, SPI_0, 2}, {P3_30, SPI_1, 1}, - {P4_6, SPI_1, 2}, + {P4_6, SPI_1, ((1 << SSELNUM_SHIFT) | 2)}, {NC , NC , 0} }; From f23bb080d6bbd3740ac22cc70cdd6da6a235e3de Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 16 Jul 2019 12:29:32 -0500 Subject: [PATCH 27/37] LPC54114: Fix compile warnings Signed-off-by: Mahesh Mahadevan --- .../TARGET_LPC54114/TARGET_LPCXpresso/device.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/device.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/device.h index 3c4cd45e69..1de3f8a64e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/device.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/device.h @@ -29,8 +29,8 @@ SYSCON_PDRUNCFG_PDEN_SRAM0_MASK | SYSCON_PDRUNCFG_PDEN_SRAM1_MASK | SYSCON_PDRUNCFG_PDEN_SRAM2_MASK) /* Defines used by the sleep code */ -#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M -#define LPC_CLOCK_RUN BOARD_BootClockFROHF48M +#define LPC_CLOCK_INTERNAL_IRC BOARD_BootClockFRO12M() +#define LPC_CLOCK_RUN BOARD_BootClockFROHF48M() #define DEVICE_ID_LENGTH 24 From ecb444b9894f66da4cb87f1305825d18c180d142 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Wed, 17 Jul 2019 15:18:59 -0500 Subject: [PATCH 28/37] MCUXpresso: Fix the LPC GPIO IRQ driver The IRQ disable was always disabling both rising and falling edges of the interrupt thereby causing failures in cases when one of the two should stay enabled. Signed-off-by: Mahesh Mahadevan --- .../TARGET_LPC/gpio_irq_api.c | 35 ++++++++++++++----- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_irq_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_irq_api.c index 46cea7a73b..7a67048baa 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_irq_api.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_irq_api.c @@ -67,6 +67,13 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 return -1; } + obj->pin = pin & 0x1F; + obj->port = pin / 32; + + if (obj->port >= INTERRUPT_PORTS) { + return -1; + } + irq_handler = handler; for (i = 0; i < NUMBER_OF_GPIO_INTS; i++) { @@ -82,13 +89,6 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32 return -1; } - obj->pin = pin & 0x1F; - obj->port = pin / 32; - - if (obj->port >= INTERRUPT_PORTS) { - return -1; - } - /* Connect trigger sources to PINT */ INPUTMUX_Init(INPUTMUX); @@ -139,7 +139,26 @@ void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) } } } else { - PINT_PinInterruptConfig(PINT, (pint_pin_int_t)obj->ch, kPINT_PinIntEnableNone, NULL); + if (event == IRQ_RISE) { + /* Checking if falling edge interrupt is already enabled on this pin */ + if (PINT->IENF & (1U << obj->ch)) { + /* Leave falling edge interrupt enabled */ + PINT_PinInterruptConfig(PINT, (pint_pin_int_t)obj->ch, kPINT_PinIntEnableFallEdge, pint_intr_callback); + } else { + /* Both rising and falling edge interrupt are disabled */ + PINT_PinInterruptConfig(PINT, (pint_pin_int_t)obj->ch, kPINT_PinIntEnableNone, pint_intr_callback); + } + } else { + /* Checking if rising edge interrupt is already enabled on this pin */ + if (PINT->IENR & (1U << obj->ch)) { + /* Leave rising edge interrupt enabled */ + PINT_PinInterruptConfig(PINT, (pint_pin_int_t)obj->ch, kPINT_PinIntEnableRiseEdge, pint_intr_callback); + } else { + /* Both rising and falling edge interrupt are disabled */ + PINT_PinInterruptConfig(PINT, (pint_pin_int_t)obj->ch, kPINT_PinIntEnableNone, pint_intr_callback); + } + } + } } From 30e747760aaa3124fc57e1e2b0ced25bf9600b3b Mon Sep 17 00:00:00 2001 From: Ben Cooke Date: Fri, 19 Jul 2019 13:24:12 -0500 Subject: [PATCH 29/37] NRF52840: enable TRNG in Nordic SDK config --- .../TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h index ab33c47dc6..b595f21deb 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h @@ -1047,7 +1047,7 @@ // The nRF HW backend provide access to RNG peripheral in nRF5x devices. //========================================================== #ifndef NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED -#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 0 +#define NRF_CRYPTO_BACKEND_NRF_HW_RNG_ENABLED 1 #endif // NRF_CRYPTO_BACKEND_NRF_HW_RNG_MBEDTLS_CTR_DRBG_ENABLED - Enable mbed TLS CTR-DRBG algorithm. @@ -2921,7 +2921,7 @@ // NRFX_RNG_ENABLED - nrfx_rng - RNG peripheral driver //========================================================== #ifndef NRFX_RNG_ENABLED -#define NRFX_RNG_ENABLED 0 +#define NRFX_RNG_ENABLED 1 #endif // NRFX_RNG_CONFIG_ERROR_CORRECTION - Error correction @@ -4953,7 +4953,7 @@ // RNG_ENABLED - nrf_drv_rng - RNG peripheral driver - legacy layer //========================================================== #ifndef RNG_ENABLED -#define RNG_ENABLED 0 +#define RNG_ENABLED 1 #endif // RNG_CONFIG_ERROR_CORRECTION - Error correction @@ -6848,7 +6848,7 @@ // NRF_QUEUE_ENABLED - nrf_queue - Queue module //========================================================== #ifndef NRF_QUEUE_ENABLED -#define NRF_QUEUE_ENABLED 0 +#define NRF_QUEUE_ENABLED 1 #endif // NRF_QUEUE_CLI_CMDS - Enable CLI commands specific to the module From 2d1f7fa78ce9904844f1e78133b795849551a1de Mon Sep 17 00:00:00 2001 From: Ben Cooke Date: Fri, 19 Jul 2019 11:28:25 -0500 Subject: [PATCH 30/37] NRF52840: fix include path issues for cordio ll and gcc --- .../stack/controller/sources/ble/bb/bb_ble_reslist.c | 4 ++-- .../stack/controller/sources/ble/lctr/lctr_act_enc.c | 2 +- .../stack/controller/sources/ble/ll/ll_main_enc_slave.c | 2 +- .../TARGET_NRF5x/stack/sources/pal_bb_ble_rf.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/bb/bb_ble_reslist.c b/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/bb/bb_ble_reslist.c index 2a4933bd01..4da6eb99c4 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/bb/bb_ble_reslist.c +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/bb/bb_ble_reslist.c @@ -25,8 +25,8 @@ #include "bb_ble_api.h" #include "bb_ble_api_reslist.h" #include "bb_ble_api_pdufilt.h" -#include "pal_bb_ble.h" -#include "pal_crypto.h" +#include "stack/platform/include/pal_bb_ble.h" +#include "stack/platform/include/pal_crypto.h" #include "wsf_assert.h" #include "ll_math.h" #include "util/bda.h" diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/lctr/lctr_act_enc.c b/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/lctr/lctr_act_enc.c index dd06f1b4ea..8aabf6cf05 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/lctr/lctr_act_enc.c +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/lctr/lctr_act_enc.c @@ -27,7 +27,7 @@ #include "wsf_msg.h" #include "wsf_trace.h" #include "util/bstream.h" -#include "pal_crypto.h" +#include "stack/platform/include/pal_crypto.h" #include /*************************************************************************************************/ diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/ll/ll_main_enc_slave.c b/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/ll/ll_main_enc_slave.c index d47e843fb9..3f3c837a9d 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/ll/ll_main_enc_slave.c +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO_LL/stack/controller/sources/ble/ll/ll_main_enc_slave.c @@ -26,7 +26,7 @@ #include "ll_math.h" #include "wsf_msg.h" #include "wsf_trace.h" -#include "pal_crypto.h" +#include "stack/platform/include/pal_crypto.h" #include /*************************************************************************************************/ diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb_ble_rf.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb_ble_rf.c index a12adce13f..0dfc6f5907 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb_ble_rf.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NORDIC_CORDIO/TARGET_NRF5x/stack/sources/pal_bb_ble_rf.c @@ -21,7 +21,7 @@ */ /*************************************************************************************************/ -#include "pal_types.h" +#include "stack/platform/include/pal_types.h" /************************************************************************************************** Macros From fa620d55ce35c9eed47256117f83f6da0eecbbc4 Mon Sep 17 00:00:00 2001 From: George Beckstein Date: Wed, 17 Jul 2019 11:43:20 -0400 Subject: [PATCH 31/37] Fix SAADC resolution for nRF52-based targets... again --- .../TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h | 2 +- .../TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h index 5f0e99d6f5..cf8441200c 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/config/sdk_config.h @@ -5063,7 +5063,7 @@ // <3=> 14 bit #ifndef SAADC_CONFIG_RESOLUTION -#define SAADC_CONFIG_RESOLUTION 1 +#define SAADC_CONFIG_RESOLUTION 2 #endif // SAADC_CONFIG_OVERSAMPLE - Sample period diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h index b595f21deb..4a00de8238 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/config/sdk_config.h @@ -5063,7 +5063,7 @@ // <3=> 14 bit #ifndef SAADC_CONFIG_RESOLUTION -#define SAADC_CONFIG_RESOLUTION 1 +#define SAADC_CONFIG_RESOLUTION 2 #endif // SAADC_CONFIG_OVERSAMPLE - Sample period From 3c6348d04d85f665a538c91f5a7c6135628c3f41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tomasz=20Mo=C5=84?= Date: Tue, 16 Jul 2019 16:26:31 +0200 Subject: [PATCH 32/37] GCC ARM: Increase develop and release debug level Do not specify the debug level for develop and release profiles. Instead rely on the compiler to choose sensible default (-g2). Note that -g1 is minimal debugging information and does not include structure definitions which quite heavily reduces debugging experience. For develop and release profiles this results in elf file containing structure definitions. This does not impact debug profile as it already did use -g3 which is the highest debug level. Compatible debuggers (eg. gdb, SEGGER Ozone) can use the extra information to provide better debugging experience. For example, when compiled .elf is loaded in gdb, this change makes it trivial to access internal RTX data. Without this change on develop profile: (gdb) print osRtxInfo.thread.run 'osRtxInfo' has unknown type; cast it to its declared type With this change on develop profile: (gdb) print osRtxInfo.thread.run $1 = {curr = 0x20014F04, next = 0x20014F04} --- tools/profiles/develop.json | 2 +- tools/profiles/release.json | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/profiles/develop.json b/tools/profiles/develop.json index 3360c696fd..7c21b2b887 100644 --- a/tools/profiles/develop.json +++ b/tools/profiles/develop.json @@ -5,7 +5,7 @@ "-fmessage-length=0", "-fno-exceptions", "-ffunction-sections", "-fdata-sections", "-funsigned-char", "-MMD", "-fno-delete-null-pointer-checks", - "-fomit-frame-pointer", "-Os", "-g1", "-DMBED_TRAP_ERRORS_ENABLED=1"], + "-fomit-frame-pointer", "-Os", "-g", "-DMBED_TRAP_ERRORS_ENABLED=1"], "asm": ["-x", "assembler-with-cpp"], "c": ["-std=gnu11"], "cxx": ["-std=gnu++14", "-fno-rtti", "-Wvla"], diff --git a/tools/profiles/release.json b/tools/profiles/release.json index 4007eaf581..f989a96717 100644 --- a/tools/profiles/release.json +++ b/tools/profiles/release.json @@ -5,7 +5,7 @@ "-fmessage-length=0", "-fno-exceptions", "-ffunction-sections", "-fdata-sections", "-funsigned-char", "-MMD", "-fno-delete-null-pointer-checks", - "-fomit-frame-pointer", "-Os", "-DNDEBUG", "-g1"], + "-fomit-frame-pointer", "-Os", "-DNDEBUG", "-g"], "asm": ["-x", "assembler-with-cpp"], "c": ["-std=gnu11"], "cxx": ["-std=gnu++14", "-fno-rtti", "-Wvla"], From 6e1dc8426301ae2b64f9f94a171ad283578a11b4 Mon Sep 17 00:00:00 2001 From: Ben Cooke Date: Fri, 19 Jul 2019 10:22:05 -0500 Subject: [PATCH 33/37] nrf52840: remove align instructions from gcc linker for ARM.extab exidx sections --- .../TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld | 2 -- 1 file changed, 2 deletions(-) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld index efca2de256..5fb464724a 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/device/TOOLCHAIN_GCC_ARM/NRF52840.ld @@ -149,14 +149,12 @@ SECTIONS .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(8); } > FLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) - . = ALIGN(8); } > FLASH __exidx_end = .; From 01bd07c9a23c86e2fd7e8b101d9bb87eec32babd Mon Sep 17 00:00:00 2001 From: Vladislav Talanov Date: Thu, 18 Jul 2019 18:07:12 +0300 Subject: [PATCH 34/37] add defines sectors for STM32F446ZE --- tools/arm_pack_manager/index.json | 105 +++++++++++++++++++++++++++++- 1 file changed, 102 insertions(+), 3 deletions(-) diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index 0fe5a9deb2..290bbe2fa2 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -374249,7 +374249,40 @@ "units": 1 } }, - "sectors": null, + "sectors": [ + [ + 134217728, + 16384 + ], + [ + 134234112, + 16384 + ], + [ + 134250496, + 16384 + ], + [ + 134266880, + 16384 + ], + [ + 134283264, + 65536 + ], + [ + 134348800, + 131072 + ], + [ + 134479872, + 131072 + ], + [ + 134610944, + 131072 + ] + ], "sub_family": "STM32F446", "vendor": "STMicroelectronics:13" }, @@ -374328,7 +374361,40 @@ "units": 1 } }, - "sectors": null, + "sectors": [ + [ + 134217728, + 16384 + ], + [ + 134234112, + 16384 + ], + [ + 134250496, + 16384 + ], + [ + 134266880, + 16384 + ], + [ + 134283264, + 65536 + ], + [ + 134348800, + 131072 + ], + [ + 134479872, + 131072 + ], + [ + 134610944, + 131072 + ] + ], "sub_family": "STM32F446", "vendor": "STMicroelectronics:13" }, @@ -374407,7 +374473,40 @@ "units": 1 } }, - "sectors": null, + "sectors": [ + [ + 134217728, + 16384 + ], + [ + 134234112, + 16384 + ], + [ + 134250496, + 16384 + ], + [ + 134266880, + 16384 + ], + [ + 134283264, + 65536 + ], + [ + 134348800, + 131072 + ], + [ + 134479872, + 131072 + ], + [ + 134610944, + 131072 + ] + ], "sub_family": "STM32F446", "vendor": "STMicroelectronics:13" }, From dbe9bfc685c37e749aeac7060f5c8991667b96b7 Mon Sep 17 00:00:00 2001 From: Evelyne Donnaes Date: Thu, 25 Jul 2019 15:18:28 +0100 Subject: [PATCH 35/37] Update Mbed version block --- platform/mbed_version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/mbed_version.h b/platform/mbed_version.h index feb3134a29..c4f5b3408e 100644 --- a/platform/mbed_version.h +++ b/platform/mbed_version.h @@ -44,7 +44,7 @@ * * @note 99 is default value for development version (master branch) */ -#define MBED_PATCH_VERSION 1 +#define MBED_PATCH_VERSION 2 #define MBED_ENCODE_VERSION(major, minor, patch) ((major)*10000 + (minor)*100 + (patch)) From 23986f1eb6ed7a23731f66da772b839fe85b9e57 Mon Sep 17 00:00:00 2001 From: Ari Parkkila Date: Tue, 23 Jul 2019 03:04:24 -0700 Subject: [PATCH 36/37] Cellular: Fix to delete context just once --- features/cellular/framework/AT/AT_CellularContext.cpp | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/features/cellular/framework/AT/AT_CellularContext.cpp b/features/cellular/framework/AT/AT_CellularContext.cpp index d9207d41d6..40ddbeaf57 100644 --- a/features/cellular/framework/AT/AT_CellularContext.cpp +++ b/features/cellular/framework/AT/AT_CellularContext.cpp @@ -757,10 +757,7 @@ void AT_CellularContext::check_and_deactivate_context() } if (_new_context_set) { - _at.clear_error(); - _at.cmd_start("AT+CGDCONT="); - _at.write_int(_cid); - _at.cmd_stop_read_resp(); + delete_current_context(); } _at.restore_at_timeout(); From 337c5b424f9ac1fd0a9a47e31c305da3171893ee Mon Sep 17 00:00:00 2001 From: Evelyne Donnaes Date: Fri, 26 Jul 2019 15:58:04 +0100 Subject: [PATCH 37/37] "Update secure binaries for LPC55S69_S (ARMC6)" --- .../prebuilt/crypto_access_control.bin | Bin 163520 -> 163520 bytes .../TARGET_M33_NS/prebuilt/spm_client.bin | Bin 163520 -> 163520 bytes .../TARGET_M33_NS/prebuilt/spm_server.bin | Bin 163520 -> 163520 bytes .../TARGET_M33_NS/prebuilt/spm_smoke.bin | Bin 163520 -> 163520 bytes .../TARGET_M33_NS/prebuilt/tfm.bin | Bin 163520 -> 163520 bytes 5 files changed, 0 insertions(+), 0 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/crypto_access_control.bin b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC55S69/TARGET_M33_NS/prebuilt/crypto_access_control.bin index aab038ff7d11c5af1ef435443e866846e8cd02e1..9311869bc30ef5f72f979346a1b022b7c6a82785 100644 GIT binary patch delta 11934 zcmZuX3tUu1_xD`(2_kn{2o{#u&JsHxD#w~`XtyU)*mkojerpI{}TJua!;eeeIwF4~jdZ#Xk&&YU?jb6zudPq@`5 z-0H>!AU`T&nRCKY*bP%G(X3q##X`8M5;VdZ)i}5&oKbxS*DO2KL25{}><_idg7dn7 zS@QD@NV0AAACUAm$-avuj93@qMPOguXZuUNaQEx>cp?!rFAAjC+>38`tY>=sr|(} z^(x2eE=$vy9_GjhI} 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