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Merge pull request #14626 from jeromecoutant/DEV_STM32WB_1_11_1 

STM32WB update drivers version to CUBE V1.11.1
pull/14655/head
Martin Kojtal 2021-05-11 10:55:14 +02:00 committed by GitHub
parent 3bd40d3161 6f9bc14898
commit b80128ff77
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
207 changed files with 44413 additions and 3997 deletions
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44
connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/ble_bufsize.h
View File

@ -1,6 +1,6 @@
/*****************************************************************************
* @file ble_bufsize.h
* @author MCD Application Team
* @author MCD
* @brief Definition of BLE stack buffers size
*****************************************************************************
* @attention
@ -25,11 +25,6 @@
*/
#define BLE_DEFAULT_ATT_MTU 23
/*
* BLE_DEFAULT_MAX_ATT_MTU: maximum supported ATT MTU size.
*/
#define BLE_DEFAULT_MAX_ATT_MTU 158
/*
* BLE_DEFAULT_MAX_ATT_SIZE: maximum attribute size.
*/
@ -81,13 +76,6 @@
((pw) + MAX(BLE_MEM_BLOCK_X_MTU(mtu, n_link), \
BLE_MBLOCKS_SECURE_CONNECTIONS))
/*
* BLE_DEFAULT_MBLOCKS_COUNT: default memory blocks count
*/
#define BLE_DEFAULT_MBLOCKS_COUNT(n_link) \
BLE_MBLOCKS_CALC(BLE_DEFAULT_PREP_WRITE_LIST_SIZE, \
BLE_DEFAULT_MAX_ATT_MTU, n_link)
/*
* BLE_FIXED_BUFFER_SIZE_BYTES:
* A part of the RAM, is dinamically allocated by initilizing all the pointers
@ -102,23 +90,31 @@
* - a part, that may be considered "fixed", i.e. independent from the above
* mentioned parameters.
*/
#if (SLAVE_ONLY == 0) && (LL_ONLY == 0)
#define BLE_FIXED_BUFFER_SIZE_BYTES 6960 /* Full stack */
#elif SLAVE_ONLY == 0
#define BLE_FIXED_BUFFER_SIZE_BYTES 6256 /* LL only */
#if (BEACON_ONLY != 0)
#define BLE_FIXED_BUFFER_SIZE_BYTES 6212 /* Beacon only */
#elif (LL_ONLY != 0)
#define BLE_FIXED_BUFFER_SIZE_BYTES 6272 /* LL only */
#elif (SLAVE_ONLY != 0)
#define BLE_FIXED_BUFFER_SIZE_BYTES 6712 /* Peripheral only */
#elif (BASIC_FEATURES != 0)
#define BLE_FIXED_BUFFER_SIZE_BYTES 6972 /* Basic Features */
#else
#define BLE_FIXED_BUFFER_SIZE_BYTES 6696 /* Slave only */
#define BLE_FIXED_BUFFER_SIZE_BYTES 7240 /* Full stack */
#endif
/*
* BLE_PER_LINK_SIZE_BYTES: additional memory size used per link
*/
#if (SLAVE_ONLY == 0) && (LL_ONLY == 0)
#define BLE_PER_LINK_SIZE_BYTES 380 /* Full stack */
#elif SLAVE_ONLY == 0
#if (BEACON_ONLY != 0)
#define BLE_PER_LINK_SIZE_BYTES 148 /* Beacon only */
#elif (LL_ONLY != 0)
#define BLE_PER_LINK_SIZE_BYTES 196 /* LL only */
#elif (SLAVE_ONLY != 0)
#define BLE_PER_LINK_SIZE_BYTES 332 /* Peripheral only */
#elif (BASIC_FEATURES != 0)
#define BLE_PER_LINK_SIZE_BYTES 332 /* Basic Features */
#else
#define BLE_PER_LINK_SIZE_BYTES 332 /* Slave only */
#define BLE_PER_LINK_SIZE_BYTES 384 /* Full stack */
#endif
/*
@ -126,7 +122,7 @@
* needed for the storage of data structures (except GATT database elements)
* whose size depends on the number of supported connections.
*
* @param num_links: Maximum number of simultaneous connections that the device
* @param n_link: Maximum number of simultaneous connections that the device
* will support. Valid values are from 1 to 8.
*
* @param mblocks_count: Number of memory blocks allocated for packets.
@ -158,4 +154,4 @@
(40 * (num_gatt_attributes)) + (48 * (num_gatt_services)))
#endif /* ! BLE_BUFSIZE_H__ */
#endif /* BLE_BUFSIZE_H__ */

45
connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/mbox_def.h
View File

@ -104,7 +104,7 @@ extern "C" {
{
uint8_t *cmdrsp_buffer;
uint8_t *m0cmd_buffer;
} MB_LldBleTable_t;
} MB_BleLldTable_t;
typedef struct
{
@ -157,9 +157,32 @@ extern "C" {
MB_Mac_802_15_4_t *p_mac_802_15_4_table;
MB_ZigbeeTable_t *p_zigbee_table;
MB_LldTestsTable_t *p_lld_tests_table;
MB_LldBleTable_t *p_lld_ble_table;
MB_BleLldTable_t *p_ble_lld_table;
} MB_RefTable_t;
/**
* This table shall be used only in the case the CPU2 runs the FUS.
* It is used by the command SHCI_GetWirelessFwInfo()
*/
typedef struct
{
uint32_t DeviceInfoTableState;
uint8_t Reserved1;
uint8_t LastFusActiveState;
uint8_t LastWirelessStackState;
uint8_t CurrentWirelessStackType;
uint32_t SafeBootVersion;
uint32_t FusVersion;
uint32_t FusMemorySize;
uint32_t WirelessStackVersion;
uint32_t WirelessStackMemorySize;
uint32_t WirelessFirmwareBleInfo;
uint32_t WirelessFirmwareThreadInfo;
uint32_t Reserved2;
uint64_t UID64;
uint16_t DeviceId;
} MB_FUS_DeviceInfoTable_t ;
#ifdef __cplusplus
}
#endif
@ -201,12 +224,12 @@ extern "C" {
* | |
* |<---HW_IPCC_BLE_EVENT_CHANNEL--------------------|
* | |
* | (LLD BLE) |
* |----HW_IPCC_LLD_BLE_CMD_CHANNEL----------------->|
* | (BLE LLD) |
* |----HW_IPCC_BLE_LLD_CMD_CHANNEL----------------->|
* | |
* |<---HW_IPCC_LLD_BLE_RSP_CHANNEL------------------|
* |<---HW_IPCC_BLE_LLD_RSP_CHANNEL------------------|
* | |
* |<---HW_IPCC_LLD_BLE_M0_CMD_CHANNEL---------------|
* |<---HW_IPCC_BLE_LLD_M0_CMD_CHANNEL---------------|
* | |
* | (MAC) |
* |----HW_IPCC_MAC_802_15_4_CMD_RSP_CHANNEL-------->|
@ -235,8 +258,8 @@ extern "C" {
#define HW_IPCC_MM_RELEASE_BUFFER_CHANNEL LL_IPCC_CHANNEL_4
#define HW_IPCC_THREAD_CLI_CMD_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLDTESTS_CLI_CMD_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLD_BLE_CLI_CMD_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLD_BLE_CMD_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_BLE_LLD_CLI_CMD_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_BLE_LLD_CMD_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_HCI_ACL_DATA_CHANNEL LL_IPCC_CHANNEL_6
/** CPU2 */
@ -246,12 +269,12 @@ extern "C" {
#define HW_IPCC_ZIGBEE_APPLI_NOTIF_ACK_CHANNEL LL_IPCC_CHANNEL_3
#define HW_IPCC_MAC_802_15_4_NOTIFICATION_ACK_CHANNEL LL_IPCC_CHANNEL_3
#define HW_IPCC_LLDTESTS_M0_CMD_CHANNEL LL_IPCC_CHANNEL_3
#define HW_IPCC_LLD_BLE_M0_CMD_CHANNEL LL_IPCC_CHANNEL_3
#define HW_IPCC_BLE_LLD_M0_CMD_CHANNEL LL_IPCC_CHANNEL_3
#define HW_IPCC_TRACES_CHANNEL LL_IPCC_CHANNEL_4
#define HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLDTESTS_CLI_RSP_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLD_BLE_CLI_RSP_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_LLD_BLE_RSP_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_BLE_LLD_CLI_RSP_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_BLE_LLD_RSP_CHANNEL LL_IPCC_CHANNEL_5
#define HW_IPCC_ZIGBEE_M0_REQUEST_CHANNEL LL_IPCC_CHANNEL_5
#endif /*__MBOX_H */

191
connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/shci.c
View File

@ -223,7 +223,6 @@ SHCI_CmdStatus_t SHCI_C2_FUS_StartWs( void )
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey( uint8_t key_index )
{
/**
@ -244,6 +243,44 @@ SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey( uint8_t key_index )
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_FUS_UnloadUsrKey( uint8_t key_index )
{
/**
* Buffer is large enough to hold command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;
p_rsp = (TL_EvtPacket_t *)local_buffer;
local_buffer[0] = key_index;
shci_send( SHCI_OPCODE_C2_FUS_UNLOAD_USR_KEY,
1,
local_buffer,
p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_FUS_ActivateAntiRollback( void )
{
/**
* Buffer is large enough to hold command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;
p_rsp = (TL_EvtPacket_t *)local_buffer;
shci_send( SHCI_OPCODE_C2_FUS_ACTIVATE_ANTIROLLBACK,
0,
0,
p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_BLE_Init( SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket )
{
/**
@ -298,7 +335,7 @@ SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init( uint8_t param_size, uint8_t * p_param )
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_LLD_BLE_Init( uint8_t param_size, uint8_t * p_param )
SHCI_CmdStatus_t SHCI_C2_BLE_LLD_Init( uint8_t param_size, uint8_t * p_param )
{
/**
* Buffer is large enough to hold command complete without payload
@ -308,7 +345,7 @@ SHCI_CmdStatus_t SHCI_C2_LLD_BLE_Init( uint8_t param_size, uint8_t * p_param )
p_rsp = (TL_EvtPacket_t *)local_buffer;
shci_send( SHCI_OPCODE_C2_LLD_BLE_INIT,
shci_send( SHCI_OPCODE_C2_BLE_LLD_INIT,
param_size,
p_param,
p_rsp );
@ -392,6 +429,44 @@ SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode( SHCI_C2_CONCURRENT_Mode_Param_t Mod
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_GetNextBleEvtTime( SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t *pParam )
{
/**
* Buffer is large enough to hold command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE+4];
TL_EvtPacket_t * p_rsp;
p_rsp = (TL_EvtPacket_t *)local_buffer;
shci_send( SHCI_OPCODE_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME,
0,
0,
p_rsp );
memcpy((void*)&(pParam->relative_time), (void*)&((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[1], sizeof(pParam->relative_time));
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification( void )
{
/**
* Buffer is large enough to hold command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;
p_rsp = (TL_EvtPacket_t *)local_buffer;
shci_send( SHCI_OPCODE_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION,
0,
0,
p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData( SHCI_C2_FLASH_Ip_t Ip )
{
/**
@ -552,6 +627,23 @@ SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket)
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_802_15_4_DeInit( void )
{
/**
* Buffer is large enough to hold command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;
p_rsp = (TL_EvtPacket_t *)local_buffer;
shci_send( SHCI_OPCODE_C2_802_15_4_DEINIT,
0,
0,
p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
/**
* Local System COMMAND
@ -562,46 +654,89 @@ SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo )
{
uint32_t ipccdba = 0;
MB_RefTable_t * p_RefTable = NULL;
uint32_t version = 0;
uint32_t memorySize = 0;
uint32_t infoStack = 0;
uint32_t wireless_firmware_version = 0;
uint32_t wireless_firmware_memorySize = 0;
uint32_t wireless_firmware_infoStack = 0;
MB_FUS_DeviceInfoTable_t * p_fus_device_info_table = NULL;
uint32_t fus_version = 0;
uint32_t fus_memorySize = 0;
ipccdba = READ_BIT( FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA );
p_RefTable = (MB_RefTable_t*)((ipccdba<<2) + SRAM2A_BASE);
/**
* The Device Info Table mapping depends on which firmware is running on CPU2.
* If the FUS is running on CPU2, FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD shall be written in the table.
* Otherwise, it means the Wireless Firmware is running on the CPU2
*/
p_fus_device_info_table = (MB_FUS_DeviceInfoTable_t*)(*(uint32_t*)((ipccdba<<2) + SRAM2A_BASE));
if(p_fus_device_info_table->DeviceInfoTableState == FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD)
{
/* The FUS is running on CPU2 */
/**
* Retrieve the WirelessFwInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
wireless_firmware_version = p_fus_device_info_table->WirelessStackVersion;
wireless_firmware_memorySize = p_fus_device_info_table->WirelessStackMemorySize;
wireless_firmware_infoStack = p_fus_device_info_table->WirelessFirmwareBleInfo;
/**
* Retrieve the FusInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
fus_version = p_fus_device_info_table->FusVersion;
fus_memorySize = p_fus_device_info_table->FusMemorySize;
}
else
{
/* The Wireless Firmware is running on CPU2 */
p_RefTable = (MB_RefTable_t*)((ipccdba<<2) + SRAM2A_BASE);
/**
* Retrieve the WirelessFwInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
wireless_firmware_version = p_RefTable->p_device_info_table->WirelessFwInfoTable.Version;
wireless_firmware_memorySize = p_RefTable->p_device_info_table->WirelessFwInfoTable.MemorySize;
wireless_firmware_infoStack = p_RefTable->p_device_info_table->WirelessFwInfoTable.InfoStack;
/**
* Retrieve the FusInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
fus_version = p_RefTable->p_device_info_table->FusInfoTable.Version;
fus_memorySize = p_RefTable->p_device_info_table->FusInfoTable.MemorySize;
}
/**
* Retrieve the WirelessFwInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
version = p_RefTable->p_device_info_table->WirelessFwInfoTable.Version;
pWirelessInfo->VersionMajor = ((version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET);
pWirelessInfo->VersionMinor = ((version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET);
pWirelessInfo->VersionSub = ((version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET);
pWirelessInfo->VersionBranch = ((version & INFO_VERSION_BRANCH_MASK) >> INFO_VERSION_BRANCH_OFFSET);
pWirelessInfo->VersionReleaseType = ((version & INFO_VERSION_TYPE_MASK) >> INFO_VERSION_TYPE_OFFSET);
pWirelessInfo->VersionMajor = ((wireless_firmware_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET);
pWirelessInfo->VersionMinor = ((wireless_firmware_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET);
pWirelessInfo->VersionSub = ((wireless_firmware_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET);
pWirelessInfo->VersionBranch = ((wireless_firmware_version & INFO_VERSION_BRANCH_MASK) >> INFO_VERSION_BRANCH_OFFSET);
pWirelessInfo->VersionReleaseType = ((wireless_firmware_version & INFO_VERSION_TYPE_MASK) >> INFO_VERSION_TYPE_OFFSET);
memorySize = p_RefTable->p_device_info_table->WirelessFwInfoTable.MemorySize;
pWirelessInfo->MemorySizeSram2B = ((memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET);
pWirelessInfo->MemorySizeSram2A = ((memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET);
pWirelessInfo->MemorySizeSram1 = ((memorySize & INFO_SIZE_SRAM1_MASK) >> INFO_SIZE_SRAM1_OFFSET);
pWirelessInfo->MemorySizeFlash = ((memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET);
pWirelessInfo->MemorySizeSram2B = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET);
pWirelessInfo->MemorySizeSram2A = ((wireless_firmware_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET);
pWirelessInfo->MemorySizeSram1 = ((wireless_firmware_memorySize & INFO_SIZE_SRAM1_MASK) >> INFO_SIZE_SRAM1_OFFSET);
pWirelessInfo->MemorySizeFlash = ((wireless_firmware_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET);
infoStack = p_RefTable->p_device_info_table->WirelessFwInfoTable.InfoStack;
pWirelessInfo->StackType = ((infoStack & INFO_STACK_TYPE_MASK) >> INFO_STACK_TYPE_OFFSET);
pWirelessInfo->StackType = ((wireless_firmware_infoStack & INFO_STACK_TYPE_MASK) >> INFO_STACK_TYPE_OFFSET);
/**
* Retrieve the FusInfoTable
* This table is stored in RAM at startup during the TL (transport layer) initialization
*/
version = p_RefTable->p_device_info_table->FusInfoTable.Version;
pWirelessInfo->FusVersionMajor = ((version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET);
pWirelessInfo->FusVersionMinor = ((version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET);
pWirelessInfo->FusVersionSub = ((version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET);
pWirelessInfo->FusVersionMajor = ((fus_version & INFO_VERSION_MAJOR_MASK) >> INFO_VERSION_MAJOR_OFFSET);
pWirelessInfo->FusVersionMinor = ((fus_version & INFO_VERSION_MINOR_MASK) >> INFO_VERSION_MINOR_OFFSET);
pWirelessInfo->FusVersionSub = ((fus_version & INFO_VERSION_SUB_MASK) >> INFO_VERSION_SUB_OFFSET);
memorySize = p_RefTable->p_device_info_table->FusInfoTable.MemorySize;
pWirelessInfo->FusMemorySizeSram2B = ((memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET);
pWirelessInfo->FusMemorySizeSram2A = ((memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET);
pWirelessInfo->FusMemorySizeFlash = ((memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET);
pWirelessInfo->FusMemorySizeSram2B = ((fus_memorySize & INFO_SIZE_SRAM2B_MASK) >> INFO_SIZE_SRAM2B_OFFSET);
pWirelessInfo->FusMemorySizeSram2A = ((fus_memorySize & INFO_SIZE_SRAM2A_MASK) >> INFO_SIZE_SRAM2A_OFFSET);
pWirelessInfo->FusMemorySizeFlash = ((fus_memorySize & INFO_SIZE_FLASH_MASK) >> INFO_SIZE_FLASH_OFFSET);
return (SHCI_Success);
}

383
connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/shci.h
View File

@ -35,22 +35,22 @@ extern "C" {
typedef enum
{
WIRELESS_FW_RUNNING = 0x00,
RSS_FW_RUNNING = 0x01,
FUS_FW_RUNNING = 0x01,
} SHCI_SysEvt_Ready_Rsp_t;
/* ERROR CODES
*
* These error codes are detected on M0 side and are send back to the M4 via a system
* notification message. It is up to the application running on M4 to manage these errors
* These error codes are detected on CPU2 side and are send back to the CPU1 via a system
* notification message. It is up to the application running on CPU1 to manage these errors
*
* These errors can be generated by all layers (low level driver, stack, framework infrastructure, etc..)
*/
typedef enum
{
ERR_BLE_INIT = 0,
ERR_THREAD_LLD_FATAL_ERROR = 125, /* The LLD driver used on 802_15_4 detected a fatal error */
ERR_THREAD_UNKNOWN_CMD = 126, /* The command send by the M4 to control the Thread stack is unknown */
ERR_ZIGBEE_UNKNOWN_CMD = 200, /* The command send by the M4 to control the Zigbee stack is unknown */
ERR_BLE_INIT = 0, /* This event is currently not reported by the CPU2 */
ERR_THREAD_LLD_FATAL_ERROR = 125, /* The LLD driver used on 802_15_4 detected a fatal error */
ERR_THREAD_UNKNOWN_CMD = 126, /* The command send by the CPU1 to control the Thread stack is unknown */
ERR_ZIGBEE_UNKNOWN_CMD = 200, /* The command send by the CPU1 to control the Zigbee stack is unknown */
} SCHI_SystemErrCode_t;
#define SHCI_EVTCODE ( 0xFF )
@ -64,11 +64,12 @@ extern "C" {
SHCI_SUB_EVT_CODE_READY = SHCI_SUB_EVT_CODE_BASE,
SHCI_SUB_EVT_ERROR_NOTIF,
SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE,
SHCI_SUB_EVT_OT_NVM_RAM_UPDATE,
SHCI_SUB_EVT_THREAD_NVM_RAM_UPDATE,
SHCI_SUB_EVT_NVM_START_WRITE,
SHCI_SUB_EVT_NVM_END_WRITE,
SHCI_SUB_EVT_NVM_START_ERASE,
SHCI_SUB_EVT_NVM_END_ERASE,
SHCI_SUB_EVT_CODE_CONCURRENT_802154_EVT,
} SHCI_SUB_EVT_CODE_t;
/**
@ -101,7 +102,7 @@ extern "C" {
} SHCI_C2_BleNvmRamUpdate_Evt_t;
/**
* SHCI_SUB_EVT_OT_NVM_RAM_UPDATE
* SHCI_SUB_EVT_THREAD_NVM_RAM_UPDATE
* This notifies the CPU1 which part of the OT NVM RAM has been updated so that only the modified
* section could be written in Flash/NVM
* StartAddress : Start address of the section that has been modified
@ -110,7 +111,7 @@ extern "C" {
typedef PACKED_STRUCT{
uint32_t StartAddress;
uint32_t Size;
} SHCI_C2_OtNvmRamUpdate_Evt_t;
} SHCI_C2_ThreadNvmRamUpdate_Evt_t;
/**
* SHCI_SUB_EVT_NVM_START_WRITE
@ -151,6 +152,11 @@ extern "C" {
/* SYSTEM COMMAND */
typedef PACKED_STRUCT
{
/**
* MetaData holds :
* 2*32bits for chaining list
* 1*32bits with BLE header (type + Opcode + Length)
*/
uint32_t MetaData[3];
} SHCI_Header_t;
@ -160,6 +166,7 @@ extern "C" {
SHCI_UNKNOWN_CMD = 0x01,
SHCI_ERR_UNSUPPORTED_FEATURE = 0x11,
SHCI_ERR_INVALID_HCI_CMD_PARAMS = 0x12,
SHCI_ERR_INVALID_PARAMS = 0x42,
SHCI_FUS_CMD_NOT_SUPPORTED = 0xFF,
} SHCI_CmdStatus_t;
@ -192,8 +199,8 @@ extern "C" {
SHCI_OCF_C2_FUS_RESERVED2,
SHCI_OCF_C2_FUS_RESERVED3,
SHCI_OCF_C2_FUS_LOCK_USR_KEY,
SHCI_OCF_C2_FUS_RESERVED5,
SHCI_OCF_C2_FUS_RESERVED6,
SHCI_OCF_C2_FUS_UNLOAD_USR_KEY,
SHCI_OCF_C2_FUS_ACTIVATE_ANTIROLLBACK,
SHCI_OCF_C2_FUS_RESERVED7,
SHCI_OCF_C2_FUS_RESERVED8,
SHCI_OCF_C2_FUS_RESERVED9,
@ -214,23 +221,47 @@ extern "C" {
SHCI_OCF_C2_LLD_TESTS_INIT,
SHCI_OCF_C2_EXTPA_CONFIG,
SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL,
SHCI_OCF_C2_LLD_BLE_INIT,
SHCI_OCF_C2_CONFIG,
SHCI_OCF_C2_BLE_LLD_INIT,
SHCI_OCF_C2_CONFIG,
SHCI_OCF_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME,
SHCI_OCF_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION,
SHCI_OCF_C2_802_15_4_DEINIT,
} SHCI_OCF_t;
#define SHCI_OPCODE_C2_FUS_GET_STATE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE)
/** No command parameters */
/** Response parameters*/
/** It responds a 1 byte value holding FUS State error code when the FUS State value is 0xFF (FUS_STATE_VALUE_ERROR) */
typedef enum
{
FUS_STATE_NO_ERROR = 0x00,
FUS_STATE_IMG_NOT_FOUND = 0x01,
FUS_STATE_IMG_CORRUPT = 0x02,
FUS_STATE_IMG_NOT_AUTHENTIC = 0x03,
FUS_STATE_IMG_NOT_ENOUGH_SPACE = 0x04,
FUS_STATE_ERR_UNKNOWN = 0xFF,
FUS_STATE_ERROR_NO_ERROR = 0x00,
FUS_STATE_ERROR_IMG_NOT_FOUND = 0x01,
FUS_STATE_ERROR_IMG_CORRUPT = 0x02,
FUS_STATE_ERROR_IMG_NOT_AUTHENTIC = 0x03,
FUS_STATE_ERROR_IMG_NOT_ENOUGH_SPACE = 0x04,
FUS_STATE_ERROR_IMAGE_USRABORT = 0x05,
FUS_STATE_ERROR_IMAGE_ERSERROR = 0x06,
FUS_STATE_ERROR_IMAGE_WRTERROR = 0x07,
FUS_STATE_ERROR_AUTH_TAG_ST_NOTFOUND = 0x08,
FUS_STATE_ERROR_AUTH_TAG_CUST_NOTFOUND = 0x09,
FUS_STATE_ERROR_AUTH_KEY_LOCKED = 0x0A,
FUS_STATE_ERROR_FW_ROLLBACK_ERROR = 0x11,
FUS_STATE_ERROR_STATE_NOT_RUNNING = 0xFE,
FUS_STATE_ERROR_ERR_UNKNOWN = 0xFF,
} SHCI_FUS_GetState_ErrorCode_t;
enum
{
FUS_STATE_VALUE_IDLE = 0x00,
FUS_STATE_VALUE_FW_UPGRD_ONGOING = 0x10,
FUS_STATE_VALUE_FW_UPGRD_ONGOING_END = 0x1F, /* All values between 0x10 and 0x1F has the same meaning */
FUS_STATE_VALUE_FUS_UPGRD_ONGOING = 0x20,
FUS_STATE_VALUE_FUS_UPGRD_ONGOING_END = 0x2F, /* All values between 0x20 and 0x2F has the same meaning */
FUS_STATE_VALUE_SERVICE_ONGOING = 0x30,
FUS_STATE_VALUE_SERVICE_ONGOING_END = 0x3F, /* All values between 0x30 and 0x3F has the same meaning */
FUS_STATE_VALUE_ERROR = 0xFF,
};
#define SHCI_OPCODE_C2_FUS_RESERVED1 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED1)
/** No command parameters */
/** No response parameters*/
@ -306,11 +337,11 @@ extern "C" {
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_RESERVED5 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED5)
#define SHCI_OPCODE_C2_FUS_UNLOAD_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UNLOAD_USR_KEY)
/** No command parameters */
/** No response parameters*/
/** 1 byte holding the key index value */
#define SHCI_OPCODE_C2_FUS_RESERVED6 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED6)
#define SHCI_OPCODE_C2_FUS_ACTIVATE_ANTIROLLBACK (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_ACTIVATE_ANTIROLLBACK)
/** No command parameters */
/** No response parameters*/
@ -341,24 +372,192 @@ extern "C" {
#define SHCI_OPCODE_C2_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_INIT)
/** THE ORDER SHALL NOT BE CHANGED */
typedef PACKED_STRUCT{
uint8_t* pBleBufferAddress; /**< NOT USED CURRENTLY */
uint32_t BleBufferSize; /**< Size of the Buffer allocated in pBleBufferAddress */
uint8_t* pBleBufferAddress; /**< NOT USED - shall be set to 0 */
uint32_t BleBufferSize; /**< NOT USED - shall be set to 0 */
/**
* NumAttrRecord
* Maximum number of attribute records related to all the required characteristics (excluding the services)
* that can be stored in the GATT database, for the specific BLE user application.
* For each characteristic, the number of attribute records goes from two to five depending on the characteristic properties:
* - minimum of two (one for declaration and one for the value)
* - add one more record for each additional property: notify or indicate, broadcast, extended property.
* The total calculated value must be increased by 9, due to the records related to the standard attribute profile and
* GAP service characteristics, and automatically added when initializing GATT and GAP layers
* - Min value: <number of user attributes> + 9
* - Max value: depending on the GATT database defined by user application
*/
uint16_t NumAttrRecord;
/**
* NumAttrServ
* Defines the maximum number of services that can be stored in the GATT database. Note that the GAP and GATT services
* are automatically added at initialization so this parameter must be the number of user services increased by two.
* - Min value: <number of user service> + 2
* - Max value: depending GATT database defined by user application
*/
uint16_t NumAttrServ;
/**
* AttrValueArrSize
* NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure )
*
* Size of the storage area for the attribute values.
* Each characteristic contributes to the attrValueArrSize value as follows:
* - Characteristic value length plus:
* + 5 bytes if characteristic UUID is 16 bits
* + 19 bytes if characteristic UUID is 128 bits
* + 2 bytes if characteristic has a server configuration descriptor
* + 2 bytes * NumOfLinks if the characteristic has a client configuration descriptor
* + 2 bytes if the characteristic has extended properties
* Each descriptor contributes to the attrValueArrSize value as follows:
* - Descriptor length
*/
uint16_t AttrValueArrSize;
/**
* NumOfLinks
* Maximum number of BLE links supported
* - Min value: 1
* - Max value: 8
*/
uint8_t NumOfLinks;
/**
* ExtendedPacketLengthEnable
* Disable/enable the extended packet length BLE 5.0 feature
* - Disable: 0
* - Enable: 1
*/
uint8_t ExtendedPacketLengthEnable;
/**
* PrWriteListSize
* NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure )
*
* Maximum number of supported “prepare write request”
* - Min value: given by the macro DEFAULT_PREP_WRITE_LIST_SIZE
* - Max value: a value higher than the minimum required can be specified, but it is not recommended
*/
uint8_t PrWriteListSize;
/**
* MblockCount
* NOTE: This parameter is overwritten by the CPU2 with an hardcoded optimal value when the parameter "Options" is set to "LL_only"
* ( see Options description in that structure )
*
* Number of allocated memory blocks for the BLE stack
* - Min value: given by the macro MBLOCKS_CALC
* - Max value: a higher value can improve data throughput performance, but uses more memory
*/
uint8_t MblockCount;
/**
* AttMtu
* NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure )
*
* Maximum ATT MTU size supported
* - Min value: 23
* - Max value: 512
*/
uint16_t AttMtu;
/**
* SlaveSca
* The sleep clock accuracy (ppm value) that used in BLE connected slave mode to calculate the window widening
* (in combination with the sleep clock accuracy sent by master in CONNECT_REQ PDU),
* refer to BLE 5.0 specifications - Vol 6 - Part B - chap 4.5.7 and 4.2.2
* - Min value: 0
* - Max value: 500 (worst possible admitted by specification)
*/
uint16_t SlaveSca;
/**
* MasterSca
* The sleep clock accuracy handled in master mode. It is used to determine the connection and advertising events timing.
* It is transmitted to the slave in CONNEC_REQ PDU used by the slave to calculate the window widening,
* see SlaveSca and Bluetooth Core Specification v5.0 Vol 6 - Part B - chap 4.5.7 and 4.2.2
* Possible values:
* - 251 ppm to 500 ppm: 0
* - 151 ppm to 250 ppm: 1
* - 101 ppm to 150 ppm: 2
* - 76 ppm to 100 ppm: 3
* - 51 ppm to 75 ppm: 4
* - 31 ppm to 50 ppm: 5
* - 21 ppm to 30 ppm: 6
* - 0 ppm to 20 ppm: 7
*/
uint8_t MasterSca;
/**
* LsSource
* Source for the 32 kHz slow speed clock.
* - External crystal LSE: 0 - No calibration
* - Others:1 - As the accuracy of this oscillator can vary depending upon external conditions (temperature),
* it is calibrated every second to ensure correct behavior of timing sensitive BLE operations
*/
uint8_t LsSource;
/**
* MaxConnEventLength
* This parameter determines the maximum duration of a slave connection event. When this duration is reached the slave closes
* the current connections event (whatever is the CE_length parameter specified by the master in HCI_CREATE_CONNECTION HCI command),
* expressed in units of 625/256 µs (~2.44 µs)
* - Min value: 0 (if 0 is specified, the master and slave perform only a single TX-RX exchange per connection event)
* - Max value: 1638400 (4000 ms). A higher value can be specified (max 0xFFFFFFFF) but results in a maximum connection time
* of 4000 ms as specified. In this case the parameter is not applied, and the predicted CE length calculated on slave is not shortened
*/
uint32_t MaxConnEventLength;
/**
* HsStartupTime
* Startup time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 µs (~2.44 µs).
* - Min value: 0
* - Max value: 820 (~2 ms). A higher value can be specified, but the value that implemented in stack is forced to ~2 ms
*/
uint16_t HsStartupTime;
/**
* ViterbiEnable
* Viterbi implementation in BLE LL reception.
* - 0: Enable
* - 1: Disable
*/
uint8_t ViterbiEnable;
uint8_t LlOnly;
/**
* Options flags
* - bit 0: 1: LL only 0: LL + host
* - bit 1: 1: no service change desc. 0: with service change desc.
* - bit 2: 1: device name Read-Only 0: device name R/W
* - bit 7: 1: LE Power Class 1 0: LE Power Classe 2-3
* - other bits: reserved ( shall be set to 0)
*/
uint8_t Options;
/**
* HwVersion
* Reserved for future use - shall be set to 0
*/
uint8_t HwVersion;
/**
* Maximum number of connection-oriented channels in initiator mode.
* Range: 0 .. 64
*/
uint8_t max_coc_initiator_nbr;
/**
* Minimum transmit power in dBm supported by the Controller.
* Range: -127 .. 20
*/
int8_t min_tx_power;
/**
* Maximum transmit power in dBm supported by the Controller.
* Range: -127 .. 20
*/
int8_t max_tx_power;
} SHCI_C2_Ble_Init_Cmd_Param_t;
typedef PACKED_STRUCT{
@ -366,7 +565,23 @@ extern "C" {
SHCI_C2_Ble_Init_Cmd_Param_t Param;
} SHCI_C2_Ble_Init_Cmd_Packet_t;
/** No response parameters*/
/**
* Options
* Each definition below may be added together to build the Options value
* WARNING : Only one definition per bit shall be added to build the Options value
*/
#define SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY (1<<0)
#define SHCI_C2_BLE_INIT_OPTIONS_LL_HOST (0<<0)
#define SHCI_C2_BLE_INIT_OPTIONS_NO_SVC_CHANGE_DESC (1<<1)
#define SHCI_C2_BLE_INIT_OPTIONS_WITH_SVC_CHANGE_DESC (0<<1)
#define SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RO (1<<2)
#define SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RW (0<<2)
#define SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_1 (1<<7)
#define SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3 (0<<7)
#define SHCI_OPCODE_C2_THREAD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_THREAD_INIT)
/** No command parameters */
@ -420,9 +635,22 @@ extern "C" {
BLE_ENABLE,
THREAD_ENABLE,
ZIGBEE_ENABLE,
MAC_ENABLE,
} SHCI_C2_CONCURRENT_Mode_Param_t;
/** No response parameters*/
#define SHCI_OPCODE_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME)
/** command parameters */
typedef PACKED_STRUCT
{
uint32_t relative_time;
} SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t;
/** No response parameters*/
#define SHCI_OPCODE_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FLASH_STORE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_STORE_DATA)
#define SHCI_OPCODE_C2_FLASH_ERASE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_DATA)
/** command parameters */
@ -444,7 +672,7 @@ extern "C" {
#define SHCI_OPCODE_C2_LLD_TESTS_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_TESTS_INIT)
#define SHCI_OPCODE_C2_LLD_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_BLE_INIT)
#define SHCI_OPCODE_C2_BLE_LLD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_LLD_INIT)
#define SHCI_OPCODE_C2_EXTPA_CONFIG (( SHCI_OGF << 10) + SHCI_OCF_C2_EXTPA_CONFIG)
/** Command parameters */
@ -490,6 +718,8 @@ extern "C" {
uint32_t ThreadNvmRamAddress;
} SHCI_C2_CONFIG_Cmd_Param_t;
#define SHCI_OPCODE_C2_802_15_4_DEINIT (( SHCI_OGF << 10) + SHCI_OCF_C2_802_15_4_DEINIT)
/**
* PayloadCmdSize
* Value that shall be used
@ -512,7 +742,7 @@ extern "C" {
*/
#define SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE (1<<0)
#define SHCI_C2_CONFIG_EVTMASK1_BIT1_BLE_NVM_RAM_UPDATE_ENABLE (1<<1)
#define SHCI_C2_CONFIG_EVTMASK1_BIT2_OT_NVM_RAM_UPDATE_ENABLE (1<<2)
#define SHCI_C2_CONFIG_EVTMASK1_BIT2_THREAD_NVM_RAM_UPDATE_ENABLE (1<<2)
#define SHCI_C2_CONFIG_EVTMASK1_BIT3_NVM_START_WRITE_ENABLE (1<<3)
#define SHCI_C2_CONFIG_EVTMASK1_BIT4_NVM_END_WRITE_ENABLE (1<<4)
#define SHCI_C2_CONFIG_EVTMASK1_BIT5_NVM_START_ERASE_ENABLE (1<<5)
@ -536,18 +766,17 @@ extern "C" {
/** No response parameters*/
/* Exported type --------------------------------------------------------*/
typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t;
#define FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD (0xA94656B9)
/*
* At startup, the informations relative to the wireless binary are stored in RAM trough a structure defined by
* SHCI_WirelessFwInfoTable_t.This structure contains 4 fields (Version,MemorySize, Stack_info and a reserved part)
* MB_WirelessFwInfoTable_t.This structure contains 4 fields (Version,MemorySize, Stack_info and a reserved part)
* each of those coded on 32 bits as shown on the table below:
*
*
* |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |
* -------------------------------------------------------------------------------------------------
* Version | Major version | Minor version | Sub version | Branch |Releas Type|
* Version | Major version | Minor version | Sub version | Branch |ReleaseType|
* -------------------------------------------------------------------------------------------------
* MemorySize | SRAM2B (kB) | SRAM2A (kB) | SRAM1 (kB) | FLASH (4kb) |
* -------------------------------------------------------------------------------------------------
@ -587,16 +816,17 @@ typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t;
#define INFO_STACK_TYPE_MASK 0x000000ff
#define INFO_STACK_TYPE_NONE 0
#define INFO_STACK_TYPE_BLE_STANDARD 0x01
#define INFO_STACK_TYPE_BLE_FULL 0x01
#define INFO_STACK_TYPE_BLE_HCI 0x02
#define INFO_STACK_TYPE_BLE_LIGHT 0x03
#define INFO_STACK_TYPE_BLE_BEACON 0x04
#define INFO_STACK_TYPE_THREAD_FTD 0x10
#define INFO_STACK_TYPE_THREAD_MTD 0x11
#define INFO_STACK_TYPE_ZIGBEE_FFD 0x30
#define INFO_STACK_TYPE_ZIGBEE_RFD 0x31
#define INFO_STACK_TYPE_MAC 0x40
#define INFO_STACK_TYPE_BLE_THREAD_FTD_STATIC 0x50
#define INFO_STACK_TYPE_BLE_THREAD_FTD_DYAMIC 0x51
#define INFO_STACK_TYPE_BLE_THREAD_FTD_DYAMIC 0x51
#define INFO_STACK_TYPE_802154_LLD_TESTS 0x60
#define INFO_STACK_TYPE_802154_PHY_VALID 0x61
#define INFO_STACK_TYPE_BLE_PHY_VALID 0x62
@ -604,8 +834,11 @@ typedef MB_WirelessFwInfoTable_t SHCI_WirelessFwInfoTable_t;
#define INFO_STACK_TYPE_BLE_RLV 0x64
#define INFO_STACK_TYPE_802154_RLV 0x65
#define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_STATIC 0x70
#define INFO_STACK_TYPE_BLE_ZIGBEE_RFD_STATIC 0x71
#define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_DYNAMIC 0x78
#define INFO_STACK_TYPE_BLE_ZIGBEE_RFD_DYNAMIC 0x79
#define INFO_STACK_TYPE_RLV 0x80
#define INFO_STACK_TYPE_BLE_MAC_STATIC 0x90
typedef struct {
/**
@ -635,18 +868,16 @@ typedef struct {
/* Exported functions ------------------------------------------------------- */
/**
* For all SHCI_C2_FUS_xxx() command:
* When the wireless FW is running on the CPU2, the command returns SHCI_FUS_CMD_NOT_SUPPORTED
* When any FUS command is sent after the SHCI_FUS_CMD_NOT_SUPPORTED has been received,
* the CPU2 switches on the RSS ( This reboots automatically the device )
*/
/**
* SHCI_C2_FUS_GetState
* @brief Read the FUS State
* If the user is not interested by the Error code response, a null value may
* be passed as parameter
*
* Note: This command is fully supported only by the FUS.
* When the wireless firmware receives that command, it responds SHCI_FUS_CMD_NOT_SUPPORTED the first time.
* When the wireless firmware receives that command a second time, it reboots the full device with the FUS running on CPU2
*
* @param p_rsp : return the error code when the FUS State Value = 0xFF
* @retval FUS State Values
*/
@ -655,6 +886,7 @@ typedef struct {
/**
* SHCI_C2_FUS_FwUpgrade
* @brief Request the FUS to install the CPU2 firmware update
* Note: This command is only supported by the FUS.
*
* @param fw_src_add: Address of the firmware image location
* @param fw_dest_add: Address of the firmware destination
@ -665,6 +897,7 @@ typedef struct {
/**
* SHCI_C2_FUS_FwDelete
* @brief Delete the wireless stack on CPU2
* Note: This command is only supported by the FUS.
*
* @param None
* @retval Status
@ -674,6 +907,7 @@ typedef struct {
/**
* SHCI_C2_FUS_UpdateAuthKey
* @brief Request the FUS to update the authentication key
* Note: This command is only supported by the FUS.
*
* @param pCmdPacket
* @retval Status
@ -683,6 +917,7 @@ typedef struct {
/**
* SHCI_C2_FUS_LockAuthKey
* @brief Request the FUS to prevent any future update of the authentication key
* Note: This command is only supported by the FUS.
*
* @param None
* @retval Status
@ -692,6 +927,7 @@ typedef struct {
/**
* SHCI_C2_FUS_StoreUsrKey
* @brief Request the FUS to store the user key
* Note: This command is supported by both the FUS and the wireless stack.
*
* @param pParam : command parameter
* @param p_key_index : Index allocated by the FUS to the stored key
@ -703,6 +939,7 @@ typedef struct {
/**
* SHCI_C2_FUS_LoadUsrKey
* @brief Request the FUS to load the user key into the AES
* Note: This command is supported by both the FUS and the wireless stack.
*
* @param key_index : index of the user key to load in AES1
* @retval Status
@ -712,6 +949,7 @@ typedef struct {
/**
* SHCI_C2_FUS_StartWs
* @brief Request the FUS to reboot on the wireless stack
* Note: This command is only supported by the FUS.
*
* @param None
* @retval Status
@ -721,17 +959,41 @@ typedef struct {
/**
* SHCI_C2_FUS_LockUsrKey
* @brief Request the FUS to lock the user key so that it cannot be updated later on
* Note: This command is supported by both the FUS and the wireless stack.
*
* @param key_index : index of the user key to lock
* @retval Status
*/
SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey( uint8_t key_index );
/**
* SHCI_C2_FUS_UnloadUsrKey
* @brief Request the FUS to Unload the user key so that the CPU1 may use the AES with another Key
* Note: This command is supported by both the FUS and the wireless stack.
*
* @param key_index : index of the user key to unload
* @retval Status
*/
SHCI_CmdStatus_t SHCI_C2_FUS_UnloadUsrKey( uint8_t key_index );
/**
* SHCI_C2_FUS_ActivateAntiRollback
* @brief Request the FUS to enable the AntiRollback feature so that it is not possible to update the wireless firmware
* with an older version than the current one.
* Note:
* - This command is only supported by the FUS.
* - Once this feature is enabled, it is not possible anymore to disable it.
*
* @param None
* @retval Status
*/
SHCI_CmdStatus_t SHCI_C2_FUS_ActivateAntiRollback( void );
/**
* SHCI_C2_BLE_Init
* @brief Provides parameters and starts the BLE Stack
*
* @param pCmdPacket : Parameters to be provided to the BLE Stack
* @param pCmdPacket : Parameters are described SHCI_C2_Ble_Init_Cmd_Packet_t declaration
* @retval Status
*/
SHCI_CmdStatus_t SHCI_C2_BLE_Init( SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket );
@ -756,14 +1018,14 @@ typedef struct {
SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init( uint8_t param_size, uint8_t * p_param );
/**
* SHCI_C2_LLD_BLE_Init
* @brief Starts the LLD tests CLI
* SHCI_C2_BLE_LLD_Init
* @brief Starts the LLD tests BLE
*
* @param param_size : Nb of bytes
* @param p_param : pointeur with data to give from M4 to M0
* @retval Status
*/
SHCI_CmdStatus_t SHCI_C2_LLD_BLE_Init( uint8_t param_size, uint8_t * p_param );
SHCI_CmdStatus_t SHCI_C2_BLE_LLD_Init( uint8_t param_size, uint8_t * p_param );
/**
* SHCI_C2_ZIGBEE_Init
@ -800,6 +1062,24 @@ typedef struct {
* @retval Status
*/
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode( SHCI_C2_CONCURRENT_Mode_Param_t Mode );
/**
* SHCI_C2_CONCURRENT_GetNextBleEvtTime
* @brief Get the next BLE event date (relative time)
*
* @param Command Packet
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_GetNextBleEvtTime( SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t *pParam );
/**
* SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification
* @brief Activate the next 802.15.4 event notification (one shot)
*
* @param None
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification( void );
/**
* SHCI_C2_FLASH_StoreData
@ -842,7 +1122,7 @@ typedef struct {
/**
* SHCI_GetWirelessFwInfo
* @brief This function read back the informations relative to the wireless binary loaded.
* Refer yourself to SHCI_WirelessFwInfoTable_t structure to get the significance
* Refer yourself to MB_WirelessFwInfoTable_t structure to get the significance
* of the different parameters returned.
* @param pWirelessInfo : Pointer to WirelessFwInfo_t.
*
@ -935,6 +1215,15 @@ typedef struct {
*/
SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket);
/**
* SHCI_C2_802_15_4_DeInit
* @brief Deinit 802.15.4 layer (to be used before entering StandBy mode)
*
* @param None
* @retval Status
*/
SHCI_CmdStatus_t SHCI_C2_802_15_4_DeInit( void );
#ifdef __cplusplus
}
#endif

101
connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/shci_tl.c
View File

@ -24,33 +24,6 @@
#include "stm_list.h"
#include "shci_tl.h"
#include "mbed_toolchain.h"
/**
* These traces are not yet supported in an usual way in the delivery package
* They can enabled by adding the definition of TL_SHCI_CMD_DBG_EN and/or TL_SHCI_EVT_DBG_EN in the preprocessor option in the IDE
*/
#if ( (TL_SHCI_CMD_DBG_EN != 0) || (TL_SHCI_EVT_DBG_EN != 0) )
#include "app_conf.h"
#include "dbg_trace.h"
#endif
#if (TL_SHCI_CMD_DBG_EN != 0)
#define TL_SHCI_CMD_DBG_MSG PRINT_MESG_DBG
#define TL_SHCI_CMD_DBG_BUF PRINT_LOG_BUFF_DBG
#else
#define TL_SHCI_CMD_DBG_MSG(...)
#define TL_SHCI_CMD_DBG_BUF(...)
#endif
#if (TL_SHCI_EVT_DBG_EN != 0)
#define TL_SHCI_EVT_DBG_MSG PRINT_MESG_DBG
#define TL_SHCI_EVT_DBG_BUF PRINT_LOG_BUFF_DBG
#else
#define TL_SHCI_EVT_DBG_MSG(...)
#define TL_SHCI_EVT_DBG_BUF(...)
#endif
/* Private typedef -----------------------------------------------------------*/
typedef enum
{
@ -88,9 +61,6 @@ static void Cmd_SetStatus(SHCI_TL_CmdStatus_t shcicmdstatus);
static void TlCmdEvtReceived(TL_EvtPacket_t *shcievt);
static void TlUserEvtReceived(TL_EvtPacket_t *shcievt);
static void TlInit( TL_CmdPacket_t * p_cmdbuffer );
static void OutputCmdTrace(TL_CmdPacket_t *pCmdBuffer);
static void OutputRspTrace(TL_EvtPacket_t *p_rsp);
static void OutputEvtTrace(TL_EvtPacket_t *phcievtbuffer);
/* Interface ------- ---------------------------------------------------------*/
void shci_init(void(* UserEvtRx)(void* pData), void* pConf)
@ -128,8 +98,6 @@ void shci_user_evt_proc(void)
{
LST_remove_head ( &SHciAsynchEventQueue, (tListNode **)&phcievtbuffer );
OutputEvtTrace(phcievtbuffer);
if (shciContext.UserEvtRx != NULL)
{
UserEvtRxParam.pckt = phcievtbuffer;
@ -186,8 +154,6 @@ void shci_send( uint16_t cmd_code, uint8_t len_cmd_payload, uint8_t * p_cmd_payl
memcpy(pCmdBuffer->cmdserial.cmd.payload, p_cmd_payload, len_cmd_payload );
OutputCmdTrace(pCmdBuffer);
shciContext.io.Send(0,0);
shci_cmd_resp_wait(SHCI_TL_DEFAULT_TIMEOUT);
@ -198,8 +164,6 @@ void shci_send( uint16_t cmd_code, uint8_t len_cmd_payload, uint8_t * p_cmd_payl
*/
memcpy( &(p_rsp->evtserial), pCmdBuffer, ((TL_EvtSerial_t*)pCmdBuffer)->evt.plen + TL_EVT_HDR_SIZE );
OutputRspTrace(p_rsp);
Cmd_SetStatus(SHCI_TL_CmdAvailable);
return;
@ -269,69 +233,8 @@ static void TlUserEvtReceived(TL_EvtPacket_t *shcievt)
return;
}
static void OutputCmdTrace(TL_CmdPacket_t *pCmdBuffer)
{
TL_SHCI_CMD_DBG_MSG("sys cmd: 0x%04X", pCmdBuffer->cmdserial.cmd.cmdcode);
if(pCmdBuffer->cmdserial.cmd.plen != 0)
{
TL_SHCI_CMD_DBG_MSG(" payload:");
TL_SHCI_CMD_DBG_BUF(pCmdBuffer->cmdserial.cmd.payload, pCmdBuffer->cmdserial.cmd.plen, "");
}
TL_SHCI_CMD_DBG_MSG("\r\n");
return;
}
static void OutputRspTrace(TL_EvtPacket_t *p_rsp)
{
switch(p_rsp->evtserial.evt.evtcode)
{
case TL_BLEEVT_CC_OPCODE:
TL_SHCI_CMD_DBG_MSG("sys rsp: 0x%02X", p_rsp->evtserial.evt.evtcode);
TL_SHCI_CMD_DBG_MSG(" cmd opcode: 0x%02X", ((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->cmdcode);
TL_SHCI_CMD_DBG_MSG(" status: 0x%02X", ((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
if((p_rsp->evtserial.evt.plen-4) != 0)
{
TL_SHCI_CMD_DBG_MSG(" payload:");
TL_SHCI_CMD_DBG_BUF(&((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[1], p_rsp->evtserial.evt.plen-4, "");
}
break;
default:
TL_SHCI_CMD_DBG_MSG("unknown sys rsp received: %02X", p_rsp->evtserial.evt.evtcode);
break;
}
TL_SHCI_CMD_DBG_MSG("\r\n");
return;
}
static void OutputEvtTrace(TL_EvtPacket_t *phcievtbuffer)
{
if(phcievtbuffer->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE)
{
TL_SHCI_EVT_DBG_MSG("unknown sys evt received: %02X", phcievtbuffer->evtserial.evt.evtcode);
}
else
{
TL_SHCI_EVT_DBG_MSG("sys evt: 0x%02X", phcievtbuffer->evtserial.evt.evtcode);
TL_SHCI_EVT_DBG_MSG(" subevtcode: 0x%04X", ((TL_AsynchEvt_t*)(phcievtbuffer->evtserial.evt.payload))->subevtcode);
if((phcievtbuffer->evtserial.evt.plen-2) != 0)
{
TL_SHCI_EVT_DBG_MSG(" payload:");
TL_SHCI_EVT_DBG_BUF(((TL_AsynchEvt_t*)(phcievtbuffer->evtserial.evt.payload))->payload, phcievtbuffer->evtserial.evt.plen-2, "");
}
}
TL_SHCI_EVT_DBG_MSG("\r\n");
return;
}
/* Weak implementation ----------------------------------------------------------------*/
MBED_WEAK void shci_cmd_resp_wait(uint32_t timeout)
__WEAK void shci_cmd_resp_wait(uint32_t timeout)
{
(void)timeout;
@ -341,7 +244,7 @@ MBED_WEAK void shci_cmd_resp_wait(uint32_t timeout)
return;
}
MBED_WEAK void shci_cmd_resp_release(uint32_t flag)
__WEAK void shci_cmd_resp_release(uint32_t flag)
{
(void)flag;

29
connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/stm32_wpan_common.h
View File

@ -1,21 +1,21 @@
/**
******************************************************************************
* @file stm32_wpan_common.h
* @author MCD Application Team
* @brief Common file to utilities
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
******************************************************************************
* @file stm32_wpan_common.h
* @author MCD Application Team
* @brief Common file to utilities
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
@ -31,6 +31,7 @@ extern "C" {
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include "cmsis_compiler.h"
/* -------------------------------- *
* Basic definitions *
@ -142,7 +143,7 @@ extern "C" {
#define PACKED_STRUCT struct PACKED__
#elif defined (__ICCARM__)
#define PACKED_STRUCT __packed struct
#elif
#else
#define PACKED_STRUCT __packed struct
#endif

3
connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/stm_list.h
View File

@ -22,8 +22,9 @@
#define _STM_LIST_H_
/* Includes ------------------------------------------------------------------*/
#include "stm32_wpan_common.h"
typedef struct _tListNode {
typedef PACKED_STRUCT _tListNode {
struct _tListNode * next;
struct _tListNode * prev;
} tListNode;

26
connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/tl.h
View File

@ -195,9 +195,9 @@ typedef struct
typedef struct
{
uint8_t *p_LldBleCmdRspBuffer;
uint8_t *p_LldBleM0CmdBuffer;
} TL_LLD_BLE_Config_t;
uint8_t *p_BleLldCmdRspBuffer;
uint8_t *p_BleLldM0CmdBuffer;
} TL_BLE_LLD_Config_t;
typedef struct
{
@ -282,17 +282,17 @@ void TL_LLDTESTS_ReceiveM0Cmd( TL_CmdPacket_t * Notbuffer );
void TL_LLDTESTS_SendM0CmdAck( void );
/******************************************************************************
* LLD BLE
* BLE LLD
******************************************************************************/
void TL_LLD_BLE_Init( TL_LLD_BLE_Config_t *p_Config );
void TL_LLD_BLE_SendCliCmd( void );
void TL_LLD_BLE_ReceiveCliRsp( TL_CmdPacket_t * Notbuffer );
void TL_LLD_BLE_SendCliRspAck( void );
void TL_LLD_BLE_ReceiveM0Cmd( TL_CmdPacket_t * Notbuffer );
void TL_LLD_BLE_SendM0CmdAck( void );
void TL_LLD_BLE_SendCmd( void );
void TL_LLD_BLE_ReceiveRsp( TL_CmdPacket_t * Notbuffer );
void TL_LLD_BLE_SendRspAck( void );
void TL_BLE_LLD_Init( TL_BLE_LLD_Config_t *p_Config );
void TL_BLE_LLD_SendCliCmd( void );
void TL_BLE_LLD_ReceiveCliRsp( TL_CmdPacket_t * Notbuffer );
void TL_BLE_LLD_SendCliRspAck( void );
void TL_BLE_LLD_ReceiveM0Cmd( TL_CmdPacket_t * Notbuffer );
void TL_BLE_LLD_SendM0CmdAck( void );
void TL_BLE_LLD_SendCmd( void );
void TL_BLE_LLD_ReceiveRsp( TL_CmdPacket_t * Notbuffer );
void TL_BLE_LLD_SendRspAck( void );
/******************************************************************************
* MEMORY MANAGER
******************************************************************************/

349
connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/tl_mbox.c
View File

@ -22,28 +22,23 @@
#include "stm32_wpan_common.h"
#include "hw.h"
#include "mbed_toolchain.h"
#include "stm_list.h"
#include "tl.h"
#include "mbox_def.h"
/**
* These traces are not yet supported in an usual way in the delivery package
* They can enabled by adding the definition of TL_MM_DBG_EN in the preprocessor option in the IDE
*/
#if(TL_MM_DBG_EN != 0)
#include "app_conf.h"
#include "dbg_trace.h"
#endif
#if (TL_MM_DBG_EN != 0)
#define TL_MM_DBG__MSG PRINT_MESG_DBG
#else
#define TL_MM_DBG__MSG(...)
#endif
#include "tl_dbg_conf.h"
/* Private typedef -----------------------------------------------------------*/
typedef enum
{
TL_MB_MM_RELEASE_BUFFER,
TL_MB_BLE_CMD,
TL_MB_BLE_CMD_RSP,
TL_MB_BLE_ASYNCH_EVT,
TL_MB_SYS_CMD,
TL_MB_SYS_CMD_RSP,
TL_MB_SYS_ASYNCH_EVT,
} TL_MB_PacketType_t;
/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@ -54,7 +49,7 @@ PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static MB_DeviceInfoTable_t TL_DeviceInfoTa
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static MB_BleTable_t TL_BleTable;
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static MB_ThreadTable_t TL_ThreadTable;
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static MB_LldTestsTable_t TL_LldTestsTable;
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static MB_LldBleTable_t TL_LldBleTable;
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static MB_BleLldTable_t TL_BleLldTable;
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static MB_SysTable_t TL_SysTable;
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static MB_MemManagerTable_t TL_MemManagerTable;
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static MB_TracesTable_t TL_TracesTable;
@ -79,7 +74,7 @@ static void (* SYS_EVT_IoBusCallBackFunction) (TL_EvtPacket_t *phcievt);
/* Global variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void SendFreeBuf( void );
static void OutputMemReleaseTrace(TL_EvtPacket_t * phcievt);
static void OutputDbgTrace(TL_MB_PacketType_t packet_type, uint8_t* buffer);
/* Public Functions Definition ------------------------------------------------------*/
@ -100,7 +95,7 @@ void TL_Init( void )
TL_RefTable.p_ble_table = &TL_BleTable;
TL_RefTable.p_thread_table = &TL_ThreadTable;
TL_RefTable.p_lld_tests_table = &TL_LldTestsTable;
TL_RefTable.p_lld_ble_table = &TL_LldBleTable;
TL_RefTable.p_ble_lld_table = &TL_BleLldTable;
TL_RefTable.p_sys_table = &TL_SysTable;
TL_RefTable.p_mem_manager_table = &TL_MemManagerTable;
TL_RefTable.p_traces_table = &TL_TracesTable;
@ -144,6 +139,8 @@ int32_t TL_BLE_SendCmd( uint8_t* buffer, uint16_t size )
((TL_CmdPacket_t*)(TL_RefTable.p_ble_table->pcmd_buffer))->cmdserial.type = TL_BLECMD_PKT_TYPE;
OutputDbgTrace(TL_MB_BLE_CMD, TL_RefTable.p_ble_table->pcmd_buffer);
HW_IPCC_BLE_SendCmd();
return 0;
@ -157,6 +154,15 @@ void HW_IPCC_BLE_RxEvtNot(void)
{
LST_remove_head (&EvtQueue, (tListNode **)&phcievt);
if ( ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CS_OPCODE) || ((phcievt->evtserial.evt.evtcode) == TL_BLEEVT_CC_OPCODE ) )
{
OutputDbgTrace(TL_MB_BLE_CMD_RSP, (uint8_t*)phcievt);
}
else
{
OutputDbgTrace(TL_MB_BLE_ASYNCH_EVT, (uint8_t*)phcievt);
}
BLE_IoBusEvtCallBackFunction(phcievt);
}
@ -211,6 +217,8 @@ int32_t TL_SYS_SendCmd( uint8_t* buffer, uint16_t size )
((TL_CmdPacket_t *)(TL_RefTable.p_sys_table->pcmd_buffer))->cmdserial.type = TL_SYSCMD_PKT_TYPE;
OutputDbgTrace(TL_MB_SYS_CMD, TL_RefTable.p_sys_table->pcmd_buffer);
HW_IPCC_SYS_SendCmd();
return 0;
@ -218,6 +226,8 @@ int32_t TL_SYS_SendCmd( uint8_t* buffer, uint16_t size )
void HW_IPCC_SYS_CmdEvtNot(void)
{
OutputDbgTrace(TL_MB_SYS_CMD_RSP, (uint8_t*)(TL_RefTable.p_sys_table->pcmd_buffer) );
SYS_CMD_IoBusCallBackFunction( (TL_EvtPacket_t*)(TL_RefTable.p_sys_table->pcmd_buffer) );
return;
@ -230,6 +240,9 @@ void HW_IPCC_SYS_EvtNot( void )
while(LST_is_empty(&SystemEvtQueue) == FALSE)
{
LST_remove_head (&SystemEvtQueue, (tListNode **)&p_evt);
OutputDbgTrace(TL_MB_SYS_ASYNCH_EVT, (uint8_t*)p_evt );
SYS_EVT_IoBusCallBackFunction( p_evt );
}
@ -312,9 +325,9 @@ void HW_IPCC_THREAD_CliEvtNot( void )
return;
}
MBED_WEAK void TL_OT_CmdEvtReceived( TL_EvtPacket_t * Otbuffer ){};
MBED_WEAK void TL_THREAD_NotReceived( TL_EvtPacket_t * Notbuffer ){};
MBED_WEAK void TL_THREAD_CliNotReceived( TL_EvtPacket_t * Notbuffer ){};
__WEAK void TL_OT_CmdEvtReceived( TL_EvtPacket_t * Otbuffer ){};
__WEAK void TL_THREAD_NotReceived( TL_EvtPacket_t * Notbuffer ){};
__WEAK void TL_THREAD_CliNotReceived( TL_EvtPacket_t * Notbuffer ){};
#endif /* THREAD_WB */
@ -365,80 +378,80 @@ void TL_LLDTESTS_SendM0CmdAck( void )
return;
}
MBED_WEAK void TL_LLDTESTS_ReceiveCliRsp( TL_CmdPacket_t * Notbuffer ){};
MBED_WEAK void TL_LLDTESTS_ReceiveM0Cmd( TL_CmdPacket_t * Notbuffer ){};
__WEAK void TL_LLDTESTS_ReceiveCliRsp( TL_CmdPacket_t * Notbuffer ){};
__WEAK void TL_LLDTESTS_ReceiveM0Cmd( TL_CmdPacket_t * Notbuffer ){};
#endif /* LLD_TESTS_WB */
/******************************************************************************
* LLD BLE
* BLE LLD
******************************************************************************/
#ifdef LLD_BLE_WB
void TL_LLD_BLE_Init( TL_LLD_BLE_Config_t *p_Config )
#ifdef BLE_LLD_WB
void TL_BLE_LLD_Init( TL_BLE_LLD_Config_t *p_Config )
{
MB_LldBleTable_t * p_lld_ble_table;
MB_BleLldTable_t * p_ble_lld_table;
p_lld_ble_table = TL_RefTable.p_lld_ble_table;
p_lld_ble_table->cmdrsp_buffer = p_Config->p_LldBleCmdRspBuffer;
p_lld_ble_table->m0cmd_buffer = p_Config->p_LldBleM0CmdBuffer;
HW_IPCC_LLD_BLE_Init();
p_ble_lld_table = TL_RefTable.p_ble_lld_table;
p_ble_lld_table->cmdrsp_buffer = p_Config->p_BleLldCmdRspBuffer;
p_ble_lld_table->m0cmd_buffer = p_Config->p_BleLldM0CmdBuffer;
HW_IPCC_BLE_LLD_Init();
return;
}
void TL_LLD_BLE_SendCliCmd( void )
void TL_BLE_LLD_SendCliCmd( void )
{
((TL_CmdPacket_t *)(TL_RefTable.p_lld_ble_table->cmdrsp_buffer))->cmdserial.type = TL_CLICMD_PKT_TYPE;
HW_IPCC_LLD_BLE_SendCliCmd();
((TL_CmdPacket_t *)(TL_RefTable.p_ble_lld_table->cmdrsp_buffer))->cmdserial.type = TL_CLICMD_PKT_TYPE;
HW_IPCC_BLE_LLD_SendCliCmd();
return;
}
void HW_IPCC_LLD_BLE_ReceiveCliRsp( void )
void HW_IPCC_BLE_LLD_ReceiveCliRsp( void )
{
TL_LLD_BLE_ReceiveCliRsp( (TL_CmdPacket_t*)(TL_RefTable.p_lld_ble_table->cmdrsp_buffer) );
TL_BLE_LLD_ReceiveCliRsp( (TL_CmdPacket_t*)(TL_RefTable.p_ble_lld_table->cmdrsp_buffer) );
return;
}
void TL_LLD_BLE_SendCliRspAck( void )
void TL_BLE_LLD_SendCliRspAck( void )
{
HW_IPCC_LLD_BLE_SendCliRspAck();
HW_IPCC_BLE_LLD_SendCliRspAck();
return;
}
void HW_IPCC_LLD_BLE_ReceiveM0Cmd( void )
void HW_IPCC_BLE_LLD_ReceiveM0Cmd( void )
{
TL_LLD_BLE_ReceiveM0Cmd( (TL_CmdPacket_t*)(TL_RefTable.p_lld_ble_table->m0cmd_buffer) );
TL_BLE_LLD_ReceiveM0Cmd( (TL_CmdPacket_t*)(TL_RefTable.p_ble_lld_table->m0cmd_buffer) );
return;
}
void TL_LLD_BLE_SendM0CmdAck( void )
void TL_BLE_LLD_SendM0CmdAck( void )
{
HW_IPCC_LLD_BLE_SendM0CmdAck();
HW_IPCC_BLE_LLD_SendM0CmdAck();
return;
}
MBED_WEAK void TL_LLD_BLE_ReceiveCliRsp( TL_CmdPacket_t * Notbuffer ){};
MBED_WEAK void TL_LLD_BLE_ReceiveM0Cmd( TL_CmdPacket_t * Notbuffer ){};
__WEAK void TL_BLE_LLD_ReceiveCliRsp( TL_CmdPacket_t * Notbuffer ){};
__WEAK void TL_BLE_LLD_ReceiveM0Cmd( TL_CmdPacket_t * Notbuffer ){};
/* Transparent Mode */
void TL_LLD_BLE_SendCmd( void )
void TL_BLE_LLD_SendCmd( void )
{
((TL_CmdPacket_t *)(TL_RefTable.p_lld_ble_table->cmdrsp_buffer))->cmdserial.type = TL_CLICMD_PKT_TYPE;
HW_IPCC_LLD_BLE_SendCmd();
((TL_CmdPacket_t *)(TL_RefTable.p_ble_lld_table->cmdrsp_buffer))->cmdserial.type = TL_CLICMD_PKT_TYPE;
HW_IPCC_BLE_LLD_SendCmd();
return;
}
void HW_IPCC_LLD_BLE_ReceiveRsp( void )
void HW_IPCC_BLE_LLD_ReceiveRsp( void )
{
TL_LLD_BLE_ReceiveRsp( (TL_CmdPacket_t*)(TL_RefTable.p_lld_ble_table->cmdrsp_buffer) );
TL_BLE_LLD_ReceiveRsp( (TL_CmdPacket_t*)(TL_RefTable.p_ble_lld_table->cmdrsp_buffer) );
return;
}
void TL_LLD_BLE_SendRspAck( void )
void TL_BLE_LLD_SendRspAck( void )
{
HW_IPCC_LLD_BLE_SendRspAck();
HW_IPCC_BLE_LLD_SendRspAck();
return;
}
#endif /* LLD_BLE_WB */
#endif /* BLE_LLD_WB */
#ifdef MAC_802_15_4_WB
/******************************************************************************
@ -490,8 +503,8 @@ void HW_IPCC_MAC_802_15_4_EvtNot( void )
return;
}
MBED_WEAK void TL_MAC_802_15_4_CmdEvtReceived( TL_EvtPacket_t * Otbuffer ){};
MBED_WEAK void TL_MAC_802_15_4_NotReceived( TL_EvtPacket_t * Notbuffer ){};
__WEAK void TL_MAC_802_15_4_CmdEvtReceived( TL_EvtPacket_t * Otbuffer ){};
__WEAK void TL_MAC_802_15_4_NotReceived( TL_EvtPacket_t * Notbuffer ){};
#endif
#ifdef ZIGBEE_WB
@ -567,8 +580,8 @@ void TL_ZIGBEE_SendM4AckToM0Request(void)
}
MBED_WEAK void TL_ZIGBEE_CmdEvtReceived( TL_EvtPacket_t * Otbuffer ){};
MBED_WEAK void TL_ZIGBEE_NotReceived( TL_EvtPacket_t * Notbuffer ){};
__WEAK void TL_ZIGBEE_CmdEvtReceived( TL_EvtPacket_t * Otbuffer ){};
__WEAK void TL_ZIGBEE_NotReceived( TL_EvtPacket_t * Notbuffer ){};
#endif
@ -600,7 +613,7 @@ void TL_MM_EvtDone(TL_EvtPacket_t * phcievt)
{
LST_insert_tail(&LocalFreeBufQueue, (tListNode *)phcievt);
OutputMemReleaseTrace(phcievt);
OutputDbgTrace(TL_MB_MM_RELEASE_BUFFER, (uint8_t*)phcievt);
HW_IPCC_MM_SendFreeBuf( SendFreeBuf );
@ -620,39 +633,6 @@ static void SendFreeBuf( void )
return;
}
static void OutputMemReleaseTrace(TL_EvtPacket_t * phcievt)
{
switch(phcievt->evtserial.evt.evtcode)
{
case TL_BLEEVT_CS_OPCODE:
TL_MM_DBG__MSG("mm evt released: 0x%02X", phcievt->evtserial.evt.evtcode);
TL_MM_DBG__MSG(" cmd opcode: 0x%04X", ((TL_CsEvt_t*)(phcievt->evtserial.evt.payload))->cmdcode);
TL_MM_DBG__MSG(" buffer addr: 0x%08X", phcievt);
break;
case TL_BLEEVT_CC_OPCODE:
TL_MM_DBG__MSG("mm evt released: 0x%02X", phcievt->evtserial.evt.evtcode);
TL_MM_DBG__MSG(" cmd opcode: 0x%04X", ((TL_CcEvt_t*)(phcievt->evtserial.evt.payload))->cmdcode);
TL_MM_DBG__MSG(" buffer addr: 0x%08X", phcievt);
break;
case TL_BLEEVT_VS_OPCODE:
TL_MM_DBG__MSG("mm evt released: 0x%02X", phcievt->evtserial.evt.evtcode);
TL_MM_DBG__MSG(" subevtcode: 0x%04X", ((TL_AsynchEvt_t*)(phcievt->evtserial.evt.payload))->subevtcode);
TL_MM_DBG__MSG(" buffer addr: 0x%08X", phcievt);
break;
default:
TL_MM_DBG__MSG("mm evt released: 0x%02X", phcievt->evtserial.evt.evtcode);
TL_MM_DBG__MSG(" buffer addr: 0x%08X", phcievt);
break;
}
TL_MM_DBG__MSG("\r\n");
return;
}
/******************************************************************************
* TRACES
******************************************************************************/
@ -680,9 +660,192 @@ void HW_IPCC_TRACES_EvtNot(void)
return;
}
MBED_WEAK void TL_TRACES_EvtReceived( TL_EvtPacket_t * hcievt )
__WEAK void TL_TRACES_EvtReceived( TL_EvtPacket_t * hcievt )
{
(void)(hcievt);
}
/******************************************************************************
* DEBUG INFORMATION
******************************************************************************/
static void OutputDbgTrace(TL_MB_PacketType_t packet_type, uint8_t* buffer)
{
TL_EvtPacket_t *p_evt_packet;
TL_CmdPacket_t *p_cmd_packet;
switch(packet_type)
{
case TL_MB_MM_RELEASE_BUFFER:
p_evt_packet = (TL_EvtPacket_t*)buffer;
switch(p_evt_packet->evtserial.evt.evtcode)
{
case TL_BLEEVT_CS_OPCODE:
TL_MM_DBG_MSG("mm evt released: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
TL_MM_DBG_MSG(" cmd opcode: 0x%04X", ((TL_CsEvt_t*)(p_evt_packet->evtserial.evt.payload))->cmdcode);
TL_MM_DBG_MSG(" buffer addr: 0x%08X", p_evt_packet);
break;
case TL_BLEEVT_CC_OPCODE:
TL_MM_DBG_MSG("mm evt released: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
TL_MM_DBG_MSG(" cmd opcode: 0x%04X", ((TL_CcEvt_t*)(p_evt_packet->evtserial.evt.payload))->cmdcode);
TL_MM_DBG_MSG(" buffer addr: 0x%08X", p_evt_packet);
break;
case TL_BLEEVT_VS_OPCODE:
TL_MM_DBG_MSG("mm evt released: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
TL_MM_DBG_MSG(" subevtcode: 0x%04X", ((TL_AsynchEvt_t*)(p_evt_packet->evtserial.evt.payload))->subevtcode);
TL_MM_DBG_MSG(" buffer addr: 0x%08X", p_evt_packet);
break;
default:
TL_MM_DBG_MSG("mm evt released: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
TL_MM_DBG_MSG(" buffer addr: 0x%08X", p_evt_packet);
break;
}
TL_MM_DBG_MSG("\r\n");
break;
case TL_MB_BLE_CMD:
p_cmd_packet = (TL_CmdPacket_t*)buffer;
TL_HCI_CMD_DBG_MSG("ble cmd: 0x%04X", p_cmd_packet->cmdserial.cmd.cmdcode);
if(p_cmd_packet->cmdserial.cmd.plen != 0)
{
TL_HCI_CMD_DBG_MSG(" payload:");
TL_HCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, "");
}
TL_HCI_CMD_DBG_MSG("\r\n");
TL_HCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE);
break;
case TL_MB_BLE_CMD_RSP:
p_evt_packet = (TL_EvtPacket_t*)buffer;
switch(p_evt_packet->evtserial.evt.evtcode)
{
case TL_BLEEVT_CS_OPCODE:
TL_HCI_CMD_DBG_MSG("ble rsp: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
TL_HCI_CMD_DBG_MSG(" cmd opcode: 0x%04X", ((TL_CsEvt_t*)(p_evt_packet->evtserial.evt.payload))->cmdcode);
TL_HCI_CMD_DBG_MSG(" numhci: 0x%02X", ((TL_CsEvt_t*)(p_evt_packet->evtserial.evt.payload))->numcmd);
TL_HCI_CMD_DBG_MSG(" status: 0x%02X", ((TL_CsEvt_t*)(p_evt_packet->evtserial.evt.payload))->status);
break;
case TL_BLEEVT_CC_OPCODE:
TL_HCI_CMD_DBG_MSG("ble rsp: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
TL_HCI_CMD_DBG_MSG(" cmd opcode: 0x%04X", ((TL_CcEvt_t*)(p_evt_packet->evtserial.evt.payload))->cmdcode);
TL_HCI_CMD_DBG_MSG(" numhci: 0x%02X", ((TL_CcEvt_t*)(p_evt_packet->evtserial.evt.payload))->numcmd);
TL_HCI_CMD_DBG_MSG(" status: 0x%02X", ((TL_CcEvt_t*)(p_evt_packet->evtserial.evt.payload))->payload[0]);
if((p_evt_packet->evtserial.evt.plen-4) != 0)
{
TL_HCI_CMD_DBG_MSG(" payload:");
TL_HCI_CMD_DBG_BUF(&((TL_CcEvt_t*)(p_evt_packet->evtserial.evt.payload))->payload[1], p_evt_packet->evtserial.evt.plen-4, "");
}
break;
default:
TL_HCI_CMD_DBG_MSG("unknown ble rsp received: %02X", p_evt_packet->evtserial.evt.evtcode);
break;
}
TL_HCI_CMD_DBG_MSG("\r\n");
TL_HCI_CMD_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE);
break;
case TL_MB_BLE_ASYNCH_EVT:
p_evt_packet = (TL_EvtPacket_t*)buffer;
if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE)
{
TL_HCI_EVT_DBG_MSG("ble evt: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
if((p_evt_packet->evtserial.evt.plen) != 0)
{
TL_HCI_EVT_DBG_MSG(" payload:");
TL_HCI_EVT_DBG_BUF(p_evt_packet->evtserial.evt.payload, p_evt_packet->evtserial.evt.plen, "");
}
}
else
{
TL_HCI_EVT_DBG_MSG("ble evt: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
TL_HCI_EVT_DBG_MSG(" subevtcode: 0x%04X", ((TL_AsynchEvt_t*)(p_evt_packet->evtserial.evt.payload))->subevtcode);
if((p_evt_packet->evtserial.evt.plen-2) != 0)
{
TL_HCI_EVT_DBG_MSG(" payload:");
TL_HCI_EVT_DBG_BUF(((TL_AsynchEvt_t*)(p_evt_packet->evtserial.evt.payload))->payload, p_evt_packet->evtserial.evt.plen-2, "");
}
}
TL_HCI_EVT_DBG_MSG("\r\n");
TL_HCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE);
break;
case TL_MB_SYS_CMD:
p_cmd_packet = (TL_CmdPacket_t*)buffer;
TL_SHCI_CMD_DBG_MSG("sys cmd: 0x%04X", p_cmd_packet->cmdserial.cmd.cmdcode);
if(p_cmd_packet->cmdserial.cmd.plen != 0)
{
TL_SHCI_CMD_DBG_MSG(" payload:");
TL_SHCI_CMD_DBG_BUF(p_cmd_packet->cmdserial.cmd.payload, p_cmd_packet->cmdserial.cmd.plen, "");
}
TL_SHCI_CMD_DBG_MSG("\r\n");
TL_SHCI_CMD_DBG_RAW(&p_cmd_packet->cmdserial, p_cmd_packet->cmdserial.cmd.plen+TL_CMD_HDR_SIZE);
break;
case TL_MB_SYS_CMD_RSP:
p_evt_packet = (TL_EvtPacket_t*)buffer;
switch(p_evt_packet->evtserial.evt.evtcode)
{
case TL_BLEEVT_CC_OPCODE:
TL_SHCI_CMD_DBG_MSG("sys rsp: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
TL_SHCI_CMD_DBG_MSG(" cmd opcode: 0x%02X", ((TL_CcEvt_t*)(p_evt_packet->evtserial.evt.payload))->cmdcode);
TL_SHCI_CMD_DBG_MSG(" status: 0x%02X", ((TL_CcEvt_t*)(p_evt_packet->evtserial.evt.payload))->payload[0]);
if((p_evt_packet->evtserial.evt.plen-4) != 0)
{
TL_SHCI_CMD_DBG_MSG(" payload:");
TL_SHCI_CMD_DBG_BUF(&((TL_CcEvt_t*)(p_evt_packet->evtserial.evt.payload))->payload[1], p_evt_packet->evtserial.evt.plen-4, "");
}
break;
default:
TL_SHCI_CMD_DBG_MSG("unknown sys rsp received: %02X", p_evt_packet->evtserial.evt.evtcode);
break;
}
TL_SHCI_CMD_DBG_MSG("\r\n");
TL_SHCI_CMD_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE);
break;
case TL_MB_SYS_ASYNCH_EVT:
p_evt_packet = (TL_EvtPacket_t*)buffer;
if(p_evt_packet->evtserial.evt.evtcode != TL_BLEEVT_VS_OPCODE)
{
TL_SHCI_EVT_DBG_MSG("unknown sys evt received: %02X", p_evt_packet->evtserial.evt.evtcode);
}
else
{
TL_SHCI_EVT_DBG_MSG("sys evt: 0x%02X", p_evt_packet->evtserial.evt.evtcode);
TL_SHCI_EVT_DBG_MSG(" subevtcode: 0x%04X", ((TL_AsynchEvt_t*)(p_evt_packet->evtserial.evt.payload))->subevtcode);
if((p_evt_packet->evtserial.evt.plen-2) != 0)
{
TL_SHCI_EVT_DBG_MSG(" payload:");
TL_SHCI_EVT_DBG_BUF(((TL_AsynchEvt_t*)(p_evt_packet->evtserial.evt.payload))->payload, p_evt_packet->evtserial.evt.plen-2, "");
}
}
TL_SHCI_EVT_DBG_MSG("\r\n");
TL_SHCI_EVT_DBG_RAW(&p_evt_packet->evtserial, p_evt_packet->evtserial.evt.plen+TL_EVT_HDR_SIZE);
break;
default:
break;
}
return;
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
targets/TARGET_STM/README.md
View File

@ -74,7 +74,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br
| L1 | 1.10.2 | https://github.com/STMicroelectronics/STM32CubeL1 |
| L4 | 1.17.0 | https://github.com/STMicroelectronics/STM32CubeL4 |
| L5 | 1.3.0 | https://github.com/STMicroelectronics/STM32CubeL5 |
| WB | 1.8.0 | https://github.com/STMicroelectronics/STM32CubeWB |
| WB | 1.11.1 | https://github.com/STMicroelectronics/STM32CubeWB |
| WL | 1.0.0 | https://github.com/STMicroelectronics/STM32CubeWL |
In Mbed OS repository, we try to minimize the difference between "official" and copied files.

25
targets/TARGET_STM/TARGET_STM32WB/CMakeLists.txt
View File

@ -1,14 +1,26 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(TARGET_STM32WB50xx EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB55xx EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB5Mxx EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB10xC EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB15xC EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB30xE EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB35xC EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB35xE EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB50xG EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB55xC EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB55xE EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB55xG EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB55xY EXCLUDE_FROM_ALL)
add_subdirectory(TARGET_STM32WB5MxG EXCLUDE_FROM_ALL)
add_subdirectory(STM32Cube_FW EXCLUDE_FROM_ALL)
add_library(mbed-stm32wb INTERFACE)
target_include_directories(mbed-stm32wb
INTERFACE
.
)
target_sources(mbed-stm32wb
INTERFACE
analogin_device.c
@ -20,9 +32,4 @@ target_sources(mbed-stm32wb
wb_sleep.c
)
target_include_directories(mbed-stm32wb
INTERFACE
.
)
target_link_libraries(mbed-stm32wb INTERFACE mbed-stm mbed-stm32wbcube-fw)

79
targets/TARGET_STM/TARGET_STM32WB/README.md
View File

@ -1,3 +1,14 @@
* [STM32WB family](#stm32wb-family)
* [Supported boards](#supported-boards)
* [NUCLEO_WB55RG](#nucleo_wb55rg)
* [DISCO_WB5MMG (STM32WB5MM-DK)](#disco_wb5mmg-stm32wb5mm-dk)
* [BLE](#ble)
* [MBED-OS support](#mbed-os-support)
* [mbed-trace support](#mbed-trace-support)
* [BLE FW update](#ble-fw-update)
* [BLE FW flashing procedure](#ble-fw-flashing-procedure)
# STM32WB family
[st.com STM32WB family page](https://www.st.com/en/microcontrollers-microprocessors/stm32wb-series.html)
@ -9,13 +20,15 @@ This ST MCU family is dual-core : based on an Arm Cortex-M4 core and an Arm Cort
# Supported boards
## NUCLEO_WB55RG
## NUCLEO_WB55RG (NUCLEO-WB55RG)
[st.com STM32WB55RG MCU page](https://www.st.com/en/microcontrollers-microprocessors/stm32wb55rg.html)
[st.com NUCLEO page](https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html)
[st.com NUCLEO board page](https://www.st.com/en/evaluation-tools/nucleo-wb55rg.html)
[mbed.com NUCLEO page](https://os.mbed.com/platforms/ST-Nucleo-WB55RG/)
[st.com Pack board page](https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html)
[mbed.com platform page](https://os.mbed.com/platforms/ST-Nucleo-WB55RG/)
- Total FLASH is 1MB, but note that it is shared by M4 and M0 cores.
- mbed-os application size is then limited to 768 KB
@ -30,6 +43,32 @@ SRAM1 is dedicated for M4 core, and then for mbed-os applications.
SRAM2 is dedicated for M0 core and inter CPU communication, and then can not be addressed.
## DISCO_WB5MMG (STM32WB5MM-DK)
[st.com STM32WB5MMG module page](https://www.st.com/en/microcontrollers-microprocessors/stm32wb5mmg.html)
[st.com DISCO board page](https://www.st.com/en/evaluation-tools/stm32wb5mm-dk.html)
[mbed.com platform page](https://os.mbed.com/platforms/DISCO-WB5MMG/)
- Total FLASH is 1MB, but note that it is shared by M4 and M0 cores.
- mbed-os application size is then limited to 768 KB
- RAM: 256 KB
- SRAM1: 192 KB
- SRAM2a: 32 KB
- SRAM2b: 32 KB
SRAM1 is dedicated for M4 core, and then for mbed-os applications.
SRAM2 is dedicated for M0 core and inter CPU communication, and then can not be addressed.
NB: MBED CLI1 tool can be used thanks to this command:
```
mbedls -m 0884:DISCO_WB5MMG
```
# BLE
## MBED-OS support
@ -41,8 +80,8 @@ Note that the BLE controller firmware running on the cortex-M0 is the same as in
- within mbed, the controller will run only the below-HCI part
- within STcubeFW (and STM32WPAN middleware), it can run also up to GATT / GAP layers ...
Official ST Application Note AN5289: Building wireless applications with STM32WB Series microcontrollers :
https://www.st.com/resource/en/application_note/dm00598033-building-wireless-applications-with-stm32wb-series-microcontrollers-stmicroelectronics.pdf
Official ST Application Note :
[AN5289: Building wireless applications with STM32WB Series microcontrollers](https://www.st.com/resource/en/application_note/dm00598033-building-wireless-applications-with-stm32wb-series-microcontrollers-stmicroelectronics.pdf)
@ -52,19 +91,19 @@ trace group: BLE_WB
example:
````
[INFO][BLE_WB]: WIRELESS COPROCESSOR FW VERSION ID = 1.8.0
[INFO][BLE_WB]: WIRELESS COPROCESSOR FW STACK TYPE = 1
[DBG ][BLE_WB]: mbox_write type:1, len:3
[INFO][BLE_WB]: TX>> BLE CMD
[DBG ][BLE_WB]: Type 0x1
[DBG ][BLE_WB]: Cmd 0xc03
[DBG ][BLE_WB]: Len 0D]
[INFO][BLWB]: WIRELESS COPROCESSOR FW VERSION ID = 1.11.1
[INFO][BLWB]: WIRELESS COPROCESSOR FW STACK TYPE = 1
[DBG ][BLWB]: mbox_write type:1, len:3
[INFO][BLWB]: TX>> BLE CMD
[DBG ][BLWB]: Type 0x1
[DBG ][BLWB]: Cmd 0xc03
[DBG ][BLWB]: Len 0D]
````
## BLE FW update
Official ST Application Note AN5185: ST firmware upgrade services for STM32WB Series :
http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00513965.pdf
Official ST Application Note :
[AN5185: ST firmware upgrade services for STM32WB Series](http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00513965.pdf)
Latest BLE FW :
https://github.com/STMicroelectronics/STM32CubeWB/blob/master/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Stack_full_fw.bin
@ -105,7 +144,7 @@ Firmware delete finished
fwdelete command execution finished
```
- STEP 4 : Read and upgrade FUS Version
- STEP 4 : Read FUS Version
```
$ STM32_Programmer_CLI.exe -c port=usb1 -r32 0x20030030 1
@ -121,17 +160,19 @@ Reading 32-bit memory content
- STEP 5A if last result is 00050300 : Download new FUS :
```
$ ./STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade stm32wb5x_FUS_fw_1_0_2.bin 0x080EC000 firstinstall=0
$ ./STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade stm32wb5x_FUS_fw_for_fus_0_5_3.bin 0x080EC000 firstinstall=0
```
- STEP 5B if last result is 01000100 or 01000200 : Download new FUS :
```
$ STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade stm32wb5x_FUS_fw.bin 0x080EC000 firstinstall=0
...
Firmware Upgrade Success
```
- STEP 4 (to check) : Read and upgrade FUS Version
- STEP 4 (to check) : Read FUS Version
```
$ STM32_Programmer_CLI.exe -c port=usb1 -r32 0x20030030 1
@ -140,14 +181,14 @@ Reading 32-bit memory content
Size : 4 Bytes
Address: : 0x20030030
0x20030030 : 01010000
0x20030030 : 01020000
```
- STEP 6 : Download new wireless stack :
```
$ STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade stm32wb5x_BLE_Stack_full_fw.bin 0x080CB000 firstinstall=1
$ STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade stm32wb5x_BLE_Stack_full_fw.bin 0x080CA000 firstinstall=1
...
Download firmware image at address 0x80cb000 ...

10856
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb10xx.h Normal file
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File diff suppressed because it is too large Load Diff

10986
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb15xx.h Normal file
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File diff suppressed because it is too large Load Diff

6
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb30xx.h
View File

@ -17,10 +17,10 @@
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
@ -51,7 +51,7 @@
#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
#define __FPU_PRESENT 1 /*!< FPU present */
/**
* @}
*/

12
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb35xx.h
View File

@ -17,10 +17,10 @@
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
@ -51,7 +51,7 @@
#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
#define __FPU_PRESENT 1 /*!< FPU present */
/**
* @}
*/
@ -3469,9 +3469,6 @@ typedef struct
#define EXTI_IMR2_IM42_Pos (10U)
#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< CPU1 Interrupt Mask on line 42 */
#define EXTI_IMR2_IM43_Pos (11U)
#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< CPU1 Interrupt Mask on line 43 */
#define EXTI_IMR2_IM44_Pos (12U)
#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< CPU1 Interrupt Mask on line 44 */
@ -3687,9 +3684,6 @@ typedef struct
#define EXTI_C2IMR2_IM42_Pos (10U)
#define EXTI_C2IMR2_IM42_Msk (0x1UL << EXTI_C2IMR2_IM42_Pos) /*!< 0x00000400 */
#define EXTI_C2IMR2_IM42 EXTI_C2IMR2_IM42_Msk /*!< CPU2 Interrupt Mask on line 42 */
#define EXTI_C2IMR2_IM43_Pos (11U)
#define EXTI_C2IMR2_IM43_Msk (0x1UL << EXTI_C2IMR2_IM43_Pos) /*!< 0x00000800 */
#define EXTI_C2IMR2_IM43 EXTI_C2IMR2_IM43_Msk /*!< CPU2 Interrupt Mask on line 43 */
#define EXTI_C2IMR2_IM44_Pos (12U)
#define EXTI_C2IMR2_IM44_Msk (0x1UL << EXTI_C2IMR2_IM44_Pos) /*!< 0x00001000 */
#define EXTI_C2IMR2_IM44 EXTI_C2IMR2_IM44_Msk /*!< CPU2 Interrupt Mask on line 44 */

9
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb50xx.h
View File

@ -17,10 +17,10 @@
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
@ -51,7 +51,7 @@
#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
#define __FPU_PRESENT 1 /*!< FPU present */
/**
* @}
*/
@ -6347,9 +6347,6 @@ typedef struct
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
#define RCC_CR_CSSON_Pos (19U)
#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */

9
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb55xx.h
View File

@ -17,10 +17,10 @@
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
@ -51,7 +51,7 @@
#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */ // MBED
#define __FPU_PRESENT 1 /*!< FPU present */
/**
* @}
*/
@ -7325,9 +7325,6 @@ typedef struct
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
#define RCC_CR_CSSON_Pos (19U)
#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */

11
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb5mxx.h
View File

@ -17,10 +17,10 @@
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
@ -51,9 +51,7 @@
#define __VTOR_PRESENT 1U /*!< Vector Table Register supported */
#define __NVIC_PRIO_BITS 4U /*!< STM32WBxx uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#ifndef __FPU_PRESENT
#define __FPU_PRESENT 1U /*!< FPU present */
#endif
#define __FPU_PRESENT 1 /*!< FPU present */
/**
* @}
*/
@ -7327,9 +7325,6 @@ typedef struct
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
#define RCC_CR_CSSON_Pos (19U)
#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */

10
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wbxx.h
View File

@ -19,10 +19,10 @@
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
@ -69,7 +69,7 @@
* @brief CMSIS Device version number
*/
#define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */
#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\
@ -95,6 +95,10 @@
#include "stm32wb35xx.h"
#elif defined(STM32WB30xx)
#include "stm32wb30xx.h"
#elif defined(STM32WB15xx)
#include "stm32wb15xx.h"
#elif defined(STM32WB10xx)
#include "stm32wb10xx.h"
#else
#error "Please select first the target STM32WBxx device used in your application, for instance xxx (in stm32wbxx.h file)"
#endif

6
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/system_stm32wbxx.h
View File

@ -9,10 +9,10 @@
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* This software component is licensed by ST under Apache License, Version 2.0,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
* opensource.org/licenses/Apache-2.0
*
******************************************************************************
*/
@ -64,7 +64,7 @@ extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB10xx)
extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */
#endif
/**

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMakeLists.txt
View File

@ -5,7 +5,6 @@ add_library(mbed-stm32wbcube-fw INTERFACE)
target_sources(mbed-stm32wbcube-fw
INTERFACE
otp.c
STM32WBxx_HAL_Driver/stm32wbxx_hal.c
STM32WBxx_HAL_Driver/stm32wbxx_hal_adc.c
STM32WBxx_HAL_Driver/stm32wbxx_hal_adc_ex.c
@ -75,8 +74,9 @@ target_sources(mbed-stm32wbcube-fw
STM32WBxx_HAL_Driver/stm32wbxx_ll_usart.c
STM32WBxx_HAL_Driver/stm32wbxx_ll_usb.c
STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
stm32_lpm_if.c
system_stm32wbxx.c
otp.c
stm32_lpm_if.c
)
target_include_directories(mbed-stm32wbcube-fw

178
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/Legacy/stm32_hal_legacy.h
View File

@ -23,7 +23,7 @@
#define STM32_HAL_LEGACY
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@ -38,7 +38,6 @@
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
/**
* @}
*/
@ -383,7 +382,6 @@
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
/**
* @}
*/
@ -596,24 +594,24 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
@ -774,49 +772,6 @@
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
/** @brief Constants defining the events that can be selected to configure the
* set/reset crossbar of a timer output
*/
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
/** @brief Constants defining the event filtering applied to external events
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
@ -896,7 +851,6 @@
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
/**
* @}
*/
@ -969,6 +923,11 @@
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
#if defined(STM32L4) || defined(STM32L5)
#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
#elif defined(STM32G4)
#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
#endif
/**
* @}
@ -980,15 +939,15 @@
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32H7)
#define I2S_IT_TXE I2S_IT_TXP
#define I2S_IT_RXNE I2S_IT_RXP
#define I2S_IT_TXE I2S_IT_TXP
#define I2S_IT_RXNE I2S_IT_RXP
#define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP
#define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP
#endif
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
@ -1023,7 +982,7 @@
/**
* @}
*/
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
@ -1123,16 +1082,16 @@
#if defined(STM32H7)
#define SPI_FLAG_TXE SPI_FLAG_TXP
#define SPI_FLAG_RXNE SPI_FLAG_RXP
#define SPI_FLAG_TXE SPI_FLAG_TXP
#define SPI_FLAG_RXNE SPI_FLAG_RXP
#define SPI_IT_TXE SPI_IT_TXP
#define SPI_IT_RXNE SPI_IT_RXP
#define SPI_IT_TXE SPI_IT_TXP
#define SPI_IT_RXNE SPI_IT_RXP
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#endif /* STM32H7 */
@ -1459,7 +1418,7 @@
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
@ -1481,7 +1440,7 @@
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
@ -1495,7 +1454,8 @@
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
@ -1503,7 +1463,8 @@
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
@ -1526,9 +1487,9 @@
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
/**
/**
* @}
*/
*/
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
@ -1538,7 +1499,8 @@
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
@ -1563,9 +1525,9 @@
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
#endif /* STM32F4 */
/**
/**
* @}
*/
*/
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
@ -1620,9 +1582,9 @@
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
/**
/**
* @}
*/
*/
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
@ -1871,15 +1833,15 @@
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
#if defined(STM32H7)
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
#else
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
#endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
@ -2090,8 +2052,8 @@
*/
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
((WAVE) == DAC_WAVE_NOISE)|| \
((WAVE) == DAC_WAVE_TRIANGLE))
((WAVE) == DAC_WAVE_NOISE)|| \
((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
@ -2147,7 +2109,7 @@
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
#if defined(STM32H7)
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#endif
/**
@ -2284,7 +2246,8 @@
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
@ -3252,7 +3215,7 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@ -3381,7 +3344,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@ -3401,19 +3364,19 @@
#else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM
@ -3597,6 +3560,13 @@
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
#define USART_OVERSAMPLING_16 0x00000000U
#define USART_OVERSAMPLING_8 USART_CR1_OVER8
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
((__SAMPLING__) == USART_OVERSAMPLING_8))
#endif /* STM32F0 || STM32F3 || STM32F7 */
/**
* @}
*/

2
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
View File

@ -56,7 +56,7 @@
* @brief STM32WBxx HAL Driver version number
*/
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WBxx_HAL_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
#define __STM32WBxx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */
#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\

5
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal.h
View File

@ -521,8 +521,13 @@ typedef enum
(((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
#if defined(STM32WB15xx)
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
#define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x0000000FU))
#else
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
#define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)
#endif
#if defined(VREFBUF)
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \

927
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc.c
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File diff suppressed because it is too large Load Diff

290
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc.h
View File

@ -44,6 +44,9 @@ extern "C" {
* @{
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief ADC group regular oversampling structure definition
*/
@ -67,6 +70,7 @@ typedef struct
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
} ADC_OversamplingTypeDef;
#endif
/**
* @brief Structure definition of ADC instance and ADC group regular.
@ -131,6 +135,13 @@ typedef struct
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
(in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
#if defined(ADC_SUPPORT_2_5_MSPS)
FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
This parameter can be set to ENABLE or DISABLE.
Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
#endif
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
@ -147,9 +158,13 @@ typedef struct
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group regular number of discontinuous conversions" not available on ADC peripheral of this STM32WB device */
#else
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
#endif
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
@ -176,12 +191,47 @@ typedef struct
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
#if defined (ADC_SUPPORT_2_5_MSPS)
uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
#endif
#if !defined (ADC_SUPPORT_2_5_MSPS)
FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
#endif
#if defined (ADC_SUPPORT_2_5_MSPS)
uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode.
This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
Note: ADC trigger frequency mode must be set to low frequency when
a duration is exceeded before ADC conversion start trigger event
(between ADC enable and ADC conversion start trigger event
or between two ADC conversion start trigger event).
Duration value: Refer to device datasheet, parameter "tIdle".
Note: When ADC trigger frequency mode is set to low frequency,
some rearm cycles are inserted before performing ADC conversion
start, inducing a delay of 2 ADC clock cycles. */
#endif
} ADC_InitTypeDef;
@ -218,6 +268,7 @@ typedef struct
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values. */
#if !defined (ADC_SUPPORT_2_5_MSPS)
uint32_t SingleDiff; /*!< Select single-ended or differential input.
In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
@ -241,6 +292,7 @@ typedef struct
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */
#endif
} ADC_ChannelConfTypeDef;
/**
@ -253,7 +305,7 @@ typedef struct
{
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel). Note: Analog Watchdog 2 and 3 are not available on devices: STM32WB10xx, STM32WB15xx.
This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
@ -367,7 +419,11 @@ typedef struct
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
#if defined (ADC_SUPPORT_2_5_MSPS)
uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */
#else
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
#endif
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
@ -474,7 +530,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @{
*/
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@ -482,8 +538,33 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
* @{
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Note: On STM32WB10xx, STM32WB15xx devices, ADC group regular sequencer */
/* both modes "fully configurable" or "not fully configurable" are */
/* available. */
/* Scan mode values must be compatible with other STM32 devices having */
/* a configurable sequencer. */
/* Scan direction setting values are defined by taking in account */
/* already defined values for other STM32 devices: */
/* ADC_SCAN_DISABLE (0x00000000UL) */
/* ADC_SCAN_ENABLE (0x00000001UL) */
/* Sequencer fully configurable with only rank 1 enabled is considered */
/* as default setting equivalent to scan enable. */
/* In case of migration from another STM32 device, the user will be */
/* warned of change of setting choices with assert check. */
#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */
#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */
#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */
#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */
#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 devices */
#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 devices */
#else
#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@ -493,6 +574,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC4 (LL_ADC_REG_TRIG_EXT_TIM2_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
#else
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
@ -501,6 +590,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
#endif
/**
* @}
*/
@ -537,6 +627,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */
#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
#else
#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
@ -553,10 +656,36 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
#endif
/**
* @}
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME ADC instance - Sampling time common to a group of channels
* @{
*/
#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME_INST_SCOPE Channel - Sampling time (ADC instance scope for sampling time common 1 or 2, not channel wise)
* @{
*/
#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */
#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */
#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */
#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */
#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */
#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */
#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */
/**
* @}
*/
#else
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
@ -571,6 +700,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/**
* @}
*/
#endif
/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
* @{
@ -607,8 +737,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @{
*/
#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */
#else
#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
#endif
/**
* @}
*/
@ -627,6 +761,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @}
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
@ -657,6 +794,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/**
* @}
*/
#endif
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
@ -676,6 +814,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @}
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
* @{
*/
#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
/**
* @}
*/
#endif
/** @defgroup ADC_Event_type ADC Event type
* @{
@ -685,7 +834,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
#if !defined (ADC_SUPPORT_2_5_MSPS)
#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
#endif
/**
* @}
*/
@ -699,12 +850,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
#if defined (ADC_SUPPORT_2_5_MSPS)
#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC end of calibration interrupt source */
#define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */
#else
#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
#endif
#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
@ -720,13 +876,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
#if defined (ADC_SUPPORT_2_5_MSPS)
#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC end of calibration flag */
#define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */
#else
#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
#endif
#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
/**
* @}
*/
@ -781,7 +941,11 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (8UL)))
#else
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
#endif
/**
@ -863,6 +1027,15 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @param __REGTRIG__ programmed ADC regular conversions external trigger.
* @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
#else
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
@ -872,6 +1045,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
#endif
/**
* @brief Verify the ADC regular conversions check for converted data availability.
@ -889,11 +1063,26 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \
((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) )
#endif
/**
* @brief Verify the ADC conversions sampling time.
* @param __TIME__ ADC conversions sampling time.
* @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \
((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_7CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_19CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_39CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_79CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_160CYCLES_5) )
#else
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
@ -902,28 +1091,45 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
#endif
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \
((RANK) == ADC_RANK_NONE) )
#endif
/**
* @brief Verify the ADC regular channel setting.
* @param __CHANNEL__ programmed ADC regular channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
* @param RANK programmed ADC regular channel.
* @retval SET (RANK is valid) or RESET (RANK is invalid)
*/
#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
((__CHANNEL__) == ADC_REGULAR_RANK_16) )
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \
((RANK) == ADC_REGULAR_RANK_2 ) || \
((RANK) == ADC_REGULAR_RANK_3 ) || \
((RANK) == ADC_REGULAR_RANK_4 ) || \
((RANK) == ADC_REGULAR_RANK_5 ) || \
((RANK) == ADC_REGULAR_RANK_6 ) || \
((RANK) == ADC_REGULAR_RANK_7 ) || \
((RANK) == ADC_REGULAR_RANK_8 ) )
#else
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \
((RANK) == ADC_REGULAR_RANK_2 ) || \
((RANK) == ADC_REGULAR_RANK_3 ) || \
((RANK) == ADC_REGULAR_RANK_4 ) || \
((RANK) == ADC_REGULAR_RANK_5 ) || \
((RANK) == ADC_REGULAR_RANK_6 ) || \
((RANK) == ADC_REGULAR_RANK_7 ) || \
((RANK) == ADC_REGULAR_RANK_8 ) || \
((RANK) == ADC_REGULAR_RANK_9 ) || \
((RANK) == ADC_REGULAR_RANK_10) || \
((RANK) == ADC_REGULAR_RANK_11) || \
((RANK) == ADC_REGULAR_RANK_12) || \
((RANK) == ADC_REGULAR_RANK_13) || \
((RANK) == ADC_REGULAR_RANK_14) || \
((RANK) == ADC_REGULAR_RANK_15) || \
((RANK) == ADC_REGULAR_RANK_16) )
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
@ -950,6 +1156,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
#if defined (ADC_SUPPORT_2_5_MSPS)
#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */
#endif
/**
* @}
*/
@ -994,10 +1204,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
*
* (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
@ -1015,10 +1227,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
*
* (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
@ -1033,12 +1247,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source (1)
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source (1)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source (1)
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
*
* (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval State of interruption (SET or RESET)
*/
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
@ -1054,12 +1270,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR ADC overrun flag
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag (1)
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag (1)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag (1)
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
*
* (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval State of flag (TRUE or FALSE).
*/
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
@ -1075,12 +1293,14 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR ADC overrun flag
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag (1)
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag (1)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag (1)
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
*
* (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval None
*/
/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */

114
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc_ex.c
View File

@ -3,18 +3,18 @@
* @file stm32wbxx_hal_adc_ex.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Operation functions
* ++ Start, stop, get result of conversions of ADC group injected,
* using 2 possible modes: polling, interruption.
* using 2 possible modes: polling, interruption (not available on devices: STM32WB10xx, STM32WB15xx).
* ++ Calibration
* +++ ADC automatic self-calibration
* +++ Calibration factors get or set
* + Control functions
* ++ Channels configuration on ADC group injected
* ++ Channels configuration on ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx)
* + State functions
* ++ ADC group injected contexts queue management
* ++ ADC group injected contexts queue management (not available on devices: STM32WB10xx, STM32WB15xx)
* Other functions (generic functions) are available in file
* "stm32wbxx_hal_adc.c".
*
@ -99,12 +99,12 @@
(+) Get calibration factors for single or differential ending.
(+) Set calibration factors for single or differential ending.
(+) Start conversion of ADC group injected.
(+) Stop conversion of ADC group injected.
(+) Poll for conversion complete on ADC group injected.
(+) Get result of ADC group injected channel conversion.
(+) Start conversion of ADC group injected and enable interruptions.
(+) Stop conversion of ADC group injected and disable interruptions.
(+) Start conversion of ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx).
(+) Stop conversion of ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx).
(+) Poll for conversion complete on ADC group injected (not available on devices: STM32WB10xx, STM32WB15xx).
(+) Get result of ADC group injected channel conversion (not available on devices: STM32WB10xx, STM32WB15xx).
(+) Start conversion of ADC group injected and enable interruptions (not available on devices: STM32WB10xx, STM32WB15xx).
(+) Stop conversion of ADC group injected and disable interruptions (not available on devices: STM32WB10xx, STM32WB15xx).
@endverbatim
* @{
@ -118,11 +118,17 @@
* @param SingleDiff Selection of single-ended or differential input
* This parameter can be one of the following values:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1)
*
* (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
#if defined (ADC_SUPPORT_2_5_MSPS)
UNUSED(SingleDiff);
#endif
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
@ -142,12 +148,22 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
#if defined (ADC_SUPPORT_2_5_MSPS)
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
#else
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
#endif /* ADC_SUPPORT_2_5_MSPS */
/* Start ADC calibration in mode single-ended or differential */
#if defined (ADC_SUPPORT_2_5_MSPS)
LL_ADC_StartCalibration(hadc->Instance);
#else
LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
#endif /* ADC_SUPPORT_2_5_MSPS */
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
@ -192,17 +208,27 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t
* @param hadc ADC handle.
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1)
*
* (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @retval Calibration value.
*/
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
#if defined (ADC_SUPPORT_2_5_MSPS)
UNUSED(SingleDiff);
#endif
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Return the selected ADC calibration value */
#if defined (ADC_SUPPORT_2_5_MSPS)
return LL_ADC_GetCalibrationFactor(hadc->Instance);
#else
return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
#endif
}
/**
@ -211,15 +237,25 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t Single
* @param hadc ADC handle
* @param SingleDiff This parameter can be only:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended (1)
*
* (1) On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx.
* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
* @retval HAL state
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
{
#if defined (ADC_SUPPORT_2_5_MSPS)
UNUSED(SingleDiff);
#endif
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_adc_is_conversion_on_going_regular;
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
uint32_t tmp_adc_is_conversion_on_going_injected;
#endif /* ADC_SUPPORT_2_5_MSPS */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -232,15 +268,27 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32
/* Verification of hardware constraints before modifying the calibration */
/* factors register: ADC must be enabled, no conversion on going. */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
#endif /* ADC_SUPPORT_2_5_MSPS */
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
#endif /* ADC_SUPPORT_2_5_MSPS */
)
{
/* Set the selected ADC calibration value */
#if defined (ADC_SUPPORT_2_5_MSPS)
LL_ADC_SetCalibrationFactor(hadc->Instance, CalibrationFactor);
#else
LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
#endif
}
else
{
@ -260,6 +308,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32
return tmp_hal_status;
}
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief Enable ADC, start conversion of injected group.
* @note Interruptions enabled in this function: None.
@ -454,13 +505,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
/* Process unlocked */
__HAL_UNLOCK(hadc);
/* Process unlocked */
__HAL_UNLOCK(hadc);
return HAL_TIMEOUT;
return HAL_TIMEOUT;
}
}
}
}
@ -705,7 +760,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
#endif /* ADC_SUPPORT_2_5_MSPS */
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief Get ADC injected group conversion result.
* @note Reading register JDRx automatically clears ADC flag JEOC
@ -797,6 +856,7 @@ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
*/
}
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Analog watchdog 2 callback in non-blocking mode.
@ -844,6 +904,9 @@ __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
*/
}
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief Stop ADC conversion of regular group (and injected channels in
* case of auto_injection mode), disable ADC peripheral if no
@ -1038,11 +1101,15 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
/* Return function status */
return tmp_hal_status;
}
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
* @brief ADC Extended Peripheral Control functions
*
@ -1506,7 +1573,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
/* Return function status */
return tmp_hal_status;
}
#endif /* ADC_SUPPORT_2_5_MSPS */
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief Enable Injected Queue
* @note This function resets CFGR register JQDIS bit in order to enable the
@ -1584,6 +1655,7 @@ HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
return tmp_hal_status;
}
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Disable ADC voltage regulator.
@ -1615,8 +1687,11 @@ HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
return tmp_hal_status;
}
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief Enter ADC deep-power-down mode
* @brief Enter ADC deep power-down mode
* @note This mode is achieved in setting DEEPPWD bit and allows to save power
* in reducing leakage currents. It is particularly interesting before
* entering stop modes.
@ -1651,6 +1726,7 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
return tmp_hal_status;
}
#endif
/**
* @}

154
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc_ex.h
View File

@ -41,6 +41,9 @@ extern "C" {
* @{
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief ADC Injected Conversion Oversampling structure definition
*/
@ -170,6 +173,7 @@ typedef struct
Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
} ADC_InjectionConfTypeDef;
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
@ -181,6 +185,9 @@ typedef struct
* @{
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
* @{
*/
@ -206,12 +213,15 @@ typedef struct
/**
* @}
*/
#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
* @{
*/
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
#if !defined (ADC_SUPPORT_2_5_MSPS)
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
#endif
/**
* @}
*/
@ -228,6 +238,9 @@ typedef struct
* @}
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
* @{
*/
@ -238,13 +251,18 @@ typedef struct
/**
* @}
*/
#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
* @{
*/
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@ -315,6 +333,9 @@ typedef struct
*/
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief Set the selected injected Channel rank.
* @param __CHANNELNB__ Channel number.
@ -336,6 +357,7 @@ typedef struct
* @retval None
*/
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Configure ADC discontinuous conversion mode for regular group
@ -365,6 +387,47 @@ typedef struct
*/
#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
#if defined (ADC_SUPPORT_2_5_MSPS)
/**
* @brief Enable ADC overrun mode.
* @param _OVERRUN_MODE_ Overrun mode.
* @retval Overun bit setting to be programmed into CFGR register
*/
/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */
/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
/* as the default case to be compliant with other STM32 devices. */
#define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \
( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
)? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \
)
/**
* @brief Enable the ADC auto off mode.
* @param _AUTOOFF_ Auto off bit enable or disable.
* @retval None
*/
#define ADC_CFGR_AUTOOFF(_AUTOOFF_) \
((_AUTOOFF_) << 15UL)
/**
* @brief Set ADC scan mode with differentiation of sequencer setting
* fixed or configurable
* @param _SCAN_MODE_ Scan conversion mode.
* @retval None
*/
/* Note: Scan mode set using this macro (instead of parameter direct set) */
/* due to different modes on other STM32 devices: */
/* if scan mode is disabled, sequencer is set to fully configurable */
/* with setting of only rank 1 enabled afterwards. */
#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \
( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \
)? \
((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \
: \
(ADC_CFGR1_CHSELRMOD) \
)
#endif
/**
* @brief Configure the ADC DMA continuous request.
* @param __DMACONTREQ_MODE__ DMA continuous request mode.
@ -400,8 +463,13 @@ typedef struct
* @param __THRESHOLD__ Value to be shifted
* @retval None
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL))
#else
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
#endif
/**
* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
@ -414,22 +482,38 @@ typedef struct
* @param __THRESHOLD__ Value to be shifted
* @retval None
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) != (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)) ? \
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
((__THRESHOLD__) << 2UL) \
)
#else
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
((__THRESHOLD__) << 2UL) \
)
#endif
/**
* @brief Clear Common Control Register.
* @param __HANDLE__ ADC handle.
* @retval None
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
ADC_CCR_PRESC | \
ADC_CCR_VBATEN | \
ADC_CCR_TSEN | \
ADC_CCR_VREFEN )
#else
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
ADC_CCR_PRESC | \
ADC_CCR_VBATEN | \
ADC_CCR_TSEN | \
ADC_CCR_VREFEN )
#endif
/**
@ -453,12 +537,16 @@ typedef struct
*/
#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief Verify the length of scheduled injected conversions group.
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
*/
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Calibration factor size verification (7 bits maximum).
@ -525,8 +613,12 @@ typedef struct
* @param __SING_DIFF__ programmed channel setting.
* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) ((__SING_DIFF__) == ADC_SINGLE_ENDED)
#else
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
#endif
/**
* @brief Verify the ADC offset management setting.
@ -539,6 +631,9 @@ typedef struct
((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief Verify the ADC injected channel setting.
* @param __CHANNEL__ programmed ADC injected channel.
@ -572,21 +667,31 @@ typedef struct
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Verify the ADC analog watchdog setting.
* @param __WATCHDOG__ programmed ADC analog watchdog setting.
* @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1)
#else
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
#endif
/**
* @brief Verify the ADC analog watchdog mode setting.
* @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) )
#else
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
@ -594,6 +699,12 @@ typedef struct
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
#endif /* ADC_SUPPORT_2_5_MSPS */
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \
((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) )
#endif
/**
* @brief Verify the ADC conversion (regular or injected or both).
@ -609,13 +720,24 @@ typedef struct
* @param __EVENT__ ADC event.
* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
*/
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
((__EVENT__) == ADC_AWD1_EVENT) || \
((__EVENT__) == ADC_AWD2_EVENT) || \
((__EVENT__) == ADC_AWD3_EVENT) || \
((__EVENT__) == ADC_OVR_EVENT) )
#else
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
((__EVENT__) == ADC_AWD_EVENT) || \
((__EVENT__) == ADC_AWD2_EVENT) || \
((__EVENT__) == ADC_AWD3_EVENT) || \
((__EVENT__) == ADC_OVR_EVENT) || \
((__EVENT__) == ADC_JQOVF_EVENT) )
#endif /* ADC_SUPPORT_2_5_MSPS */
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief Verify the ADC oversampling ratio.
* @param __RATIO__ programmed ADC oversampling ratio.
@ -629,6 +751,7 @@ typedef struct
((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
#endif
/**
* @brief Verify the ADC oversampling shift.
@ -653,6 +776,8 @@ typedef struct
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
#if defined (ADC_SUPPORT_2_5_MSPS)
#else
/**
* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
* @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
@ -660,6 +785,7 @@ typedef struct
*/
#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
#endif
/**
* @brief Verify the DFSDM mode configuration.
@ -702,6 +828,9 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc,
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
uint32_t CalibrationFactor);
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
@ -710,21 +839,34 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *h
/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
#endif /* ADC_SUPPORT_2_5_MSPS */
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
#endif /* ADC_SUPPORT_2_5_MSPS */
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
#endif /* ADC_SUPPORT_2_5_MSPS */
void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* ADC group regular conversions stop */
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@ -733,11 +875,23 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
* @{
*/
/* Peripheral Control functions ***********************************************/
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
#endif /* ADC_SUPPORT_2_5_MSPS */
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
#endif /* ADC_SUPPORT_2_5_MSPS */
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */
#else
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
#endif
/**
* @}

7
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_comp.c
View File

@ -18,7 +18,8 @@
[..]
The STM32WBxx device family integrates two analog comparators instances:
COMP1, COMP2.
COMP1, COMP2 except for the STM32WB15xx, STM32WB10xx products featuring only
one instance: COMP1.
In the rest of the file, all comments related to a pair of comparators are not
applicable to STM32WB15xx, STM32WB10xx.
(#) Comparators input minus (inverting input) and input plus (non inverting input)
@ -350,7 +351,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
@ -724,7 +725,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
while(wait_loop_index != 0UL)
{
wait_loop_index--;

14
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_comp.h
View File

@ -181,7 +181,11 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
* @{
*/
#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2) */
#if defined(STM32WB15xx) || defined(STM32WB10xx)
/* COMP_INPUT_PLUS_IO1 not available on this device */
#else
#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */
#endif
#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
/**
@ -196,7 +200,11 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2) */
#if defined(STM32WB15xx) || defined(STM32WB10xx)
/* COMP_INPUT_MINUS_IO2 not available on this device */
#else
#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */
#endif
#define COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
#define COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
#define COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
@ -595,7 +603,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
#endif
/* Note: On this STM32 serie, comparator input minus parameters are */
/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */

1116
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_cryp.c
View File

File diff suppressed because it is too large Load Diff

10
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_cryp.h
View File

@ -109,7 +109,7 @@ typedef struct __CRYP_HandleTypeDef
typedef struct
#endif
{
AES_TypeDef *Instance; /*!< AES Register base address */
AES_TypeDef *Instance; /*!< AES Register base address */
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
@ -120,13 +120,13 @@ typedef struct
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
__IO uint16_t CrypHeaderCount; /*!< Counter of header data */
__IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */
__IO uint16_t CrypInCount; /*!< Counter of input data */
__IO uint16_t CrypInCount; /*!< Counter of input data in words */
__IO uint16_t CrypOutCount; /*!< Counter of output data */
__IO uint16_t CrypOutCount; /*!< Counter of output data in words */
uint16_t Size; /*!< length of input data in words */
uint16_t Size; /*!< Length of input data */
uint32_t Phase; /*!< CRYP peripheral phase */

43
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_def.h
View File

@ -54,8 +54,9 @@ typedef enum
} HAL_LockTypeDef;
/* Exported macros -----------------------------------------------------------*/
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#ifndef UNUSED
#define UNUSED(X) (void)(X) /* To avoid gcc/g++ warnings */
#endif
#define HAL_MAX_DELAY 0xFFFFFFFFU
@ -107,7 +108,15 @@ typedef enum
}while (0)
#endif /* USE_RTOS */
#if defined ( __GNUC__ )
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@ -118,8 +127,14 @@ typedef enum
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
/* GNU Compiler */
#if defined (__GNUC__)
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
@ -131,11 +146,9 @@ typedef enum
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
/* ARM Compiler */
#if defined (__CC_ARM)
#if defined (__CC_ARM) /* ARM Compiler V5 */
#define __ALIGN_BEGIN __align(4)
/* IAR Compiler */
#elif defined (__ICCARM__)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
@ -144,9 +157,9 @@ typedef enum
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler V4/V5 and V6
--------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
@ -176,9 +189,9 @@ typedef enum
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )

26
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.h
View File

@ -105,7 +105,7 @@ typedef struct
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u)
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u)
#else
#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u)
@ -122,7 +122,7 @@ typedef struct
#define EXTI_LINE_23 (EXTI_RESERVED | EXTI_REG1 | 0x17u)
#endif
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
#else
#define EXTI_LINE_25 (EXTI_RESERVED | EXTI_REG1 | 0x19u)
@ -136,7 +136,7 @@ typedef struct
#endif
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx)
#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
#else
#define EXTI_LINE_31 (EXTI_RESERVED | EXTI_REG1 | 0x1Fu)
@ -273,21 +273,21 @@ typedef struct
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \

54
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.h
View File

@ -75,6 +75,7 @@ typedef struct
uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
This parameter can be a combination of the values of
@ref FLASH_OB_USER_AGC_TRIM, @ref FLASH_OB_USER_BOR_LEVEL
@ref FLASH_OB_USER_RESET_CONFIG(*), @ref FLASH_OB_USER_INPUT_RESET_HOLDER(*)
@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
@ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
@ -280,6 +281,9 @@ typedef struct
#define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */
#define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */
#define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */
#if defined(FLASH_OPTR_IRHEN)
#define OB_USER_INPUT_RESET_HOLDER FLASH_OPTR_IRHEN /*!< Internal reset holder enable */
#endif
#define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */
#define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */
#define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */
@ -289,12 +293,24 @@ typedef struct
#define OB_USER_SRAM2RST FLASH_OPTR_SRAM2RST /*!< SRAM2 erase when system reset */
#define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */
#define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */
#if defined(FLASH_OPTR_nRST_MODE)
#define OB_USER_NRST_MODE FLASH_OPTR_nRST_MODE /*!< Reset pin configuration */
#endif
#define OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM /*!< Automatic Gain Control Trimming */
#if defined(FLASH_OPTR_IRHEN) && defined(FLASH_OPTR_nRST_MODE)
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \
OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \
OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \
OB_USER_nBOOT0 | OB_USER_AGC_TRIM | OB_USER_NRST_MODE | \
OB_USER_INPUT_RESET_HOLDER) /*!< all option bits */
#else
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \
OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \
OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \
OB_USER_nBOOT0 | OB_USER_AGC_TRIM) /*!< all option bits */
#endif
/**
* @}
@ -435,6 +451,29 @@ typedef struct
* @}
*/
#if defined(FLASH_OPTR_nRST_MODE)
/** @defgroup FLASH_OB_USER_RESET_CONFIG FLASH Option Bytes User reset config bit
* @{
*/
#define OB_RESET_MODE_INPUT_ONLY FLASH_OPTR_nRST_MODE_0 /*!< Reset pin is in Reset input mode only */
#define OB_RESET_MODE_GPIO FLASH_OPTR_nRST_MODE_1 /*!< Reset pin is in GPIO normal mode only */
#define OB_RESET_MODE_INPUT_OUTPUT (FLASH_OPTR_nRST_MODE_0 | FLASH_OPTR_nRST_MODE_1) /*!< Reset pin is in Reset input and output mode */
/**
* @}
*/
#endif
#if defined(FLASH_OPTR_IRHEN)
/** @defgroup FLASH_OB_USER_INPUT_RESET_HOLDER FLASH Option Bytes User input reset holder bit
* @{
*/
#define OB_IRH_ENABLE 0x00000000U /*!< Internal Reset handler enable */
#define OB_IRH_DISABLE FLASH_OPTR_IRHEN /*!< Internal Reset handler disable */
/**
* @}
*/
#endif
/** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE
* @{
*/
@ -526,6 +565,7 @@ typedef struct
#define SRAM2B_START_SECURE_ADDR_1 (SRAM2B_BASE + 0x0400U) /* When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_2 (SRAM2B_BASE + 0x0800U) /* When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_3 (SRAM2B_BASE + 0x0C00U) /* When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#if !defined(STM32WB15xx)
#define SRAM2B_START_SECURE_ADDR_4 (SRAM2B_BASE + 0x1000U) /* When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_5 (SRAM2B_BASE + 0x1400U) /* When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_6 (SRAM2B_BASE + 0x1800U) /* When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
@ -555,6 +595,9 @@ typedef struct
#define SRAM2B_START_SECURE_ADDR_30 (SRAM2B_BASE + 0x7800U) /* When in secure mode (SRAM2B_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_31 (SRAM2B_BASE + 0x7C00U) /* When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x8000U) /* The RAM2B is accessible to M0 Plus and M4 */
#else
#define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x0C00U) /* The RAM2B is accessible to M0 Plus and M4 */
#endif
/**
* @}
@ -813,12 +856,21 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U)
#define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */
#if defined(STM32WB15xx)
#define FLASH_PAGE_SIZE 0x00000800U /*!< FLASH Page Size, 2 KBytes */
#else
#define FLASH_PAGE_SIZE 0x00001000U /*!< FLASH Page Size, 4 KBytes */
#endif
#define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE)
#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */
#if defined(STM32WB15xx)
#define FLASH_PCROP_GRANULARITY_OFFSET 10U /*!< FLASH Code Readout Protection granularity offset */
#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 1 KBytes */
#else
#define FLASH_PCROP_GRANULARITY_OFFSET 11U /*!< FLASH Code Readout Protection granularity offset */
#define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 2 KBytes */
#endif
#define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */
/**
@ -857,7 +909,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__)))
#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)(FLASH_PAGE_SIZE - 1U)) == (__VALUE__)))
#define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
#define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
#define IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE))

26
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
View File

@ -607,6 +607,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32
* @arg @ref OB_STOP_RST or @ref OB_STOP_NORST
* @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
* @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
* @arg @ref OB_IRH_ENABLE or @ref OB_IRH_DISABLE (*)
* @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
* @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN
* @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN
@ -616,6 +617,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32
* @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE
* @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN
* @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET
* @arg @ref OB_RESET_MODE_INPUT_ONLY or @ref OB_RESET_MODE_GPIO or @ref OB_RESET_MODE_INPUT_OUTPUT (*)
* @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7
* @param RDPLevel: specifies the read protection level.
* This parameter can be one of the following values:
@ -768,21 +770,35 @@ static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam)
MODIFY_REG(sfr_reg_val, FLASH_SFR_SFSA, (((pOBParam->SecureFlashStartAddr - FLASH_BASE) / FLASH_PAGE_SIZE) << FLASH_SFR_SFSA_Pos));
/* Configure SRRVR register */
#if defined(FLASH_SRRVR_SBRSA_A)
MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA_A | FLASH_SRRVR_SBRSA_B), \
(((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_A_Pos)) | \
((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_B_Pos))));
#else
MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA | FLASH_SRRVR_SNBRSA), \
(((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_Pos)) | \
((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SNBRSA_Pos))));
#endif
/* If Full System Secure mode is requested, clear all the corresponding bit */
/* Else set the corresponding bit */
if (pOBParam->SecureMode == SYSTEM_IN_SECURE_MODE)
{
CLEAR_BIT(sfr_reg_val, FLASH_SFR_FSD);
#if defined(FLASH_SRRVR_BRSD_A)
CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B));
#else
CLEAR_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD));
#endif
}
else
{
SET_BIT(sfr_reg_val, FLASH_SFR_FSD);
#if defined(FLASH_SRRVR_BRSD_A)
SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD_A | FLASH_SRRVR_BRSD_B));
#else
SET_BIT(srrvr_reg_val, (FLASH_SRRVR_BRSD | FLASH_SRRVR_NBRSD));
#endif
}
/* Update Flash registers */
@ -870,6 +886,7 @@ static uint32_t FLASH_OB_GetRDP(void)
* @arg @ref OB_STOP_RST or @ref OB_STOP_RST
* @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
* @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
* @arg @ref OB_IRH_ENABLE or @ref OB_IRH_DISABLE (*)
* @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
* @arg @ref OB_IWDG_STOP_FREEZE or @ref OB_IWDG_STOP_RUN
* @arg @ref OB_IWDG_STDBY_FREEZE or @ref OB_IWDG_STDBY_RUN
@ -879,6 +896,7 @@ static uint32_t FLASH_OB_GetRDP(void)
* @arg @ref OB_SRAM2_RST_ERASE or @ref OB_SRAM2_RST_NOT_ERASE
* @arg @ref OB_BOOT0_FROM_OB or @ref OB_BOOT0_FROM_PIN
* @arg @ref OB_BOOT0_RESET or @ref OB_BOOT0_SET
* @arg @ref OB_RESET_MODE_INPUT_ONLY or @ref OB_RESET_MODE_GPIO or @ref OB_RESET_MODE_INPUT_OUTPUT (*)
* @arg @ref OB_AGC_TRIM_0 or @ref OB_AGC_TRIM_1 or ... or @ref OB_AGC_TRIM_7
*/
static uint32_t FLASH_OB_GetUser(void)
@ -952,12 +970,20 @@ static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint3
*SecureFlashStartAddr = ((user_config * FLASH_PAGE_SIZE) + FLASH_BASE);
/* Get Secure SRAM2a start address */
#if defined(FLASH_SRRVR_SBRSA_A)
user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_A) >> FLASH_SRRVR_SBRSA_A_Pos);
#else
user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos);
#endif
*SecureRAM2aStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2A_BASE);
/* Get Secure SRAM2b start address */
#if defined(FLASH_SRRVR_SBRSA_B)
user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA_B) >> FLASH_SRRVR_SBRSA_B_Pos);
#else
user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos);
#endif
*SecureRAM2bStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2B_BASE);

104
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio_ex.h
View File

@ -521,6 +521,110 @@
#endif
#if defined (STM32WB15xx) || defined (STM32WB10xx)
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */
#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */
#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */
#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */
#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */
#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
#define GPIO_AF4_SPI1 ((uint8_t)0x04) /*!< SPI1 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */
#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */
#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */
#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */
#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */
#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */
#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */
#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */
#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */
#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */
#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */
#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */
#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */
#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */
#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */
#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */
#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */
#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */
#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */
#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */
#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */
#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */
#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */
#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_COMP1 ((uint8_t)0x0c) /*!< COMP1 Alternate Function mapping */
#define GPIO_AF12_TIM1 ((uint8_t)0x0c) /*!< TIM1 Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_TIM2 ((uint8_t)0x0e) /*!< TIM2 Alternate Function mapping */
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0e) /*!< LPTIM2 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)
#endif
/**
* @}

14
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c.c
View File

@ -93,7 +93,7 @@
[..]
(+) A specific option field manage the different steps of a sequential transfer
(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
@ -112,7 +112,7 @@
or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
(++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
interface.
@ -122,7 +122,7 @@
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
(+) Differents sequential I2C interfaces are listed below:
(+) Different sequential I2C interfaces are listed below:
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
(+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
@ -4835,7 +4835,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
/* Check if all Datas have already been sent */
/* Check if all data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
{
@ -5719,7 +5719,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
}
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
/* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
/* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
I2C_ITSlaveSeqCplt(hi2c);
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@ -5856,7 +5856,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
/* If state is an abort treatment on goind, don't change state */
/* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
{
@ -6570,7 +6570,7 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
}
/**
* @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
* @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
* @param hi2c I2C handle.
* @retval None
*/

47
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c_ex.h
View File

@ -38,7 +38,6 @@ extern "C" {
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
@ -75,24 +74,51 @@ extern "C" {
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
* @{
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
@ -118,9 +144,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
/**
* @}
*/
@ -142,14 +165,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif

2
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_irda.c
View File

@ -2230,7 +2230,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
uint32_t tmpreg;
IRDA_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
uint32_t pclk;
/* Check the communication parameters */

17
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_irda.h
View File

@ -78,7 +78,8 @@ typedef struct
/**
* @brief HAL IRDA State definition
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
* @note HAL IRDA State value is a combination of 2 different substates:
* gState and RxState (see @ref IRDA_State_Definition).
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@ -87,14 +88,14 @@ typedef struct
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP not initialized. HAL IRDA Init function already called)
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
@ -104,9 +105,9 @@ typedef struct
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP not initialized)
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state

2
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_iwdg.c
View File

@ -47,7 +47,7 @@
[..] Default timeout value (necessary for IWDG_SR status register update):
Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
This frequency being subject to variations as mentioned above, the
This frequency being subject to variations as mentioned above, the
default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
below) may become too short or too long.
In such cases, this default timeout value can be tuned by redefining

72
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_lptim.c
View File

@ -188,10 +188,10 @@
*/
#if defined(LPTIM2)
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \
(((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT())
(((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT())
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \
(((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT())
(((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT())
#else
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT()
@ -215,8 +215,8 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t
*/
/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions.
*
* @brief Initialization and Configuration functions.
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@ -253,19 +253,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source));
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge));
}
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime));
assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
}
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
@ -299,21 +297,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL));
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
}
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL));
}
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)
{
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT));
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL));
}
/* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
/* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */
tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD |
LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE));
/* Set initialization parameters */
@ -332,19 +327,21 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
hlptim->Init.UltraLowPowerClock.SampleTime);
}
/* Configure the active edge or edges used by the counter only if LPTIM is
* clocked by an external clock source
*/
if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
/* Configure LPTIM external clock polarity and digital filter */
if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
|| (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity);
tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
hlptim->Init.UltraLowPowerClock.SampleTime);
}
/* Configure LPTIM external trigger */
if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE)
{
/* Enable External trigger and set the trigger source */
tmpcfgr |= (hlptim->Init.Trigger.Source |
hlptim->Init.Trigger.ActiveEdge);
tmpcfgr |= (hlptim->Init.Trigger.Source |
hlptim->Init.Trigger.ActiveEdge |
hlptim->Init.Trigger.SampleTime);
}
/* Write to LPTIMx CFGR */
@ -468,8 +465,8 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
*/
/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions
* @brief Start-Stop operation functions.
*
* @brief Start-Stop operation functions.
*
@verbatim
==============================================================================
##### LPTIM Start Stop operation functions #####
@ -1594,7 +1591,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
hlptim->State = HAL_LPTIM_STATE_BUSY;
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
&& (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@ -1675,7 +1673,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance);
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM)
&& (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
{
/* Check if clock is prescaled */
assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler));
@ -1766,8 +1765,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
*/
/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions
* @brief Read operation functions.
*
* @brief Read operation functions.
*
@verbatim
==============================================================================
##### LPTIM Read operation functions #####
@ -1824,8 +1823,8 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
*/
/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
* @brief LPTIM IRQ handler.
*
* @brief LPTIM IRQ handler.
*
@verbatim
==============================================================================
##### LPTIM IRQ handler and callbacks #####
@ -2292,8 +2291,8 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
*/
/** @defgroup LPTIM_Group5 Peripheral State functions
* @brief Peripheral State functions.
*
* @brief Peripheral State functions.
*
@verbatim
==============================================================================
##### Peripheral State functions #####
@ -2368,8 +2367,7 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t
{
result = HAL_TIMEOUT;
}
}
while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
} while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
return result;
}

106
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_lptim.h
View File

@ -384,10 +384,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@ -537,13 +537,16 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @retval Interrupt status.
*/
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1\
&= ~(LPTIM_EXTI_LINE_LPTIM1))
#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1\
&= ~(LPTIM_EXTI_LINE_LPTIM2))
/**
* @}
@ -555,9 +558,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
*/
/** @addtogroup LPTIM_Exported_Functions_Group1
* @brief Initialization and Configuration functions.
* @{
*/
* @brief Initialization and Configuration functions.
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@ -570,9 +573,9 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
*/
/** @addtogroup LPTIM_Exported_Functions_Group2
* @brief Start-Stop operation functions.
* @{
*/
* @brief Start-Stop operation functions.
* @{
*/
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
@ -626,9 +629,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
*/
/** @addtogroup LPTIM_Exported_Functions_Group3
* @brief Read operation functions.
* @{
*/
* @brief Read operation functions.
* @{
*/
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
@ -638,9 +641,9 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
*/
/** @addtogroup LPTIM_Exported_Functions_Group4
* @brief LPTIM IRQ handler and callback functions.
* @{
*/
* @brief LPTIM IRQ handler and callback functions.
* @{
*/
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@ -655,17 +658,20 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim,
HAL_LPTIM_CallbackIDTypeDef CallbackID,
pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim,
HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup LPTIM_Group5
* @brief Peripheral State functions.
* @{
*/
* @brief Peripheral State functions.
* @{
*/
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/**
@ -771,43 +777,43 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
#if defined(COMP1)
#if defined(COMP2)
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
((((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|| \
(((__INSTANCE__) == LPTIM2) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
((((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|| \
(((__INSTANCE__) == LPTIM2) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
#else
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
((((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|| \
(((__INSTANCE__) == LPTIM2) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))))
((((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|| \
(((__INSTANCE__) == LPTIM2) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))))
#endif
#else
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
((((__INSTANCE__) == LPTIM1) && \
((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ) \
|| \
(((__INSTANCE__) == LPTIM2) && \
((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO)))
((((__INSTANCE__) == LPTIM1) && \
((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ) \
|| \
(((__INSTANCE__) == LPTIM2) && \
((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO)))
#endif
#if defined(COMP2)
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
(((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
(((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
#else
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
(((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO)))
(((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO)))
#endif
/**

425
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd.c
View File

@ -88,6 +88,8 @@
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
/**
* @}
@ -99,8 +101,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
*/
/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@ -204,7 +206,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
}
return HAL_OK;
}
@ -224,7 +226,10 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
hpcd->State = HAL_PCD_STATE_BUSY;
/* Stop Device */
(void)HAL_PCD_Stop(hpcd);
if (USB_StopDevice(hpcd->Instance) != HAL_OK)
{
return HAL_ERROR;
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
if (hpcd->MspDeInitCallback == NULL)
@ -293,7 +298,9 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -503,7 +510,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca
* @param pCallback pointer to the USB PCD Data OUT Stage Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -538,7 +546,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
}
/**
* @brief UnRegister the USB PCD Data OUT Stage Callback
* @brief Unregister the USB PCD Data OUT Stage Callback
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@ -576,7 +584,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd
* @param pCallback pointer to the USB PCD Data IN Stage Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataInStageCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -611,7 +620,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, p
}
/**
* @brief UnRegister the USB PCD Data IN Stage Callback
* @brief Unregister the USB PCD Data IN Stage Callback
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@ -649,7 +658,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)
* @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoOutIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -684,7 +694,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
}
/**
* @brief UnRegister the USB PCD Iso OUT incomplete Callback
* @brief Unregister the USB PCD Iso OUT incomplete Callback
* USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@ -722,7 +732,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd
* @param pCallback pointer to the USB PCD Iso IN incomplete Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoInIncpltCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -757,7 +768,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, p
}
/**
* @brief UnRegister the USB PCD Iso IN incomplete Callback
* @brief Unregister the USB PCD Iso IN incomplete Callback
* USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@ -830,7 +841,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC
}
/**
* @brief UnRegister the USB PCD BCD Callback
* @brief Unregister the USB PCD BCD Callback
* USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@ -903,7 +914,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC
}
/**
* @brief UnRegister the USB PCD LPM Callback
* @brief Unregister the USB PCD LPM Callback
* USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@ -940,8 +951,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
*/
/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @brief Data transfers functions
*
* @brief Data transfers functions
*
@verbatim
===============================================================================
##### IO operation functions #####
@ -962,9 +973,10 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
(void)USB_DevConnect(hpcd->Instance);
__HAL_PCD_ENABLE(hpcd);
(void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@ -977,9 +989,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
(void)USB_StopDevice(hpcd->Instance);
(void)USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
@ -1288,8 +1298,8 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
*/
/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
* @brief management functions
*
* @brief management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
@ -1312,6 +1322,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
__HAL_LOCK(hpcd);
(void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@ -1325,6 +1336,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
__HAL_LOCK(hpcd);
(void)USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@ -1340,6 +1352,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
hpcd->USB_Address = address;
(void)USB_SetDevAddress(hpcd->Instance, address);
__HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
@ -1350,7 +1363,8 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
* @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
PCD_EPTypeDef *ep;
@ -1477,6 +1491,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_fill_db = 1U;
ep->xfer_len_db = len;
ep->xfer_count = 0U;
ep->is_in = 1U;
ep->num = ep_addr & EP_ADDR_MSK;
@ -1525,10 +1541,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
__HAL_LOCK(hpcd);
(void)USB_EPSetStall(hpcd->Instance, ep);
if ((ep_addr & EP_ADDR_MSK) == 0U)
{
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup);
}
__HAL_UNLOCK(hpcd);
return HAL_OK;
@ -1610,8 +1623,8 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
*/
/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
@ -1656,15 +1669,14 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
PCD_EPTypeDef *ep;
uint16_t count;
uint16_t wIstr;
uint16_t wEPVal;
uint16_t count, wIstr, wEPVal, TxByteNbre;
uint8_t epindex;
/* stay in loop while pending interrupts */
while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U)
{
wIstr = hpcd->Instance->ISTR;
/* extract highest priority endpoint number */
epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
@ -1725,7 +1737,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
HAL_PCD_SetupStageCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
@ -1748,27 +1759,31 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U)
{
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
}
}
}
}
else
{
/* Decode and service non control endpoints interrupt */
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
ep = &hpcd->OUT_ep[epindex];
/* OUT double Buffering */
/* OUT Single Buffering */
if (ep->doublebuffer == 0U)
{
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
@ -1776,25 +1791,35 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
}
else
{
/* free EP OUT Buffer */
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
/* manage double buffer bulk out */
if (ep->type == EP_TYPE_BULK)
{
/* read from endpoint BUF0Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
}
count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
}
else
else /* manage double buffer iso out */
{
/* read from endpoint BUF1Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (count != 0U)
/* free EP OUT Buffer */
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
/* read from endpoint BUF0Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
}
}
else
{
/* read from endpoint BUF1Addr buffer */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
}
}
}
}
@ -1813,10 +1838,10 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
}
else
{
(void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
(void) USB_EPStartXfer(hpcd->Instance, ep);
}
} /* if((wEPVal & EP_CTR_RX) */
}
if ((wEPVal & USB_EP_CTR_TX) != 0U)
{
@ -1825,31 +1850,301 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
/* multi-packet on the NON control IN endpoint */
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
ep->xfer_buff += ep->xfer_count;
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
/* Manage Bulk Single Buffer Transaction */
if ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))
{
/* TX COMPLETE */
/* multi-packet on the NON control IN endpoint */
TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len > TxByteNbre)
{
ep->xfer_len -= TxByteNbre;
}
else
{
ep->xfer_len = 0U;
}
/* Zero Length Packet? */
if (ep->xfer_len == 0U)
{
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* Transfer is not yet Done */
ep->xfer_buff += TxByteNbre;
ep->xfer_count += TxByteNbre;
(void)USB_EPStartXfer(hpcd->Instance, ep);
}
}
/* Double Buffer Iso/bulk IN (bulk transfer Len > Ep_Mps) */
else
{
(void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
(void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
}
}
}
}
return HAL_OK;
}
/**
* @brief Manage double buffer bulk out transaction from ISR
* @param hpcd PCD handle
* @param ep current endpoint handle
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
uint16_t count;
/* Manage Buffer0 OUT */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
/* Get count of received Data on buffer0 */
count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len >= count)
{
ep->xfer_len -= count;
}
else
{
ep->xfer_len = 0U;
}
if (ep->xfer_len == 0U)
{
/* set NAK to OUT endpoint since double buffer is enabled */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
/* Check if Buffer1 is in blocked sate which requires to toggle */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
}
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
}
}
/* Manage Buffer 1 DTOG_RX=0 */
else
{
/* Get count of received data */
count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len >= count)
{
ep->xfer_len -= count;
}
else
{
ep->xfer_len = 0U;
}
if (ep->xfer_len == 0U)
{
/* set NAK on the current endpoint */
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
}
/*Need to FreeUser Buffer*/
if ((wEPVal & USB_EP_DTOG_TX) == 0U)
{
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
}
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
}
}
return count;
}
/**
* @brief Manage double buffer bulk IN transaction from ISR
* @param hpcd PCD handle
* @param ep current endpoint handle
* @param wEPVal Last snapshot of EPRx register value taken in ISR
* @retval HAL status
*/
static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
PCD_EPTypeDef *ep, uint16_t wEPVal)
{
uint32_t len;
uint16_t TxByteNbre;
/* Data Buffer0 ACK received */
if ((wEPVal & USB_EP_DTOG_TX) != 0U)
{
/* multi-packet on the NON control IN endpoint */
TxByteNbre = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len > TxByteNbre)
{
ep->xfer_len -= TxByteNbre;
}
else
{
ep->xfer_len = 0U;
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) != 0U)
{
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
{
ep->xfer_buff += TxByteNbre;
ep->xfer_count += TxByteNbre;
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len_db -= len;
}
else if (ep->xfer_len_db == 0U)
{
len = TxByteNbre;
ep->xfer_fill_db = 0U;
}
else
{
ep->xfer_fill_db = 0U;
len = ep->xfer_len_db;
ep->xfer_len_db = 0U;
}
/* Write remaining Data to Buffer */
/* Set the Double buffer counter for pma buffer1 */
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
/* Copy user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
}
}
}
else /* Data Buffer1 ACK received */
{
/* multi-packet on the NON control IN endpoint */
TxByteNbre = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
if (ep->xfer_len >= TxByteNbre)
{
ep->xfer_len -= TxByteNbre;
}
else
{
ep->xfer_len = 0U;
}
/* Transfer is completed */
if (ep->xfer_len == 0U)
{
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U);
/* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataInStageCallback(hpcd, ep->num);
#else
HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
}
}
else /* Transfer is not yet Done */
{
/* need to Free USB Buff */
if ((wEPVal & USB_EP_DTOG_RX) == 0U)
{
PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
}
/* Still there is data to Fill in the next Buffer */
if (ep->xfer_fill_db == 1U)
{
ep->xfer_buff += TxByteNbre;
ep->xfer_count += TxByteNbre;
/* Calculate the len of the new buffer to fill */
if (ep->xfer_len_db >= ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len_db -= len;
}
else if (ep->xfer_len_db == 0U)
{
len = TxByteNbre;
ep->xfer_fill_db = 0U;
}
else
{
len = ep->xfer_len_db;
ep->xfer_len_db = 0U;
ep->xfer_fill_db = 0;
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
/* Copy the user buffer to USB PMA */
USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
}
}
}
/*enable endpoint IN*/
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
return HAL_OK;
}
/**
* @}
*/

269
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd.h
View File

@ -99,16 +99,16 @@ typedef struct __PCD_HandleTypeDef
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
@ -188,9 +188,9 @@ typedef struct
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
@ -233,7 +233,7 @@ typedef enum
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
@ -260,25 +260,41 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType
* @}
*/
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataInStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoInIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
pPCD_BcdCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
pPCD_LpmCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
@ -317,16 +333,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
*/
@ -353,7 +377,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*/
#define USB_WAKEUP_EXTI_LINE (0x1U << 28) /*!< USB FS EXTI Line WakeUp Interrupt */
#define USB_WAKEUP_EXTI_LINE (0x1U << 28) /*!< USB FS EXTI Line WakeUp Interrupt */
/**
@ -363,10 +387,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
*/
#define PCD_EP0MPS_64 DEP0CTL_MPS_64
#define PCD_EP0MPS_32 DEP0CTL_MPS_32
#define PCD_EP0MPS_16 DEP0CTL_MPS_16
#define PCD_EP0MPS_08 DEP0CTL_MPS_8
#define PCD_EP0MPS_64 EP_MPS_64
#define PCD_EP0MPS_32 EP_MPS_32
#define PCD_EP0MPS_16 EP_MPS_16
#define PCD_EP0MPS_08 EP_MPS_8
/**
* @}
*/
@ -401,8 +425,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
* @{
*/
/******************** Bit definition for USB_COUNTn_RX register *************/
#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
@ -412,10 +436,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
/* ENDPOINT transfer */
#define USB_EP0StartXfer USB_EPStartXfer
#define USB_EP0StartXfer USB_EPStartXfer
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
@ -424,8 +448,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wType Endpoint Type.
* @retval None
*/
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
@ -442,18 +465,19 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum, bDir
* @retval None
*/
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \
if ((bDir) == 0U) \
{ \
/* OUT double buffered endpoint */ \
PCD_TX_DTOG((USBx), (bEpNum)); \
} \
else if ((bDir) == 1U) \
{ \
/* IN double buffered endpoint */ \
PCD_RX_DTOG((USBx), (bEpNum)); \
} \
} while(0)
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
do { \
if ((bDir) == 0U) \
{ \
/* OUT double buffered endpoint */ \
PCD_TX_DTOG((USBx), (bEpNum)); \
} \
else if ((bDir) == 1U) \
{ \
/* IN double buffered endpoint */ \
PCD_RX_DTOG((USBx), (bEpNum)); \
} \
} while(0)
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
@ -462,21 +486,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \
uint16_t _wRegVal; \
\
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
{ \
/* toggle first bit ? */ \
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
{ \
} \
/* toggle second bit ? */ \
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TX_STATUS */
/**
@ -486,19 +511,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_RX_STATUS */
@ -511,7 +537,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wStatetx new state.
* @retval None
*/
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
@ -564,10 +591,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval TRUE = endpoint in stall condition.
*/
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
== USB_EP_TX_STALL)
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
== USB_EP_RX_STALL)
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
/**
* @brief set & clear EP_KIND bit.
@ -575,7 +600,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) do { \
#define PCD_SET_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
@ -583,7 +609,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
} while(0) /* PCD_SET_EP_KIND */
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
@ -615,7 +642,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
@ -623,7 +651,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_RX_EP_CTR */
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
@ -637,7 +666,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) do { \
#define PCD_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
@ -645,7 +675,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
} while(0) /* PCD_RX_DTOG */
#define PCD_TX_DTOG(USBx, bEpNum) do { \
#define PCD_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
@ -658,7 +689,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
@ -669,7 +701,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* PCD_CLEAR_RX_DTOG */
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
@ -687,7 +720,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param bAddr Address.
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
@ -713,23 +747,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wAddr address to be set (must be word aligned).
* @retval None
*/
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_TX_ADDRESS */
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_TX_ADDRESS */
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_RX_ADDRESS */
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_RX_ADDRESS */
/**
* @brief Gets address of the tx/rx buffer.
@ -747,7 +783,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wNBlocks no. of Blocks.
* @retval None
*/
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 5; \
if (((wCount) & 0x1fU) == 0U) \
{ \
@ -756,7 +793,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 1; \
if (((wCount) & 0x1U) != 0U) \
{ \
@ -765,7 +803,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
*(pdwReg) = (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \
uint32_t wNBlocks; \
if ((wCount) == 0U) \
{ \
@ -782,10 +821,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *pdwReg; \
\
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *pdwReg; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
@ -798,23 +838,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wCount Counter value.
* @retval None
*/
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
*_wRegVal = (uint16_t)(wCount); \
} while(0)
} while(0)
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
} while(0)
} while(0)
/**
* @brief gets counter of the tx buffer.
@ -832,10 +874,13 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wBuf0Addr buffer 0 address.
* @retval Counter value
*/
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
do { \
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
do { \
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
@ -847,7 +892,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wBuf1Addr = buffer 1 address.
* @retval None
*/
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
do { \
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF_ADDR */
@ -870,7 +916,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @param wCount: Counter value
* @retval None
*/
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
do { \
if ((bDir) == 0U) \
/* OUT endpoint */ \
{ \
@ -886,7 +933,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* SetEPDblBuf0Count*/
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
do { \
uint32_t _wBase = (uint32_t)(USBx); \
__IO uint16_t *_wEPRegVal; \
\
@ -907,10 +955,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
} \
} while(0) /* SetEPDblBuf1Count */
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
do { \
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
} while(0) /* PCD_SET_EP_DBUF_CNT */
} while(0) /* PCD_SET_EP_DBUF_CNT */
/**
* @brief Gets buffer 0/1 rx/tx counter for double buffering.

8
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd_ex.c
View File

@ -49,7 +49,7 @@
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
*
*
@verbatim
===============================================================================
##### Extended features functions #####
@ -78,10 +78,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress)
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress)
{
PCD_EPTypeDef *ep;

6
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd_ex.h
View File

@ -49,10 +49,8 @@ extern "C" {
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
uint16_t ep_addr,
uint16_t ep_kind,
uint32_t pmaadress);
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress);
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);

12
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
View File

@ -127,11 +127,13 @@ void HAL_PWR_DeInit(void)
/* Clear all flags */
LL_PWR_WriteReg(SCR,
LL_PWR_SCR_CC2HF
| LL_PWR_SCR_C802AF
LL_PWR_SCR_CC2HF
| LL_PWR_SCR_CBLEAF
| LL_PWR_SCR_CCRPEF
#if defined(PWR_CR3_E802A)
| LL_PWR_SCR_C802AF
| LL_PWR_SCR_C802WUF
#endif
| LL_PWR_SCR_CBLEWUF
#if defined(PWR_CR5_SMPSEN)
| LL_PWR_SCR_CBORHF
@ -222,8 +224,9 @@ void HAL_PWR_DisableBkUpAccess(void)
(+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
(+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
(+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
(+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
(+) Standby mode with SRAM2a: all clocks are stopped except LSI and LSE, SRAM2a content preserved, main regulator off, low power regulator on.
Note: On devices STM32WB15xx, STM32WB10xx, retention is extended to SRAM1, SRAM2a, SRAM2b.
(+) Standby mode without SRAM2a: all clocks are stopped except LSI and LSE, main and low power regulators off.
(+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
@ -266,6 +269,7 @@ void HAL_PWR_DisableBkUpAccess(void)
The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2
or for porting reasons HAL_PWR_EnterSTOPMode().
Note: Low power Stop2 mode is not available on devices STM32WB15xx, STM32WB10xx.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
(++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode)

2
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.h
View File

@ -105,7 +105,9 @@ typedef struct
*/
#define PWR_LOWPOWERMODE_STOP0 (0x00000000u) /*!< Stop 0: stop mode with main regulator */
#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: stop mode with low power regulator */
#if defined(PWR_SUPPORT_STOP2)
#define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1) /*!< Stop 2: stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/
#endif
#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */
#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */
/**

31
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
View File

@ -281,7 +281,7 @@ void HAL_PWREx_DisableBLEActivityIT(void)
CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Enable 802.15.4 Activity interrupt.
* @retval None
@ -299,6 +299,7 @@ void HAL_PWREx_Disable802ActivityIT(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_E802A);
}
#endif
/**
* @brief Enable CPU2 on-Hold interrupt.
@ -640,9 +641,11 @@ void HAL_PWREx_ReleaseCore(uint32_t CPU)
/****************************************************************************/
/**
* @brief Enable BKRAM content retention in Standby mode.
* @note When RRS bit is set, SRAM is powered by the low-power regulator in
* @brief Enable SRAM2a content retention in Standby mode.
* @note When RRS bit is set, SRAM2a is powered by the low-power regulator in
* Standby mode and its content is kept.
* @note On devices STM32WB15xx, STM32WB10xx, retention is extended
* to SRAM1, SRAM2a and SRAM2b.
* @retval None
*/
void HAL_PWREx_EnableSRAMRetention(void)
@ -651,9 +654,11 @@ void HAL_PWREx_EnableSRAMRetention(void)
}
/**
* @brief Disable BKRAM content retention in Standby mode.
* @note When RRS bit is reset, SRAM is powered off in Standby mode
* @brief Disable SRAM2a content retention in Standby mode.
* @note When RRS bit is reset, SRAM2a is powered off in Standby mode
* and its content is lost.
* @note On devices STM32WB15xx, STM32WB10xx, retention is extended
* to SRAM1, SRAM2a and SRAM2b.
* @retval None
*/
void HAL_PWREx_DisableSRAMRetention(void)
@ -678,7 +683,7 @@ void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode)
if((PowerMode & PWR_FLASHPD_LPRUN) != 0U)
{
/* Unlock bit FPDR */
WRITE_REG(PWR->CR1, 0x0000C1B0U);
WRITE_REG(PWR->CR1, 0x0000C1B0UL);
}
/* Set flash power down mode */
@ -910,7 +915,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS)
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop,
* - open mode if system low power mode is stop1, stop2, standby or shutdown
* - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
* @retval None
*/
void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
@ -924,7 +929,7 @@ void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
* requested operating mode can differ from effective low power mode.
* - dependency on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop,
* - open mode if system low power mode is stop1, stop2, standby or shutdown
* - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
* - dependency on BOR level:
* - bypass mode if supply voltage drops below BOR level
* @note This functions check flags of SMPS operating modes step down
@ -936,7 +941,7 @@ void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode)
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop,
* - open mode if system low power mode is stop1, stop2, standby or shutdown
* - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
*/
uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void)
{
@ -1129,7 +1134,6 @@ void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Enter Stop 1 mode.
* @note In Stop 1 mode, only low power voltage regulator is ON.
@ -1182,7 +1186,7 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
#if defined(PWR_SUPPORT_STOP2)
/**
* @brief Enter Stop 2 mode.
* @note In Stop 2 mode, only low power voltage regulator is ON.
@ -1244,10 +1248,7 @@ void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
/* Reset SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
#endif
/**
* @brief Enter Shutdown mode.

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.h
View File

@ -366,7 +366,9 @@ typedef struct
#endif
#define PWR_FLAG_PVDO (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos) /*!< Power Voltage Detector output flag */
#if defined(PWR_CR2_PVME1)
#define PWR_FLAG_PVMO1 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO1_Pos) /*!< Power Voltage Monitoring 1 output flag */
#endif
#define PWR_FLAG_PVMO3 (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos) /*!< Power Voltage Monitoring 3 output flag */
/*------------------------------EXTSCR---------------------------*/
@ -938,7 +940,9 @@ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
#if defined(PWR_SUPPORT_STOP2)
void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
#endif
void HAL_PWREx_EnterSHUTDOWNMode(void);
void HAL_PWREx_PVD_PVM_IRQHandler(void);

32
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
View File

@ -320,11 +320,6 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON);
#endif
#if defined(RCC_CR_HSEBYP)
/* Reset HSEBYP bit once HSE is OFF */
LL_RCC_HSE_DisableBypass();
#endif
/* Get Start Tick*/
tickstart = HAL_GetTick();
@ -454,7 +449,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Update the SystemCoreClock global variable */
SystemCoreClockUpdate();
SystemCoreClock = HAL_RCC_GetHCLKFreq();
if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
@ -822,6 +818,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
#if defined(RCC_HSI48_SUPPORT)
/*------------------------------ HSI48 Configuration -----------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
{
@ -864,6 +861,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
}
#endif
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
@ -1261,7 +1259,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
/*---------------------------------------------------------------------------*/
/* Update the SystemCoreClock global variable */
SystemCoreClockUpdate();
SystemCoreClock = HAL_RCC_GetHCLKFreq();
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(HAL_GetTickPrio());
}
@ -1530,25 +1529,17 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \
RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2 | RCC_OSCILLATORTYPE_HSI48;
RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_LSI2;
#if defined(RCC_HSI48_SUPPORT)
RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
#endif
/* Get the HSE configuration -----------------------------------------------*/
#if defined(RCC_CR_HSEBYP)
if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
}
else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
{
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
}
#else
if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
{
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
}
#endif
else
{
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
@ -1604,6 +1595,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
#if defined(RCC_HSI48_SUPPORT)
/* Get the HSI48 configuration ---------------------------------------------*/
if ((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
{
@ -1613,7 +1605,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
}
#endif
/* Get the PLL configuration -----------------------------------------------*/
if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)

275
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.h
View File

@ -59,23 +59,28 @@ extern "C" {
* @{
*/
#if defined(RCC_HSI48_SUPPORT)
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
#else
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI1) == RCC_OSCILLATORTYPE_LSI1) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI2) == RCC_OSCILLATORTYPE_LSI2) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
#if defined(RCC_CR_HSEBYP)
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
((__HSE__) == RCC_HSE_BYPASS))
#else
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON))
#endif
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON))
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
((__LSE__) == RCC_LSE_BYPASS))
@ -93,9 +98,9 @@ extern "C" {
#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
#if defined(RCC_HSI48_SUPPORT)
#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
#endif
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
((__PLL__) == RCC_PLL_ON))
@ -177,16 +182,28 @@ extern "C" {
((__MCOX__) == RCC_MCO2))
#endif
#if defined(RCC_HSI48_SUPPORT)
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
#else
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSI1) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSI2) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSE))
#endif
#define IS_RCC_MCO2SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__))
#define IS_RCC_MCO3SOURCE(__SOURCE__) IS_RCC_MCO1SOURCE((__SOURCE__))
@ -279,8 +296,10 @@ typedef struct
uint32_t MSIClockRange; /*!< The MSI frequency range.
This parameter can be a value of @ref RCC_MSI_Clock_Range */
#if defined(RCC_HSI48_SUPPORT)
uint32_t HSI48State; /*!< The new state of the HSI48 .
This parameter can be a value of @ref RCC_HSI48_Config */
#endif
RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
@ -342,7 +361,9 @@ typedef struct
#define RCC_OSCILLATORTYPE_LSI1 0x00000008U /*!< LSI1 to configure */
#define RCC_OSCILLATORTYPE_LSI2 0x00000010U /*!< LSI2 to configure */
#define RCC_OSCILLATORTYPE_MSI 0x00000020U /*!< MSI to configure */
#if defined(RCC_HSI48_SUPPORT)
#define RCC_OSCILLATORTYPE_HSI48 0x00000040U /*!< HSI48 to configure */
#endif
/**
* @}
*/
@ -352,9 +373,6 @@ typedef struct
*/
#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
#if defined(RCC_CR_HSEBYP)
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
#endif
/**
* @}
*/
@ -400,7 +418,7 @@ typedef struct
* @}
*/
#if defined(RCC_HSI48_SUPPORT)
/** @defgroup RCC_HSI48_Config HSI48 Config
* @{
*/
@ -409,7 +427,7 @@ typedef struct
/**
* @}
*/
#endif
/** @defgroup RCC_PLL_Config PLL Config
* @{
@ -523,9 +541,6 @@ typedef struct
#define RCC_PLL_SAI1CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI1CLK selection from main PLL */
#endif
#define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */
#if defined(SPI_I2S_SUPPORT)
#define RCC_PLL_I2SCLK RCC_PLLCFGR_PLLPEN /*!< PLLI2SCLK selection from main PLL */
#endif
/**
* @}
*/
@ -666,7 +681,9 @@ typedef struct
#define RCC_MCO1SOURCE_LSI1 LL_RCC_MCO1SOURCE_LSI1 /*!< LSI1 selection as MCO1 source */
#define RCC_MCO1SOURCE_LSI2 LL_RCC_MCO1SOURCE_LSI2 /*!< LSI2 selection as MCO1 source */
#define RCC_MCO1SOURCE_LSE LL_RCC_MCO1SOURCE_LSE /*!< LSE selection as MCO1 source */
#if defined(RCC_HSI48_SUPPORT)
#define RCC_MCO1SOURCE_HSI48 LL_RCC_MCO1SOURCE_HSI48 /*!< HSI48 selection as MCO1 source */
#endif
#define RCC_MCO1SOURCE_HSE_BEFORE_STAB LL_RCC_MCO1SOURCE_HSE_BEFORE_STAB /*!< HSE before stabilization selection as MCO1 source */
/**
@ -726,7 +743,9 @@ typedef struct
#endif
#define RCC_IT_HSECSS LL_RCC_CIFR_CSSF /*!< HSE Clock Security System Interrupt flag */
#define RCC_IT_LSECSS LL_RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
#if defined(RCC_HSI48_SUPPORT)
#define RCC_IT_HSI48RDY LL_RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
#endif
/**
* @}
*/
@ -767,8 +786,9 @@ typedef struct
#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
/* Flags in the CRRCR register */
#if defined(RCC_HSI48_SUPPORT)
#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
#endif
/**
* @}
*/
@ -850,8 +870,9 @@ typedef struct
#endif
#define __HAL_RCC_GPIOE_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_AES1_CLK_ENABLE() LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@ -863,9 +884,9 @@ typedef struct
#endif
#define __HAL_RCC_GPIOE_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_AES1_CLK_DISABLE() LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@ -976,6 +997,9 @@ typedef struct
* @{
*/
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_ADC_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_TIM1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)
@ -985,6 +1009,9 @@ typedef struct
#define __HAL_RCC_SAI1_CLK_ENABLE() LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SAI1)
#endif
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_ADC_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_TIM1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_CLK_DISABLE() LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1)
@ -1046,7 +1073,9 @@ typedef struct
#endif
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_AES1_IS_CLK_ENABLED() LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@ -1059,7 +1088,9 @@ typedef struct
#endif
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOE))
#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH))
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_ADC))
#endif
#if defined(AES1)
#define __HAL_RCC_AES1_IS_CLK_DISABLED() !(LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_AES1))
#endif
@ -1172,6 +1203,9 @@ typedef struct
* @{
*/
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_IS_CLK_ENABLED() LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)
@ -1182,6 +1216,9 @@ typedef struct
#endif
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC))
#endif
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1))
#define __HAL_RCC_SPI1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1))
#define __HAL_RCC_USART1_IS_CLK_DISABLED() !(LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1))
@ -1245,7 +1282,9 @@ typedef struct
#endif
#define __HAL_RCC_C2GPIOE_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_CLK_ENABLE() LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@ -1258,7 +1297,9 @@ typedef struct
#endif
#define __HAL_RCC_C2GPIOE_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_CLK_DISABLE() LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@ -1363,6 +1404,9 @@ typedef struct
* @{
*/
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_C2TIM1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_C2SPI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_C2USART1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
@ -1372,6 +1416,9 @@ typedef struct
#define __HAL_RCC_C2SAI1_CLK_ENABLE() LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
#endif
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_C2TIM1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_C2SPI1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_C2USART1_CLK_DISABLE() LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
@ -1394,11 +1441,14 @@ typedef struct
*/
#define __HAL_RCC_C2BLE_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_BLE)
#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_CLK_ENABLE() LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_802)
#endif
#define __HAL_RCC_C2BLE_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_BLE)
#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_CLK_DISABLE() LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_802)
#endif
/**
* @}
@ -1454,7 +1504,9 @@ typedef struct
#endif
#define __HAL_RCC_C2GPIOE_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_IS_CLK_ENABLED() LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@ -1467,7 +1519,9 @@ typedef struct
#endif
#define __HAL_RCC_C2GPIOE_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOE))
#define __HAL_RCC_C2GPIOH_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH))
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_ADC))
#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_IS_CLK_DISABLED() !(LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_AES1))
#endif
@ -1572,6 +1626,9 @@ typedef struct
* @{
*/
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_C2TIM1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_C2SPI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_C2USART1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)
@ -1581,6 +1638,9 @@ typedef struct
#define __HAL_RCC_C2SAI1_IS_CLK_ENABLED() LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SAI1)
#endif
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC))
#endif
#define __HAL_RCC_C2TIM1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1))
#define __HAL_RCC_C2SPI1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1))
#define __HAL_RCC_C2USART1_IS_CLK_DISABLED() !( LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1))
@ -1604,10 +1664,14 @@ typedef struct
*/
#define __HAL_RCC_C2BLE_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE)
#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_IS_CLK_ENABLED() LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802)
#endif
#define __HAL_RCC_C2BLE_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_BLE))
#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_IS_CLK_DISABLED() !(LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_802))
#endif
/**
* @}
@ -1659,7 +1723,9 @@ typedef struct
#endif
#define __HAL_RCC_GPIOE_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_AES1_FORCE_RESET() LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@ -1673,7 +1739,9 @@ typedef struct
#endif
#define __HAL_RCC_GPIOE_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_AES1_RELEASE_RESET() LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@ -1786,6 +1854,9 @@ typedef struct
* @{
*/
#define __HAL_RCC_APB2_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL)
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_ADC_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_TIM1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_FORCE_RESET() LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1)
@ -1796,6 +1867,9 @@ typedef struct
#endif
#define __HAL_RCC_APB2_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL)
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_ADC_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_TIM1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_RELEASE_RESET() LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1)
@ -1895,7 +1969,9 @@ typedef struct
#endif
#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_AES1_CLK_SLEEP_ENABLE() LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@ -1908,7 +1984,9 @@ typedef struct
#endif
#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_AES1_CLK_SLEEP_DISABLE() LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_AES1)
#endif
@ -1921,7 +1999,9 @@ typedef struct
#endif
#define __HAL_RCC_C2GPIOE_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_CLK_SLEEP_ENABLE() LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@ -1934,7 +2014,9 @@ typedef struct
#endif
#define __HAL_RCC_C2GPIOE_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOE)
#define __HAL_RCC_C2GPIOH_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_ADC)
#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_CLK_SLEEP_DISABLE() LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_AES1)
#endif
@ -2103,6 +2185,9 @@ typedef struct
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
@ -2112,6 +2197,9 @@ typedef struct
#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)
#endif
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
@ -2121,6 +2209,9 @@ typedef struct
#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SAI1)
#endif
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_C2TIM1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_C2SPI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_C2USART1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
@ -2130,6 +2221,9 @@ typedef struct
#define __HAL_RCC_C2SAI1_CLK_SLEEP_ENABLE() LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SAI1)
#endif
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_C2ADC_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC)
#endif
#define __HAL_RCC_C2TIM1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
#define __HAL_RCC_C2SPI1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
#define __HAL_RCC_C2USART1_CLK_SLEEP_DISABLE() LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
@ -2213,7 +2307,9 @@ typedef struct
#endif
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET)
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET)
#endif
#if defined(AES1)
#define __HAL_RCC_AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) != RESET)
#endif
@ -2226,7 +2322,9 @@ typedef struct
#endif
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET)
#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET)
#endif
#if defined(AES1)
#define __HAL_RCC_AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AES1SMEN) == RESET)
#endif
@ -2239,7 +2337,9 @@ typedef struct
#endif
#define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) != RESET)
#define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) != RESET)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) != RESET)
#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) != RESET)
#endif
@ -2252,7 +2352,9 @@ typedef struct
#endif
#define __HAL_RCC_C2GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOESMEN) == RESET)
#define __HAL_RCC_C2GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_GPIOHSMEN) == RESET)
#if defined(ADC_SUPPORT_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_ADCSMEN) == RESET)
#endif
#if defined(AES1)
#define __HAL_RCC_C2AES1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2AHB2SMENR, RCC_C2AHB2SMENR_AES1SMEN) == RESET)
#endif
@ -2419,6 +2521,9 @@ typedef struct
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADCSMEN) != RESET)
#endif
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET)
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET)
#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET)
@ -2428,6 +2533,9 @@ typedef struct
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET)
#endif
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_ADCSMEN) == RESET)
#endif
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET)
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET)
#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET)
@ -2437,6 +2545,9 @@ typedef struct
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET)
#endif
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_ADCSMEN) != RESET)
#endif
#define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) != RESET)
#define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) != RESET)
#define __HAL_RCC_C2USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) != RESET)
@ -2446,6 +2557,9 @@ typedef struct
#define __HAL_RCC_C2SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SAI1SMEN) != RESET)
#endif
#if defined(ADC_SUPPORT_2_5_MSPS)
#define __HAL_RCC_C2ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_ADCSMEN) == RESET)
#endif
#define __HAL_RCC_C2TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_TIM1SMEN) == RESET)
#define __HAL_RCC_C2SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_SPI1SMEN) == RESET)
#define __HAL_RCC_C2USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB2SMENR, RCC_C2APB2SMENR_USART1SMEN) == RESET)
@ -2467,10 +2581,14 @@ typedef struct
* @{
*/
#define __HAL_RCC_C2BLE_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)
#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_CLK_SLEEP_ENABLE() LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)
#endif
#define __HAL_RCC_C2BLE_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_BLE)
#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_CLK_SLEEP_DISABLE() LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_802)
#endif
/**
* @}
*/
@ -2484,10 +2602,14 @@ typedef struct
* @{
*/
#define __HAL_RCC_C2BLE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) != RESET)
#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) != RESET)
#endif
#define __HAL_RCC_C2BLE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_BLESMEN) == RESET)
#if defined(RCC_802_SUPPORT)
#define __HAL_RCC_C2802_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->C2APB3SMENR, RCC_C2APB3SMENR_802SMEN) == RESET)
#endif
/**
* @}
*/
@ -2689,10 +2811,7 @@ typedef struct
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* @note After enabling the HSE (RCC_HSE_ON), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
* @note HSE state can not be changed if it is used directly or through the
@ -2707,29 +2826,9 @@ typedef struct
* @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
* 6 HSE oscillator clock cycles.
* @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. (*)
* @note (*) Value not defined for all devices
* @retval None
*/
#if defined(RCC_CR_HSEBYP)
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
do { \
if((__STATE__) == RCC_HSE_ON) \
{ \
LL_RCC_HSE_Enable(); \
} \
else if((__STATE__) == RCC_HSE_BYPASS) \
{ \
LL_RCC_HSE_EnableBypass(); \
LL_RCC_HSE_Enable(); \
} \
else \
{ \
LL_RCC_HSE_Disable(); \
LL_RCC_HSE_DisableBypass(); \
} \
} while(0U)
#else
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
do { \
if((__STATE__) == RCC_HSE_ON) \
@ -2741,7 +2840,6 @@ typedef struct
LL_RCC_HSE_Disable(); \
} \
} while(0U)
#endif
/** @brief Macros to enable or disable the HSE Prescaler
* @note HSE div2 could be used as Sysclk or PLL entry in Range2
@ -2789,6 +2887,7 @@ typedef struct
} while(0U)
#if defined(RCC_HSI48_SUPPORT)
/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
* @note After enabling the HSI48, the application software should wait on HSI48RDY
@ -2798,6 +2897,7 @@ typedef struct
*/
#define __HAL_RCC_HSI48_ENABLE() LL_RCC_HSI48_Enable()
#define __HAL_RCC_HSI48_DISABLE() LL_RCC_HSI48_Disable()
#endif
/** @brief Macros to configure HSE sense amplifier threshold.
* @note to configure HSE sense amplifier, first disable HSE
@ -2988,7 +3088,6 @@ typedef struct
* @arg @ref RCC_PLL_USBCLK This Clock is used to generate the clock for the USB FS (48 MHz)
* @arg @ref RCC_PLL_RNGCLK This clock is used to generate the clock for RNG
* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 64MHz)
* @arg @ref RCC_PLL_I2SCLK This Clock is used to generate the clock for the I2S
* @retval None
*/
#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
@ -3069,8 +3168,8 @@ typedef struct
* @arg @ref RCC_MCO1SOURCE_LSI1 LSI1 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI2 LSI2 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source (*)
*
* @param __MCODIV__ specifies the MCO clock prescaler.
* This parameter can be one of the following values:
* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
@ -3078,6 +3177,8 @@ typedef struct
* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
*
* @note (*) Value not defined for all devices
*/
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__))
@ -3098,8 +3199,11 @@ typedef struct
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable
* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable
* @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt enable (*)
* @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable
*
* @note (*) Value not defined for all devices
*
* @retval None
*/
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
@ -3115,8 +3219,11 @@ typedef struct
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt enable
* @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt enable
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt enable
* @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt enable
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt enable (*)
* @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt enable
*
* @note (*) Value not defined for all devices
*
* @retval None
*/
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
@ -3134,8 +3241,10 @@ typedef struct
* @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt clear
* @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt clear
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt clear
* @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt clear
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt clear (*)
* @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt clear
*
* @note (*) Value not defined for all devices
*/
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
@ -3151,8 +3260,11 @@ typedef struct
* @arg @ref RCC_IT_PLLRDY PLLSAI1 ready interrupt flag
* @arg @ref RCC_IT_HSECSS HSE Clock security system interrupt flag
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt flag
* @arg @ref RCC_IT_HSI48RDY PLLHSI48 ready interrupt flag
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt flag (*)
* @arg @ref RCC_IT_LSI2RDY LSI2 ready interrupt flag
*
* @note (*) Value not defined for all devices
*
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
@ -3167,23 +3279,26 @@ typedef struct
/** @brief Check whether the selected RCC flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
* @arg @ref RCC_FLAG_PLLRDY PLLSAI1 clock ready
* @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
* @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
* @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready
* @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready
* @arg @ref RCC_FLAG_BORRST BOR reset
* @arg @ref RCC_FLAG_OBLRST OBLRST reset
* @arg @ref RCC_FLAG_PINRST Pin reset
* @arg @ref RCC_FLAG_SFTRST Software reset
* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
* @arg @ref RCC_FLAG_LPWRRST Low Power reset
* @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready
* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
* @arg @ref RCC_FLAG_PLLRDY PLLSAI1 clock ready
* @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 (*)
* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
* @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
* @arg @ref RCC_FLAG_LSI1RDY LSI1 oscillator clock ready
* @arg @ref RCC_FLAG_LSI2RDY LSI2 oscillator clock ready
* @arg @ref RCC_FLAG_BORRST BOR reset
* @arg @ref RCC_FLAG_OBLRST OBLRST reset
* @arg @ref RCC_FLAG_PINRST Pin reset
* @arg @ref RCC_FLAG_SFTRST Software reset
* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
* @arg @ref RCC_FLAG_LPWRRST Low Power reset
*
* @note (*) Value not defined for all devices
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \

82
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
View File

@ -139,7 +139,6 @@ static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void);
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
* @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
* @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
*
*
* @note Care must be taken when @ref HAL_RCCEx_PeriphCLKConfig() is used to select
@ -429,23 +428,6 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
#endif
#if defined(SPI_I2S_SUPPORT)
/*-------------------- I2S clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure the I2S clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
if (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
{
/* Enable RCC_PLL_I2SCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2SCLK);
}
}
#endif
return status;
}
@ -456,7 +438,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals
* clocks(SAI1, LPTIM1, LPTIM2, I2C1, I2C3, LPUART1,
* USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS, I2S).
* USART1, RTC, ADCx, USB, RNG, RFWKP, SMPS).
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
@ -487,9 +469,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SMPS;
#endif
#if defined(SPI_I2S_SUPPORT)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
#endif
#if defined(SAI1)
/* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
@ -551,10 +530,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->SmpsClockSelection = __HAL_RCC_GET_SMPS_SOURCE();
#endif
#if defined(SPI_I2S_SUPPORT)
/* Get the I2S clock source -----------------------------------------------*/
PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
#endif
}
/**
@ -575,7 +550,6 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
* @arg @ref RCC_PERIPHCLK_RFWAKEUP RFWKP peripheral clock
* @arg @ref RCC_PERIPHCLK_SMPS SMPS peripheral clock
* @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock
* @retval Frequency in Hz
*/
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
@ -724,6 +698,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
else /* HSI48 clock divided by 3 used as RNG clock source */
{
#if defined(RCC_HSI48_SUPPORT)
if (LL_RCC_HSI48_IsReady() == 1U)
{
frequency = HSI48_VALUE / 3U;
@ -732,6 +707,9 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{
/* Nothing to do as frequency already initialized to 0U */
}
#else
/* Nothing to do as frequency already initialized to 0U */
#endif
}
}
#if defined(USB)
@ -876,6 +854,17 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Nothing to do as frequency already initialized to 0U */
}
break;
#elif defined(STM32WB15xx)
case LL_RCC_ADC_CLKSOURCE_HSI: /* HSI clock used as ADC clock source */
if (LL_RCC_HSI_IsReady() == 1U)
{
frequency = HSI_VALUE;
}
else
{
/* Nothing to do as frequency already initialized to 0U */
}
break;
#endif
case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
frequency = HAL_RCC_GetSysClockFreq();
@ -1050,19 +1039,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Nothing to do as frequency already initialized to 0U */
}
}
else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSI) /* LSI clock used as RF Wakeup clock source */
{
const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
if ((temp_lsi1ready == 1U) || (temp_lsi2ready == 1U))
{
frequency = LSI_VALUE;
}
else
{
/* Nothing to do as frequency already initialized to 0U */
}
}
else if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024) /* HSE clock used as RF Wakeup clock source */
{
frequency = HSE_VALUE / 1024U;
@ -1127,32 +1103,6 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
/* Nothing to do as frequency already initialized to 0U */
}
}
#endif
#if defined(SPI_I2S_SUPPORT)
if (PeriphClk == RCC_PERIPHCLK_I2S)
{
switch (LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE))
{
case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S Clock is External clock */
frequency = EXTERNAL_CLOCK_VALUE;
break;
case LL_RCC_I2S_CLKSOURCE_HSI: /* I2S Clock is HSI Osc. */
if (LL_RCC_HSI_IsReady() == 1U)
{
frequency = HSI_VALUE;
}
break;
case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S Clock is PLL */
frequency = RCC_PLL_GetFreqDomain_P();
break;
case LL_RCC_I2S_CLKSOURCE_NONE: /* No clock used as I2S clock source */
default:
break;
}
}
#endif
return (frequency);
}

87
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.h
View File

@ -86,21 +86,17 @@ extern "C" {
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \
(((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS))
#elif defined(LPUART1) && defined(USB) && defined(RCC_SMPS_SUPPORT) && defined(SPI_I2S_SUPPORT)
#elif defined(LPUART1)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \
(((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S))
(((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP))
#else
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
@ -159,6 +155,7 @@ extern "C" {
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
#if defined(RCC_HSI48_SUPPORT)
#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
@ -166,6 +163,14 @@ extern "C" {
((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_LSE))
#else
#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_LSE))
#endif
#if defined(USB)
#if defined(SAI1)
@ -188,6 +193,12 @@ extern "C" {
((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
#elif defined(STM32WB15xx)
#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_HSI) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
#else
#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
@ -195,18 +206,10 @@ extern "C" {
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
#endif
#if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx)
#define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \
((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSE) || \
((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024))
#else
#define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \
((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSE) || \
((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024))
#endif
#if defined(RCC_SMPS_SUPPORT)
#define IS_RCC_SMPSCLKDIV(__DIV__) \
@ -221,13 +224,6 @@ extern "C" {
((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE))
#endif
#if defined(SPI_I2S_SUPPORT)
#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_I2SCLKSOURCE_NONE) || \
((__SOURCE__) == RCC_I2SCLKSOURCE_HSI) || \
((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_I2SCLKSOURCE_PIN))
#endif
#if defined(SAI1)
#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
@ -364,10 +360,6 @@ typedef struct
This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */
#endif
#if defined(SPI_I2S_SUPPORT)
uint32_t I2sClockSelection; /*!< Specifies I2s clock source.
This parameter can be a value of @ref RCCEx_I2s_Clock_Source */
#endif
} RCC_PeriphCLKInitTypeDef;
@ -479,9 +471,6 @@ typedef struct
#if defined(RCC_SMPS_SUPPORT)
#define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */
#endif
#if defined(SPI_I2S_SUPPORT)
#define RCC_PERIPHCLK_I2S 0x00004000U /*!< I2S Peripheral Clock Selection */
#endif
/**
* @}
*/
@ -602,6 +591,8 @@ typedef struct
#define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */
#if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx)
#define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */
#elif defined (STM32WB15xx)
#define RCC_ADCCLKSOURCE_HSI LL_RCC_ADC_CLKSOURCE_HSI /*!< HSI clock selected as ADC clock */
#endif
#define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */
#define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */
@ -627,9 +618,6 @@ typedef struct
#define RCC_RFWKPCLKSOURCE_NONE LL_RCC_RFWKP_CLKSOURCE_NONE /*!< None clock selected as RF system wakeup clock */
#define RCC_RFWKPCLKSOURCE_LSE LL_RCC_RFWKP_CLKSOURCE_LSE /*!< LSE clock selected as RF system wakeup clock */
#if defined(STM32WB55xx) || defined (STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx)
#define RCC_RFWKPCLKSOURCE_LSI LL_RCC_RFWKP_CLKSOURCE_LSI /*!< LSI clock selected as RF system wakeup clock */
#endif
#define RCC_RFWKPCLKSOURCE_HSE_DIV1024 LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024 /*!< HSE clock divided by 1024 selected as RF system wakeup clock */
/**
@ -670,18 +658,6 @@ typedef struct
*/
#endif
#if defined(SPI_I2S_SUPPORT)
/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
* @{
*/
#define RCC_I2SCLKSOURCE_NONE LL_RCC_I2S_CLKSOURCE_NONE /*!< No clock selected as I2S clock */
#define RCC_I2SCLKSOURCE_PLL LL_RCC_I2S_CLKSOURCE_PLL /*!< PLL "Q" clock selected as I2S clock source */
#define RCC_I2SCLKSOURCE_HSI LL_RCC_I2S_CLKSOURCE_HSI /*!< HSI clock selected as I2S clock */
#define RCC_I2SCLKSOURCE_PIN LL_RCC_I2S_CLKSOURCE_PIN /*!< External clock selected as I2S clock */
/**
* @}
*/
#endif
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
* @{
@ -1220,9 +1196,7 @@ typedef struct
* This parameter can be one of the following values:
* @arg @ref RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock
* @arg @ref RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock
* @arg @ref RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock (*)
* @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock
* @note (*) Value not defined for all devices
* @retval None
*/
#define __HAL_RCC_RFWAKEUP_CONFIG(__RFWKP_CLKSOURCE__) LL_RCC_SetRFWKPClockSource(__RFWKP_CLKSOURCE__)
@ -1231,9 +1205,7 @@ typedef struct
* This parameter can be one of the following values:
* @arg @ref RCC_RFWKPCLKSOURCE_NONE No clock selected as RFWKP clock
* @arg @ref RCC_RFWKPCLKSOURCE_LSE LSE Clock selected as RFWKP clock
* @arg @ref RCC_RFWKPCLKSOURCE_LSI LSI Clock selected as RFWKP clock (*)
* @arg @ref RCC_RFWKPCLKSOURCE_HSE_DIV1024 HSE div1024 Clock selected as RFWKP clock
* @note (*) Value not defined for all devices
*/
#define __HAL_RCC_GET_RFWAKEUP_SOURCE() LL_RCC_GetRFWKPClockSource()
@ -1297,27 +1269,6 @@ typedef struct
* @{
*/
#if defined(SPI_I2S_SUPPORT)
/** @brief Macro to configure the I2S clock (I2SCLK).
* @param __I2S_CLKSOURCE__ specifies the I2S clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock
* @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock
* @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock
* @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock
* @retval None
*/
#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__) LL_RCC_SetI2SClockSource(__I2S_CLKSOURCE__)
/** @brief Macro to get the I2S clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_I2SCLKSOURCE_NONE No clock selected as I2S clock
* @arg @ref RCC_I2SCLKSOURCE_PLL PLL "Q" selected as I2S clock
* @arg @ref RCC_I2SCLKSOURCE_HSI HSI selected as I2S clock
* @arg @ref RCC_I2SCLKSOURCE_PIN External clock selected as I2S clock
*/
#define __HAL_RCC_GET_I2S_SOURCE() LL_RCC_GetI2SClockSource(LL_RCC_I2S_CLKSOURCE)
#endif
#if defined(SAI1)
/** @brief Enable PLLSAI1RDY interrupt.

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.c
View File

@ -318,7 +318,11 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
/* Exit Initialization mode */
hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
#if defined(RTC_OR_ALARMOUTTYPE)
hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
#else
hrtc->Instance->OR &= (uint32_t)~(RTC_OR_OUT_RMP);
#endif
hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
/* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */

8
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.h
View File

@ -81,6 +81,7 @@ typedef struct
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
This parameter is dedicated to the PC13 configuration.
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
}RTC_InitTypeDef;
@ -264,8 +265,9 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
#if defined(RTC_OR_ALARMOUTTYPE)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)
#endif
/**
* @}
*/
@ -868,8 +870,12 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
#if defined(RTC_OUTPUT_TYPE_PUSHPULL)
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
#else
#define IS_RTC_OUTPUT_TYPE(TYPE) ((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN)
#endif
#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
((REMAP) == RTC_OUTPUT_REMAP_POS1))

5
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smartcard.c
View File

@ -2326,7 +2326,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
uint32_t tmpreg;
SMARTCARD_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK;
const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
uint32_t pclk;
/* Check the parameters */
@ -2351,8 +2351,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
* Configure the Parity and Mode:
* set PS bit according to hsmartcard->Init.Parity value
* set TE and RE bits according to hsmartcard->Init.Mode value */
tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode;
tmpreg = ((uint32_t)(hsmartcard->Init.Parity)) | ((uint32_t)(hsmartcard->Init.Mode)) | ((uint32_t)(hsmartcard->Init.WordLength));
MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
/*-------------------------- USART CR2 Configuration -----------------------*/

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smartcard.h
View File

@ -159,7 +159,7 @@ typedef struct
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)
* 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@ -176,7 +176,7 @@ typedef struct
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized)
* 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smartcard_ex.c
View File

@ -458,8 +458,8 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE)
{

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smbus.c
View File

@ -1854,7 +1854,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
/* REenable the selected SMBUS peripheral */
/* Re-enable the selected SMBUS peripheral */
__HAL_SMBUS_ENABLE(hsmbus);
/* Call the corresponding callback to inform upper layer of End of Transfer */
@ -2616,7 +2616,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre
}
/**
* @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
* @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
* @param hsmbus SMBUS handle.
* @retval None
*/

2
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smbus.h
View File

@ -65,7 +65,7 @@ typedef struct
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref SMBUS_own_address2_masks. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.

457
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
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File diff suppressed because it is too large Load Diff

106
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.h
View File

@ -400,35 +400,35 @@ typedef struct
*/
typedef enum
{
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
, HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
, HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
} HAL_TIM_CallbackIDTypeDef;
/**
@ -924,7 +924,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
(if none of the break inputs BRK and BRK2 is active) */
/**
* @}
@ -1073,24 +1073,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
@ -2019,6 +2019,8 @@ mode.
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
@ -2062,7 +2064,7 @@ mode.
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
(__HANDLE__)->ChannelState[5])
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
@ -2085,7 +2087,7 @@ mode.
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
@ -2270,9 +2272,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);

144
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
View File

@ -112,6 +112,13 @@
(((__INSTANCE__) == TIM1) ? (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) : \
((__INSTANCE__) == TIM2) ? (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) : \
((__INSTANCE__) == TIM16) ? TIM16_OR_TI1_RMP : TIM17_OR_TI1_RMP)
#elif defined(STM32WB10xx)
#define TIM_GET_OR_MASK(__INSTANCE__) \
(((__INSTANCE__) == TIM1) ? (TIM1_OR_ETR_ADC1_RMP) : (TIM2_OR_ETR_RMP))
#elif defined(STM32WB15xx)
#define TIM_GET_OR_MASK(__INSTANCE__) \
(((__INSTANCE__) == TIM1) ? (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) : \
(TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))
#else
#define TIM_GET_OR_MASK(__INSTANCE__) \
(((__INSTANCE__) == TIM1) ? (TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) : \
@ -352,9 +359,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@ -364,7 +371,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the Input Capture channel 1
(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
@ -432,9 +439,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
/* Check the TIM channels state */
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
@ -518,12 +525,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/* Set the TIM channel state */
if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
|| (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
{
return HAL_BUSY;
}
else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
&& (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
{
if ((pData == NULL) && (Length > 0U))
{
@ -553,6 +560,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/* Enable the DMA channel for Capture 1*/
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the capture compare 1 Interrupt */
@ -654,7 +662,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
{
return HAL_ERROR;
}
/* Set the TIM complementary channel state */
TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
@ -918,6 +926,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@ -937,6 +946,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@ -956,6 +966,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Output Compare DMA request */
@ -1372,6 +1383,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 1 DMA request */
@ -1391,6 +1403,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 2 DMA request */
@ -1410,6 +1423,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
{
/* Return error status */
return HAL_ERROR;
}
/* Enable the TIM Capture/Compare 3 DMA request */
@ -1532,8 +1546,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/**
* @brief Starts the TIM One Pulse signal generation on the complementary
* output.
* @note OutputChannel must match the pulse output channel chosen when calling
* @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel TIM Channel to be enabled
* @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@ -1542,22 +1558,28 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the complementary One Pulse output channel and the Input Capture channel */
TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
@ -1573,8 +1595,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
* @note OutputChannel must match the pulse output channel chosen when calling
* @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel TIM Channel to be disabled
* @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@ -1598,8 +1622,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@ -1608,8 +1634,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
* @note OutputChannel must match the pulse output channel chosen when calling
* @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel TIM Channel to be enabled
* @param OutputChannel pulse output channel to enable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@ -1618,22 +1646,28 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel);
HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel);
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
/* Check the TIM channels state */
if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY)
|| (input_channel_state != HAL_TIM_CHANNEL_STATE_READY))
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
{
return HAL_ERROR;
}
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@ -1655,8 +1689,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
* @note OutputChannel must match the pulse output channel chosen when calling
* @ref HAL_TIM_OnePulse_ConfigChannel().
* @param htim TIM One Pulse handle
* @param OutputChannel TIM Channel to be disabled
* @param OutputChannel pulse output channel to disable
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@ -1686,8 +1722,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
__HAL_TIM_DISABLE(htim);
/* Set the TIM channels state */
TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
/* Return function status */
return HAL_OK;
@ -2378,15 +2416,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br
/* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
do
while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
{
if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != TIM_BDTR_BKDSRM)
if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
{
return HAL_OK;
/* New check to avoid false timeout detection in case of preemption */
if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
{
return HAL_TIMEOUT;
}
}
} while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT);
return HAL_TIMEOUT;
}
}
break;
}
@ -2399,15 +2439,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br
/* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
do
while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
{
if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != TIM_BDTR_BK2DSRM)
if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
{
return HAL_OK;
/* New check to avoid false timeout detection in case of preemption */
if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
{
return HAL_TIMEOUT;
}
}
} while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT);
return HAL_TIMEOUT;
}
}
break;
}
@ -2538,12 +2580,12 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN)
{
HAL_TIM_ChannelStateTypeDef channel_state;
/* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
return channel_state;
}
/**
@ -2610,7 +2652,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
if (hdma == htim->hdma[TIM_DMA_ID_CC1])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
@ -2619,7 +2661,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@ -2628,7 +2670,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
@ -2637,7 +2679,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
if (hdma->Init.Mode == DMA_NORMAL)
{
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
@ -2662,7 +2704,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
* @param hdma pointer to DMA handle.
* @retval None
*/
void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
@ -2685,13 +2727,13 @@ void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
{
/* nothing to do */
}
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->ErrorCallback(htim);
#else
HAL_TIM_ErrorCallback(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}

57
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.h
View File

@ -206,46 +206,53 @@ TIMEx_BreakInputConfigTypeDef;
* @{
*/
#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFE3FECU) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFE3FF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#elif defined(STM32WB10xx)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFF3FECU) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFF3FF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFFFFFDU) == 0x00000000U))))
#elif defined(STM32WB15xx)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFF3FECU) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFF3FF0U) == 0x00000000U))))
#else
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#endif
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) \
(((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) \
(((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
#if defined(COMP1)
#if defined(COMP2)
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
#else
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1))
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN))
#endif
#else
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN))
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN))
#endif
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \
(((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \
(((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) \
(((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) \
(((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
/**
* @}

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tsc.c
View File

@ -254,6 +254,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc)
assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation));
assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler));
assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler));
assert_param(IS_TSC_PG_PRESC_VS_CTPL(htsc->Init.PulseGeneratorPrescaler, htsc->Init.CTPulseLowLength));
assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue));
assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode));
assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity));
@ -427,7 +428,8 @@ __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc)
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
pTSC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tsc.h
View File

@ -628,6 +628,10 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to
((__VALUE__) == TSC_PG_PRESC_DIV64) || \
((__VALUE__) == TSC_PG_PRESC_DIV128))
#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && ((__CTPL__) > TSC_CTPL_2CYCLES)) || \
(((__PGPSC__) == TSC_PG_PRESC_DIV2) && ((__CTPL__) > TSC_CTPL_1CYCLE)) || \
(((__PGPSC__) > TSC_PG_PRESC_DIV2) && (((__CTPL__) == TSC_CTPL_1CYCLE) || ((__CTPL__) > TSC_CTPL_1CYCLE))))
#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
((__VALUE__) == TSC_MCV_511) || \
((__VALUE__) == TSC_MCV_1023) || \

889
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart.c
View File

File diff suppressed because it is too large Load Diff

240
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart.h
View File

@ -51,7 +51,7 @@ typedef struct
#if defined(LPUART1)
LPUART:
=======
Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
UART:
=====
@ -59,9 +59,11 @@ typedef struct
- If oversampling is 16 or in LIN mode,
Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
- If oversampling is 8,
Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]
Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1
Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) /
((huart->Init.BaudRate)))[3:0]) >> 1
where uart_ker_ck_pres is the UART input clock divided by a prescaler */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
@ -84,7 +86,8 @@ typedef struct
or disabled.
This parameter can be a value of @ref UART_Hardware_Flow_Control. */
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled,
to achieve higher speed (up to f_PCLK/8).
This parameter can be a value of @ref UART_Over_Sampling. */
uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
@ -103,7 +106,8 @@ typedef struct
{
uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
Advanced Features may be initialized at the same time .
This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
This parameter can be a value of
@ref UART_Advanced_Features_Initialization_Type. */
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
This parameter can be a value of @ref UART_Tx_Inv. */
@ -137,7 +141,8 @@ typedef struct
/**
* @brief HAL UART State definition
* @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
* @note HAL UART State value is a combination of 2 different substates:
* gState and RxState (see @ref UART_State_Definition).
* - gState contains UART state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@ -148,7 +153,7 @@ typedef struct
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized. HAL UART Init function already called)
* 1 : Init done (Peripheral initialized. HAL UART Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
@ -165,7 +170,7 @@ typedef struct
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral not initialized)
* 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
@ -189,6 +194,17 @@ typedef enum
UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
} UART_ClockSourceTypeDef;
/**
* @brief HAL UART Reception type definition
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
* It is expected to admit following values :
* HAL_UART_RECEPTION_STANDARD = 0x00U,
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
* HAL_UART_RECEPTION_TORTO = 0x02U,
* HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,
*/
typedef uint32_t HAL_UART_RxTypeTypeDef;
/**
* @brief UART handle Structure definition
*/
@ -221,6 +237,8 @@ typedef struct __UART_HandleTypeDef
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@ -232,11 +250,11 @@ typedef struct __UART_HandleTypeDef
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_UART_StateTypeDef */
and also related to Tx operations. This parameter
can be a value of @ref HAL_UART_StateTypeDef */
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
This parameter can be a value of @ref HAL_UART_StateTypeDef */
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This
parameter can be a value of @ref HAL_UART_StateTypeDef */
__IO uint32_t ErrorCode; /*!< UART Error code */
@ -252,6 +270,7 @@ typedef struct __UART_HandleTypeDef
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */
void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
@ -286,6 +305,7 @@ typedef enum
* @brief HAL UART Callback pointer definition
*/
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@ -312,8 +332,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
Not to be used for neither gState nor RxState.Value is result
of combination (Or) between gState and RxState values */
#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error
@ -325,16 +345,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_Error_Definition UART Error Definition
* @{
*/
#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */
#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */
#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
* @}
@ -431,10 +451,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
* @{
*/
#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */
#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */
#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection
on start bit */
#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection
on falling edge */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection
on 0x7F frame detection */
#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection
on 0x55 frame detection */
/**
* @}
*/
@ -596,8 +620,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_MSB_First UART Advanced Feature MSB First
* @{
*/
#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received
first disable */
#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received
first enable */
/**
* @}
*/
@ -623,7 +649,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
* @{
*/
#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */
/**
* @}
*/
@ -631,9 +657,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
* @{
*/
#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */
#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */
#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */
#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register
not empty or RXFIFO is not empty */
/**
* @}
*/
@ -650,7 +677,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
* @{
*/
#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */
#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB
position in CR1 register */
/**
* @}
*/
@ -658,7 +686,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
* @{
*/
#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */
#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB
position in CR1 register */
/**
* @}
*/
@ -733,28 +762,28 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */
#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */
#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
#define UART_IT_CM 0x112EU /*!< UART character match interruption */
#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */
#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */
#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */
#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */
#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
#define UART_IT_PE 0x0028U /*!< UART parity error interruption */
#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */
#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */
#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */
#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */
#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */
#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */
#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */
#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */
#define UART_IT_CM 0x112EU /*!< UART character match interruption */
#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */
#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */
#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */
#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */
#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */
#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */
#define UART_IT_ERR 0x0060U /*!< UART error interruption */
#define UART_IT_ERR 0x0060U /*!< UART error interruption */
#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */
#define UART_IT_NE 0x0200U /*!< UART noise error interruption */
#define UART_IT_FE 0x0100U /*!< UART frame error interruption */
/**
* @}
*/
@ -778,6 +807,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @}
*/
/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
* @{
*/
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */
#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */
/**
* @}
*/
/**
* @}
@ -929,10 +968,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\
((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
((__HANDLE__)->Instance->CR1 |= (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
((__HANDLE__)->Instance->CR2 |= (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U <<\
((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Disable the specified UART interrupt.
* @param __HANDLE__ specifies the UART Handle.
@ -957,9 +1001,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\
((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
((__INTERRUPT__) & UART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Check whether the specified UART interrupt has occurred or not.
* @param __HANDLE__ specifies the UART Handle.
@ -1010,9 +1060,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET)
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
(__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
(__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (1U <<\
(((uint16_t)(__INTERRUPT__)) &\
UART_IT_MASK))) != RESET) ? SET : RESET)
/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the UART Handle.
@ -1079,8 +1133,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@ -1097,8 +1152,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@ -1115,8 +1171,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@ -1133,8 +1190,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* - macro could only be called when corresponding UART instance is disabled
* (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
* macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
* @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
@ -1176,9 +1234,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)\
+ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
#endif
#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
(uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \
)
#endif /* LPUART1 */
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ UART clock.
@ -1186,8 +1246,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
(((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
* @param __PCLK__ UART clock.
@ -1195,8 +1255,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])\
+ ((__BAUD__)/2U)) / (__BAUD__))
#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \
((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
#if defined(LPUART1)
/** @brief Check whether or not UART instance is Low Power UART.
@ -1204,7 +1264,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
*/
#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
#endif
#endif /* LPUART1 */
/** @brief Check UART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user.
@ -1244,7 +1304,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
*/
#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
((__STOPBITS__) == UART_STOPBITS_2))
#endif
#endif /* LPUART1 */
/**
* @brief Ensure that UART frame parity is valid.
@ -1441,8 +1501,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
* @param __AUTOBAUDRATE__ UART auto Baud rate state.
* @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
*/
#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
/**
* @brief Ensure that UART DMA enabling or disabling on error setting is valid.
@ -1520,7 +1581,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer
/* Prescaler Table used in BRR computation macros.
Declared as extern here to allow use of private UART macros, outside of HAL UART fonctions */
Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
extern const uint16_t UARTPrescTable[12];
@ -1547,6 +1608,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
@ -1585,6 +1649,8 @@ void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
/**
* @}
*/
@ -1630,13 +1696,15 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
* @{
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
/**
* @}

310
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart_ex.c
View File

@ -332,6 +332,41 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
(+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
(+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
[..] This subsection also provides a set of additional functions providing enhanced reception
services to user. (For example, these functions allow application to handle use cases
where number of data to be received is unknown).
(#) Compared to standard reception services which only consider number of received
data elements as reception completion criteria, these functions also consider additional events
as triggers for updating reception status to caller :
(+) Detection of inactivity period (RX line has not been active for a given period).
(++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
for 1 frame time, after last received byte.
(++) RX inactivity detected by RTO, i.e. line has been in idle state
for a programmable time, after last received byte.
(+) Detection that a specific character has been received.
(#) There are two mode of transfer:
(+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
or till IDLE event occurs. Reception is handled only during function execution.
When function exits, no data reception could occur. HAL status and number of actually received data elements,
are returned by function after finishing transfer.
(+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
(#) Blocking mode API:
(+) HAL_UARTEx_ReceiveToIdle()
(#) Non-Blocking mode API with Interrupt:
(+) HAL_UARTEx_ReceiveToIdle_IT()
(#) Non-Blocking mode API with DMA:
(+) HAL_UARTEx_ReceiveToIdle_DMA()
@endverbatim
* @{
*/
@ -416,7 +451,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
/* Init tickstart for timeout managment*/
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Wait until REACK flag is set */
@ -652,6 +687,269 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
return HAL_OK;
}
/**
* @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
* @note HAL_OK is returned if reception is completed (expected number of data has been received)
* or if reception is stopped after IDLE event (less than the expected number of data has been received)
* In this case, RxLen output parameter indicates number of data available in reception buffer.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
* of uint16_t available through pData.
* @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
* is not empty. Read operations from the RDR register are performed when
* RXFNE flag is set. From hardware perspective, RXFNE flag and
* RXNE are mapped on the same bit-field.
* @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor.
* When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
* @param huart UART handle.
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
* @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
* @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
{
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint16_t uhMask;
uint32_t tickstart;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
__HAL_LOCK(huart);
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
huart->RxXferSize = Size;
huart->RxXferCount = Size;
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
uhMask = huart->Mask;
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
{
pdata8bits = NULL;
pdata16bits = (uint16_t *) pData;
}
else
{
pdata8bits = pData;
pdata16bits = NULL;
}
__HAL_UNLOCK(huart);
/* Initialize output number of received elements */
*RxLen = 0U;
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
/* Check if IDLE flag is set */
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
{
/* Clear IDLE flag in ISR */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
/* If Set, but no data ever received, clear flag without exiting loop */
/* If Set, and data has already been received, this means Idle Event is valid : End reception */
if (*RxLen > 0U)
{
huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
}
}
/* Check if RXNE flag is set */
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
{
if (pdata8bits == NULL)
{
*pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
pdata16bits++;
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
pdata8bits++;
}
/* Increment number of received elements */
*RxLen += 1U;
huart->RxXferCount--;
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{
huart->RxState = HAL_UART_STATE_READY;
return HAL_TIMEOUT;
}
}
}
/* Set number of received elements in output parameter : RxLen */
*RxLen = huart->RxXferSize - huart->RxXferCount;
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
* to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
* number of received data elements.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
* of uint16_t available through pData.
* @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor.
* When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled using uint16_t pointer cast). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
* @param huart UART handle.
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef status;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
__HAL_LOCK(huart);
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
status = UART_Start_Receive_IT(huart, pData, Size);
/* Check Rx process has been successfully started */
if (status == HAL_OK)
{
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
else
{
/* In case of errors already pending when reception is started,
Interrupts may have already been raised and lead to reception abortion.
(Overrun error for instance).
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
status = HAL_ERROR;
}
}
return status;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
* @note Reception is initiated by this function call. Further progress of reception is achieved thanks
* to DMA services, transferring automatically received data elements in user reception buffer and
* calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
* reception phase as ended. In all cases, callback execution will indicate number of received data elements.
* @note When the UART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of uint16_t. In this case, Size must indicate the number
* of uint16_t available through pData.
* @note Dual core specific: there is no support for unaligned accesses on the Cortex-M0+ processor.
* When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits)
* (as received data will be handled by DMA from halfword frontier). Depending on compilation chain,
* use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData.
* @param huart UART handle.
* @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
* @param Size Amount of data elements (uint8_t or uint16_t) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
HAL_StatusTypeDef status;
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
{
if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
__HAL_LOCK(huart);
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
status = UART_Start_Receive_DMA(huart, pData, Size);
/* Check Rx process has been successfully started */
if (status == HAL_OK)
{
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
}
else
{
/* In case of errors already pending when reception is started,
Interrupts may have already been raised and lead to reception abortion.
(Overrun error for instance).
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
status = HAL_ERROR;
}
}
return status;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
@ -694,8 +992,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
uint8_t tx_fifo_depth;
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
{
@ -708,8 +1006,10 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
tx_fifo_depth = TX_FIFO_DEPTH;
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
(uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
(uint16_t)denominator[rx_fifo_threshold];
}
}
/**

5
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_uart_ex.h
View File

@ -174,6 +174,11 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
/**
* @}
*/

26
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_usart.c
View File

@ -49,7 +49,7 @@
by calling the customized HAL_USART_MspInit(&husart) API.
[..]
(@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's
(@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to USART API's
HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and
HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef.
@ -529,9 +529,9 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US
}
/**
* @brief Unregister an UART Callback
* UART callaback is redirected to the weak predefined callback
* @param husart uart handle
* @brief Unregister an USART Callback
* USART callaback is redirected to the weak predefined callback
* @param husart usart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
@ -732,7 +732,7 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
/**
* @brief Simplex send an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@ -830,7 +830,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
/**
* @brief Receive an amount of data in blocking mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@ -942,7 +942,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@ -1091,7 +1091,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
/**
* @brief Send an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@ -1175,7 +1175,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT
/**
* @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@ -1279,7 +1279,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@ -1377,7 +1377,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
/**
* @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@ -1463,7 +1463,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@ -1580,7 +1580,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_usart.h
View File

@ -138,7 +138,7 @@ typedef struct __USART_HandleTypeDef
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value
of @ref USARTEx_Slave_Mode */
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
@ -697,7 +697,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock.
* @param __BAUD__ Baud rate set by the user.
* @param __CLOCKPRESCALER__ UART prescaler value.
* @param __CLOCKPRESCALER__ USART prescaler value.
* @retval Division result
*/
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))

8
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_usart_ex.c
View File

@ -57,10 +57,10 @@
/** @defgroup USARTEx_Private_Constants USARTEx Private Constants
* @{
*/
/* UART RX FIFO depth */
/* USART RX FIFO depth */
#define RX_FIFO_DEPTH 8U
/* UART TX FIFO depth */
/* USART TX FIFO depth */
#define TX_FIFO_DEPTH 8U
/**
* @}
@ -503,8 +503,8 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
/* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */
uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (husart->FifoMode == USART_FIFOMODE_DISABLE)
{

43
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_wwdg.c
View File

@ -21,6 +21,13 @@
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
(+) If required by application, an Early Wakeup Interrupt can be triggered
in order to be warned before WWDG expiration. The Early Wakeup Interrupt
(EWI) can be used if specific safety operations or data logging must
be performed before the actual reset is generated. When the downcounter
reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt
line to be enabled in NVIC. Once enabled, EWI interrupt cannot be
disabled except by a system reset.
(+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG
reset occurs.
(+) The WWDG counter input clock is derived from the APB clock divided
@ -34,7 +41,8 @@
(+) Typical values:
(++) Counter min (T[5;0] = 0x00) at 64 MHz (PCLK1) with zero prescaler:
max timeout before reset: approximately 64us
(++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler dividing by 128:
(++) Counter max (T[5;0] = 0x3F) at 64 MHz (PCLK1) with prescaler
dividing by 128:
max timeout before reset: approximately 524.28ms
##### How to use this driver #####
@ -45,16 +53,16 @@
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window and counter value
using HAL_WWDG_Init() function.
(+) Start the WWDG using HAL_WWDG_Start() function.
When the WWDG is enabled the counter value should be configured to
a value greater than 0x40 to prevent generating an immediate reset.
(+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is
generated when the counter reaches 0x40, and then start the WWDG using
HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can
add his own code by customization of callback HAL_WWDG_WakeupCallback.
Once enabled, EWI interrupt cannot be disabled except by a system reset.
(+) Configure the WWDG prescaler, refresh window value, counter value and early
interrupt status using HAL_WWDG_Init() function. This will automatically
enable WWDG and start its downcounter. Time reference can be taken from
function exit. Care must be taken to provide a counter value
greater than 0x40 to prevent generation of immediate reset.
(+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is
triggered by the interrupt service routine, flag will be automatically
cleared and HAL_WWDG_WakeupCallback user callback will be executed. User
can add his own code by customization of callback HAL_WWDG_WakeupCallback.
(+) Then the application program must refresh the WWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_WWDG_Refresh() function. This operation must occur only when
@ -64,7 +72,7 @@
=============================
[..]
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows
the user to configure dynamically the driver callbacks. Use Functions
HAL_WWDG_RegisterCallback() to register a user callback.
@ -96,7 +104,7 @@
*** WWDG HAL driver macros list ***
===================================
[..]
Below the list of most used macros in WWDG HAL driver.
Below the list of available macros in WWDG HAL driver.
(+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags
@ -197,7 +205,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
#else
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
@ -242,7 +250,8 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
* @param pCallback pointer to the Callback function
* @retval status
*/
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
pWWDG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -303,7 +312,7 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD
return status;
}
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
@ -371,7 +380,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
#else
/* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
}
}
}

21
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_wwdg.h
View File

@ -56,7 +56,7 @@ typedef struct
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
} WWDG_InitTypeDef;
@ -68,17 +68,17 @@ typedef struct
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
#endif
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
} WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
@ -87,8 +87,8 @@ typedef struct
*/
typedef enum
{
HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
} HAL_WWDG_CallbackIDTypeDef;
/**
@ -96,7 +96,7 @@ typedef enum
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
@ -268,9 +268,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
#endif
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}

315
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_adc.c
View File

@ -67,6 +67,12 @@
#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
/* after the channel configuration has been changed. */
/* Driver timeout is approximated to 6 CPU cycles. */
#define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
#endif
/**
* @}
@ -80,6 +86,22 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* common to several ADC instances. */
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
)
#else
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
@ -97,9 +119,19 @@
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
)
#endif
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC instance. */
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_CLOCK(__CLOCK__) \
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
)
#endif
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
@ -112,13 +144,32 @@
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
)
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
)
#else
#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
)
#endif
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group regular */
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4 ) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
)
#else
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
@ -130,6 +181,7 @@
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
)
#endif
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
@ -147,6 +199,25 @@
|| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
)
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
( ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
|| ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
)
#endif
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
)
#else
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
@ -165,7 +236,13 @@
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
)
#endif
#if defined (ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
)
#else
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
@ -177,7 +254,7 @@
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
)
#endif
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group injected */
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
@ -245,11 +322,19 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Force reset of ADC clock (core clock) */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
/* Release reset of ADC clock (core clock) */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
#else
/* Force reset of ADC clock (core clock) */
LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC);
/* Release reset of ADC clock (core clock) */
LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC);
#endif /* ADC_SUPPORT_2_5_MSPS */
return SUCCESS;
}
@ -342,7 +427,11 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
/* Set ADC_CommonInitStruct fields to default values */
/* Set fields of ADC common */
/* (all ADC instances belonging to the same ADC common instance) */
#if defined (ADC_SUPPORT_2_5_MSPS)
ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
#else
ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
#endif /* ADC_SUPPORT_2_5_MSPS */
}
@ -387,6 +476,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
}
}
#if !defined (ADC_SUPPORT_2_5_MSPS)
/* Set ADC group injected trigger source to SW start to ensure to not */
/* have an external trigger event occurring during the conversion stop */
/* ADC disable process. */
@ -414,12 +504,28 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
break;
}
}
#else
/* Wait for ADC conversions are effectively stopped */
timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1UL)
{
timeout_cpu_cycles--;
if(timeout_cpu_cycles == 0UL)
{
/* Time-out error */
status = ERROR;
break;
}
}
#endif /* ADC_SUPPORT_2_5_MSPS */
#if !defined (ADC_SUPPORT_2_5_MSPS)
/* Flush group injected contexts queue (register JSQR): */
/* Note: Bit JQM must be set to empty the contexts queue (otherwise */
/* contexts queue is maintained with the last active context). */
LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
#endif
/* Disable the ADC instance */
LL_ADC_Disable(ADCx);
@ -438,11 +544,19 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
}
/* Check whether ADC state is compliant with expected state */
#if defined (ADC_SUPPORT_2_5_MSPS)
if (READ_BIT(ADCx->CR,
(ADC_CR_ADSTP | ADC_CR_ADSTART
| ADC_CR_ADDIS | ADC_CR_ADEN )
)
== 0UL)
#else
if (READ_BIT(ADCx->CR,
(ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
| ADC_CR_ADDIS | ADC_CR_ADEN)
)
== 0UL)
#endif
{
/* ========== Reset ADC registers ========== */
/* Reset register IER */
@ -452,12 +566,17 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
| LL_ADC_IT_EOS
| LL_ADC_IT_OVR
| LL_ADC_IT_EOSMP
#if !defined (ADC_SUPPORT_2_5_MSPS)
| LL_ADC_IT_JEOC
| LL_ADC_IT_JEOS
| LL_ADC_IT_JQOVF
#endif
| LL_ADC_IT_AWD1
| LL_ADC_IT_AWD2
| LL_ADC_IT_AWD3
#if defined (ADC_SUPPORT_2_5_MSPS)
| LL_ADC_IT_CCRDY
#endif
)
);
@ -468,15 +587,26 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
| LL_ADC_FLAG_EOS
| LL_ADC_FLAG_OVR
| LL_ADC_FLAG_EOSMP
#if !defined (ADC_SUPPORT_2_5_MSPS)
| LL_ADC_FLAG_JEOC
| LL_ADC_FLAG_JEOS
| LL_ADC_FLAG_JQOVF
#endif
| LL_ADC_FLAG_AWD1
| LL_ADC_FLAG_AWD2
| LL_ADC_FLAG_AWD3
#if defined (ADC_SUPPORT_2_5_MSPS)
| LL_ADC_FLAG_CCRDY
#endif
)
);
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Reset register CR */
/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
/* "read-set": no direct reset applicable. */
CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN);
#else
/* Reset register CR */
/* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
/* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
@ -489,7 +619,66 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
/* already done above. */
CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
#endif
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Reset register CFGR1 */
CLEAR_BIT(ADCx->CFGR1,
( ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
| ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
| ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
| ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
);
/* Reset register SMPR */
CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP1 | ADC_SMPR_SMP2 | ADC_SMPR_SMPSEL);
/* Reset register TR1 */
MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
/* Reset register CHSELR */
CLEAR_BIT(ADCx->CHSELR,
( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
| ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
| ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
| ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
| ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
);
/* Wait for ADC channel configuration ready */
timeout_cpu_cycles = ADC_TIMEOUT_CCRDY_CPU_CYCLES;
while (LL_ADC_IsActiveFlag_CCRDY(ADCx) == 0UL)
{
timeout_cpu_cycles--;
if(timeout_cpu_cycles == 0UL)
{
/* Time-out error */
status = ERROR;
break;
}
}
/* Clear flag ADC channel configuration ready */
LL_ADC_ClearFlag_CCRDY(ADCx);
/* Reset register DR */
/* bits in access mode read only, no direct reset applicable */
/* Reset register CALFACT */
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
/* Reset register CFGR2 */
/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
/* already done above. */
/* Note: Register reset last due to selection of asynchronous clock, */
/* ADC clock then depends of configuration clock source at system */
/* level. */
CLEAR_BIT(ADCx->CFGR2,
( ADC_CFGR2_CKMODE
| ADC_CFGR2_LFTRIG )
);
#else
/* Reset register CFGR */
MODIFY_REG(ADCx->CFGR,
(ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
@ -506,6 +695,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
(ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
| ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
);
/* Reset register SMPR1 */
CLEAR_BIT(ADCx->SMPR1,
@ -585,6 +775,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
/* Reset register CALFACT */
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
#endif
}
else
{
@ -640,6 +831,9 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
#if defined (ADC_SUPPORT_2_5_MSPS)
assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
#endif
assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
@ -653,6 +847,24 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
/* - Set ADC data resolution */
/* - Set ADC conversion data alignment */
/* - Set ADC low power mode */
#if defined (ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1,
ADC_CFGR1_RES
| ADC_CFGR1_ALIGN
| ADC_CFGR1_WAIT
| ADC_CFGR1_AUTOFF
,
ADC_InitStruct->Resolution
| ADC_InitStruct->DataAlignment
| ADC_InitStruct->LowPowerMode
);
MODIFY_REG(ADCx->CFGR2,
ADC_CFGR2_CKMODE
,
ADC_InitStruct->Clock
);
#else
MODIFY_REG(ADCx->CFGR,
ADC_CFGR_RES
| ADC_CFGR_ALIGN
@ -662,7 +874,7 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
| ADC_InitStruct->DataAlignment
| ADC_InitStruct->LowPowerMode
);
#endif
}
else
{
@ -682,6 +894,9 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
{
/* Set ADC_InitStruct fields to default values */
/* Set fields of ADC instance */
#if defined (ADC_SUPPORT_2_5_MSPS)
ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
#endif
ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
@ -706,6 +921,9 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
* @note On devices STM32WB10xx, STM32WB15xx: Before using this function,
* ADC group regular sequencer must be configured: refer to function
* @ref LL_ADC_REG_SetSequencerConfigurable().
* @note After using this function, other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
@ -727,11 +945,34 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
#if defined (ADC_SUPPORT_2_5_MSPS)
if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
}
if ((LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
|| (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
/* ADC group regular continuous mode and discontinuous mode */
/* can not be enabled simultenaeously */
assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
|| (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
}
#else
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
/* ADC group regular continuous mode and discontinuous mode */
/* can not be enabled simultenaeously */
assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
|| (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
}
#endif
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
@ -751,6 +992,52 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
/* - Set ADC group regular overrun behavior */
/* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
#if defined (ADC_SUPPORT_2_5_MSPS)
if( (LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
|| (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
)
{
/* Case of sequencer mode fixed
or sequencer length >= 2 ranks with sequencer mode fully configurable:
discontinuous mode configured */
MODIFY_REG(ADCx->CFGR1,
ADC_CFGR1_EXTSEL
| ADC_CFGR1_EXTEN
| ADC_CFGR1_DISCEN
| ADC_CFGR1_CONT
| ADC_CFGR1_DMAEN
| ADC_CFGR1_DMACFG
| ADC_CFGR1_OVRMOD
,
ADC_REG_InitStruct->TriggerSource
| ADC_REG_InitStruct->SequencerDiscont
| ADC_REG_InitStruct->ContinuousMode
| ADC_REG_InitStruct->DMATransfer
| ADC_REG_InitStruct->Overrun
);
}
else
{
/* Case of sequencer mode fully configurable
and sequencer length 1 rank (sequencer disabled):
discontinuous mode discarded (fixed to disable) */
MODIFY_REG(ADCx->CFGR1,
ADC_CFGR1_EXTSEL
| ADC_CFGR1_EXTEN
| ADC_CFGR1_DISCEN
| ADC_CFGR1_CONT
| ADC_CFGR1_DMAEN
| ADC_CFGR1_DMACFG
| ADC_CFGR1_OVRMOD
,
ADC_REG_InitStruct->TriggerSource
| LL_ADC_REG_SEQ_DISCONT_DISABLE
| ADC_REG_InitStruct->ContinuousMode
| ADC_REG_InitStruct->DMATransfer
| ADC_REG_InitStruct->Overrun
);
}
#else
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
MODIFY_REG(ADCx->CFGR,
@ -789,9 +1076,17 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
| ADC_REG_InitStruct->Overrun
);
}
#endif /* ADC_SUPPORT_2_5_MSPS */
/* Set ADC group regular sequencer length and scan direction */
#if defined (ADC_SUPPORT_2_5_MSPS)
if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
{
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
}
#else
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
#endif
}
else
{
@ -821,6 +1116,9 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
}
#if defined (ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
* @brief Initialize some features of ADC group injected.
* @note These parameters have an impact on ADC scope: ADC group injected.
@ -847,6 +1145,12 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
* @note Caution if feature ADC group injected contexts queue is enabled
* (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
* using successively several times this function will appear as
* having no effect.
* To set several features of ADC group injected, use
* function @ref LL_ADC_INJ_ConfigQueueContext().
* @param ADCx ADC instance
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
@ -934,6 +1238,7 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
}
#endif
/**
* @}
*/

2287
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_adc.h
View File

File diff suppressed because it is too large Load Diff

646
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_bus.h
View File

File diff suppressed because it is too large Load Diff

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_comp.c
View File

@ -55,7 +55,7 @@
|| ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \
)
/* Note: On this STM32 serie, comparator input plus parameters are */
/* Note: On this STM32 series, comparator input plus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
@ -72,7 +72,7 @@
)
#endif
/* Note: On this STM32 serie, comparator input minus parameters are */
/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */

18
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_comp.h
View File

@ -138,7 +138,11 @@ typedef struct
/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
* @{
*/
#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2) */
#if defined(STM32WB15xx) || defined(STM32WB10xx)
/* LL_COMP_INPUT_PLUS_IO1 not available on this device */
#else
#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1 (except device STM32WB35xx), pin PB4 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */
#endif
#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
#define LL_COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
/**
@ -153,7 +157,11 @@ typedef struct
#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA9 for COMP1, pin PB3 for COMP2) */
#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2) */
#if defined(STM32WB15xx) || defined(STM32WB10xx)
/* LL_COMP_INPUT_MINUS_IO2 not available on this device */
#else
#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1 (except device STM32WB35xx), pin PB7 for COMP2). Note: On STM32WB serie, parameter not available on devices: STM32WB10xx, STM32WB15xx. */
#endif
#define LL_COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
#define LL_COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
#define LL_COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
@ -307,7 +315,7 @@ typedef struct
*/
__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
{
/* Note: On this STM32 serie, window mode can be set only */
/* Note: On this STM32 series, window mode can be set only */
/* from COMP instance: COMP2. */
MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WINMODE, WindowMode);
}
@ -378,7 +386,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note On this STM32 serie, scaler bridge is configurable:
* @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
@ -464,7 +472,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note On this STM32 serie, scaler bridge is configurable:
* @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or

18
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_exti.h
View File

@ -107,7 +107,7 @@ typedef struct
#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */
#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */
#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx)
#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
#endif
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
@ -118,7 +118,7 @@ typedef struct
#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */
#endif
#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx)
#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */
#endif
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
@ -126,7 +126,7 @@ typedef struct
#endif
#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */
#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined STM32WB35xx
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx)
#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */
#endif
@ -141,6 +141,16 @@ typedef struct
LL_EXTI_LINE_21 | LL_EXTI_LINE_22 | LL_EXTI_LINE_23 | \
LL_EXTI_LINE_24 | LL_EXTI_LINE_25 | LL_EXTI_LINE_28 | \
LL_EXTI_LINE_29 | LL_EXTI_LINE_30 | LL_EXTI_LINE_31) /*!< All Extended line not reserved*/
#elif defined (STM32WB15xx)
#define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \
LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \
LL_EXTI_LINE_6 | LL_EXTI_LINE_7 | LL_EXTI_LINE_8 | \
LL_EXTI_LINE_9 | LL_EXTI_LINE_10 | LL_EXTI_LINE_11 | \
LL_EXTI_LINE_12 | LL_EXTI_LINE_13 | LL_EXTI_LINE_14 | \
LL_EXTI_LINE_15 | LL_EXTI_LINE_16 | LL_EXTI_LINE_17 | \
LL_EXTI_LINE_18 | LL_EXTI_LINE_19 | LL_EXTI_LINE_20 | \
LL_EXTI_LINE_22 | LL_EXTI_LINE_24 | LL_EXTI_LINE_25 | \
LL_EXTI_LINE_29 | LL_EXTI_LINE_30 | LL_EXTI_LINE_31) /*!< All Extended line not reserved*/
#else
#define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \
LL_EXTI_LINE_3 | LL_EXTI_LINE_4 | LL_EXTI_LINE_5 | \
@ -180,7 +190,7 @@ typedef struct
#define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \
LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \
LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_44 | \
LL_EXTI_LINE_45 | LL_EXTI_LINE_48) /*!< All Extended line not reserved*/
LL_EXTI_LINE_45 | LL_EXTI_LINE_46 | LL_EXTI_LINE_48) /*!< All Extended line not reserved*/
#else
#define LL_EXTI_LINE_ALL_32_63 (LL_EXTI_LINE_33 | LL_EXTI_LINE_36 | LL_EXTI_LINE_37 | \
LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \

2
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_i2c.h
View File

@ -1163,7 +1163,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout
}
/**
* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
* @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
* @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB

23
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_lptim.c
View File

@ -48,22 +48,22 @@
* @{
*/
#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
|| ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
|| ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
|| ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
|| ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
|| ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
|| ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
/**
* @}
*/
@ -263,8 +263,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
}
while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
} while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}

2
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_lptim.h
View File

@ -155,7 +155,7 @@ typedef struct
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
* @{
*/
#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
/**
* @}

9
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_lpuart.c
View File

@ -153,8 +153,10 @@ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
/**
* @brief Initialize LPUART registers according to the specified
* parameters in LPUART_InitStruct.
* @note As some bits in LPUART configuration registers can only be written when the LPUART is disabled (USART_CR1_UE bit =0),
* LPUART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note As some bits in LPUART configuration registers can only be written when
* the LPUART is disabled (USART_CR1_UE bit =0),
* LPUART Peripheral should be in disabled state prior calling this function.
* Otherwise, ERROR result will be returned.
* @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
* @param LPUARTx LPUART Instance
* @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
@ -200,7 +202,8 @@ ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART
/*---------------------------- LPUART CR3 Configuration -----------------------
* Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to LPUART_InitStruct->HardwareFlowControl value.
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according
* to LPUART_InitStruct->HardwareFlowControl value.
*/
LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);

58
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_lpuart.h
View File

@ -100,36 +100,43 @@ typedef struct
uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetPrescaler().*/
uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref LPUART_LL_EC_PARITY.
This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetHWFlowCtrl().*/
} LL_LPUART_InitTypeDef;
@ -267,18 +274,18 @@ typedef struct
/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */
#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */
#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */
#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */
#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */
#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */
#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */
#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */
#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */
#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */
#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
@ -442,8 +449,9 @@ typedef struct
* @param __BAUDRATE__ Baud Rate value to achieve
* @retval LPUARTDIV value to be used for BRR register filling
*/
#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\
+ (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
* LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
/**
* @}
@ -629,7 +637,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
*/
__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
(RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
@ -1345,7 +1354,10 @@ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t BaudRate)
{
LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
if (BaudRate != 0U)
{
LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
}
}
/**

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.c
View File

@ -109,10 +109,12 @@ ErrorStatus LL_PWR_DeInit(void)
/* Clear all flags */
LL_PWR_WriteReg(SCR,
LL_PWR_SCR_CC2HF
| LL_PWR_SCR_C802AF
| LL_PWR_SCR_CBLEAF
| LL_PWR_SCR_CCRPEF
#if defined(PWR_CR3_E802A)
| LL_PWR_SCR_C802AF
| LL_PWR_SCR_C802WUF
#endif
| LL_PWR_SCR_CBLEWUF
#if defined(PWR_CR5_SMPSEN)
| LL_PWR_SCR_CBORHF

96
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_pwr.h
View File

@ -90,10 +90,12 @@ extern "C" {
#endif
#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
#define LL_PWR_SCR_CC2HF PWR_SCR_CC2HF
#define LL_PWR_SCR_C802AF PWR_SCR_C802AF
#define LL_PWR_SCR_CBLEAF PWR_SCR_CBLEAF
#define LL_PWR_SCR_CCRPEF PWR_SCR_CCRPEF
#if defined(PWR_CR3_E802A)
#define LL_PWR_SCR_C802AF PWR_SCR_C802AF
#define LL_PWR_SCR_C802WUF PWR_SCR_C802WUF
#endif
#define LL_PWR_SCR_CBLEWUF PWR_SCR_CBLEWUF
#if defined(PWR_CR5_SMPSEN)
#define LL_PWR_SCR_CBORHF PWR_SCR_CBORHF
@ -145,9 +147,12 @@ extern "C" {
/* Radio (BLE or 802.15.4) flags */
#define LL_PWR_FLAG_BLEWU PWR_SR1_BLEWUF /* BLE wakeup interrupt flag */
#define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */
#define LL_PWR_FLAG_BLEA PWR_SR1_BLEAF /* BLE end of activity interrupt flag */
#if defined(PWR_CR3_E802A)
#define LL_PWR_FLAG_802WU PWR_SR1_802WUF /* 802.15.4 wakeup interrupt flag */
#define LL_PWR_FLAG_802A PWR_SR1_802AF /* 802.15.4 end of activity interrupt flag */
#endif
#define LL_PWR_FLAG_CRPE PWR_SR1_CRPEF /* Critical radio phase end of activity interrupt flag */
#define LL_PWR_FLAG_CRP PWR_EXTSCR_CRPF /* Critical radio system phase */
@ -179,7 +184,9 @@ extern "C" {
*/
#define LL_PWR_MODE_STOP0 (0x000000000U)
#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_0)
#if defined(PWR_SUPPORT_STOP2)
#define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_1)
#endif
#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0)
#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_2)
/**
@ -521,9 +528,11 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
* @param LowPowerMode This parameter can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP0
* @arg @ref LL_PWR_MODE_STOP1
* @arg @ref LL_PWR_MODE_STOP2
* @arg @ref LL_PWR_MODE_STOP2 (*)
* @arg @ref LL_PWR_MODE_STANDBY
* @arg @ref LL_PWR_MODE_SHUTDOWN
*
* (*) Not available on devices STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
@ -537,9 +546,11 @@ __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP0
* @arg @ref LL_PWR_MODE_STOP1
* @arg @ref LL_PWR_MODE_STOP2
* @arg @ref LL_PWR_MODE_STOP2 (*)
* @arg @ref LL_PWR_MODE_STANDBY
* @arg @ref LL_PWR_MODE_SHUTDOWN
*
* (*) Not available on devices STM32WB15xx, STM32WB10xx
*/
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
{
@ -557,7 +568,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
__STATIC_INLINE void LL_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
{
/* Unlock bit FPDR */
WRITE_REG(PWR->CR1, 0x0000C1B0U);
WRITE_REG(PWR->CR1, 0x0000C1B0UL);
/* Update bit FPDR */
MODIFY_REG(PWR->CR1, PWR_CR1_FPDR, FlashLowPowerMode);
@ -640,7 +651,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
* @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
* @arg @ref LL_PWR_PVM_VDDA_1_62V
*
* (*) Not available on devices STM32WB50xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
@ -656,7 +667,7 @@ __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
* @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
* @arg @ref LL_PWR_PVM_VDDA_1_62V
*
* (*) Not available on devices STM32WB50xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
@ -672,7 +683,7 @@ __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
* @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
* @arg @ref LL_PWR_PVM_VDDA_1_62V
*
* (*) Not available on devices STM32WB50xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
@ -808,7 +819,9 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
}
/**
* @brief Enable SRAM2 content retention in Standby mode
* @brief Enable SRAM2a content retention in Standby mode
* @note On devices STM32WB15xx, STM32WB10xx, retention is extended
* to SRAM1, SRAM2a and SRAM2b.
* @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
* @retval None
*/
@ -818,7 +831,9 @@ __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
}
/**
* @brief Disable SRAM2 content retention in Standby mode
* @brief Disable SRAM2a content retention in Standby mode
* @note On devices STM32WB15xx, STM32WB10xx, retention is extended
* to SRAM1, SRAM2a and SRAM2b.
* @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
* @retval None
*/
@ -829,6 +844,8 @@ __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
/**
* @brief Check if SRAM2 content retention in Standby mode is enabled
* @note On devices STM32WB15xx, STM32WB10xx, retention is extended
* to SRAM1, SRAM2a and SRAM2b.
* @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
* @retval State of bit (1 or 0).
*/
@ -851,7 +868,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
@ -873,7 +890,7 @@ __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
@ -895,7 +912,7 @@ __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
@ -972,7 +989,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
@ -994,7 +1011,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
@ -1016,7 +1033,7 @@ __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
@ -1323,7 +1340,7 @@ __STATIC_INLINE uint32_t LL_PWR_GetBORConfig(void)
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop0,
* - open mode if system low power mode is stop1, stop2, standby or shutdown
* - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
* @retval None
*/
__STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode)
@ -1345,7 +1362,7 @@ __STATIC_INLINE void LL_PWR_SMPS_SetMode(uint32_t OperatingMode)
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop0,
* - open mode if system low power mode is stop1, stop2, standby or shutdown
* - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
*/
__STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void)
{
@ -1366,7 +1383,7 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void)
* requested operating mode can differ from effective low power mode.
* - dependency on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop0,
* - open mode if system low power mode is stop1, stop2, standby or shutdown
* - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
* - dependency on BOR level:
* - bypass mode if supply voltage drops below BOR level
* @note This functions check flags of SMPS operating modes step down
@ -1380,7 +1397,7 @@ __STATIC_INLINE uint32_t LL_PWR_SMPS_GetMode(void)
*
* (1) SMPS operating mode step down or open depends on system low-power mode:
* - step down mode if system low power mode is run, LP run or stop0,
* - open mode if system low power mode is stop1, stop2, standby or shutdown
* - open mode if system low power mode is Stop1, Stop2, Standby or Shutdown
*/
__STATIC_INLINE uint32_t LL_PWR_SMPS_GetEffectiveMode(void)
{
@ -1637,9 +1654,11 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledBootC2(void)
* @param LowPowerMode This parameter can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP0
* @arg @ref LL_PWR_MODE_STOP1
* @arg @ref LL_PWR_MODE_STOP2
* @arg @ref LL_PWR_MODE_STOP2 (*)
* @arg @ref LL_PWR_MODE_STANDBY
* @arg @ref LL_PWR_MODE_SHUTDOWN
*
* (*) Not available on devices STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)
@ -1653,9 +1672,11 @@ __STATIC_INLINE void LL_C2_PWR_SetPowerMode(uint32_t LowPowerMode)
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP0
* @arg @ref LL_PWR_MODE_STOP1
* @arg @ref LL_PWR_MODE_STOP2
* @arg @ref LL_PWR_MODE_STOP2 (*)
* @arg @ref LL_PWR_MODE_STANDBY
* @arg @ref LL_PWR_MODE_SHUTDOWN
*
* (*) Not available on devices STM32WB15xx, STM32WB10xx
*/
__STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void)
{
@ -1673,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_GetPowerMode(void)
__STATIC_INLINE void LL_C2_PWR_SetFlashPowerModeLPRun(uint32_t FlashLowPowerMode)
{
/* Unlock bit FPDR */
WRITE_REG(PWR->C2CR1, 0x0000C1B0U);
WRITE_REG(PWR->C2CR1, 0x0000C1B0UL);
/* Update bit FPDR */
MODIFY_REG(PWR->C2CR1, PWR_C2CR1_FPDR, FlashLowPowerMode);
@ -1761,7 +1782,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledInternWU(void)
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
@ -1783,7 +1804,7 @@ __STATIC_INLINE void LL_C2_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
@ -1805,7 +1826,7 @@ __STATIC_INLINE void LL_C2_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
*
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx
* (*) Not available on devices STM32WB50xx, STM32WB35xx, STM32WB30xx, STM32WB15xx, STM32WB10xx
* @retval None
*/
__STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
@ -1874,6 +1895,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_BLE(void)
return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_BLEEWKUP) == (PWR_C2CR1_BLEEWKUP)) ? 1UL : 0UL);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Wakeup 802.15.4 controller from its sleep mode
* @note This bit is automatically reset when 802.15.4 controller
@ -1896,6 +1918,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsWokenUp_802_15_4(void)
{
return ((READ_BIT(PWR->C2CR1, PWR_C2CR1_802EWKUP) == (PWR_C2CR1_802EWKUP)) ? 1UL : 0UL);
}
#endif
/**
* @}
@ -2179,6 +2202,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEWU(void)
return ((READ_BIT(PWR->SR1, PWR_SR1_BLEWUF) == (PWR_SR1_BLEWUF)) ? 1UL : 0UL);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Get 802.15.4 wakeup interrupt flag
* @rmtoll SR1 802WUF LL_PWR_IsActiveFlag_802WU
@ -2188,6 +2212,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802WU(void)
{
return ((READ_BIT(PWR->SR1, PWR_SR1_802WUF) == (PWR_SR1_802WUF)) ? 1UL : 0UL);
}
#endif
/**
* @brief Get BLE end of activity interrupt flag
@ -2199,6 +2224,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BLEA(void)
return ((READ_BIT(PWR->SR1, PWR_SR1_BLEAF) == (PWR_SR1_BLEAF)) ? 1UL : 0UL);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Get 802.15.4 end of activity interrupt flag
* @rmtoll SR1 802AF LL_PWR_IsActiveFlag_802A
@ -2208,6 +2234,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_802A(void)
{
return ((READ_BIT(PWR->SR1, PWR_SR1_802AF) == (PWR_SR1_802AF)) ? 1UL : 0UL);
}
#endif
/**
* @brief Get critical radio phase end of activity interrupt flag
@ -2239,6 +2266,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_BLEWU(void)
WRITE_REG(PWR->SCR, PWR_SCR_CBLEWUF);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Clear 802.15.4 wakeup interrupt flag
* @rmtoll SCR 802WU LL_PWR_ClearFlag_802WU
@ -2248,6 +2276,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_802WU(void)
{
WRITE_REG(PWR->SCR, PWR_SCR_C802WUF);
}
#endif
/**
* @brief Clear BLE end of activity interrupt flag
@ -2259,6 +2288,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_BLEA(void)
WRITE_REG(PWR->SCR, PWR_SCR_CBLEAF);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Clear 802.15.4 end of activity interrupt flag
* @rmtoll SCR 802AF LL_PWR_ClearFlag_802A
@ -2268,6 +2298,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_802A(void)
{
WRITE_REG(PWR->SCR, PWR_SCR_C802AF);
}
#endif
/**
* @brief Clear critical radio phase end of activity interrupt flag
@ -2461,6 +2492,7 @@ __STATIC_INLINE void LL_PWR_EnableIT_BLEA(void)
SET_BIT(PWR->CR3, PWR_CR3_EBLEA);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Enable 802.15.4 end of activity interrupt for CPU1
* @rmtoll CR3 E802A LL_PWR_EnableIT_802A
@ -2470,7 +2502,7 @@ __STATIC_INLINE void LL_PWR_EnableIT_802A(void)
{
SET_BIT(PWR->CR3, PWR_CR3_E802A);
}
#endif
/**
* @brief Disable BLE end of activity interrupt for CPU1
@ -2482,6 +2514,7 @@ __STATIC_INLINE void LL_PWR_DisableIT_BLEA(void)
CLEAR_BIT(PWR->CR3, PWR_CR3_EBLEA);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Disable 802.15.4 end of activity interrupt for CPU1
* @rmtoll CR3 E802A LL_PWR_DisableIT_802A
@ -2491,6 +2524,7 @@ __STATIC_INLINE void LL_PWR_DisableIT_802A(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_E802A);
}
#endif
/**
* @brief Check if BLE end of activity interrupt is enabled for CPU1
@ -2502,6 +2536,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_BLEA(void)
return ((READ_BIT(PWR->CR3, PWR_CR3_EBLEA) == (PWR_CR3_EBLEA)) ? 1UL : 0UL);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Check if 802.15.4 end of activity interrupt is enabled for CPU1
* @rmtoll CR3 E802A LL_PWR_IsEnabledIT_802A
@ -2511,6 +2546,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_802A(void)
{
return ((READ_BIT(PWR->CR3, PWR_CR3_E802A) == (PWR_CR3_E802A)) ? 1UL : 0UL);
}
#endif
/**
* @brief Enable critical radio phase end of activity interrupt for CPU1
@ -2598,6 +2634,7 @@ __STATIC_INLINE void LL_C2_PWR_EnableIT_BLEWU(void)
SET_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Enable 802.15.4 host wakeup interrupt for CPU2
* @rmtoll C2CR3 E802WUP LL_C2_PWR_EnableIT_802WU
@ -2607,6 +2644,7 @@ __STATIC_INLINE void LL_C2_PWR_EnableIT_802WU(void)
{
SET_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP);
}
#endif
/**
* @brief Disable BLE host wakeup interrupt for CPU2
@ -2618,6 +2656,7 @@ __STATIC_INLINE void LL_C2_PWR_DisableIT_BLEWU(void)
CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Disable 802.15.4 host wakeup interrupt for CPU2
* @rmtoll C2CR3 E802WUP LL_C2_PWR_DisableIT_802WU
@ -2627,6 +2666,7 @@ __STATIC_INLINE void LL_C2_PWR_DisableIT_802WU(void)
{
CLEAR_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP);
}
#endif
/**
* @brief Check if BLE host wakeup interrupt is enabled for CPU2
@ -2638,6 +2678,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_BLEWU(void)
return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_EBLEWUP) == (PWR_C2CR3_EBLEWUP)) ? 1UL : 0UL);
}
#if defined(PWR_CR3_E802A)
/**
* @brief Check if 802.15.4 host wakeup interrupt is enabled for CPU2
* @rmtoll C2CR3 E802WUP LL_C2_PWR_IsEnabledIT_802WU
@ -2647,6 +2688,7 @@ __STATIC_INLINE uint32_t LL_C2_PWR_IsEnabledIT_802WU(void)
{
return ((READ_BIT(PWR->C2CR3, PWR_C2CR3_E802WUP) == (PWR_C2CR3_E802WUP)) ? 1UL : 0UL);
}
#endif
/**
* @}

164
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_rcc.c
View File

@ -72,9 +72,6 @@
#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
#if defined(SPI_I2S_SUPPORT)
#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
#endif
/**
* @}
*/
@ -83,34 +80,31 @@
/** @defgroup RCC_LL_Private_Functions RCC Private functions
* @{
*/
uint32_t RCC_PLL_GetFreqDomain_SYS(void);
static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
#if defined(SAI1)
uint32_t RCC_PLL_GetFreqDomain_SAI(void);
static uint32_t RCC_PLL_GetFreqDomain_SAI(void);
#endif
uint32_t RCC_PLL_GetFreqDomain_ADC(void);
uint32_t RCC_PLL_GetFreqDomain_48M(void);
static uint32_t RCC_PLL_GetFreqDomain_ADC(void);
static uint32_t RCC_PLL_GetFreqDomain_48M(void);
#if defined(SAI1)
uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void);
static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void);
static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void);
#endif
#if defined(SPI_I2S_SUPPORT)
uint32_t RCC_PLL_GetFreqDomain_I2S(void);
#endif
uint32_t RCC_GetSystemClockFreq(void);
static uint32_t RCC_GetSystemClockFreq(void);
uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency);
uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency);
uint32_t RCC_GetHCLK4ClockFreq(uint32_t SYSCLK_Frequency);
uint32_t RCC_GetHCLK5ClockFreq(void);
static uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency);
static uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency);
static uint32_t RCC_GetHCLK4ClockFreq(uint32_t SYSCLK_Frequency);
static uint32_t RCC_GetHCLK5ClockFreq(void);
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
/**
* @}
*/
@ -190,13 +184,17 @@ ErrorStatus LL_RCC_DeInit(void)
LL_RCC_WriteReg(CIER, 0x00000000U);
/* Clear all interrupt flags */
#if defined(SAI1)
vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLLSAI1RDYC | \
RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
#else
vl_mask = RCC_CICR_LSI1RDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
RCC_CICR_CSSC | RCC_CICR_HSI48RDYC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
RCC_CICR_CSSC | RCC_CICR_LSECSSC | RCC_CICR_LSI2RDYC;
#if defined(SAI1)
vl_mask |= RCC_CICR_PLLSAI1RDYC;
#endif
#if defined(RCC_HSI48_SUPPORT)
vl_mask |= RCC_CICR_HSI48RDYC;
#endif
LL_RCC_WriteReg(CICR, vl_mask);
/* Clear reset flags */
@ -210,8 +208,10 @@ ErrorStatus LL_RCC_DeInit(void)
/* RF Wakeup Clock Source selection */
LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_NONE);
#if defined(RCC_HSI48_SUPPORT)
/* HSI48 reset */
LL_RCC_HSI48_Disable();
#endif
/* HSECR register write unlock & then reset*/
LL_RCC_WriteReg(HSECR, HSE_CONTROL_UNLOCK_KEY);
@ -407,7 +407,8 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
* @brief Return I2Cx clock frequency
* @param I2CxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2C1_CLKSOURCE
* @arg @ref LL_RCC_I2C3_CLKSOURCE
* @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
* @note (*) Value not defined for all devices
* @retval I2C clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
*/
@ -689,6 +690,7 @@ uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource)
}
break;
#if defined(RCC_HSI48_SUPPORT)
case LL_RCC_CLK48_CLKSOURCE_HSI48: /* HSI48 clock used as CLK48 clock source */
default:
if (LL_RCC_HSI48_IsReady() == 1U)
@ -696,6 +698,11 @@ uint32_t LL_RCC_GetCLK48ClockFreq(uint32_t CLK48xSource)
clk48_frequency = HSI48_VALUE;
}
break;
#else
default:
/* Nothing to do */
break;
#endif
}
return clk48_frequency;
@ -853,7 +860,6 @@ uint32_t LL_RCC_GetRTCClockFreq(void)
uint32_t LL_RCC_GetRFWKPClockFreq(void)
{
uint32_t rfwkp_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
uint32_t temp = LL_RCC_LSI2_IsReady();
/* RTCCLK clock frequency */
switch (LL_RCC_GetRFWKPClockSource())
@ -865,13 +871,6 @@ uint32_t LL_RCC_GetRFWKPClockFreq(void)
}
break;
case LL_RCC_RFWKP_CLKSOURCE_LSI: /* LSI clock used as RF Wakeup clock source */
if ((LL_RCC_LSI1_IsReady() == 1UL) || (temp == 1UL))
{
rfwkp_frequency = LSI_VALUE;
}
break;
case LL_RCC_RFWKP_CLKSOURCE_HSE_DIV1024: /* HSE clock used as RF Wakeup clock source */
rfwkp_frequency = HSE_VALUE / 1024U;
break;
@ -885,46 +884,6 @@ uint32_t LL_RCC_GetRFWKPClockFreq(void)
return rfwkp_frequency;
}
#if defined(SPI_I2S_SUPPORT)
/**
* @brief Return I2Sx clock frequency
* @param I2SxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2S_CLKSOURCE
* @retval I2S clock frequency (in Hz)
* - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI) or PLLs (PLL) is not ready
*/
uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
{
uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check parameter */
assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
/* I2SCLK clock frequency */
switch (LL_RCC_GetI2SClockSource(I2SxSource))
{
case LL_RCC_I2S_CLKSOURCE_PLL: /* I2S2 Clock is PLL"P" */
if (LL_RCC_PLL_IsReady() == 1U)
{
i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
}
break;
case LL_RCC_I2S_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
i2s_frequency = EXTERNAL_CLOCK_VALUE;
break;
case LL_RCC_I2S_CLKSOURCE_HSI: /* HSI clock used as I2S clock source */
default:
if (LL_RCC_HSI_IsReady() == 1U)
{
i2s_frequency = HSI_VALUE;
}
break;
}
return i2s_frequency;
}
#endif
/**
* @}
@ -942,7 +901,7 @@ uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
* @brief Return SYSTEM clock (SYSCLK) frequency
* @retval SYSTEM clock frequency (in Hz)
*/
uint32_t RCC_GetSystemClockFreq(void)
static uint32_t RCC_GetSystemClockFreq(void)
{
uint32_t frequency;
@ -985,7 +944,7 @@ uint32_t RCC_GetSystemClockFreq(void)
* @param SYSCLK_Frequency SYSCLK clock frequency
* @retval HCLK1 clock frequency (in Hz)
*/
uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency)
static uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency)
{
/* HCLK clock frequency */
return __LL_RCC_CALC_HCLK1_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
@ -996,7 +955,7 @@ uint32_t RCC_GetHCLK1ClockFreq(uint32_t SYSCLK_Frequency)
* @param SYSCLK_Frequency SYSCLK clock frequency
* @retval HCLK2 clock frequency (in Hz)
*/
uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency)
static uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency)
{
/* HCLK clock frequency */
return __LL_RCC_CALC_HCLK2_FREQ(SYSCLK_Frequency, LL_C2_RCC_GetAHBPrescaler());
@ -1007,7 +966,7 @@ uint32_t RCC_GetHCLK2ClockFreq(uint32_t SYSCLK_Frequency)
* @param SYSCLK_Frequency SYSCLK clock frequency
* @retval HCLK4 clock frequency (in Hz)
*/
uint32_t RCC_GetHCLK4ClockFreq(uint32_t SYSCLK_Frequency)
static uint32_t RCC_GetHCLK4ClockFreq(uint32_t SYSCLK_Frequency)
{
/* HCLK clock frequency */
return __LL_RCC_CALC_HCLK4_FREQ(SYSCLK_Frequency, LL_RCC_GetAHB4Prescaler());
@ -1017,7 +976,7 @@ uint32_t RCC_GetHCLK4ClockFreq(uint32_t SYSCLK_Frequency)
* @brief Return HCLK5 clock frequency
* @retval HCLK5 clock frequency (in Hz)
*/
uint32_t RCC_GetHCLK5ClockFreq(void)
static uint32_t RCC_GetHCLK5ClockFreq(void)
{
uint32_t frequency;
@ -1047,7 +1006,7 @@ uint32_t RCC_GetHCLK5ClockFreq(void)
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK1 clock frequency (in Hz)
*/
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK1 clock frequency */
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
@ -1058,7 +1017,7 @@ uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
* @param HCLK_Frequency HCLK clock frequency
* @retval PCLK2 clock frequency (in Hz)
*/
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
{
/* PCLK2 clock frequency */
return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
@ -1068,7 +1027,7 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
* @brief Return PLL clock (PLLRCLK) frequency used for system domain
* @retval PLLRCLK clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
{
uint32_t pllinputfreq, pllsource;
@ -1111,7 +1070,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void)
* @brief Return PLL clock (PLLPCLK) frequency used for SAI domain
* @retval PLLPCLK clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_SAI(void)
static uint32_t RCC_PLL_GetFreqDomain_SAI(void)
{
uint32_t pllinputfreq, pllsource;
@ -1154,7 +1113,7 @@ uint32_t RCC_PLL_GetFreqDomain_SAI(void)
* @brief Return PLL clock (PLLPCLK) frequency used for ADC domain
* @retval PLLPCLK clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_ADC(void)
static uint32_t RCC_PLL_GetFreqDomain_ADC(void)
{
uint32_t pllinputfreq, pllsource;
@ -1198,7 +1157,7 @@ uint32_t RCC_PLL_GetFreqDomain_ADC(void)
* @brief Return PLL clock (PLLQCLK) frequency used for 48 MHz domain
* @retval PLLQCLK clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_48M(void)
static uint32_t RCC_PLL_GetFreqDomain_48M(void)
{
uint32_t pllinputfreq, pllsource;
@ -1242,7 +1201,7 @@ uint32_t RCC_PLL_GetFreqDomain_48M(void)
* @brief Return PLLSAI1 clock (PLLSAI1PCLK) frequency used for SAI domain
* @retval PLLSAI1PCLK clock frequency (in Hz)
*/
uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
{
uint32_t pllinputfreq, pllsource;
@ -1284,7 +1243,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void)
* @brief Return PLLSAI1 clock (PLLSAI1QCLK) frequency used for 48Mhz domain
* @retval PLLSAI1QCLK clock frequency (in Hz)
*/
uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
{
uint32_t pllinputfreq, pllsource;
@ -1325,7 +1284,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void)
* @brief Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain
* @retval PLLSAI1RCLK clock frequency (in Hz)
*/
uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
{
uint32_t pllinputfreq, pllsource;
@ -1363,35 +1322,6 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void)
}
#endif
#if defined(SPI_I2S_SUPPORT)
/**
* @brief Return PLL clock frequency used for I2S domain
* @retval PLL clock frequency (in Hz)
*/
uint32_t RCC_PLL_GetFreqDomain_I2S(void)
{
uint32_t pllinputfreq, pllsource;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
I2S Domain clock = PLL_VCO / PLLP
*/
pllsource = LL_RCC_PLL_GetMainSource();
switch (pllsource)
{
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllinputfreq = HSE_VALUE;
break;
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllinputfreq = HSI_VALUE;
break;
}
return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
}
#endif
/**
* @}

621
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_rcc.h
View File

File diff suppressed because it is too large Load Diff

6
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_rtc.h
View File

@ -334,14 +334,16 @@ typedef struct
* @}
*/
#if defined(RTC_OR_ALARMOUTTYPE)
/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
* @{
*/
#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
/**
* @}
*/
#endif
/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN
* @{
@ -830,6 +832,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
}
#if defined(RTC_OR_ALARMOUTTYPE)
/**
* @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
* @note Used only when RTC_ALARM is mapped on PC13
@ -858,6 +861,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));
}
#endif
/**
* @brief Enable initialization mode

120
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_tim.h
View File

@ -127,7 +127,11 @@ static const uint8_t SHIFT_TAB_OISx[] =
#define TIMx_OR_RMP_SHIFT 16U
#define TIMx_OR_RMP_MASK 0x0000FFFFU
#define TIM1_OR_RMP_MASK ((TIM1_OR_ETR_ADC1_RMP | TIM1_OR_TI1_RMP) << TIMx_OR_RMP_SHIFT)
#if defined(USB)
#define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP | TIM2_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
#else
#define TIM2_OR_RMP_MASK ((TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP) << TIMx_OR_RMP_SHIFT)
#endif
#if defined(TIM16)
#define TIM16_OR_RMP_MASK (TIM16_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
#endif /* TIM16 */
@ -598,8 +602,8 @@ typedef struct
/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
* @{
*/
#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
@ -1544,7 +1548,16 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
uint32_t counter_mode;
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
if (counter_mode == 0U)
{
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
}
return counter_mode;
}
/**
@ -1999,8 +2012,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@ -2044,8 +2057,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@ -2083,8 +2096,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@ -2117,7 +2130,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
@ -2149,7 +2162,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
@ -2186,7 +2199,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
@ -2218,7 +2231,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
@ -2243,8 +2256,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2269,8 +2282,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2295,9 +2308,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@ -2321,8 +2334,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2346,8 +2359,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2371,9 +2384,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@ -2400,8 +2413,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2427,8 +2440,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@ -2456,9 +2469,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@ -2727,8 +2740,8 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@ -2755,8 +2768,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@ -2779,8 +2792,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@ -2805,8 +2818,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@ -2830,8 +2843,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@ -2868,8 +2881,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@ -2905,8 +2918,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@ -2934,7 +2947,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
@ -2962,7 +2975,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}
@ -3361,7 +3374,6 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u
*/
__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
{
MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
}
@ -3700,7 +3712,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
*/
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
SET_BIT(*pReg, Source);
}
@ -3728,7 +3740,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B
*/
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
CLEAR_BIT(*pReg, Source);
}
@ -3760,7 +3772,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
uint32_t Polarity)
{
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
}
/**

54
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_usart.c
View File

@ -75,9 +75,6 @@
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
@ -249,9 +246,6 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini
/* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
/* Check BRR is lower than or equal to 0xFFFF */
assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
}
/*---------------------------- USART PRESC Configuration -----------------------
@ -289,7 +283,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
@ -309,37 +303,25 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
/*---------------------------- USART CR2 Configuration -----------------------*/
/* If Clock signal has to be output */
if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
{
/* Deactivate Clock signal delivery :
* - Disable Clock Output: USART_CR2_CLKEN cleared
*/
LL_USART_DisableSCLKOutput(USARTx);
}
else
{
/* Ensure USART instance is USART capable */
assert_param(IS_USART_INSTANCE(USARTx));
/* Ensure USART instance is USART capable */
assert_param(IS_USART_INSTANCE(USARTx));
/* Check clock related parameters */
assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
/* Check clock related parameters */
assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
/*---------------------------- USART CR2 Configuration -----------------------
* Configure USARTx CR2 (Clock signal related bits) with parameters:
* - Enable Clock Output: USART_CR2_CLKEN set
* - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
* - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
* - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
*/
MODIFY_REG(USARTx->CR2,
USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
}
/*---------------------------- USART CR2 Configuration -----------------------
* Configure USARTx CR2 (Clock signal related bits) with parameters:
* - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value
* - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
* - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
* - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
*/
MODIFY_REG(USARTx->CR2,
USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity |
USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
}
/* Else (USART not in Disabled state => return ERROR */
else

559
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_usb.c
View File

@ -56,8 +56,8 @@
/**
* @brief Initializes the USB Core
* @param USBx: USB Instance
* @param cfg : pointer to a USB_CfgTypeDef structure that contains
* @param USBx USB Instance
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@ -78,13 +78,16 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
/**
* @brief USB_EnableGlobalInt
* Enables the controller's Global Int in the AHB Config reg
* @param USBx : Selected device
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
{
uint32_t winterruptmask;
/* Clear pending interrupts */
USBx->ISTR = 0U;
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
USB_CNTR_SUSPM | USB_CNTR_ERRM |
@ -92,7 +95,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
USB_CNTR_RESETM | USB_CNTR_L1REQM;
/* Set interrupt mask */
USBx->CNTR |= (uint16_t)winterruptmask;
USBx->CNTR = (uint16_t)winterruptmask;
return HAL_OK;
}
@ -100,9 +103,9 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx)
/**
* @brief USB_DisableGlobalInt
* Disable the controller's Global Int in the AHB Config reg
* @param USBx : Selected device
* @param USBx Selected device
* @retval HAL status
*/
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
uint32_t winterruptmask;
@ -120,11 +123,11 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
}
/**
* @brief USB_SetCurrentMode : Set functional mode
* @param USBx : Selected device
* @param mode : current core mode
* @brief USB_SetCurrentMode Set functional mode
* @param USBx Selected device
* @param mode current core mode
* This parameter can be one of the these values:
* @arg USB_DEVICE_MODE: Peripheral mode mode
* @arg USB_DEVICE_MODE Peripheral mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
@ -141,10 +144,10 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
}
/**
* @brief USB_DevInit : Initializes the USB controller registers
* @brief USB_DevInit Initializes the USB controller registers
* for device mode
* @param USBx : Selected device
* @param cfg : pointer to a USB_CfgTypeDef structure that contains
* @param USBx Selected device
* @param cfg pointer to a USB_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@ -154,89 +157,26 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg)
UNUSED(cfg);
/* Init Device */
/*CNTR_FRES = 1*/
/* CNTR_FRES = 1 */
USBx->CNTR = (uint16_t)USB_CNTR_FRES;
/*CNTR_FRES = 0*/
/* CNTR_FRES = 0 */
USBx->CNTR = 0U;
/*Clear pending interrupts*/
/* Clear pending interrupts */
USBx->ISTR = 0U;
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
/* Enable USB Device Interrupt mask */
(void)USB_EnableGlobalInt(USBx);
return HAL_OK;
}
/**
* @brief USB_SetDevSpeed :Initializes the device speed
* depending on the PHY type and the enumeration speed of the device.
* @param USBx Selected device
* @param speed device speed
* @retval Hal status
*/
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(speed);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_FlushTxFifo : Flush a Tx FIFO
* @param USBx : Selected device
* @param num : FIFO number
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(num);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_FlushRxFifo : Flush Rx FIFO
* @param USBx : Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
#if defined (HAL_PCD_MODULE_ENABLED)
/**
* @brief Activate and configure an endpoint
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@ -297,9 +237,11 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
/*Set the endpoint Receive buffer address */
PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress);
/*Set the endpoint Receive buffer counter*/
PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket);
PCD_CLEAR_RX_DTOG(USBx, ep->num);
/* Configure VALID status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
@ -309,6 +251,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
/* Set the endpoint as double buffered */
PCD_SET_EP_DBUF(USBx, ep->num);
/* Set buffer address for double buffered mode */
PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1);
@ -318,9 +261,6 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
/* Reset value of the data toggle bits for the endpoint out */
PCD_TX_DTOG(USBx, ep->num);
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
@ -329,7 +269,6 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
PCD_RX_DTOG(USBx, ep->num);
if (ep->type != EP_TYPE_ISOC)
{
@ -351,8 +290,8 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
/**
* @brief De-activate and de-initialize an endpoint
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@ -362,12 +301,14 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
if (ep->is_in != 0U)
{
PCD_CLEAR_TX_DTOG(USBx, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
else
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
}
@ -393,6 +334,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
PCD_RX_DTOG(USBx, ep->num);
/* Configure DISABLE status for the Endpoint*/
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS);
@ -403,15 +345,16 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep)
}
/**
* @brief USB_EPStartXfer : setup and starts a transfer over an EP
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @brief USB_EPStartXfer setup and starts a transfer over an EP
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
uint16_t pmabuffer;
uint32_t len;
uint16_t pmabuffer;
uint16_t wEPVal;
/* IN endpoint */
if (ep->is_in == 1U)
@ -420,12 +363,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len -= len;
}
else
{
len = ep->xfer_len;
ep->xfer_len = 0U;
}
/* configure and validate Tx endpoint */
@ -436,49 +377,225 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
}
else
{
/* Write the data to the USB endpoint */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
/* double buffer bulk management */
if (ep->type == EP_TYPE_BULK)
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
}
if (ep->xfer_len_db > ep->maxpacket)
{
/* enable double buffer */
PCD_SET_EP_DBUF(USBx, ep->num);
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
/* Fill the two first buffer in the Buffer0 & Buffer1 */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
ep->xfer_buff += len;
if (ep->xfer_len_db > ep->maxpacket)
{
ep->xfer_len_db -= len;
}
else
{
len = ep->xfer_len_db;
ep->xfer_len_db = 0U;
}
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
ep->xfer_buff += len;
if (ep->xfer_len_db > ep->maxpacket)
{
ep->xfer_len_db -= len;
}
else
{
len = ep->xfer_len_db;
ep->xfer_len_db = 0U;
}
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
}
/* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer */
else
{
len = ep->xfer_len_db;
/* disable double buffer mode */
PCD_CLEAR_EP_DBUF(USBx, ep->num);
/* Set Tx count with nbre of byte to be transmitted */
PCD_SET_EP_TX_CNT(USBx, ep->num, len);
pmabuffer = ep->pmaaddr0;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
}/* end if bulk double buffer */
/* manage isochronous double buffer IN mode */
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
/* enable double buffer */
PCD_SET_EP_DBUF(USBx, ep->num);
/* each Time to write in PMA xfer_len_db will */
ep->xfer_len_db -= len;
/* Fill the data buffer */
if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
ep->xfer_buff += len;
if (ep->xfer_len_db > ep->maxpacket)
{
ep->xfer_len_db -= len;
}
else
{
len = ep->xfer_len_db;
ep->xfer_len_db = 0U;
}
if (len > 0U)
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
}
else
{
/* Set the Double buffer counter for pmabuffer0 */
PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr0;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
ep->xfer_buff += len;
if (ep->xfer_len_db > ep->maxpacket)
{
ep->xfer_len_db -= len;
}
else
{
len = ep->xfer_len_db;
ep->xfer_len_db = 0U;
}
if (len > 0U)
{
/* Set the Double buffer counter for pmabuffer1 */
PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
pmabuffer = ep->pmaaddr1;
/* Write the user buffer to USB PMA */
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
}
}
}
USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
}
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
}
else /* OUT endpoint */
{
/* Multi packet transfer*/
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len -= len;
}
else
{
len = ep->xfer_len;
ep->xfer_len = 0U;
}
/* configure and validate Rx endpoint */
if (ep->doublebuffer == 0U)
{
/*Set RX buffer count*/
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len -= len;
}
else
{
len = ep->xfer_len;
ep->xfer_len = 0U;
}
/* configure and validate Rx endpoint */
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
else
{
/*Set the Double buffer counter*/
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
/* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */
/* Set the Double buffer counter */
if (ep->type == EP_TYPE_BULK)
{
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
/* Coming from ISR */
if (ep->xfer_count != 0U)
{
/* update last value to check if there is blocking state */
wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
/*Blocking State */
if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
(((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
{
PCD_FreeUserBuffer(USBx, ep->num, 0U);
}
}
}
/* iso out double */
else if (ep->type == EP_TYPE_ISOC)
{
/* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
ep->xfer_len -= len;
}
else
{
len = ep->xfer_len;
ep->xfer_len = 0U;
}
PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
}
else
{
return HAL_ERROR;
}
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
@ -487,54 +604,11 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep)
return HAL_OK;
}
/**
* @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
* with the EP/channel
* @param USBx : Selected device
* @param src : pointer to source buffer
* @param ch_ep_num : endpoint or host channel number
* @param len : Number of bytes to write
* @retval HAL status
*/
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(src);
UNUSED(ch_ep_num);
UNUSED(len);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_ReadPacket : read a packet from the Tx FIFO associated
* with the EP/channel
* @param USBx : Selected device
* @param dest : destination pointer
* @param len : Number of bytes to read
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(dest);
UNUSED(len);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return ((void *)NULL);
}
/**
* @brief USB_EPSetStall : set a stall condition over an EP
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @brief USB_EPSetStall set a stall condition over an EP
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@ -552,9 +626,9 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
}
/**
* @brief USB_EPClearStall : Clear a stall condition over an EP
* @param USBx : Selected device
* @param ep: pointer to endpoint structure
* @brief USB_EPClearStall Clear a stall condition over an EP
* @param USBx Selected device
* @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
@ -575,17 +649,18 @@ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep)
{
PCD_CLEAR_RX_DTOG(USBx, ep->num);
/* Configure VALID status for the Endpoint*/
/* Configure VALID status for the Endpoint */
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
}
}
return HAL_OK;
}
#endif
/**
* @brief USB_StopDevice : Stop the usb device mode
* @param USBx : Selected device
* @brief USB_StopDevice Stop the usb device mode
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
@ -603,9 +678,9 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx)
}
/**
* @brief USB_SetDevAddress : Stop the usb device mode
* @param USBx : Selected device
* @param address : new device address to be assigned
* @brief USB_SetDevAddress Stop the usb device mode
* @param USBx Selected device
* @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
@ -621,8 +696,8 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address)
}
/**
* @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
* @param USBx : Selected device
* @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
@ -634,8 +709,8 @@ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx)
}
/**
* @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx : Selected device
* @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
@ -647,8 +722,8 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx)
}
/**
* @brief USB_ReadInterrupts: return the global USB interrupt status
* @param USBx : Selected device
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
@ -659,114 +734,9 @@ uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
return tmpreg;
}
/**
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
* @param USBx : Selected device
* @retval HAL status
*/
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return (0);
}
/**
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
* @param USBx : Selected device
* @retval HAL status
*/
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return (0);
}
/**
* @brief Returns Device OUT EP Interrupt register
* @param USBx : Selected device
* @param epnum : endpoint number
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(epnum);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return (0);
}
/**
* @brief Returns Device IN EP Interrupt register
* @param USBx : Selected device
* @param epnum : endpoint number
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(epnum);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return (0);
}
/**
* @brief USB_ClearInterrupts: clear a USB interrupt
* @param USBx Selected device
* @param interrupt interrupt flag
* @retval None
*/
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(interrupt);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
}
/**
* @brief Prepare the EP0 to start the first control setup
* @param USBx Selected device
* @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(USBx);
UNUSED(psetup);
/* NOTE : - This function is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral.
- This function is added to ensure compatibility across platforms.
*/
return HAL_OK;
}
/**
* @brief USB_ActivateRemoteWakeup : active remote wakeup signalling
* @param USBx Selected device
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
@ -777,13 +747,14 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx)
}
/**
* @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling
* @param USBx Selected device
* @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling
* @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
{
USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
return HAL_OK;
}
@ -792,7 +763,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx)
* @param USBx USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
@ -822,11 +793,11 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui
}
/**
* @brief Copy a buffer from user memory area to packet memory area (PMA)
* @param USBx: USB peripheral instance register address.
* @brief Copy data from packet memory area (PMA) to user memory buffer
* @param USBx USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
* @param wNBytes: no. of bytes to be copied.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)

36
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_usb.h
View File

@ -118,6 +118,10 @@ typedef struct
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
} USB_EPTypeDef;
@ -131,10 +135,10 @@ typedef struct
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
#define EP_MPS_64 0U
#define EP_MPS_32 1U
#define EP_MPS_16 2U
#define EP_MPS_8 3U
/**
* @}
*/
@ -183,32 +187,28 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num);
#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len);
void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
#endif
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum);
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
/**
* @}

14
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_ll_utils.c
View File

@ -258,7 +258,7 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
*/
ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
{
ErrorStatus status = SUCCESS;
ErrorStatus status = ERROR;
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
uint16_t index;
uint32_t timeout;
@ -283,11 +283,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
const uint32_t UTILS_LATENCY_RANGE[] = {LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2, LL_FLASH_LATENCY_3};
/* Frequency cannot be equal to 0 or greater than max clock */
if ((HCLK4Frequency == 0U) || (HCLK4Frequency > maxfreq))
{
status = ERROR;
}
else
if ((HCLK4Frequency > 0U) && (HCLK4Frequency <= maxfreq))
{
#if defined(PWR_CR1_VOS)
if (voltagescaling == LL_PWR_REGU_VOLTAGE_SCALE1)
@ -297,6 +293,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
{
latency = UTILS_LATENCY_RANGE[index];
status = SUCCESS;
break;
}
}
@ -308,6 +305,7 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS2[index])
{
latency = UTILS_LATENCY_RANGE[index];
status = SUCCESS;
break;
}
}
@ -318,11 +316,15 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK4Frequency)
if (HCLK4Frequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
{
latency = UTILS_LATENCY_RANGE[index];
status = SUCCESS;
break;
}
}
#endif
}
if (status != ERROR)
{
LL_FLASH_SetLatency(latency);
/* Check that the new number of wait states is taken into account to access the Flash

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