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[M487] Align with BSP

pull/4608/head
ccli8 2017-06-09 17:42:21 +08:00
parent 23672b09a2
commit b7dedbe917
22 changed files with 966 additions and 456 deletions
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62
targets/TARGET_NUVOTON/TARGET_M480/device/M480.h
View File

@ -618,7 +618,7 @@ typedef struct {
* | | |This bit is used to control HSUSB PHY at reset state or active state.
* | | |0 = HSUSB PHY at reset state.
* | | |1 = HSUSB PHY at active state.
* | | |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode.
* | | |Note: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode.
* @var SYS_T::GPA_MFPL
* Offset: 0x30 GPIOA Low Byte Multiple Function Control Register
* ---------------------------------------------------------------------------------------------------
@ -2151,13 +2151,12 @@ typedef struct {
* | | |01 = Set core voltage to 1.2V.
* | | |10 = Set core voltage to 0.9V.
* | | |11 = Reserved.
* |[21:16] |CVSSTEP |Core Voltage Scaling Step(Write Protect)
* | | |This bit filed set voltage step when core voltage is changing. The unit is 10mV.
* | | |Core voltage scaling voltage step = (CVSSTEP + 1) * 10mV.
* |[31:24] |CVSPRD |Core Voltage Scaling Period(Write Protect)
* | | |This bit filed sets period between voltage steps when core voltage is changing. The unit is us.
* | | |If CVSPRD = 0 , the period between two core voltage steps is 1us.
* | | |Core voltage scaling period = (CVSPRD + 1) * 1us.
* |[21:16] |LVSSTEP |LDO Voltage Scaling Step(Write Protect)
* | | |The LVSSTEP value is LDO voltage rising step.
* | | |Core voltage scaling voltage step = (LVSSTEP + 1) * 10mV.
* |[31:24] |LVSPRD |LDO Voltage Scaling Period(Write Protect)
* | | |The LVSPRD value is the period of each LDO voltage rising step.
* | | |LDO voltage scaling period = (LVSPRD + 1) * 1us.
* @var SYS_T::PLSTS
* Offset: 0x1FC Power Level Status Register
* ---------------------------------------------------------------------------------------------------
@ -2168,12 +2167,10 @@ typedef struct {
* | | |After core voltage change is completed, this bit will be cleared automatically by hardware.
* | | |0 = Core voltage change is completed.
* | | |1 = Core voltage change is ongoing.
* |[9:8] |CURPL |Current Power Level (Read Only)
* | | |This bit field reflect the current core voltage level.
* | | |00 = Current core voltage is 1.26V.
* | | |01 = Current core voltage is 1.2V.
* | | |10 = Current core voltage is 0.9V.
* | | |11 = Reserved.
* |[9:8] |PLSTATUS |Power Level Status (Read Only)
* | | |00 = Power level is PL0.
* | | |01 = Power level is PL1.
* | | |Others = Reserved.
* @var SYS_T::AHBMCTL
* Offset: 0x400 AHB Bus Matrix Priority Control Register
* ---------------------------------------------------------------------------------------------------
@ -3406,17 +3403,17 @@ typedef struct {
#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */
#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */
#define SYS_PLCTL_CVSSTEP_Pos (16) /*!< SYS_T::PLCTL: CVSSTEP Position */
#define SYS_PLCTL_CVSSTEP_Msk (0x3ful << SYS_PLCTL_CVSSTEP_Pos) /*!< SYS_T::PLCTL: CVSSTEP Mask */
#define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */
#define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */
#define SYS_PLCTL_CVSPRD_Pos (24) /*!< SYS_T::PLCTL: CVSPRD Position */
#define SYS_PLCTL_CVSPRD_Msk (0xfful << SYS_PLCTL_CVSPRD_Pos) /*!< SYS_T::PLCTL: CVSPRD Mask */
#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */
#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */
#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */
#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */
#define SYS_PLSTS_CURPL_Pos (8) /*!< SYS_T::PLSTS: CURPL Position */
#define SYS_PLSTS_CURPL_Msk (0x3ul << SYS_PLSTS_CURPL_Pos) /*!< SYS_T::PLSTS: CURPL Mask */
#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */
#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */
#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */
#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */
@ -32564,12 +32561,12 @@ typedef struct {
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |SADDR |ECC DMA Source Address
* | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between
* | | |SRAM memory space and ECC accelerator. The SADDR keeps the source address of the data
* | | |buffer where the source text is stored. Based on the source address, the ECC accelerator
* | | |can read the DATA and PARAMETER from SRAM memory space and do ECC operation. The start
* | | |of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are
* | | |ignored. SADDR can be read and written. In DMA mode, software must update the CRPT_ECC_SADDR
* | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between
* | | |SRAM memory space and ECC accelerator. The SADDR keeps the source address of the data
* | | |buffer where the source text is stored. Based on the source address, the ECC accelerator
* | | |can read the DATA and PARAMETER from SRAM memory space and do ECC operation. The start
* | | |of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are
* | | |ignored. SADDR can be read and written. In DMA mode, software must update the CRPT_ECC_SADDR
* | | |before triggering START.
* @var CRPT_T::ECC_DADDR
* Offset: 0xA4C ECC DMA Destination Address Register
@ -35522,6 +35519,15 @@ typedef struct {
#define OPA_CALCTL_CALTRG2_Pos (2) /*!< OPA_T::CALCTL: CALTRG2 Position */
#define OPA_CALCTL_CALTRG2_Msk (0x1ul << OPA_CALCTL_CALTRG2_Pos) /*!< OPA_T::CALCTL: CALTRG2 Mask */
#define OPA_CALCTL_CALCLK0_Pos (4) /*!< OPA_T::CALCTL: CALCLK0 Position */
#define OPA_CALCTL_CALCLK0_Msk (0x3ul << OPA_CALCTL_CALCLK0_Pos) /*!< OPA_T::CALCTL: CALCLK0 Mask */
#define OPA_CALCTL_CALCLK1_Pos (6) /*!< OPA_T::CALCTL: CALCLK1 Position */
#define OPA_CALCTL_CALCLK1_Msk (0x3ul << OPA_CALCTL_CALCLK1_Pos) /*!< OPA_T::CALCTL: CALCLK1 Mask */
#define OPA_CALCTL_CALCLK2_Pos (8) /*!< OPA_T::CALCTL: CALCLK2 Position */
#define OPA_CALCTL_CALCLK2_Msk (0x3ul << OPA_CALCTL_CALCLK2_Pos) /*!< OPA_T::CALCTL: CALCLK2 Mask */
#define OPA_CALCTL_CALRVS0_Pos (16) /*!< OPA_T::CALCTL: CALRVS0 Position */
#define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) /*!< OPA_T::CALCTL: CALRVS0 Mask */
@ -35637,7 +35643,7 @@ typedef struct {
#define ACMP_BASE (APBPERIPH_BASE + 0x05000UL)
#define USBD_BASE (APBPERIPH_BASE + 0x80000UL)
#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL)
#define HSOTG_BASE (APBPERIPH_BASE + 0x0D000UL)
#define HSOTG_BASE (APBPERIPH_BASE + 0x0F000UL)
#define TIMER2_BASE (APBPERIPH_BASE + 0x11000UL)
#define TIMER3_BASE (APBPERIPH_BASE + 0x11100UL)
#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL)
@ -35996,6 +36002,8 @@ typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile
#include "m480_sdh.h"
#include "m480_usbd.h"
#include "m480_hsusbd.h"
#include "m480_otg.h"
#include "m480_hsotg.h"
#ifdef __cplusplus

10
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_can.c
View File

@ -656,13 +656,11 @@ uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
SystemCoreClockUpdate();
if(tCAN == CAN0) {
if(CLK->CLKSEL0 & ((uint32_t)1 << 6)) {
u64PCLK_DIV = (uint64_t)2;
}
u64PCLK_DIV = (uint64_t)(CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk);
u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV);
} else if(tCAN == CAN1) {
if(CLK->CLKSEL0 & ((uint32_t)1 << 7)) {
u64PCLK_DIV = (uint64_t)2;
}
u64PCLK_DIV = (uint64_t)((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) >> CLK_PCLKDIV_APB1DIV_Pos);
u64PCLK_DIV = (uint64_t)(1 << u64PCLK_DIV);
}
clock_freq = SystemCoreClock / u64PCLK_DIV;

2
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_clk.h
View File

@ -516,7 +516,7 @@ __STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
u32PllReg = CLK->PLLCTL;
if((u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) == (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) {
if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) {
u32PllFreq = 0UL; /* PLL is in power down mode or fix low */
} else if((u32PllReg & CLK_PLLCTL_BP_Msk) == CLK_PLLCTL_BP_Msk) {
if((u32PllReg & CLK_PLLCTL_PLLSRC_HIRC) == CLK_PLLCTL_PLLSRC_HIRC) {

65
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_crypto.c
View File

@ -46,6 +46,9 @@ static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count);
static char get_Nth_nibble_char(uint32_t val32, uint32_t idx);
static void Hex2Reg(char input[], uint32_t volatile reg[]);
static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]);
static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift);
static char ch2hex(char ch);
static int get_nibble_value(char c);
/** @endcond HIDDEN_SYMBOLS */
@ -757,12 +760,13 @@ static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) { }
static char ch2hex(char ch)
{
if (ch <= '9') {
return ch - '0';
ch = ch - '0';
} else if ((ch <= 'z') && (ch >= 'a')) {
return ch - 'a' + 10U;
ch = ch - 'a' + 10U;
} else {
return ch - 'A' + 10U;
ch = ch - 'A' + 10U;
}
return ch;
}
static void Hex2Reg(char input[], uint32_t volatile reg[])
@ -787,26 +791,26 @@ static void Hex2Reg(char input[], uint32_t volatile reg[])
static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift)
{
int hex, carry;
uint32_t hex, carry;
int si, ri;
uint32_t i, val32;
si = (int)strlen(input) - 1;
ri = 0;
carry = 0;
ri = 0L;
carry = 0UL;
while (si >= 0) {
val32 = 0UL;
for (i = 0UL; (i < 8UL) && (si >= 0); i++) {
hex = ch2hex(input[si]);
for (i = 0UL; (i < 8UL) && (si >= 0L); i++) {
hex = (uint32_t)ch2hex(input[si]);
hex <<= shift;
val32 |= (uint32_t)((hex & 0xF) | carry) << (i * 4UL);
carry = (hex >> 4) & 0xF;
val32 |= (uint32_t)((hex & 0xFUL) | carry) << (i * 4UL);
carry = (hex >> 4UL) & 0xFUL;
si--;
}
reg[ri++] = val32;
}
if (carry != 0) {
if (carry != 0UL) {
reg[ri] = carry;
}
}
@ -905,17 +909,17 @@ static int32_t ecc_init_curve(E_ECC_CURVE ecc_curve)
static int get_nibble_value(char c)
{
if ((c >= '0') && (c <= '9')) {
return c - '0';
c = c - '0';
}
if ((c >= 'a') && (c <= 'f')) {
return c - 'a' - 10;
c = c - 'a' - (char)10;
}
if ((c >= 'A') && (c <= 'F')) {
return c - 'A' - 10;
c = c - 'A' - (char)10;
}
return 0;
return (int)c;
}
volatile uint32_t g_ECC_done, g_ECCERR_done;
@ -950,35 +954,36 @@ void ECC_DriverISR(void)
* @return 0 Is not valid.
* @return -1 Invalid curve.
*/
int ECC_IsPrivateKeyValid(E_ECC_CURVE ecc_curve, char *private_k)
int ECC_IsPrivateKeyValid(E_ECC_CURVE ecc_curve, char private_k[])
{
int i;
uint32_t i;
int ret = -1;
pCurve = get_curve(ecc_curve);
if (pCurve == NULL) {
return -1;
ret = -1;
}
if (strlen(private_k) < strlen(pCurve->Eorder)) {
return 1;
ret = 1;
}
if (strlen(private_k) > strlen(pCurve->Eorder)) {
return 0;
ret = 0;
}
for (i = 0; i < strlen(private_k); i++) {
for (i = 0UL; i < strlen(private_k); i++) {
if (get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i])) {
return 1;
ret = 1;
break;
}
}
return 0;
return ret;
}
/**
* @brief Given a private key and curve to generate the public key pair.
* @param[in] private_k The input private key
.
* @param[in] private_k The input private key.
* @param[in] ecc_curve The pre-defined ECC curve.
* @param[out] public_k1 The output public key 1.
* @param[out] public_k2 The output public key 2.
@ -995,9 +1000,9 @@ int32_t ECC_GeneratePublicKey(E_ECC_CURVE ecc_curve, char *private_k, char publ
if (ret == 0) {
for (i = 0; i < 18; i++)
for (i = 0; i < 18; i++) {
CRPT->ECC_K[i] = 0UL;
}
Hex2Reg(private_k, CRPT->ECC_K);
/* set FSEL (Field selection) */
@ -1152,8 +1157,9 @@ int32_t ECC_GenerateSignature(E_ECC_CURVE ecc_curve, char *message,
*/
/* 3-(4) Write the random integer k to K register */
for (i = 0; i < 18; i++)
for (i = 0; i < 18; i++) {
CRPT->ECC_K[i] = 0UL;
}
Hex2Reg(k, CRPT->ECC_K);
run_ecc_codec(ECCOP_POINT_MUL);
@ -1224,8 +1230,9 @@ int32_t ECC_GenerateSignature(E_ECC_CURVE ecc_curve, char *message,
CRPT->ECC_Y1[0] = 0x1UL;
/* 4-(3) Write the random integer k to X1 registers */
for (i = 0; i < 18; i++)
for (i = 0; i < 18; i++) {
CRPT->ECC_X1[i] = 0UL;
}
Hex2Reg(k, CRPT->ECC_X1);
run_ecc_codec(ECCOP_MODULE | MODOP_DIV);

2
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_crypto.h
View File

@ -315,7 +315,7 @@ void SHA_Start(uint32_t u32DMAMode);
void SHA_SetDMATransfer(uint32_t u32SrcAddr, uint32_t u32TransCnt);
void SHA_Read(uint32_t u32Digest[]);
void ECC_DriverISR(void);
int ECC_IsPrivateKeyValid(E_ECC_CURVE ecc_curve, char *private_k);
int ECC_IsPrivateKeyValid(E_ECC_CURVE ecc_curve, char private_k[]);
int32_t ECC_GeneratePublicKey(E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]);
int32_t ECC_GenerateSecretZ(E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]);
int32_t ECC_GenerateSignature(E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S);

127
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_emac.c
View File

@ -25,11 +25,6 @@
/** @addtogroup M480_EMAC_EXPORTED_CONSTANTS EMAC Exported Constants
@{
*/
/* Un-comment to print EMAC debug message */
#define EMAC_DBG
#ifndef EMAC_DBG
#define printf(...)
#endif
/* PHY Register Description */
#define PHY_CNTL_REG 0x00UL /*!< PHY control register address */
@ -389,8 +384,7 @@ void EMAC_Open(uint8_t *pu8MacAddr)
/* Configure the MAC control register. */
EMAC->CTL = EMAC_CTL_STRIPCRC_Msk |
EMAC_CTL_RMIIEN_Msk |
EMAC_CTL_RMIIRXCTL_Msk;
EMAC_CTL_RMIIEN_Msk;
/* Accept packets for us and all broadcast and multicast packets */
EMAC->CAMCTL = EMAC_CAMCTL_CMPEN_Msk |
@ -409,6 +403,7 @@ void EMAC_Open(uint8_t *pu8MacAddr)
void EMAC_Close(void)
{
EMAC->CTL |= EMAC_CTL_RST_Msk;
while(EMAC->CTL & EMAC_CTL_RST_Msk) {}
}
/**
@ -479,9 +474,7 @@ uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size)
if (reg & EMAC_INTSTS_RXBEIF_Msk) {
/* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
while(1) {
;
}
while(1) {}
} else {
/* Get Rx Frame Descriptor */
@ -500,18 +493,10 @@ uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size)
u32Count = 1UL;
} else {
/* Save Error status if necessary */
if (status & EMAC_RXFD_RP) {
;
}
if (status & EMAC_RXFD_ALIE) {
;
}
if (status & EMAC_RXFD_PTLE) {
;
}
if (status & EMAC_RXFD_CRCE) {
;
}
if (status & EMAC_RXFD_RP) {}
if (status & EMAC_RXFD_ALIE) {}
if (status & EMAC_RXFD_PTLE) {}
if (status & EMAC_RXFD_CRCE) {}
}
}
}
@ -543,9 +528,7 @@ uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec,
if (reg & EMAC_INTSTS_RXBEIF_Msk) {
/* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
while(1) {
;
}
while(1) {}
} else {
/* Get Rx Frame Descriptor */
@ -569,18 +552,10 @@ uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec,
u32Count = 1UL;
} else {
/* Save Error status if necessary */
if (status & EMAC_RXFD_RP) {
;
}
if (status & EMAC_RXFD_ALIE) {
;
}
if (status & EMAC_RXFD_PTLE) {
;
}
if (status & EMAC_RXFD_CRCE) {
;
}
if (status & EMAC_RXFD_RP) {}
if (status & EMAC_RXFD_ALIE) {}
if (status & EMAC_RXFD_PTLE) {}
if (status & EMAC_RXFD_CRCE) {}
}
}
}
@ -605,15 +580,15 @@ void EMAC_RecvPktDone(void)
desc->u32Data = desc->u32Backup1;
desc->u32Next = desc->u32Backup2;
/* Change ownership to DMA for next use */
desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
/* Get Next Frame Descriptor pointer to process */
desc = (EMAC_DESCRIPTOR_T *)desc->u32Next;
/* Save last processed Rx descriptor */
u32CurrentRxDesc = (uint32_t)desc;
/* Change ownership to DMA for next use */
desc->u32Status1 |= EMAC_DESC_OWN_EMAC;
EMAC_TRIGGER_RX();
}
@ -679,9 +654,7 @@ uint32_t EMAC_SendPktDone(void)
if (reg & EMAC_INTSTS_TXBEIF_Msk) {
/* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
while(1) {
;
}
while(1) {}
} else {
/* Process the descriptor(s). */
last_tx_desc = EMAC->CTXDSA ;
@ -698,30 +671,14 @@ uint32_t EMAC_SendPktDone(void)
u32Count++;
} else {
/* Do nothing here on error. */
if (status & EMAC_TXFD_TXABT) {
;
}
if (status & EMAC_TXFD_DEF) {
;
}
if (status & EMAC_TXFD_PAU) {
;
}
if (status & EMAC_TXFD_EXDEF) {
;
}
if (status & EMAC_TXFD_NCS) {
;
}
if (status & EMAC_TXFD_SQE) {
;
}
if (status & EMAC_TXFD_LC) {
;
}
if (status & EMAC_TXFD_TXHA) {
;
}
if (status & EMAC_TXFD_TXABT) {}
if (status & EMAC_TXFD_DEF) {}
if (status & EMAC_TXFD_PAU) {}
if (status & EMAC_TXFD_EXDEF) {}
if (status & EMAC_TXFD_NCS) {}
if (status & EMAC_TXFD_SQE) {}
if (status & EMAC_TXFD_LC) {}
if (status & EMAC_TXFD_TXHA) {}
}
/* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */
@ -760,9 +717,7 @@ uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec)
if (reg & EMAC_INTSTS_TXBEIF_Msk) {
/* Bus error occurred, this is usually a bad sign about software bug and will occur again... */
while(1) {
;
}
while(1) {}
} else {
/* Process the descriptor.
Get our first descriptor to process */
@ -778,30 +733,14 @@ uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec)
*pu32Nsec = EMAC_Subsec2Nsec(desc->u32Data); /* Sub nano second store in DATA field */
} else {
/* Do nothing here on error. */
if (status & EMAC_TXFD_TXABT) {
;
}
if (status & EMAC_TXFD_DEF) {
;
}
if (status & EMAC_TXFD_PAU) {
;
}
if (status & EMAC_TXFD_EXDEF) {
;
}
if (status & EMAC_TXFD_NCS) {
;
}
if (status & EMAC_TXFD_SQE) {
;
}
if (status & EMAC_TXFD_LC) {
;
}
if (status & EMAC_TXFD_TXHA) {
;
}
if (status & EMAC_TXFD_TXABT) {}
if (status & EMAC_TXFD_DEF) {}
if (status & EMAC_TXFD_PAU) {}
if (status & EMAC_TXFD_EXDEF) {}
if (status & EMAC_TXFD_NCS) {}
if (status & EMAC_TXFD_SQE) {}
if (status & EMAC_TXFD_LC) {}
if (status & EMAC_TXFD_TXHA) {}
}
/* restore descriptor link list and data pointer they will be overwrite if time stamp enabled */

44
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_epwm.c
View File

@ -244,22 +244,22 @@ void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask)
* - EPWM1 : EPWM Group 1
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
* - \ref EPWM_TRIGGER_ADC_EVEN_ZERO_POINT
* - \ref EPWM_TRIGGER_ADC_EVEN_PERIOD_POINT
* - \ref EPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT
* - \ref EPWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT
* - \ref EPWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT
* - \ref EPWM_TRIGGER_ADC_ODD_ZERO_POINT
* - \ref EPWM_TRIGGER_ADC_ODD_PERIOD_POINT
* - \ref EPWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT
* - \ref EPWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT
* - \ref EPWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT
* - \ref EPWM_TRIGGER_ADC_CH_0_FREE_CMP_UP_COUNT_POINT
* - \ref EPWM_TRIGGER_ADC_CH_0_FREE_CMP_DOWN_COUNT_POINT
* - \ref EPWM_TRIGGER_ADC_CH_2_FREE_CMP_UP_COUNT_POINT
* - \ref EPWM_TRIGGER_ADC_CH_2_FREE_CMP_DOWN_COUNT_POINT
* - \ref EPWM_TRIGGER_ADC_CH_4_FREE_CMP_UP_COUNT_POINT
* - \ref EPWM_TRIGGER_ADC_CH_4_FREE_CMP_DOWN_COUNT_POINT
* - \ref EPWM_TRG_ADC_EVEN_ZERO
* - \ref EPWM_TRG_ADC_EVEN_PERIOD
* - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD
* - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP
* - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN
* - \ref EPWM_TRG_ADC_ODD_ZERO
* - \ref EPWM_TRG_ADC_ODD_PERIOD
* - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD
* - \ref EPWM_TRG_ADC_ODD_COMPARE_UP
* - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN
* - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP
* - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN
* - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP
* - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN
* - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP
* - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN
* @return None
* @details This function is used to enable selected channel to trigger ADC.
*/
@ -329,10 +329,10 @@ uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
* - EPWM1 : EPWM Group 1
* @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5
* @param[in] u32Condition The condition to trigger DAC. Combination of following conditions:
* - \ref EPWM_TRIGGER_DAC_ZERO_POINT
* - \ref EPWM_TRIGGER_DAC_PERIOD_POINT
* - \ref EPWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT
* - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT
* - \ref EPWM_TRIGGER_DAC_ZERO
* - \ref EPWM_TRIGGER_DAC_PERIOD
* - \ref EPWM_TRIGGER_DAC_COMPARE_UP
* - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN
* @return None
* @details This function is used to enable selected channel to trigger DAC.
*/
@ -352,8 +352,8 @@ void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Con
*/
void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum)
{
(epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO_POINT | EPWM_TRIGGER_DAC_PERIOD_POINT | EPWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT | \
EPWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT) << u32ChannelNum);
(epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | \
EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum);
}
/**

44
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_epwm.h
View File

@ -63,27 +63,27 @@ extern "C"
/*---------------------------------------------------------------------------------------------------------*/
/* Trigger Source Select Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define EPWM_TRIGGER_ADC_EVEN_ZERO_POINT (0U) /*!< EPWM trigger ADC while counter of even channel matches zero point \hideinitializer */
#define EPWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1U) /*!< EPWM trigger ADC while counter of even channel matches period point \hideinitializer */
#define EPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2U) /*!< EPWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */
#define EPWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT (3U) /*!< EPWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */
#define EPWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT (4U) /*!< EPWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */
#define EPWM_TRIGGER_ADC_ODD_ZERO_POINT (5U) /*!< EPWM trigger ADC while counter of odd channel matches zero point \hideinitializer */
#define EPWM_TRIGGER_ADC_ODD_PERIOD_POINT (6U) /*!< EPWM trigger ADC while counter of odd channel matches period point \hideinitializer */
#define EPWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT (7U) /*!< EPWM trigger ADC while counter of odd channel matches zero or period point \hideinitializer */
#define EPWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT (8U) /*!< EPWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */
#define EPWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT (9U) /*!< EPWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */
#define EPWM_TRIGGER_ADC_CH_0_FREE_CMP_UP_COUNT_POINT (10U) /*!< EPWM trigger ADC while counter of channel 0 matches up count to free comparator point \hideinitializer */
#define EPWM_TRIGGER_ADC_CH_0_FREE_CMP_DOWN_COUNT_POINT (11U) /*!< EPWM trigger ADC while counter of channel 0 matches down count to free comparator point \hideinitializer */
#define EPWM_TRIGGER_ADC_CH_2_FREE_CMP_UP_COUNT_POINT (12U) /*!< EPWM trigger ADC while counter of channel 2 matches up count to free comparator point \hideinitializer */
#define EPWM_TRIGGER_ADC_CH_2_FREE_CMP_DOWN_COUNT_POINT (13U) /*!< EPWM trigger ADC while counter of channel 2 matches down count to free comparator point \hideinitializer */
#define EPWM_TRIGGER_ADC_CH_4_FREE_CMP_UP_COUNT_POINT (14U) /*!< EPWM trigger ADC while counter of channel 4 matches up count to free comparator point \hideinitializer */
#define EPWM_TRIGGER_ADC_CH_4_FREE_CMP_DOWN_COUNT_POINT (15U) /*!< EPWM trigger ADC while counter of channel 4 matches down count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_EVEN_ZERO (0U) /*!< EPWM trigger ADC while counter of even channel matches zero point \hideinitializer */
#define EPWM_TRG_ADC_EVEN_PERIOD (1U) /*!< EPWM trigger ADC while counter of even channel matches period point \hideinitializer */
#define EPWM_TRG_ADC_EVEN_ZERO_PERIOD (2U) /*!< EPWM trigger ADC while counter of even channel matches zero or period point \hideinitializer */
#define EPWM_TRG_ADC_EVEN_COMPARE_UP (3U) /*!< EPWM trigger ADC while counter of even channel matches up count to comparator point \hideinitializer */
#define EPWM_TRG_ADC_EVEN_COMPARE_DOWN (4U) /*!< EPWM trigger ADC while counter of even channel matches down count to comparator point \hideinitializer */
#define EPWM_TRG_ADC_ODD_ZERO (5U) /*!< EPWM trigger ADC while counter of odd channel matches zero point \hideinitializer */
#define EPWM_TRG_ADC_ODD_PERIOD (6U) /*!< EPWM trigger ADC while counter of odd channel matches period point \hideinitializer */
#define EPWM_TRG_ADC_ODD_ZERO_PERIOD (7U) /*!< EPWM trigger ADC while counter of odd channel matches zero or period point \hideinitializer */
#define EPWM_TRG_ADC_ODD_COMPARE_UP (8U) /*!< EPWM trigger ADC while counter of odd channel matches up count to comparator point \hideinitializer */
#define EPWM_TRG_ADC_ODD_COMPARE_DOWN (9U) /*!< EPWM trigger ADC while counter of odd channel matches down count to comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_0_FREE_CMP_UP (10U) /*!< EPWM trigger ADC while counter of channel 0 matches up count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN (11U) /*!< EPWM trigger ADC while counter of channel 0 matches down count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_2_FREE_CMP_UP (12U) /*!< EPWM trigger ADC while counter of channel 2 matches up count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN (13U) /*!< EPWM trigger ADC while counter of channel 2 matches down count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_4_FREE_CMP_UP (14U) /*!< EPWM trigger ADC while counter of channel 4 matches up count to free comparator point \hideinitializer */
#define EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN (15U) /*!< EPWM trigger ADC while counter of channel 4 matches down count to free comparator point \hideinitializer */
#define EPWM_TRIGGER_DAC_ZERO_POINT (0x1U) /*!< EPWM trigger ADC while counter down count to 0 \hideinitializer */
#define EPWM_TRIGGER_DAC_PERIOD_POINT (0x100U) /*!< EPWM trigger ADC while counter matches (PERIOD + 1) \hideinitializer */
#define EPWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT (0x10000U) /*!< EPWM trigger ADC while counter up count to CMPDAT \hideinitializer */
#define EPWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT (0x1000000U) /*!< EPWM trigger ADC while counter down count to CMPDAT \hideinitializer */
#define EPWM_TRIGGER_DAC_ZERO (0x1U) /*!< EPWM trigger ADC while counter down count to 0 \hideinitializer */
#define EPWM_TRIGGER_DAC_PERIOD (0x100U) /*!< EPWM trigger ADC while counter matches (PERIOD + 1) \hideinitializer */
#define EPWM_TRIGGER_DAC_COMPARE_UP (0x10000U) /*!< EPWM trigger ADC while counter up count to CMPDAT \hideinitializer */
#define EPWM_TRIGGER_DAC_COMPARE_DOWN (0x1000000U) /*!< EPWM trigger ADC while counter down count to CMPDAT \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Fail brake Control Constant Definitions */
@ -108,8 +108,8 @@ extern "C"
#define EPWM_FB_LEVEL_SYS_RAM (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */
#define EPWM_FB_LEVEL_SYS_COR (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */
#define EPWM_FB_EDGE (0U) /*!< edge-detect fault brake */
#define EPWM_FB_LEVEL (8U) /*!< level-detect fault brake */
#define EPWM_FB_EDGE (0U) /*!< edge-detect fault brake \hideinitializer */
#define EPWM_FB_LEVEL (8U) /*!< level-detect fault brake \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/
/* Leading Edge Blanking Control Constant Definitions */

268
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_hsotg.h Normal file
View File

@ -0,0 +1,268 @@
/**************************************************************************//**
* @file hsotg.h
* @version V0.10
* @brief M480 Series HSOTG Driver Header File
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __HSOTG_H__
#define __HSOTG_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M480_Device_Driver M480 Device Driver
@{
*/
/** @addtogroup M480_HSOTG_Driver HSOTG Driver
@{
*/
/** @addtogroup M480_HSOTG_EXPORTED_CONSTANTS HSOTG Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* HSOTG constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define HSOTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */
#define HSOTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */
#define HSOTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */
#define HSOTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */
/*@}*/ /* end of group M480_HSOTG_EXPORTED_CONSTANTS */
/** @addtogroup M480_HSOTG_EXPORTED_FUNCTIONS HSOTG Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Define Macros and functions */
/*---------------------------------------------------------------------------------------------------------*/
/**
* @brief This macro is used to enable HSOTG function
* @param None
* @return None
* @details This macro will set OTGEN bit of HSOTG_CTL register to enable HSOTG function.
* \hideinitializer
*/
#define HSOTG_ENABLE() (HSOTG->CTL |= HSOTG_CTL_OTGEN_Msk)
/**
* @brief This macro is used to disable HSOTG function
* @param None
* @return None
* @details This macro will clear OTGEN bit of HSOTG_CTL register to disable HSOTG function.
* \hideinitializer
*/
#define HSOTG_DISABLE() (HSOTG->CTL &= ~HSOTG_CTL_OTGEN_Msk)
/**
* @brief This macro is used to enable USB PHY
* @param None
* @return None
* @details When the USB role is selected as HSOTG device, use this macro to enable USB PHY.
* This macro will set OTGPHYEN bit of HSOTG_PHYCTL register to enable USB PHY.
* \hideinitializer
*/
#define HSOTG_ENABLE_PHY() (HSOTG->PHYCTL |= HSOTG_PHYCTL_OTGPHYEN_Msk)
/**
* @brief This macro is used to disable USB PHY
* @param None
* @return None
* @details This macro will clear OTGPHYEN bit of HSOTG_PHYCTL register to disable USB PHY.
* \hideinitializer
*/
#define HSOTG_DISABLE_PHY() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_OTGPHYEN_Msk)
/**
* @brief This macro is used to enable ID detection function
* @param None
* @return None
* @details This macro will set IDDETEN bit of HSOTG_PHYCTL register to enable ID detection function.
* \hideinitializer
*/
#define HSOTG_ENABLE_ID_DETECT() (HSOTG->PHYCTL |= HSOTG_PHYCTL_IDDETEN_Msk)
/**
* @brief This macro is used to disable ID detection function
* @param None
* @return None
* @details This macro will clear IDDETEN bit of HSOTG_PHYCTL register to disable ID detection function.
* \hideinitializer
*/
#define HSOTG_DISABLE_ID_DETECT() (HSOTG->PHYCTL &= ~HSOTG_PHYCTL_IDDETEN_Msk)
/**
* @brief This macro is used to enable HSOTG wake-up function
* @param None
* @return None
* @details This macro will set WKEN bit of HSOTG_CTL register to enable HSOTG wake-up function.
* \hideinitializer
*/
#define HSOTG_ENABLE_WAKEUP() (HSOTG->CTL |= HSOTG_CTL_WKEN_Msk)
/**
* @brief This macro is used to disable HSOTG wake-up function
* @param None
* @return None
* @details This macro will clear WKEN bit of HSOTG_CTL register to disable HSOTG wake-up function.
* \hideinitializer
*/
#define HSOTG_DISABLE_WAKEUP() (HSOTG->CTL &= ~HSOTG_CTL_WKEN_Msk)
/**
* @brief This macro is used to set the polarity of USB_VBUS_EN pin
* @param[in] u32Pol The polarity selection. Valid values are listed below.
* - \ref HSOTG_VBUS_EN_ACTIVE_HIGH
* - \ref HSOTG_VBUS_EN_ACTIVE_LOW
* @return None
* @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
* \hideinitializer
*/
#define HSOTG_SET_VBUS_EN_POL(u32Pol) (HSOTG->PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<HSOTG_PHYCTL_VBENPOL_Pos))
/**
* @brief This macro is used to set the polarity of USB_VBUS_ST pin
* @param[in] u32Pol The polarity selection. Valid values are listed below.
* - \ref HSOTG_VBUS_ST_VALID_HIGH
* - \ref HSOTG_VBUS_ST_VALID_LOW
* @return None
* @details This macro is used to set the polarity of external USB VBUS power switch status signal.
* \hideinitializer
*/
#define HSOTG_SET_VBUS_STS_POL(u32Pol) (HSOTG->PHYCTL = (HSOTG->PHYCTL & (~HSOTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<HSOTG_PHYCTL_VBSTSPOL_Pos))
/**
* @brief This macro is used to enable HSOTG related interrupts
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
* - \ref HSOTG_INTEN_ROLECHGIEN_Msk
* - \ref HSOTG_INTEN_VBEIEN_Msk
* - \ref HSOTG_INTEN_SRPFIEN_Msk
* - \ref HSOTG_INTEN_HNPFIEN_Msk
* - \ref HSOTG_INTEN_GOIDLEIEN_Msk
* - \ref HSOTG_INTEN_IDCHGIEN_Msk
* - \ref HSOTG_INTEN_PDEVIEN_Msk
* - \ref HSOTG_INTEN_HOSTIEN_Msk
* - \ref HSOTG_INTEN_BVLDCHGIEN_Msk
* - \ref HSOTG_INTEN_AVLDCHGIEN_Msk
* - \ref HSOTG_INTEN_VBCHGIEN_Msk
* - \ref HSOTG_INTEN_SECHGIEN_Msk
* - \ref HSOTG_INTEN_SRPDETIEN_Msk
* @return None
* @details This macro will enable HSOTG related interrupts specified by u32Mask parameter.
* \hideinitializer
*/
#define HSOTG_ENABLE_INT(u32Mask) (HSOTG->INTEN |= (u32Mask))
/**
* @brief This macro is used to disable HSOTG related interrupts
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
* - \ref HSOTG_INTEN_ROLECHGIEN_Msk
* - \ref HSOTG_INTEN_VBEIEN_Msk
* - \ref HSOTG_INTEN_SRPFIEN_Msk
* - \ref HSOTG_INTEN_HNPFIEN_Msk
* - \ref HSOTG_INTEN_GOIDLEIEN_Msk
* - \ref HSOTG_INTEN_IDCHGIEN_Msk
* - \ref HSOTG_INTEN_PDEVIEN_Msk
* - \ref HSOTG_INTEN_HOSTIEN_Msk
* - \ref HSOTG_INTEN_BVLDCHGIEN_Msk
* - \ref HSOTG_INTEN_AVLDCHGIEN_Msk
* - \ref HSOTG_INTEN_VBCHGIEN_Msk
* - \ref HSOTG_INTEN_SECHGIEN_Msk
* - \ref HSOTG_INTEN_SRPDETIEN_Msk
* @return None
* @details This macro will disable HSOTG related interrupts specified by u32Mask parameter.
* \hideinitializer
*/
#define HSOTG_DISABLE_INT(u32Mask) (HSOTG->INTEN &= ~(u32Mask))
/**
* @brief This macro is used to get HSOTG related interrupt flags
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
* - \ref HSOTG_INTSTS_ROLECHGIF_Msk
* - \ref HSOTG_INTSTS_VBEIF_Msk
* - \ref HSOTG_INTSTS_SRPFIF_Msk
* - \ref HSOTG_INTSTS_HNPFIF_Msk
* - \ref HSOTG_INTSTS_GOIDLEIF_Msk
* - \ref HSOTG_INTSTS_IDCHGIF_Msk
* - \ref HSOTG_INTSTS_PDEVIF_Msk
* - \ref HSOTG_INTSTS_HOSTIF_Msk
* - \ref HSOTG_INTSTS_BVLDCHGIF_Msk
* - \ref HSOTG_INTSTS_AVLDCHGIF_Msk
* - \ref HSOTG_INTSTS_VBCHGIF_Msk
* - \ref HSOTG_INTSTS_SECHGIF_Msk
* - \ref HSOTG_INTSTS_SRPDETIF_Msk
* @return Interrupt flags of selected sources.
* @details This macro will return HSOTG related interrupt flags specified by u32Mask parameter.
* \hideinitializer
*/
#define HSOTG_GET_INT_FLAG(u32Mask) (HSOTG->INTSTS & (u32Mask))
/**
* @brief This macro is used to clear HSOTG related interrupt flags
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
* - \ref HSOTG_INTSTS_ROLECHGIF_Msk
* - \ref HSOTG_INTSTS_VBEIF_Msk
* - \ref HSOTG_INTSTS_SRPFIF_Msk
* - \ref HSOTG_INTSTS_HNPFIF_Msk
* - \ref HSOTG_INTSTS_GOIDLEIF_Msk
* - \ref HSOTG_INTSTS_IDCHGIF_Msk
* - \ref HSOTG_INTSTS_PDEVIF_Msk
* - \ref HSOTG_INTSTS_HOSTIF_Msk
* - \ref HSOTG_INTSTS_BVLDCHGIF_Msk
* - \ref HSOTG_INTSTS_AVLDCHGIF_Msk
* - \ref HSOTG_INTSTS_VBCHGIF_Msk
* - \ref HSOTG_INTSTS_SECHGIF_Msk
* - \ref HSOTG_INTSTS_SRPDETIF_Msk
* @return None
* @details This macro will clear HSOTG related interrupt flags specified by u32Mask parameter.
* \hideinitializer
*/
#define HSOTG_CLR_INT_FLAG(u32Mask) (HSOTG->INTSTS = (u32Mask))
/**
* @brief This macro is used to get HSOTG related status
* @param[in] u32Mask The combination of user specified source. Valid values are listed below.
* - \ref HSOTG_STATUS_OVERCUR_Msk
* - \ref HSOTG_STATUS_IDSTS_Msk
* - \ref HSOTG_STATUS_SESSEND_Msk
* - \ref HSOTG_STATUS_BVLD_Msk
* - \ref HSOTG_STATUS_AVLD_Msk
* - \ref HSOTG_STATUS_VBUSVLD_Msk
* @return The user specified status.
* @details This macro will return HSOTG related status specified by u32Mask parameter.
* \hideinitializer
*/
#define HSOTG_GET_STATUS(u32Mask) (HSOTG->STATUS & (u32Mask))
/*@}*/ /* end of group M480_HSOTG_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M480_HSOTG_Driver */
/*@}*/ /* end of group M480_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __HSOTG_H__ */
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

6
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_hsusbd.c
View File

@ -388,10 +388,14 @@ void HSUSBD_StandardRequest(void)
break;
}
case SET_FEATURE: {
if ((gUsbCmd.wValue & 0x3ul) == 2ul) { /* TEST_MODE*/
if ((gUsbCmd.wValue & 0x3ul) == 2ul) { /* TEST_MODE */
g_hsusbd_EnableTestMode = (uint8_t)1ul;
g_hsusbd_TestSelector = (uint8_t)(gUsbCmd.wIndex >> 8);
}
if ((gUsbCmd.wValue & 0x3ul) == 3ul) { /* HNP ebable */
HSOTG->CTL |= (HSOTG_CTL_HNPREQEN_Msk | HSOTG_CTL_BUSREQ_Msk);
}
/* Status stage */
HSUSBD_CLR_CEP_INT_FLAG(HSUSBD_CEPINTSTS_STSDONEIF_Msk);
HSUSBD_SET_CEP_STATE(HSUSBD_CEPCTL_NAKCLR);

6
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_opa.h
View File

@ -25,7 +25,7 @@ extern "C"
/** @addtogroup OPA_EXPORTED_CONSTANTS OPA Exported Constants
@{
*/
#define OPA_CALIBRATION_CLK_1K (0UL) /*!< OPA calibration clock select 1 KHz \hideinitializer */
#define OPA_CALIBRATION_RV_1_2_AVDD (0UL) /*!< OPA calibration reference voltage select 1/2 AVDD \hideinitializer */
#define OPA_CALIBRATION_RV_H_L_VCM (1UL) /*!< OPA calibration reference voltage select from high vcm to low vcm \hideinitializer */
@ -136,7 +136,8 @@ __STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa, uint32_t u32OpaNum, uint32_t
* @brief This function is used to configure and start OPA calibration
* @param[in] opa The pointer of the specified OPA module
* @param[in] u32OpaNum The OPA number. 0 for OPA0; 1 for OPA1; 2 for OPA2.
* @param[in] u32ClockSel This parameter is not used
* @param[in] u32ClockSel Select OPA calibration clock
* - \ref OPA_CALIBRATION_CLK_1K
* @param[in] u32RefVol Select OPA reference voltage
* - \ref OPA_CALIBRATION_RV_1_2_AVDD
* - \ref OPA_CALIBRATION_RV_H_L_VCM
@ -153,6 +154,7 @@ __STATIC_INLINE int32_t OPA_Calibration(OPA_T *opa,
uint32_t u32CALResult;
int32_t i32Ret = 0L;
(opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALCLK0_Msk << (u32OpaNum << 1)));
(opa)->CALCTL = (((opa)->CALCTL) & ~(OPA_CALCTL_CALRVS0_Msk << (u32OpaNum))) | (((u32RefVol) << OPA_CALCTL_CALRVS0_Pos) << (u32OpaNum));
(opa)->CALCTL |= (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum));
while((opa)->CALCTL & (OPA_CALCTL_CALTRG0_Msk << (u32OpaNum))){}

268
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_otg.h Normal file
View File

@ -0,0 +1,268 @@
/**************************************************************************//**
* @file otg.h
* @version V0.10
* @brief M480 Series OTG Driver Header File
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#ifndef __OTG_H__
#define __OTG_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup M480_Device_Driver M480 Device Driver
@{
*/
/** @addtogroup M480_OTG_Driver OTG Driver
@{
*/
/** @addtogroup M480_OTG_EXPORTED_CONSTANTS OTG Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* OTG constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. \hideinitializer */
#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. \hideinitializer */
#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. \hideinitializer */
#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. \hideinitializer */
/*@}*/ /* end of group M480_OTG_EXPORTED_CONSTANTS */
/** @addtogroup M480_OTG_EXPORTED_FUNCTIONS OTG Exported Functions
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Define Macros and functions */
/*---------------------------------------------------------------------------------------------------------*/
/**
* @brief This macro is used to enable OTG function
* @param None
* @return None
* @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function.
* \hideinitializer
*/
#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
/**
* @brief This macro is used to disable OTG function
* @param None
* @return None
* @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function.
* \hideinitializer
*/
#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
/**
* @brief This macro is used to enable USB PHY
* @param None
* @return None
* @details When the USB role is selected as OTG device, use this macro to enable USB PHY.
* This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY.
* \hideinitializer
*/
#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
/**
* @brief This macro is used to disable USB PHY
* @param None
* @return None
* @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY.
* \hideinitializer
*/
#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
/**
* @brief This macro is used to enable ID detection function
* @param None
* @return None
* @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function.
* \hideinitializer
*/
#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
/**
* @brief This macro is used to disable ID detection function
* @param None
* @return None
* @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function.
* \hideinitializer
*/
#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
/**
* @brief This macro is used to enable OTG wake-up function
* @param None
* @return None
* @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function.
* \hideinitializer
*/
#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
/**
* @brief This macro is used to disable OTG wake-up function
* @param None
* @return None
* @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function.
* \hideinitializer
*/
#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
/**
* @brief This macro is used to set the polarity of USB_VBUS_EN pin
* @param[in] u32Pol The polarity selection. Valid values are listed below.
* - \ref OTG_VBUS_EN_ACTIVE_HIGH
* - \ref OTG_VBUS_EN_ACTIVE_LOW
* @return None
* @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
* \hideinitializer
*/
#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos))
/**
* @brief This macro is used to set the polarity of USB_VBUS_ST pin
* @param[in] u32Pol The polarity selection. Valid values are listed below.
* - \ref OTG_VBUS_ST_VALID_HIGH
* - \ref OTG_VBUS_ST_VALID_LOW
* @return None
* @details This macro is used to set the polarity of external USB VBUS power switch status signal.
* \hideinitializer
*/
#define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos))
/**
* @brief This macro is used to enable OTG related interrupts
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
* - \ref OTG_INTEN_ROLECHGIEN_Msk
* - \ref OTG_INTEN_VBEIEN_Msk
* - \ref OTG_INTEN_SRPFIEN_Msk
* - \ref OTG_INTEN_HNPFIEN_Msk
* - \ref OTG_INTEN_GOIDLEIEN_Msk
* - \ref OTG_INTEN_IDCHGIEN_Msk
* - \ref OTG_INTEN_PDEVIEN_Msk
* - \ref OTG_INTEN_HOSTIEN_Msk
* - \ref OTG_INTEN_BVLDCHGIEN_Msk
* - \ref OTG_INTEN_AVLDCHGIEN_Msk
* - \ref OTG_INTEN_VBCHGIEN_Msk
* - \ref OTG_INTEN_SECHGIEN_Msk
* - \ref OTG_INTEN_SRPDETIEN_Msk
* @return None
* @details This macro will enable OTG related interrupts specified by u32Mask parameter.
* \hideinitializer
*/
#define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask))
/**
* @brief This macro is used to disable OTG related interrupts
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
* - \ref OTG_INTEN_ROLECHGIEN_Msk
* - \ref OTG_INTEN_VBEIEN_Msk
* - \ref OTG_INTEN_SRPFIEN_Msk
* - \ref OTG_INTEN_HNPFIEN_Msk
* - \ref OTG_INTEN_GOIDLEIEN_Msk
* - \ref OTG_INTEN_IDCHGIEN_Msk
* - \ref OTG_INTEN_PDEVIEN_Msk
* - \ref OTG_INTEN_HOSTIEN_Msk
* - \ref OTG_INTEN_BVLDCHGIEN_Msk
* - \ref OTG_INTEN_AVLDCHGIEN_Msk
* - \ref OTG_INTEN_VBCHGIEN_Msk
* - \ref OTG_INTEN_SECHGIEN_Msk
* - \ref OTG_INTEN_SRPDETIEN_Msk
* @return None
* @details This macro will disable OTG related interrupts specified by u32Mask parameter.
* \hideinitializer
*/
#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask))
/**
* @brief This macro is used to get OTG related interrupt flags
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
* - \ref OTG_INTSTS_ROLECHGIF_Msk
* - \ref OTG_INTSTS_VBEIF_Msk
* - \ref OTG_INTSTS_SRPFIF_Msk
* - \ref OTG_INTSTS_HNPFIF_Msk
* - \ref OTG_INTSTS_GOIDLEIF_Msk
* - \ref OTG_INTSTS_IDCHGIF_Msk
* - \ref OTG_INTSTS_PDEVIF_Msk
* - \ref OTG_INTSTS_HOSTIF_Msk
* - \ref OTG_INTSTS_BVLDCHGIF_Msk
* - \ref OTG_INTSTS_AVLDCHGIF_Msk
* - \ref OTG_INTSTS_VBCHGIF_Msk
* - \ref OTG_INTSTS_SECHGIF_Msk
* - \ref OTG_INTSTS_SRPDETIF_Msk
* @return Interrupt flags of selected sources.
* @details This macro will return OTG related interrupt flags specified by u32Mask parameter.
* \hideinitializer
*/
#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask))
/**
* @brief This macro is used to clear OTG related interrupt flags
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
* - \ref OTG_INTSTS_ROLECHGIF_Msk
* - \ref OTG_INTSTS_VBEIF_Msk
* - \ref OTG_INTSTS_SRPFIF_Msk
* - \ref OTG_INTSTS_HNPFIF_Msk
* - \ref OTG_INTSTS_GOIDLEIF_Msk
* - \ref OTG_INTSTS_IDCHGIF_Msk
* - \ref OTG_INTSTS_PDEVIF_Msk
* - \ref OTG_INTSTS_HOSTIF_Msk
* - \ref OTG_INTSTS_BVLDCHGIF_Msk
* - \ref OTG_INTSTS_AVLDCHGIF_Msk
* - \ref OTG_INTSTS_VBCHGIF_Msk
* - \ref OTG_INTSTS_SECHGIF_Msk
* - \ref OTG_INTSTS_SRPDETIF_Msk
* @return None
* @details This macro will clear OTG related interrupt flags specified by u32Mask parameter.
* \hideinitializer
*/
#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask))
/**
* @brief This macro is used to get OTG related status
* @param[in] u32Mask The combination of user specified source. Valid values are listed below.
* - \ref OTG_STATUS_OVERCUR_Msk
* - \ref OTG_STATUS_IDSTS_Msk
* - \ref OTG_STATUS_SESSEND_Msk
* - \ref OTG_STATUS_BVLD_Msk
* - \ref OTG_STATUS_AVLD_Msk
* - \ref OTG_STATUS_VBUSVLD_Msk
* @return The user specified status.
* @details This macro will return OTG related status specified by u32Mask parameter.
* \hideinitializer
*/
#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask))
/*@}*/ /* end of group M480_OTG_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group M480_OTG_Driver */
/*@}*/ /* end of group M480_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif /*__OTG_H__ */
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

15
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_rtc.c
View File

@ -344,6 +344,7 @@ void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
}
/* Set Day of the Week */
RTC_WaitAccessEnable();
RTC->WEEKDAY = sPt->u32DayOfWeek;
/*-----------------------------------------------------------------------------------------------------*/
@ -368,6 +369,7 @@ void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt)
/*-----------------------------------------------------------------------------------------------------*/
RTC_WaitAccessEnable();
RTC->CAL = (uint32_t)u32RegCAL;
RTC_WaitAccessEnable();
RTC->TIME = (uint32_t)u32RegTIME;
}
}
@ -415,9 +417,6 @@ void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
}
/* Set Day of the Week */
RTC->WEEKDAY = sPt->u32DayOfWeek;
/*-----------------------------------------------------------------------------------------------------*/
/* Set RTC Alarm Date and Time */
/*-----------------------------------------------------------------------------------------------------*/
@ -437,6 +436,7 @@ void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt)
RTC_WaitAccessEnable();
RTC->CALM = (uint32_t)u32RegCALM;
RTC_WaitAccessEnable();
RTC->TALM = (uint32_t)u32RegTALM;
}
}
@ -466,12 +466,12 @@ void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t
u32RegCAL |= ((u32Day / 10ul) << 4);
u32RegCAL |= (u32Day % 10ul);
RTC_WaitAccessEnable();
/* Set Day of the Week */
RTC_WaitAccessEnable();
RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk;
/* Set RTC Calender Loading */
RTC_WaitAccessEnable();
RTC->CAL = (uint32_t)u32RegCAL;
}
@ -514,6 +514,7 @@ void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint3
RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk;
}
RTC_WaitAccessEnable();
RTC->TIME = (uint32_t)u32RegTIME;
}
@ -585,6 +586,7 @@ void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second,
}
/* Set RTC Alarm Time */
RTC_WaitAccessEnable();
RTC->TALM = (uint32_t)u32RegTALM;
}
@ -652,6 +654,7 @@ void RTC_SetTickPeriod(uint32_t u32TickSelection)
*/
void RTC_EnableInt(uint32_t u32IntFlagMask)
{
RTC_WaitAccessEnable();
RTC->INTEN |= u32IntFlagMask;
}
@ -674,7 +677,9 @@ void RTC_EnableInt(uint32_t u32IntFlagMask)
*/
void RTC_DisableInt(uint32_t u32IntFlagMask)
{
RTC_WaitAccessEnable();
RTC->INTEN &= ~u32IntFlagMask;
RTC_WaitAccessEnable();
RTC->INTSTS = u32IntFlagMask;
}

6
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_rtc.h
View File

@ -270,9 +270,9 @@ typedef struct {
*/
#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue))
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
static __INLINE void RTC_WaitAccessEnable(void);
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
static __INLINE void RTC_WaitAccessEnable(void);
/**
* @brief Wait RTC Access Enable
*

5
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sdh.c
View File

@ -37,7 +37,6 @@ uint32_t _SDH_uR3_CMD = 0ul;
uint32_t _SDH_uR7_CMD = 0ul;
uint8_t volatile _SDH_SDDataReady = FALSE;
uint8_t *_SDH_pSDHCBuffer;
uint32_t _SDH_ReferenceClock;
#if defined (__CC_ARM)
@ -547,8 +546,7 @@ uint32_t SDH_SelectCardType(SDH_T *sdh)
/* if SD card set 4bit */
if (pSD->CardType == SDH_TYPE_SD_HIGH) {
_SDH_pSDHCBuffer = (uint8_t *)((uint32_t)_SDH_ucSDHCBuffer);
sdh->DMASA = (uint32_t)_SDH_pSDHCBuffer;
sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer;
sdh->BLEN = 0x07ul; /* 64 bit */
if ((status = SDH_SDCmdAndRsp(sdh, 55ul, pSD->RCA, 0ul)) != Successful) {
@ -559,6 +557,7 @@ uint32_t SDH_SelectCardType(SDH_T *sdh)
}
if ((_SDH_ucSDHCBuffer[0] & 0xful) == 0x2ul) {
// if ((_SDH_ucSDHCBuffer[0] & 0xful) == 0xful) {
status = SDH_SwitchToHighSpeed(sdh, pSD);
if (status == Successful) {
/* divider */

17
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sdh.h
View File

@ -95,8 +95,8 @@ extern SDH_INFO_T SD0, SD1;
*
* @param[in] sdh Select SDH0 or SDH1.
* @param[in] u32IntMask Interrupt type mask:
* \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN0_Msk / \ref SDH_INTEN_CDIEN1_Msk /
* \ref SDH_INTEN_CDSRC0_Msk / \ref SDH_INTEN_CDSRC1_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
* \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /
* \ref SDH_INTEN_CDSRC_Msk \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
* \ref SDH_INTEN_WKIEN_Msk
*
* @return None.
@ -109,9 +109,8 @@ extern SDH_INFO_T SD0, SD1;
*
* @param[in] sdh Select SDH0 or SDH1.
* @param[in] u32IntMask Interrupt type mask:
* \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN0_Msk / \ref SDH_INTEN_CDIEN1_Msk /
* \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC0_Msk /
* \ref SDH_INTEN_CDSRC1_Msk
* \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /
* \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk /
*
* @return None.
* \hideinitializer
@ -125,8 +124,8 @@ extern SDH_INFO_T SD0, SD1;
* @param[in] u32IntMask Interrupt type mask:
* \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk /
* \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk /
* \ref SDH_INTSTS_CDIF0_Msk / \ref SDH_INTSTS_CDIF1_Msk / \ref SDH_INTSTS_RTOIF_Msk /
* \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS0_Msk / \ref SDH_INTSTS_CDSTS1_Msk /
* \ref SDH_INTSTS_CDIF_Msk \ref SDH_INTSTS_RTOIF_Msk /
* \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk /
* \ref SDH_INTSTS_DAT1STS_Msk
*
*
@ -142,8 +141,8 @@ extern SDH_INFO_T SD0, SD1;
*
* @param[in] sdh Select SDH0 or SDH1.
* @param[in] u32IntMask Interrupt type mask:
* \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF0_Msk /
* \ref SDH_INTSTS_CDIF1_Msk / \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk
* \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk /
* \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk
*
*
* @return None.

311
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_spim.c
View File

@ -53,6 +53,7 @@ static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx);
static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx);
static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
@ -79,15 +80,15 @@ static void SwitchNBitOutput(uint32_t u32NBit)
{
switch (u32NBit) {
case 1UL:
_SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */
SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */
break;
case 2UL:
_SPIM_ENABLE_DUAL_OUTPUT_MODE(); /* 2-bit, Output. */
SPIM_ENABLE_DUAL_OUTPUT_MODE(); /* 2-bit, Output. */
break;
case 4UL:
_SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 4-bit, Output. */
SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 4-bit, Output. */
break;
default:
@ -99,15 +100,15 @@ static void SwitchNBitInput(uint32_t u32NBit)
{
switch (u32NBit) {
case 1UL:
_SPIM_ENABLE_SING_INPUT_MODE(); /* 1-bit, Input. */
SPIM_ENABLE_SING_INPUT_MODE(); /* 1-bit, Input. */
break;
case 2UL:
_SPIM_ENABLE_DUAL_INPUT_MODE(); /* 2-bit, Input. */
SPIM_ENABLE_DUAL_INPUT_MODE(); /* 2-bit, Input. */
break;
case 4UL:
_SPIM_ENABLE_QUAD_INPUT_MODE(); /* 4-bit, Input. */
SPIM_ENABLE_QUAD_INPUT_MODE(); /* 4-bit, Input. */
break;
default:
@ -153,11 +154,11 @@ static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx)
}
if (dataNum) {
_SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
_SPIM_SET_DATA_WIDTH(32UL);
_SPIM_SET_DATA_NUM(dataNum);
_SPIM_SET_GO();
_SPIM_WAIT_FREE();
SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
SPIM_SET_DATA_WIDTH(32UL);
SPIM_SET_DATA_NUM(dataNum);
SPIM_SET_GO();
SPIM_WAIT_FREE();
}
if (u32NTx && (u32NTx < 4UL)) {
@ -169,11 +170,11 @@ static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx)
u32NTx = 0UL;
SPIM->TX[0] = tmp;
_SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
_SPIM_SET_DATA_WIDTH(rnm * 8UL);
_SPIM_SET_DATA_NUM(1UL);
_SPIM_SET_GO();
_SPIM_WAIT_FREE();
SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
SPIM_SET_DATA_WIDTH(rnm * 8UL);
SPIM_SET_DATA_NUM(1UL);
SPIM_SET_GO();
SPIM_WAIT_FREE();
}
}
}
@ -202,11 +203,11 @@ static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx)
}
if (dataNum) {
_SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
_SPIM_SET_DATA_WIDTH(32UL);
_SPIM_SET_DATA_NUM(dataNum);
_SPIM_SET_GO();
_SPIM_WAIT_FREE();
SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
SPIM_SET_DATA_WIDTH(32UL);
SPIM_SET_DATA_NUM(dataNum);
SPIM_SET_GO();
SPIM_WAIT_FREE();
}
while (dataNum) {
@ -222,11 +223,11 @@ static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx)
if (u32NRx && (u32NRx < 4UL)) {
uint32_t tmp;
_SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
_SPIM_SET_DATA_WIDTH(u32NRx * 8UL);
_SPIM_SET_DATA_NUM(1UL);
_SPIM_SET_GO();
_SPIM_WAIT_FREE();
SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch to Normal mode. */
SPIM_SET_DATA_WIDTH(u32NRx * 8UL);
SPIM_SET_DATA_NUM(1UL);
SPIM_SET_GO();
SPIM_WAIT_FREE();
tmp = SPIM->RX[0];
memcpy(&pu8RxBuf[buf_idx], &tmp, u32NRx);
@ -236,6 +237,25 @@ static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx)
}
}
/**
* @brief Issue Read Status Register #1 command.
* @param dataBuf Receive buffer.
* @param u32NRx Size of receive buffer.
* @param u32NBit N-bit transmit/receive.
* @return None.
*/
static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
{
uint8_t cmdBuf[] = {OPCODE_RDSR}; /* 1-byte Read Status Register #1 command. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
SwitchNBitInput(u32NBit);
spim_read(dataBuf, u32NRx);
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
/**
* @brief Issue Write Status Register #1 command.
* @param dataBuf Transmit buffer.
@ -248,50 +268,12 @@ static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_
uint8_t cmdBuf[] = {OPCODE_WRSR, 0x00U}; /* 1-byte Write Status Register #1 command + 1-byte data. */
cmdBuf[1] = dataBuf[0];
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
/**
* @brief Issue Read Status Register #1 command.
* @param dataBuf Receive buffer.
* @param u32NRx Size of receive buffer.
* @param u32NBit N-bit transmit/receive.
* @return None.
*/
static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
{
uint8_t cmdBuf[] = {OPCODE_RDSR}; /* 1-byte Read Status Register #1 command. */
_SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
SwitchNBitInput(u32NBit);
spim_read(dataBuf, u32NRx);
_SPIM_SET_SS_EN(0); /* CS deactivated. */
}
/**
* @brief Issue Write Status Register #2 command.
* @param dataBuf Transmit buffer.
* @param u32NTx Size of transmit buffer.
* @param u32NBit N-bit transmit/receive.
* @return None.
*/
static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
{
uint8_t cmdBuf[] = {OPCODE_WRSR2, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */
cmdBuf[1] = dataBuf[0];
_SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
}
#if 0 /* not used */
/**
* @brief Issue Read Status Register #2 command.
* @param dataBuf Receive buffer.
@ -303,14 +285,34 @@ static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_
{
uint8_t cmdBuf[] = {OPCODE_RDSR2}; /* 1-byte Read Status Register #1 command. */
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
SwitchNBitInput(u32NBit);
spim_read(dataBuf, sizeof (dataBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
/**
* @brief Issue Winbond Write Status Register command. This command write both Status Register-1
* and Status Register-2.
* @param dataBuf Transmit buffer.
* @param u32NTx Size of transmit buffer.
* @param u32NBit N-bit transmit/receive.
* @return None.
*/
static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
{
uint8_t cmdBuf[3] = {OPCODE_WRSR, 0U, 0U};
cmdBuf[1] = dataBuf[0];
cmdBuf[2] = dataBuf[1];
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
#endif
#if 0 /* not used */
/**
@ -325,10 +327,10 @@ static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32
uint8_t cmdBuf[] = {OPCODE_WRSR3, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */
cmdBuf[1] = dataBuf[0];
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
#endif
@ -343,12 +345,12 @@ static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_
{
uint8_t cmdBuf[] = {OPCODE_RDSR3}; /* 1-byte Read Status Register #1 command. */
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
SwitchNBitInput(u32NBit);
spim_read(dataBuf, sizeof (dataBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
#if 0 /* not used */
@ -364,10 +366,10 @@ static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint3
uint8_t cmdBuf[] = {OPCODE_WRSCUR, 0x00U}; /* 1-byte Write Status Register #2 command + 1-byte data. */
cmdBuf[1] = dataBuf[0];
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
#endif
@ -382,12 +384,12 @@ static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32
{
uint8_t cmdBuf[] = {OPCODE_RDSCUR}; /* 1-byte Read Status Register #1 command. */
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
SwitchNBitInput(u32NBit);
spim_read(dataBuf, sizeof (dataBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
/**
@ -408,16 +410,19 @@ static int spim_is_write_done(uint32_t u32NBit)
*/
static int spim_wait_write_done(uint32_t u32NBit)
{
int count, ret = -1;
uint32_t count;
int ret = -1;
for (count = 0; count < 0x1000000; count++) {
for (count = 0UL; count < SystemCoreClock/1000UL; count++) {
if (spim_is_write_done(u32NBit)) {
ret = 0;
break;
}
}
SPIM_DBGMSG("spim_wait_write_done time-out!!\n");
return ret;
if (ret != 0) {
SPIM_DBGMSG("spim_wait_write_done time-out!!\n");
}
return -1;
}
/**
@ -431,10 +436,10 @@ static void spim_set_write_enable(int isEn, uint32_t u32NBit)
uint8_t cmdBuf[] = {0U}; /* 1-byte Write Enable command. */
cmdBuf[0] = isEn ? OPCODE_WREN : OPCODE_WRDI;
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
/** @endcond HIDDEN_SYMBOLS */
@ -446,7 +451,7 @@ static void spim_set_write_enable(int isEn, uint32_t u32NBit)
*/
uint32_t SPIM_GetSClkFreq(void)
{
uint32_t clkDiv = _SPIM_GET_CLOCK_DIVIDER();
uint32_t clkDiv = SPIM_GET_CLOCK_DIVIDER();
return clkDiv ? SystemCoreClock / (clkDiv * 2U) : SystemCoreClock;
}
@ -464,38 +469,38 @@ int SPIM_InitFlash(int clrWP)
uint32_t i;
int32_t ret = -1;
_SPI_SET_SS_ACTLVL(0);
SPIM_SET_SS_ACTLVL(0);
/*
* Because not sure in SPI or QPI mode, do QPI reset and then SPI reset.
*/
/* QPI Reset Enable */
cmdBuf[0] = OPCODE_RSTEN;
_SPIM_SET_SS_EN(1); /* CS activated. */
_SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */
SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
/* QPI Reset */
cmdBuf[0] = OPCODE_RST;
_SPIM_SET_SS_EN(1); /* CS activated. */
_SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */
SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_ENABLE_QUAD_OUTPUT_MODE(); /* 1-bit, Output. */
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
/* SPI ResetEnable */
cmdBuf[0] = OPCODE_RSTEN;
_SPIM_SET_SS_EN(1); /* CS activated. */
_SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */
SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
/* SPI Reset */
cmdBuf[0] = OPCODE_RST;
_SPIM_SET_SS_EN(1); /* CS activated. */
_SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */
SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_ENABLE_SING_OUTPUT_MODE(); /* 1-bit, Output. */
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
if (clrWP) {
uint8_t dataBuf[] = {0x00U};
@ -531,12 +536,12 @@ void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit)
{
uint8_t cmdBuf[] = { OPCODE_RDID }; /* 1-byte JEDEC ID command. */
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
SwitchNBitInput(u32NBit);
spim_read(idBuf, u32NRx);
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
/** @cond HIDDEN_SYMBOLS */
@ -548,24 +553,24 @@ static void spim_enable_spansion_quad_mode(int isEn)
cmdBuf[0] = 0x5U; /* Read Status Register-1 */
_SPIM_SET_SS_EN(1);
SPIM_SET_SS_EN(1);
SwitchNBitOutput(1UL);
spim_write(cmdBuf, sizeof (cmdBuf));
SwitchNBitInput(1UL);
spim_read(dataBuf, sizeof (dataBuf));
_SPIM_SET_SS_EN(0);
SPIM_SET_SS_EN(0);
/* SPIM_DBGMSG("SR1 = 0x%x\n", dataBuf[0]); */
status1 = dataBuf[0];
cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */
_SPIM_SET_SS_EN(1);
SPIM_SET_SS_EN(1);
SwitchNBitOutput(1UL);
spim_write(cmdBuf, sizeof (cmdBuf));
SwitchNBitInput(1UL);
spim_read(dataBuf, sizeof (dataBuf));
_SPIM_SET_SS_EN(0);
SPIM_SET_SS_EN(0);
/* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */
spim_set_write_enable(1, 1UL);
@ -579,22 +584,22 @@ static void spim_enable_spansion_quad_mode(int isEn)
cmdBuf[2] = dataBuf[0] & ~0x2U; /* clear QUAD */
}
_SPIM_SET_SS_EN(1);
SPIM_SET_SS_EN(1);
SwitchNBitOutput(1UL);
spim_write(cmdBuf, 3UL);
_SPIM_SET_SS_EN(0);
SPIM_SET_SS_EN(0);
spim_set_write_enable(0, 1UL);
cmdBuf[0] = 0x35U; /* Read Configuration Register-1 */
_SPIM_SET_SS_EN(1);
SPIM_SET_SS_EN(1);
SwitchNBitOutput(1UL);
spim_write(cmdBuf, sizeof (cmdBuf));
SwitchNBitInput(1UL);
spim_read(dataBuf, sizeof (dataBuf));
_SPIM_SET_SS_EN(0);
SPIM_SET_SS_EN(0);
/* SPIM_DBGMSG("CR1 = 0x%x\n", dataBuf[0]); */
N_delay(10000);
@ -611,18 +616,30 @@ static void spim_enable_spansion_quad_mode(int isEn)
void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit)
{
uint8_t idBuf[3];
uint8_t dataBuf[1];
uint8_t dataBuf[2];
SPIM_ReadJedecId(idBuf, sizeof (idBuf), u32NBit);
/* SPIM_DBGMSG("Flash ID is 0x%x\n", idBuf[0]); */
SPIM_DBGMSG("SPIM_SetQuadEnable - Flash ID is 0x%x\n", idBuf[0]);
switch (idBuf[0]) {
case MFGID_WINBOND: /* Winbond SPI flash */
SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
if (isEn) {
dataBuf[1] |= SR2_QE;
} else {
dataBuf[1] &= ~SR2_QE;
}
spim_set_write_enable(1, u32NBit); /* Write Enable. */
dataBuf[0] = isEn ? SR2_QE : 0U;
SPIM_WriteStatusRegister2(dataBuf, sizeof (dataBuf), u32NBit);
spim_wait_write_done(u32NBit);
SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
SPIM_DBGMSG("Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
break;
case MFGID_MXIC: /* MXIC SPI flash. */
@ -659,17 +676,17 @@ static void spim_eon_set_qpi_mode(int isEn)
if (isEn) { /* Assume in SPI mode. */
cmdBuf[0] = OPCODE_ENQPI;
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(1UL);
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
} else { /* Assume in QPI mode. */
cmdBuf[0] = OPCODE_EXQPI;
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(4UL);
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
SPIM_ReadStatusRegister(status, sizeof (status), 1UL);
@ -683,12 +700,12 @@ static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit)
uint8_t dataBuf[1];
cmdBuf[0] = OPCODE_BRRD;
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, 1UL);
SwitchNBitInput(1UL);
spim_read(dataBuf, 1UL);
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_DBGMSG("Bank Address register= 0x%x\n", dataBuf[0]);
@ -700,10 +717,10 @@ static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit)
cmdBuf[1] = dataBuf[0] & ~0x80U; /* clear EXTADD */
}
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(1UL);
spim_write(cmdBuf, 2UL);
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
/** @cond HIDDEN_SYMBOLS */
@ -796,10 +813,10 @@ int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit)
if ((isSupt) && (idBuf[0] != MFGID_SPANSION)) {
cmdBuf[0] = isEn ? OPCODE_EN4B : OPCODE_EX4B;
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
/*
* FIXME: Per test, 4BYTE Indicator bit doesn't set after EN4B, which
@ -829,10 +846,10 @@ void SPIM_ChipErase(uint32_t u32NBit, int isSync)
spim_set_write_enable(1, u32NBit); /* Write Enable. */
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, sizeof (cmdBuf));
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
if (isSync) {
spim_wait_write_done(u32NBit);
@ -868,10 +885,10 @@ void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32
cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL);
}
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBit);
spim_write(cmdBuf, buf_idx);
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
if (isSync) {
spim_wait_write_done(u32NBit);
@ -902,7 +919,7 @@ static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t
spim_set_write_enable(1, u32NBitCmd); /* Write Enable. */
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
SwitchNBitOutput(u32NBitCmd);
cmdBuf[0] = wrCmd;
@ -926,7 +943,7 @@ static void SPIM_WriteInPageDataByIo(uint32_t u32Addr, int is4ByteAddr, uint32_t
SwitchNBitOutput(u32NBitDat);
spim_write(pu8TxBuf, u32NTx); /* Write out data. */
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
if (isSync) {
spim_wait_write_done(u32NBitCmd);
@ -954,17 +971,17 @@ static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr, int is4ByteAddr, u
spim_eon_set_qpi_mode(1); /* Enter QPI mode. */
}
_SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEWRITE);/* Switch to Page Write mode. */
_SPIM_SET_SPIM_MODE(wrCmd); /* SPIM mode. */
_SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */
SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEWRITE);/* Switch to Page Write mode. */
SPIM_SET_SPIM_MODE(wrCmd); /* SPIM mode. */
SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */
SPIM->SRAMADDR = (uint32_t) pu8TxBuf; /* SRAM u32Address. */
SPIM->DMACNT = u32NTx; /* Transfer length. */
SPIM->FADDR = u32Addr; /* Flash u32Address.*/
_SPIM_SET_GO(); /* Go. */
SPIM_SET_GO(); /* Go. */
if (isSync) {
_SPIM_WAIT_FREE();
SPIM_WAIT_FREE();
}
if (wrCmd == CMD_QUAD_PAGE_PROGRAM_EON) {
@ -1040,7 +1057,7 @@ void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu
uint8_t cmdBuf[16];
uint32_t buf_idx;
_SPIM_SET_SS_EN(1); /* CS activated. */
SPIM_SET_SS_EN(1); /* CS activated. */
cmdBuf[0] = rdCmd;
SwitchNBitOutput(u32NBitCmd);
@ -1071,7 +1088,7 @@ void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu
SwitchNBitInput(u32NBitDat);
spim_read(pu8RxBuf, u32NRx); /* Read back data. */
_SPIM_SET_SS_EN(0); /* CS deactivated. */
SPIM_SET_SS_EN(0); /* CS deactivated. */
}
/**
@ -1130,21 +1147,17 @@ void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t
void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[],
uint32_t u32RdCmd, int isSync)
{
if ((u32RdCmd == CMD_DMA_FAST_QUAD_READ) || (u32RdCmd == CMD_DMA_NORMAL_QUAD_READ)) {
SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */
}
_SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEREAD); /* Switch to Page Read mode. */
_SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */
_SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */
SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_PAGEREAD); /* Switch to Page Read mode. */
SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */
SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-Byte Address. */
SPIM->SRAMADDR = (uint32_t) pu8RxBuf; /* SRAM u32Address. */
SPIM->DMACNT = u32NRx; /* Transfer length. */
SPIM->FADDR = u32Addr; /* Flash u32Address.*/
_SPIM_SET_GO(); /* Go. */
SPIM_SET_GO(); /* Go. */
if (isSync) {
_SPIM_WAIT_FREE(); /* Wait for DMA done. */
SPIM_WAIT_FREE(); /* Wait for DMA done. */
}
}
@ -1157,14 +1170,10 @@ void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t p
*/
void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl)
{
if ((u32RdCmd == CMD_DMA_FAST_QUAD_READ) || (u32RdCmd == CMD_DMA_NORMAL_QUAD_READ)) {
SPIM_SetQuadEnable(1, 1UL); /* Set Quad Enable. */
}
_SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-byte u32Address. */
_SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */
_SPI_SET_IDL_INTVL(u32IdleIntvl); /* Idle interval. */
_SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_DIRECTMAP); /* Switch to Direct Map mode. */
SPIM_SET_4BYTE_ADDR_EN(is4ByteAddr); /* Enable/disable 4-byte u32Address. */
SPIM_SET_SPIM_MODE(u32RdCmd); /* SPIM mode. */
SPIM_SET_IDL_INTVL(u32IdleIntvl); /* Idle interval. */
SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_DIRECTMAP); /* Switch to Direct Map mode. */
}
/**
@ -1173,7 +1182,7 @@ void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32Idl
*/
void SPIM_ExitDirectMapMode(void)
{
_SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch back to Normal mode. */
SPIM_SET_OPMODE(SPIM_CTL0_OPMODE_IO); /* Switch back to Normal mode. */
}

138
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_spim.h
View File

@ -57,6 +57,8 @@ extern "C"
#define CMD_DMA_NORMAL_READ (0x03UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Read Data (Page Read Mode Use) \hideinitializer */
#define CMD_DMA_FAST_READ (0x0BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read (Page Read Mode Use) \hideinitializer */
#define CMD_DMA_NORMAL_DUAL_READ (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
#define CMD_DMA_FAST_READ_DUAL_OUTPUT (0x3BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
#define CMD_DMA_FAST_READ_QUAD_OUTPUT (0x6BUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
#define CMD_DMA_FAST_DUAL_READ (0xBBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Dual Output (Page Read Mode Use) \hideinitializer */
#define CMD_DMA_NORMAL_QUAD_READ (0xE7UL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */
#define CMD_DMA_FAST_QUAD_READ (0xEBUL << SPIM_CTL0_CMDCODE_Pos) /*!< SPIM_CTL0: Fast Read Quad I/O (Page Read Mode Use) \hideinitializer */
@ -81,8 +83,6 @@ E_MFGID;
#define OPCODE_WRSR2 0x31U /* Write status register #2 */
#define OPCODE_RDSR3 0x15U /* Read status register #3*/
#define OPCODE_WRSR3 0x11U /* Write status register #3 */
#define OPCODE_NORM_READ 0x03U /* Read data bytes (low frequency) */
#define OPCODE_FAST_READ 0x0bU /* Read data bytes (high frequency) */
#define OPCODE_PP 0x02U /* Page program (up to 256 bytes) */
#define OPCODE_SE_4K 0x20U /* Erase 4KB sector */
#define OPCODE_BE_32K 0x52U /* Erase 32KB block */
@ -92,6 +92,10 @@ E_MFGID;
#define OPCODE_RDID 0x9fU /* Read JEDEC ID */
#define OPCODE_BRRD 0x16U /* SPANSION flash - Bank Register Read command */
#define OPCODE_BRWR 0x17U /* SPANSION flash - Bank Register write command */
#define OPCODE_NORM_READ 0x03U /* Read data bytes */
#define OPCODE_FAST_READ 0x0bU /* Read data bytes */
#define OPCODE_FAST_DUAL_READ 0x3bU /* Read data bytes */
#define OPCODE_FAST_QUAD_READ 0x6bU /* Read data bytes */
/* Used for SST flashes only. */
#define OPCODE_BP 0x02U /* Byte program */
@ -112,14 +116,14 @@ E_MFGID;
#define OPCODE_EXQPI 0xFFU
/* Status Register bits. */
#define SR_WIP 1U /* Write in progress */
#define SR_WEL 2U /* Write enable latch */
#define SR_WIP 0x1U /* Write in progress */
#define SR_WEL 0x2U /* Write enable latch */
#define SR_QE 0x40U /* Quad Enable for MXIC */
/* Status Register #2 bits. */
#define SR2_QE 2U /* Quad Enable for Winbond */
#define SR2_QE 0x2U /* Quad Enable for Winbond */
/* meaning of other SR_* bits may differ between vendors */
#define SR_BP0 4U /* Block protect 0 */
#define SR_BP1 8U /* Block protect 1 */
#define SR_BP0 0x4U /* Block protect 0 */
#define SR_BP1 0x8U /* Block protect 1 */
#define SR_BP2 0x10U /* Block protect 2 */
#define SR_SRWD 0x80U /* SR write protect */
#define SR3_ADR 0x01U /* 4-byte u32Address mode */
@ -144,31 +148,31 @@ E_MFGID;
* @details Enable cipher.
* \hideinitializer
*/
#define _SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk)
#define SPIM_ENABLE_CIPHER() (SPIM->CTL0 &= ~SPIM_CTL0_CIPHOFF_Msk)
/**
* @details Disable cipher.
* \hideinitializer
*/
#define _SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk)
#define SPIM_DISABLE_CIPHER() (SPIM->CTL0 |= SPIM_CTL0_CIPHOFF_Msk)
/**
* @details Enable cipher balance
* \hideinitializer
*/
#define _SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk)
#define SPIM_ENABLE_BALEN() (SPIM->CTL0 |= SPIM_CTL0_BALEN_Msk)
/**
* @details Disable cipher balance
* \hideinitializer
*/
#define _SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk)
#define SPIM_DISABLE_BALEN() (SPIM->CTL0 &= ~SPIM_CTL0_BALEN_Msk)
/**
* @details Set 4-byte address to be enabled/disabled.
* \hideinitializer
*/
#define _SPIM_SET_4BYTE_ADDR_EN(x) \
#define SPIM_SET_4BYTE_ADDR_EN(x) \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_B4ADDREN_Msk)) | (((x) ? 1UL : 0UL) << SPIM_CTL0_B4ADDREN_Pos); \
} while (0)
@ -177,25 +181,25 @@ E_MFGID;
* @details Enable SPIM interrupt
* \hideinitializer
*/
#define _SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk)
#define SPIM_ENABLE_INT() (SPIM->CTL0 |= SPIM_CTL0_IEN_Msk)
/**
* @details Disable SPIM interrupt
* \hideinitializer
*/
#define _SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk)
#define SPIM_DISABLE_INT() (SPIM->CTL0 &= ~SPIM_CTL0_IEN_Msk)
/**
* @details Is interrupt flag on.
* \hideinitializer
*/
#define _SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL)
#define SPIM_IS_IF_ON() ((SPIM->CTL0 & SPIM_CTL0_IF_Msk) != 0UL)
/**
* @details Clear interrupt flag.
* \hideinitializer
*/
#define _SPIM_CLR_INT() \
#define SPIM_CLR_INT() \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_IF_Msk)) | (1UL << SPIM_CTL0_IF_Pos); \
} while (0)
@ -204,7 +208,7 @@ E_MFGID;
* @details Set transmit/receive bit length
* \hideinitializer
*/
#define _SPIM_SET_DATA_WIDTH(x) \
#define SPIM_SET_DATA_WIDTH(x) \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_DWIDTH_Msk)) | (((x) - 1U) << SPIM_CTL0_DWIDTH_Pos); \
} while (0)
@ -213,14 +217,14 @@ E_MFGID;
* @details Get data transmit/receive bit length setting
* \hideinitializer
*/
#define _SPIM_GET_DATA_WIDTH() \
#define SPIM_GET_DATA_WIDTH() \
(((SPIM->CTL0 & SPIM_CTL0_DWIDTH_Msk) >> SPIM_CTL0_DWIDTH_Pos)+1U)
/**
* @details Set data transmit/receive burst number
* \hideinitializer
*/
#define _SPIM_SET_DATA_NUM(x) \
#define SPIM_SET_DATA_NUM(x) \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_BURSTNUM_Msk)) | (((x) - 1U) << SPIM_CTL0_BURSTNUM_Pos); \
} while (0)
@ -229,14 +233,14 @@ E_MFGID;
* @details Get data transmit/receive burst number
* \hideinitializer
*/
#define _SPIM_GET_DATA_NUM() \
#define SPIM_GET_DATA_NUM() \
(((SPIM->CTL0 & SPIM_CTL0_BURSTNUM_Msk) >> SPIM_CTL0_BURSTNUM_Pos)+1U)
/**
* @details Enable Single Input mode.
* \hideinitializer
*/
#define _SPIM_ENABLE_SING_INPUT_MODE() \
#define SPIM_ENABLE_SING_INPUT_MODE() \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(1)); \
} while (0)
@ -245,7 +249,7 @@ E_MFGID;
* @details Enable Single Output mode.
* \hideinitializer
*/
#define _SPIM_ENABLE_SING_OUTPUT_MODE() \
#define SPIM_ENABLE_SING_OUTPUT_MODE() \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_SING | SPIM_CTL0_RW_IN(0)); \
} while (0)
@ -254,7 +258,7 @@ E_MFGID;
* @details Enable Dual Input mode.
* \hideinitializer
*/
#define _SPIM_ENABLE_DUAL_INPUT_MODE() \
#define SPIM_ENABLE_DUAL_INPUT_MODE() \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(1U)); \
} while (0)
@ -263,7 +267,7 @@ E_MFGID;
* @details Enable Dual Output mode.
* \hideinitializer
*/
#define _SPIM_ENABLE_DUAL_OUTPUT_MODE() \
#define SPIM_ENABLE_DUAL_OUTPUT_MODE() \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_DUAL | SPIM_CTL0_RW_IN(0U)); \
} while (0)
@ -272,7 +276,7 @@ E_MFGID;
* @details Enable Quad Input mode.
* \hideinitializer
*/
#define _SPIM_ENABLE_QUAD_INPUT_MODE() \
#define SPIM_ENABLE_QUAD_INPUT_MODE() \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(1U)); \
} while (0)
@ -281,7 +285,7 @@ E_MFGID;
* @details Enable Quad Output mode.
* \hideinitializer
*/
#define _SPIM_ENABLE_QUAD_OUTPUT_MODE() \
#define SPIM_ENABLE_QUAD_OUTPUT_MODE() \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~(SPIM_CTL0_BITMODE_Msk | SPIM_CTL0_QDIODIR_Msk))) | (SPIM_CTL0_BITMODE_QUAD | SPIM_CTL0_RW_IN(0U)); \
} while (0)
@ -290,7 +294,7 @@ E_MFGID;
* @details Set suspend interval which ranges between 0 and 15.
* \hideinitializer
*/
#define _SPIM_SET_SUSP_INTVL(x) \
#define SPIM_SET_SUSP_INTVL(x) \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_SUSPITV_Msk)) | ((x) << SPIM_CTL0_SUSPITV_Pos); \
} while (0)
@ -299,14 +303,14 @@ E_MFGID;
* @details Get suspend interval setting
* \hideinitializer
*/
#define _SPIM_GET_SUSP_INTVL() \
#define SPIM_GET_SUSP_INTVL() \
((SPIM->CTL0 & SPIM_CTL0_SUSPITV_Msk) >> SPIM_CTL0_SUSPITV_Pos)
/**
* @details Set operation mode.
* \hideinitializer
*/
#define _SPIM_SET_OPMODE(x) \
#define SPIM_SET_OPMODE(x) \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_OPMODE_Msk)) | (x); \
} while (0)
@ -315,13 +319,13 @@ E_MFGID;
* @details Get operation mode.
* \hideinitializer
*/
#define _SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk)
#define SPIM_GET_OP_MODE() (SPIM->CTL0 & SPIM_CTL0_OPMODE_Msk)
/**
* @details Set SPIM mode.
* \hideinitializer
*/
#define _SPIM_SET_SPIM_MODE(x) \
#define SPIM_SET_SPIM_MODE(x) \
do { \
SPIM->CTL0 = (SPIM->CTL0 & (~SPIM_CTL0_CMDCODE_Msk)) | (x); \
} while (0)
@ -330,25 +334,25 @@ E_MFGID;
* @details Get SPIM mode.
* \hideinitializer
*/
#define _SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk)
#define SPIM_GET_SPIM_MODE() (SPIM->CTL0 & SPIM_CTL0_CMDCODE_Msk)
/**
* @details Start operation.
* \hideinitializer
*/
#define _SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk)
#define SPIM_SET_GO() (SPIM->CTL1 |= SPIM_CTL1_SPIMEN_Msk)
/**
* @details Is engine busy.
* \hideinitializer
*/
#define _SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk)
#define SPIM_IS_BUSY() (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk)
/**
* @details Wait for free.
* \hideinitializer
*/
#define _SPIM_WAIT_FREE() \
#define SPIM_WAIT_FREE() \
do { \
while (SPIM->CTL1 & SPIM_CTL1_SPIMEN_Msk) { } \
} while (0)
@ -357,49 +361,49 @@ E_MFGID;
* @details Enable cache.
* \hideinitializer
*/
#define _SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk)
#define SPIM_ENABLE_CACHE() (SPIM->CTL1 &= ~SPIM_CTL1_CACHEOFF_Msk)
/**
* @details Disable cache.
* \hideinitializer
*/
#define _SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk)
#define SPIM_DISABLE_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CACHEOFF_Msk)
/**
* @details Is cache enabled.
* \hideinitializer
*/
#define _SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1)
#define SPIM_IS_CACHE_EN() ((SPIM->CTL1 & SPIM_CTL1_CACHEOFF_Msk) ? 0 : 1)
/**
* @details Enable CCM
* \hideinitializer
*/
#define _SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk)
#define SPIM_ENABLE_CCM() (SPIM->CTL1 |= SPIM_CTL1_CCMEN_Msk)
/**
* @details Disable CCM.
* \hideinitializer
*/
#define _SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk)
#define SPIM_DISABLE_CCM() (SPIM->CTL1 &= ~SPIM_CTL1_CCMEN_Msk)
/**
* @details Is CCM enabled.
* \hideinitializer
*/
#define _SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos)
#define SPIM_IS_CCM_EN() ((SPIM->CTL1 & SPIM_CTL1_CCMEN_Msk) >> SPIM_CTL1_CCMEN_Pos)
/**
* @details Invalidate cache.
* \hideinitializer
*/
#define _SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk)
#define SPIM_INVALID_CACHE() (SPIM->CTL1 |= SPIM_CTL1_CDINVAL_Msk)
/**
* @details Set SS(Select Active) to active level.
* \hideinitializer
*/
#define _SPIM_SET_SS_EN(x) \
#define SPIM_SET_SS_EN(x) \
do { \
(SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SS_Msk)) | ((! (x) ? 1UL : 0UL) << SPIM_CTL1_SS_Pos)); \
} while (0)
@ -408,14 +412,14 @@ E_MFGID;
* @details Is SS(Select Active) in active level.
* \hideinitializer
*/
#define _SPI_GET_SS_EN() \
#define SPIM_GET_SS_EN() \
(!(SPIM->CTL1 & SPIM_CTL1_SS_Msk))
/**
* @details Set active level of slave select to be high/low.
* \hideinitializer
*/
#define _SPI_SET_SS_ACTLVL(x) \
#define SPIM_SET_SS_ACTLVL(x) \
do { \
(SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_SSACTPOL_Msk)) | ((!! (x) ? 1UL : 0UL) << SPIM_CTL1_SSACTPOL_Pos)); \
} while (0)
@ -424,7 +428,7 @@ E_MFGID;
* @details Set idle time interval
* \hideinitializer
*/
#define _SPI_SET_IDL_INTVL(x) \
#define SPIM_SET_IDL_INTVL(x) \
do { \
SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_IDLETIME_Msk)) | ((x) << SPIM_CTL1_IDLETIME_Pos); \
} while (0)
@ -433,14 +437,14 @@ E_MFGID;
* @details Get idle time interval setting
* \hideinitializer
*/
#define _SPI_GET_IDL_INTVL() \
#define SPIM_GET_IDL_INTVL() \
((SPIM->CTL1 & SPIM_CTL1_IDLETIME_Msk) >> SPIM_CTL1_IDLETIME_Pos)
/**
* @details Set SPIM clock divider
* \hideinitializer
*/
#define _SPIM_SET_CLOCK_DIVIDER(x) \
#define SPIM_SET_CLOCK_DIVIDER(x) \
do { \
SPIM->CTL1 = (SPIM->CTL1 & (~SPIM_CTL1_DIVIDER_Msk)) | ((x) << SPIM_CTL1_DIVIDER_Pos); \
} while (0)
@ -449,14 +453,14 @@ E_MFGID;
* @details Get SPIM current clock divider setting
* \hideinitializer
*/
#define _SPIM_GET_CLOCK_DIVIDER() \
#define SPIM_GET_CLOCK_DIVIDER() \
((SPIM->CTL1 & SPIM_CTL1_DIVIDER_Msk) >> SPIM_CTL1_DIVIDER_Pos)
/**
* @details Set SPI flash deselect time interval of DMA write mode
* \hideinitializer
*/
#define _SPIM_SET_RXCLKDLY_DWDELSEL(x) \
#define SPIM_SET_RXCLKDLY_DWDELSEL(x) \
do { \
(SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_DWDELSEL_Msk)) | ((x) << SPIM_RXCLKDLY_DWDELSEL_Pos)); \
} while (0)
@ -465,14 +469,14 @@ E_MFGID;
* @details Get SPI flash deselect time interval of DMA write mode
* \hideinitializer
*/
#define _SPIM_GET_RXCLKDLY_DWDELSEL() \
#define SPIM_GET_RXCLKDLY_DWDELSEL() \
((SPIM->RXCLKDLY & SPIM_RXCLKDLY_DWDELSEL_Msk) >> SPIM_RXCLKDLY_DWDELSEL_Pos)
/**
* @details Set sampling clock delay selection for received data
* \hideinitializer
*/
#define _SPIM_SET_RXCLKDLY_RDDLYSEL(x) \
#define SPIM_SET_RXCLKDLY_RDDLYSEL(x) \
do { \
(SPIM->RXCLKDLY = (SPIM->RXCLKDLY & (~SPIM_RXCLKDLY_RDDLYSEL_Msk)) | ((x) << SPIM_RXCLKDLY_RDDLYSEL_Pos)); \
} while (0)
@ -481,28 +485,28 @@ E_MFGID;
* @details Get sampling clock delay selection for received data
* \hideinitializer
*/
#define _SPIM_GET_RXCLKDLY_RDDLYSEL() \
#define SPIM_GET_RXCLKDLY_RDDLYSEL() \
((SPIM->RXCLKDLY & SPIM_RXCLKDLY_RDDLYSEL_Msk) >> SPIM_RXCLKDLY_RDDLYSEL_Pos)
/**
* @details Set sampling clock edge selection for received data
* \hideinitializer
*/
#define _SPIM_SET_RXCLKDLY_RDEDGE() \
#define SPIM_SET_RXCLKDLY_RDEDGE() \
(SPIM->RXCLKDLY |= SPIM_RXCLKDLY_RDEDGE_Msk); \
/**
* @details Get sampling clock edge selection for received data
* \hideinitializer
*/
#define _SPIM_CLR_RXCLKDLY_RDEDGE() \
#define SPIM_CLR_RXCLKDLY_RDEDGE() \
(SPIM->RXCLKDLY &= ~SPIM_RXCLKDLY_RDEDGE_Msk)
/**
* @details Set mode bits data for continuous read mode
* \hideinitializer
*/
#define _SPIM_SET_DMMCTL_CRMDAT(x) \
#define SPIM_SET_DMMCTL_CRMDAT(x) \
do { \
(SPIM->DMMCTL = (SPIM->DMMCTL & (~SPIM_DMMCTL_CRMDAT_Msk)) | ((x) << SPIM_DMMCTL_CRMDAT_Pos)) | SPIM_DMMCTL_CREN_Msk; \
} while (0)
@ -511,14 +515,14 @@ E_MFGID;
* @details Get mode bits data for continuous read mode
* \hideinitializer
*/
#define _SPIM_GET_DMMCTL_CRMDAT() \
#define SPIM_GET_DMMCTL_CRMDAT() \
((SPIM->DMMCTL & SPIM_DMMCTL_CRMDAT_Msk) >> SPIM_DMMCTL_CRMDAT_Pos)
/**
* @details Set DMM mode SPI flash deselect time
* \hideinitializer
*/
#define _SPIM_DMM_SET_DESELTIM(x) \
#define SPIM_DMM_SET_DESELTIM(x) \
do { \
SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_DESELTIM_Msk) | (((x) & 0x1FUL) << SPIM_DMMCTL_DESELTIM_Pos); \
} while (0)
@ -527,38 +531,38 @@ E_MFGID;
* @details Get current DMM mode SPI flash deselect time setting
* \hideinitializer
*/
#define _SPIM_DMM_GET_DESELTIM() \
#define SPIM_DMM_GET_DESELTIM() \
((SPIM->DMMCTL & SPIM_DMMCTL_DESELTIM_Msk) >> SPIM_DMMCTL_DESELTIM_Pos)
/**
* @details Enable DMM mode burst wrap mode
* \hideinitializer
*/
#define _SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk)
#define SPIM_DMM_ENABLE_BWEN() (SPIM->DMMCTL |= SPIM_DMMCTL_BWEN_Msk)
/**
* @details Disable DMM mode burst wrap mode
* \hideinitializer
*/
#define _SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk)
#define SPIM_DMM_DISABLE_BWEN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_BWEN_Msk)
/**
* @details Enable DMM mode continuous read mode
* \hideinitializer
*/
#define _SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk)
#define SPIM_DMM_ENABLE_CREN() (SPIM->DMMCTL |= SPIM_DMMCTL_CREN_Msk)
/**
* @details Disable DMM mode continuous read mode
* \hideinitializer
*/
#define _SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk)
#define SPIM_DMM_DISABLE_CREN() (SPIM->DMMCTL &= ~SPIM_DMMCTL_CREN_Msk)
/**
* @details Set DMM mode SPI flash active SCLK time
* \hideinitializer
*/
#define _SPIM_DMM_SET_ACTSCLKT(x) \
#define SPIM_DMM_SET_ACTSCLKT(x) \
do { \
SPIM->DMMCTL = (SPIM->DMMCTL & ~SPIM_DMMCTL_ACTSCLKT_Msk) | (((x) & 0xFUL) << SPIM_DMMCTL_ACTSCLKT_Pos) | SPIM_DMMCTL_UACTSCLK_Msk; \
} while (0)
@ -567,13 +571,13 @@ E_MFGID;
* @details Set SPI flash active SCLK time as SPIM default
* \hideinitializer
*/
#define _SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk)
#define SPIM_DMM_SET_DEFAULT_ACTSCLK() (SPIM->DMMCTL &= ~SPIM_DMMCTL_UACTSCLK_Msk)
/**
* @details Set dummy cycle number (Only for DMM mode and DMA mode)
* \hideinitializer
*/
#define _SPIM_SET_DCNUM(x) \
#define SPIM_SET_DCNUM(x) \
do { \
SPIM->CTL2 = (SPIM->CTL2 & ~SPIM_CTL2_DCNUM_Msk) | (((x) & 0x1FUL) << SPIM_CTL2_DCNUM_Pos) | SPIM_CTL2_USETEN_Msk; \
} while (0)
@ -582,7 +586,7 @@ E_MFGID;
* @details Set dummy cycle number (Only for DMM mode and DMA mode) as SPIM default
* \hideinitializer
*/
#define _SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk)
#define SPIM_SET_DEFAULT_DCNUM(x) (SPIM->CTL2 &= ~SPIM_CTL2_USETEN_Msk)

2
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sys.h
View File

@ -280,7 +280,7 @@ Example 1: If user want to set PA.0 as SC0_CLK in initial function,
#define SYS_GPA_MFPH_PA11MFP_I2C2_SCL (0x07UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< I2C2 clock pin. \hideinitializer */
#define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 (0x09UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< BPWM0 channel0 output/capture input. \hideinitializer */
#define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT (0x0AUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< EPWM0 counter synchronous trigger output pin. \hideinitializer */
#define SYS_GPA_MFPH_PA11MFP_TM0_EXT (0x0DUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Timer0 event counter input / toggle output */
#define SYS_GPA_MFPH_PA11MFP_TM0_EXT (0x0DUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< Timer0 event counter input / toggle output \hideinitializer */
#define SYS_GPA_MFPH_PA11MFP_DAC1_ST (0x0EUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< DAC1 external trigger input. \hideinitializer */
#define SYS_GPA_MFPH_PA12MFP_GPIO (0x00UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< General purpose digital I/O pin. \hideinitializer */
#define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK (0x02UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< I2S0 bit clock pin. \hideinitializer */

4
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usbd.h
View File

@ -46,8 +46,8 @@ extern const S_USBD_INFO_T gsInfo;
/** @addtogroup M480_USBD_EXPORTED_CONSTANTS USBD Exported Constants
@{
*/
#define USBD_BUF_BASE (USBD_BASE+0x100ul) /*!< USBD buffer base address */
#define USBD_MAX_EP 12ul /*!< Total EP number */
#define USBD_BUF_BASE (USBD_BASE+0x100ul) /*!< USBD buffer base address \hideinitializer */
#define USBD_MAX_EP 12ul /*!< Total EP number \hideinitializer */
#define EP0 0ul /*!< Endpoint 0 \hideinitializer */
#define EP1 1ul /*!< Endpoint 1 \hideinitializer */

14
targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_usci_spi.c
View File

@ -350,7 +350,7 @@ uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)
/* Check slave selection signal active interrupt flag */
u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSACTIF_Msk;
if(((u32Mask & USPI_SSACT_INT_MASK)==USPI_PROTSTS_SSACTIF_Msk) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk)) {
if(((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk)) {
u32IntFlag |= USPI_SSACT_INT_MASK;
} else {}
@ -367,13 +367,13 @@ uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)
} else {}
/* Check TX under run interrupt flag */
u32TmpFlag = uspi->PROTSTS & USPI_BUFSTS_TXUDRIF_Msk;
u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk;
if(((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_TXUDRIF_Msk)) {
u32IntFlag |= USPI_TXUDR_INT_MASK;
} else {}
/* Check RX overrun interrupt flag */
u32TmpFlag = uspi->PROTSTS & USPI_BUFSTS_RXOVIF_Msk;
u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXOVIF_Msk;
if(((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_RXOVIF_Msk)) {
u32IntFlag |= USPI_RXOV_INT_MASK;
} else {}
@ -493,25 +493,25 @@ uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask)
} else {}
/* Check RX empty flag */
u32TmpFlag = uspi->PROTSTS & USPI_BUFSTS_RXEMPTY_Msk;
u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk;
if(((u32Mask & USPI_RX_EMPTY_MASK)==USPI_RX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_RXEMPTY_Msk)) {
u32Flag |= USPI_RX_EMPTY_MASK;
} else {}
/* Check RX full flag */
u32TmpFlag = uspi->PROTSTS & USPI_BUFSTS_RXFULL_Msk;
u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXFULL_Msk;
if(((u32Mask & USPI_RX_FULL_MASK)==USPI_RX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_RXFULL_Msk)) {
u32Flag |= USPI_RX_FULL_MASK;
} else {}
/* Check TX empty flag */
u32TmpFlag = uspi->PROTSTS & USPI_BUFSTS_TXEMPTY_Msk;
u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk;
if(((u32Mask & USPI_TX_EMPTY_MASK)==USPI_TX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_TXEMPTY_Msk)) {
u32Flag |= USPI_TX_EMPTY_MASK;
} else {}
/* Check TX full flag */
u32TmpFlag = uspi->PROTSTS & USPI_BUFSTS_TXFULL_Msk;
u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXFULL_Msk;
if(((u32Mask & USPI_TX_FULL_MASK)==USPI_TX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_TXFULL_Msk)) {
u32Flag |= USPI_TX_FULL_MASK;
} else {}

6
targets/TARGET_NUVOTON/TARGET_M480/device/system_M480.c
View File

@ -85,8 +85,8 @@ void SystemInit (void)
// NOTE: SPIM must keep enabled to run CCM mode.
CLK_EnableModuleClock(SPIM_MODULE);
SYS_ResetModule(SPIM_RST);
_SPIM_DISABLE_CACHE();
_SPIM_ENABLE_CCM();
while (! _SPIM_IS_CCM_EN());
SPIM_DISABLE_CACHE();
SPIM_ENABLE_CCM();
while (! SPIM_IS_CCM_EN());
}
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/