diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct index e379c37b1c..8af0ae892e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct @@ -8,45 +8,17 @@ ** ** Compiler: Keil ARM C/C++ Compiler ** Reference manual: IMXRT1050RM Rev.1, 03/2018 -** Version: rev. 0.1, 2017-01-10 -** Build: b180606 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** -** The Clear BSD License ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2018 NXP ** All rights reserved. ** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted (subject to the limitations in the -** disclaimer below) provided that the following conditions are met: -** -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** -** * Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from -** this software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -146,8 +118,8 @@ LR_IROM1 m_flash_config_start m_text_start+m_text_size-m_flash_config_start { } ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down } - RW_m_ram_text m_text2_start UNINIT m_text2_size { ; load address = execution address - * (RamFunction) + RW_m_ram_text m_text2_start m_text2_size { + * (CodeQuickAccess) } RW_m_ncache m_ncache_start m_ncache_size { ; ncache RW data * (NonCacheable.init) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S index a40c03d6ac..928f7d081d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/startup_MIMXRT1052.S @@ -2,44 +2,16 @@ ; * @file: startup_MIMXRT1052.s ; * @purpose: CMSIS Cortex-M7 Core Device Startup File ; * MIMXRT1052 -; * @version: 0.1 -; * @date: 2017-1-10 -; * @build: b180509 +; * @version: 1.2 +; * @date: 2018-11-27 +; * @build: b190124 ; * ------------------------------------------------------------------------- ; * -; * The Clear BSD License ; * Copyright 1997-2016 Freescale Semiconductor, Inc. -; * Copyright 2016-2018 NXP +; * Copyright 2016-2019 NXP ; * All rights reserved. ; * -; * Redistribution and use in source and binary forms, with or without -; * modification, are permitted (subject to the limitations in the -; * disclaimer below) provided that the following conditions are met: -; * -; * * Redistributions of source code must retain the above copyright -; * notice, this list of conditions and the following disclaimer. -; * -; * * Redistributions in binary form must reproduce the above copyright -; * notice, this list of conditions and the following disclaimer in the -; * documentation and/or other materials provided with the distribution. -; * -; * * Neither the name of the copyright holder nor the names of its -; * contributors may be used to endorse or promote products derived from -; * this software without specific prior written permission. -; * -; * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -; * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -; * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -; * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -; * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -; * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -; * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -; * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * SPDX-License-Identifier: BSD-3-Clause ; * ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ ; * @@ -137,10 +109,10 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD SAI3_RX_IRQHandler ;SAI3 interrupt DCD SAI3_TX_IRQHandler ;SAI3 interrupt DCD SPDIF_IRQHandler ;SPDIF interrupt - DCD ANATOP_EVENT0_IRQHandler ;ANATOP interrupt - DCD ANATOP_EVENT1_IRQHandler ;ANATOP interrupt - DCD ANATOP_TAMP_LOW_HIGH_IRQHandler ;ANATOP interrupt - DCD ANATOP_TEMP_PANIC_IRQHandler ;ANATOP interrupt + DCD PMU_EVENT_IRQHandler ;Brown-out event interrupt + DCD Reserved78_IRQHandler ;Reserved interrupt + DCD TEMP_LOW_HIGH_IRQHandler ;TempSensor low/high interrupt + DCD TEMP_PANIC_IRQHandler ;TempSensor panic interrupt DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt DCD USB_PHY2_IRQHandler ;USBPHY (UTMI0), Interrupt DCD ADC1_IRQHandler ;ADC1 interrupt @@ -228,14 +200,14 @@ __Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt - DCD Reserved168_IRQHandler ;Reserved interrupt - DCD Reserved169_IRQHandler ;Reserved interrupt - DCD Reserved170_IRQHandler ;Reserved interrupt - DCD Reserved171_IRQHandler ;Reserved interrupt - DCD Reserved172_IRQHandler ;Reserved interrupt - DCD Reserved173_IRQHandler ;Reserved interrupt - DCD SJC_ARM_DEBUG_IRQHandler ;SJC ARM debug interrupt - DCD NMI_WAKEUP_IRQHandler ;NMI wake up + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 DCD DefaultISR ;176 DCD DefaultISR ;177 DCD DefaultISR ;178 @@ -781,10 +753,10 @@ Default_Handler\ EXPORT SAI3_RX_DriverIRQHandler [WEAK] EXPORT SAI3_TX_DriverIRQHandler [WEAK] EXPORT SPDIF_DriverIRQHandler [WEAK] - EXPORT ANATOP_EVENT0_IRQHandler [WEAK] - EXPORT ANATOP_EVENT1_IRQHandler [WEAK] - EXPORT ANATOP_TAMP_LOW_HIGH_IRQHandler [WEAK] - EXPORT ANATOP_TEMP_PANIC_IRQHandler [WEAK] + EXPORT PMU_EVENT_IRQHandler [WEAK] + EXPORT Reserved78_IRQHandler [WEAK] + EXPORT TEMP_LOW_HIGH_IRQHandler [WEAK] + EXPORT TEMP_PANIC_IRQHandler [WEAK] EXPORT USB_PHY1_IRQHandler [WEAK] EXPORT USB_PHY2_IRQHandler [WEAK] EXPORT ADC1_IRQHandler [WEAK] @@ -872,14 +844,6 @@ Default_Handler\ EXPORT PWM4_2_IRQHandler [WEAK] EXPORT PWM4_3_IRQHandler [WEAK] EXPORT PWM4_FAULT_IRQHandler [WEAK] - EXPORT Reserved168_IRQHandler [WEAK] - EXPORT Reserved169_IRQHandler [WEAK] - EXPORT Reserved170_IRQHandler [WEAK] - EXPORT Reserved171_IRQHandler [WEAK] - EXPORT Reserved172_IRQHandler [WEAK] - EXPORT Reserved173_IRQHandler [WEAK] - EXPORT SJC_ARM_DEBUG_IRQHandler [WEAK] - EXPORT NMI_WAKEUP_IRQHandler [WEAK] EXPORT DefaultISR [WEAK] DMA0_DMA16_DriverIRQHandler DMA1_DMA17_DriverIRQHandler @@ -942,10 +906,10 @@ SAI2_DriverIRQHandler SAI3_RX_DriverIRQHandler SAI3_TX_DriverIRQHandler SPDIF_DriverIRQHandler -ANATOP_EVENT0_IRQHandler -ANATOP_EVENT1_IRQHandler -ANATOP_TAMP_LOW_HIGH_IRQHandler -ANATOP_TEMP_PANIC_IRQHandler +PMU_EVENT_IRQHandler +Reserved78_IRQHandler +TEMP_LOW_HIGH_IRQHandler +TEMP_PANIC_IRQHandler USB_PHY1_IRQHandler USB_PHY2_IRQHandler ADC1_IRQHandler @@ -1033,14 +997,6 @@ PWM4_1_IRQHandler PWM4_2_IRQHandler PWM4_3_IRQHandler PWM4_FAULT_IRQHandler -Reserved168_IRQHandler -Reserved169_IRQHandler -Reserved170_IRQHandler -Reserved171_IRQHandler -Reserved172_IRQHandler -Reserved173_IRQHandler -SJC_ARM_DEBUG_IRQHandler -NMI_WAKEUP_IRQHandler DefaultISR LDR R0, =DefaultISR BX R0 diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld index baa8999fc9..5992de5b7e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld @@ -7,45 +7,17 @@ ** ** Compiler: GNU C Compiler ** Reference manual: IMXRT1050RM Rev.1, 03/2018 -** Version: rev. 0.1, 2017-01-10 -** Build: b180509 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 ** ** Abstract: ** Linker file for the GNU C Compiler ** -** The Clear BSD License ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2018 NXP ** All rights reserved. ** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted (subject to the limitations in the -** disclaimer below) provided that the following conditions are met: -** -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** -** * Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from -** this software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -227,16 +199,15 @@ SECTIONS . = ALIGN(8); __data_end__ = .; /* define a global symbol at data end */ } > m_data - __ram_function_flash_start = __DATA_ROM + (__data_end__ - __data_start__); /* Symbol is used by startup for TCM data initialization */ .ram_function : AT(__ram_function_flash_start) { . = ALIGN(32); - __ram_function_ram_start = .; - *(RamFunction) + __ram_function_start__ = .; + *(CodeQuickAccess) . = ALIGN(128); - __ram_function_ram_end = .; + __ram_function_end__ = .; } > m_text2 __ram_function_size = SIZEOF(.ram_function); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S index a35793b80b..6eb7e3cdf0 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/startup_MIMXRT1052.S @@ -2,44 +2,16 @@ /* @file: startup_MIMXRT1052.s */ /* @purpose: CMSIS Cortex-M7 Core Device Startup File */ /* MIMXRT1052 */ -/* @version: 0.1 */ -/* @date: 2017-1-10 */ -/* @build: b180509 */ +/* @version: 1.2 */ +/* @date: 2018-11-27 */ +/* @build: b190124 */ /* ------------------------------------------------------------------------- */ /* */ -/* The Clear BSD License */ /* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2018 NXP */ +/* Copyright 2016-2019 NXP */ /* All rights reserved. */ /* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted (subject to the limitations in the */ -/* disclaimer below) provided that the following conditions are met: */ -/* */ -/* * Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* * Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in the */ -/* documentation and/or other materials provided with the distribution. */ -/* */ -/* * Neither the name of the copyright holder nor the names of its */ -/* contributors may be used to endorse or promote products derived from */ -/* this software without specific prior written permission. */ -/* */ -/* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE */ -/* GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT */ -/* HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED */ -/* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ -/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ -/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE */ -/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ -/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ -/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */ -/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ -/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE */ -/* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN */ -/* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* SPDX-License-Identifier: BSD-3-Clause */ /*****************************************************************************/ /* Version: GCC for ARM Embedded Processors */ /*****************************************************************************/ @@ -129,10 +101,10 @@ __isr_vector: .long SAI3_RX_IRQHandler /* SAI3 interrupt*/ .long SAI3_TX_IRQHandler /* SAI3 interrupt*/ .long SPDIF_IRQHandler /* SPDIF interrupt*/ - .long ANATOP_EVENT0_IRQHandler /* ANATOP interrupt*/ - .long ANATOP_EVENT1_IRQHandler /* ANATOP interrupt*/ - .long ANATOP_TAMP_LOW_HIGH_IRQHandler /* ANATOP interrupt*/ - .long ANATOP_TEMP_PANIC_IRQHandler /* ANATOP interrupt*/ + .long PMU_EVENT_IRQHandler /* Brown-out event interrupt*/ + .long Reserved78_IRQHandler /* Reserved interrupt*/ + .long TEMP_LOW_HIGH_IRQHandler /* TempSensor low/high interrupt*/ + .long TEMP_PANIC_IRQHandler /* TempSensor panic interrupt*/ .long USB_PHY1_IRQHandler /* USBPHY (UTMI0), Interrupt*/ .long USB_PHY2_IRQHandler /* USBPHY (UTMI0), Interrupt*/ .long ADC1_IRQHandler /* ADC1 interrupt*/ @@ -220,14 +192,14 @@ __isr_vector: .long PWM4_2_IRQHandler /* PWM4 capture 2, compare 2, or reload 0 interrupt*/ .long PWM4_3_IRQHandler /* PWM4 capture 3, compare 3, or reload 0 interrupt*/ .long PWM4_FAULT_IRQHandler /* PWM4 fault or reload error interrupt*/ - .long Reserved168_IRQHandler /* Reserved interrupt*/ - .long Reserved169_IRQHandler /* Reserved interrupt*/ - .long Reserved170_IRQHandler /* Reserved interrupt*/ - .long Reserved171_IRQHandler /* Reserved interrupt*/ - .long Reserved172_IRQHandler /* Reserved interrupt*/ - .long Reserved173_IRQHandler /* Reserved interrupt*/ - .long SJC_ARM_DEBUG_IRQHandler /* SJC ARM debug interrupt*/ - .long NMI_WAKEUP_IRQHandler /* NMI wake up*/ + .long DefaultISR /* 168*/ + .long DefaultISR /* 169*/ + .long DefaultISR /* 170*/ + .long DefaultISR /* 171*/ + .long DefaultISR /* 172*/ + .long DefaultISR /* 173*/ + .long DefaultISR /* 174*/ + .long DefaultISR /* 175*/ .long DefaultISR /* 176*/ .long DefaultISR /* 177*/ .long DefaultISR /* 178*/ @@ -339,23 +311,17 @@ Reset_Handler: * __etext: End of code section, i.e., begin of data sections to copy from. * __data_start__/__data_end__: RAM address range that data should be * __noncachedata_start__/__noncachedata_end__ : none cachable region + * __ram_function_start__/__ram_function_end__ : ramfunction region * copied to. Both must be aligned to 4 bytes boundary. */ ldr r1, =__etext ldr r2, =__data_start__ ldr r3, =__data_end__ -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else +#ifdef __PERFORMANCE_IMPLEMENTATION +/* Here are two copies of loop implementations. First one favors performance + * and the second one favors code size. Default uses the second one. + * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ subs r3, r2 ble .LC1 .LC0: @@ -364,18 +330,45 @@ Reset_Handler: str r0, [r2, r3] bgt .LC0 .LC1: -#endif -#ifdef __STARTUP_INITIALIZE_NONCACHEDATA - ldr r2, =__noncachedata_start__ - ldr r3, =__noncachedata_init_end__ -#if 1 -.LC2: +#else /* code size implemenation */ +.LC0: cmp r2, r3 ittt lt ldrlt r0, [r1], #4 strlt r0, [r2], #4 - blt .LC2 -#else + blt .LC0 +#endif +#ifdef __STARTUP_INITIALIZE_RAMFUNCTION + ldr r2, =__ram_function_start__ + ldr r3, =__ram_function_end__ +#ifdef __PERFORMANCE_IMPLEMENTATION +/* Here are two copies of loop implementations. First one favors performance + * and the second one favors code size. Default uses the second one. + * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ + subs r3, r2 + ble .LC_ramfunc_copy_end +.LC_ramfunc_copy_start: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC_ramfunc_copy_start +.LC_ramfunc_copy_end: +#else /* code size implemenation */ +.LC_ramfunc_copy_start: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC_ramfunc_copy_start +#endif +#endif /* __STARTUP_INITIALIZE_RAMFUNCTION */ +#ifdef __STARTUP_INITIALIZE_NONCACHEDATA + ldr r2, =__noncachedata_start__ + ldr r3, =__noncachedata_init_end__ +#ifdef __PERFORMANCE_IMPLEMENTATION +/* Here are two copies of loop implementations. First one favors performance + * and the second one favors code size. Default uses the second one. + * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */ subs r3, r2 ble .LC3 .LC2: @@ -384,6 +377,13 @@ Reset_Handler: str r0, [r2, r3] bgt .LC2 .LC3: +#else /* code size implemenation */ +.LC2: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC2 #endif /* zero inited ncache section initialization */ ldr r3, =__noncachedata_end__ @@ -484,15 +484,6 @@ SysTick_Handler: bx r0 .size SysTick_Handler, . - SysTick_Handler - .align 1 - .thumb_func - .weak NMI_WAKEUP_IRQHandler - .type NMI_WAKEUP_IRQHandler, %function -NMI_WAKEUP_IRQHandler: - ldr r0,=NMI_WAKEUP_IRQHandler - bx r0 - .size NMI_WAKEUP_IRQHandler, . - NMI_WAKEUP_IRQHandler - .align 1 .thumb_func .weak DMA0_DMA16_IRQHandler @@ -991,10 +982,10 @@ ENET_1588_Timer_IRQHandler: def_irq_handler SAI3_RX_DriverIRQHandler def_irq_handler SAI3_TX_DriverIRQHandler def_irq_handler SPDIF_DriverIRQHandler - def_irq_handler ANATOP_EVENT0_IRQHandler - def_irq_handler ANATOP_EVENT1_IRQHandler - def_irq_handler ANATOP_TAMP_LOW_HIGH_IRQHandler - def_irq_handler ANATOP_TEMP_PANIC_IRQHandler + def_irq_handler PMU_EVENT_IRQHandler + def_irq_handler Reserved78_IRQHandler + def_irq_handler TEMP_LOW_HIGH_IRQHandler + def_irq_handler TEMP_PANIC_IRQHandler def_irq_handler USB_PHY1_IRQHandler def_irq_handler USB_PHY2_IRQHandler def_irq_handler ADC1_IRQHandler @@ -1082,12 +1073,5 @@ ENET_1588_Timer_IRQHandler: def_irq_handler PWM4_2_IRQHandler def_irq_handler PWM4_3_IRQHandler def_irq_handler PWM4_FAULT_IRQHandler - def_irq_handler Reserved168_IRQHandler - def_irq_handler Reserved169_IRQHandler - def_irq_handler Reserved170_IRQHandler - def_irq_handler Reserved171_IRQHandler - def_irq_handler Reserved172_IRQHandler - def_irq_handler Reserved173_IRQHandler - def_irq_handler SJC_ARM_DEBUG_IRQHandler .end diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf index 2842fee8d6..43b30f2872 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf @@ -7,45 +7,17 @@ ** ** Compiler: IAR ANSI C/C++ Compiler for ARM ** Reference manual: IMXRT1050RM Rev.1, 03/2018 -** Version: rev. 0.1, 2017-01-10 -** Build: b180509 +** Version: rev. 1.0, 2018-09-21 +** Build: b180921 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** -** The Clear BSD License ** Copyright 2016 Freescale Semiconductor, Inc. ** Copyright 2016-2018 NXP ** All rights reserved. ** -** Redistribution and use in source and binary forms, with or without -** modification, are permitted (subject to the limitations in the -** disclaimer below) provided that the following conditions are met: -** -** * Redistributions of source code must retain the above copyright -** notice, this list of conditions and the following disclaimer. -** -** * Redistributions in binary form must reproduce the above copyright -** notice, this list of conditions and the following disclaimer in the -** documentation and/or other materials provided with the distribution. -** -** * Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from -** this software without specific prior written permission. -** -** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** SPDX-License-Identifier: BSD-3-Clause ** ** http: www.nxp.com ** mail: support@nxp.com @@ -95,6 +67,7 @@ define symbol m_boot_hdr_ivt_start = 0x60001000; define symbol m_boot_hdr_boot_data_start = 0x60001020; define symbol m_boot_hdr_dcd_data_start = 0x60001030; +/* Sizes */ if (isdefinedsymbol(__stack_size__)) { define symbol __size_cstack__ = __stack_size__; } else { @@ -129,8 +102,9 @@ define block HEAP with alignment = 8, size = __size_heap__ { }; define block RW { first readwrite, section m_usb_dma_init_data }; define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data }; define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init }; +define block QACCESS_FUNC {section .textrw}; -initialize by copy { readwrite, section .textrw }; +initialize by copy { readwrite }; do not initialize { section .noinit }; place at address mem: m_interrupts_start { readonly section .intvec }; @@ -143,10 +117,10 @@ place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_ keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data }; place in TEXT_region { readonly }; -place in DATA3_region { block RW }; -place in DATA3_region { block ZI }; -place in DATA3_region { last block HEAP }; +place in DATA3_region { block RW }; +place in DATA3_region { block ZI }; +place in DATA3_region { last block HEAP }; place in CSTACK_region { block CSTACK }; place in NCACHE_region { block NCACHE_VAR }; -place in TEXT2_region { section .textrw}; +place in TEXT2_region { block QACCESS_FUNC }; place in m_interrupts_ram_region { section m_interrupts_ram }; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S index 620c96ee70..247f46540c 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/startup_MIMXRT1052.S @@ -2,44 +2,16 @@ ; @file: startup_MIMXRT1052.s ; @purpose: CMSIS Cortex-M7 Core Device Startup File ; MIMXRT1052 -; @version: 0.1 -; @date: 2017-1-10 -; @build: b180509 +; @version: 1.2 +; @date: 2018-11-27 +; @build: b190124 ; ------------------------------------------------------------------------- ; -; The Clear BSD License ; Copyright 1997-2016 Freescale Semiconductor, Inc. -; Copyright 2016-2018 NXP +; Copyright 2016-2019 NXP ; All rights reserved. ; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted (subject to the limitations in the -; disclaimer below) provided that the following conditions are met: -; -; * Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; -; * Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; -; * Neither the name of the copyright holder nor the names of its -; contributors may be used to endorse or promote products derived from -; this software without specific prior written permission. -; -; NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE -; GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT -; HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED -; WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -; BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE -; OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN -; IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; SPDX-License-Identifier: BSD-3-Clause ; ; The modules in this file are included in the libraries, and may be replaced ; by any user-defined modules that define the PUBLIC symbol _program_start or @@ -155,10 +127,10 @@ __vector_table_0x1c DCD SAI3_RX_IRQHandler ;SAI3 interrupt DCD SAI3_TX_IRQHandler ;SAI3 interrupt DCD SPDIF_IRQHandler ;SPDIF interrupt - DCD ANATOP_EVENT0_IRQHandler ;ANATOP interrupt - DCD ANATOP_EVENT1_IRQHandler ;ANATOP interrupt - DCD ANATOP_TAMP_LOW_HIGH_IRQHandler ;ANATOP interrupt - DCD ANATOP_TEMP_PANIC_IRQHandler ;ANATOP interrupt + DCD PMU_EVENT_IRQHandler ;Brown-out event interrupt + DCD Reserved78_IRQHandler ;Reserved interrupt + DCD TEMP_LOW_HIGH_IRQHandler ;TempSensor low/high interrupt + DCD TEMP_PANIC_IRQHandler ;TempSensor panic interrupt DCD USB_PHY1_IRQHandler ;USBPHY (UTMI0), Interrupt DCD USB_PHY2_IRQHandler ;USBPHY (UTMI0), Interrupt DCD ADC1_IRQHandler ;ADC1 interrupt @@ -246,14 +218,14 @@ __vector_table_0x1c DCD PWM4_2_IRQHandler ;PWM4 capture 2, compare 2, or reload 0 interrupt DCD PWM4_3_IRQHandler ;PWM4 capture 3, compare 3, or reload 0 interrupt DCD PWM4_FAULT_IRQHandler ;PWM4 fault or reload error interrupt - DCD Reserved168_IRQHandler ;Reserved interrupt - DCD Reserved169_IRQHandler ;Reserved interrupt - DCD Reserved170_IRQHandler ;Reserved interrupt - DCD Reserved171_IRQHandler ;Reserved interrupt - DCD Reserved172_IRQHandler ;Reserved interrupt - DCD Reserved173_IRQHandler ;Reserved interrupt - DCD SJC_ARM_DEBUG_IRQHandler ;SJC ARM debug interrupt - DCD NMI_WAKEUP_IRQHandler ;NMI wake up + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 DCD DefaultISR ;176 DCD DefaultISR ;177 DCD DefaultISR ;178 @@ -707,10 +679,10 @@ SPDIF_IRQHandler LDR R0, =SPDIF_DriverIRQHandler BX R0 - PUBWEAK ANATOP_EVENT0_IRQHandler - PUBWEAK ANATOP_EVENT1_IRQHandler - PUBWEAK ANATOP_TAMP_LOW_HIGH_IRQHandler - PUBWEAK ANATOP_TEMP_PANIC_IRQHandler + PUBWEAK PMU_EVENT_IRQHandler + PUBWEAK Reserved78_IRQHandler + PUBWEAK TEMP_LOW_HIGH_IRQHandler + PUBWEAK TEMP_PANIC_IRQHandler PUBWEAK USB_PHY1_IRQHandler PUBWEAK USB_PHY2_IRQHandler PUBWEAK ADC1_IRQHandler @@ -840,14 +812,6 @@ ENET_1588_Timer_IRQHandler PUBWEAK PWM4_2_IRQHandler PUBWEAK PWM4_3_IRQHandler PUBWEAK PWM4_FAULT_IRQHandler - PUBWEAK Reserved168_IRQHandler - PUBWEAK Reserved169_IRQHandler - PUBWEAK Reserved170_IRQHandler - PUBWEAK Reserved171_IRQHandler - PUBWEAK Reserved172_IRQHandler - PUBWEAK Reserved173_IRQHandler - PUBWEAK SJC_ARM_DEBUG_IRQHandler - PUBWEAK NMI_WAKEUP_IRQHandler PUBWEAK DefaultISR SECTION .text:CODE:REORDER:NOROOT(1) DMA0_DMA16_DriverIRQHandler @@ -911,10 +875,10 @@ SAI2_DriverIRQHandler SAI3_RX_DriverIRQHandler SAI3_TX_DriverIRQHandler SPDIF_DriverIRQHandler -ANATOP_EVENT0_IRQHandler -ANATOP_EVENT1_IRQHandler -ANATOP_TAMP_LOW_HIGH_IRQHandler -ANATOP_TEMP_PANIC_IRQHandler +PMU_EVENT_IRQHandler +Reserved78_IRQHandler +TEMP_LOW_HIGH_IRQHandler +TEMP_PANIC_IRQHandler USB_PHY1_IRQHandler USB_PHY2_IRQHandler ADC1_IRQHandler @@ -1002,14 +966,6 @@ PWM4_1_IRQHandler PWM4_2_IRQHandler PWM4_3_IRQHandler PWM4_FAULT_IRQHandler -Reserved168_IRQHandler -Reserved169_IRQHandler -Reserved170_IRQHandler -Reserved171_IRQHandler -Reserved172_IRQHandler -Reserved173_IRQHandler -SJC_ARM_DEBUG_IRQHandler -NMI_WAKEUP_IRQHandler DefaultISR B DefaultISR