diff --git a/libraries/mbed/common/InterruptManager.cpp b/libraries/mbed/common/InterruptManager.cpp index 59ce56b94d..e92fb68d4e 100644 --- a/libraries/mbed/common/InterruptManager.cpp +++ b/libraries/mbed/common/InterruptManager.cpp @@ -1,3 +1,6 @@ +#include "cmsis.h" +#if defined(NVIC_NUM_VECTORS) + #include "InterruptManager.h" #include @@ -87,3 +90,4 @@ void InterruptManager::static_irq_helper() { } // namespace mbed +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h new file mode 100644 index 0000000000..0db2805e52 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h @@ -0,0 +1,1035 @@ +/**************************************************************************//** + * @file MBRZA1H.h + * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for + * Renesas MBRZA1H Device Series + * @version + * @date 19 Sept 2013 + * + * @note + * + ******************************************************************************/ + +/* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved */ + +#ifndef __MBRZA1H_H__ +#define __MBRZA1H_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/****** SGI Interrupts Numbers ****************************************/ + SGI0_IRQn = 0, + SGI1_IRQn = 1, + SGI2_IRQn = 2, + SGI3_IRQn = 3, + SGI4_IRQn = 4, + SGI5_IRQn = 5, + SGI6_IRQn = 6, + SGI7_IRQn = 7, + SGI8_IRQn = 8, + SGI9_IRQn = 9, + SGI10_IRQn = 10, + SGI11_IRQn = 11, + SGI12_IRQn = 12, + SGI13_IRQn = 13, + SGI14_IRQn = 14, + SGI15_IRQn = 15, + +/****** Cortex-A9 Processor Exceptions Numbers ****************************************/ + /* 16 - 578 */ + PMUIRQ0_IRQn = 16, + COMMRX0_IRQn = 17, + COMMTX0_IRQn = 18, + CTIIRQ0_IRQn = 19, + + IRQ0_IRQn = 32, + IRQ1_IRQn = 33, + IRQ2_IRQn = 34, + IRQ3_IRQn = 35, + IRQ4_IRQn = 36, + IRQ5_IRQn = 37, + IRQ6_IRQn = 38, + IRQ7_IRQn = 39, + + PL310ERR_IRQn = 40, + + DMAINT0_IRQn = 41, /*!< DMAC Interrupt */ + DMAINT1_IRQn = 42, /*!< DMAC Interrupt */ + DMAINT2_IRQn = 43, /*!< DMAC Interrupt */ + DMAINT3_IRQn = 44, /*!< DMAC Interrupt */ + DMAINT4_IRQn = 45, /*!< DMAC Interrupt */ + DMAINT5_IRQn = 46, /*!< DMAC Interrupt */ + DMAINT6_IRQn = 47, /*!< DMAC Interrupt */ + DMAINT7_IRQn = 48, /*!< DMAC Interrupt */ + DMAINT8_IRQn = 49, /*!< DMAC Interrupt */ + DMAINT9_IRQn = 50, /*!< DMAC Interrupt */ + DMAINT10_IRQn = 51, /*!< DMAC Interrupt */ + DMAINT11_IRQn = 52, /*!< DMAC Interrupt */ + DMAINT12_IRQn = 53, /*!< DMAC Interrupt */ + DMAINT13_IRQn = 54, /*!< DMAC Interrupt */ + DMAINT14_IRQn = 55, /*!< DMAC Interrupt */ + DMAINT15_IRQn = 56, /*!< DMAC Interrupt */ + DMAERR_IRQn = 57, /*!< DMAC Interrupt */ + + /* 58-72 Reserved */ + + USBI0_IRQn = 73, + USBI1_IRQn = 74, + + S0_VI_VSYNC0_IRQn = 75, + S0_LO_VSYNC0_IRQn = 76, + S0_VSYNCERR0_IRQn = 77, + GR3_VLINE0_IRQn = 78, + S0_VFIELD0_IRQn = 79, + IV1_VBUFERR0_IRQn = 80, + IV3_VBUFERR0_IRQn = 81, + IV5_VBUFERR0_IRQn = 82, + IV6_VBUFERR0_IRQn = 83, + S0_WLINE0_IRQn = 84, + S1_VI_VSYNC0_IRQn = 85, + S1_LO_VSYNC0_IRQn = 86, + S1_VSYNCERR0_IRQn = 87, + S1_VFIELD0_IRQn = 88, + IV2_VBUFERR0_IRQn = 89, + IV4_VBUFERR0_IRQn = 90, + S1_WLINE0_IRQn = 91, + OIR_VI_VSYNC0_IRQn = 92, + OIR_LO_VSYNC0_IRQn = 93, + OIR_VSYNCERR0_IRQn = 94, + OIR_VFIELD0_IRQn = 95, + IV7_VBUFERR0_IRQn = 96, + IV8_VBUFERR0_IRQn = 97, + /* 98 Reserved */ + S0_VI_VSYNC1_IRQn = 99, + S0_LO_VSYNC1_IRQn = 100, + S0_VSYNCERR1_IRQn = 101, + GR3_VLINE1_IRQn = 102, + S0_VFIELD1_IRQn = 103, + IV1_VBUFERR1_IRQn = 104, + IV3_VBUFERR1_IRQn = 105, + IV5_VBUFERR1_IRQn = 106, + IV6_VBUFERR1_IRQn = 107, + S0_WLINE1_IRQn = 108, + S1_VI_VSYNC1_IRQn = 109, + S1_LO_VSYNC1_IRQn = 110, + S1_VSYNCERR1_IRQn = 111, + S1_VFIELD1_IRQn = 112, + IV2_VBUFERR1_IRQn = 113, + IV4_VBUFERR1_IRQn = 114, + S1_WLINE1_IRQn = 115, + OIR_VI_VSYNC1_IRQn = 116, + OIR_LO_VSYNC1_IRQn = 117, + OIR_VSYNCERR1_IRQn = 118, + OIR_VFIELD1_IRQn = 119, + IV7_VBUFERR1_IRQn = 120, + IV8_VBUFERR1_IRQn = 121, + /* Reserved = 122 */ + + IMRDI_IRQn = 123, + IMR2I0_IRQn = 124, + IMR2I1_IRQn = 125, + + JEDI_IRQn = 126, + JDTI_IRQn = 127, + + CMP0_IRQn = 128, + CMP1_IRQn = 129, + + INT0_IRQn = 130, + INT1_IRQn = 131, + INT2_IRQn = 132, + INT3_IRQn = 133, + + OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */ + OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */ + + CMI_IRQn = 136, + WTOUT_IRQn = 137, + + ITI_IRQn = 138, + + TGI0A_IRQn = 139, + TGI0B_IRQn = 140, + TGI0C_IRQn = 141, + TGI0D_IRQn = 142, + TGI0V_IRQn = 143, + TGI0E_IRQn = 144, + TGI0F_IRQn = 145, + TGI1A_IRQn = 146, + TGI1B_IRQn = 147, + TGI1V_IRQn = 148, + TGI1U_IRQn = 149, + TGI2A_IRQn = 150, + TGI2B_IRQn = 151, + TGI2V_IRQn = 152, + TGI2U_IRQn = 153, + TGI3A_IRQn = 154, + TGI3B_IRQn = 155, + TGI3C_IRQn = 156, + TGI3D_IRQn = 157, + TGI3V_IRQn = 158, + TGI4A_IRQn = 159, + TGI4B_IRQn = 160, + TGI4C_IRQn = 161, + TGI4D_IRQn = 162, + TGI4V_IRQn = 163, + + CMI1_IRQn = 164, + CMI2_IRQn = 165, + + SGDEI0_IRQn = 166, + SGDEI1_IRQn = 167, + SGDEI2_IRQn = 168, + SGDEI3_IRQn = 169, + + ADI_IRQn = 170, + LMTI_IRQn = 171, + + SSII0_IRQn = 172, /*!< SSIF Interrupt */ + SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */ + SSITXI0_IRQn = 174, /*!< SSIF Interrupt */ + SSII1_IRQn = 175, /*!< SSIF Interrupt */ + SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */ + SSITXI1_IRQn = 177, /*!< SSIF Interrupt */ + SSII2_IRQn = 178, /*!< SSIF Interrupt */ + SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */ + SSII3_IRQn = 180, /*!< SSIF Interrupt */ + SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */ + SSITXI3_IRQn = 182, /*!< SSIF Interrupt */ + SSII4_IRQn = 183, /*!< SSIF Interrupt */ + SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */ + SSII5_IRQn = 185, /*!< SSIF Interrupt */ + SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */ + SSITXI5_IRQn = 187, /*!< SSIF Interrupt */ + + SPDIFI_IRQn = 188, + + INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */ + INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */ + INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */ + INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */ + INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */ + INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */ + INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */ + INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */ + INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */ + INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */ + INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */ + INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */ + INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */ + INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */ + INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */ + INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */ + INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */ + INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */ + INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */ + INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */ + INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */ + INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */ + INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */ + INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */ + INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */ + INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */ + INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */ + INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */ + INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */ + INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */ + INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */ + INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */ + + SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */ + SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */ + SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */ + SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */ + SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */ + SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */ + SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */ + SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */ + SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */ + SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */ + SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */ + SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */ + SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */ + SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */ + SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */ + SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */ + SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */ + SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */ + SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */ + SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */ + SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */ + SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */ + SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */ + SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */ + SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */ + SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */ + SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */ + SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */ + SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */ + SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */ + SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */ + SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */ + + INTRCANGERR_IRQn = 253, + INTRCANGRECC_IRQn = 254, + INTRCAN0REC_IRQn = 255, + INTRCAN0ERR_IRQn = 256, + INTRCAN0TRX_IRQn = 257, + INTRCAN1REC_IRQn = 258, + INTRCAN1ERR_IRQn = 259, + INTRCAN1TRX_IRQn = 260, + INTRCAN2REC_IRQn = 261, + INTRCAN2ERR_IRQn = 262, + INTRCAN2TRX_IRQn = 263, + INTRCAN3REC_IRQn = 264, + INTRCAN3ERR_IRQn = 265, + INTRCAN3TRX_IRQn = 266, + INTRCAN4REC_IRQn = 267, + INTRCAN4ERR_IRQn = 268, + INTRCAN4TRX_IRQn = 269, + + RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */ + RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */ + RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */ + RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */ + RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */ + RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */ + RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */ + RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */ + RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */ + RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */ + RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */ + RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */ + RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */ + RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */ + RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */ + + IEBBTD_IRQn = 285, + IEBBTERR_IRQn = 286, + IEBBTSTA_IRQn = 287, + IEBBTV_IRQn = 288, + + ISY_IRQn = 289, + IERR_IRQn = 290, + ITARG_IRQn = 291, + ISEC_IRQn = 292, + IBUF_IRQn = 293, + IREADY_IRQn = 294, + + STERB_IRQn = 295, + FLTENDI_IRQn = 296, + FLTREQ0I_IRQn = 297, + FLTREQ1I_IRQn = 298, + + MMC0_IRQn = 299, + MMC1_IRQn = 300, + MMC2_IRQn = 301, + + SCHI0_3_IRQn = 302, + SDHI0_0_IRQn = 303, + SDHI0_1_IRQn = 304, + SCHI1_3_IRQn = 305, + SDHI1_0_IRQn = 306, + SDHI1_1_IRQn = 307, + + ARM_IRQn = 308, + PRD_IRQn = 309, + CUP_IRQn = 310, + + SCUAI0_IRQn = 311, + SCUAI1_IRQn = 312, + SCUFDI0_IRQn = 313, + SCUFDI1_IRQn = 314, + SCUFDI2_IRQn = 315, + SCUFDI3_IRQn = 316, + SCUFUI0_IRQn = 317, + SCUFUI1_IRQn = 318, + SCUFUI2_IRQn = 319, + SCUFUI3_IRQn = 320, + SCUDVI0_IRQn = 321, + SCUDVI1_IRQn = 322, + SCUDVI2_IRQn = 323, + SCUDVI3_IRQn = 324, + + MLB_CINT_IRQn = 325, + MLB_SINT_IRQn = 326, + + DRC10_IRQn = 327, + DRC11_IRQn = 328, + + /* 329-330 Reserved */ + + LINI0_INT_T_IRQn = 331, + LINI0_INT_R_IRQn = 332, + LINI0_INT_S_IRQn = 333, + LINI0_INT_M_IRQn = 334, + LINI1_INT_T_IRQn = 335, + LINI1_INT_R_IRQn = 336, + LINI1_INT_S_IRQn = 337, + LINI1_INT_M_IRQn = 338, + + /* 339-346 Reserved */ + + SCIERI0_IRQn = 347, + SCIRXI0_IRQn = 348, + SCITXI0_IRQn = 349, + SCITEI0_IRQn = 350, + SCIERI1_IRQn = 351, + SCIRXI1_IRQn = 352, + SCITXI1_IRQn = 353, + SCITEI1_IRQn = 354, + + AVBI_DATA = 355, + AVBI_ERROR = 356, + AVBI_MANAGE = 357, + AVBI_MAC = 358, + + ETHERI_IRQn = 359, + + /* 360-363 Reserved */ + + CEUI_IRQn = 364, + + /* 365-380 Reserved */ + + + H2XMLB_ERRINT_IRQn = 381, + H2XIC1_ERRINT_IRQn = 382, + X2HPERI1_ERRINT_IRQn = 383, + X2HPERR2_ERRINT_IRQn = 384, + X2HPERR34_ERRINT_IRQn= 385, + X2HPERR5_ERRINT_IRQn = 386, + X2HPERR67_ERRINT_IRQn= 387, + X2HDBGR_ERRINT_IRQn = 388, + X2HBSC_ERRINT_IRQn = 389, + X2HSPI1_ERRINT_IRQn = 390, + X2HSPI2_ERRINT_IRQn = 391, + PRRI_IRQn = 392, + + IFEI0_IRQn = 393, + OFFI0_IRQn = 394, + PFVEI0_IRQn = 395, + IFEI1_IRQn = 396, + OFFI1_IRQn = 397, + PFVEI1_IRQn = 398, + + /* 399-415 Reserved */ + TINT0_IRQn = 416, + TINT1_IRQn = 417, + TINT2_IRQn = 418, + TINT3_IRQn = 419, + TINT4_IRQn = 420, + TINT5_IRQn = 421, + TINT6_IRQn = 422, + TINT7_IRQn = 423, + TINT8_IRQn = 424, + TINT9_IRQn = 425, + TINT10_IRQn = 426, + TINT11_IRQn = 427, + TINT12_IRQn = 428, + TINT13_IRQn = 429, + TINT14_IRQn = 430, + TINT15_IRQn = 431, + TINT16_IRQn = 432, + TINT17_IRQn = 433, + TINT18_IRQn = 434, + TINT19_IRQn = 435, + TINT20_IRQn = 436, + TINT21_IRQn = 437, + TINT22_IRQn = 438, + TINT23_IRQn = 439, + TINT24_IRQn = 440, + TINT25_IRQn = 441, + TINT26_IRQn = 442, + TINT27_IRQn = 443, + TINT28_IRQn = 444, + TINT29_IRQn = 445, + TINT30_IRQn = 446, + TINT31_IRQn = 447, + TINT32_IRQn = 448, + TINT33_IRQn = 449, + TINT34_IRQn = 450, + TINT35_IRQn = 451, + TINT36_IRQn = 452, + TINT37_IRQn = 453, + TINT38_IRQn = 454, + TINT39_IRQn = 455, + TINT40_IRQn = 456, + TINT41_IRQn = 457, + TINT42_IRQn = 458, + TINT43_IRQn = 459, + TINT44_IRQn = 460, + TINT45_IRQn = 461, + TINT46_IRQn = 462, + TINT47_IRQn = 463, + TINT48_IRQn = 464, + TINT49_IRQn = 465, + TINT50_IRQn = 466, + TINT51_IRQn = 467, + TINT52_IRQn = 468, + TINT53_IRQn = 469, + TINT54_IRQn = 470, + TINT55_IRQn = 471, + TINT56_IRQn = 472, + TINT57_IRQn = 473, + TINT58_IRQn = 474, + TINT59_IRQn = 475, + TINT60_IRQn = 476, + TINT61_IRQn = 477, + TINT62_IRQn = 478, + TINT63_IRQn = 479, + TINT64_IRQn = 480, + TINT65_IRQn = 481, + TINT66_IRQn = 482, + TINT67_IRQn = 483, + TINT68_IRQn = 484, + TINT69_IRQn = 485, + TINT70_IRQn = 486, + TINT71_IRQn = 487, + TINT72_IRQn = 488, + TINT73_IRQn = 489, + TINT74_IRQn = 490, + TINT75_IRQn = 491, + TINT76_IRQn = 492, + TINT77_IRQn = 493, + TINT78_IRQn = 494, + TINT79_IRQn = 495, + TINT80_IRQn = 496, + TINT81_IRQn = 497, + TINT82_IRQn = 498, + TINT83_IRQn = 499, + TINT84_IRQn = 500, + TINT85_IRQn = 501, + TINT86_IRQn = 502, + TINT87_IRQn = 503, + TINT88_IRQn = 504, + TINT89_IRQn = 505, + TINT90_IRQn = 506, + TINT91_IRQn = 507, + TINT92_IRQn = 508, + TINT93_IRQn = 509, + TINT94_IRQn = 510, + TINT95_IRQn = 511, + TINT96_IRQn = 512, + TINT97_IRQn = 513, + TINT98_IRQn = 514, + TINT99_IRQn = 515, + TINT100_IRQn = 516, + TINT101_IRQn = 517, + TINT102_IRQn = 518, + TINT103_IRQn = 519, + TINT104_IRQn = 520, + TINT105_IRQn = 521, + TINT106_IRQn = 522, + TINT107_IRQn = 523, + TINT108_IRQn = 524, + TINT109_IRQn = 525, + TINT110_IRQn = 526, + TINT111_IRQn = 527, + TINT112_IRQn = 528, + TINT113_IRQn = 529, + TINT114_IRQn = 530, + TINT115_IRQn = 531, + TINT116_IRQn = 532, + TINT117_IRQn = 533, + TINT118_IRQn = 534, + TINT119_IRQn = 535, + TINT120_IRQn = 536, + TINT121_IRQn = 537, + TINT122_IRQn = 538, + TINT123_IRQn = 539, + TINT124_IRQn = 540, + TINT125_IRQn = 541, + TINT126_IRQn = 542, + TINT127_IRQn = 543, + TINT128_IRQn = 544, + TINT129_IRQn = 545, + TINT130_IRQn = 546, + TINT131_IRQn = 547, + TINT132_IRQn = 548, + TINT133_IRQn = 549, + TINT134_IRQn = 550, + TINT135_IRQn = 551, + TINT136_IRQn = 552, + TINT137_IRQn = 553, + TINT138_IRQn = 554, + TINT139_IRQn = 555, + TINT140_IRQn = 556, + TINT141_IRQn = 557, + TINT142_IRQn = 558, + TINT143_IRQn = 559, + TINT144_IRQn = 560, + TINT145_IRQn = 561, + TINT146_IRQn = 562, + TINT147_IRQn = 563, + TINT148_IRQn = 564, + TINT149_IRQn = 565, + TINT150_IRQn = 566, + TINT151_IRQn = 567, + TINT152_IRQn = 568, + TINT153_IRQn = 569, + TINT154_IRQn = 570, + TINT155_IRQn = 571, + TINT156_IRQn = 572, + TINT157_IRQn = 573, + TINT158_IRQn = 574, + TINT159_IRQn = 575, + TINT160_IRQn = 576, + TINT161_IRQn = 577, + TINT162_IRQn = 578, + TINT163_IRQn = 579, + TINT164_IRQn = 580, + TINT165_IRQn = 581, + TINT166_IRQn = 582, + TINT167_IRQn = 583, + TINT168_IRQn = 584, + TINT169_IRQn = 585, + TINT170_IRQn = 586 + +} IRQn_Type; + +#define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn + +/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ +#define __CA9_REV 0x0000 /*!< Core revision r0 */ + +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +#include +#include "system_MBRZA1H.h" + + +/******************************************************************************/ +/* Device Specific Peripheral Section */ +/******************************************************************************/ +/** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals + Renesas_RZ_A1 Device Specific Peripheral registers structures + @{ +*/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +#include "pl310.h" +#include "gic.h" + +#include "ostm_iodefine.h" +#include "gpio_iodefine.h" +#include "cpg_iodefine.h" +#include "l2c_iodefine.h" + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/*@}*/ /* end of group Renesas_RZ_A1_Peripherals */ + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping + @{ +*/ + +/* R7S72100 CPU board */ +#define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ +#define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ +#define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ +#define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ +#define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ +#define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ +#define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ +#define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ +#define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ +#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ +#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ +#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ +#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ +#define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ +#define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ +#define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ +#define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ + +//Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map +//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0. +#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = NON_SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = NORMAL; \ + region.sec_t = SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0. +#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = NON_SECURE; \ + region.xn_t = EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +//Sect_Normal_RO. Sect_Normal_Cod, but not executable +#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = NON_SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable +#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = WB_WA; \ + region.outer_norm_t = WB_WA; \ + region.mem_t = NORMAL; \ + region.sec_t = NON_SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); +//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 +#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = READ; \ + region.user_t = READ; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); + +//Sect_Device_RW. Sect_Device_RO, but writeable +#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = STRONGLY_ORDERED; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_section_descriptor(&descriptor_l1, region); +//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 +#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); + +//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 +#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ + region.domain = 0x0; \ + region.e_t = ECC_DISABLED; \ + region.g_t = GLOBAL; \ + region.inner_norm_t = NON_CACHEABLE; \ + region.outer_norm_t = NON_CACHEABLE; \ + region.mem_t = SHARED_DEVICE; \ + region.sec_t = SECURE; \ + region.xn_t = NON_EXECUTE; \ + region.priv_t = RW; \ + region.user_t = RW; \ + region.sh_t = NON_SHARED; \ + __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); + +/*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */ + +/******************************************************************************/ +/* Clock Settings */ +/******************************************************************************/ +/** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions + @{ +*/ + +/* + * Clock Mode 0 settings + * SW1-4(MD_CLK):ON + * SW1-5(MD_CLKS):ON + * FRQCR=0x1035 + * CLKEN2 = 0b - unstable + * CLKEN[1:0]=01b - Output, Low, Low + * IFC[1:0] =00b - CPU clock is 1/1 PLL clock + * FRQCR2=0x0001 + * GFC[1:0] =01b - Graphic clock is 2/3 bus clock + */ +#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u) +#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u) +#define CM0_RENESAS_RZ_A1_I_CLK (400000000u) +#define CM0_RENESAS_RZ_A1_G_CLK (266666666u) +#define CM0_RENESAS_RZ_A1_B_CLK (133333333u) +#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u) +#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) + +/* + * Clock Mode 1 settings + * SW1-4(MD_CLK):OFF + * SW1-5(MD_CLKS):ON + * FRQCR=0x1335 + * CLKEN2 = 0b - unstable + * CLKEN[1:0]=01b - Output, Low, Low + * IFC[1:0] =11b - CPU clock is 1/3 PLL clock + * FRQCR2=0x0003 + * GFC[1:0] =11b - graphic clock is 1/3 bus clock + */ +#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u) +#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u) +#define CM1_RENESAS_RZ_A1_I_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_G_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_B_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) +#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) + +/*@}*/ /* end of group Renesas_RZ_A1_Clocks */ + +/******************************************************************************/ +/* CPG Settings */ +/******************************************************************************/ +/** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions + @{ +*/ + +#define CPG_FRQCR_SHIFT_CKOEN2 (14) +#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) +#define CPG_FRQCR_SHIFT_CKOEN0 (12) +#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) +#define CPG_FRQCR_SHIFT_IFC (8) +#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) + +#define CPG_FRQCR2_SHIFT_GFC (0) +#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) + + +#define CPG_STBCR1_BIT_STBY (0x80u) +#define CPG_STBCR1_BIT_DEEP (0x40u) +#define CPG_STBCR2_BIT_HIZ (0x80u) +#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ +#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ +#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ +#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ +#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ +#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ +#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ +#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ +#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ +#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ +#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ +#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ +#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ +#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ +#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ +#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ +#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ +#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ +#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ +#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ +#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ +#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ +#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ +#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ +#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */ +#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ +#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ +#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ +#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */ +#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */ +#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ +#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ +#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ +#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ +#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */ +#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ +#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ +#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ +#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ +#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ +#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ +#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ +#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ +#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ +#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ +#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ +#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ +#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ +#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ +#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ +#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ +#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ +#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ +#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ +#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ +#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ +#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ +#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ +#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ +#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ +#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ +#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ +#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ +#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ +#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ +#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ +#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ +#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ +#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ +#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ +#define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */ +#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ +#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ +#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ +#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ +#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ +#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ +#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ +#define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */ +#define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */ +#define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */ +#define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */ +#define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */ +#define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */ +#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ +#define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */ +#define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */ +#define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */ +#define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */ +#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ +#define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */ +#define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */ +#define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */ +#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ +#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ +#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ +#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ +#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ +#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ +#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ +#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ +#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ +#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ +#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ +#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ +#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ +#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ + +/*@}*/ /* end of group Renesas_RZ_A1_CPG */ + +/******************************************************************************/ +/* GPIO Settings */ +/******************************************************************************/ +/** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions + @{ +*/ + +#define GPIO_BIT_N0 (1u << 0) +#define GPIO_BIT_N1 (1u << 1) +#define GPIO_BIT_N2 (1u << 2) +#define GPIO_BIT_N3 (1u << 3) +#define GPIO_BIT_N4 (1u << 4) +#define GPIO_BIT_N5 (1u << 5) +#define GPIO_BIT_N6 (1u << 6) +#define GPIO_BIT_N7 (1u << 7) +#define GPIO_BIT_N8 (1u << 8) +#define GPIO_BIT_N9 (1u << 9) +#define GPIO_BIT_N10 (1u << 10) +#define GPIO_BIT_N11 (1u << 11) +#define GPIO_BIT_N12 (1u << 12) +#define GPIO_BIT_N13 (1u << 13) +#define GPIO_BIT_N14 (1u << 14) +#define GPIO_BIT_N15 (1u << 15) + + +#define MD_BOOT10_MASK (0x3) + +#define MD_BOOT10_BM0 (0x0) +#define MD_BOOT10_BM1 (0x2) +#define MD_BOOT10_BM3 (0x1) +#define MD_BOOT10_BM4_5 (0x3) + +#define MD_CLK (1u << 2) +#define MD_CLKS (1u << 3) + +/*@}*/ /* end of group Renesas_RZ_A1_GPIO */ + +#ifdef __cplusplus +} +#endif + +#endif // __MBRZA1H_H__ diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.c new file mode 100644 index 0000000000..7468a862fe --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.c @@ -0,0 +1,261 @@ +/**************************************************************************//** +* @file RZ_A1_Init.c +* $Rev: 624 $ +* $Date:: 2013-04-24 13:37:48 +0900#$ +* @brief RZ_A1 Initialize +******************************************************************************/ + +/* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved */ + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include "MBRZA1H.h" +#include "RZ_A1_Init.h" + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ +#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040) +#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040) + +#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu) + +/****************************************************************************** +Imported global variables and functions (from other files) +******************************************************************************/ + +/****************************************************************************** +Exported global variables and functions (to be accessed by other files) +******************************************************************************/ + +/****************************************************************************** +Private global variables and functions +******************************************************************************/ + +/**************************************************************************//** +* Function Name: RZ_A1_SetSramWriteEnable +* @brief Initialize Board settings +* +* Description:
+* Set SRAM write enable +* @param none +* @retval none +******************************************************************************/ +void RZ_A1_SetSramWriteEnable(void) +{ + /* Enable SRAM write access */ + CPG.SYSCR3 = 0x0F; + + return; +} + +/**************************************************************************//** +* Function Name: RZ_A1_InitClock +* @brief Initialize Board settings +* +* Description:
+* Initialize Clock +* @param none +* @retval none +******************************************************************************/ +void RZ_A1_InitClock(void) +{ + /* Cancel L2C standby status before clock change */ + L2CREG15_POWER_CTRL = 0x00000001; + + /* Clock settings */ + /* ClockMode0 */ + CPG.FRQCR = 0x1035; /* CPU Clock =399.99MHz */ + CPG.FRQCR2 = 0x0001; /* G Clock =266.66MHz */ + + return; +} + +/**************************************************************************//** +* Function Name: RZ_A1_IsClockMode0 +* @brief Query Clock Mode +* +* Description:
+* Answer ClockMode0 or not +* @param none +* @retval true : clock mode 0 +* @retval false : clock mode 1 +******************************************************************************/ +int RZ_A1_IsClockMode0(void) +{ + /* ClockMode0 */ + return true; +} + +/**************************************************************************//** +* Function Name: RZ_A1_InitBus +* @brief Initialize Bus +* +* Description:
+* Initialize CS0-CS3 pin and access timing +* @param none +* @retval none +******************************************************************************/ +void RZ_A1_InitBus(void) +{ + /***********************************************************************/ + /* Set pin alternative mode of NOR_FLASH(CS0, CS1) and SDRAM(CS2, CS3) */ + /***********************************************************************/ + + /* PORT9 partly set to Alternative Mode 1 + P9_1(A25), P9_0(A24) + */ + GPIO.PIBC9 &= ~(uint16_t)0x0003u; + GPIO.PBDC9 &= ~(uint16_t)0x0003u; + GPIO.PM9 |= (uint16_t)0x0003u; + GPIO.PMC9 &= ~(uint16_t)0x0003u; + GPIO.PIPC9 &= ~(uint16_t)0x0003u; + + GPIO.PBDC9 &= ~(uint16_t)0x0003u; + GPIO.PFC9 &= ~(uint16_t)0x0003u; + GPIO.PFCE9 &= ~(uint16_t)0x0003u; + GPIO.PFCAE9 &= ~(uint16_t)0x0003u; + + GPIO.PIPC9 |= (uint16_t)0x0003u; + GPIO.PMC9 |= (uint16_t)0x0003u; + + /* PORT8 fully set to Alternative Mode 1 + P8_15(A23), P8_14(A22), P8_13(A21), P8_12(A20), + P8_11(A19), P8_10(A18), P8_9(A17), P8_8(A16), + P8_7(A15), P8_6(A14), P8_5(A13), P8_4(A12), + P8_3(A11), P8_2(A10), P8_1(A9), P8_0(A8), + */ + GPIO.PIBC8 = 0x0000u; + GPIO.PBDC8 = 0x0000u; + GPIO.PM8 = 0xffffu; + GPIO.PMC8 = 0x0000u; + GPIO.PIPC8 = 0x0000u; + + GPIO.PBDC8 = 0x0000u; + GPIO.PFC8 = 0x0000u; + GPIO.PFCE8 = 0x0000u; + GPIO.PFCAE8 = 0x0000u; + + GPIO.PIPC8 = 0xffffu; + GPIO.PMC8 = 0xffffu; + + /* PORT7 fully set to Alternative Mode 1 + P7_15(A7), P7_14(A6), P7_13(A5), P7_12(A4), + P7_11(A3), P7_10(A2), P7_9(A1), P7_8(RD#), + P7_7(DQMLU#), P7_6(WE#0/DQMLL#), P7_5(RD/WR#), P7_4(CKE), + P7_3(CAS#), P7_2(RAS#), P7_1(CS3#), P7_0(CS0#) + */ + GPIO.PIBC7 = 0x0000u; + GPIO.PBDC7 = 0x0000u; + GPIO.PM7 = 0xffffu; + GPIO.PMC7 = 0x0000u; + GPIO.PIPC7 = 0x0000u; + + GPIO.PBDC7 = 0x0000u; + GPIO.PFC7 = 0x0000u; + GPIO.PFCE7 = 0x0000u; + GPIO.PFCAE7 = 0x0000u; + + GPIO.PIPC7 = 0xffffu; + GPIO.PMC7 = 0xffffu; + + /* PORT6 fully set to Alternative Mode 1 + P6_15(D15), P6_14(D14), P6_13(D13), P6_12(D12), + P6_11(D11), P6_10(D10), P6_9(D9), P6_8(D8), + P6_7(D7), P6_6(D6), P6_5(D5), P6_4(D4), + P6_3(D3), P6_2(D2), P6_1(D1), P6_0(D0) + Alternative Mode 1 + */ + GPIO.PIBC6 = 0x0000u; + GPIO.PBDC6 = 0x0000u; + GPIO.PM6 = 0xffffu; + GPIO.PMC6 = 0x0000u; + GPIO.PIPC6 = 0x0000u; + + GPIO.PBDC6 = 0xffffu; + GPIO.PFC6 = 0x0000u; + GPIO.PFCE6 = 0x0000u; + GPIO.PFCAE6 = 0x0000u; + + GPIO.PIPC6 = 0xffffu; + GPIO.PMC6 = 0xffffu; + + /* PORT5 partly set to Alternative Mode 6 + P5_8(CS2#), + */ + GPIO.PIBC5 &= ~(uint16_t)0x0100u; + GPIO.PBDC5 &= ~(uint16_t)0x0100u; + GPIO.PM5 |= (uint16_t)0x0100u; + GPIO.PMC5 &= ~(uint16_t)0x0100u; + GPIO.PIPC5 &= ~(uint16_t)0x0100u; + + GPIO.PBDC5 &= ~(uint16_t)0x0100u; + GPIO.PFC5 |= (uint16_t)0x0100u; + GPIO.PFCE5 &= ~(uint16_t)0x0100u; + GPIO.PFCAE5 |= (uint16_t)0x0100u; + + GPIO.PIPC5 |= (uint16_t)0x0100u; + GPIO.PMC5 |= (uint16_t)0x0100u; + + /* PORT3 partly set to Alternative Mode 7 + P3_7(CS1#), + */ + GPIO.PIBC3 &= ~(uint16_t)0x0080u; + GPIO.PBDC3 &= ~(uint16_t)0x0080u; + GPIO.PM3 |= (uint16_t)0x0080u; + GPIO.PMC3 &= ~(uint16_t)0x0080u; + GPIO.PIPC3 &= ~(uint16_t)0x0080u; + + GPIO.PBDC3 &= ~(uint16_t)0x0080u; + GPIO.PFC3 &= ~(uint16_t)0x0080u; + GPIO.PFCE3 |= (uint16_t)0x0080u; + GPIO.PFCAE3 |= (uint16_t)0x0080u; + + GPIO.PIPC3 |= (uint16_t)0x0080u; + GPIO.PMC3 |= (uint16_t)0x0080u; + + /***********************************************************************/ + /* Set bus access timing of NOR_FLASH(CS0, CS1) and SDRAM(CS2, CS3) */ + /***********************************************************************/ + + /* CSn Bus Control Register */ + BSC.CS0BCR = 0x10000c00;/* IWW=001b(1cyc),TYPE=000b(Normal),BSZ=10b(16bit)*/ + BSC.CS1BCR = 0x10000c00;/* IWW=001b(1cyc),TYPE=000b(Normal),BSZ=10b(16bit)*/ + BSC.CS2BCR = 0x00004c00;/* TYPE=100b(SDRAM), BSZ=10b(16bit) */ + BSC.CS3BCR = 0x00004c00;/* TYPE=100b(SDRAM), BSZ=10b(16bit) */ + + /* CS0 Wait Control Register(Normal type) */ + /* BAS=0b SW=01b(1.5cyc) WR=0110b(6cyc) WM=1b(ignore) HW=00b(0.5cyc) */ + BSC.CS0WCR = 0x00000b40; + /* CS1 Wait Control Register(Normal type) */ + /* BAS=0b SW=01b(1.5cyc) WR=0110b(6cyc) WM=1b(ignore) HW=00b(0.5cyc) */ + BSC.CS1WCR = 0x00000b40; + + /* CS2,3 Wait Control Register(SDRAM type) */ + BSC.CS2WCR = 0x00000480;/* A2CL=01b 2cycle */ + BSC.CS3WCR = 0x00002492;/* WTRP=01b 1cycle, WTRCD=01b 1cycle, A3CL=01b 2cycle, TRWL=10b 2cycle, WTRC=10b 5cycle */ + + /* SDRAM Control Register */ + BSC.SDCR = 0x00120812; + + /* Refresh Timer Constant Register */ + BSC.RTCOR = 0xa55a0020; + + /* Refresh Timer Control Status Register */ + BSC.RTCSR = 0xa55a0010; + + /* Write SDRAM Mode Register */ + CS2_SDRAM_MODE_16BIT_CAS2_BR_BW = 0x0000; + CS3_SDRAM_MODE_16BIT_CAS2_BR_BW = 0x0000; + + return; +} + +/****************************************************************************** +End of file +******************************************************************************/ diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.h new file mode 100644 index 0000000000..5ed63b71da --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.h @@ -0,0 +1,51 @@ +/**************************************************************************//** +* @file RZ_A1_Init.h +* $Rev: 531 $ +* $Date:: 2013-04-16 13:07:35 +0900#$ +* @brief RZ_A1 Initialize +******************************************************************************/ + +/* Copyright (C) 2013 Renesas Electronics Corporation. All rights reserved */ + +#ifndef RZ_A1_INIT_H +#define RZ_A1_INIT_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include +#include +#include "iodefine.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + +/****************************************************************************** +Macro definitions +******************************************************************************/ + +/****************************************************************************** +Variable Externs +******************************************************************************/ + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + +void RZ_A1_SetSramWriteEnable(void); +void RZ_A1_InitClock(void); +int RZ_A1_IsClockMode0(void); +void RZ_A1_InitBus(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* RZ_A1_INIT_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct new file mode 100644 index 0000000000..8e17c2bcf8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/MBRZA1H.sct @@ -0,0 +1,50 @@ + + +LOAD_TTB 0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM +{ + TTB +0 EMPTY 0x4000 + { } ; Level-1 Translation Table for MMU +} + +SFLASH_BOOT 0x18000000 (0x8000) +{ + BOOT_LOADER_BEGIN 0x18000000 FIXED + { + * ( BOOT_LOADER ) + } + +} + +SFLASH 0x18008000 (0x08000000-0x8000) +{ + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; S-Flash ROM : Executable cached region + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + VECTORS 0x18008000 FIXED + { + * (RESET, +FIRST) ; Vector table and other (assembler) startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + } + + RO_DATA +0 ALIGN 0x00100000 FIXED + { * (+RO-DATA) } ; Application RO data (.constdata) + + RW_DATA 0x20600000 0x00100000 ; Page 1 of On-Chip Large-Capacity RAM (0x20060000 to 0x206FFFFF) + { * (+RW) } ; Application RW data (.data) + + ZI_DATA 0x20100000 0x00100000 ; Page 1 of On-Chip Large-Capacity RAM (0x20010000 to 0x201FFFFF) + { * (+ZI) } ; Application ZI data (.bss) + + RW_DATA_NC 0x60900000 0x00100000 + { * (NC_DATA) } ; Application RW data Non cached area + + ZI_DATA_NC +0 + { * (NC_BSS) } ; Application ZI data Non cached area + + ;HEAP 0x90000000 + ;{ * (HEAP) } +} + + diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/startup_MBRZA1H.s b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/startup_MBRZA1H.s new file mode 100644 index 0000000000..1102ed37fe --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_ARM_STD/startup_MBRZA1H.s @@ -0,0 +1,454 @@ +;/***************************************************************************** +; * @file: startup_MBRZA1H.s +; * @purpose: CMSIS Cortex-A9 Core Device Startup File +; * for the NXP MBRZA1H Device Series +; * @version: V1.02, modified for mbed +; * @date: 27. July 2009, modified 3rd Aug 2009 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2009 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + +GICI_BASE EQU 0xe8202000 +ICCIAR_OFFSET EQU 0x0000000C +ICCEOIR_OFFSET EQU 0x00000010 +ICCHPIR_OFFSET EQU 0x00000018 + +GICD_BASE EQU 0xe8201000 +ICDISER0_OFFSET EQU 0x00000100 +ICDICER0_OFFSET EQU 0x00000180 +ICDISPR0_OFFSET EQU 0x00000200 +ICDABR0_OFFSET EQU 0x00000300 +ICDIPR0_OFFSET EQU 0x00000400 + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled +T_Bit EQU 0x20 ; when T bit is set, core is in Thumb state + +GIC_ERRATA_CHECK_1 EQU 0x000003FE +GIC_ERRATA_CHECK_2 EQU 0x000003FF + + +Sect_Normal EQU 0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +Sect_Normal_Cod EQU 0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +Sect_Normal_RO EQU 0x0000dc16 ;as Sect_Normal_Cod, but not executable +Sect_Normal_RW EQU 0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable +Sect_SO EQU 0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 +Sect_Device_RO EQU 0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0 +Sect_Device_RW EQU 0x00000c12 ;as Sect_Device_RO, but writeable +Sect_Fault EQU 0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored) + +RAM_BASE EQU 0x80000000 +VRAM_BASE EQU 0x18000000 +SRAM_BASE EQU 0x2e000000 +ETHERNET EQU 0x1a000000 +CS3_PERIPHERAL_BASE EQU 0x1c000000 + +; Stack Configuration +; Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8> +; + +UND_Stack_Size EQU 0x00000100 +SVC_Stack_Size EQU 0x00000100 +ABT_Stack_Size EQU 0x00000100 +FIQ_Stack_Size EQU 0x00000000 +IRQ_Stack_Size EQU 0x00000100 +USR_Stack_Size EQU 0x00000100 + +ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ + FIQ_Stack_Size + IRQ_Stack_Size) + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE USR_Stack_Size +__initial_sp SPACE ISR_Stack_Size + +Stack_Top + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00080000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + ARM + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, CODE, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors LDR PC, Reset_Addr ; Address of Reset Handler + LDR PC, Undef_Addr ; Address of Undef Handler + LDR PC, SVC_Addr ; Address of SVC Handler + LDR PC, PAbt_Addr ; Address of Prefetch Abort Handler + LDR PC, DAbt_Addr ; Address of Data Abort Handler + NOP ; Reserved Vector + LDR PC, IRQ_Addr ; Address of IRQ Handler + LDR PC, FIQ_Addr ; Address of FIQ Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +Reset_Addr DCD Reset_Handler +Undef_Addr DCD Undef_Handler +SVC_Addr DCD SVC_Handler +PAbt_Addr DCD PAbt_Handler +DAbt_Addr DCD DAbt_Handler +IRQ_Addr DCD IRQ_Handler +FIQ_Addr DCD FIQ_Handler + + AREA |.text|, CODE, READONLY + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT InitMemorySubsystem + IMPORT __main + IMPORT RZ_A1_SetSramWriteEnable + + ; Put any cores other than 0 to sleep + MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR + ANDS R0, R0, #3 +goToSleep + WFINE + BNE goToSleep + +; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. +; Enables Full Access i.e. in both privileged and non privileged modes + MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR) + ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11 + MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR) + ISB + +; Switch on the VFP and NEON hardware + MOV r0, #0x40000000 + VMSR FPEXC, r0 ; Write FPEXC register, EN bit set + + MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register + BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache + BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache + BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU + BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction + BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs + MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register + ISB + +; Set Vector Base Address Register (VBAR) to point to this application's vector table + LDR R0, =__Vectors + MCR p15, 0, R0, c12, c0, 0 + +; Setup Stack for each exceptional mode + LDR R0, =Stack_Top + +; Enter Undefined Instruction Mode and set its Stack Pointer + MSR CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #UND_Stack_Size + +; Enter Abort Mode and set its Stack Pointer + MSR CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #ABT_Stack_Size + +; Enter FIQ Mode and set its Stack Pointer + MSR CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #FIQ_Stack_Size + +; Enter IRQ Mode and set its Stack Pointer + MSR CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit + MOV SP, R0 + SUB R0, R0, #IRQ_Stack_Size + +; Enter Supervisor Mode and set its Stack Pointer + MSR CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit + MOV SP, R0 + +; Enter System Mode to complete initialization and enter kernel + MSR CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit + MOV SP, R0 + + ISB + + LDR R0, =RZ_A1_SetSramWriteEnable + BLX R0 + + IMPORT create_translation_table + BL create_translation_table + +; USR/SYS stack pointer will be set during kernel init + + LDR R0, =SystemInit + BLX R0 + LDR R0, =InitMemorySubsystem + BLX R0 + LDR R0, =__main + BLX R0 + + ENDP + +Undef_Handler\ + PROC + EXPORT Undef_Handler [WEAK] + IMPORT CUndefHandler + SRSFD SP!, #Mode_UND + PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack + + MRS R0, SPSR + TST R0, #T_Bit ; Check mode + MOVEQ R1, #4 ; R1 = 4 ARM mode + MOVNE R1, #2 ; R1 = 2 Thumb mode + SUB R0, LR, R1 + LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction + BEQ undef_cont + + ;Thumb instruction + ;Determine if it is a 32-bit Thumb instruction + LDRH R0, [R0] + MOV R2, #0x1c + CMP R2, R0, LSR #11 + BHS undef_cont ;16-bit Thumb instruction + + ;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. + LDRH R2, [LR] + ORR R0, R2, R0, LSL #16 +undef_cont + MOV R2, LR ; Set LR to third argument + +; AND R12, SP, #4 ; Ensure stack is 8-byte aligned + MOV R3, SP ; Ensure stack is 8-byte aligned + AND R12, R3, #4 + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + ;R0 Offending instruction + ;R1 =2 (Thumb) or =4 (ARM) + BL CUndefHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry + SUB LR, LR, R0 + LDR R0, [SP, #28] ; Restore stacked SPSR + MSR SPSR_CXSF, R0 + POP {R0-R4, R12} ; Restore stacked APCS registers + ADD SP, SP, #8 ; Adjust SP for already-restored banked registers + MOVS PC, LR + ENDP + +PAbt_Handler\ + PROC + EXPORT PAbt_Handler [WEAK] + IMPORT CPAbtHandler + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack + PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack + MRC p15, 0, R0, c5, c0, 1 ; IFSR + MRC p15, 0, R1, c6, c0, 2 ; IFAR + + MOV R2, LR ; Set LR to third argument + +; AND R12, SP, #4 ; Ensure stack is 8-byte aligned + MOV R3, SP ; Ensure stack is 8-byte aligned + AND R12, R3, #4 + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + BL CPAbtHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R4, R12} ; Restore stack APCS registers + RFEFD SP! ; Return from exception + ENDP + + +DAbt_Handler\ + PROC + EXPORT DAbt_Handler [WEAK] + IMPORT CDAbtHandler + SUB LR, LR, #8 ; Pre-adjust LR + SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack + PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack + CLREX ; State of exclusive monitors unknown after taken data abort + MRC p15, 0, R0, c5, c0, 0 ; DFSR + MRC p15, 0, R1, c6, c0, 0 ; DFAR + + MOV R2, LR ; Set LR to third argument + +; AND R12, SP, #4 ; Ensure stack is 8-byte aligned + MOV R3, SP ; Ensure stack is 8-byte aligned + AND R12, R3, #4 + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR + + BL CDAbtHandler + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R4, R12} ; Restore stacked APCS registers + RFEFD SP! ; Return from exception + ENDP + +FIQ_Handler\ + PROC + EXPORT FIQ_Handler [WEAK] + ;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, + ;; so if a real FIQ Handler is implemented, this will be needed before returning: + ;; LDR R1, =GICI_BASE + ;; LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 + B . + ENDP + +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +IRQ_Handler\ + PROC + EXPORT IRQ_Handler [WEAK] + IMPORT IRQCount + IMPORT IRQTable + IMPORT IRQNestLevel + + ;prologue + SUB LR, LR, #4 ; Pre-adjust LR + SRSFD SP!, #Mode_SVC ; Save LR_IRQ and SPRS_IRQ to SVC mode stack + CPS #Mode_SVC ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL + PUSH {R0-R3, R12} ; Save remaining APCS corruptible registers to SVC stack + +; AND R1, SP, #4 ; Ensure stack is 8-byte aligned + MOV R3, SP ; Ensure stack is 8-byte aligned + AND R1, R3, #4 + SUB SP, SP, R1 ; Adjust stack + PUSH {R1, LR} ; Store stack adjustment and LR_SVC to SVC stack + + LDR R0, =IRQNestLevel ; Get address of nesting counter + LDR R1, [R0] + ADD R1, R1, #1 ; Increment nesting counter + STR R1, [R0] + + ;identify and acknowledge interrupt + LDR R1, =GICI_BASE + LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 + LDR R0, [R1, #ICCIAR_OFFSET] ; Read ICCIAR (GIC CPU Interface register) + DSB ; Ensure that interrupt acknowledge completes before re-enabling interrupts + + ; Workaround GIC 390 errata 733075 + ; If the ID is not 0, then service the interrupt as normal. + ; If the ID is 0 and active, then service interrupt ID 0 as normal. + ; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it + ; with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. + ; + LDR R2, =GICD_BASE + LDR R3, =GIC_ERRATA_CHECK_1 + CMP R0, R3 + BEQ unlock_cpu + LDR R3, =GIC_ERRATA_CHECK_2 + CMP R0, R3 + BEQ unlock_cpu + CMP R0, #0 + BNE int_active ; If the ID is not 0, then service the interrupt + LDR R3, [R2, #ICDABR0_OFFSET] ; Get the interrupt state + TST R3, #1 + BNE int_active ; If active, then service the interrupt +unlock_cpu + LDR R3, [R2, #ICDIPR0_OFFSET] ; Not active, so unlock the CPU interface + STR R3, [R2, #ICDIPR0_OFFSET] ; with a dummy write + DSB ; Ensure the write completes before continuing + B ret_irq ; Do not service the spurious interrupt + ; End workaround + +int_active + LDR R2, =IRQCount ; Read number of IRQs + LDR R2, [R2] + CMP R0, R2 ; Clean up and return if no handler + BHS ret_irq ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling + LDR R2, =IRQTable ; Get address of handler + LDR R2, [R2, R0, LSL #2] + CMP R2, #0 ; Clean up and return if handler address is 0 + BEQ ret_irq + PUSH {R0,R1} + + CPSIE i ; Now safe to re-enable interrupts + BLX R2 ; Call handler. R0 will be IRQ number + CPSID i ; Disable interrupts again + + ;write EOIR (GIC CPU Interface register) + POP {R0,R1} + DSB ; Ensure that interrupt source is cleared before we write the EOIR +ret_irq + ;epilogue + STR R0, [R1, #ICCEOIR_OFFSET] + + LDR R0, =IRQNestLevel ; Get address of nesting counter + LDR R1, [R0] + SUB R1, R1, #1 ; Decrement nesting counter + STR R1, [R0] + + POP {R1, LR} ; Get stack adjustment and restore LR_SVC + ADD SP, SP, R1 ; Unadjust stack + + POP {R0-R3,R12} ; Restore stacked APCS registers + RFEFD SP! ; Return from exception + ENDP + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + USR_Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ENDIF + + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld new file mode 100644 index 0000000000..c76a57017b --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/RZA1H.ld @@ -0,0 +1,155 @@ +/* Linker script for mbed LPC1768 */ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x20000000, LENGTH = 512K + RAM (rwx) : ORIGIN = 0x20080000, LENGTH = (1M) + + USB_RAM(rwx) : ORIGIN = 0x20180000, LENGTH = 16K + ETH_RAM(rwx) : ORIGIN = 0x20280000, LENGTH = 16K +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + Image$$RW_RAM1$$Base = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE (__fini_array_end = .); + + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + + .bss : + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + Image$$RW_RAM1$$ZI$$Limit = . ; + } > RAM + + + .heap : + { + __end__ = .; + end = __end__; + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy : + { + *(.stack) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + +} diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/irqfiq_handler.s b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/irqfiq_handler.s new file mode 100644 index 0000000000..0428daba25 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/irqfiq_handler.s @@ -0,0 +1,125 @@ +@/******************************************************************************* +@* DISCLAIMER +@* This software is supplied by Renesas Electronics Corporation and is only +@* intended for use with Renesas products. No other uses are authorized. This +@* software is owned by Renesas Electronics Corporation and is protected under +@* all applicable laws, including copyright laws. +@* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +@* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +@* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +@* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +@* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +@* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +@* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +@* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +@* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +@* Renesas reserves the right, without notice, to make changes to this software +@* and to discontinue the availability of this software. By using this software, +@* you agree to the additional terms and conditions found by accessing the +@* following link: +@* http://www.renesas.com/disclaimer +@* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +@*******************************************************************************/ +@/******************************************************************************* +@* File Name : irqfiq_handler.s +@* $Rev: 823 $ +@* $Date:: 2014-04-21 16:45:10 +0900#$ +@* Description : IRQ, FIQ handler +@*******************************************************************************/ + + +@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs + .EQU SYS_MODE, 0x1f + +@ INTC ICCIAR register address + .EQU INTC_ICCIAR_ADDR, 0xE820200C +@ INTC ICCEOIR register address + .EQU INTC_ICCEOIR_ADDR, 0xE8202010 +@ INTC ICDABR0 register address + .EQU INTC_ICDABR0_ADDR, 0xE8201300 +@ INTC ICDIPR0 register address + .EQU INTC_ICDIPR0_ADDR, 0xE8201400 +@ INTC ICCHPIR register address + .EQU INTC_ICCHPIR_ADDR, 0xE8202018 + +@================================================================== +@ Entry point for the FIQ handler +@================================================================== +@ PRESERVE8 +@ .section IRQ_FIQ_HANDLER, #execinstr + .text + .arm + +@ IMPORT FiqHandler_Interrupt +@ IMPORT INTC_Handler_Interrupt + + .global irq_handler + .global fiq_handler + + +@****************************************************************************** +@ Function Name : fiq_handler +@ Description : This function is the assembler function executed when the FIQ +@ : interrupt is generated. +@****************************************************************************** +fiq_handler: + B FiqHandler_Interrupt + + +@****************************************************************************** +@ Function Name : irq_handler +@ Description : This function is the assembler function executed when the IRQ +@ : interrupt is generated. After saving the stack pointer and +@ : the stack for general registers and obtaining the INTC interrupt +@ : source ID, calls the IntcIrqHandler_interrupt function written +@ : in C language to execute the processing for the INTC interrupt +@ : handler corresponding to the interrupt source ID. +@ : After the INTC interrupt handler processing, restores +@ : the stack pointer and the general registers from the stack and +@ : returns from the IRQ interrupt processing. +@****************************************************************************** +irq_handler: + SUB lr, lr, #4 + SRSDB sp!, #SYS_MODE @;; Store LR_irq and SPSR_irq in system mode stack + CPS #SYS_MODE @;; Switch to system mode + PUSH {r0-r3, r12} @;; Store other AAPCS registers + LDR r1, =INTC_ICCHPIR_ADDR + LDR r3, [r1] + LDR r2, =INTC_ICCIAR_ADDR + LDR r0, [r2] @;; Read ICCIAR + LDR r2, =0x000003FF + AND r3, r0, r2 + CMP r3, r2 + BEQ end_of_handler + CMP r3, #0 + BNE int_active + LDR r2, =INTC_ICDABR0_ADDR + LDR r3, [r2] + AND r3, r3, #0x00000001 + CMP r3, #0 + BNE int_active + LDR r2, =INTC_ICDIPR0_ADDR + LDR r3, [r2] + STR r3, [r2] + B end_of_handler +int_active: + PUSH {r0} + MOV r1, sp @;; + AND r1, r1, #4 @;; Make alignment for stack + SUB sp, sp, r1 @;; + PUSH {r1, lr} + BL INTC_Handler_Interrupt @;; First argument(r0) = ICCIAR read value + POP {r1, lr} + ADD sp, sp, r1 + POP {r0} + LDR r2, =INTC_ICCEOIR_ADDR + STR r0, [r2] @;; Write ICCEOIR +end_of_handler: + POP {r0-r3, r12} @;; Restore registers + RFEIA sp! @;; Return from system mode stack using RFE + +Literals3: + .LTORG + + + .END diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s new file mode 100644 index 0000000000..d0c7bae2d9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s @@ -0,0 +1,247 @@ +/* File: startup_ARMCM3.s + * Purpose: startup file for Cortex-M3/M4 devices. Should use with + * GNU Tools for ARM Embedded Processors + * Version: V1.1 + * Date: 17 June 2011 + * + * Copyright (C) 2011 ARM Limited. All rights reserved. + * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + */ + .syntax unified + +@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs + .equ USR_MODE, 0x10 + .equ FIQ_MODE, 0x11 + .equ IRQ_MODE, 0x12 + .equ SVC_MODE, 0x13 + .equ ABT_MODE, 0x17 + .equ UND_MODE, 0x1b + .equ SYS_MODE, 0x1f + .equ Thum_bit, 0x20 @ CPSR/SPSR Thumb bit + +/* Memory Model + The HEAP starts at the end of the DATA section and grows upward. + + The STACK starts at the end of the RAM and grows downward. + + The HEAP and stack STACK are only checked at compile time: + (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE + + This is just a check for the bare minimum for the Heap+Stack area before + aborting compilation, it is not the run time limit: + Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 + */ + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop +__AStackLimit: + .space Stack_Size + .size __AStackLimit, . - __AStackLimit +__AStackTop: + .size __AStackTop, . - __AStackTop +__BStackLimit: + .space Stack_Size + .size __BStackLimit, . - __StackLimit +__BStackTop: + .size __BStackTop, . - __BStackTop +__CStackLimit: + .space Stack_Size + .size __CStackLimit, . - __CStackLimit +__CStackTop: + .size __CStackTop, . - __CStackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x800 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long 0xe59ff018 // 0x00 + .long 0xe59ff018 // 0x04 + .long 0xe59ff018 // 0x08 + .long 0xe59ff018 // 0x0c + .long 0xe59ff018 // 0x10 + .long 0xe59ff018 // 0x14 + .long 0xe59ff018 // 0x18 + .long 0xe59ff018 // 0x1c + + .long Reset_Handler /* 0x20 */ + .long undefinedInstruction /* 0x24 */ + .long softwareInterrupt /* 0x28 */ + .long prefetchAboart /* 0x2c */ + .long dataAbort /* 0x30 */ + .long 0 /* Reserved */ + .long irq_handler /* IRQ */ + .long fiq_handler /* FIQ */ + + + .size __isr_vector, . - __isr_vector + + .text +// .thumb +// .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * _etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + mrc p15, 0, r0, c1, c0, 0 @;; Read CP15 System Control register (SCTLR) + bic r0, r0, #(0x1 << 12) @;; Clear I bit 12 to disable I Cache + bic r0, r0, #(0x1 << 2) @;; Clear C bit 2 to disable D Cache + bic r0, r0, #0x1 @;; Clear M bit 0 to disable MMU + mcr p15, 0, r0, c1, c0, 0 @;; Write value back to CP15 System Control register + + @;; SVC Mode(Default) + LDR sp, =__AStackTop + + CPS #IRQ_MODE @;; IRQ Mode + LDR sp, =__BStackTop + + CPS #FIQ_MODE @;; FIQ Mode + LDR sp, =__CStackTop + + @CPS #ABT_MODE @;; ABT Mode + @LDR sp, =__StackTop + + CPS #SYS_MODE @;; SYS Mode + +@; System mode Stack pointer is set up ARM_LIB_STACK in the __main()->__entry() + LDR sp, =__StackTop + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.Lflash_to_ram_loop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .Lflash_to_ram_loop + + ldr r0, =set_low_vector + blx r0 + ldr r0, =enable_VFP + blx r0 + + ldr r0, =SystemInit + blx r0 + ldr r0, =_start + bx r0 + +set_low_vector: + mrc p15, 0, r0, c1, c0, 0 + mov r1, #0xffffdfff + and r0, r1 + mcr p15, 0, r0, c1, c0, 0 + + mrc p15, 0, r0, c12, c0, 0 // vector set + mov r0, #0x20000000 + mcr p15, 0, r0, c12, c0, 0 // vector set + bx lr + +.equ VFPEnable, 0x40000000 +enable_VFP: + ;; + mrc p15, 0, r0, c1, c0, 2 ; + orr r0, r0, #(3 << 20) ; + orr r0, r0, #(3 << 22) ; + bic r0, r0, #(3 << 30) ; + mcr p15, 0, r0, c1, c0, 2 ; + isb ; + ;; + mov r0, #VFPEnable + vmsr fpexc, r0 + bx lr + ;; + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + def_default_handler undefinedInstruction /* 0x24 */ + def_default_handler softwareInterrupt /* 0x28 */ + def_default_handler prefetchAboart /* 0x2c */ + def_default_handler dataAbort /* 0x30 */ + def_default_handler Default_Handler /* --- */ + + .global __disable_irq + .global __enable_irq + + .global __disable_fiq + .global __enable_fiq + +__disable_irq: + mrs r0,apsr @ formerly cpsr + and r0,r0,#0x80 + cpsid i + bx lr + +__enable_irq: + cpsie i + bx lr + + +__disable_fiq: + cpsid f + bx lr + +__enable_fiq: + cpsie f + bx lr + + + + .end + diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis.h new file mode 100644 index 0000000000..0f9a540cdd --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/cmsis.h @@ -0,0 +1,12 @@ +/* mbed Microcontroller Library - CMSIS + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * A generic CMSIS include header, pulling in LPC1768 specifics + */ + +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H + +#include "MBRZA1H.h" + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/dev_drv.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/dev_drv.h new file mode 100644 index 0000000000..deb2ebbc13 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/dev_drv.h @@ -0,0 +1,85 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/****************************************************************************** +* File Name : dev_drv.h +* $Rev: 809 $ +* $Date:: 2014-04-09 15:06:36 +0900#$ +* Description : Device driver header +******************************************************************************/ +#ifndef DEV_DRV_H +#define DEV_DRV_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ + + +/****************************************************************************** +Typedef definitions +******************************************************************************/ + + +/****************************************************************************** +Macro definitions +******************************************************************************/ +/* ==== Arguments, Return values ==== */ +#define DEVDRV_SUCCESS (0) /* Success */ +#define DEVDRV_ERROR (-1) /* Failure */ + +/* ==== Flags ==== */ +#define DEVDRV_FLAG_OFF (0) /* Flag OFF */ +#define DEVDRV_FLAG_ON (1) /* Flag ON */ + +/* ==== Channels ==== */ +typedef enum devdrv_ch +{ + DEVDRV_CH_0, /* Channel 0 */ + DEVDRV_CH_1, /* Channel 1 */ + DEVDRV_CH_2, /* Channel 2 */ + DEVDRV_CH_3, /* Channel 3 */ + DEVDRV_CH_4, /* Channel 4 */ + DEVDRV_CH_5, /* Channel 5 */ + DEVDRV_CH_6, /* Channel 6 */ + DEVDRV_CH_7, /* Channel 7 */ + DEVDRV_CH_8, /* Channel 8 */ + DEVDRV_CH_9, /* Channel 9 */ + DEVDRV_CH_10, /* Channel 10 */ + DEVDRV_CH_11, /* Channel 11 */ + DEVDRV_CH_12, /* Channel 12 */ + DEVDRV_CH_13, /* Channel 13 */ + DEVDRV_CH_14, /* Channel 14 */ + DEVDRV_CH_15 /* Channel 15 */ +} devdrv_ch_t; + +/****************************************************************************** +Variable Externs +******************************************************************************/ + + +/****************************************************************************** +Functions Prototypes +******************************************************************************/ + +#endif /* DEV_DRV_H */ + +/* End of File */ diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.c new file mode 100644 index 0000000000..e33b11122d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.c @@ -0,0 +1,305 @@ +/**************************************************************************//** + * @file gic.c + * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version + * @date 19 Sept 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#include "MBRZA1H.h" + +#define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */ +#define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */ + +/* Globals for use of post-scatterloading code that must access GIC */ +const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE; +const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE; + +void GIC_EnableDistributor(void) +{ + GICDistributor->ICDDCR |= 1; //enable distributor +} + +void GIC_DisableDistributor(void) +{ + GICDistributor->ICDDCR &=~1; //disable distributor +} + +uint32_t GIC_DistributorInfo(void) +{ + return (uint32_t)(GICDistributor->ICDICTR); +} + +uint32_t GIC_DistributorImplementer(void) +{ + return (uint32_t)(GICDistributor->ICDIIDR); +} + +void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) +{ + volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); + field += IRQn % 4; + *field = (uint8_t)cpu_target & 0xf; +} + +void GIC_SetICDICFR (const uint32_t *ICDICFRn) +{ + uint32_t i, num_irq; + + //Get the maximum number of interrupts that the GIC supports + num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); + + for (i = 0; i < (num_irq/16); i++) + { + GICDistributor->ICDISPR[i] = *ICDICFRn++; + } +} + +uint32_t GIC_GetTarget(IRQn_Type IRQn) +{ + volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); + field += IRQn % 4; + return ((uint32_t)*field & 0xf); +} + +void GIC_EnableInterface(void) +{ + GICInterface->ICCICR |= 1; //enable interface +} + +void GIC_DisableInterface(void) +{ + GICInterface->ICCICR &=~1; //disable distributor +} + +IRQn_Type GIC_AcknowledgePending(void) +{ + return (IRQn_Type)(GICInterface->ICCIAR); +} + +void GIC_EndInterrupt(IRQn_Type IRQn) +{ + GICInterface->ICCEOIR = IRQn; +} + +void GIC_EnableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32); +} + +void GIC_DisableIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32); +} + +void GIC_SetPendingIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32); +} + +void GIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32); +} + +void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model) +{ + volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]); + int bit_shift = (IRQn % 16)<<1; + uint8_t save_byte; + + field += (bit_shift / 8); + bit_shift %= 8; + + save_byte = *field; + save_byte &= ((uint8_t)~(3u << bit_shift)); + + *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift); +} + +void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); + field += (IRQn % 4); + *field = (uint8_t)priority; +} + +uint32_t GIC_GetPriority(IRQn_Type IRQn) +{ + volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); + field += (IRQn % 4); + return (uint32_t)*field; +} + +void GIC_InterfacePriorityMask(uint32_t priority) +{ + GICInterface->ICCPMR = priority & 0xff; //set priority mask +} + +void GIC_SetBinaryPoint(uint32_t binary_point) +{ + GICInterface->ICCBPR = binary_point & 0x07; //set binary point +} + +uint32_t GIC_GetBinaryPoint(uint32_t binary_point) +{ + return (uint32_t)GICInterface->ICCBPR; +} + +uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) +{ + uint32_t pending, active; + + active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1; + pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1; + + return ((active<<1) | pending); +} + +void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) +{ + GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf); +} + +void GIC_DistInit(void) +{ + //IRQn_Type i; + uint32_t i; + uint32_t num_irq = 0; + uint32_t priority_field; + + //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableDistributor(); + //Get the maximum number of interrupts that the GIC supports + num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an ICDIPR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0, 0xff); + priority_field = GIC_GetPriority((IRQn_Type)0); + + for (i = 32; i < num_irq; i++) + { + //Disable all SPI the interrupts + GIC_DisableIRQ((IRQn_Type)i); + //Set level-sensitive and N-N model + //GIC_SetLevelModel(i, 0, 0); + //Set priority + GIC_SetPriority((IRQn_Type)i, priority_field/2); + //Set target list to "all cpus" + GIC_SetTarget((IRQn_Type)i, 0xff); + } + /* Set level-edge and 1-N model */ + /* GICDistributor->ICDICFR[ 0] is read only */ + GICDistributor->ICDICFR[ 1] = 0x00000055; + GICDistributor->ICDICFR[ 2] = 0xFFFD5555; + GICDistributor->ICDICFR[ 3] = 0x555FFFFF; + GICDistributor->ICDICFR[ 4] = 0x55555555; + GICDistributor->ICDICFR[ 5] = 0x55555555; + GICDistributor->ICDICFR[ 6] = 0x55555555; + GICDistributor->ICDICFR[ 7] = 0x55555555; + GICDistributor->ICDICFR[ 8] = 0x5555F555; + GICDistributor->ICDICFR[ 9] = 0x55555555; + GICDistributor->ICDICFR[10] = 0x55555555; + GICDistributor->ICDICFR[11] = 0xF5555555; + GICDistributor->ICDICFR[12] = 0xF555F555; + GICDistributor->ICDICFR[13] = 0x5555F555; + GICDistributor->ICDICFR[14] = 0x55555555; + GICDistributor->ICDICFR[15] = 0x55555555; + GICDistributor->ICDICFR[16] = 0x55555555; + GICDistributor->ICDICFR[17] = 0xFD555555; + GICDistributor->ICDICFR[18] = 0x55555557; + GICDistributor->ICDICFR[19] = 0x55555555; + GICDistributor->ICDICFR[20] = 0xFFD55555; + GICDistributor->ICDICFR[21] = 0x5F55557F; + GICDistributor->ICDICFR[22] = 0xFD55555F; + GICDistributor->ICDICFR[23] = 0x55555557; + GICDistributor->ICDICFR[24] = 0x55555555; + GICDistributor->ICDICFR[25] = 0x55555555; + GICDistributor->ICDICFR[26] = 0x55555555; + GICDistributor->ICDICFR[27] = 0x55555555; + GICDistributor->ICDICFR[28] = 0x55555555; + GICDistributor->ICDICFR[29] = 0x55555555; + GICDistributor->ICDICFR[30] = 0x55555555; + GICDistributor->ICDICFR[31] = 0x55555555; + GICDistributor->ICDICFR[32] = 0x55555555; + GICDistributor->ICDICFR[33] = 0x55555555; + + //Enable distributor + GIC_EnableDistributor(); +} + +void GIC_CPUInterfaceInit(void) +{ + IRQn_Type i; + uint32_t priority_field; + + //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, + //configuring all of the interrupts as Secure. + + //Disable interrupt forwarding + GIC_DisableInterface(); + + /* Priority level is implementation defined. + To determine the number of priority bits implemented write 0xFF to an ICDIPR + priority field and read back the value stored.*/ + GIC_SetPriority((IRQn_Type)0, 0xff); + priority_field = GIC_GetPriority((IRQn_Type)0); + + //SGI and PPI + for (i = (IRQn_Type)0; i < 32; i++) + { + //Set level-sensitive and N-N model for PPI + //if(i > 15) + //GIC_SetLevelModel(i, 0, 0); + //Disable SGI and PPI interrupts + GIC_DisableIRQ(i); + //Set priority + GIC_SetPriority(i, priority_field/2); + } + //Enable interface + GIC_EnableInterface(); + //Set binary point to 0 + GIC_SetBinaryPoint(0); + //Set priority mask + GIC_InterfacePriorityMask(0xff); +} + +void GIC_Enable(void) +{ + GIC_DistInit(); + GIC_CPUInterfaceInit(); //per CPU +} + diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.h new file mode 100644 index 0000000000..d4cbfd81ab --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/gic.h @@ -0,0 +1,316 @@ +/**************************************************************************//** + * @file gic.h + * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version + * @date 29 August 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef GIC_H_ +#define GIC_H_ + +/* IO definitions (access restrictions to peripheral registers) */ +/** +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) + */ +typedef struct +{ + __IO uint32_t ICDDCR; + __I uint32_t ICDICTR; + __I uint32_t ICDIIDR; + uint32_t RESERVED0[29]; + __IO uint32_t ICDISR[32]; + __IO uint32_t ICDISER[32]; + __IO uint32_t ICDICER[32]; + __IO uint32_t ICDISPR[32]; + __IO uint32_t ICDICPR[32]; + __I uint32_t ICDABR[32]; + uint32_t RESERVED1[32]; + __IO uint32_t ICDIPR[256]; + __IO uint32_t ICDIPTR[256]; + __IO uint32_t ICDICFR[64]; + uint32_t RESERVED2[128]; + __IO uint32_t ICDSGIR; +} GICDistributor_Type; + +/** \brief Structure type to access the Controller Interface (GICC) + */ +typedef struct +{ + __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register + __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register + __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register + __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register + __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register + __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register + __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register + __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register + + uint32_t RESERVED[55]; + + __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register +} GICInterface_Type; + +/*@} end of GICD */ + +/* ########################## GIC functions #################################### */ +/** \brief Functions that manage interrupts via the GIC. + @{ + */ + +/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface + + Enables the forwarding of pending interrupts to the CPU interfaces. + + */ +void GIC_EnableDistributor(void); + +/** \brief Disable Distributor + + Disables the forwarding of pending interrupts to the CPU interfaces. + + */ +void GIC_DisableDistributor(void); + +/** \brief Provides information about the configuration of the GIC. + Provides information about the configuration of the GIC. + - whether the GIC implements the Security Extensions + - the maximum number of interrupt IDs that the GIC supports + - the number of CPU interfaces implemented + - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). + + \return Distributor Information. + */ +uint32_t GIC_DistributorInfo(void); + +/** \brief Distributor Implementer Identification Register. + + Distributor Implementer Identification Register + + \return Implementer Information. + */ +uint32_t GIC_DistributorImplementer(void); + +/** \brief Set list of processors that the interrupt is sent to if it is asserted. + + The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. + This field stores the list of processors that the interrupt is sent to if it is asserted. + + \param [in] IRQn Interrupt number. + \param [in] target CPU target + */ +void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target); + +/** \brief Get list of processors that the interrupt is sent to if it is asserted. + + The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. + This field stores the list of processors that the interrupt is sent to if it is asserted. + + \param [in] IRQn Interrupt number. + \param [in] target CPU target +*/ +uint32_t GIC_GetTarget(IRQn_Type IRQn); + +/** \brief Enable Interface + + Enables the signalling of interrupts to the target processors. + + */ +void GIC_EnableInterface(void); + +/** \brief Disable Interface + + Disables the signalling of interrupts to the target processors. + + */ +void GIC_DisableInterface(void); + +/** \brief Acknowledge Interrupt + + The function acknowledges the highest priority pending interrupt and returns its IRQ number. + + \return Interrupt number + */ +IRQn_Type GIC_AcknowledgePending(void); + +/** \brief End Interrupt + + The function writes the end of interrupt register, indicating that handling of the interrupt is complete. + + \param [in] IRQn Interrupt number. + */ +void GIC_EndInterrupt(IRQn_Type IRQn); + + +/** \brief Enable Interrupt + + Set-enable bit for each interrupt supported by the GIC. + + \param [in] IRQn External interrupt number. + */ +void GIC_EnableIRQ(IRQn_Type IRQn); + +/** \brief Disable Interrupt + + Clear-enable bit for each interrupt supported by the GIC. + + \param [in] IRQn Number of the external interrupt to disable + */ +void GIC_DisableIRQ(IRQn_Type IRQn); + +/** \brief Set Pending Interrupt + + Set-pending bit for each interrupt supported by the GIC. + + \param [in] IRQn Interrupt number. + */ +void GIC_SetPendingIRQ(IRQn_Type IRQn); + +/** \brief Clear Pending Interrupt + + Clear-pending bit for each interrupt supported by the GIC + + \param [in] IRQn Number of the interrupt for clear pending + */ +void GIC_ClearPendingIRQ(IRQn_Type IRQn); + +/** \brief Int_config field for each interrupt supported by the GIC. + + This field identifies whether the corresponding interrupt is: + (1) edge-triggered or (0) level-sensitive + (1) 1-N model or (0) N-N model + + \param [in] IRQn Interrupt number. + \param [in] edge_level (1) edge-triggered or (0) level-sensitive + \param [in] model (1) 1-N model or (0) N-N model + */ +void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model); + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority); + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + */ +uint32_t GIC_GetPriority(IRQn_Type IRQn); + +/** \brief CPU Interface Priority Mask Register + + The priority mask level for the CPU interface. If the priority of an interrupt is higher than the + value indicated by this field, the interface signals the interrupt to the processor. + + \param [in] Mask. + */ +void GIC_InterfacePriorityMask(uint32_t priority); + +/** \brief Set the binary point. + + Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field. + + \param [in] Mask. + */ +void GIC_SetBinaryPoint(uint32_t binary_point); + +/** \brief Get the binary point. + + Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field. + + \return Binary point. + */ +uint32_t GIC_GetBinaryPoint(uint32_t binary_point); + +/** \brief Get Interrupt state. + + Get the interrupt state, whether pending and/or active + + \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active + */ +uint32_t GIC_GetIRQStatus(IRQn_Type IRQn); + +/** \brief Send Software Generated interrupt + + Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor. +GIC_InterfacePriorityMask + \param [in] IRQn The Interrupt ID of the SGI. + \param [in] target_list CPUTargetList + \param [in] filter_list TargetListFilter + */ +void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list); + +/** \brief API call to initialise the interrupt distributor + + API call to initialise the interrupt distributor + + */ +void GIC_DistInit(void); + +/** \brief API call to initialise the CPU interface + + API call to initialise the CPU interface + + */ +void GIC_CPUInterfaceInit(void); + +/** \brief API call to set the Interrupt Configuration Registers + + API call to initialise the Interrupt Configuration Registers + + */ +void GIC_SetICDICFR (const uint32_t *ICDICFRn); + +/** \brief API call to Enable the GIC + + API call to Enable the GIC + + */ +void GIC_Enable(void); + +#endif /* GIC_H_ */ diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefine.h new file mode 100644 index 0000000000..2bb23881a2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefine.h @@ -0,0 +1,136 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef R7S72100_IODEFINE_H +#define R7S72100_IODEFINE_H +#define IODEFINE_H_VERSION 100 + +enum iodefine_byte_select_t +{ + L = 0, H = 1, + LL= 0, LH = 1, HL = 2, HH = 3 +}; + +/*********************************************************************** + <<< [iodefine_reg32_t] >>> +- Padding : sizeof(iodefine_reg32_t) == 4 +- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +- &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3 +- Endian : Independent (Same as CPU endian as register endian) +- Bit-Order : Independent +************************************************************************/ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ +union iodefine_reg32_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ + volatile uint8_t UINT8[4]; /* 8-bit Access */ +}; +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ + +/*********************************************************************** + <<< [iodefine_reg32_16_t] >>> +- Padding : sizeof(iodefine_reg32_16_t) == 4 +- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +- Endian : Independent (Same as CPU endian as register endian) +- Bit-Order : Independent +************************************************************************/ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ +union iodefine_reg32_16_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ +}; +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ + +/*********************************************************************** + <<< [iodefine_reg16_8_t] >>> +- Padding : sizeof(iodefine_reg16_8_t) == 2 +- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1 +- Endian : Independent (Same as CPU endian as register endian) +- Bit-Order : Independent +************************************************************************/ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ +union iodefine_reg16_8_t +{ + volatile uint16_t UINT16; /* 16-bit Access */ + volatile uint8_t UINT8[2]; /* 8-bit Access */ +}; +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ + + + + + + +#include "iodefines/adc_iodefine.h" /* (V1.00a) */ +#include "iodefines/bsc_iodefine.h" /* (V1.00a) */ +#include "iodefines/ceu_iodefine.h" /* (V1.00a) */ +#include "iodefines/cpg_iodefine.h" /* (V1.00a) */ +#include "iodefines/disc_iodefine.h" /* (V1.00a) */ +#include "iodefines/dmac_iodefine.h" /* (V1.00a) */ +#include "iodefines/dvdec_iodefine.h" /* (V1.00a) */ +#include "iodefines/ether_iodefine.h" /* (V1.00a) */ +#include "iodefines/flctl_iodefine.h" /* (V1.00a) */ +#include "iodefines/gpio_iodefine.h" /* (V1.00a) */ +#include "iodefines/ieb_iodefine.h" /* (V1.00a) */ +#include "iodefines/inb_iodefine.h" /* (V1.00a) */ +#include "iodefines/intc_iodefine.h" /* (V1.00a) */ +#include "iodefines/irda_iodefine.h" /* (V1.00a) */ +#include "iodefines/jcu_iodefine.h" /* (V1.00a) */ +#include "iodefines/l2c_iodefine.h" /* (V1.00a) */ +#include "iodefines/lin_iodefine.h" /* (V1.00a) */ +#include "iodefines/lvds_iodefine.h" /* (V1.00a) */ +#include "iodefines/mlb_iodefine.h" /* (V1.00a) */ +#include "iodefines/mmc_iodefine.h" /* (V1.00a) */ +#include "iodefines/mtu2_iodefine.h" /* (V1.00a) */ +#include "iodefines/ostm_iodefine.h" /* (V1.00a) */ +#include "iodefines/pfv_iodefine.h" /* (V1.00a) */ +#include "iodefines/pwm_iodefine.h" /* (V1.00a) */ +#include "iodefines/riic_iodefine.h" /* (V1.00a) */ +#include "iodefines/romdec_iodefine.h" /* (V1.00a) */ +#include "iodefines/rscan0_iodefine.h" /* (V1.00a) */ +#include "iodefines/rspi_iodefine.h" /* (V1.00a) */ +#include "iodefines/rtc_iodefine.h" /* (V1.00a) */ +#include "iodefines/scif_iodefine.h" /* (V1.00a) */ +#include "iodefines/scim_iodefine.h" /* (V1.00a) */ +#include "iodefines/scux_iodefine.h" /* (V1.00a) */ +#include "iodefines/sdg_iodefine.h" /* (V1.00a) */ +#include "iodefines/spdif_iodefine.h" /* (V1.00a) */ +#include "iodefines/spibsc_iodefine.h" /* (V1.00a) */ +#include "iodefines/ssif_iodefine.h" /* (V1.00a) */ +#include "iodefines/usb20_iodefine.h" /* (V1.00a) */ +#include "iodefines/vdc5_iodefine.h" /* (V1.00a) */ +#include "iodefines/wdt_iodefine.h" /* (V1.00a) */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/adc_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/adc_iodefine.h new file mode 100644 index 0000000000..55bc7ddd26 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/adc_iodefine.h @@ -0,0 +1,98 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : adc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef ADC_IODEFINE_H +#define ADC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_adc +{ /* ADC */ + volatile uint16_t ADDRA; /* ADDRA */ + volatile uint16_t ADDRB; /* ADDRB */ + volatile uint16_t ADDRC; /* ADDRC */ + volatile uint16_t ADDRD; /* ADDRD */ + volatile uint16_t ADDRE; /* ADDRE */ + volatile uint16_t ADDRF; /* ADDRF */ + volatile uint16_t ADDRG; /* ADDRG */ + volatile uint16_t ADDRH; /* ADDRH */ + volatile uint8_t dummy32[16]; /* */ + volatile uint16_t ADCMPHA; /* ADCMPHA */ + volatile uint16_t ADCMPLA; /* ADCMPLA */ + volatile uint16_t ADCMPHB; /* ADCMPHB */ + volatile uint16_t ADCMPLB; /* ADCMPLB */ + volatile uint16_t ADCMPHC; /* ADCMPHC */ + volatile uint16_t ADCMPLC; /* ADCMPLC */ + volatile uint16_t ADCMPHD; /* ADCMPHD */ + volatile uint16_t ADCMPLD; /* ADCMPLD */ + volatile uint16_t ADCMPHE; /* ADCMPHE */ + volatile uint16_t ADCMPLE; /* ADCMPLE */ + volatile uint16_t ADCMPHF; /* ADCMPHF */ + volatile uint16_t ADCMPLF; /* ADCMPLF */ + volatile uint16_t ADCMPHG; /* ADCMPHG */ + volatile uint16_t ADCMPLG; /* ADCMPLG */ + volatile uint16_t ADCMPHH; /* ADCMPHH */ + volatile uint16_t ADCMPLH; /* ADCMPLH */ + volatile uint8_t dummy33[32]; /* */ + volatile uint16_t ADCSR; /* ADCSR */ + volatile uint16_t ADCMPER; /* ADCMPER */ + volatile uint16_t ADCMPSR; /* ADCMPSR */ +}; + + +#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */ + + +#define ADCADDRA ADC.ADDRA +#define ADCADDRB ADC.ADDRB +#define ADCADDRC ADC.ADDRC +#define ADCADDRD ADC.ADDRD +#define ADCADDRE ADC.ADDRE +#define ADCADDRF ADC.ADDRF +#define ADCADDRG ADC.ADDRG +#define ADCADDRH ADC.ADDRH +#define ADCADCMPHA ADC.ADCMPHA +#define ADCADCMPLA ADC.ADCMPLA +#define ADCADCMPHB ADC.ADCMPHB +#define ADCADCMPLB ADC.ADCMPLB +#define ADCADCMPHC ADC.ADCMPHC +#define ADCADCMPLC ADC.ADCMPLC +#define ADCADCMPHD ADC.ADCMPHD +#define ADCADCMPLD ADC.ADCMPLD +#define ADCADCMPHE ADC.ADCMPHE +#define ADCADCMPLE ADC.ADCMPLE +#define ADCADCMPHF ADC.ADCMPHF +#define ADCADCMPLF ADC.ADCMPLF +#define ADCADCMPHG ADC.ADCMPHG +#define ADCADCMPLG ADC.ADCMPLG +#define ADCADCMPHH ADC.ADCMPHH +#define ADCADCMPLH ADC.ADCMPLH +#define ADCADCSR ADC.ADCSR +#define ADCADCMPER ADC.ADCMPER +#define ADCADCMPSR ADC.ADCMPSR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/bsc_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/bsc_iodefine.h new file mode 100644 index 0000000000..0d327ac760 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/bsc_iodefine.h @@ -0,0 +1,99 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : bsc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef BSC_IODEFINE_H +#define BSC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_bsc +{ /* BSC */ + volatile uint32_t CMNCR; /* CMNCR */ +#define BSC_CSnBCR_COUNT 6 + volatile uint32_t CS0BCR; /* CS0BCR */ + volatile uint32_t CS1BCR; /* CS1BCR */ + volatile uint32_t CS2BCR; /* CS2BCR */ + volatile uint32_t CS3BCR; /* CS3BCR */ + volatile uint32_t CS4BCR; /* CS4BCR */ + volatile uint32_t CS5BCR; /* CS5BCR */ + volatile uint8_t dummy4[12]; /* */ +#define BSC_CSnWCR_COUNT 6 + volatile uint32_t CS0WCR; /* CS0WCR */ + volatile uint32_t CS1WCR; /* CS1WCR */ + volatile uint32_t CS2WCR; /* CS2WCR */ + volatile uint32_t CS3WCR; /* CS3WCR */ + volatile uint32_t CS4WCR; /* CS4WCR */ + volatile uint32_t CS5WCR; /* CS5WCR */ + volatile uint8_t dummy5[12]; /* */ + volatile uint32_t SDCR; /* SDCR */ + volatile uint32_t RTCSR; /* RTCSR */ + volatile uint32_t RTCNT; /* RTCNT */ + volatile uint32_t RTCOR; /* RTCOR */ + volatile uint8_t dummy6[4]; /* */ +#define BSC_TOSCORn_COUNT 6 + volatile uint32_t TOSCOR0; /* TOSCOR0 */ + volatile uint32_t TOSCOR1; /* TOSCOR1 */ + volatile uint32_t TOSCOR2; /* TOSCOR2 */ + volatile uint32_t TOSCOR3; /* TOSCOR3 */ + volatile uint32_t TOSCOR4; /* TOSCOR4 */ + volatile uint32_t TOSCOR5; /* TOSCOR5 */ + volatile uint8_t dummy7[8]; /* */ + volatile uint32_t TOSTR; /* TOSTR */ + volatile uint32_t TOENR; /* TOENR */ +}; + + +#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ + + +#define BSCCMNCR BSC.CMNCR +#define BSCCS0BCR BSC.CS0BCR +#define BSCCS1BCR BSC.CS1BCR +#define BSCCS2BCR BSC.CS2BCR +#define BSCCS3BCR BSC.CS3BCR +#define BSCCS4BCR BSC.CS4BCR +#define BSCCS5BCR BSC.CS5BCR +#define BSCCS0WCR BSC.CS0WCR +#define BSCCS1WCR BSC.CS1WCR +#define BSCCS2WCR BSC.CS2WCR +#define BSCCS3WCR BSC.CS3WCR +#define BSCCS4WCR BSC.CS4WCR +#define BSCCS5WCR BSC.CS5WCR +#define BSCSDCR BSC.SDCR +#define BSCRTCSR BSC.RTCSR +#define BSCRTCNT BSC.RTCNT +#define BSCRTCOR BSC.RTCOR +#define BSCTOSCOR0 BSC.TOSCOR0 +#define BSCTOSCOR1 BSC.TOSCOR1 +#define BSCTOSCOR2 BSC.TOSCOR2 +#define BSCTOSCOR3 BSC.TOSCOR3 +#define BSCTOSCOR4 BSC.TOSCOR4 +#define BSCTOSCOR5 BSC.TOSCOR5 +#define BSCTOSTR BSC.TOSTR +#define BSCTOENR BSC.TOENR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ceu_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ceu_iodefine.h new file mode 100644 index 0000000000..535b18bed0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ceu_iodefine.h @@ -0,0 +1,269 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ceu_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef CEU_IODEFINE_H +#define CEU_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_ceu +{ /* CEU */ +/* start of struct st_ceu_n */ + volatile uint32_t CAPSR; /* CAPSR */ + volatile uint32_t CAPCR; /* CAPCR */ + volatile uint32_t CAMCR; /* CAMCR */ + volatile uint32_t CMCYR; /* CMCYR */ + volatile uint32_t CAMOR_A; /* CAMOR_A */ + volatile uint32_t CAPWR_A; /* CAPWR_A */ + volatile uint32_t CAIFR; /* CAIFR */ + volatile uint8_t dummy305[12]; /* */ + volatile uint32_t CRCNTR; /* CRCNTR */ + volatile uint32_t CRCMPR; /* CRCMPR */ + volatile uint32_t CFLCR_A; /* CFLCR_A */ + volatile uint32_t CFSZR_A; /* CFSZR_A */ + volatile uint32_t CDWDR_A; /* CDWDR_A */ + volatile uint32_t CDAYR_A; /* CDAYR_A */ + volatile uint32_t CDACR_A; /* CDACR_A */ + volatile uint32_t CDBYR_A; /* CDBYR_A */ + volatile uint32_t CDBCR_A; /* CDBCR_A */ + volatile uint32_t CBDSR_A; /* CBDSR_A */ + volatile uint8_t dummy306[12]; /* */ + volatile uint32_t CFWCR; /* CFWCR */ + volatile uint32_t CLFCR_A; /* CLFCR_A */ + volatile uint32_t CDOCR_A; /* CDOCR_A */ + volatile uint8_t dummy307[8]; /* */ + volatile uint32_t CEIER; /* CEIER */ + volatile uint32_t CETCR; /* CETCR */ + volatile uint8_t dummy308[4]; /* */ + volatile uint32_t CSTSR; /* CSTSR */ + volatile uint8_t dummy309[4]; /* */ + volatile uint32_t CDSSR; /* CDSSR */ + volatile uint8_t dummy310[8]; /* */ + volatile uint32_t CDAYR2_A; /* CDAYR2_A */ + volatile uint32_t CDACR2_A; /* CDACR2_A */ + volatile uint32_t CDBYR2_A; /* CDBYR2_A */ + volatile uint32_t CDBCR2_A; /* CDBCR2_A */ +/* end of struct st_ceu_n */ + volatile uint8_t dummy3110[3936]; /* */ +/* start of struct st_ceu_n */ + volatile uint8_t dummy3111[4]; /* */ + volatile uint8_t dummy3112[4]; /* */ + volatile uint8_t dummy3113[4]; /* */ + volatile uint8_t dummy3114[4]; /* */ + volatile uint32_t CAMOR_B; /* CAMOR_B */ + volatile uint32_t CAPWR_B; /* CAPWR_B */ + volatile uint8_t dummy3120[4]; /* */ + volatile uint8_t dummy3121[12]; /* */ + volatile uint8_t dummy3122[4]; /* */ + volatile uint8_t dummy3123[4]; /* */ + volatile uint32_t CFLCR_B; /* CFLCR_B */ + volatile uint32_t CFSZR_B; /* CFSZR_B */ + volatile uint32_t CDWDR_B; /* CDWDR_B */ + volatile uint32_t CDAYR_B; /* CDAYR_B */ + volatile uint32_t CDACR_B; /* CDACR_B */ + volatile uint32_t CDBYR_B; /* CDBYR_B */ + volatile uint32_t CDBCR_B; /* CDBCR_B */ + volatile uint32_t CBDSR_B; /* CBDSR_B */ + volatile uint8_t dummy3130[12]; /* */ + volatile uint8_t dummy3131[4]; /* */ + volatile uint32_t CLFCR_B; /* CLFCR_B */ + volatile uint32_t CDOCR_B; /* CDOCR_B */ + volatile uint8_t dummy3140[8]; /* */ + volatile uint8_t dummy3141[4]; /* */ + volatile uint8_t dummy3142[4]; /* */ + volatile uint8_t dummy3143[4]; /* */ + volatile uint8_t dummy3144[4]; /* */ + volatile uint8_t dummy3145[4]; /* */ + volatile uint8_t dummy3146[4]; /* */ + volatile uint8_t dummy3147[8]; /* */ + volatile uint32_t CDAYR2_B; /* CDAYR2_B */ + volatile uint32_t CDACR2_B; /* CDACR2_B */ + volatile uint32_t CDBYR2_B; /* CDBYR2_B */ + volatile uint32_t CDBCR2_B; /* CDBCR2_B */ +/* end of struct st_ceu_n */ + volatile uint8_t dummy3150[3936]; /* */ +/* start of struct st_ceu_n */ + volatile uint8_t dummy3151[4]; /* */ + volatile uint8_t dummy3152[4]; /* */ + volatile uint8_t dummy3153[4]; /* */ + volatile uint8_t dummy3154[4]; /* */ + volatile uint32_t CAMOR_M; /* CAMOR_M */ + volatile uint32_t CAPWR_M; /* CAPWR_M */ + volatile uint8_t dummy3160[4]; /* */ + volatile uint8_t dummy3161[12]; /* */ + volatile uint8_t dummy3162[4]; /* */ + volatile uint8_t dummy3163[4]; /* */ + volatile uint32_t CFLCR_M; /* CFLCR_M */ + volatile uint32_t CFSZR_M; /* CFSZR_M */ + volatile uint32_t CDWDR_M; /* CDWDR_M */ + volatile uint32_t CDAYR_M; /* CDAYR_M */ + volatile uint32_t CDACR_M; /* CDACR_M */ + volatile uint32_t CDBYR_M; /* CDBYR_M */ + volatile uint32_t CDBCR_M; /* CDBCR_M */ + volatile uint32_t CBDSR_M; /* CBDSR_M */ + volatile uint8_t dummy3170[12]; /* */ + volatile uint8_t dummy3171[4]; /* */ + volatile uint32_t CLFCR_M; /* CLFCR_M */ + volatile uint32_t CDOCR_M; /* CDOCR_M */ + volatile uint8_t dummy3180[8]; /* */ + volatile uint8_t dummy3181[4]; /* */ + volatile uint8_t dummy3182[4]; /* */ + volatile uint8_t dummy3183[4]; /* */ + volatile uint8_t dummy3184[4]; /* */ + volatile uint8_t dummy3185[4]; /* */ + volatile uint8_t dummy3186[4]; /* */ + volatile uint8_t dummy3187[8]; /* */ + volatile uint32_t CDAYR2_M; /* CDAYR2_M */ + volatile uint32_t CDACR2_M; /* CDACR2_M */ + volatile uint32_t CDBYR2_M; /* CDBYR2_M */ + volatile uint32_t CDBCR2_M; /* CDBCR2_M */ +/* end of struct st_ceu_n */ +}; + + +struct st_ceu_n +{ + volatile uint32_t not_common1; /* */ + volatile uint32_t not_common2; /* */ + volatile uint32_t not_common3; /* */ + volatile uint32_t not_common4; /* */ + volatile uint32_t CAMOR; /* CAMOR */ + volatile uint32_t CAPWR; /* CAPWR */ + volatile uint32_t not_common5; /* */ + volatile uint8_t dummy322[12]; /* */ + volatile uint32_t not_common6; /* */ + volatile uint32_t not_common7; /* */ + volatile uint32_t CFLCR; /* CFLCR */ + volatile uint32_t CFSZR; /* CFSZR */ + volatile uint32_t CDWDR; /* CDWDR */ + volatile uint32_t CDAYR; /* CDAYR */ + volatile uint32_t CDACR; /* CDACR */ + volatile uint32_t CDBYR; /* CDBYR */ + volatile uint32_t CDBCR; /* CDBCR */ + volatile uint32_t CBDSR; /* CBDSR */ + volatile uint8_t dummy323[12]; /* */ + volatile uint32_t not_common8; /* */ + volatile uint32_t CLFCR; /* CLFCR */ + volatile uint32_t CDOCR; /* CDOCR */ + volatile uint8_t dummy324[8]; /* */ + volatile uint32_t not_common9; /* */ + volatile uint32_t not_common10; /* */ + volatile uint8_t dummy325[4]; /* */ + volatile uint32_t not_common11; /* */ + volatile uint8_t dummy326[4]; /* */ + volatile uint32_t not_common12; /* */ + volatile uint8_t dummy327[8]; /* */ + volatile uint32_t CDAYR2; /* CDAYR2 */ + volatile uint32_t CDACR2; /* CDACR2 */ + volatile uint32_t CDBYR2; /* CDBYR2 */ + volatile uint32_t CDBCR2; /* CDBCR2 */ +}; + + +#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ + + +/* Start of channnel array defines of CEU */ + +/* Channnel array defines of CEUn */ +/*(Sample) value = CEUn[ channel ]->CAMOR; */ +#define CEUn_COUNT 3 +#define CEUn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + (volatile struct st_ceu_n*)&CEU_A, \ + (volatile struct st_ceu_n*)&CEU_B, \ + (volatile struct st_ceu_n*)&CEU_M \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ +#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ +#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ + +/* End of channnel array defines of CEU */ + + +#define CEUCAPSR CEU.CAPSR +#define CEUCAPCR CEU.CAPCR +#define CEUCAMCR CEU.CAMCR +#define CEUCMCYR CEU.CMCYR +#define CEUCAMOR_A CEU.CAMOR_A +#define CEUCAPWR_A CEU.CAPWR_A +#define CEUCAIFR CEU.CAIFR +#define CEUCRCNTR CEU.CRCNTR +#define CEUCRCMPR CEU.CRCMPR +#define CEUCFLCR_A CEU.CFLCR_A +#define CEUCFSZR_A CEU.CFSZR_A +#define CEUCDWDR_A CEU.CDWDR_A +#define CEUCDAYR_A CEU.CDAYR_A +#define CEUCDACR_A CEU.CDACR_A +#define CEUCDBYR_A CEU.CDBYR_A +#define CEUCDBCR_A CEU.CDBCR_A +#define CEUCBDSR_A CEU.CBDSR_A +#define CEUCFWCR CEU.CFWCR +#define CEUCLFCR_A CEU.CLFCR_A +#define CEUCDOCR_A CEU.CDOCR_A +#define CEUCEIER CEU.CEIER +#define CEUCETCR CEU.CETCR +#define CEUCSTSR CEU.CSTSR +#define CEUCDSSR CEU.CDSSR +#define CEUCDAYR2_A CEU.CDAYR2_A +#define CEUCDACR2_A CEU.CDACR2_A +#define CEUCDBYR2_A CEU.CDBYR2_A +#define CEUCDBCR2_A CEU.CDBCR2_A +#define CEUCAMOR_B CEU.CAMOR_B +#define CEUCAPWR_B CEU.CAPWR_B +#define CEUCFLCR_B CEU.CFLCR_B +#define CEUCFSZR_B CEU.CFSZR_B +#define CEUCDWDR_B CEU.CDWDR_B +#define CEUCDAYR_B CEU.CDAYR_B +#define CEUCDACR_B CEU.CDACR_B +#define CEUCDBYR_B CEU.CDBYR_B +#define CEUCDBCR_B CEU.CDBCR_B +#define CEUCBDSR_B CEU.CBDSR_B +#define CEUCLFCR_B CEU.CLFCR_B +#define CEUCDOCR_B CEU.CDOCR_B +#define CEUCDAYR2_B CEU.CDAYR2_B +#define CEUCDACR2_B CEU.CDACR2_B +#define CEUCDBYR2_B CEU.CDBYR2_B +#define CEUCDBCR2_B CEU.CDBCR2_B +#define CEUCAMOR_M CEU.CAMOR_M +#define CEUCAPWR_M CEU.CAPWR_M +#define CEUCFLCR_M CEU.CFLCR_M +#define CEUCFSZR_M CEU.CFSZR_M +#define CEUCDWDR_M CEU.CDWDR_M +#define CEUCDAYR_M CEU.CDAYR_M +#define CEUCDACR_M CEU.CDACR_M +#define CEUCDBYR_M CEU.CDBYR_M +#define CEUCDBCR_M CEU.CDBCR_M +#define CEUCBDSR_M CEU.CBDSR_M +#define CEUCLFCR_M CEU.CLFCR_M +#define CEUCDOCR_M CEU.CDOCR_M +#define CEUCDAYR2_M CEU.CDAYR2_M +#define CEUCDACR2_M CEU.CDACR2_M +#define CEUCDBYR2_M CEU.CDBYR2_M +#define CEUCDBCR2_M CEU.CDBCR2_M +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/cpg_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/cpg_iodefine.h new file mode 100644 index 0000000000..5fc9890ff5 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/cpg_iodefine.h @@ -0,0 +1,239 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : cpg_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef CPG_IODEFINE_H +#define CPG_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_cpg +{ /* CPG */ + volatile uint16_t FRQCR; /* FRQCR */ + volatile uint8_t dummy319[2]; /* */ + volatile uint16_t FRQCR2; /* FRQCR2 */ + volatile uint8_t dummy320[2]; /* */ + volatile uint8_t CPUSTS; /* CPUSTS */ + volatile uint8_t dummy321[7]; /* */ + volatile uint8_t STBCR1; /* STBCR1 */ + volatile uint8_t dummy322[3]; /* */ + volatile uint8_t STBCR2; /* STBCR2 */ + volatile uint8_t dummy323[11]; /* */ + volatile uint8_t STBREQ1; /* STBREQ1 */ + volatile uint8_t dummy324[3]; /* */ + volatile uint8_t STBREQ2; /* STBREQ2 */ + volatile uint8_t dummy325[11]; /* */ + volatile uint8_t STBACK1; /* STBACK1 */ + volatile uint8_t dummy326[3]; /* */ + volatile uint8_t STBACK2; /* STBACK2 */ + volatile uint8_t dummy327[955]; /* */ +/* start of struct st_cpg_from_syscr1 */ + volatile uint8_t SYSCR1; /* SYSCR1 */ + volatile uint8_t dummy328[3]; /* */ +/* end of struct st_cpg_from_syscr1 */ +/* start of struct st_cpg_from_syscr1 */ + volatile uint8_t SYSCR2; /* SYSCR2 */ + volatile uint8_t dummy329[3]; /* */ +/* end of struct st_cpg_from_syscr1 */ +/* start of struct st_cpg_from_syscr1 */ + volatile uint8_t SYSCR3; /* SYSCR3 */ + volatile uint8_t dummy3300[3]; /* */ +/* end of struct st_cpg_from_syscr1 */ + volatile uint8_t dummy3301[20]; /* */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR3; /* STBCR3 */ + volatile uint8_t dummy331[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR4; /* STBCR4 */ + volatile uint8_t dummy332[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR5; /* STBCR5 */ + volatile uint8_t dummy333[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR6; /* STBCR6 */ + volatile uint8_t dummy334[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR7; /* STBCR7 */ + volatile uint8_t dummy335[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR8; /* STBCR8 */ + volatile uint8_t dummy336[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR9; /* STBCR9 */ + volatile uint8_t dummy337[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR10; /* STBCR10 */ + volatile uint8_t dummy338[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR11; /* STBCR11 */ + volatile uint8_t dummy339[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ +/* start of struct st_cpg_from_stbcr3 */ + volatile uint8_t STBCR12; /* STBCR12 */ + volatile uint8_t dummy3400[3]; /* */ +/* end of struct st_cpg_from_stbcr3 */ + volatile uint8_t dummy3401[24]; /* */ +/* start of struct st_cpg_from_swrstcr1 */ + volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ + volatile uint8_t dummy341[3]; /* */ +/* end of struct st_cpg_from_swrstcr1 */ +/* start of struct st_cpg_from_swrstcr1 */ + volatile uint8_t SWRSTCR2; /* SWRSTCR2 */ + volatile uint8_t dummy342[3]; /* */ +/* end of struct st_cpg_from_swrstcr1 */ +/* start of struct st_cpg_from_swrstcr1 */ + volatile uint8_t SWRSTCR3; /* SWRSTCR3 */ + volatile uint8_t dummy3430[3]; /* */ +/* end of struct st_cpg_from_swrstcr1 */ + volatile uint8_t dummy3431[4]; /* */ + volatile uint8_t STBCR13; /* STBCR13 */ + volatile uint8_t dummy344[70543]; /* */ + volatile uint8_t RRAMKP; /* RRAMKP */ + volatile uint8_t dummy345[1]; /* */ + volatile uint8_t DSCTR; /* DSCTR */ + volatile uint8_t dummy346[1]; /* */ + volatile uint16_t DSSSR; /* DSSSR */ + volatile uint16_t DSESR; /* DSESR */ + volatile uint16_t DSFR; /* DSFR */ + volatile uint8_t dummy347[6]; /* */ + volatile uint8_t XTALCTR; /* XTALCTR */ +}; + + +struct st_cpg_from_syscr1 +{ + volatile uint8_t SYSCR1; /* SYSCR1 */ + volatile uint8_t dummy1[3]; /* */ +}; + + +struct st_cpg_from_stbcr3 +{ + volatile uint8_t STBCR3; /* STBCR3 */ + volatile uint8_t dummy1[3]; /* */ +}; + + +struct st_cpg_from_swrstcr1 +{ + volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ + volatile uint8_t dummy1[3]; /* */ +}; + + +#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */ + + +/* Start of channnel array defines of CPG */ + +/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */ +#define CPG_FROM_SWRSTCR1_ARRAY_COUNT 3 +#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */ +#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */ +#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */ + + +/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */ +/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */ +#define CPG_FROM_STBCR3_ARRAY_COUNT 10 +#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \ + &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */ +#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */ +#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */ +#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */ +#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */ +#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */ +#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */ +#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */ +#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */ +#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */ + + +/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */ +#define CPG_FROM_SYSCR1_ARRAY_COUNT 3 +#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */ +#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */ +#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */ + +/* End of channnel array defines of CPG */ + + +#define CPGFRQCR CPG.FRQCR +#define CPGFRQCR2 CPG.FRQCR2 +#define CPGCPUSTS CPG.CPUSTS +#define CPGSTBCR1 CPG.STBCR1 +#define CPGSTBCR2 CPG.STBCR2 +#define CPGSTBREQ1 CPG.STBREQ1 +#define CPGSTBREQ2 CPG.STBREQ2 +#define CPGSTBACK1 CPG.STBACK1 +#define CPGSTBACK2 CPG.STBACK2 +#define CPGSYSCR1 CPG.SYSCR1 +#define CPGSYSCR2 CPG.SYSCR2 +#define CPGSYSCR3 CPG.SYSCR3 +#define CPGSTBCR3 CPG.STBCR3 +#define CPGSTBCR4 CPG.STBCR4 +#define CPGSTBCR5 CPG.STBCR5 +#define CPGSTBCR6 CPG.STBCR6 +#define CPGSTBCR7 CPG.STBCR7 +#define CPGSTBCR8 CPG.STBCR8 +#define CPGSTBCR9 CPG.STBCR9 +#define CPGSTBCR10 CPG.STBCR10 +#define CPGSTBCR11 CPG.STBCR11 +#define CPGSTBCR12 CPG.STBCR12 +#define CPGSWRSTCR1 CPG.SWRSTCR1 +#define CPGSWRSTCR2 CPG.SWRSTCR2 +#define CPGSWRSTCR3 CPG.SWRSTCR3 +#define CPGSTBCR13 CPG.STBCR13 +#define CPGRRAMKP CPG.RRAMKP +#define CPGDSCTR CPG.DSCTR +#define CPGDSSSR CPG.DSSSR +#define CPGDSESR CPG.DSESR +#define CPGDSFR CPG.DSFR +#define CPGXTALCTR CPG.XTALCTR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/disc_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/disc_iodefine.h new file mode 100644 index 0000000000..8844fa2afb --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/disc_iodefine.h @@ -0,0 +1,93 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : disc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef DISC_IODEFINE_H +#define DISC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_disc +{ /* DISC */ + volatile uint32_t DOCMCR; /* DOCMCR */ + volatile uint32_t DOCMSTR; /* DOCMSTR */ + volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */ + volatile uint32_t DOCMIENR; /* DOCMIENR */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t DOCMPMR; /* DOCMPMR */ + volatile uint32_t DOCMECRCR; /* DOCMECRCR */ + volatile uint32_t DOCMCCRCR; /* DOCMCCRCR */ + volatile uint32_t DOCMSPXR; /* DOCMSPXR */ + volatile uint32_t DOCMSPYR; /* DOCMSPYR */ + volatile uint32_t DOCMSZXR; /* DOCMSZXR */ + volatile uint32_t DOCMSZYR; /* DOCMSZYR */ + volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */ +}; + + +#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */ +#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */ + + +/* Start of channnel array defines of DISC */ + +/* Channnel array defines of DISC */ +/*(Sample) value = DISC[ channel ]->DOCMCR; */ +#define DISC_COUNT 2 +#define DISC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DISC0, &DISC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of DISC */ + + +#define DISC0DOCMCR DISC0.DOCMCR +#define DISC0DOCMSTR DISC0.DOCMSTR +#define DISC0DOCMCLSTR DISC0.DOCMCLSTR +#define DISC0DOCMIENR DISC0.DOCMIENR +#define DISC0DOCMPMR DISC0.DOCMPMR +#define DISC0DOCMECRCR DISC0.DOCMECRCR +#define DISC0DOCMCCRCR DISC0.DOCMCCRCR +#define DISC0DOCMSPXR DISC0.DOCMSPXR +#define DISC0DOCMSPYR DISC0.DOCMSPYR +#define DISC0DOCMSZXR DISC0.DOCMSZXR +#define DISC0DOCMSZYR DISC0.DOCMSZYR +#define DISC0DOCMCRCIR DISC0.DOCMCRCIR +#define DISC1DOCMCR DISC1.DOCMCR +#define DISC1DOCMSTR DISC1.DOCMSTR +#define DISC1DOCMCLSTR DISC1.DOCMCLSTR +#define DISC1DOCMIENR DISC1.DOCMIENR +#define DISC1DOCMPMR DISC1.DOCMPMR +#define DISC1DOCMECRCR DISC1.DOCMECRCR +#define DISC1DOCMCCRCR DISC1.DOCMCCRCR +#define DISC1DOCMSPXR DISC1.DOCMSPXR +#define DISC1DOCMSPYR DISC1.DOCMSPYR +#define DISC1DOCMSZXR DISC1.DOCMSZXR +#define DISC1DOCMSZYR DISC1.DOCMSZYR +#define DISC1DOCMCRCIR DISC1.DOCMCRCIR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dmac_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dmac_iodefine.h new file mode 100644 index 0000000000..0faf27fbe0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dmac_iodefine.h @@ -0,0 +1,733 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : dmac_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef DMAC_IODEFINE_H +#define DMAC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_dmac +{ /* DMAC */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_0; /* N0SA_0 */ + volatile uint32_t N0DA_0; /* N0DA_0 */ + volatile uint32_t N0TB_0; /* N0TB_0 */ + volatile uint32_t N1SA_0; /* N1SA_0 */ + volatile uint32_t N1DA_0; /* N1DA_0 */ + volatile uint32_t N1TB_0; /* N1TB_0 */ + volatile uint32_t CRSA_0; /* CRSA_0 */ + volatile uint32_t CRDA_0; /* CRDA_0 */ + volatile uint32_t CRTB_0; /* CRTB_0 */ + volatile uint32_t CHSTAT_0; /* CHSTAT_0 */ + volatile uint32_t CHCTRL_0; /* CHCTRL_0 */ + volatile uint32_t CHCFG_0; /* CHCFG_0 */ + volatile uint32_t CHITVL_0; /* CHITVL_0 */ + volatile uint32_t CHEXT_0; /* CHEXT_0 */ + volatile uint32_t NXLA_0; /* NXLA_0 */ + volatile uint32_t CRLA_0; /* CRLA_0 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_1; /* N0SA_1 */ + volatile uint32_t N0DA_1; /* N0DA_1 */ + volatile uint32_t N0TB_1; /* N0TB_1 */ + volatile uint32_t N1SA_1; /* N1SA_1 */ + volatile uint32_t N1DA_1; /* N1DA_1 */ + volatile uint32_t N1TB_1; /* N1TB_1 */ + volatile uint32_t CRSA_1; /* CRSA_1 */ + volatile uint32_t CRDA_1; /* CRDA_1 */ + volatile uint32_t CRTB_1; /* CRTB_1 */ + volatile uint32_t CHSTAT_1; /* CHSTAT_1 */ + volatile uint32_t CHCTRL_1; /* CHCTRL_1 */ + volatile uint32_t CHCFG_1; /* CHCFG_1 */ + volatile uint32_t CHITVL_1; /* CHITVL_1 */ + volatile uint32_t CHEXT_1; /* CHEXT_1 */ + volatile uint32_t NXLA_1; /* NXLA_1 */ + volatile uint32_t CRLA_1; /* CRLA_1 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_2; /* N0SA_2 */ + volatile uint32_t N0DA_2; /* N0DA_2 */ + volatile uint32_t N0TB_2; /* N0TB_2 */ + volatile uint32_t N1SA_2; /* N1SA_2 */ + volatile uint32_t N1DA_2; /* N1DA_2 */ + volatile uint32_t N1TB_2; /* N1TB_2 */ + volatile uint32_t CRSA_2; /* CRSA_2 */ + volatile uint32_t CRDA_2; /* CRDA_2 */ + volatile uint32_t CRTB_2; /* CRTB_2 */ + volatile uint32_t CHSTAT_2; /* CHSTAT_2 */ + volatile uint32_t CHCTRL_2; /* CHCTRL_2 */ + volatile uint32_t CHCFG_2; /* CHCFG_2 */ + volatile uint32_t CHITVL_2; /* CHITVL_2 */ + volatile uint32_t CHEXT_2; /* CHEXT_2 */ + volatile uint32_t NXLA_2; /* NXLA_2 */ + volatile uint32_t CRLA_2; /* CRLA_2 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_3; /* N0SA_3 */ + volatile uint32_t N0DA_3; /* N0DA_3 */ + volatile uint32_t N0TB_3; /* N0TB_3 */ + volatile uint32_t N1SA_3; /* N1SA_3 */ + volatile uint32_t N1DA_3; /* N1DA_3 */ + volatile uint32_t N1TB_3; /* N1TB_3 */ + volatile uint32_t CRSA_3; /* CRSA_3 */ + volatile uint32_t CRDA_3; /* CRDA_3 */ + volatile uint32_t CRTB_3; /* CRTB_3 */ + volatile uint32_t CHSTAT_3; /* CHSTAT_3 */ + volatile uint32_t CHCTRL_3; /* CHCTRL_3 */ + volatile uint32_t CHCFG_3; /* CHCFG_3 */ + volatile uint32_t CHITVL_3; /* CHITVL_3 */ + volatile uint32_t CHEXT_3; /* CHEXT_3 */ + volatile uint32_t NXLA_3; /* NXLA_3 */ + volatile uint32_t CRLA_3; /* CRLA_3 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_4; /* N0SA_4 */ + volatile uint32_t N0DA_4; /* N0DA_4 */ + volatile uint32_t N0TB_4; /* N0TB_4 */ + volatile uint32_t N1SA_4; /* N1SA_4 */ + volatile uint32_t N1DA_4; /* N1DA_4 */ + volatile uint32_t N1TB_4; /* N1TB_4 */ + volatile uint32_t CRSA_4; /* CRSA_4 */ + volatile uint32_t CRDA_4; /* CRDA_4 */ + volatile uint32_t CRTB_4; /* CRTB_4 */ + volatile uint32_t CHSTAT_4; /* CHSTAT_4 */ + volatile uint32_t CHCTRL_4; /* CHCTRL_4 */ + volatile uint32_t CHCFG_4; /* CHCFG_4 */ + volatile uint32_t CHITVL_4; /* CHITVL_4 */ + volatile uint32_t CHEXT_4; /* CHEXT_4 */ + volatile uint32_t NXLA_4; /* NXLA_4 */ + volatile uint32_t CRLA_4; /* CRLA_4 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_5; /* N0SA_5 */ + volatile uint32_t N0DA_5; /* N0DA_5 */ + volatile uint32_t N0TB_5; /* N0TB_5 */ + volatile uint32_t N1SA_5; /* N1SA_5 */ + volatile uint32_t N1DA_5; /* N1DA_5 */ + volatile uint32_t N1TB_5; /* N1TB_5 */ + volatile uint32_t CRSA_5; /* CRSA_5 */ + volatile uint32_t CRDA_5; /* CRDA_5 */ + volatile uint32_t CRTB_5; /* CRTB_5 */ + volatile uint32_t CHSTAT_5; /* CHSTAT_5 */ + volatile uint32_t CHCTRL_5; /* CHCTRL_5 */ + volatile uint32_t CHCFG_5; /* CHCFG_5 */ + volatile uint32_t CHITVL_5; /* CHITVL_5 */ + volatile uint32_t CHEXT_5; /* CHEXT_5 */ + volatile uint32_t NXLA_5; /* NXLA_5 */ + volatile uint32_t CRLA_5; /* CRLA_5 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_6; /* N0SA_6 */ + volatile uint32_t N0DA_6; /* N0DA_6 */ + volatile uint32_t N0TB_6; /* N0TB_6 */ + volatile uint32_t N1SA_6; /* N1SA_6 */ + volatile uint32_t N1DA_6; /* N1DA_6 */ + volatile uint32_t N1TB_6; /* N1TB_6 */ + volatile uint32_t CRSA_6; /* CRSA_6 */ + volatile uint32_t CRDA_6; /* CRDA_6 */ + volatile uint32_t CRTB_6; /* CRTB_6 */ + volatile uint32_t CHSTAT_6; /* CHSTAT_6 */ + volatile uint32_t CHCTRL_6; /* CHCTRL_6 */ + volatile uint32_t CHCFG_6; /* CHCFG_6 */ + volatile uint32_t CHITVL_6; /* CHITVL_6 */ + volatile uint32_t CHEXT_6; /* CHEXT_6 */ + volatile uint32_t NXLA_6; /* NXLA_6 */ + volatile uint32_t CRLA_6; /* CRLA_6 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_7; /* N0SA_7 */ + volatile uint32_t N0DA_7; /* N0DA_7 */ + volatile uint32_t N0TB_7; /* N0TB_7 */ + volatile uint32_t N1SA_7; /* N1SA_7 */ + volatile uint32_t N1DA_7; /* N1DA_7 */ + volatile uint32_t N1TB_7; /* N1TB_7 */ + volatile uint32_t CRSA_7; /* CRSA_7 */ + volatile uint32_t CRDA_7; /* CRDA_7 */ + volatile uint32_t CRTB_7; /* CRTB_7 */ + volatile uint32_t CHSTAT_7; /* CHSTAT_7 */ + volatile uint32_t CHCTRL_7; /* CHCTRL_7 */ + volatile uint32_t CHCFG_7; /* CHCFG_7 */ + volatile uint32_t CHITVL_7; /* CHITVL_7 */ + volatile uint32_t CHEXT_7; /* CHEXT_7 */ + volatile uint32_t NXLA_7; /* NXLA_7 */ + volatile uint32_t CRLA_7; /* CRLA_7 */ +/* end of struct st_dmac_n */ + volatile uint8_t dummy187[256]; /* */ +/* start of struct st_dmaccommon_n */ + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ + volatile uint8_t dummy188[12]; /* */ + volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ + volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ + volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ + volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ + volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ +/* end of struct st_dmaccommon_n */ + volatile uint8_t dummy189[220]; /* */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_8; /* N0SA_8 */ + volatile uint32_t N0DA_8; /* N0DA_8 */ + volatile uint32_t N0TB_8; /* N0TB_8 */ + volatile uint32_t N1SA_8; /* N1SA_8 */ + volatile uint32_t N1DA_8; /* N1DA_8 */ + volatile uint32_t N1TB_8; /* N1TB_8 */ + volatile uint32_t CRSA_8; /* CRSA_8 */ + volatile uint32_t CRDA_8; /* CRDA_8 */ + volatile uint32_t CRTB_8; /* CRTB_8 */ + volatile uint32_t CHSTAT_8; /* CHSTAT_8 */ + volatile uint32_t CHCTRL_8; /* CHCTRL_8 */ + volatile uint32_t CHCFG_8; /* CHCFG_8 */ + volatile uint32_t CHITVL_8; /* CHITVL_8 */ + volatile uint32_t CHEXT_8; /* CHEXT_8 */ + volatile uint32_t NXLA_8; /* NXLA_8 */ + volatile uint32_t CRLA_8; /* CRLA_8 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_9; /* N0SA_9 */ + volatile uint32_t N0DA_9; /* N0DA_9 */ + volatile uint32_t N0TB_9; /* N0TB_9 */ + volatile uint32_t N1SA_9; /* N1SA_9 */ + volatile uint32_t N1DA_9; /* N1DA_9 */ + volatile uint32_t N1TB_9; /* N1TB_9 */ + volatile uint32_t CRSA_9; /* CRSA_9 */ + volatile uint32_t CRDA_9; /* CRDA_9 */ + volatile uint32_t CRTB_9; /* CRTB_9 */ + volatile uint32_t CHSTAT_9; /* CHSTAT_9 */ + volatile uint32_t CHCTRL_9; /* CHCTRL_9 */ + volatile uint32_t CHCFG_9; /* CHCFG_9 */ + volatile uint32_t CHITVL_9; /* CHITVL_9 */ + volatile uint32_t CHEXT_9; /* CHEXT_9 */ + volatile uint32_t NXLA_9; /* NXLA_9 */ + volatile uint32_t CRLA_9; /* CRLA_9 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_10; /* N0SA_10 */ + volatile uint32_t N0DA_10; /* N0DA_10 */ + volatile uint32_t N0TB_10; /* N0TB_10 */ + volatile uint32_t N1SA_10; /* N1SA_10 */ + volatile uint32_t N1DA_10; /* N1DA_10 */ + volatile uint32_t N1TB_10; /* N1TB_10 */ + volatile uint32_t CRSA_10; /* CRSA_10 */ + volatile uint32_t CRDA_10; /* CRDA_10 */ + volatile uint32_t CRTB_10; /* CRTB_10 */ + volatile uint32_t CHSTAT_10; /* CHSTAT_10 */ + volatile uint32_t CHCTRL_10; /* CHCTRL_10 */ + volatile uint32_t CHCFG_10; /* CHCFG_10 */ + volatile uint32_t CHITVL_10; /* CHITVL_10 */ + volatile uint32_t CHEXT_10; /* CHEXT_10 */ + volatile uint32_t NXLA_10; /* NXLA_10 */ + volatile uint32_t CRLA_10; /* CRLA_10 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_11; /* N0SA_11 */ + volatile uint32_t N0DA_11; /* N0DA_11 */ + volatile uint32_t N0TB_11; /* N0TB_11 */ + volatile uint32_t N1SA_11; /* N1SA_11 */ + volatile uint32_t N1DA_11; /* N1DA_11 */ + volatile uint32_t N1TB_11; /* N1TB_11 */ + volatile uint32_t CRSA_11; /* CRSA_11 */ + volatile uint32_t CRDA_11; /* CRDA_11 */ + volatile uint32_t CRTB_11; /* CRTB_11 */ + volatile uint32_t CHSTAT_11; /* CHSTAT_11 */ + volatile uint32_t CHCTRL_11; /* CHCTRL_11 */ + volatile uint32_t CHCFG_11; /* CHCFG_11 */ + volatile uint32_t CHITVL_11; /* CHITVL_11 */ + volatile uint32_t CHEXT_11; /* CHEXT_11 */ + volatile uint32_t NXLA_11; /* NXLA_11 */ + volatile uint32_t CRLA_11; /* CRLA_11 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_12; /* N0SA_12 */ + volatile uint32_t N0DA_12; /* N0DA_12 */ + volatile uint32_t N0TB_12; /* N0TB_12 */ + volatile uint32_t N1SA_12; /* N1SA_12 */ + volatile uint32_t N1DA_12; /* N1DA_12 */ + volatile uint32_t N1TB_12; /* N1TB_12 */ + volatile uint32_t CRSA_12; /* CRSA_12 */ + volatile uint32_t CRDA_12; /* CRDA_12 */ + volatile uint32_t CRTB_12; /* CRTB_12 */ + volatile uint32_t CHSTAT_12; /* CHSTAT_12 */ + volatile uint32_t CHCTRL_12; /* CHCTRL_12 */ + volatile uint32_t CHCFG_12; /* CHCFG_12 */ + volatile uint32_t CHITVL_12; /* CHITVL_12 */ + volatile uint32_t CHEXT_12; /* CHEXT_12 */ + volatile uint32_t NXLA_12; /* NXLA_12 */ + volatile uint32_t CRLA_12; /* CRLA_12 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_13; /* N0SA_13 */ + volatile uint32_t N0DA_13; /* N0DA_13 */ + volatile uint32_t N0TB_13; /* N0TB_13 */ + volatile uint32_t N1SA_13; /* N1SA_13 */ + volatile uint32_t N1DA_13; /* N1DA_13 */ + volatile uint32_t N1TB_13; /* N1TB_13 */ + volatile uint32_t CRSA_13; /* CRSA_13 */ + volatile uint32_t CRDA_13; /* CRDA_13 */ + volatile uint32_t CRTB_13; /* CRTB_13 */ + volatile uint32_t CHSTAT_13; /* CHSTAT_13 */ + volatile uint32_t CHCTRL_13; /* CHCTRL_13 */ + volatile uint32_t CHCFG_13; /* CHCFG_13 */ + volatile uint32_t CHITVL_13; /* CHITVL_13 */ + volatile uint32_t CHEXT_13; /* CHEXT_13 */ + volatile uint32_t NXLA_13; /* NXLA_13 */ + volatile uint32_t CRLA_13; /* CRLA_13 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_14; /* N0SA_14 */ + volatile uint32_t N0DA_14; /* N0DA_14 */ + volatile uint32_t N0TB_14; /* N0TB_14 */ + volatile uint32_t N1SA_14; /* N1SA_14 */ + volatile uint32_t N1DA_14; /* N1DA_14 */ + volatile uint32_t N1TB_14; /* N1TB_14 */ + volatile uint32_t CRSA_14; /* CRSA_14 */ + volatile uint32_t CRDA_14; /* CRDA_14 */ + volatile uint32_t CRTB_14; /* CRTB_14 */ + volatile uint32_t CHSTAT_14; /* CHSTAT_14 */ + volatile uint32_t CHCTRL_14; /* CHCTRL_14 */ + volatile uint32_t CHCFG_14; /* CHCFG_14 */ + volatile uint32_t CHITVL_14; /* CHITVL_14 */ + volatile uint32_t CHEXT_14; /* CHEXT_14 */ + volatile uint32_t NXLA_14; /* NXLA_14 */ + volatile uint32_t CRLA_14; /* CRLA_14 */ +/* end of struct st_dmac_n */ +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_15; /* N0SA_15 */ + volatile uint32_t N0DA_15; /* N0DA_15 */ + volatile uint32_t N0TB_15; /* N0TB_15 */ + volatile uint32_t N1SA_15; /* N1SA_15 */ + volatile uint32_t N1DA_15; /* N1DA_15 */ + volatile uint32_t N1TB_15; /* N1TB_15 */ + volatile uint32_t CRSA_15; /* CRSA_15 */ + volatile uint32_t CRDA_15; /* CRDA_15 */ + volatile uint32_t CRTB_15; /* CRTB_15 */ + volatile uint32_t CHSTAT_15; /* CHSTAT_15 */ + volatile uint32_t CHCTRL_15; /* CHCTRL_15 */ + volatile uint32_t CHCFG_15; /* CHCFG_15 */ + volatile uint32_t CHITVL_15; /* CHITVL_15 */ + volatile uint32_t CHEXT_15; /* CHEXT_15 */ + volatile uint32_t NXLA_15; /* NXLA_15 */ + volatile uint32_t CRLA_15; /* CRLA_15 */ +/* end of struct st_dmac_n */ + volatile uint8_t dummy190[256]; /* */ +/* start of struct st_dmaccommon_n */ + volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */ + volatile uint8_t dummy191[12]; /* */ + volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */ + volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */ + volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */ + volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */ + volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */ +/* end of struct st_dmaccommon_n */ + volatile uint8_t dummy192[350095580]; /* */ + volatile uint32_t DMARS0; /* DMARS0 */ + volatile uint32_t DMARS1; /* DMARS1 */ + volatile uint32_t DMARS2; /* DMARS2 */ + volatile uint32_t DMARS3; /* DMARS3 */ + volatile uint32_t DMARS4; /* DMARS4 */ + volatile uint32_t DMARS5; /* DMARS5 */ + volatile uint32_t DMARS6; /* DMARS6 */ + volatile uint32_t DMARS7; /* DMARS7 */ +}; + + +struct st_dmaccommon_n +{ + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ + volatile uint8_t dummy1[12]; /* */ + volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ + volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ + volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ + volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ + volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ +}; + + +struct st_dmac_n +{ + volatile uint32_t N0SA_n; /* N0SA_n */ + volatile uint32_t N0DA_n; /* N0DA_n */ + volatile uint32_t N0TB_n; /* N0TB_n */ + volatile uint32_t N1SA_n; /* N1SA_n */ + volatile uint32_t N1DA_n; /* N1DA_n */ + volatile uint32_t N1TB_n; /* N1TB_n */ + volatile uint32_t CRSA_n; /* CRSA_n */ + volatile uint32_t CRDA_n; /* CRDA_n */ + volatile uint32_t CRTB_n; /* CRTB_n */ + volatile uint32_t CHSTAT_n; /* CHSTAT_n */ + volatile uint32_t CHCTRL_n; /* CHCTRL_n */ + volatile uint32_t CHCFG_n; /* CHCFG_n */ + volatile uint32_t CHITVL_n; /* CHITVL_n */ + volatile uint32_t CHEXT_n; /* CHEXT_n */ + volatile uint32_t NXLA_n; /* NXLA_n */ + volatile uint32_t CRLA_n; /* CRLA_n */ +}; + + +#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */ + + +/* Start of channnel array defines of DMAC */ + +/* Channnel array defines of DMACn */ +/*(Sample) value = DMACn[ channel ]->N0SA_n; */ +#define DMACn_COUNT 16 +#define DMACn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \ + &DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */ +#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */ +#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */ +#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */ +#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */ +#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */ +#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */ +#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */ +#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */ +#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */ +#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */ +#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */ +#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */ +#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */ +#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */ +#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */ + + +/* Channnel array defines of DMACnn */ +/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */ +#define DMACnn_COUNT 2 +#define DMACnn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC07, &DMAC815 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */ +#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */ + + +/* Channnel array defines of DMACmm */ +/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */ +struct st_dmars_mm +{ + uint32_t DMARS; /* DMARS */ +}; +#define DMACmm_COUNT 8 +#define DMACmm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */ +#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */ +#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */ +#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */ +#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */ +#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */ +#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */ +#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */ + +/* End of channnel array defines of DMAC */ + + +#define DMACN0SA_0 DMAC.N0SA_0 +#define DMACN0DA_0 DMAC.N0DA_0 +#define DMACN0TB_0 DMAC.N0TB_0 +#define DMACN1SA_0 DMAC.N1SA_0 +#define DMACN1DA_0 DMAC.N1DA_0 +#define DMACN1TB_0 DMAC.N1TB_0 +#define DMACCRSA_0 DMAC.CRSA_0 +#define DMACCRDA_0 DMAC.CRDA_0 +#define DMACCRTB_0 DMAC.CRTB_0 +#define DMACCHSTAT_0 DMAC.CHSTAT_0 +#define DMACCHCTRL_0 DMAC.CHCTRL_0 +#define DMACCHCFG_0 DMAC.CHCFG_0 +#define DMACCHITVL_0 DMAC.CHITVL_0 +#define DMACCHEXT_0 DMAC.CHEXT_0 +#define DMACNXLA_0 DMAC.NXLA_0 +#define DMACCRLA_0 DMAC.CRLA_0 +#define DMACN0SA_1 DMAC.N0SA_1 +#define DMACN0DA_1 DMAC.N0DA_1 +#define DMACN0TB_1 DMAC.N0TB_1 +#define DMACN1SA_1 DMAC.N1SA_1 +#define DMACN1DA_1 DMAC.N1DA_1 +#define DMACN1TB_1 DMAC.N1TB_1 +#define DMACCRSA_1 DMAC.CRSA_1 +#define DMACCRDA_1 DMAC.CRDA_1 +#define DMACCRTB_1 DMAC.CRTB_1 +#define DMACCHSTAT_1 DMAC.CHSTAT_1 +#define DMACCHCTRL_1 DMAC.CHCTRL_1 +#define DMACCHCFG_1 DMAC.CHCFG_1 +#define DMACCHITVL_1 DMAC.CHITVL_1 +#define DMACCHEXT_1 DMAC.CHEXT_1 +#define DMACNXLA_1 DMAC.NXLA_1 +#define DMACCRLA_1 DMAC.CRLA_1 +#define DMACN0SA_2 DMAC.N0SA_2 +#define DMACN0DA_2 DMAC.N0DA_2 +#define DMACN0TB_2 DMAC.N0TB_2 +#define DMACN1SA_2 DMAC.N1SA_2 +#define DMACN1DA_2 DMAC.N1DA_2 +#define DMACN1TB_2 DMAC.N1TB_2 +#define DMACCRSA_2 DMAC.CRSA_2 +#define DMACCRDA_2 DMAC.CRDA_2 +#define DMACCRTB_2 DMAC.CRTB_2 +#define DMACCHSTAT_2 DMAC.CHSTAT_2 +#define DMACCHCTRL_2 DMAC.CHCTRL_2 +#define DMACCHCFG_2 DMAC.CHCFG_2 +#define DMACCHITVL_2 DMAC.CHITVL_2 +#define DMACCHEXT_2 DMAC.CHEXT_2 +#define DMACNXLA_2 DMAC.NXLA_2 +#define DMACCRLA_2 DMAC.CRLA_2 +#define DMACN0SA_3 DMAC.N0SA_3 +#define DMACN0DA_3 DMAC.N0DA_3 +#define DMACN0TB_3 DMAC.N0TB_3 +#define DMACN1SA_3 DMAC.N1SA_3 +#define DMACN1DA_3 DMAC.N1DA_3 +#define DMACN1TB_3 DMAC.N1TB_3 +#define DMACCRSA_3 DMAC.CRSA_3 +#define DMACCRDA_3 DMAC.CRDA_3 +#define DMACCRTB_3 DMAC.CRTB_3 +#define DMACCHSTAT_3 DMAC.CHSTAT_3 +#define DMACCHCTRL_3 DMAC.CHCTRL_3 +#define DMACCHCFG_3 DMAC.CHCFG_3 +#define DMACCHITVL_3 DMAC.CHITVL_3 +#define DMACCHEXT_3 DMAC.CHEXT_3 +#define DMACNXLA_3 DMAC.NXLA_3 +#define DMACCRLA_3 DMAC.CRLA_3 +#define DMACN0SA_4 DMAC.N0SA_4 +#define DMACN0DA_4 DMAC.N0DA_4 +#define DMACN0TB_4 DMAC.N0TB_4 +#define DMACN1SA_4 DMAC.N1SA_4 +#define DMACN1DA_4 DMAC.N1DA_4 +#define DMACN1TB_4 DMAC.N1TB_4 +#define DMACCRSA_4 DMAC.CRSA_4 +#define DMACCRDA_4 DMAC.CRDA_4 +#define DMACCRTB_4 DMAC.CRTB_4 +#define DMACCHSTAT_4 DMAC.CHSTAT_4 +#define DMACCHCTRL_4 DMAC.CHCTRL_4 +#define DMACCHCFG_4 DMAC.CHCFG_4 +#define DMACCHITVL_4 DMAC.CHITVL_4 +#define DMACCHEXT_4 DMAC.CHEXT_4 +#define DMACNXLA_4 DMAC.NXLA_4 +#define DMACCRLA_4 DMAC.CRLA_4 +#define DMACN0SA_5 DMAC.N0SA_5 +#define DMACN0DA_5 DMAC.N0DA_5 +#define DMACN0TB_5 DMAC.N0TB_5 +#define DMACN1SA_5 DMAC.N1SA_5 +#define DMACN1DA_5 DMAC.N1DA_5 +#define DMACN1TB_5 DMAC.N1TB_5 +#define DMACCRSA_5 DMAC.CRSA_5 +#define DMACCRDA_5 DMAC.CRDA_5 +#define DMACCRTB_5 DMAC.CRTB_5 +#define DMACCHSTAT_5 DMAC.CHSTAT_5 +#define DMACCHCTRL_5 DMAC.CHCTRL_5 +#define DMACCHCFG_5 DMAC.CHCFG_5 +#define DMACCHITVL_5 DMAC.CHITVL_5 +#define DMACCHEXT_5 DMAC.CHEXT_5 +#define DMACNXLA_5 DMAC.NXLA_5 +#define DMACCRLA_5 DMAC.CRLA_5 +#define DMACN0SA_6 DMAC.N0SA_6 +#define DMACN0DA_6 DMAC.N0DA_6 +#define DMACN0TB_6 DMAC.N0TB_6 +#define DMACN1SA_6 DMAC.N1SA_6 +#define DMACN1DA_6 DMAC.N1DA_6 +#define DMACN1TB_6 DMAC.N1TB_6 +#define DMACCRSA_6 DMAC.CRSA_6 +#define DMACCRDA_6 DMAC.CRDA_6 +#define DMACCRTB_6 DMAC.CRTB_6 +#define DMACCHSTAT_6 DMAC.CHSTAT_6 +#define DMACCHCTRL_6 DMAC.CHCTRL_6 +#define DMACCHCFG_6 DMAC.CHCFG_6 +#define DMACCHITVL_6 DMAC.CHITVL_6 +#define DMACCHEXT_6 DMAC.CHEXT_6 +#define DMACNXLA_6 DMAC.NXLA_6 +#define DMACCRLA_6 DMAC.CRLA_6 +#define DMACN0SA_7 DMAC.N0SA_7 +#define DMACN0DA_7 DMAC.N0DA_7 +#define DMACN0TB_7 DMAC.N0TB_7 +#define DMACN1SA_7 DMAC.N1SA_7 +#define DMACN1DA_7 DMAC.N1DA_7 +#define DMACN1TB_7 DMAC.N1TB_7 +#define DMACCRSA_7 DMAC.CRSA_7 +#define DMACCRDA_7 DMAC.CRDA_7 +#define DMACCRTB_7 DMAC.CRTB_7 +#define DMACCHSTAT_7 DMAC.CHSTAT_7 +#define DMACCHCTRL_7 DMAC.CHCTRL_7 +#define DMACCHCFG_7 DMAC.CHCFG_7 +#define DMACCHITVL_7 DMAC.CHITVL_7 +#define DMACCHEXT_7 DMAC.CHEXT_7 +#define DMACNXLA_7 DMAC.NXLA_7 +#define DMACCRLA_7 DMAC.CRLA_7 +#define DMACDCTRL_0_7 DMAC.DCTRL_0_7 +#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7 +#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7 +#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7 +#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7 +#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7 +#define DMACN0SA_8 DMAC.N0SA_8 +#define DMACN0DA_8 DMAC.N0DA_8 +#define DMACN0TB_8 DMAC.N0TB_8 +#define DMACN1SA_8 DMAC.N1SA_8 +#define DMACN1DA_8 DMAC.N1DA_8 +#define DMACN1TB_8 DMAC.N1TB_8 +#define DMACCRSA_8 DMAC.CRSA_8 +#define DMACCRDA_8 DMAC.CRDA_8 +#define DMACCRTB_8 DMAC.CRTB_8 +#define DMACCHSTAT_8 DMAC.CHSTAT_8 +#define DMACCHCTRL_8 DMAC.CHCTRL_8 +#define DMACCHCFG_8 DMAC.CHCFG_8 +#define DMACCHITVL_8 DMAC.CHITVL_8 +#define DMACCHEXT_8 DMAC.CHEXT_8 +#define DMACNXLA_8 DMAC.NXLA_8 +#define DMACCRLA_8 DMAC.CRLA_8 +#define DMACN0SA_9 DMAC.N0SA_9 +#define DMACN0DA_9 DMAC.N0DA_9 +#define DMACN0TB_9 DMAC.N0TB_9 +#define DMACN1SA_9 DMAC.N1SA_9 +#define DMACN1DA_9 DMAC.N1DA_9 +#define DMACN1TB_9 DMAC.N1TB_9 +#define DMACCRSA_9 DMAC.CRSA_9 +#define DMACCRDA_9 DMAC.CRDA_9 +#define DMACCRTB_9 DMAC.CRTB_9 +#define DMACCHSTAT_9 DMAC.CHSTAT_9 +#define DMACCHCTRL_9 DMAC.CHCTRL_9 +#define DMACCHCFG_9 DMAC.CHCFG_9 +#define DMACCHITVL_9 DMAC.CHITVL_9 +#define DMACCHEXT_9 DMAC.CHEXT_9 +#define DMACNXLA_9 DMAC.NXLA_9 +#define DMACCRLA_9 DMAC.CRLA_9 +#define DMACN0SA_10 DMAC.N0SA_10 +#define DMACN0DA_10 DMAC.N0DA_10 +#define DMACN0TB_10 DMAC.N0TB_10 +#define DMACN1SA_10 DMAC.N1SA_10 +#define DMACN1DA_10 DMAC.N1DA_10 +#define DMACN1TB_10 DMAC.N1TB_10 +#define DMACCRSA_10 DMAC.CRSA_10 +#define DMACCRDA_10 DMAC.CRDA_10 +#define DMACCRTB_10 DMAC.CRTB_10 +#define DMACCHSTAT_10 DMAC.CHSTAT_10 +#define DMACCHCTRL_10 DMAC.CHCTRL_10 +#define DMACCHCFG_10 DMAC.CHCFG_10 +#define DMACCHITVL_10 DMAC.CHITVL_10 +#define DMACCHEXT_10 DMAC.CHEXT_10 +#define DMACNXLA_10 DMAC.NXLA_10 +#define DMACCRLA_10 DMAC.CRLA_10 +#define DMACN0SA_11 DMAC.N0SA_11 +#define DMACN0DA_11 DMAC.N0DA_11 +#define DMACN0TB_11 DMAC.N0TB_11 +#define DMACN1SA_11 DMAC.N1SA_11 +#define DMACN1DA_11 DMAC.N1DA_11 +#define DMACN1TB_11 DMAC.N1TB_11 +#define DMACCRSA_11 DMAC.CRSA_11 +#define DMACCRDA_11 DMAC.CRDA_11 +#define DMACCRTB_11 DMAC.CRTB_11 +#define DMACCHSTAT_11 DMAC.CHSTAT_11 +#define DMACCHCTRL_11 DMAC.CHCTRL_11 +#define DMACCHCFG_11 DMAC.CHCFG_11 +#define DMACCHITVL_11 DMAC.CHITVL_11 +#define DMACCHEXT_11 DMAC.CHEXT_11 +#define DMACNXLA_11 DMAC.NXLA_11 +#define DMACCRLA_11 DMAC.CRLA_11 +#define DMACN0SA_12 DMAC.N0SA_12 +#define DMACN0DA_12 DMAC.N0DA_12 +#define DMACN0TB_12 DMAC.N0TB_12 +#define DMACN1SA_12 DMAC.N1SA_12 +#define DMACN1DA_12 DMAC.N1DA_12 +#define DMACN1TB_12 DMAC.N1TB_12 +#define DMACCRSA_12 DMAC.CRSA_12 +#define DMACCRDA_12 DMAC.CRDA_12 +#define DMACCRTB_12 DMAC.CRTB_12 +#define DMACCHSTAT_12 DMAC.CHSTAT_12 +#define DMACCHCTRL_12 DMAC.CHCTRL_12 +#define DMACCHCFG_12 DMAC.CHCFG_12 +#define DMACCHITVL_12 DMAC.CHITVL_12 +#define DMACCHEXT_12 DMAC.CHEXT_12 +#define DMACNXLA_12 DMAC.NXLA_12 +#define DMACCRLA_12 DMAC.CRLA_12 +#define DMACN0SA_13 DMAC.N0SA_13 +#define DMACN0DA_13 DMAC.N0DA_13 +#define DMACN0TB_13 DMAC.N0TB_13 +#define DMACN1SA_13 DMAC.N1SA_13 +#define DMACN1DA_13 DMAC.N1DA_13 +#define DMACN1TB_13 DMAC.N1TB_13 +#define DMACCRSA_13 DMAC.CRSA_13 +#define DMACCRDA_13 DMAC.CRDA_13 +#define DMACCRTB_13 DMAC.CRTB_13 +#define DMACCHSTAT_13 DMAC.CHSTAT_13 +#define DMACCHCTRL_13 DMAC.CHCTRL_13 +#define DMACCHCFG_13 DMAC.CHCFG_13 +#define DMACCHITVL_13 DMAC.CHITVL_13 +#define DMACCHEXT_13 DMAC.CHEXT_13 +#define DMACNXLA_13 DMAC.NXLA_13 +#define DMACCRLA_13 DMAC.CRLA_13 +#define DMACN0SA_14 DMAC.N0SA_14 +#define DMACN0DA_14 DMAC.N0DA_14 +#define DMACN0TB_14 DMAC.N0TB_14 +#define DMACN1SA_14 DMAC.N1SA_14 +#define DMACN1DA_14 DMAC.N1DA_14 +#define DMACN1TB_14 DMAC.N1TB_14 +#define DMACCRSA_14 DMAC.CRSA_14 +#define DMACCRDA_14 DMAC.CRDA_14 +#define DMACCRTB_14 DMAC.CRTB_14 +#define DMACCHSTAT_14 DMAC.CHSTAT_14 +#define DMACCHCTRL_14 DMAC.CHCTRL_14 +#define DMACCHCFG_14 DMAC.CHCFG_14 +#define DMACCHITVL_14 DMAC.CHITVL_14 +#define DMACCHEXT_14 DMAC.CHEXT_14 +#define DMACNXLA_14 DMAC.NXLA_14 +#define DMACCRLA_14 DMAC.CRLA_14 +#define DMACN0SA_15 DMAC.N0SA_15 +#define DMACN0DA_15 DMAC.N0DA_15 +#define DMACN0TB_15 DMAC.N0TB_15 +#define DMACN1SA_15 DMAC.N1SA_15 +#define DMACN1DA_15 DMAC.N1DA_15 +#define DMACN1TB_15 DMAC.N1TB_15 +#define DMACCRSA_15 DMAC.CRSA_15 +#define DMACCRDA_15 DMAC.CRDA_15 +#define DMACCRTB_15 DMAC.CRTB_15 +#define DMACCHSTAT_15 DMAC.CHSTAT_15 +#define DMACCHCTRL_15 DMAC.CHCTRL_15 +#define DMACCHCFG_15 DMAC.CHCFG_15 +#define DMACCHITVL_15 DMAC.CHITVL_15 +#define DMACCHEXT_15 DMAC.CHEXT_15 +#define DMACNXLA_15 DMAC.NXLA_15 +#define DMACCRLA_15 DMAC.CRLA_15 +#define DMACDCTRL_8_15 DMAC.DCTRL_8_15 +#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15 +#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15 +#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15 +#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15 +#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15 +#define DMACDMARS0 DMAC.DMARS0 +#define DMACDMARS1 DMAC.DMARS1 +#define DMACDMARS2 DMAC.DMARS2 +#define DMACDMARS3 DMAC.DMARS3 +#define DMACDMARS4 DMAC.DMARS4 +#define DMACDMARS5 DMAC.DMARS5 +#define DMACDMARS6 DMAC.DMARS6 +#define DMACDMARS7 DMAC.DMARS7 +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dvdec_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dvdec_iodefine.h new file mode 100644 index 0000000000..6c28acb009 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dvdec_iodefine.h @@ -0,0 +1,391 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : dvdec_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef DVDEC_IODEFINE_H +#define DVDEC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_dvdec +{ /* DVDEC */ + volatile uint16_t ADCCR1; /* ADCCR1 */ + volatile uint8_t dummy1[4]; /* */ +#define DVDEC_TGCRn_COUNT 3 + volatile uint16_t TGCR1; /* TGCR1 */ + volatile uint16_t TGCR2; /* TGCR2 */ + volatile uint16_t TGCR3; /* TGCR3 */ + volatile uint8_t dummy2[6]; /* */ +#define DVDEC_SYNSCRn_COUNT 5 + volatile uint16_t SYNSCR1; /* SYNSCR1 */ + volatile uint16_t SYNSCR2; /* SYNSCR2 */ + volatile uint16_t SYNSCR3; /* SYNSCR3 */ + volatile uint16_t SYNSCR4; /* SYNSCR4 */ + volatile uint16_t SYNSCR5; /* SYNSCR5 */ +#define DVDEC_HAFCCRn_COUNT 3 + volatile uint16_t HAFCCR1; /* HAFCCR1 */ + volatile uint16_t HAFCCR2; /* HAFCCR2 */ + volatile uint16_t HAFCCR3; /* HAFCCR3 */ + volatile uint16_t VCDWCR1; /* VCDWCR1 */ + volatile uint8_t dummy3[4]; /* */ +#define DVDEC_DCPCRn_COUNT 8 + volatile uint16_t DCPCR1; /* DCPCR1 */ + volatile uint16_t DCPCR2; /* DCPCR2 */ + volatile uint16_t DCPCR3; /* DCPCR3 */ + volatile uint16_t DCPCR4; /* DCPCR4 */ + volatile uint16_t DCPCR5; /* DCPCR5 */ + volatile uint16_t DCPCR6; /* DCPCR6 */ + volatile uint16_t DCPCR7; /* DCPCR7 */ + volatile uint16_t DCPCR8; /* DCPCR8 */ + volatile uint16_t NSDCR; /* NSDCR */ + volatile uint16_t BTLCR; /* BTLCR */ + volatile uint16_t BTGPCR; /* BTGPCR */ +#define DVDEC_ACCCRn_COUNT 3 + volatile uint16_t ACCCR1; /* ACCCR1 */ + volatile uint16_t ACCCR2; /* ACCCR2 */ + volatile uint16_t ACCCR3; /* ACCCR3 */ + volatile uint16_t TINTCR; /* TINTCR */ + volatile uint16_t YCDCR; /* YCDCR */ +#define DVDEC_AGCCRn_COUNT 2 + volatile uint16_t AGCCR1; /* AGCCR1 */ + volatile uint16_t AGCCR2; /* AGCCR2 */ + volatile uint16_t PKLIMITCR; /* PKLIMITCR */ +#define DVDEC_RGORCRn_COUNT 7 + volatile uint16_t RGORCR1; /* RGORCR1 */ + volatile uint16_t RGORCR2; /* RGORCR2 */ + volatile uint16_t RGORCR3; /* RGORCR3 */ + volatile uint16_t RGORCR4; /* RGORCR4 */ + volatile uint16_t RGORCR5; /* RGORCR5 */ + volatile uint16_t RGORCR6; /* RGORCR6 */ + volatile uint16_t RGORCR7; /* RGORCR7 */ + volatile uint8_t dummy4[24]; /* */ + volatile uint16_t AFCPFCR; /* AFCPFCR */ + volatile uint16_t RUPDCR; /* RUPDCR */ + volatile uint16_t VSYNCSR; /* VSYNCSR */ + volatile uint16_t HSYNCSR; /* HSYNCSR */ +#define DVDEC_DCPSRn_COUNT 2 + volatile uint16_t DCPSR1; /* DCPSR1 */ + volatile uint16_t DCPSR2; /* DCPSR2 */ + volatile uint8_t dummy5[4]; /* */ + volatile uint16_t NSDSR; /* NSDSR */ +#define DVDEC_CROMASRn_COUNT 2 + volatile uint16_t CROMASR1; /* CROMASR1 */ + volatile uint16_t CROMASR2; /* CROMASR2 */ + volatile uint16_t SYNCSSR; /* SYNCSSR */ +#define DVDEC_AGCCSRn_COUNT 2 + volatile uint16_t AGCCSR1; /* AGCCSR1 */ + volatile uint16_t AGCCSR2; /* AGCCSR2 */ + volatile uint8_t dummy6[108]; /* */ +#define DVDEC_YCSCRn_COUNT 7 + volatile uint16_t YCSCR3; /* YCSCR3 */ + volatile uint16_t YCSCR4; /* YCSCR4 */ + volatile uint16_t YCSCR5; /* YCSCR5 */ + volatile uint16_t YCSCR6; /* YCSCR6 */ + volatile uint16_t YCSCR7; /* YCSCR7 */ + volatile uint16_t YCSCR8; /* YCSCR8 */ + volatile uint16_t YCSCR9; /* YCSCR9 */ + volatile uint8_t dummy7[2]; /* */ + volatile uint16_t YCSCR11; /* YCSCR11 */ + volatile uint16_t YCSCR12; /* YCSCR12 */ + volatile uint8_t dummy8[104]; /* */ + volatile uint16_t DCPCR9; /* DCPCR9 */ + volatile uint8_t dummy9[16]; /* */ +#define DVDEC_YCTWA_Fn_COUNT 9 + volatile uint16_t YCTWA_F0; /* YCTWA_F0 */ + volatile uint16_t YCTWA_F1; /* YCTWA_F1 */ + volatile uint16_t YCTWA_F2; /* YCTWA_F2 */ + volatile uint16_t YCTWA_F3; /* YCTWA_F3 */ + volatile uint16_t YCTWA_F4; /* YCTWA_F4 */ + volatile uint16_t YCTWA_F5; /* YCTWA_F5 */ + volatile uint16_t YCTWA_F6; /* YCTWA_F6 */ + volatile uint16_t YCTWA_F7; /* YCTWA_F7 */ + volatile uint16_t YCTWA_F8; /* YCTWA_F8 */ +#define DVDEC_YCTWB_Fn_COUNT 9 + volatile uint16_t YCTWB_F0; /* YCTWB_F0 */ + volatile uint16_t YCTWB_F1; /* YCTWB_F1 */ + volatile uint16_t YCTWB_F2; /* YCTWB_F2 */ + volatile uint16_t YCTWB_F3; /* YCTWB_F3 */ + volatile uint16_t YCTWB_F4; /* YCTWB_F4 */ + volatile uint16_t YCTWB_F5; /* YCTWB_F5 */ + volatile uint16_t YCTWB_F6; /* YCTWB_F6 */ + volatile uint16_t YCTWB_F7; /* YCTWB_F7 */ + volatile uint16_t YCTWB_F8; /* YCTWB_F8 */ +#define DVDEC_YCTNA_Fn_COUNT 9 + volatile uint16_t YCTNA_F0; /* YCTNA_F0 */ + volatile uint16_t YCTNA_F1; /* YCTNA_F1 */ + volatile uint16_t YCTNA_F2; /* YCTNA_F2 */ + volatile uint16_t YCTNA_F3; /* YCTNA_F3 */ + volatile uint16_t YCTNA_F4; /* YCTNA_F4 */ + volatile uint16_t YCTNA_F5; /* YCTNA_F5 */ + volatile uint16_t YCTNA_F6; /* YCTNA_F6 */ + volatile uint16_t YCTNA_F7; /* YCTNA_F7 */ + volatile uint16_t YCTNA_F8; /* YCTNA_F8 */ +#define DVDEC_YCTNB_Fn_COUNT 9 + volatile uint16_t YCTNB_F0; /* YCTNB_F0 */ + volatile uint16_t YCTNB_F1; /* YCTNB_F1 */ + volatile uint16_t YCTNB_F2; /* YCTNB_F2 */ + volatile uint16_t YCTNB_F3; /* YCTNB_F3 */ + volatile uint16_t YCTNB_F4; /* YCTNB_F4 */ + volatile uint16_t YCTNB_F5; /* YCTNB_F5 */ + volatile uint16_t YCTNB_F6; /* YCTNB_F6 */ + volatile uint16_t YCTNB_F7; /* YCTNB_F7 */ + volatile uint16_t YCTNB_F8; /* YCTNB_F8 */ + volatile uint8_t dummy10[38]; /* */ + volatile uint16_t YGAINCR; /* YGAINCR */ + volatile uint16_t CBGAINCR; /* CBGAINCR */ + volatile uint16_t CRGAINCR; /* CRGAINCR */ + volatile uint8_t dummy11[122]; /* */ + volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */ + volatile uint16_t PGACR; /* PGACR */ + volatile uint16_t ADCCR2; /* ADCCR2 */ +}; + + +#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */ +#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */ + + +/* Start of channnel array defines of DVDEC */ + +/* Channnel array defines of DVDEC */ +/*(Sample) value = DVDEC[ channel ]->ADCCR1; */ +#define DVDEC_COUNT 2 +#define DVDEC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DVDEC0, &DVDEC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of DVDEC */ + + +#define ADCCR1_1 DVDEC1.ADCCR1 +#define TGCR1_1 DVDEC1.TGCR1 +#define TGCR2_1 DVDEC1.TGCR2 +#define TGCR3_1 DVDEC1.TGCR3 +#define SYNSCR1_1 DVDEC1.SYNSCR1 +#define SYNSCR2_1 DVDEC1.SYNSCR2 +#define SYNSCR3_1 DVDEC1.SYNSCR3 +#define SYNSCR4_1 DVDEC1.SYNSCR4 +#define SYNSCR5_1 DVDEC1.SYNSCR5 +#define HAFCCR1_1 DVDEC1.HAFCCR1 +#define HAFCCR2_1 DVDEC1.HAFCCR2 +#define HAFCCR3_1 DVDEC1.HAFCCR3 +#define VCDWCR1_1 DVDEC1.VCDWCR1 +#define DCPCR1_1 DVDEC1.DCPCR1 +#define DCPCR2_1 DVDEC1.DCPCR2 +#define DCPCR3_1 DVDEC1.DCPCR3 +#define DCPCR4_1 DVDEC1.DCPCR4 +#define DCPCR5_1 DVDEC1.DCPCR5 +#define DCPCR6_1 DVDEC1.DCPCR6 +#define DCPCR7_1 DVDEC1.DCPCR7 +#define DCPCR8_1 DVDEC1.DCPCR8 +#define NSDCR_1 DVDEC1.NSDCR +#define BTLCR_1 DVDEC1.BTLCR +#define BTGPCR_1 DVDEC1.BTGPCR +#define ACCCR1_1 DVDEC1.ACCCR1 +#define ACCCR2_1 DVDEC1.ACCCR2 +#define ACCCR3_1 DVDEC1.ACCCR3 +#define TINTCR_1 DVDEC1.TINTCR +#define YCDCR_1 DVDEC1.YCDCR +#define AGCCR1_1 DVDEC1.AGCCR1 +#define AGCCR2_1 DVDEC1.AGCCR2 +#define PKLIMITCR_1 DVDEC1.PKLIMITCR +#define RGORCR1_1 DVDEC1.RGORCR1 +#define RGORCR2_1 DVDEC1.RGORCR2 +#define RGORCR3_1 DVDEC1.RGORCR3 +#define RGORCR4_1 DVDEC1.RGORCR4 +#define RGORCR5_1 DVDEC1.RGORCR5 +#define RGORCR6_1 DVDEC1.RGORCR6 +#define RGORCR7_1 DVDEC1.RGORCR7 +#define AFCPFCR_1 DVDEC1.AFCPFCR +#define RUPDCR_1 DVDEC1.RUPDCR +#define VSYNCSR_1 DVDEC1.VSYNCSR +#define HSYNCSR_1 DVDEC1.HSYNCSR +#define DCPSR1_1 DVDEC1.DCPSR1 +#define DCPSR2_1 DVDEC1.DCPSR2 +#define NSDSR_1 DVDEC1.NSDSR +#define CROMASR1_1 DVDEC1.CROMASR1 +#define CROMASR2_1 DVDEC1.CROMASR2 +#define SYNCSSR_1 DVDEC1.SYNCSSR +#define AGCCSR1_1 DVDEC1.AGCCSR1 +#define AGCCSR2_1 DVDEC1.AGCCSR2 +#define YCSCR3_1 DVDEC1.YCSCR3 +#define YCSCR4_1 DVDEC1.YCSCR4 +#define YCSCR5_1 DVDEC1.YCSCR5 +#define YCSCR6_1 DVDEC1.YCSCR6 +#define YCSCR7_1 DVDEC1.YCSCR7 +#define YCSCR8_1 DVDEC1.YCSCR8 +#define YCSCR9_1 DVDEC1.YCSCR9 +#define YCSCR11_1 DVDEC1.YCSCR11 +#define YCSCR12_1 DVDEC1.YCSCR12 +#define DCPCR9_1 DVDEC1.DCPCR9 +#define YCTWA_F0_1 DVDEC1.YCTWA_F0 +#define YCTWA_F1_1 DVDEC1.YCTWA_F1 +#define YCTWA_F2_1 DVDEC1.YCTWA_F2 +#define YCTWA_F3_1 DVDEC1.YCTWA_F3 +#define YCTWA_F4_1 DVDEC1.YCTWA_F4 +#define YCTWA_F5_1 DVDEC1.YCTWA_F5 +#define YCTWA_F6_1 DVDEC1.YCTWA_F6 +#define YCTWA_F7_1 DVDEC1.YCTWA_F7 +#define YCTWA_F8_1 DVDEC1.YCTWA_F8 +#define YCTWB_F0_1 DVDEC1.YCTWB_F0 +#define YCTWB_F1_1 DVDEC1.YCTWB_F1 +#define YCTWB_F2_1 DVDEC1.YCTWB_F2 +#define YCTWB_F3_1 DVDEC1.YCTWB_F3 +#define YCTWB_F4_1 DVDEC1.YCTWB_F4 +#define YCTWB_F5_1 DVDEC1.YCTWB_F5 +#define YCTWB_F6_1 DVDEC1.YCTWB_F6 +#define YCTWB_F7_1 DVDEC1.YCTWB_F7 +#define YCTWB_F8_1 DVDEC1.YCTWB_F8 +#define YCTNA_F0_1 DVDEC1.YCTNA_F0 +#define YCTNA_F1_1 DVDEC1.YCTNA_F1 +#define YCTNA_F2_1 DVDEC1.YCTNA_F2 +#define YCTNA_F3_1 DVDEC1.YCTNA_F3 +#define YCTNA_F4_1 DVDEC1.YCTNA_F4 +#define YCTNA_F5_1 DVDEC1.YCTNA_F5 +#define YCTNA_F6_1 DVDEC1.YCTNA_F6 +#define YCTNA_F7_1 DVDEC1.YCTNA_F7 +#define YCTNA_F8_1 DVDEC1.YCTNA_F8 +#define YCTNB_F0_1 DVDEC1.YCTNB_F0 +#define YCTNB_F1_1 DVDEC1.YCTNB_F1 +#define YCTNB_F2_1 DVDEC1.YCTNB_F2 +#define YCTNB_F3_1 DVDEC1.YCTNB_F3 +#define YCTNB_F4_1 DVDEC1.YCTNB_F4 +#define YCTNB_F5_1 DVDEC1.YCTNB_F5 +#define YCTNB_F6_1 DVDEC1.YCTNB_F6 +#define YCTNB_F7_1 DVDEC1.YCTNB_F7 +#define YCTNB_F8_1 DVDEC1.YCTNB_F8 +#define YGAINCR_1 DVDEC1.YGAINCR +#define CBGAINCR_1 DVDEC1.CBGAINCR +#define CRGAINCR_1 DVDEC1.CRGAINCR +#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE +#define PGACR_1 DVDEC1.PGACR +#define ADCCR2_1 DVDEC1.ADCCR2 +#define ADCCR1_0 DVDEC0.ADCCR1 +#define TGCR1_0 DVDEC0.TGCR1 +#define TGCR2_0 DVDEC0.TGCR2 +#define TGCR3_0 DVDEC0.TGCR3 +#define SYNSCR1_0 DVDEC0.SYNSCR1 +#define SYNSCR2_0 DVDEC0.SYNSCR2 +#define SYNSCR3_0 DVDEC0.SYNSCR3 +#define SYNSCR4_0 DVDEC0.SYNSCR4 +#define SYNSCR5_0 DVDEC0.SYNSCR5 +#define HAFCCR1_0 DVDEC0.HAFCCR1 +#define HAFCCR2_0 DVDEC0.HAFCCR2 +#define HAFCCR3_0 DVDEC0.HAFCCR3 +#define VCDWCR1_0 DVDEC0.VCDWCR1 +#define DCPCR1_0 DVDEC0.DCPCR1 +#define DCPCR2_0 DVDEC0.DCPCR2 +#define DCPCR3_0 DVDEC0.DCPCR3 +#define DCPCR4_0 DVDEC0.DCPCR4 +#define DCPCR5_0 DVDEC0.DCPCR5 +#define DCPCR6_0 DVDEC0.DCPCR6 +#define DCPCR7_0 DVDEC0.DCPCR7 +#define DCPCR8_0 DVDEC0.DCPCR8 +#define NSDCR_0 DVDEC0.NSDCR +#define BTLCR_0 DVDEC0.BTLCR +#define BTGPCR_0 DVDEC0.BTGPCR +#define ACCCR1_0 DVDEC0.ACCCR1 +#define ACCCR2_0 DVDEC0.ACCCR2 +#define ACCCR3_0 DVDEC0.ACCCR3 +#define TINTCR_0 DVDEC0.TINTCR +#define YCDCR_0 DVDEC0.YCDCR +#define AGCCR1_0 DVDEC0.AGCCR1 +#define AGCCR2_0 DVDEC0.AGCCR2 +#define PKLIMITCR_0 DVDEC0.PKLIMITCR +#define RGORCR1_0 DVDEC0.RGORCR1 +#define RGORCR2_0 DVDEC0.RGORCR2 +#define RGORCR3_0 DVDEC0.RGORCR3 +#define RGORCR4_0 DVDEC0.RGORCR4 +#define RGORCR5_0 DVDEC0.RGORCR5 +#define RGORCR6_0 DVDEC0.RGORCR6 +#define RGORCR7_0 DVDEC0.RGORCR7 +#define AFCPFCR_0 DVDEC0.AFCPFCR +#define RUPDCR_0 DVDEC0.RUPDCR +#define VSYNCSR_0 DVDEC0.VSYNCSR +#define HSYNCSR_0 DVDEC0.HSYNCSR +#define DCPSR1_0 DVDEC0.DCPSR1 +#define DCPSR2_0 DVDEC0.DCPSR2 +#define NSDSR_0 DVDEC0.NSDSR +#define CROMASR1_0 DVDEC0.CROMASR1 +#define CROMASR2_0 DVDEC0.CROMASR2 +#define SYNCSSR_0 DVDEC0.SYNCSSR +#define AGCCSR1_0 DVDEC0.AGCCSR1 +#define AGCCSR2_0 DVDEC0.AGCCSR2 +#define YCSCR3_0 DVDEC0.YCSCR3 +#define YCSCR4_0 DVDEC0.YCSCR4 +#define YCSCR5_0 DVDEC0.YCSCR5 +#define YCSCR6_0 DVDEC0.YCSCR6 +#define YCSCR7_0 DVDEC0.YCSCR7 +#define YCSCR8_0 DVDEC0.YCSCR8 +#define YCSCR9_0 DVDEC0.YCSCR9 +#define YCSCR11_0 DVDEC0.YCSCR11 +#define YCSCR12_0 DVDEC0.YCSCR12 +#define DCPCR9_0 DVDEC0.DCPCR9 +#define YCTWA_F0_0 DVDEC0.YCTWA_F0 +#define YCTWA_F1_0 DVDEC0.YCTWA_F1 +#define YCTWA_F2_0 DVDEC0.YCTWA_F2 +#define YCTWA_F3_0 DVDEC0.YCTWA_F3 +#define YCTWA_F4_0 DVDEC0.YCTWA_F4 +#define YCTWA_F5_0 DVDEC0.YCTWA_F5 +#define YCTWA_F6_0 DVDEC0.YCTWA_F6 +#define YCTWA_F7_0 DVDEC0.YCTWA_F7 +#define YCTWA_F8_0 DVDEC0.YCTWA_F8 +#define YCTWB_F0_0 DVDEC0.YCTWB_F0 +#define YCTWB_F1_0 DVDEC0.YCTWB_F1 +#define YCTWB_F2_0 DVDEC0.YCTWB_F2 +#define YCTWB_F3_0 DVDEC0.YCTWB_F3 +#define YCTWB_F4_0 DVDEC0.YCTWB_F4 +#define YCTWB_F5_0 DVDEC0.YCTWB_F5 +#define YCTWB_F6_0 DVDEC0.YCTWB_F6 +#define YCTWB_F7_0 DVDEC0.YCTWB_F7 +#define YCTWB_F8_0 DVDEC0.YCTWB_F8 +#define YCTNA_F0_0 DVDEC0.YCTNA_F0 +#define YCTNA_F1_0 DVDEC0.YCTNA_F1 +#define YCTNA_F2_0 DVDEC0.YCTNA_F2 +#define YCTNA_F3_0 DVDEC0.YCTNA_F3 +#define YCTNA_F4_0 DVDEC0.YCTNA_F4 +#define YCTNA_F5_0 DVDEC0.YCTNA_F5 +#define YCTNA_F6_0 DVDEC0.YCTNA_F6 +#define YCTNA_F7_0 DVDEC0.YCTNA_F7 +#define YCTNA_F8_0 DVDEC0.YCTNA_F8 +#define YCTNB_F0_0 DVDEC0.YCTNB_F0 +#define YCTNB_F1_0 DVDEC0.YCTNB_F1 +#define YCTNB_F2_0 DVDEC0.YCTNB_F2 +#define YCTNB_F3_0 DVDEC0.YCTNB_F3 +#define YCTNB_F4_0 DVDEC0.YCTNB_F4 +#define YCTNB_F5_0 DVDEC0.YCTNB_F5 +#define YCTNB_F6_0 DVDEC0.YCTNB_F6 +#define YCTNB_F7_0 DVDEC0.YCTNB_F7 +#define YCTNB_F8_0 DVDEC0.YCTNB_F8 +#define YGAINCR_0 DVDEC0.YGAINCR +#define CBGAINCR_0 DVDEC0.CBGAINCR +#define CRGAINCR_0 DVDEC0.CRGAINCR +#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE +#define PGACR_0 DVDEC0.PGACR +#define ADCCR2_0 DVDEC0.ADCCR2 +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ether_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ether_iodefine.h new file mode 100644 index 0000000000..88b268ec7d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ether_iodefine.h @@ -0,0 +1,427 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ether_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef ETHER_IODEFINE_H +#define ETHER_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_ether +{ /* ETHER */ + volatile uint32_t EDSR0; /* EDSR0 */ + volatile uint8_t dummy207[12]; /* */ + volatile uint32_t TDLAR0; /* TDLAR0 */ + volatile uint32_t TDFAR0; /* TDFAR0 */ + volatile uint32_t TDFXR0; /* TDFXR0 */ + volatile uint32_t TDFFR0; /* TDFFR0 */ + volatile uint8_t dummy208[16]; /* */ + volatile uint32_t RDLAR0; /* RDLAR0 */ + volatile uint32_t RDFAR0; /* RDFAR0 */ + volatile uint32_t RDFXR0; /* RDFXR0 */ + volatile uint32_t RDFFR0; /* RDFFR0 */ + volatile uint8_t dummy209[960]; /* */ + volatile uint32_t EDMR0; /* EDMR0 */ + volatile uint8_t dummy210[4]; /* */ + volatile uint32_t EDTRR0; /* EDTRR0 */ + volatile uint8_t dummy211[4]; /* */ + volatile uint32_t EDRRR0; /* EDRRR0 */ + volatile uint8_t dummy212[20]; /* */ + volatile uint32_t EESR0; /* EESR0 */ + volatile uint8_t dummy213[4]; /* */ + volatile uint32_t EESIPR0; /* EESIPR0 */ + volatile uint8_t dummy214[4]; /* */ + volatile uint32_t TRSCER0; /* TRSCER0 */ + volatile uint8_t dummy215[4]; /* */ + volatile uint32_t RMFCR0; /* RMFCR0 */ + volatile uint8_t dummy216[4]; /* */ + volatile uint32_t TFTR0; /* TFTR0 */ + volatile uint8_t dummy217[4]; /* */ + volatile uint32_t FDR0; /* FDR0 */ + volatile uint8_t dummy218[4]; /* */ + volatile uint32_t RMCR0; /* RMCR0 */ + volatile uint8_t dummy219[4]; /* */ + volatile uint32_t RPADIR0; /* RPADIR0 */ + volatile uint8_t dummy220[4]; /* */ + volatile uint32_t FCFTR0; /* FCFTR0 */ + volatile uint8_t dummy221[120]; /* */ + volatile uint32_t CSMR; /* CSMR */ + volatile uint32_t CSSBM; /* CSSBM */ + volatile uint32_t CSSMR; /* CSSMR */ + volatile uint8_t dummy222[16]; /* */ + volatile uint32_t ECMR0; /* ECMR0 */ + volatile uint8_t dummy223[4]; /* */ + volatile uint32_t RFLR0; /* RFLR0 */ + volatile uint8_t dummy224[4]; /* */ + volatile uint32_t ECSR0; /* ECSR0 */ + volatile uint8_t dummy225[4]; /* */ + volatile uint32_t ECSIPR0; /* ECSIPR0 */ + volatile uint8_t dummy226[4]; /* */ + volatile uint32_t PIR0; /* PIR0 */ + volatile uint8_t dummy227[48]; /* */ + volatile uint32_t APR0; /* APR0 */ + volatile uint32_t MPR0; /* MPR0 */ + volatile uint32_t PFTCR0; /* PFTCR0 */ + volatile uint32_t PFRCR0; /* PFRCR0 */ + volatile uint32_t TPAUSER0; /* TPAUSER0 */ + volatile uint8_t dummy228[88]; /* */ + volatile uint32_t MAHR0; /* MAHR0 */ + volatile uint8_t dummy229[4]; /* */ + volatile uint32_t MALR0; /* MALR0 */ + volatile uint8_t dummy230[372]; /* */ + volatile uint32_t CEFCR0; /* CEFCR0 */ + volatile uint8_t dummy231[4]; /* */ + volatile uint32_t FRECR0; /* FRECR0 */ + volatile uint8_t dummy232[4]; /* */ + volatile uint32_t TSFRCR0; /* TSFRCR0 */ + volatile uint8_t dummy233[4]; /* */ + volatile uint32_t TLFRCR0; /* TLFRCR0 */ + volatile uint8_t dummy234[4]; /* */ + volatile uint32_t RFCR0; /* RFCR0 */ + volatile uint8_t dummy235[20]; /* */ + volatile uint32_t MAFCR0; /* MAFCR0 */ + volatile uint8_t dummy236[4228]; /* */ + volatile uint32_t ARSTR; /* ARSTR */ + volatile uint32_t TSU_CTRST; /* TSU_CTRST */ + volatile uint8_t dummy237[80]; /* */ + volatile uint32_t TSU_VTAG0; /* TSU_VTAG0 */ + volatile uint8_t dummy238[4]; /* */ + volatile uint32_t TSU_ADSBSY; /* TSU_ADSBSY */ + volatile uint32_t TSU_TEN; /* TSU_TEN */ + volatile uint8_t dummy239[24]; /* */ + volatile uint32_t TXNLCR0; /* TXNLCR0 */ + volatile uint32_t TXALCR0; /* TXALCR0 */ + volatile uint32_t RXNLCR0; /* RXNLCR0 */ + volatile uint32_t RXALCR0; /* RXALCR0 */ + volatile uint8_t dummy240[112]; /* */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ + volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */ + volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */ + volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */ + volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */ + volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */ + volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */ + volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */ + volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */ + volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */ + volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */ + volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */ + volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */ + volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */ + volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */ + volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */ + volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */ + volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */ + volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */ + volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */ + volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */ + volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */ + volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */ + volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */ + volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */ + volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */ + volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */ + volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */ + volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */ + volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */ + volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */ + volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */ +/* end of struct st_ether_from_tsu_adrh0 */ +/* start of struct st_ether_from_tsu_adrh0 */ + volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */ + volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */ +/* end of struct st_ether_from_tsu_adrh0 */ +}; + + +struct st_ether_from_tsu_adrh0 +{ + volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ + volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ +}; + + +#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */ + + +/* Start of channnel array defines of ETHER */ + +/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */ +/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */ +#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT 32 +#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \ + ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \ + ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \ + ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */ +#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */ +#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */ +#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */ +#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */ +#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */ +#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */ +#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */ +#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */ +#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */ +#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */ +#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */ +#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */ +#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */ +#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */ +#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */ +#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */ +#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */ +#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */ +#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */ +#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */ +#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */ +#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */ +#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */ +#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */ +#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */ +#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */ +#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */ +#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */ +#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */ +#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */ +#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */ + +/* End of channnel array defines of ETHER */ + + +#define ETHEREDSR0 ETHER.EDSR0 +#define ETHERTDLAR0 ETHER.TDLAR0 +#define ETHERTDFAR0 ETHER.TDFAR0 +#define ETHERTDFXR0 ETHER.TDFXR0 +#define ETHERTDFFR0 ETHER.TDFFR0 +#define ETHERRDLAR0 ETHER.RDLAR0 +#define ETHERRDFAR0 ETHER.RDFAR0 +#define ETHERRDFXR0 ETHER.RDFXR0 +#define ETHERRDFFR0 ETHER.RDFFR0 +#define ETHEREDMR0 ETHER.EDMR0 +#define ETHEREDTRR0 ETHER.EDTRR0 +#define ETHEREDRRR0 ETHER.EDRRR0 +#define ETHEREESR0 ETHER.EESR0 +#define ETHEREESIPR0 ETHER.EESIPR0 +#define ETHERTRSCER0 ETHER.TRSCER0 +#define ETHERRMFCR0 ETHER.RMFCR0 +#define ETHERTFTR0 ETHER.TFTR0 +#define ETHERFDR0 ETHER.FDR0 +#define ETHERRMCR0 ETHER.RMCR0 +#define ETHERRPADIR0 ETHER.RPADIR0 +#define ETHERFCFTR0 ETHER.FCFTR0 +#define ETHERCSMR ETHER.CSMR +#define ETHERCSSBM ETHER.CSSBM +#define ETHERCSSMR ETHER.CSSMR +#define ETHERECMR0 ETHER.ECMR0 +#define ETHERRFLR0 ETHER.RFLR0 +#define ETHERECSR0 ETHER.ECSR0 +#define ETHERECSIPR0 ETHER.ECSIPR0 +#define ETHERPIR0 ETHER.PIR0 +#define ETHERAPR0 ETHER.APR0 +#define ETHERMPR0 ETHER.MPR0 +#define ETHERPFTCR0 ETHER.PFTCR0 +#define ETHERPFRCR0 ETHER.PFRCR0 +#define ETHERTPAUSER0 ETHER.TPAUSER0 +#define ETHERMAHR0 ETHER.MAHR0 +#define ETHERMALR0 ETHER.MALR0 +#define ETHERCEFCR0 ETHER.CEFCR0 +#define ETHERFRECR0 ETHER.FRECR0 +#define ETHERTSFRCR0 ETHER.TSFRCR0 +#define ETHERTLFRCR0 ETHER.TLFRCR0 +#define ETHERRFCR0 ETHER.RFCR0 +#define ETHERMAFCR0 ETHER.MAFCR0 +#define ETHERARSTR ETHER.ARSTR +#define ETHERTSU_CTRST ETHER.TSU_CTRST +#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0 +#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY +#define ETHERTSU_TEN ETHER.TSU_TEN +#define ETHERTXNLCR0 ETHER.TXNLCR0 +#define ETHERTXALCR0 ETHER.TXALCR0 +#define ETHERRXNLCR0 ETHER.RXNLCR0 +#define ETHERRXALCR0 ETHER.RXALCR0 +#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0 +#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0 +#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1 +#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1 +#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2 +#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2 +#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3 +#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3 +#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4 +#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4 +#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5 +#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5 +#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6 +#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6 +#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7 +#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7 +#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8 +#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8 +#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9 +#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9 +#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10 +#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10 +#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11 +#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11 +#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12 +#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12 +#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13 +#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13 +#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14 +#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14 +#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15 +#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15 +#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16 +#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16 +#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17 +#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17 +#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18 +#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18 +#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19 +#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19 +#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20 +#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20 +#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21 +#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21 +#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22 +#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22 +#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23 +#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23 +#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24 +#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24 +#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25 +#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25 +#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26 +#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26 +#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27 +#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27 +#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28 +#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28 +#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29 +#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29 +#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30 +#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30 +#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31 +#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31 +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/flctl_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/flctl_iodefine.h new file mode 100644 index 0000000000..3f8ec183c2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/flctl_iodefine.h @@ -0,0 +1,72 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : flctl_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef FLCTL_IODEFINE_H +#define FLCTL_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_flctl +{ /* FLCTL */ + volatile uint32_t FLCMNCR; /* FLCMNCR */ + volatile uint32_t FLCMDCR; /* FLCMDCR */ + volatile uint32_t FLCMCDR; /* FLCMCDR */ + volatile uint32_t FLADR; /* FLADR */ + volatile uint32_t FLDATAR; /* FLDATAR */ + volatile uint32_t FLDTCNTR; /* FLDTCNTR */ + volatile uint32_t FLINTDMACR; /* FLINTDMACR */ + volatile uint32_t FLBSYTMR; /* FLBSYTMR */ + volatile uint32_t FLBSYCNT; /* FLBSYCNT */ + volatile uint8_t dummy555[8]; /* */ + volatile uint8_t FLTRCR; /* FLTRCR */ + volatile uint8_t dummy556[15]; /* */ + volatile uint32_t FLADR2; /* FLADR2 */ + volatile uint8_t dummy557[16]; /* */ + volatile uint32_t FLDTFIFO; /* FLDTFIFO */ + volatile uint8_t dummy558[12]; /* */ + volatile uint32_t FLECFIFO; /* FLECFIFO */ +}; + + +#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */ + + +#define FLCTLFLCMNCR FLCTL.FLCMNCR +#define FLCTLFLCMDCR FLCTL.FLCMDCR +#define FLCTLFLCMCDR FLCTL.FLCMCDR +#define FLCTLFLADR FLCTL.FLADR +#define FLCTLFLDATAR FLCTL.FLDATAR +#define FLCTLFLDTCNTR FLCTL.FLDTCNTR +#define FLCTLFLINTDMACR FLCTL.FLINTDMACR +#define FLCTLFLBSYTMR FLCTL.FLBSYTMR +#define FLCTLFLBSYCNT FLCTL.FLBSYCNT +#define FLCTLFLTRCR FLCTL.FLTRCR +#define FLCTLFLADR2 FLCTL.FLADR2 +#define FLCTLFLDTFIFO FLCTL.FLDTFIFO +#define FLCTLFLECFIFO FLCTL.FLECFIFO +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/gpio_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/gpio_iodefine.h new file mode 100644 index 0000000000..8bedb518ff --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/gpio_iodefine.h @@ -0,0 +1,1074 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : gpio_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef GPIO_IODEFINE_H +#define GPIO_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_gpio +{ /* GPIO */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P1; /* P1 */ + volatile uint8_t dummy348[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P2; /* P2 */ + volatile uint8_t dummy349[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P3; /* P3 */ + volatile uint8_t dummy350[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P4; /* P4 */ + volatile uint8_t dummy351[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P5; /* P5 */ + volatile uint8_t dummy352[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P6; /* P6 */ + volatile uint8_t dummy353[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P7; /* P7 */ + volatile uint8_t dummy354[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P8; /* P8 */ + volatile uint8_t dummy355[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P9; /* P9 */ + volatile uint8_t dummy356[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P10; /* P10 */ + volatile uint8_t dummy357[2]; /* */ +/* end of struct st_gpio_from_p1 */ +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P11; /* P11 */ + volatile uint8_t dummy3580[2]; /* */ +/* end of struct st_gpio_from_p1 */ + volatile uint8_t dummy3581[212]; /* */ +#define GPIO_PSRn_COUNT 11 + volatile uint32_t PSR1; /* PSR1 */ + volatile uint32_t PSR2; /* PSR2 */ + volatile uint32_t PSR3; /* PSR3 */ + volatile uint32_t PSR4; /* PSR4 */ + volatile uint32_t PSR5; /* PSR5 */ + volatile uint32_t PSR6; /* PSR6 */ + volatile uint32_t PSR7; /* PSR7 */ + volatile uint32_t PSR8; /* PSR8 */ + volatile uint32_t PSR9; /* PSR9 */ + volatile uint32_t PSR10; /* PSR10 */ + volatile uint32_t PSR11; /* PSR11 */ + volatile uint8_t dummy359[208]; /* */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR0; /* PPR0 */ + volatile uint8_t dummy360[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR1; /* PPR1 */ + volatile uint8_t dummy361[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR2; /* PPR2 */ + volatile uint8_t dummy362[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR3; /* PPR3 */ + volatile uint8_t dummy363[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR4; /* PPR4 */ + volatile uint8_t dummy364[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR5; /* PPR5 */ + volatile uint8_t dummy365[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR6; /* PPR6 */ + volatile uint8_t dummy366[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR7; /* PPR7 */ + volatile uint8_t dummy367[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR8; /* PPR8 */ + volatile uint8_t dummy368[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR9; /* PPR9 */ + volatile uint8_t dummy369[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR10; /* PPR10 */ + volatile uint8_t dummy370[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR11; /* PPR11 */ + volatile uint8_t dummy3710[2]; /* */ +/* end of struct st_gpio_from_ppr0 */ + volatile uint8_t dummy3711[212]; /* */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM1; /* PM1 */ + volatile uint8_t dummy372[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM2; /* PM2 */ + volatile uint8_t dummy373[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM3; /* PM3 */ + volatile uint8_t dummy374[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM4; /* PM4 */ + volatile uint8_t dummy375[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM5; /* PM5 */ + volatile uint8_t dummy376[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM6; /* PM6 */ + volatile uint8_t dummy377[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM7; /* PM7 */ + volatile uint8_t dummy378[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM8; /* PM8 */ + volatile uint8_t dummy379[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM9; /* PM9 */ + volatile uint8_t dummy380[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM10; /* PM10 */ + volatile uint8_t dummy381[2]; /* */ +/* end of struct st_gpio_from_pm1 */ +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM11; /* PM11 */ + volatile uint8_t dummy3820[2]; /* */ +/* end of struct st_gpio_from_pm1 */ + volatile uint8_t dummy3821[208]; /* */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC0; /* PMC0 */ + volatile uint8_t dummy383[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC1; /* PMC1 */ + volatile uint8_t dummy384[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC2; /* PMC2 */ + volatile uint8_t dummy385[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC3; /* PMC3 */ + volatile uint8_t dummy386[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC4; /* PMC4 */ + volatile uint8_t dummy387[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC5; /* PMC5 */ + volatile uint8_t dummy388[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC6; /* PMC6 */ + volatile uint8_t dummy389[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC7; /* PMC7 */ + volatile uint8_t dummy390[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC8; /* PMC8 */ + volatile uint8_t dummy391[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC9; /* PMC9 */ + volatile uint8_t dummy392[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC10; /* PMC10 */ + volatile uint8_t dummy393[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC11; /* PMC11 */ + volatile uint8_t dummy3940[2]; /* */ +/* end of struct st_gpio_from_pmc0 */ + volatile uint8_t dummy3941[212]; /* */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC1; /* PFC1 */ + volatile uint8_t dummy395[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC2; /* PFC2 */ + volatile uint8_t dummy396[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC3; /* PFC3 */ + volatile uint8_t dummy397[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC4; /* PFC4 */ + volatile uint8_t dummy398[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC5; /* PFC5 */ + volatile uint8_t dummy399[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC6; /* PFC6 */ + volatile uint8_t dummy400[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC7; /* PFC7 */ + volatile uint8_t dummy401[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC8; /* PFC8 */ + volatile uint8_t dummy402[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC9; /* PFC9 */ + volatile uint8_t dummy403[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC10; /* PFC10 */ + volatile uint8_t dummy404[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC11; /* PFC11 */ + volatile uint8_t dummy4050[2]; /* */ +/* end of struct st_gpio_from_pfc1 */ + volatile uint8_t dummy4051[212]; /* */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE1; /* PFCE1 */ + volatile uint8_t dummy406[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE2; /* PFCE2 */ + volatile uint8_t dummy407[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE3; /* PFCE3 */ + volatile uint8_t dummy408[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE4; /* PFCE4 */ + volatile uint8_t dummy409[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE5; /* PFCE5 */ + volatile uint8_t dummy410[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE6; /* PFCE6 */ + volatile uint8_t dummy411[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE7; /* PFCE7 */ + volatile uint8_t dummy412[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE8; /* PFCE8 */ + volatile uint8_t dummy413[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE9; /* PFCE9 */ + volatile uint8_t dummy414[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE10; /* PFCE10 */ + volatile uint8_t dummy415[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE11; /* PFCE11 */ + volatile uint8_t dummy4160[2]; /* */ +/* end of struct st_gpio_from_pfce1 */ + volatile uint8_t dummy4161[212]; /* */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT1; /* PNOT1 */ + volatile uint8_t dummy417[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT2; /* PNOT2 */ + volatile uint8_t dummy418[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT3; /* PNOT3 */ + volatile uint8_t dummy419[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT4; /* PNOT4 */ + volatile uint8_t dummy420[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT5; /* PNOT5 */ + volatile uint8_t dummy421[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT6; /* PNOT6 */ + volatile uint8_t dummy422[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT7; /* PNOT7 */ + volatile uint8_t dummy423[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT8; /* PNOT8 */ + volatile uint8_t dummy424[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT9; /* PNOT9 */ + volatile uint8_t dummy425[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT10; /* PNOT10 */ + volatile uint8_t dummy426[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT11; /* PNOT11 */ + volatile uint8_t dummy4270[2]; /* */ +/* end of struct st_gpio_from_pnot1 */ + volatile uint8_t dummy4271[212]; /* */ +#define GPIO_PMSRn_COUNT 11 + volatile uint32_t PMSR1; /* PMSR1 */ + volatile uint32_t PMSR2; /* PMSR2 */ + volatile uint32_t PMSR3; /* PMSR3 */ + volatile uint32_t PMSR4; /* PMSR4 */ + volatile uint32_t PMSR5; /* PMSR5 */ + volatile uint32_t PMSR6; /* PMSR6 */ + volatile uint32_t PMSR7; /* PMSR7 */ + volatile uint32_t PMSR8; /* PMSR8 */ + volatile uint32_t PMSR9; /* PMSR9 */ + volatile uint32_t PMSR10; /* PMSR10 */ + volatile uint32_t PMSR11; /* PMSR11 */ + volatile uint8_t dummy428[208]; /* */ +#define GPIO_PMCSRn_COUNT 12 + volatile uint32_t PMCSR0; /* PMCSR0 */ + volatile uint32_t PMCSR1; /* PMCSR1 */ + volatile uint32_t PMCSR2; /* PMCSR2 */ + volatile uint32_t PMCSR3; /* PMCSR3 */ + volatile uint32_t PMCSR4; /* PMCSR4 */ + volatile uint32_t PMCSR5; /* PMCSR5 */ + volatile uint32_t PMCSR6; /* PMCSR6 */ + volatile uint32_t PMCSR7; /* PMCSR7 */ + volatile uint32_t PMCSR8; /* PMCSR8 */ + volatile uint32_t PMCSR9; /* PMCSR9 */ + volatile uint32_t PMCSR10; /* PMCSR10 */ + volatile uint32_t PMCSR11; /* PMCSR11 */ + volatile uint8_t dummy429[212]; /* */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE1; /* PFCAE1 */ + volatile uint8_t dummy430[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE2; /* PFCAE2 */ + volatile uint8_t dummy431[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE3; /* PFCAE3 */ + volatile uint8_t dummy432[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE4; /* PFCAE4 */ + volatile uint8_t dummy433[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE5; /* PFCAE5 */ + volatile uint8_t dummy434[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE6; /* PFCAE6 */ + volatile uint8_t dummy435[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE7; /* PFCAE7 */ + volatile uint8_t dummy436[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE8; /* PFCAE8 */ + volatile uint8_t dummy437[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE9; /* PFCAE9 */ + volatile uint8_t dummy438[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE10; /* PFCAE10 */ + volatile uint8_t dummy439[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE11; /* PFCAE11 */ + volatile uint8_t dummy4400[2]; /* */ +/* end of struct st_gpio_from_pfcae1 */ + volatile uint8_t dummy4401[464]; /* */ + volatile uint32_t SNCR; /* SNCR */ + volatile uint8_t dummy441[13308]; /* */ + volatile uint16_t PIBC0; /* PIBC0 */ + volatile uint8_t dummy442[2]; /* */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC1; /* PIBC1 */ + volatile uint8_t dummy443[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC2; /* PIBC2 */ + volatile uint8_t dummy444[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC3; /* PIBC3 */ + volatile uint8_t dummy445[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC4; /* PIBC4 */ + volatile uint8_t dummy446[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC5; /* PIBC5 */ + volatile uint8_t dummy447[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC6; /* PIBC6 */ + volatile uint8_t dummy448[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC7; /* PIBC7 */ + volatile uint8_t dummy449[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC8; /* PIBC8 */ + volatile uint8_t dummy450[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC9; /* PIBC9 */ + volatile uint8_t dummy451[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC10; /* PIBC10 */ + volatile uint8_t dummy452[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC11; /* PIBC11 */ + volatile uint8_t dummy4530[2]; /* */ +/* end of struct st_gpio_from_pibc1 */ + volatile uint8_t dummy4531[212]; /* */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC1; /* PBDC1 */ + volatile uint8_t dummy454[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC2; /* PBDC2 */ + volatile uint8_t dummy455[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC3; /* PBDC3 */ + volatile uint8_t dummy456[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC4; /* PBDC4 */ + volatile uint8_t dummy457[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC5; /* PBDC5 */ + volatile uint8_t dummy458[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC6; /* PBDC6 */ + volatile uint8_t dummy459[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC7; /* PBDC7 */ + volatile uint8_t dummy460[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC8; /* PBDC8 */ + volatile uint8_t dummy461[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC9; /* PBDC9 */ + volatile uint8_t dummy462[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC10; /* PBDC10 */ + volatile uint8_t dummy463[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC11; /* PBDC11 */ + volatile uint8_t dummy4640[2]; /* */ +/* end of struct st_gpio_from_pbdc1 */ + volatile uint8_t dummy4641[212]; /* */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC1; /* PIPC1 */ + volatile uint8_t dummy465[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC2; /* PIPC2 */ + volatile uint8_t dummy466[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC3; /* PIPC3 */ + volatile uint8_t dummy467[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC4; /* PIPC4 */ + volatile uint8_t dummy468[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC5; /* PIPC5 */ + volatile uint8_t dummy469[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC6; /* PIPC6 */ + volatile uint8_t dummy470[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC7; /* PIPC7 */ + volatile uint8_t dummy471[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC8; /* PIPC8 */ + volatile uint8_t dummy472[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC9; /* PIPC9 */ + volatile uint8_t dummy473[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC10; /* PIPC10 */ + volatile uint8_t dummy474[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC11; /* PIPC11 */ + volatile uint8_t dummy4750[2]; /* */ +/* end of struct st_gpio_from_pipc1 */ + volatile uint8_t dummy4751[2288]; /* */ + volatile uint16_t JPPR0; /* JPPR0 */ + volatile uint8_t dummy476[30]; /* */ + volatile uint16_t JPMC0; /* JPMC0 */ + volatile uint8_t dummy477[78]; /* */ + volatile uint32_t JPMCSR0; /* JPMCSR0 */ + volatile uint8_t dummy478[876]; /* */ + volatile uint16_t JPIBC0; /* JPIBC0 */ +}; + + +struct st_gpio_from_p1 +{ + volatile uint16_t P1; /* P1 */ + volatile uint8_t dummy1[3]; /* */ +}; + + +struct st_gpio_from_ppr0 +{ + volatile uint16_t PPR0; /* PPR0 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pm1 +{ + volatile uint16_t PM1; /* PM1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pmc0 +{ + volatile uint16_t PMC0; /* PMC0 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pfc1 +{ + volatile uint16_t PFC1; /* PFC1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pfce1 +{ + volatile uint16_t PFCE1; /* PFCE1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pnot1 +{ + volatile uint16_t PNOT1; /* PNOT1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pfcae1 +{ + volatile uint16_t PFCAE1; /* PFCAE1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pibc1 +{ + volatile uint16_t PIBC1; /* PIBC1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pbdc1 +{ + volatile uint16_t PBDC1; /* PBDC1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +struct st_gpio_from_pipc1 +{ + volatile uint16_t PIPC1; /* PIPC1 */ + volatile uint8_t dummy1[2]; /* */ +}; + + +#define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */ + +/* Start of channnel array defines of GPIO */ + +/* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */ +#define GPIO_FROM_PIPC1_ARRAY_COUNT 11 +#define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \ + &GPIO_FROM_PIPC9, &GPIO_FROM_PIPC10, &GPIO_FROM_PIPC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PIPC1 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC1) /* GPIO_FROM_PIPC1 */ +#define GPIO_FROM_PIPC2 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC2) /* GPIO_FROM_PIPC2 */ +#define GPIO_FROM_PIPC3 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC3) /* GPIO_FROM_PIPC3 */ +#define GPIO_FROM_PIPC4 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC4) /* GPIO_FROM_PIPC4 */ +#define GPIO_FROM_PIPC5 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC5) /* GPIO_FROM_PIPC5 */ +#define GPIO_FROM_PIPC6 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC6) /* GPIO_FROM_PIPC6 */ +#define GPIO_FROM_PIPC7 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC7) /* GPIO_FROM_PIPC7 */ +#define GPIO_FROM_PIPC8 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC8) /* GPIO_FROM_PIPC8 */ +#define GPIO_FROM_PIPC9 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC9) /* GPIO_FROM_PIPC9 */ +#define GPIO_FROM_PIPC10 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC10) /* GPIO_FROM_PIPC10 */ +#define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */ + + +/* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */ +#define GPIO_FROM_PBDC1_ARRAY_COUNT 11 +#define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \ + &GPIO_FROM_PBDC9, &GPIO_FROM_PBDC10, &GPIO_FROM_PBDC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PBDC1 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC1) /* GPIO_FROM_PBDC1 */ +#define GPIO_FROM_PBDC2 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC2) /* GPIO_FROM_PBDC2 */ +#define GPIO_FROM_PBDC3 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC3) /* GPIO_FROM_PBDC3 */ +#define GPIO_FROM_PBDC4 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC4) /* GPIO_FROM_PBDC4 */ +#define GPIO_FROM_PBDC5 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC5) /* GPIO_FROM_PBDC5 */ +#define GPIO_FROM_PBDC6 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC6) /* GPIO_FROM_PBDC6 */ +#define GPIO_FROM_PBDC7 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC7) /* GPIO_FROM_PBDC7 */ +#define GPIO_FROM_PBDC8 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC8) /* GPIO_FROM_PBDC8 */ +#define GPIO_FROM_PBDC9 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC9) /* GPIO_FROM_PBDC9 */ +#define GPIO_FROM_PBDC10 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC10) /* GPIO_FROM_PBDC10 */ +#define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */ + + +/* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */ +#define GPIO_FROM_PIBC1_ARRAY_COUNT 11 +#define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \ + &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */ +#define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */ +#define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */ +#define GPIO_FROM_PIBC4 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC4) /* GPIO_FROM_PIBC4 */ +#define GPIO_FROM_PIBC5 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC5) /* GPIO_FROM_PIBC5 */ +#define GPIO_FROM_PIBC6 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC6) /* GPIO_FROM_PIBC6 */ +#define GPIO_FROM_PIBC7 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC7) /* GPIO_FROM_PIBC7 */ +#define GPIO_FROM_PIBC8 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC8) /* GPIO_FROM_PIBC8 */ +#define GPIO_FROM_PIBC9 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC9) /* GPIO_FROM_PIBC9 */ +#define GPIO_FROM_PIBC10 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC10) /* GPIO_FROM_PIBC10 */ +#define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */ + + +/* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */ +#define GPIO_FROM_PFCAE1_ARRAY_COUNT 11 +#define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \ + &GPIO_FROM_PFCAE9, &GPIO_FROM_PFCAE10, &GPIO_FROM_PFCAE11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFCAE1 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE1) /* GPIO_FROM_PFCAE1 */ +#define GPIO_FROM_PFCAE2 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE2) /* GPIO_FROM_PFCAE2 */ +#define GPIO_FROM_PFCAE3 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE3) /* GPIO_FROM_PFCAE3 */ +#define GPIO_FROM_PFCAE4 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE4) /* GPIO_FROM_PFCAE4 */ +#define GPIO_FROM_PFCAE5 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE5) /* GPIO_FROM_PFCAE5 */ +#define GPIO_FROM_PFCAE6 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE6) /* GPIO_FROM_PFCAE6 */ +#define GPIO_FROM_PFCAE7 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE7) /* GPIO_FROM_PFCAE7 */ +#define GPIO_FROM_PFCAE8 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE8) /* GPIO_FROM_PFCAE8 */ +#define GPIO_FROM_PFCAE9 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE9) /* GPIO_FROM_PFCAE9 */ +#define GPIO_FROM_PFCAE10 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE10) /* GPIO_FROM_PFCAE10 */ +#define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */ + + +/* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */ +/*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */ +#define GPIO_FROM_PNOT1_ARRAY_COUNT 11 +#define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \ + &GPIO_FROM_PNOT9, &GPIO_FROM_PNOT10, &GPIO_FROM_PNOT11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PNOT1 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT1) /* GPIO_FROM_PNOT1 */ +#define GPIO_FROM_PNOT2 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT2) /* GPIO_FROM_PNOT2 */ +#define GPIO_FROM_PNOT3 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT3) /* GPIO_FROM_PNOT3 */ +#define GPIO_FROM_PNOT4 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT4) /* GPIO_FROM_PNOT4 */ +#define GPIO_FROM_PNOT5 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT5) /* GPIO_FROM_PNOT5 */ +#define GPIO_FROM_PNOT6 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT6) /* GPIO_FROM_PNOT6 */ +#define GPIO_FROM_PNOT7 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT7) /* GPIO_FROM_PNOT7 */ +#define GPIO_FROM_PNOT8 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT8) /* GPIO_FROM_PNOT8 */ +#define GPIO_FROM_PNOT9 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT9) /* GPIO_FROM_PNOT9 */ +#define GPIO_FROM_PNOT10 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT10) /* GPIO_FROM_PNOT10 */ +#define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */ + + +/* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */ +#define GPIO_FROM_PFCE1_ARRAY_COUNT 11 +#define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \ + &GPIO_FROM_PFCE9, &GPIO_FROM_PFCE10, &GPIO_FROM_PFCE11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFCE1 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE1) /* GPIO_FROM_PFCE1 */ +#define GPIO_FROM_PFCE2 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE2) /* GPIO_FROM_PFCE2 */ +#define GPIO_FROM_PFCE3 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE3) /* GPIO_FROM_PFCE3 */ +#define GPIO_FROM_PFCE4 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE4) /* GPIO_FROM_PFCE4 */ +#define GPIO_FROM_PFCE5 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE5) /* GPIO_FROM_PFCE5 */ +#define GPIO_FROM_PFCE6 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE6) /* GPIO_FROM_PFCE6 */ +#define GPIO_FROM_PFCE7 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE7) /* GPIO_FROM_PFCE7 */ +#define GPIO_FROM_PFCE8 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE8) /* GPIO_FROM_PFCE8 */ +#define GPIO_FROM_PFCE9 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE9) /* GPIO_FROM_PFCE9 */ +#define GPIO_FROM_PFCE10 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE10) /* GPIO_FROM_PFCE10 */ +#define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */ + + +/* Channnel array defines of GPIO_FROM_PFC1_ARRAY */ +/*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */ +#define GPIO_FROM_PFC1_ARRAY_COUNT 11 +#define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \ + &GPIO_FROM_PFC9, &GPIO_FROM_PFC10, &GPIO_FROM_PFC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PFC1 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC1) /* GPIO_FROM_PFC1 */ +#define GPIO_FROM_PFC2 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC2) /* GPIO_FROM_PFC2 */ +#define GPIO_FROM_PFC3 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC3) /* GPIO_FROM_PFC3 */ +#define GPIO_FROM_PFC4 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC4) /* GPIO_FROM_PFC4 */ +#define GPIO_FROM_PFC5 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC5) /* GPIO_FROM_PFC5 */ +#define GPIO_FROM_PFC6 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC6) /* GPIO_FROM_PFC6 */ +#define GPIO_FROM_PFC7 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC7) /* GPIO_FROM_PFC7 */ +#define GPIO_FROM_PFC8 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC8) /* GPIO_FROM_PFC8 */ +#define GPIO_FROM_PFC9 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC9) /* GPIO_FROM_PFC9 */ +#define GPIO_FROM_PFC10 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC10) /* GPIO_FROM_PFC10 */ +#define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */ + + +/* Channnel array defines of GPIO_FROM_PMC0_ARRAY */ +/*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */ +#define GPIO_FROM_PMC0_ARRAY_COUNT 12 +#define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \ + &GPIO_FROM_PMC8, &GPIO_FROM_PMC9, &GPIO_FROM_PMC10, &GPIO_FROM_PMC11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PMC0 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC0) /* GPIO_FROM_PMC0 */ +#define GPIO_FROM_PMC1 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC1) /* GPIO_FROM_PMC1 */ +#define GPIO_FROM_PMC2 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC2) /* GPIO_FROM_PMC2 */ +#define GPIO_FROM_PMC3 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC3) /* GPIO_FROM_PMC3 */ +#define GPIO_FROM_PMC4 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC4) /* GPIO_FROM_PMC4 */ +#define GPIO_FROM_PMC5 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC5) /* GPIO_FROM_PMC5 */ +#define GPIO_FROM_PMC6 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC6) /* GPIO_FROM_PMC6 */ +#define GPIO_FROM_PMC7 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC7) /* GPIO_FROM_PMC7 */ +#define GPIO_FROM_PMC8 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC8) /* GPIO_FROM_PMC8 */ +#define GPIO_FROM_PMC9 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC9) /* GPIO_FROM_PMC9 */ +#define GPIO_FROM_PMC10 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC10) /* GPIO_FROM_PMC10 */ +#define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */ + + +/* Channnel array defines of GPIO_FROM_PM1_ARRAY */ +/*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */ +#define GPIO_FROM_PM1_ARRAY_COUNT 11 +#define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \ + &GPIO_FROM_PM9, &GPIO_FROM_PM10, &GPIO_FROM_PM11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PM1 (*(struct st_gpio_from_pm1 *)&GPIO.PM1) /* GPIO_FROM_PM1 */ +#define GPIO_FROM_PM2 (*(struct st_gpio_from_pm1 *)&GPIO.PM2) /* GPIO_FROM_PM2 */ +#define GPIO_FROM_PM3 (*(struct st_gpio_from_pm1 *)&GPIO.PM3) /* GPIO_FROM_PM3 */ +#define GPIO_FROM_PM4 (*(struct st_gpio_from_pm1 *)&GPIO.PM4) /* GPIO_FROM_PM4 */ +#define GPIO_FROM_PM5 (*(struct st_gpio_from_pm1 *)&GPIO.PM5) /* GPIO_FROM_PM5 */ +#define GPIO_FROM_PM6 (*(struct st_gpio_from_pm1 *)&GPIO.PM6) /* GPIO_FROM_PM6 */ +#define GPIO_FROM_PM7 (*(struct st_gpio_from_pm1 *)&GPIO.PM7) /* GPIO_FROM_PM7 */ +#define GPIO_FROM_PM8 (*(struct st_gpio_from_pm1 *)&GPIO.PM8) /* GPIO_FROM_PM8 */ +#define GPIO_FROM_PM9 (*(struct st_gpio_from_pm1 *)&GPIO.PM9) /* GPIO_FROM_PM9 */ +#define GPIO_FROM_PM10 (*(struct st_gpio_from_pm1 *)&GPIO.PM10) /* GPIO_FROM_PM10 */ +#define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11) /* GPIO_FROM_PM11 */ + + +/* Channnel array defines of GPIO_FROM_PPR0_ARRAY */ +/*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */ +#define GPIO_FROM_PPR0_ARRAY_COUNT 12 +#define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \ + &GPIO_FROM_PPR8, &GPIO_FROM_PPR9, &GPIO_FROM_PPR10, &GPIO_FROM_PPR11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PPR0 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR0) /* GPIO_FROM_PPR0 */ +#define GPIO_FROM_PPR1 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR1) /* GPIO_FROM_PPR1 */ +#define GPIO_FROM_PPR2 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR2) /* GPIO_FROM_PPR2 */ +#define GPIO_FROM_PPR3 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR3) /* GPIO_FROM_PPR3 */ +#define GPIO_FROM_PPR4 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR4) /* GPIO_FROM_PPR4 */ +#define GPIO_FROM_PPR5 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR5) /* GPIO_FROM_PPR5 */ +#define GPIO_FROM_PPR6 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR6) /* GPIO_FROM_PPR6 */ +#define GPIO_FROM_PPR7 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR7) /* GPIO_FROM_PPR7 */ +#define GPIO_FROM_PPR8 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR8) /* GPIO_FROM_PPR8 */ +#define GPIO_FROM_PPR9 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR9) /* GPIO_FROM_PPR9 */ +#define GPIO_FROM_PPR10 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR10) /* GPIO_FROM_PPR10 */ +#define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */ + + +/* Channnel array defines of GPIO_FROM_P1_ARRAY */ +/*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */ +#define GPIO_FROM_P1_ARRAY_COUNT 11 +#define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \ + &GPIO_FROM_P9, &GPIO_FROM_P10, &GPIO_FROM_P11 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_P1 (*(struct st_gpio_from_p1 *)&GPIO.P1) /* GPIO_FROM_P1 */ +#define GPIO_FROM_P2 (*(struct st_gpio_from_p1 *)&GPIO.P2) /* GPIO_FROM_P2 */ +#define GPIO_FROM_P3 (*(struct st_gpio_from_p1 *)&GPIO.P3) /* GPIO_FROM_P3 */ +#define GPIO_FROM_P4 (*(struct st_gpio_from_p1 *)&GPIO.P4) /* GPIO_FROM_P4 */ +#define GPIO_FROM_P5 (*(struct st_gpio_from_p1 *)&GPIO.P5) /* GPIO_FROM_P5 */ +#define GPIO_FROM_P6 (*(struct st_gpio_from_p1 *)&GPIO.P6) /* GPIO_FROM_P6 */ +#define GPIO_FROM_P7 (*(struct st_gpio_from_p1 *)&GPIO.P7) /* GPIO_FROM_P7 */ +#define GPIO_FROM_P8 (*(struct st_gpio_from_p1 *)&GPIO.P8) /* GPIO_FROM_P8 */ +#define GPIO_FROM_P9 (*(struct st_gpio_from_p1 *)&GPIO.P9) /* GPIO_FROM_P9 */ +#define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10) /* GPIO_FROM_P10 */ +#define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11) /* GPIO_FROM_P11 */ + +/* End of channnel array defines of GPIO */ + + +#define GPIOP1 GPIO.P1 +#define GPIOP2 GPIO.P2 +#define GPIOP3 GPIO.P3 +#define GPIOP4 GPIO.P4 +#define GPIOP5 GPIO.P5 +#define GPIOP6 GPIO.P6 +#define GPIOP7 GPIO.P7 +#define GPIOP8 GPIO.P8 +#define GPIOP9 GPIO.P9 +#define GPIOP10 GPIO.P10 +#define GPIOP11 GPIO.P11 +#define GPIOPSR1 GPIO.PSR1 +#define GPIOPSR2 GPIO.PSR2 +#define GPIOPSR3 GPIO.PSR3 +#define GPIOPSR4 GPIO.PSR4 +#define GPIOPSR5 GPIO.PSR5 +#define GPIOPSR6 GPIO.PSR6 +#define GPIOPSR7 GPIO.PSR7 +#define GPIOPSR8 GPIO.PSR8 +#define GPIOPSR9 GPIO.PSR9 +#define GPIOPSR10 GPIO.PSR10 +#define GPIOPSR11 GPIO.PSR11 +#define GPIOPPR0 GPIO.PPR0 +#define GPIOPPR1 GPIO.PPR1 +#define GPIOPPR2 GPIO.PPR2 +#define GPIOPPR3 GPIO.PPR3 +#define GPIOPPR4 GPIO.PPR4 +#define GPIOPPR5 GPIO.PPR5 +#define GPIOPPR6 GPIO.PPR6 +#define GPIOPPR7 GPIO.PPR7 +#define GPIOPPR8 GPIO.PPR8 +#define GPIOPPR9 GPIO.PPR9 +#define GPIOPPR10 GPIO.PPR10 +#define GPIOPPR11 GPIO.PPR11 +#define GPIOPM1 GPIO.PM1 +#define GPIOPM2 GPIO.PM2 +#define GPIOPM3 GPIO.PM3 +#define GPIOPM4 GPIO.PM4 +#define GPIOPM5 GPIO.PM5 +#define GPIOPM6 GPIO.PM6 +#define GPIOPM7 GPIO.PM7 +#define GPIOPM8 GPIO.PM8 +#define GPIOPM9 GPIO.PM9 +#define GPIOPM10 GPIO.PM10 +#define GPIOPM11 GPIO.PM11 +#define GPIOPMC0 GPIO.PMC0 +#define GPIOPMC1 GPIO.PMC1 +#define GPIOPMC2 GPIO.PMC2 +#define GPIOPMC3 GPIO.PMC3 +#define GPIOPMC4 GPIO.PMC4 +#define GPIOPMC5 GPIO.PMC5 +#define GPIOPMC6 GPIO.PMC6 +#define GPIOPMC7 GPIO.PMC7 +#define GPIOPMC8 GPIO.PMC8 +#define GPIOPMC9 GPIO.PMC9 +#define GPIOPMC10 GPIO.PMC10 +#define GPIOPMC11 GPIO.PMC11 +#define GPIOPFC1 GPIO.PFC1 +#define GPIOPFC2 GPIO.PFC2 +#define GPIOPFC3 GPIO.PFC3 +#define GPIOPFC4 GPIO.PFC4 +#define GPIOPFC5 GPIO.PFC5 +#define GPIOPFC6 GPIO.PFC6 +#define GPIOPFC7 GPIO.PFC7 +#define GPIOPFC8 GPIO.PFC8 +#define GPIOPFC9 GPIO.PFC9 +#define GPIOPFC10 GPIO.PFC10 +#define GPIOPFC11 GPIO.PFC11 +#define GPIOPFCE1 GPIO.PFCE1 +#define GPIOPFCE2 GPIO.PFCE2 +#define GPIOPFCE3 GPIO.PFCE3 +#define GPIOPFCE4 GPIO.PFCE4 +#define GPIOPFCE5 GPIO.PFCE5 +#define GPIOPFCE6 GPIO.PFCE6 +#define GPIOPFCE7 GPIO.PFCE7 +#define GPIOPFCE8 GPIO.PFCE8 +#define GPIOPFCE9 GPIO.PFCE9 +#define GPIOPFCE10 GPIO.PFCE10 +#define GPIOPFCE11 GPIO.PFCE11 +#define GPIOPNOT1 GPIO.PNOT1 +#define GPIOPNOT2 GPIO.PNOT2 +#define GPIOPNOT3 GPIO.PNOT3 +#define GPIOPNOT4 GPIO.PNOT4 +#define GPIOPNOT5 GPIO.PNOT5 +#define GPIOPNOT6 GPIO.PNOT6 +#define GPIOPNOT7 GPIO.PNOT7 +#define GPIOPNOT8 GPIO.PNOT8 +#define GPIOPNOT9 GPIO.PNOT9 +#define GPIOPNOT10 GPIO.PNOT10 +#define GPIOPNOT11 GPIO.PNOT11 +#define GPIOPMSR1 GPIO.PMSR1 +#define GPIOPMSR2 GPIO.PMSR2 +#define GPIOPMSR3 GPIO.PMSR3 +#define GPIOPMSR4 GPIO.PMSR4 +#define GPIOPMSR5 GPIO.PMSR5 +#define GPIOPMSR6 GPIO.PMSR6 +#define GPIOPMSR7 GPIO.PMSR7 +#define GPIOPMSR8 GPIO.PMSR8 +#define GPIOPMSR9 GPIO.PMSR9 +#define GPIOPMSR10 GPIO.PMSR10 +#define GPIOPMSR11 GPIO.PMSR11 +#define GPIOPMCSR0 GPIO.PMCSR0 +#define GPIOPMCSR1 GPIO.PMCSR1 +#define GPIOPMCSR2 GPIO.PMCSR2 +#define GPIOPMCSR3 GPIO.PMCSR3 +#define GPIOPMCSR4 GPIO.PMCSR4 +#define GPIOPMCSR5 GPIO.PMCSR5 +#define GPIOPMCSR6 GPIO.PMCSR6 +#define GPIOPMCSR7 GPIO.PMCSR7 +#define GPIOPMCSR8 GPIO.PMCSR8 +#define GPIOPMCSR9 GPIO.PMCSR9 +#define GPIOPMCSR10 GPIO.PMCSR10 +#define GPIOPMCSR11 GPIO.PMCSR11 +#define GPIOPFCAE1 GPIO.PFCAE1 +#define GPIOPFCAE2 GPIO.PFCAE2 +#define GPIOPFCAE3 GPIO.PFCAE3 +#define GPIOPFCAE4 GPIO.PFCAE4 +#define GPIOPFCAE5 GPIO.PFCAE5 +#define GPIOPFCAE6 GPIO.PFCAE6 +#define GPIOPFCAE7 GPIO.PFCAE7 +#define GPIOPFCAE8 GPIO.PFCAE8 +#define GPIOPFCAE9 GPIO.PFCAE9 +#define GPIOPFCAE10 GPIO.PFCAE10 +#define GPIOPFCAE11 GPIO.PFCAE11 +#define GPIOSNCR GPIO.SNCR +#define GPIOPIBC0 GPIO.PIBC0 +#define GPIOPIBC1 GPIO.PIBC1 +#define GPIOPIBC2 GPIO.PIBC2 +#define GPIOPIBC3 GPIO.PIBC3 +#define GPIOPIBC4 GPIO.PIBC4 +#define GPIOPIBC5 GPIO.PIBC5 +#define GPIOPIBC6 GPIO.PIBC6 +#define GPIOPIBC7 GPIO.PIBC7 +#define GPIOPIBC8 GPIO.PIBC8 +#define GPIOPIBC9 GPIO.PIBC9 +#define GPIOPIBC10 GPIO.PIBC10 +#define GPIOPIBC11 GPIO.PIBC11 +#define GPIOPBDC1 GPIO.PBDC1 +#define GPIOPBDC2 GPIO.PBDC2 +#define GPIOPBDC3 GPIO.PBDC3 +#define GPIOPBDC4 GPIO.PBDC4 +#define GPIOPBDC5 GPIO.PBDC5 +#define GPIOPBDC6 GPIO.PBDC6 +#define GPIOPBDC7 GPIO.PBDC7 +#define GPIOPBDC8 GPIO.PBDC8 +#define GPIOPBDC9 GPIO.PBDC9 +#define GPIOPBDC10 GPIO.PBDC10 +#define GPIOPBDC11 GPIO.PBDC11 +#define GPIOPIPC1 GPIO.PIPC1 +#define GPIOPIPC2 GPIO.PIPC2 +#define GPIOPIPC3 GPIO.PIPC3 +#define GPIOPIPC4 GPIO.PIPC4 +#define GPIOPIPC5 GPIO.PIPC5 +#define GPIOPIPC6 GPIO.PIPC6 +#define GPIOPIPC7 GPIO.PIPC7 +#define GPIOPIPC8 GPIO.PIPC8 +#define GPIOPIPC9 GPIO.PIPC9 +#define GPIOPIPC10 GPIO.PIPC10 +#define GPIOPIPC11 GPIO.PIPC11 +#define GPIOJPPR0 GPIO.JPPR0 +#define GPIOJPMC0 GPIO.JPMC0 +#define GPIOJPMCSR0 GPIO.JPMCSR0 +#define GPIOJPIBC0 GPIO.JPIBC0 +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ieb_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ieb_iodefine.h new file mode 100644 index 0000000000..8b76e23c6f --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ieb_iodefine.h @@ -0,0 +1,119 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ieb_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef IEB_IODEFINE_H +#define IEB_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_ieb +{ /* IEB */ + volatile uint8_t B0BCR; /* B0BCR */ + volatile uint8_t dummy495[3]; /* */ + volatile uint8_t B0PSR; /* B0PSR */ + volatile uint8_t dummy496[3]; /* */ + volatile uint16_t B0UAR; /* B0UAR */ + volatile uint8_t dummy497[2]; /* */ + volatile uint16_t B0SAR; /* B0SAR */ + volatile uint8_t dummy498[2]; /* */ + volatile uint16_t B0PAR; /* B0PAR */ + volatile uint8_t dummy499[2]; /* */ + volatile uint16_t B0RSA; /* B0RSA */ + volatile uint8_t dummy500[2]; /* */ + volatile uint8_t B0CDR; /* B0CDR */ + volatile uint8_t dummy501[3]; /* */ + volatile uint8_t B0TCD; /* B0TCD */ + volatile uint8_t dummy502[3]; /* */ + volatile uint8_t B0RCD; /* B0RCD */ + volatile uint8_t dummy503[3]; /* */ + volatile uint8_t B0DLR; /* B0DLR */ + volatile uint8_t dummy504[3]; /* */ + volatile uint8_t B0TDL; /* B0TDL */ + volatile uint8_t dummy505[3]; /* */ + volatile uint8_t B0RDL; /* B0RDL */ + volatile uint8_t dummy506[3]; /* */ + volatile uint8_t B0CKS; /* B0CKS */ + volatile uint8_t dummy507[3]; /* */ + volatile uint8_t B0TMS; /* B0TMS */ + volatile uint8_t dummy508[3]; /* */ + volatile uint8_t B0PCR; /* B0PCR */ + volatile uint8_t dummy509[3]; /* */ + volatile uint16_t B0BSR; /* B0BSR */ + volatile uint8_t dummy510[2]; /* */ + volatile uint8_t B0SSR; /* B0SSR */ + volatile uint8_t dummy511[3]; /* */ + volatile uint8_t B0USR; /* B0USR */ + volatile uint8_t dummy512[3]; /* */ + volatile uint8_t B0ISR; /* B0ISR */ + volatile uint8_t dummy513[3]; /* */ + volatile uint8_t B0ESR; /* B0ESR */ + volatile uint8_t dummy514[3]; /* */ + volatile uint8_t B0FSR; /* B0FSR */ + volatile uint8_t dummy515[3]; /* */ + volatile uint8_t B0SCR; /* B0SCR */ + volatile uint8_t dummy516[3]; /* */ + volatile uint8_t B0CCR; /* B0CCR */ + volatile uint8_t dummy517[3]; /* */ + volatile uint8_t B0STC0; /* B0STC0 */ + volatile uint8_t dummy518[3]; /* */ + volatile uint8_t B0STC1; /* B0STC1 */ + volatile uint8_t dummy519[3]; /* */ + volatile uint8_t B0DR; /* B0DR */ +}; + + +#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */ + + +#define IEBB0BCR IEB.B0BCR +#define IEBB0PSR IEB.B0PSR +#define IEBB0UAR IEB.B0UAR +#define IEBB0SAR IEB.B0SAR +#define IEBB0PAR IEB.B0PAR +#define IEBB0RSA IEB.B0RSA +#define IEBB0CDR IEB.B0CDR +#define IEBB0TCD IEB.B0TCD +#define IEBB0RCD IEB.B0RCD +#define IEBB0DLR IEB.B0DLR +#define IEBB0TDL IEB.B0TDL +#define IEBB0RDL IEB.B0RDL +#define IEBB0CKS IEB.B0CKS +#define IEBB0TMS IEB.B0TMS +#define IEBB0PCR IEB.B0PCR +#define IEBB0BSR IEB.B0BSR +#define IEBB0SSR IEB.B0SSR +#define IEBB0USR IEB.B0USR +#define IEBB0ISR IEB.B0ISR +#define IEBB0ESR IEB.B0ESR +#define IEBB0FSR IEB.B0FSR +#define IEBB0SCR IEB.B0SCR +#define IEBB0CCR IEB.B0CCR +#define IEBB0STC0 IEB.B0STC0 +#define IEBB0STC1 IEB.B0STC1 +#define IEBB0DR IEB.B0DR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/inb_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/inb_iodefine.h new file mode 100644 index 0000000000..f8175a6978 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/inb_iodefine.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : inb_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef INB_IODEFINE_H +#define INB_IODEFINE_H + +struct st_inb +{ /* INB */ + volatile uint32_t RMPR; /* RMPR */ +#define INB_AXIBUSCTLn_COUNT 11 + volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */ + volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */ + volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */ + volatile uint32_t AXIBUSCTL3; /* AXIBUSCTL3 */ + volatile uint32_t AXIBUSCTL4; /* AXIBUSCTL4 */ + volatile uint32_t AXIBUSCTL5; /* AXIBUSCTL5 */ + volatile uint32_t AXIBUSCTL6; /* AXIBUSCTL6 */ + volatile uint32_t AXIBUSCTL7; /* AXIBUSCTL7 */ + volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */ + volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */ + volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */ +#define INB_AXIRERRCTLn_COUNT 4 + volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */ + volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */ + volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */ + volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */ +#define INB_AXIRERRSTn_COUNT 4 + volatile uint32_t AXIRERRST0; /* AXIRERRST0 */ + volatile uint32_t AXIRERRST1; /* AXIRERRST1 */ + volatile uint32_t AXIRERRST2; /* AXIRERRST2 */ + volatile uint32_t AXIRERRST3; /* AXIRERRST3 */ +#define INB_AXIRERRCLRn_COUNT 4 + volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */ + volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */ + volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */ + volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */ +}; + + +#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ + + +#define INBRMPR INB.RMPR +#define INBAXIBUSCTL0 INB.AXIBUSCTL0 +#define INBAXIBUSCTL1 INB.AXIBUSCTL1 +#define INBAXIBUSCTL2 INB.AXIBUSCTL2 +#define INBAXIBUSCTL3 INB.AXIBUSCTL3 +#define INBAXIBUSCTL4 INB.AXIBUSCTL4 +#define INBAXIBUSCTL5 INB.AXIBUSCTL5 +#define INBAXIBUSCTL6 INB.AXIBUSCTL6 +#define INBAXIBUSCTL7 INB.AXIBUSCTL7 +#define INBAXIBUSCTL8 INB.AXIBUSCTL8 +#define INBAXIBUSCTL9 INB.AXIBUSCTL9 +#define INBAXIBUSCTL10 INB.AXIBUSCTL10 +#define INBAXIRERRCTL0 INB.AXIRERRCTL0 +#define INBAXIRERRCTL1 INB.AXIRERRCTL1 +#define INBAXIRERRCTL2 INB.AXIRERRCTL2 +#define INBAXIRERRCTL3 INB.AXIRERRCTL3 +#define INBAXIRERRST0 INB.AXIRERRST0 +#define INBAXIRERRST1 INB.AXIRERRST1 +#define INBAXIRERRST2 INB.AXIRERRST2 +#define INBAXIRERRST3 INB.AXIRERRST3 +#define INBAXIRERRCLR0 INB.AXIRERRCLR0 +#define INBAXIRERRCLR1 INB.AXIRERRCLR1 +#define INBAXIRERRCLR2 INB.AXIRERRCLR2 +#define INBAXIRERRCLR3 INB.AXIRERRCLR3 +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/intc_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/intc_iodefine.h new file mode 100644 index 0000000000..253d4b9399 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/intc_iodefine.h @@ -0,0 +1,1026 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : intc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef INTC_IODEFINE_H +#define INTC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_intc +{ /* INTC */ + volatile uint32_t ICDDCR; /* ICDDCR */ + volatile uint32_t ICDICTR; /* ICDICTR */ + volatile uint32_t ICDIIDR; /* ICDIIDR */ + volatile uint8_t dummy193[116]; /* */ +#define INTC_ICDISR0_COUNT 19 + volatile uint32_t ICDISR0; /* ICDISR0 */ + volatile uint32_t ICDISR1; /* ICDISR1 */ + volatile uint32_t ICDISR2; /* ICDISR2 */ + volatile uint32_t ICDISR3; /* ICDISR3 */ + volatile uint32_t ICDISR4; /* ICDISR4 */ + volatile uint32_t ICDISR5; /* ICDISR5 */ + volatile uint32_t ICDISR6; /* ICDISR6 */ + volatile uint32_t ICDISR7; /* ICDISR7 */ + volatile uint32_t ICDISR8; /* ICDISR8 */ + volatile uint32_t ICDISR9; /* ICDISR9 */ + volatile uint32_t ICDISR10; /* ICDISR10 */ + volatile uint32_t ICDISR11; /* ICDISR11 */ + volatile uint32_t ICDISR12; /* ICDISR12 */ + volatile uint32_t ICDISR13; /* ICDISR13 */ + volatile uint32_t ICDISR14; /* ICDISR14 */ + volatile uint32_t ICDISR15; /* ICDISR15 */ + volatile uint32_t ICDISR16; /* ICDISR16 */ + volatile uint32_t ICDISR17; /* ICDISR17 */ + volatile uint32_t ICDISR18; /* ICDISR18 */ + volatile uint8_t dummy194[52]; /* */ +#define INTC_ICDISER0_COUNT 19 + volatile uint32_t ICDISER0; /* ICDISER0 */ + volatile uint32_t ICDISER1; /* ICDISER1 */ + volatile uint32_t ICDISER2; /* ICDISER2 */ + volatile uint32_t ICDISER3; /* ICDISER3 */ + volatile uint32_t ICDISER4; /* ICDISER4 */ + volatile uint32_t ICDISER5; /* ICDISER5 */ + volatile uint32_t ICDISER6; /* ICDISER6 */ + volatile uint32_t ICDISER7; /* ICDISER7 */ + volatile uint32_t ICDISER8; /* ICDISER8 */ + volatile uint32_t ICDISER9; /* ICDISER9 */ + volatile uint32_t ICDISER10; /* ICDISER10 */ + volatile uint32_t ICDISER11; /* ICDISER11 */ + volatile uint32_t ICDISER12; /* ICDISER12 */ + volatile uint32_t ICDISER13; /* ICDISER13 */ + volatile uint32_t ICDISER14; /* ICDISER14 */ + volatile uint32_t ICDISER15; /* ICDISER15 */ + volatile uint32_t ICDISER16; /* ICDISER16 */ + volatile uint32_t ICDISER17; /* ICDISER17 */ + volatile uint32_t ICDISER18; /* ICDISER18 */ + volatile uint8_t dummy195[52]; /* */ +#define INTC_ICDICER0_COUNT 19 + volatile uint32_t ICDICER0; /* ICDICER0 */ + volatile uint32_t ICDICER1; /* ICDICER1 */ + volatile uint32_t ICDICER2; /* ICDICER2 */ + volatile uint32_t ICDICER3; /* ICDICER3 */ + volatile uint32_t ICDICER4; /* ICDICER4 */ + volatile uint32_t ICDICER5; /* ICDICER5 */ + volatile uint32_t ICDICER6; /* ICDICER6 */ + volatile uint32_t ICDICER7; /* ICDICER7 */ + volatile uint32_t ICDICER8; /* ICDICER8 */ + volatile uint32_t ICDICER9; /* ICDICER9 */ + volatile uint32_t ICDICER10; /* ICDICER10 */ + volatile uint32_t ICDICER11; /* ICDICER11 */ + volatile uint32_t ICDICER12; /* ICDICER12 */ + volatile uint32_t ICDICER13; /* ICDICER13 */ + volatile uint32_t ICDICER14; /* ICDICER14 */ + volatile uint32_t ICDICER15; /* ICDICER15 */ + volatile uint32_t ICDICER16; /* ICDICER16 */ + volatile uint32_t ICDICER17; /* ICDICER17 */ + volatile uint32_t ICDICER18; /* ICDICER18 */ + volatile uint8_t dummy196[52]; /* */ +#define INTC_ICDISPR0_COUNT 19 + volatile uint32_t ICDISPR0; /* ICDISPR0 */ + volatile uint32_t ICDISPR1; /* ICDISPR1 */ + volatile uint32_t ICDISPR2; /* ICDISPR2 */ + volatile uint32_t ICDISPR3; /* ICDISPR3 */ + volatile uint32_t ICDISPR4; /* ICDISPR4 */ + volatile uint32_t ICDISPR5; /* ICDISPR5 */ + volatile uint32_t ICDISPR6; /* ICDISPR6 */ + volatile uint32_t ICDISPR7; /* ICDISPR7 */ + volatile uint32_t ICDISPR8; /* ICDISPR8 */ + volatile uint32_t ICDISPR9; /* ICDISPR9 */ + volatile uint32_t ICDISPR10; /* ICDISPR10 */ + volatile uint32_t ICDISPR11; /* ICDISPR11 */ + volatile uint32_t ICDISPR12; /* ICDISPR12 */ + volatile uint32_t ICDISPR13; /* ICDISPR13 */ + volatile uint32_t ICDISPR14; /* ICDISPR14 */ + volatile uint32_t ICDISPR15; /* ICDISPR15 */ + volatile uint32_t ICDISPR16; /* ICDISPR16 */ + volatile uint32_t ICDISPR17; /* ICDISPR17 */ + volatile uint32_t ICDISPR18; /* ICDISPR18 */ + volatile uint8_t dummy197[52]; /* */ +#define INTC_ICDICPR0_COUNT 19 + volatile uint32_t ICDICPR0; /* ICDICPR0 */ + volatile uint32_t ICDICPR1; /* ICDICPR1 */ + volatile uint32_t ICDICPR2; /* ICDICPR2 */ + volatile uint32_t ICDICPR3; /* ICDICPR3 */ + volatile uint32_t ICDICPR4; /* ICDICPR4 */ + volatile uint32_t ICDICPR5; /* ICDICPR5 */ + volatile uint32_t ICDICPR6; /* ICDICPR6 */ + volatile uint32_t ICDICPR7; /* ICDICPR7 */ + volatile uint32_t ICDICPR8; /* ICDICPR8 */ + volatile uint32_t ICDICPR9; /* ICDICPR9 */ + volatile uint32_t ICDICPR10; /* ICDICPR10 */ + volatile uint32_t ICDICPR11; /* ICDICPR11 */ + volatile uint32_t ICDICPR12; /* ICDICPR12 */ + volatile uint32_t ICDICPR13; /* ICDICPR13 */ + volatile uint32_t ICDICPR14; /* ICDICPR14 */ + volatile uint32_t ICDICPR15; /* ICDICPR15 */ + volatile uint32_t ICDICPR16; /* ICDICPR16 */ + volatile uint32_t ICDICPR17; /* ICDICPR17 */ + volatile uint32_t ICDICPR18; /* ICDICPR18 */ + volatile uint8_t dummy198[52]; /* */ +#define INTC_ICDABR0_COUNT 19 + volatile uint32_t ICDABR0; /* ICDABR0 */ + volatile uint32_t ICDABR1; /* ICDABR1 */ + volatile uint32_t ICDABR2; /* ICDABR2 */ + volatile uint32_t ICDABR3; /* ICDABR3 */ + volatile uint32_t ICDABR4; /* ICDABR4 */ + volatile uint32_t ICDABR5; /* ICDABR5 */ + volatile uint32_t ICDABR6; /* ICDABR6 */ + volatile uint32_t ICDABR7; /* ICDABR7 */ + volatile uint32_t ICDABR8; /* ICDABR8 */ + volatile uint32_t ICDABR9; /* ICDABR9 */ + volatile uint32_t ICDABR10; /* ICDABR10 */ + volatile uint32_t ICDABR11; /* ICDABR11 */ + volatile uint32_t ICDABR12; /* ICDABR12 */ + volatile uint32_t ICDABR13; /* ICDABR13 */ + volatile uint32_t ICDABR14; /* ICDABR14 */ + volatile uint32_t ICDABR15; /* ICDABR15 */ + volatile uint32_t ICDABR16; /* ICDABR16 */ + volatile uint32_t ICDABR17; /* ICDABR17 */ + volatile uint32_t ICDABR18; /* ICDABR18 */ + volatile uint8_t dummy199[180]; /* */ +#define INTC_ICDIPR0_COUNT 147 + volatile uint32_t ICDIPR0; /* ICDIPR0 */ + volatile uint32_t ICDIPR1; /* ICDIPR1 */ + volatile uint32_t ICDIPR2; /* ICDIPR2 */ + volatile uint32_t ICDIPR3; /* ICDIPR3 */ + volatile uint32_t ICDIPR4; /* ICDIPR4 */ + volatile uint32_t ICDIPR5; /* ICDIPR5 */ + volatile uint32_t ICDIPR6; /* ICDIPR6 */ + volatile uint32_t ICDIPR7; /* ICDIPR7 */ + volatile uint32_t ICDIPR8; /* ICDIPR8 */ + volatile uint32_t ICDIPR9; /* ICDIPR9 */ + volatile uint32_t ICDIPR10; /* ICDIPR10 */ + volatile uint32_t ICDIPR11; /* ICDIPR11 */ + volatile uint32_t ICDIPR12; /* ICDIPR12 */ + volatile uint32_t ICDIPR13; /* ICDIPR13 */ + volatile uint32_t ICDIPR14; /* ICDIPR14 */ + volatile uint32_t ICDIPR15; /* ICDIPR15 */ + volatile uint32_t ICDIPR16; /* ICDIPR16 */ + volatile uint32_t ICDIPR17; /* ICDIPR17 */ + volatile uint32_t ICDIPR18; /* ICDIPR18 */ + volatile uint32_t ICDIPR19; /* ICDIPR19 */ + volatile uint32_t ICDIPR20; /* ICDIPR20 */ + volatile uint32_t ICDIPR21; /* ICDIPR21 */ + volatile uint32_t ICDIPR22; /* ICDIPR22 */ + volatile uint32_t ICDIPR23; /* ICDIPR23 */ + volatile uint32_t ICDIPR24; /* ICDIPR24 */ + volatile uint32_t ICDIPR25; /* ICDIPR25 */ + volatile uint32_t ICDIPR26; /* ICDIPR26 */ + volatile uint32_t ICDIPR27; /* ICDIPR27 */ + volatile uint32_t ICDIPR28; /* ICDIPR28 */ + volatile uint32_t ICDIPR29; /* ICDIPR29 */ + volatile uint32_t ICDIPR30; /* ICDIPR30 */ + volatile uint32_t ICDIPR31; /* ICDIPR31 */ + volatile uint32_t ICDIPR32; /* ICDIPR32 */ + volatile uint32_t ICDIPR33; /* ICDIPR33 */ + volatile uint32_t ICDIPR34; /* ICDIPR34 */ + volatile uint32_t ICDIPR35; /* ICDIPR35 */ + volatile uint32_t ICDIPR36; /* ICDIPR36 */ + volatile uint32_t ICDIPR37; /* ICDIPR37 */ + volatile uint32_t ICDIPR38; /* ICDIPR38 */ + volatile uint32_t ICDIPR39; /* ICDIPR39 */ + volatile uint32_t ICDIPR40; /* ICDIPR40 */ + volatile uint32_t ICDIPR41; /* ICDIPR41 */ + volatile uint32_t ICDIPR42; /* ICDIPR42 */ + volatile uint32_t ICDIPR43; /* ICDIPR43 */ + volatile uint32_t ICDIPR44; /* ICDIPR44 */ + volatile uint32_t ICDIPR45; /* ICDIPR45 */ + volatile uint32_t ICDIPR46; /* ICDIPR46 */ + volatile uint32_t ICDIPR47; /* ICDIPR47 */ + volatile uint32_t ICDIPR48; /* ICDIPR48 */ + volatile uint32_t ICDIPR49; /* ICDIPR49 */ + volatile uint32_t ICDIPR50; /* ICDIPR50 */ + volatile uint32_t ICDIPR51; /* ICDIPR51 */ + volatile uint32_t ICDIPR52; /* ICDIPR52 */ + volatile uint32_t ICDIPR53; /* ICDIPR53 */ + volatile uint32_t ICDIPR54; /* ICDIPR54 */ + volatile uint32_t ICDIPR55; /* ICDIPR55 */ + volatile uint32_t ICDIPR56; /* ICDIPR56 */ + volatile uint32_t ICDIPR57; /* ICDIPR57 */ + volatile uint32_t ICDIPR58; /* ICDIPR58 */ + volatile uint32_t ICDIPR59; /* ICDIPR59 */ + volatile uint32_t ICDIPR60; /* ICDIPR60 */ + volatile uint32_t ICDIPR61; /* ICDIPR61 */ + volatile uint32_t ICDIPR62; /* ICDIPR62 */ + volatile uint32_t ICDIPR63; /* ICDIPR63 */ + volatile uint32_t ICDIPR64; /* ICDIPR64 */ + volatile uint32_t ICDIPR65; /* ICDIPR65 */ + volatile uint32_t ICDIPR66; /* ICDIPR66 */ + volatile uint32_t ICDIPR67; /* ICDIPR67 */ + volatile uint32_t ICDIPR68; /* ICDIPR68 */ + volatile uint32_t ICDIPR69; /* ICDIPR69 */ + volatile uint32_t ICDIPR70; /* ICDIPR70 */ + volatile uint32_t ICDIPR71; /* ICDIPR71 */ + volatile uint32_t ICDIPR72; /* ICDIPR72 */ + volatile uint32_t ICDIPR73; /* ICDIPR73 */ + volatile uint32_t ICDIPR74; /* ICDIPR74 */ + volatile uint32_t ICDIPR75; /* ICDIPR75 */ + volatile uint32_t ICDIPR76; /* ICDIPR76 */ + volatile uint32_t ICDIPR77; /* ICDIPR77 */ + volatile uint32_t ICDIPR78; /* ICDIPR78 */ + volatile uint32_t ICDIPR79; /* ICDIPR79 */ + volatile uint32_t ICDIPR80; /* ICDIPR80 */ + volatile uint32_t ICDIPR81; /* ICDIPR81 */ + volatile uint32_t ICDIPR82; /* ICDIPR82 */ + volatile uint32_t ICDIPR83; /* ICDIPR83 */ + volatile uint32_t ICDIPR84; /* ICDIPR84 */ + volatile uint32_t ICDIPR85; /* ICDIPR85 */ + volatile uint32_t ICDIPR86; /* ICDIPR86 */ + volatile uint32_t ICDIPR87; /* ICDIPR87 */ + volatile uint32_t ICDIPR88; /* ICDIPR88 */ + volatile uint32_t ICDIPR89; /* ICDIPR89 */ + volatile uint32_t ICDIPR90; /* ICDIPR90 */ + volatile uint32_t ICDIPR91; /* ICDIPR91 */ + volatile uint32_t ICDIPR92; /* ICDIPR92 */ + volatile uint32_t ICDIPR93; /* ICDIPR93 */ + volatile uint32_t ICDIPR94; /* ICDIPR94 */ + volatile uint32_t ICDIPR95; /* ICDIPR95 */ + volatile uint32_t ICDIPR96; /* ICDIPR96 */ + volatile uint32_t ICDIPR97; /* ICDIPR97 */ + volatile uint32_t ICDIPR98; /* ICDIPR98 */ + volatile uint32_t ICDIPR99; /* ICDIPR99 */ + volatile uint32_t ICDIPR100; /* ICDIPR100 */ + volatile uint32_t ICDIPR101; /* ICDIPR101 */ + volatile uint32_t ICDIPR102; /* ICDIPR102 */ + volatile uint32_t ICDIPR103; /* ICDIPR103 */ + volatile uint32_t ICDIPR104; /* ICDIPR104 */ + volatile uint32_t ICDIPR105; /* ICDIPR105 */ + volatile uint32_t ICDIPR106; /* ICDIPR106 */ + volatile uint32_t ICDIPR107; /* ICDIPR107 */ + volatile uint32_t ICDIPR108; /* ICDIPR108 */ + volatile uint32_t ICDIPR109; /* ICDIPR109 */ + volatile uint32_t ICDIPR110; /* ICDIPR110 */ + volatile uint32_t ICDIPR111; /* ICDIPR111 */ + volatile uint32_t ICDIPR112; /* ICDIPR112 */ + volatile uint32_t ICDIPR113; /* ICDIPR113 */ + volatile uint32_t ICDIPR114; /* ICDIPR114 */ + volatile uint32_t ICDIPR115; /* ICDIPR115 */ + volatile uint32_t ICDIPR116; /* ICDIPR116 */ + volatile uint32_t ICDIPR117; /* ICDIPR117 */ + volatile uint32_t ICDIPR118; /* ICDIPR118 */ + volatile uint32_t ICDIPR119; /* ICDIPR119 */ + volatile uint32_t ICDIPR120; /* ICDIPR120 */ + volatile uint32_t ICDIPR121; /* ICDIPR121 */ + volatile uint32_t ICDIPR122; /* ICDIPR122 */ + volatile uint32_t ICDIPR123; /* ICDIPR123 */ + volatile uint32_t ICDIPR124; /* ICDIPR124 */ + volatile uint32_t ICDIPR125; /* ICDIPR125 */ + volatile uint32_t ICDIPR126; /* ICDIPR126 */ + volatile uint32_t ICDIPR127; /* ICDIPR127 */ + volatile uint32_t ICDIPR128; /* ICDIPR128 */ + volatile uint32_t ICDIPR129; /* ICDIPR129 */ + volatile uint32_t ICDIPR130; /* ICDIPR130 */ + volatile uint32_t ICDIPR131; /* ICDIPR131 */ + volatile uint32_t ICDIPR132; /* ICDIPR132 */ + volatile uint32_t ICDIPR133; /* ICDIPR133 */ + volatile uint32_t ICDIPR134; /* ICDIPR134 */ + volatile uint32_t ICDIPR135; /* ICDIPR135 */ + volatile uint32_t ICDIPR136; /* ICDIPR136 */ + volatile uint32_t ICDIPR137; /* ICDIPR137 */ + volatile uint32_t ICDIPR138; /* ICDIPR138 */ + volatile uint32_t ICDIPR139; /* ICDIPR139 */ + volatile uint32_t ICDIPR140; /* ICDIPR140 */ + volatile uint32_t ICDIPR141; /* ICDIPR141 */ + volatile uint32_t ICDIPR142; /* ICDIPR142 */ + volatile uint32_t ICDIPR143; /* ICDIPR143 */ + volatile uint32_t ICDIPR144; /* ICDIPR144 */ + volatile uint32_t ICDIPR145; /* ICDIPR145 */ + volatile uint32_t ICDIPR146; /* ICDIPR146 */ + volatile uint8_t dummy200[436]; /* */ +#define INTC_ICDIPTR0_COUNT 147 + volatile uint32_t ICDIPTR0; /* ICDIPTR0 */ + volatile uint32_t ICDIPTR1; /* ICDIPTR1 */ + volatile uint32_t ICDIPTR2; /* ICDIPTR2 */ + volatile uint32_t ICDIPTR3; /* ICDIPTR3 */ + volatile uint32_t ICDIPTR4; /* ICDIPTR4 */ + volatile uint32_t ICDIPTR5; /* ICDIPTR5 */ + volatile uint32_t ICDIPTR6; /* ICDIPTR6 */ + volatile uint32_t ICDIPTR7; /* ICDIPTR7 */ + volatile uint32_t ICDIPTR8; /* ICDIPTR8 */ + volatile uint32_t ICDIPTR9; /* ICDIPTR9 */ + volatile uint32_t ICDIPTR10; /* ICDIPTR10 */ + volatile uint32_t ICDIPTR11; /* ICDIPTR11 */ + volatile uint32_t ICDIPTR12; /* ICDIPTR12 */ + volatile uint32_t ICDIPTR13; /* ICDIPTR13 */ + volatile uint32_t ICDIPTR14; /* ICDIPTR14 */ + volatile uint32_t ICDIPTR15; /* ICDIPTR15 */ + volatile uint32_t ICDIPTR16; /* ICDIPTR16 */ + volatile uint32_t ICDIPTR17; /* ICDIPTR17 */ + volatile uint32_t ICDIPTR18; /* ICDIPTR18 */ + volatile uint32_t ICDIPTR19; /* ICDIPTR19 */ + volatile uint32_t ICDIPTR20; /* ICDIPTR20 */ + volatile uint32_t ICDIPTR21; /* ICDIPTR21 */ + volatile uint32_t ICDIPTR22; /* ICDIPTR22 */ + volatile uint32_t ICDIPTR23; /* ICDIPTR23 */ + volatile uint32_t ICDIPTR24; /* ICDIPTR24 */ + volatile uint32_t ICDIPTR25; /* ICDIPTR25 */ + volatile uint32_t ICDIPTR26; /* ICDIPTR26 */ + volatile uint32_t ICDIPTR27; /* ICDIPTR27 */ + volatile uint32_t ICDIPTR28; /* ICDIPTR28 */ + volatile uint32_t ICDIPTR29; /* ICDIPTR29 */ + volatile uint32_t ICDIPTR30; /* ICDIPTR30 */ + volatile uint32_t ICDIPTR31; /* ICDIPTR31 */ + volatile uint32_t ICDIPTR32; /* ICDIPTR32 */ + volatile uint32_t ICDIPTR33; /* ICDIPTR33 */ + volatile uint32_t ICDIPTR34; /* ICDIPTR34 */ + volatile uint32_t ICDIPTR35; /* ICDIPTR35 */ + volatile uint32_t ICDIPTR36; /* ICDIPTR36 */ + volatile uint32_t ICDIPTR37; /* ICDIPTR37 */ + volatile uint32_t ICDIPTR38; /* ICDIPTR38 */ + volatile uint32_t ICDIPTR39; /* ICDIPTR39 */ + volatile uint32_t ICDIPTR40; /* ICDIPTR40 */ + volatile uint32_t ICDIPTR41; /* ICDIPTR41 */ + volatile uint32_t ICDIPTR42; /* ICDIPTR42 */ + volatile uint32_t ICDIPTR43; /* ICDIPTR43 */ + volatile uint32_t ICDIPTR44; /* ICDIPTR44 */ + volatile uint32_t ICDIPTR45; /* ICDIPTR45 */ + volatile uint32_t ICDIPTR46; /* ICDIPTR46 */ + volatile uint32_t ICDIPTR47; /* ICDIPTR47 */ + volatile uint32_t ICDIPTR48; /* ICDIPTR48 */ + volatile uint32_t ICDIPTR49; /* ICDIPTR49 */ + volatile uint32_t ICDIPTR50; /* ICDIPTR50 */ + volatile uint32_t ICDIPTR51; /* ICDIPTR51 */ + volatile uint32_t ICDIPTR52; /* ICDIPTR52 */ + volatile uint32_t ICDIPTR53; /* ICDIPTR53 */ + volatile uint32_t ICDIPTR54; /* ICDIPTR54 */ + volatile uint32_t ICDIPTR55; /* ICDIPTR55 */ + volatile uint32_t ICDIPTR56; /* ICDIPTR56 */ + volatile uint32_t ICDIPTR57; /* ICDIPTR57 */ + volatile uint32_t ICDIPTR58; /* ICDIPTR58 */ + volatile uint32_t ICDIPTR59; /* ICDIPTR59 */ + volatile uint32_t ICDIPTR60; /* ICDIPTR60 */ + volatile uint32_t ICDIPTR61; /* ICDIPTR61 */ + volatile uint32_t ICDIPTR62; /* ICDIPTR62 */ + volatile uint32_t ICDIPTR63; /* ICDIPTR63 */ + volatile uint32_t ICDIPTR64; /* ICDIPTR64 */ + volatile uint32_t ICDIPTR65; /* ICDIPTR65 */ + volatile uint32_t ICDIPTR66; /* ICDIPTR66 */ + volatile uint32_t ICDIPTR67; /* ICDIPTR67 */ + volatile uint32_t ICDIPTR68; /* ICDIPTR68 */ + volatile uint32_t ICDIPTR69; /* ICDIPTR69 */ + volatile uint32_t ICDIPTR70; /* ICDIPTR70 */ + volatile uint32_t ICDIPTR71; /* ICDIPTR71 */ + volatile uint32_t ICDIPTR72; /* ICDIPTR72 */ + volatile uint32_t ICDIPTR73; /* ICDIPTR73 */ + volatile uint32_t ICDIPTR74; /* ICDIPTR74 */ + volatile uint32_t ICDIPTR75; /* ICDIPTR75 */ + volatile uint32_t ICDIPTR76; /* ICDIPTR76 */ + volatile uint32_t ICDIPTR77; /* ICDIPTR77 */ + volatile uint32_t ICDIPTR78; /* ICDIPTR78 */ + volatile uint32_t ICDIPTR79; /* ICDIPTR79 */ + volatile uint32_t ICDIPTR80; /* ICDIPTR80 */ + volatile uint32_t ICDIPTR81; /* ICDIPTR81 */ + volatile uint32_t ICDIPTR82; /* ICDIPTR82 */ + volatile uint32_t ICDIPTR83; /* ICDIPTR83 */ + volatile uint32_t ICDIPTR84; /* ICDIPTR84 */ + volatile uint32_t ICDIPTR85; /* ICDIPTR85 */ + volatile uint32_t ICDIPTR86; /* ICDIPTR86 */ + volatile uint32_t ICDIPTR87; /* ICDIPTR87 */ + volatile uint32_t ICDIPTR88; /* ICDIPTR88 */ + volatile uint32_t ICDIPTR89; /* ICDIPTR89 */ + volatile uint32_t ICDIPTR90; /* ICDIPTR90 */ + volatile uint32_t ICDIPTR91; /* ICDIPTR91 */ + volatile uint32_t ICDIPTR92; /* ICDIPTR92 */ + volatile uint32_t ICDIPTR93; /* ICDIPTR93 */ + volatile uint32_t ICDIPTR94; /* ICDIPTR94 */ + volatile uint32_t ICDIPTR95; /* ICDIPTR95 */ + volatile uint32_t ICDIPTR96; /* ICDIPTR96 */ + volatile uint32_t ICDIPTR97; /* ICDIPTR97 */ + volatile uint32_t ICDIPTR98; /* ICDIPTR98 */ + volatile uint32_t ICDIPTR99; /* ICDIPTR99 */ + volatile uint32_t ICDIPTR100; /* ICDIPTR100 */ + volatile uint32_t ICDIPTR101; /* ICDIPTR101 */ + volatile uint32_t ICDIPTR102; /* ICDIPTR102 */ + volatile uint32_t ICDIPTR103; /* ICDIPTR103 */ + volatile uint32_t ICDIPTR104; /* ICDIPTR104 */ + volatile uint32_t ICDIPTR105; /* ICDIPTR105 */ + volatile uint32_t ICDIPTR106; /* ICDIPTR106 */ + volatile uint32_t ICDIPTR107; /* ICDIPTR107 */ + volatile uint32_t ICDIPTR108; /* ICDIPTR108 */ + volatile uint32_t ICDIPTR109; /* ICDIPTR109 */ + volatile uint32_t ICDIPTR110; /* ICDIPTR110 */ + volatile uint32_t ICDIPTR111; /* ICDIPTR111 */ + volatile uint32_t ICDIPTR112; /* ICDIPTR112 */ + volatile uint32_t ICDIPTR113; /* ICDIPTR113 */ + volatile uint32_t ICDIPTR114; /* ICDIPTR114 */ + volatile uint32_t ICDIPTR115; /* ICDIPTR115 */ + volatile uint32_t ICDIPTR116; /* ICDIPTR116 */ + volatile uint32_t ICDIPTR117; /* ICDIPTR117 */ + volatile uint32_t ICDIPTR118; /* ICDIPTR118 */ + volatile uint32_t ICDIPTR119; /* ICDIPTR119 */ + volatile uint32_t ICDIPTR120; /* ICDIPTR120 */ + volatile uint32_t ICDIPTR121; /* ICDIPTR121 */ + volatile uint32_t ICDIPTR122; /* ICDIPTR122 */ + volatile uint32_t ICDIPTR123; /* ICDIPTR123 */ + volatile uint32_t ICDIPTR124; /* ICDIPTR124 */ + volatile uint32_t ICDIPTR125; /* ICDIPTR125 */ + volatile uint32_t ICDIPTR126; /* ICDIPTR126 */ + volatile uint32_t ICDIPTR127; /* ICDIPTR127 */ + volatile uint32_t ICDIPTR128; /* ICDIPTR128 */ + volatile uint32_t ICDIPTR129; /* ICDIPTR129 */ + volatile uint32_t ICDIPTR130; /* ICDIPTR130 */ + volatile uint32_t ICDIPTR131; /* ICDIPTR131 */ + volatile uint32_t ICDIPTR132; /* ICDIPTR132 */ + volatile uint32_t ICDIPTR133; /* ICDIPTR133 */ + volatile uint32_t ICDIPTR134; /* ICDIPTR134 */ + volatile uint32_t ICDIPTR135; /* ICDIPTR135 */ + volatile uint32_t ICDIPTR136; /* ICDIPTR136 */ + volatile uint32_t ICDIPTR137; /* ICDIPTR137 */ + volatile uint32_t ICDIPTR138; /* ICDIPTR138 */ + volatile uint32_t ICDIPTR139; /* ICDIPTR139 */ + volatile uint32_t ICDIPTR140; /* ICDIPTR140 */ + volatile uint32_t ICDIPTR141; /* ICDIPTR141 */ + volatile uint32_t ICDIPTR142; /* ICDIPTR142 */ + volatile uint32_t ICDIPTR143; /* ICDIPTR143 */ + volatile uint32_t ICDIPTR144; /* ICDIPTR144 */ + volatile uint32_t ICDIPTR145; /* ICDIPTR145 */ + volatile uint32_t ICDIPTR146; /* ICDIPTR146 */ + volatile uint8_t dummy201[436]; /* */ +#define INTC_ICDICFR0_COUNT 37 + volatile uint32_t ICDICFR0; /* ICDICFR0 */ + volatile uint32_t ICDICFR1; /* ICDICFR1 */ + volatile uint32_t ICDICFR2; /* ICDICFR2 */ + volatile uint32_t ICDICFR3; /* ICDICFR3 */ + volatile uint32_t ICDICFR4; /* ICDICFR4 */ + volatile uint32_t ICDICFR5; /* ICDICFR5 */ + volatile uint32_t ICDICFR6; /* ICDICFR6 */ + volatile uint32_t ICDICFR7; /* ICDICFR7 */ + volatile uint32_t ICDICFR8; /* ICDICFR8 */ + volatile uint32_t ICDICFR9; /* ICDICFR9 */ + volatile uint32_t ICDICFR10; /* ICDICFR10 */ + volatile uint32_t ICDICFR11; /* ICDICFR11 */ + volatile uint32_t ICDICFR12; /* ICDICFR12 */ + volatile uint32_t ICDICFR13; /* ICDICFR13 */ + volatile uint32_t ICDICFR14; /* ICDICFR14 */ + volatile uint32_t ICDICFR15; /* ICDICFR15 */ + volatile uint32_t ICDICFR16; /* ICDICFR16 */ + volatile uint32_t ICDICFR17; /* ICDICFR17 */ + volatile uint32_t ICDICFR18; /* ICDICFR18 */ + volatile uint32_t ICDICFR19; /* ICDICFR19 */ + volatile uint32_t ICDICFR20; /* ICDICFR20 */ + volatile uint32_t ICDICFR21; /* ICDICFR21 */ + volatile uint32_t ICDICFR22; /* ICDICFR22 */ + volatile uint32_t ICDICFR23; /* ICDICFR23 */ + volatile uint32_t ICDICFR24; /* ICDICFR24 */ + volatile uint32_t ICDICFR25; /* ICDICFR25 */ + volatile uint32_t ICDICFR26; /* ICDICFR26 */ + volatile uint32_t ICDICFR27; /* ICDICFR27 */ + volatile uint32_t ICDICFR28; /* ICDICFR28 */ + volatile uint32_t ICDICFR29; /* ICDICFR29 */ + volatile uint32_t ICDICFR30; /* ICDICFR30 */ + volatile uint32_t ICDICFR31; /* ICDICFR31 */ + volatile uint32_t ICDICFR32; /* ICDICFR32 */ + volatile uint32_t ICDICFR33; /* ICDICFR33 */ + volatile uint32_t ICDICFR34; /* ICDICFR34 */ + volatile uint32_t ICDICFR35; /* ICDICFR35 */ + volatile uint32_t ICDICFR36; /* ICDICFR36 */ + volatile uint8_t dummy202[108]; /* */ + volatile uint32_t PPI_STATUS; /* PPI_STATUS */ +#define INTC_SPI_STATUS0_COUNT 17 + volatile uint32_t SPI_STATUS0; /* SPI_STATUS0 */ + volatile uint32_t SPI_STATUS1; /* SPI_STATUS1 */ + volatile uint32_t SPI_STATUS2; /* SPI_STATUS2 */ + volatile uint32_t SPI_STATUS3; /* SPI_STATUS3 */ + volatile uint32_t SPI_STATUS4; /* SPI_STATUS4 */ + volatile uint32_t SPI_STATUS5; /* SPI_STATUS5 */ + volatile uint32_t SPI_STATUS6; /* SPI_STATUS6 */ + volatile uint32_t SPI_STATUS7; /* SPI_STATUS7 */ + volatile uint32_t SPI_STATUS8; /* SPI_STATUS8 */ + volatile uint32_t SPI_STATUS9; /* SPI_STATUS9 */ + volatile uint32_t SPI_STATUS10; /* SPI_STATUS10 */ + volatile uint32_t SPI_STATUS11; /* SPI_STATUS11 */ + volatile uint32_t SPI_STATUS12; /* SPI_STATUS12 */ + volatile uint32_t SPI_STATUS13; /* SPI_STATUS13 */ + volatile uint32_t SPI_STATUS14; /* SPI_STATUS14 */ + volatile uint32_t SPI_STATUS15; /* SPI_STATUS15 */ + volatile uint32_t SPI_STATUS16; /* SPI_STATUS16 */ + volatile uint8_t dummy203[440]; /* */ + volatile uint32_t ICDSGIR; /* ICDSGIR */ + volatile uint8_t dummy204[252]; /* */ + volatile uint32_t ICCICR; /* ICCICR */ + volatile uint32_t ICCPMR; /* ICCPMR */ + volatile uint32_t ICCBPR; /* ICCBPR */ + volatile uint32_t ICCIAR; /* ICCIAR */ + volatile uint32_t ICCEOIR; /* ICCEOIR */ + volatile uint32_t ICCRPR; /* ICCRPR */ + volatile uint32_t ICCHPIR; /* ICCHPIR */ + volatile uint32_t ICCABPR; /* ICCABPR */ + volatile uint8_t dummy205[220]; /* */ + volatile uint32_t ICCIIDR; /* ICCIIDR */ + volatile uint8_t dummy206[350148352]; /* */ + volatile uint16_t ICR0; /* ICR0 */ + volatile uint16_t ICR1; /* ICR1 */ + volatile uint16_t IRQRR; /* IRQRR */ +}; + + +#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */ + + +#define INTCICDDCR INTC.ICDDCR +#define INTCICDICTR INTC.ICDICTR +#define INTCICDIIDR INTC.ICDIIDR +#define INTCICDISR0 INTC.ICDISR0 +#define INTCICDISR1 INTC.ICDISR1 +#define INTCICDISR2 INTC.ICDISR2 +#define INTCICDISR3 INTC.ICDISR3 +#define INTCICDISR4 INTC.ICDISR4 +#define INTCICDISR5 INTC.ICDISR5 +#define INTCICDISR6 INTC.ICDISR6 +#define INTCICDISR7 INTC.ICDISR7 +#define INTCICDISR8 INTC.ICDISR8 +#define INTCICDISR9 INTC.ICDISR9 +#define INTCICDISR10 INTC.ICDISR10 +#define INTCICDISR11 INTC.ICDISR11 +#define INTCICDISR12 INTC.ICDISR12 +#define INTCICDISR13 INTC.ICDISR13 +#define INTCICDISR14 INTC.ICDISR14 +#define INTCICDISR15 INTC.ICDISR15 +#define INTCICDISR16 INTC.ICDISR16 +#define INTCICDISR17 INTC.ICDISR17 +#define INTCICDISR18 INTC.ICDISR18 +#define INTCICDISER0 INTC.ICDISER0 +#define INTCICDISER1 INTC.ICDISER1 +#define INTCICDISER2 INTC.ICDISER2 +#define INTCICDISER3 INTC.ICDISER3 +#define INTCICDISER4 INTC.ICDISER4 +#define INTCICDISER5 INTC.ICDISER5 +#define INTCICDISER6 INTC.ICDISER6 +#define INTCICDISER7 INTC.ICDISER7 +#define INTCICDISER8 INTC.ICDISER8 +#define INTCICDISER9 INTC.ICDISER9 +#define INTCICDISER10 INTC.ICDISER10 +#define INTCICDISER11 INTC.ICDISER11 +#define INTCICDISER12 INTC.ICDISER12 +#define INTCICDISER13 INTC.ICDISER13 +#define INTCICDISER14 INTC.ICDISER14 +#define INTCICDISER15 INTC.ICDISER15 +#define INTCICDISER16 INTC.ICDISER16 +#define INTCICDISER17 INTC.ICDISER17 +#define INTCICDISER18 INTC.ICDISER18 +#define INTCICDICER0 INTC.ICDICER0 +#define INTCICDICER1 INTC.ICDICER1 +#define INTCICDICER2 INTC.ICDICER2 +#define INTCICDICER3 INTC.ICDICER3 +#define INTCICDICER4 INTC.ICDICER4 +#define INTCICDICER5 INTC.ICDICER5 +#define INTCICDICER6 INTC.ICDICER6 +#define INTCICDICER7 INTC.ICDICER7 +#define INTCICDICER8 INTC.ICDICER8 +#define INTCICDICER9 INTC.ICDICER9 +#define INTCICDICER10 INTC.ICDICER10 +#define INTCICDICER11 INTC.ICDICER11 +#define INTCICDICER12 INTC.ICDICER12 +#define INTCICDICER13 INTC.ICDICER13 +#define INTCICDICER14 INTC.ICDICER14 +#define INTCICDICER15 INTC.ICDICER15 +#define INTCICDICER16 INTC.ICDICER16 +#define INTCICDICER17 INTC.ICDICER17 +#define INTCICDICER18 INTC.ICDICER18 +#define INTCICDISPR0 INTC.ICDISPR0 +#define INTCICDISPR1 INTC.ICDISPR1 +#define INTCICDISPR2 INTC.ICDISPR2 +#define INTCICDISPR3 INTC.ICDISPR3 +#define INTCICDISPR4 INTC.ICDISPR4 +#define INTCICDISPR5 INTC.ICDISPR5 +#define INTCICDISPR6 INTC.ICDISPR6 +#define INTCICDISPR7 INTC.ICDISPR7 +#define INTCICDISPR8 INTC.ICDISPR8 +#define INTCICDISPR9 INTC.ICDISPR9 +#define INTCICDISPR10 INTC.ICDISPR10 +#define INTCICDISPR11 INTC.ICDISPR11 +#define INTCICDISPR12 INTC.ICDISPR12 +#define INTCICDISPR13 INTC.ICDISPR13 +#define INTCICDISPR14 INTC.ICDISPR14 +#define INTCICDISPR15 INTC.ICDISPR15 +#define INTCICDISPR16 INTC.ICDISPR16 +#define INTCICDISPR17 INTC.ICDISPR17 +#define INTCICDISPR18 INTC.ICDISPR18 +#define INTCICDICPR0 INTC.ICDICPR0 +#define INTCICDICPR1 INTC.ICDICPR1 +#define INTCICDICPR2 INTC.ICDICPR2 +#define INTCICDICPR3 INTC.ICDICPR3 +#define INTCICDICPR4 INTC.ICDICPR4 +#define INTCICDICPR5 INTC.ICDICPR5 +#define INTCICDICPR6 INTC.ICDICPR6 +#define INTCICDICPR7 INTC.ICDICPR7 +#define INTCICDICPR8 INTC.ICDICPR8 +#define INTCICDICPR9 INTC.ICDICPR9 +#define INTCICDICPR10 INTC.ICDICPR10 +#define INTCICDICPR11 INTC.ICDICPR11 +#define INTCICDICPR12 INTC.ICDICPR12 +#define INTCICDICPR13 INTC.ICDICPR13 +#define INTCICDICPR14 INTC.ICDICPR14 +#define INTCICDICPR15 INTC.ICDICPR15 +#define INTCICDICPR16 INTC.ICDICPR16 +#define INTCICDICPR17 INTC.ICDICPR17 +#define INTCICDICPR18 INTC.ICDICPR18 +#define INTCICDABR0 INTC.ICDABR0 +#define INTCICDABR1 INTC.ICDABR1 +#define INTCICDABR2 INTC.ICDABR2 +#define INTCICDABR3 INTC.ICDABR3 +#define INTCICDABR4 INTC.ICDABR4 +#define INTCICDABR5 INTC.ICDABR5 +#define INTCICDABR6 INTC.ICDABR6 +#define INTCICDABR7 INTC.ICDABR7 +#define INTCICDABR8 INTC.ICDABR8 +#define INTCICDABR9 INTC.ICDABR9 +#define INTCICDABR10 INTC.ICDABR10 +#define INTCICDABR11 INTC.ICDABR11 +#define INTCICDABR12 INTC.ICDABR12 +#define INTCICDABR13 INTC.ICDABR13 +#define INTCICDABR14 INTC.ICDABR14 +#define INTCICDABR15 INTC.ICDABR15 +#define INTCICDABR16 INTC.ICDABR16 +#define INTCICDABR17 INTC.ICDABR17 +#define INTCICDABR18 INTC.ICDABR18 +#define INTCICDIPR0 INTC.ICDIPR0 +#define INTCICDIPR1 INTC.ICDIPR1 +#define INTCICDIPR2 INTC.ICDIPR2 +#define INTCICDIPR3 INTC.ICDIPR3 +#define INTCICDIPR4 INTC.ICDIPR4 +#define INTCICDIPR5 INTC.ICDIPR5 +#define INTCICDIPR6 INTC.ICDIPR6 +#define INTCICDIPR7 INTC.ICDIPR7 +#define INTCICDIPR8 INTC.ICDIPR8 +#define INTCICDIPR9 INTC.ICDIPR9 +#define INTCICDIPR10 INTC.ICDIPR10 +#define INTCICDIPR11 INTC.ICDIPR11 +#define INTCICDIPR12 INTC.ICDIPR12 +#define INTCICDIPR13 INTC.ICDIPR13 +#define INTCICDIPR14 INTC.ICDIPR14 +#define INTCICDIPR15 INTC.ICDIPR15 +#define INTCICDIPR16 INTC.ICDIPR16 +#define INTCICDIPR17 INTC.ICDIPR17 +#define INTCICDIPR18 INTC.ICDIPR18 +#define INTCICDIPR19 INTC.ICDIPR19 +#define INTCICDIPR20 INTC.ICDIPR20 +#define INTCICDIPR21 INTC.ICDIPR21 +#define INTCICDIPR22 INTC.ICDIPR22 +#define INTCICDIPR23 INTC.ICDIPR23 +#define INTCICDIPR24 INTC.ICDIPR24 +#define INTCICDIPR25 INTC.ICDIPR25 +#define INTCICDIPR26 INTC.ICDIPR26 +#define INTCICDIPR27 INTC.ICDIPR27 +#define INTCICDIPR28 INTC.ICDIPR28 +#define INTCICDIPR29 INTC.ICDIPR29 +#define INTCICDIPR30 INTC.ICDIPR30 +#define INTCICDIPR31 INTC.ICDIPR31 +#define INTCICDIPR32 INTC.ICDIPR32 +#define INTCICDIPR33 INTC.ICDIPR33 +#define INTCICDIPR34 INTC.ICDIPR34 +#define INTCICDIPR35 INTC.ICDIPR35 +#define INTCICDIPR36 INTC.ICDIPR36 +#define INTCICDIPR37 INTC.ICDIPR37 +#define INTCICDIPR38 INTC.ICDIPR38 +#define INTCICDIPR39 INTC.ICDIPR39 +#define INTCICDIPR40 INTC.ICDIPR40 +#define INTCICDIPR41 INTC.ICDIPR41 +#define INTCICDIPR42 INTC.ICDIPR42 +#define INTCICDIPR43 INTC.ICDIPR43 +#define INTCICDIPR44 INTC.ICDIPR44 +#define INTCICDIPR45 INTC.ICDIPR45 +#define INTCICDIPR46 INTC.ICDIPR46 +#define INTCICDIPR47 INTC.ICDIPR47 +#define INTCICDIPR48 INTC.ICDIPR48 +#define INTCICDIPR49 INTC.ICDIPR49 +#define INTCICDIPR50 INTC.ICDIPR50 +#define INTCICDIPR51 INTC.ICDIPR51 +#define INTCICDIPR52 INTC.ICDIPR52 +#define INTCICDIPR53 INTC.ICDIPR53 +#define INTCICDIPR54 INTC.ICDIPR54 +#define INTCICDIPR55 INTC.ICDIPR55 +#define INTCICDIPR56 INTC.ICDIPR56 +#define INTCICDIPR57 INTC.ICDIPR57 +#define INTCICDIPR58 INTC.ICDIPR58 +#define INTCICDIPR59 INTC.ICDIPR59 +#define INTCICDIPR60 INTC.ICDIPR60 +#define INTCICDIPR61 INTC.ICDIPR61 +#define INTCICDIPR62 INTC.ICDIPR62 +#define INTCICDIPR63 INTC.ICDIPR63 +#define INTCICDIPR64 INTC.ICDIPR64 +#define INTCICDIPR65 INTC.ICDIPR65 +#define INTCICDIPR66 INTC.ICDIPR66 +#define INTCICDIPR67 INTC.ICDIPR67 +#define INTCICDIPR68 INTC.ICDIPR68 +#define INTCICDIPR69 INTC.ICDIPR69 +#define INTCICDIPR70 INTC.ICDIPR70 +#define INTCICDIPR71 INTC.ICDIPR71 +#define INTCICDIPR72 INTC.ICDIPR72 +#define INTCICDIPR73 INTC.ICDIPR73 +#define INTCICDIPR74 INTC.ICDIPR74 +#define INTCICDIPR75 INTC.ICDIPR75 +#define INTCICDIPR76 INTC.ICDIPR76 +#define INTCICDIPR77 INTC.ICDIPR77 +#define INTCICDIPR78 INTC.ICDIPR78 +#define INTCICDIPR79 INTC.ICDIPR79 +#define INTCICDIPR80 INTC.ICDIPR80 +#define INTCICDIPR81 INTC.ICDIPR81 +#define INTCICDIPR82 INTC.ICDIPR82 +#define INTCICDIPR83 INTC.ICDIPR83 +#define INTCICDIPR84 INTC.ICDIPR84 +#define INTCICDIPR85 INTC.ICDIPR85 +#define INTCICDIPR86 INTC.ICDIPR86 +#define INTCICDIPR87 INTC.ICDIPR87 +#define INTCICDIPR88 INTC.ICDIPR88 +#define INTCICDIPR89 INTC.ICDIPR89 +#define INTCICDIPR90 INTC.ICDIPR90 +#define INTCICDIPR91 INTC.ICDIPR91 +#define INTCICDIPR92 INTC.ICDIPR92 +#define INTCICDIPR93 INTC.ICDIPR93 +#define INTCICDIPR94 INTC.ICDIPR94 +#define INTCICDIPR95 INTC.ICDIPR95 +#define INTCICDIPR96 INTC.ICDIPR96 +#define INTCICDIPR97 INTC.ICDIPR97 +#define INTCICDIPR98 INTC.ICDIPR98 +#define INTCICDIPR99 INTC.ICDIPR99 +#define INTCICDIPR100 INTC.ICDIPR100 +#define INTCICDIPR101 INTC.ICDIPR101 +#define INTCICDIPR102 INTC.ICDIPR102 +#define INTCICDIPR103 INTC.ICDIPR103 +#define INTCICDIPR104 INTC.ICDIPR104 +#define INTCICDIPR105 INTC.ICDIPR105 +#define INTCICDIPR106 INTC.ICDIPR106 +#define INTCICDIPR107 INTC.ICDIPR107 +#define INTCICDIPR108 INTC.ICDIPR108 +#define INTCICDIPR109 INTC.ICDIPR109 +#define INTCICDIPR110 INTC.ICDIPR110 +#define INTCICDIPR111 INTC.ICDIPR111 +#define INTCICDIPR112 INTC.ICDIPR112 +#define INTCICDIPR113 INTC.ICDIPR113 +#define INTCICDIPR114 INTC.ICDIPR114 +#define INTCICDIPR115 INTC.ICDIPR115 +#define INTCICDIPR116 INTC.ICDIPR116 +#define INTCICDIPR117 INTC.ICDIPR117 +#define INTCICDIPR118 INTC.ICDIPR118 +#define INTCICDIPR119 INTC.ICDIPR119 +#define INTCICDIPR120 INTC.ICDIPR120 +#define INTCICDIPR121 INTC.ICDIPR121 +#define INTCICDIPR122 INTC.ICDIPR122 +#define INTCICDIPR123 INTC.ICDIPR123 +#define INTCICDIPR124 INTC.ICDIPR124 +#define INTCICDIPR125 INTC.ICDIPR125 +#define INTCICDIPR126 INTC.ICDIPR126 +#define INTCICDIPR127 INTC.ICDIPR127 +#define INTCICDIPR128 INTC.ICDIPR128 +#define INTCICDIPR129 INTC.ICDIPR129 +#define INTCICDIPR130 INTC.ICDIPR130 +#define INTCICDIPR131 INTC.ICDIPR131 +#define INTCICDIPR132 INTC.ICDIPR132 +#define INTCICDIPR133 INTC.ICDIPR133 +#define INTCICDIPR134 INTC.ICDIPR134 +#define INTCICDIPR135 INTC.ICDIPR135 +#define INTCICDIPR136 INTC.ICDIPR136 +#define INTCICDIPR137 INTC.ICDIPR137 +#define INTCICDIPR138 INTC.ICDIPR138 +#define INTCICDIPR139 INTC.ICDIPR139 +#define INTCICDIPR140 INTC.ICDIPR140 +#define INTCICDIPR141 INTC.ICDIPR141 +#define INTCICDIPR142 INTC.ICDIPR142 +#define INTCICDIPR143 INTC.ICDIPR143 +#define INTCICDIPR144 INTC.ICDIPR144 +#define INTCICDIPR145 INTC.ICDIPR145 +#define INTCICDIPR146 INTC.ICDIPR146 +#define INTCICDIPTR0 INTC.ICDIPTR0 +#define INTCICDIPTR1 INTC.ICDIPTR1 +#define INTCICDIPTR2 INTC.ICDIPTR2 +#define INTCICDIPTR3 INTC.ICDIPTR3 +#define INTCICDIPTR4 INTC.ICDIPTR4 +#define INTCICDIPTR5 INTC.ICDIPTR5 +#define INTCICDIPTR6 INTC.ICDIPTR6 +#define INTCICDIPTR7 INTC.ICDIPTR7 +#define INTCICDIPTR8 INTC.ICDIPTR8 +#define INTCICDIPTR9 INTC.ICDIPTR9 +#define INTCICDIPTR10 INTC.ICDIPTR10 +#define INTCICDIPTR11 INTC.ICDIPTR11 +#define INTCICDIPTR12 INTC.ICDIPTR12 +#define INTCICDIPTR13 INTC.ICDIPTR13 +#define INTCICDIPTR14 INTC.ICDIPTR14 +#define INTCICDIPTR15 INTC.ICDIPTR15 +#define INTCICDIPTR16 INTC.ICDIPTR16 +#define INTCICDIPTR17 INTC.ICDIPTR17 +#define INTCICDIPTR18 INTC.ICDIPTR18 +#define INTCICDIPTR19 INTC.ICDIPTR19 +#define INTCICDIPTR20 INTC.ICDIPTR20 +#define INTCICDIPTR21 INTC.ICDIPTR21 +#define INTCICDIPTR22 INTC.ICDIPTR22 +#define INTCICDIPTR23 INTC.ICDIPTR23 +#define INTCICDIPTR24 INTC.ICDIPTR24 +#define INTCICDIPTR25 INTC.ICDIPTR25 +#define INTCICDIPTR26 INTC.ICDIPTR26 +#define INTCICDIPTR27 INTC.ICDIPTR27 +#define INTCICDIPTR28 INTC.ICDIPTR28 +#define INTCICDIPTR29 INTC.ICDIPTR29 +#define INTCICDIPTR30 INTC.ICDIPTR30 +#define INTCICDIPTR31 INTC.ICDIPTR31 +#define INTCICDIPTR32 INTC.ICDIPTR32 +#define INTCICDIPTR33 INTC.ICDIPTR33 +#define INTCICDIPTR34 INTC.ICDIPTR34 +#define INTCICDIPTR35 INTC.ICDIPTR35 +#define INTCICDIPTR36 INTC.ICDIPTR36 +#define INTCICDIPTR37 INTC.ICDIPTR37 +#define INTCICDIPTR38 INTC.ICDIPTR38 +#define INTCICDIPTR39 INTC.ICDIPTR39 +#define INTCICDIPTR40 INTC.ICDIPTR40 +#define INTCICDIPTR41 INTC.ICDIPTR41 +#define INTCICDIPTR42 INTC.ICDIPTR42 +#define INTCICDIPTR43 INTC.ICDIPTR43 +#define INTCICDIPTR44 INTC.ICDIPTR44 +#define INTCICDIPTR45 INTC.ICDIPTR45 +#define INTCICDIPTR46 INTC.ICDIPTR46 +#define INTCICDIPTR47 INTC.ICDIPTR47 +#define INTCICDIPTR48 INTC.ICDIPTR48 +#define INTCICDIPTR49 INTC.ICDIPTR49 +#define INTCICDIPTR50 INTC.ICDIPTR50 +#define INTCICDIPTR51 INTC.ICDIPTR51 +#define INTCICDIPTR52 INTC.ICDIPTR52 +#define INTCICDIPTR53 INTC.ICDIPTR53 +#define INTCICDIPTR54 INTC.ICDIPTR54 +#define INTCICDIPTR55 INTC.ICDIPTR55 +#define INTCICDIPTR56 INTC.ICDIPTR56 +#define INTCICDIPTR57 INTC.ICDIPTR57 +#define INTCICDIPTR58 INTC.ICDIPTR58 +#define INTCICDIPTR59 INTC.ICDIPTR59 +#define INTCICDIPTR60 INTC.ICDIPTR60 +#define INTCICDIPTR61 INTC.ICDIPTR61 +#define INTCICDIPTR62 INTC.ICDIPTR62 +#define INTCICDIPTR63 INTC.ICDIPTR63 +#define INTCICDIPTR64 INTC.ICDIPTR64 +#define INTCICDIPTR65 INTC.ICDIPTR65 +#define INTCICDIPTR66 INTC.ICDIPTR66 +#define INTCICDIPTR67 INTC.ICDIPTR67 +#define INTCICDIPTR68 INTC.ICDIPTR68 +#define INTCICDIPTR69 INTC.ICDIPTR69 +#define INTCICDIPTR70 INTC.ICDIPTR70 +#define INTCICDIPTR71 INTC.ICDIPTR71 +#define INTCICDIPTR72 INTC.ICDIPTR72 +#define INTCICDIPTR73 INTC.ICDIPTR73 +#define INTCICDIPTR74 INTC.ICDIPTR74 +#define INTCICDIPTR75 INTC.ICDIPTR75 +#define INTCICDIPTR76 INTC.ICDIPTR76 +#define INTCICDIPTR77 INTC.ICDIPTR77 +#define INTCICDIPTR78 INTC.ICDIPTR78 +#define INTCICDIPTR79 INTC.ICDIPTR79 +#define INTCICDIPTR80 INTC.ICDIPTR80 +#define INTCICDIPTR81 INTC.ICDIPTR81 +#define INTCICDIPTR82 INTC.ICDIPTR82 +#define INTCICDIPTR83 INTC.ICDIPTR83 +#define INTCICDIPTR84 INTC.ICDIPTR84 +#define INTCICDIPTR85 INTC.ICDIPTR85 +#define INTCICDIPTR86 INTC.ICDIPTR86 +#define INTCICDIPTR87 INTC.ICDIPTR87 +#define INTCICDIPTR88 INTC.ICDIPTR88 +#define INTCICDIPTR89 INTC.ICDIPTR89 +#define INTCICDIPTR90 INTC.ICDIPTR90 +#define INTCICDIPTR91 INTC.ICDIPTR91 +#define INTCICDIPTR92 INTC.ICDIPTR92 +#define INTCICDIPTR93 INTC.ICDIPTR93 +#define INTCICDIPTR94 INTC.ICDIPTR94 +#define INTCICDIPTR95 INTC.ICDIPTR95 +#define INTCICDIPTR96 INTC.ICDIPTR96 +#define INTCICDIPTR97 INTC.ICDIPTR97 +#define INTCICDIPTR98 INTC.ICDIPTR98 +#define INTCICDIPTR99 INTC.ICDIPTR99 +#define INTCICDIPTR100 INTC.ICDIPTR100 +#define INTCICDIPTR101 INTC.ICDIPTR101 +#define INTCICDIPTR102 INTC.ICDIPTR102 +#define INTCICDIPTR103 INTC.ICDIPTR103 +#define INTCICDIPTR104 INTC.ICDIPTR104 +#define INTCICDIPTR105 INTC.ICDIPTR105 +#define INTCICDIPTR106 INTC.ICDIPTR106 +#define INTCICDIPTR107 INTC.ICDIPTR107 +#define INTCICDIPTR108 INTC.ICDIPTR108 +#define INTCICDIPTR109 INTC.ICDIPTR109 +#define INTCICDIPTR110 INTC.ICDIPTR110 +#define INTCICDIPTR111 INTC.ICDIPTR111 +#define INTCICDIPTR112 INTC.ICDIPTR112 +#define INTCICDIPTR113 INTC.ICDIPTR113 +#define INTCICDIPTR114 INTC.ICDIPTR114 +#define INTCICDIPTR115 INTC.ICDIPTR115 +#define INTCICDIPTR116 INTC.ICDIPTR116 +#define INTCICDIPTR117 INTC.ICDIPTR117 +#define INTCICDIPTR118 INTC.ICDIPTR118 +#define INTCICDIPTR119 INTC.ICDIPTR119 +#define INTCICDIPTR120 INTC.ICDIPTR120 +#define INTCICDIPTR121 INTC.ICDIPTR121 +#define INTCICDIPTR122 INTC.ICDIPTR122 +#define INTCICDIPTR123 INTC.ICDIPTR123 +#define INTCICDIPTR124 INTC.ICDIPTR124 +#define INTCICDIPTR125 INTC.ICDIPTR125 +#define INTCICDIPTR126 INTC.ICDIPTR126 +#define INTCICDIPTR127 INTC.ICDIPTR127 +#define INTCICDIPTR128 INTC.ICDIPTR128 +#define INTCICDIPTR129 INTC.ICDIPTR129 +#define INTCICDIPTR130 INTC.ICDIPTR130 +#define INTCICDIPTR131 INTC.ICDIPTR131 +#define INTCICDIPTR132 INTC.ICDIPTR132 +#define INTCICDIPTR133 INTC.ICDIPTR133 +#define INTCICDIPTR134 INTC.ICDIPTR134 +#define INTCICDIPTR135 INTC.ICDIPTR135 +#define INTCICDIPTR136 INTC.ICDIPTR136 +#define INTCICDIPTR137 INTC.ICDIPTR137 +#define INTCICDIPTR138 INTC.ICDIPTR138 +#define INTCICDIPTR139 INTC.ICDIPTR139 +#define INTCICDIPTR140 INTC.ICDIPTR140 +#define INTCICDIPTR141 INTC.ICDIPTR141 +#define INTCICDIPTR142 INTC.ICDIPTR142 +#define INTCICDIPTR143 INTC.ICDIPTR143 +#define INTCICDIPTR144 INTC.ICDIPTR144 +#define INTCICDIPTR145 INTC.ICDIPTR145 +#define INTCICDIPTR146 INTC.ICDIPTR146 +#define INTCICDICFR0 INTC.ICDICFR0 +#define INTCICDICFR1 INTC.ICDICFR1 +#define INTCICDICFR2 INTC.ICDICFR2 +#define INTCICDICFR3 INTC.ICDICFR3 +#define INTCICDICFR4 INTC.ICDICFR4 +#define INTCICDICFR5 INTC.ICDICFR5 +#define INTCICDICFR6 INTC.ICDICFR6 +#define INTCICDICFR7 INTC.ICDICFR7 +#define INTCICDICFR8 INTC.ICDICFR8 +#define INTCICDICFR9 INTC.ICDICFR9 +#define INTCICDICFR10 INTC.ICDICFR10 +#define INTCICDICFR11 INTC.ICDICFR11 +#define INTCICDICFR12 INTC.ICDICFR12 +#define INTCICDICFR13 INTC.ICDICFR13 +#define INTCICDICFR14 INTC.ICDICFR14 +#define INTCICDICFR15 INTC.ICDICFR15 +#define INTCICDICFR16 INTC.ICDICFR16 +#define INTCICDICFR17 INTC.ICDICFR17 +#define INTCICDICFR18 INTC.ICDICFR18 +#define INTCICDICFR19 INTC.ICDICFR19 +#define INTCICDICFR20 INTC.ICDICFR20 +#define INTCICDICFR21 INTC.ICDICFR21 +#define INTCICDICFR22 INTC.ICDICFR22 +#define INTCICDICFR23 INTC.ICDICFR23 +#define INTCICDICFR24 INTC.ICDICFR24 +#define INTCICDICFR25 INTC.ICDICFR25 +#define INTCICDICFR26 INTC.ICDICFR26 +#define INTCICDICFR27 INTC.ICDICFR27 +#define INTCICDICFR28 INTC.ICDICFR28 +#define INTCICDICFR29 INTC.ICDICFR29 +#define INTCICDICFR30 INTC.ICDICFR30 +#define INTCICDICFR31 INTC.ICDICFR31 +#define INTCICDICFR32 INTC.ICDICFR32 +#define INTCICDICFR33 INTC.ICDICFR33 +#define INTCICDICFR34 INTC.ICDICFR34 +#define INTCICDICFR35 INTC.ICDICFR35 +#define INTCICDICFR36 INTC.ICDICFR36 +#define INTCPPI_STATUS INTC.PPI_STATUS +#define INTCSPI_STATUS0 INTC.SPI_STATUS0 +#define INTCSPI_STATUS1 INTC.SPI_STATUS1 +#define INTCSPI_STATUS2 INTC.SPI_STATUS2 +#define INTCSPI_STATUS3 INTC.SPI_STATUS3 +#define INTCSPI_STATUS4 INTC.SPI_STATUS4 +#define INTCSPI_STATUS5 INTC.SPI_STATUS5 +#define INTCSPI_STATUS6 INTC.SPI_STATUS6 +#define INTCSPI_STATUS7 INTC.SPI_STATUS7 +#define INTCSPI_STATUS8 INTC.SPI_STATUS8 +#define INTCSPI_STATUS9 INTC.SPI_STATUS9 +#define INTCSPI_STATUS10 INTC.SPI_STATUS10 +#define INTCSPI_STATUS11 INTC.SPI_STATUS11 +#define INTCSPI_STATUS12 INTC.SPI_STATUS12 +#define INTCSPI_STATUS13 INTC.SPI_STATUS13 +#define INTCSPI_STATUS14 INTC.SPI_STATUS14 +#define INTCSPI_STATUS15 INTC.SPI_STATUS15 +#define INTCSPI_STATUS16 INTC.SPI_STATUS16 +#define INTCICDSGIR INTC.ICDSGIR +#define INTCICCICR INTC.ICCICR +#define INTCICCPMR INTC.ICCPMR +#define INTCICCBPR INTC.ICCBPR +#define INTCICCIAR INTC.ICCIAR +#define INTCICCEOIR INTC.ICCEOIR +#define INTCICCRPR INTC.ICCRPR +#define INTCICCHPIR INTC.ICCHPIR +#define INTCICCABPR INTC.ICCABPR +#define INTCICCIIDR INTC.ICCIIDR +#define INTCICR0 INTC.ICR0 +#define INTCICR1 INTC.ICR1 +#define INTCIRQRR INTC.IRQRR +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/irda_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/irda_iodefine.h new file mode 100644 index 0000000000..14665ef2d6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/irda_iodefine.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : irda_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef IRDA_IODEFINE_H +#define IRDA_IODEFINE_H + +struct st_irda +{ /* IRDA */ + volatile uint8_t IRCR; /* IRCR */ +}; + + +#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */ + + +#define IRDAIRCR IRDA.IRCR +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/jcu_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/jcu_iodefine.h new file mode 100644 index 0000000000..fa34ce2150 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/jcu_iodefine.h @@ -0,0 +1,169 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : jcu_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef JCU_IODEFINE_H +#define JCU_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_jcu +{ /* JCU */ + volatile uint8_t JCMOD; /* JCMOD */ + volatile uint8_t JCCMD; /* JCCMD */ + volatile uint8_t dummy145[1]; /* */ + volatile uint8_t JCQTN; /* JCQTN */ + volatile uint8_t JCHTN; /* JCHTN */ + volatile uint8_t JCDRIU; /* JCDRIU */ + volatile uint8_t JCDRID; /* JCDRID */ + volatile uint8_t JCVSZU; /* JCVSZU */ + volatile uint8_t JCVSZD; /* JCVSZD */ + volatile uint8_t JCHSZU; /* JCHSZU */ + volatile uint8_t JCHSZD; /* JCHSZD */ + volatile uint8_t JCDTCU; /* JCDTCU */ + volatile uint8_t JCDTCM; /* JCDTCM */ + volatile uint8_t JCDTCD; /* JCDTCD */ + volatile uint8_t JINTE0; /* JINTE0 */ + volatile uint8_t JINTS0; /* JINTS0 */ + volatile uint8_t JCDERR; /* JCDERR */ + volatile uint8_t JCRST; /* JCRST */ + volatile uint8_t dummy146[46]; /* */ + volatile uint32_t JIFECNT; /* JIFECNT */ + volatile uint32_t JIFESA; /* JIFESA */ + volatile uint32_t JIFESOFST; /* JIFESOFST */ + volatile uint32_t JIFEDA; /* JIFEDA */ + volatile uint32_t JIFESLC; /* JIFESLC */ + volatile uint32_t JIFEDDC; /* JIFEDDC */ + volatile uint32_t JIFDCNT; /* JIFDCNT */ + volatile uint32_t JIFDSA; /* JIFDSA */ + volatile uint32_t JIFDDOFST; /* JIFDDOFST */ + volatile uint32_t JIFDDA; /* JIFDDA */ + volatile uint32_t JIFDSDC; /* JIFDSDC */ + volatile uint32_t JIFDDLC; /* JIFDDLC */ + volatile uint32_t JIFDADT; /* JIFDADT */ + volatile uint8_t dummy147[24]; /* */ + volatile uint32_t JINTE1; /* JINTE1 */ + volatile uint32_t JINTS1; /* JINTS1 */ + volatile uint32_t JIFESVSZ; /* JIFESVSZ */ + volatile uint32_t JIFESHSZ; /* JIFESHSZ */ + volatile uint8_t dummy148[100]; /* */ +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL0; /* JCQTBL0 */ + volatile uint8_t dummy149[63]; /* */ +/* end of struct st_jcu_from_jcqtbl0 */ +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL1; /* JCQTBL1 */ + volatile uint8_t dummy150[63]; /* */ +/* end of struct st_jcu_from_jcqtbl0 */ +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL2; /* JCQTBL2 */ + volatile uint8_t dummy151[63]; /* */ +/* end of struct st_jcu_from_jcqtbl0 */ +/* start of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCQTBL3; /* JCQTBL3 */ + volatile uint8_t dummy152[63]; /* */ +/* end of struct st_jcu_from_jcqtbl0 */ + volatile uint8_t JCHTBD0; /* JCHTBD0 */ + volatile uint8_t dummy153[31]; /* */ + volatile uint8_t JCHTBA0; /* JCHTBA0 */ + volatile uint8_t dummy154[223]; /* */ + volatile uint8_t JCHTBD1; /* JCHTBD1 */ + volatile uint8_t dummy155[31]; /* */ + volatile uint8_t JCHTBA1; /* JCHTBA1 */ +}; + + +struct st_jcu_from_jcqtbl0 +{ + volatile uint8_t JCQTBL0; /* JCQTBL0 */ + volatile uint8_t dummy1[63]; /* */ +}; + + +#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */ + + +/* Start of channnel array defines of JCU */ + +/* Channnel array defines of JCU_JCQTBL0 */ +/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */ +#define JCU_JCQTBL0_COUNT 4 +#define JCU_JCQTBL0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */ +#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */ +#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */ +#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */ + +/* End of channnel array defines of JCU */ + + +#define JCUJCMOD JCU.JCMOD +#define JCUJCCMD JCU.JCCMD +#define JCUJCQTN JCU.JCQTN +#define JCUJCHTN JCU.JCHTN +#define JCUJCDRIU JCU.JCDRIU +#define JCUJCDRID JCU.JCDRID +#define JCUJCVSZU JCU.JCVSZU +#define JCUJCVSZD JCU.JCVSZD +#define JCUJCHSZU JCU.JCHSZU +#define JCUJCHSZD JCU.JCHSZD +#define JCUJCDTCU JCU.JCDTCU +#define JCUJCDTCM JCU.JCDTCM +#define JCUJCDTCD JCU.JCDTCD +#define JCUJINTE0 JCU.JINTE0 +#define JCUJINTS0 JCU.JINTS0 +#define JCUJCDERR JCU.JCDERR +#define JCUJCRST JCU.JCRST +#define JCUJIFECNT JCU.JIFECNT +#define JCUJIFESA JCU.JIFESA +#define JCUJIFESOFST JCU.JIFESOFST +#define JCUJIFEDA JCU.JIFEDA +#define JCUJIFESLC JCU.JIFESLC +#define JCUJIFEDDC JCU.JIFEDDC +#define JCUJIFDCNT JCU.JIFDCNT +#define JCUJIFDSA JCU.JIFDSA +#define JCUJIFDDOFST JCU.JIFDDOFST +#define JCUJIFDDA JCU.JIFDDA +#define JCUJIFDSDC JCU.JIFDSDC +#define JCUJIFDDLC JCU.JIFDDLC +#define JCUJIFDADT JCU.JIFDADT +#define JCUJINTE1 JCU.JINTE1 +#define JCUJINTS1 JCU.JINTS1 +#define JCUJIFESVSZ JCU.JIFESVSZ +#define JCUJIFESHSZ JCU.JIFESHSZ +#define JCUJCQTBL0 JCU.JCQTBL0 +#define JCUJCQTBL1 JCU.JCQTBL1 +#define JCUJCQTBL2 JCU.JCQTBL2 +#define JCUJCQTBL3 JCU.JCQTBL3 +#define JCUJCHTBD0 JCU.JCHTBD0 +#define JCUJCHTBA0 JCU.JCHTBA0 +#define JCUJCHTBD1 JCU.JCHTBD1 +#define JCUJCHTBA1 JCU.JCHTBA1 +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/l2c_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/l2c_iodefine.h new file mode 100644 index 0000000000..ba6cb180bf --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/l2c_iodefine.h @@ -0,0 +1,195 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : l2c_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef L2C_IODEFINE_H +#define L2C_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_l2c +{ /* L2C */ + volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */ + volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */ + volatile uint8_t dummy8[248]; /* */ + volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */ + volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */ + volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */ + volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */ + volatile uint8_t dummy9[240]; /* */ + volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */ + volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */ + volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */ + volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */ + volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */ + volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */ + volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */ + volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */ + volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */ + volatile uint8_t dummy10[1292]; /* */ + volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */ + volatile uint8_t dummy11[60]; /* */ + volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */ + volatile uint8_t dummy12[8]; /* */ + volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */ + volatile uint8_t dummy13[48]; /* */ + volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */ + volatile uint8_t dummy14[4]; /* */ + volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */ + volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */ + volatile uint8_t dummy15[48]; /* */ + volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */ + volatile uint8_t dummy16[4]; /* */ + volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */ + volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */ + volatile uint8_t dummy17[256]; /* */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ + volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */ + volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */ + volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */ + volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */ + volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */ + volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */ + volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ +/* start of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */ + volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */ +/* end of struct st_l2c_from_reg9_d_lockdown0 */ + volatile uint8_t dummy18[16]; /* */ + volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */ + volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */ + volatile uint8_t dummy19[680]; /* */ + volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */ + volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */ + volatile uint8_t dummy20[824]; /* */ + volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */ + volatile uint8_t dummy21[28]; /* */ + volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */ + volatile uint8_t dummy22[28]; /* */ + volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */ +}; + + +struct st_l2c_from_reg9_d_lockdown0 +{ + volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ + volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ +}; + + +#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */ + + +/* Start of channnel array defines of L2C */ + +/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */ +/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */ +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT 8 +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */ +#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */ +#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */ +#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */ +#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */ +#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */ +#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */ +#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */ + +/* End of channnel array defines of L2C */ + + +#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID +#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE +#define L2CREG1_CONTROL L2C.REG1_CONTROL +#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL +#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL +#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL +#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL +#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG +#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG +#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1 +#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0 +#define L2CREG2_INT_MASK L2C.REG2_INT_MASK +#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS +#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS +#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR +#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC +#define L2CREG7_INV_PA L2C.REG7_INV_PA +#define L2CREG7_INV_WAY L2C.REG7_INV_WAY +#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA +#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX +#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY +#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA +#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX +#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY +#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0 +#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0 +#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1 +#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1 +#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2 +#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2 +#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3 +#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3 +#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4 +#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4 +#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5 +#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5 +#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6 +#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6 +#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7 +#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7 +#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN +#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY +#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START +#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END +#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL +#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL +#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lin_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lin_iodefine.h new file mode 100644 index 0000000000..d46e7770b3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lin_iodefine.h @@ -0,0 +1,174 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : lin_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef LIN_IODEFINE_H +#define LIN_IODEFINE_H +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_lin +{ /* LIN */ + volatile uint8_t dummy1[1]; /* */ + volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */ + union iodefine_reg16_8_t RLN3nLBRP01; /* RLN3nLBRP01 */ + + volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */ + volatile uint8_t dummy2[3]; /* */ + volatile uint8_t RLN3nLMD; /* RLN3nLMD */ + volatile uint8_t RLN3nLBFC; /* RLN3nLBFC */ + volatile uint8_t RLN3nLSC; /* RLN3nLSC */ + volatile uint8_t RLN3nLWUP; /* RLN3nLWUP */ + volatile uint8_t RLN3nLIE; /* RLN3nLIE */ + volatile uint8_t RLN3nLEDE; /* RLN3nLEDE */ + volatile uint8_t RLN3nLCUC; /* RLN3nLCUC */ + volatile uint8_t dummy3[1]; /* */ + volatile uint8_t RLN3nLTRC; /* RLN3nLTRC */ + volatile uint8_t RLN3nLMST; /* RLN3nLMST */ + volatile uint8_t RLN3nLST; /* RLN3nLST */ + volatile uint8_t RLN3nLEST; /* RLN3nLEST */ + volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */ + volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */ + volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */ + volatile uint8_t RLN3nLUDB0; /* RLN3nLUDB0 */ +#define LIN_LDBn_COUNT 8 + volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */ + volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */ + volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */ + volatile uint8_t RLN3nLDBR4; /* RLN3nLDBR4 */ + volatile uint8_t RLN3nLDBR5; /* RLN3nLDBR5 */ + volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */ + volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */ + volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */ + volatile uint8_t RLN3nLUOER; /* RLN3nLUOER */ + volatile uint8_t RLN3nLUOR1; /* RLN3nLUOR1 */ + volatile uint8_t dummy4[2]; /* */ + union iodefine_reg16_8_t RLN3nLUTDR; /* RLN3nLUTDR */ + union iodefine_reg16_8_t RLN3nLURDR; /* RLN3nLURDR */ + union iodefine_reg16_8_t RLN3nLUWTDR; /* RLN3nLUWTDR */ + +}; + + +#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */ +#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */ + + +/* Start of channnel array defines of LIN */ + +/* Channnel array defines of LIN */ +/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */ +#define LIN_COUNT 2 +#define LIN_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &LIN0, &LIN1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of LIN */ + + +#define LIN0RLN30LWBR LIN0.RLN3nLWBR +#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16 +#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L] +#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H] +#define LIN0RLN30LSTC LIN0.RLN3nLSTC +#define LIN0RLN30LMD LIN0.RLN3nLMD +#define LIN0RLN30LBFC LIN0.RLN3nLBFC +#define LIN0RLN30LSC LIN0.RLN3nLSC +#define LIN0RLN30LWUP LIN0.RLN3nLWUP +#define LIN0RLN30LIE LIN0.RLN3nLIE +#define LIN0RLN30LEDE LIN0.RLN3nLEDE +#define LIN0RLN30LCUC LIN0.RLN3nLCUC +#define LIN0RLN30LTRC LIN0.RLN3nLTRC +#define LIN0RLN30LMST LIN0.RLN3nLMST +#define LIN0RLN30LST LIN0.RLN3nLST +#define LIN0RLN30LEST LIN0.RLN3nLEST +#define LIN0RLN30LDFC LIN0.RLN3nLDFC +#define LIN0RLN30LIDB LIN0.RLN3nLIDB +#define LIN0RLN30LCBR LIN0.RLN3nLCBR +#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0 +#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1 +#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2 +#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3 +#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4 +#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5 +#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6 +#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7 +#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8 +#define LIN0RLN30LUOER LIN0.RLN3nLUOER +#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1 +#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16 +#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L] +#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H] +#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16 +#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L] +#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H] +#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16 +#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L] +#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H] +#define LIN1RLN31LWBR LIN1.RLN3nLWBR +#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16 +#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L] +#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H] +#define LIN1RLN31LSTC LIN1.RLN3nLSTC +#define LIN1RLN31LMD LIN1.RLN3nLMD +#define LIN1RLN31LBFC LIN1.RLN3nLBFC +#define LIN1RLN31LSC LIN1.RLN3nLSC +#define LIN1RLN31LWUP LIN1.RLN3nLWUP +#define LIN1RLN31LIE LIN1.RLN3nLIE +#define LIN1RLN31LEDE LIN1.RLN3nLEDE +#define LIN1RLN31LCUC LIN1.RLN3nLCUC +#define LIN1RLN31LTRC LIN1.RLN3nLTRC +#define LIN1RLN31LMST LIN1.RLN3nLMST +#define LIN1RLN31LST LIN1.RLN3nLST +#define LIN1RLN31LEST LIN1.RLN3nLEST +#define LIN1RLN31LDFC LIN1.RLN3nLDFC +#define LIN1RLN31LIDB LIN1.RLN3nLIDB +#define LIN1RLN31LCBR LIN1.RLN3nLCBR +#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0 +#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1 +#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2 +#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3 +#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4 +#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5 +#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6 +#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7 +#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8 +#define LIN1RLN31LUOER LIN1.RLN3nLUOER +#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1 +#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16 +#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L] +#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H] +#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16 +#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L] +#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H] +#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16 +#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L] +#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H] +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lvds_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lvds_iodefine.h new file mode 100644 index 0000000000..797c58a023 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/lvds_iodefine.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : lvds_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef LVDS_IODEFINE_H +#define LVDS_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_lvds +{ /* LVDS */ + volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */ + volatile uint32_t LVDSFCL; /* LVDSFCL */ + volatile uint8_t dummy608[24]; /* */ + volatile uint32_t LCLKSELR; /* LCLKSELR */ + volatile uint32_t LPLLSETR; /* LPLLSETR */ + volatile uint32_t LPLLMONR; /* LPLLMONR */ +}; + + +#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */ + + +#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE +#define LVDSLVDSFCL LVDS.LVDSFCL +#define LVDSLCLKSELR LVDS.LCLKSELR +#define LVDSLPLLSETR LVDS.LPLLSETR +#define LVDSLPLLMONR LVDS.LPLLMONR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mlb_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mlb_iodefine.h new file mode 100644 index 0000000000..ae97365872 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mlb_iodefine.h @@ -0,0 +1,498 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mlb_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef MLB_IODEFINE_H +#define MLB_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_mlb +{ /* MLB */ + volatile uint32_t DCCR; /* DCCR */ + volatile uint32_t SSCR; /* SSCR */ + volatile uint32_t SDCR; /* SDCR */ + volatile uint32_t SMCR; /* SMCR */ + volatile uint8_t dummy156[12]; /* */ + volatile uint32_t VCCR; /* VCCR */ + volatile uint32_t SBCR; /* SBCR */ + volatile uint32_t ABCR; /* ABCR */ + volatile uint32_t CBCR; /* CBCR */ + volatile uint32_t IBCR; /* IBCR */ + volatile uint32_t CICR; /* CICR */ + volatile uint8_t dummy157[12]; /* */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR0; /* CECR0 */ + volatile uint32_t CSCR0; /* CSCR0 */ + volatile uint32_t CCBCR0; /* CCBCR0 */ + volatile uint32_t CNBCR0; /* CNBCR0 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR1; /* CECR1 */ + volatile uint32_t CSCR1; /* CSCR1 */ + volatile uint32_t CCBCR1; /* CCBCR1 */ + volatile uint32_t CNBCR1; /* CNBCR1 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR2; /* CECR2 */ + volatile uint32_t CSCR2; /* CSCR2 */ + volatile uint32_t CCBCR2; /* CCBCR2 */ + volatile uint32_t CNBCR2; /* CNBCR2 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR3; /* CECR3 */ + volatile uint32_t CSCR3; /* CSCR3 */ + volatile uint32_t CCBCR3; /* CCBCR3 */ + volatile uint32_t CNBCR3; /* CNBCR3 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR4; /* CECR4 */ + volatile uint32_t CSCR4; /* CSCR4 */ + volatile uint32_t CCBCR4; /* CCBCR4 */ + volatile uint32_t CNBCR4; /* CNBCR4 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR5; /* CECR5 */ + volatile uint32_t CSCR5; /* CSCR5 */ + volatile uint32_t CCBCR5; /* CCBCR5 */ + volatile uint32_t CNBCR5; /* CNBCR5 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR6; /* CECR6 */ + volatile uint32_t CSCR6; /* CSCR6 */ + volatile uint32_t CCBCR6; /* CCBCR6 */ + volatile uint32_t CNBCR6; /* CNBCR6 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR7; /* CECR7 */ + volatile uint32_t CSCR7; /* CSCR7 */ + volatile uint32_t CCBCR7; /* CCBCR7 */ + volatile uint32_t CNBCR7; /* CNBCR7 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR8; /* CECR8 */ + volatile uint32_t CSCR8; /* CSCR8 */ + volatile uint32_t CCBCR8; /* CCBCR8 */ + volatile uint32_t CNBCR8; /* CNBCR8 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR9; /* CECR9 */ + volatile uint32_t CSCR9; /* CSCR9 */ + volatile uint32_t CCBCR9; /* CCBCR9 */ + volatile uint32_t CNBCR9; /* CNBCR9 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR10; /* CECR10 */ + volatile uint32_t CSCR10; /* CSCR10 */ + volatile uint32_t CCBCR10; /* CCBCR10 */ + volatile uint32_t CNBCR10; /* CNBCR10 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR11; /* CECR11 */ + volatile uint32_t CSCR11; /* CSCR11 */ + volatile uint32_t CCBCR11; /* CCBCR11 */ + volatile uint32_t CNBCR11; /* CNBCR11 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR12; /* CECR12 */ + volatile uint32_t CSCR12; /* CSCR12 */ + volatile uint32_t CCBCR12; /* CCBCR12 */ + volatile uint32_t CNBCR12; /* CNBCR12 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR13; /* CECR13 */ + volatile uint32_t CSCR13; /* CSCR13 */ + volatile uint32_t CCBCR13; /* CCBCR13 */ + volatile uint32_t CNBCR13; /* CNBCR13 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR14; /* CECR14 */ + volatile uint32_t CSCR14; /* CSCR14 */ + volatile uint32_t CCBCR14; /* CCBCR14 */ + volatile uint32_t CNBCR14; /* CNBCR14 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR15; /* CECR15 */ + volatile uint32_t CSCR15; /* CSCR15 */ + volatile uint32_t CCBCR15; /* CCBCR15 */ + volatile uint32_t CNBCR15; /* CNBCR15 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR16; /* CECR16 */ + volatile uint32_t CSCR16; /* CSCR16 */ + volatile uint32_t CCBCR16; /* CCBCR16 */ + volatile uint32_t CNBCR16; /* CNBCR16 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR17; /* CECR17 */ + volatile uint32_t CSCR17; /* CSCR17 */ + volatile uint32_t CCBCR17; /* CCBCR17 */ + volatile uint32_t CNBCR17; /* CNBCR17 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR18; /* CECR18 */ + volatile uint32_t CSCR18; /* CSCR18 */ + volatile uint32_t CCBCR18; /* CCBCR18 */ + volatile uint32_t CNBCR18; /* CNBCR18 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR19; /* CECR19 */ + volatile uint32_t CSCR19; /* CSCR19 */ + volatile uint32_t CCBCR19; /* CCBCR19 */ + volatile uint32_t CNBCR19; /* CNBCR19 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR20; /* CECR20 */ + volatile uint32_t CSCR20; /* CSCR20 */ + volatile uint32_t CCBCR20; /* CCBCR20 */ + volatile uint32_t CNBCR20; /* CNBCR20 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR21; /* CECR21 */ + volatile uint32_t CSCR21; /* CSCR21 */ + volatile uint32_t CCBCR21; /* CCBCR21 */ + volatile uint32_t CNBCR21; /* CNBCR21 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR22; /* CECR22 */ + volatile uint32_t CSCR22; /* CSCR22 */ + volatile uint32_t CCBCR22; /* CCBCR22 */ + volatile uint32_t CNBCR22; /* CNBCR22 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR23; /* CECR23 */ + volatile uint32_t CSCR23; /* CSCR23 */ + volatile uint32_t CCBCR23; /* CCBCR23 */ + volatile uint32_t CNBCR23; /* CNBCR23 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR24; /* CECR24 */ + volatile uint32_t CSCR24; /* CSCR24 */ + volatile uint32_t CCBCR24; /* CCBCR24 */ + volatile uint32_t CNBCR24; /* CNBCR24 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR25; /* CECR25 */ + volatile uint32_t CSCR25; /* CSCR25 */ + volatile uint32_t CCBCR25; /* CCBCR25 */ + volatile uint32_t CNBCR25; /* CNBCR25 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR26; /* CECR26 */ + volatile uint32_t CSCR26; /* CSCR26 */ + volatile uint32_t CCBCR26; /* CCBCR26 */ + volatile uint32_t CNBCR26; /* CNBCR26 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR27; /* CECR27 */ + volatile uint32_t CSCR27; /* CSCR27 */ + volatile uint32_t CCBCR27; /* CCBCR27 */ + volatile uint32_t CNBCR27; /* CNBCR27 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR28; /* CECR28 */ + volatile uint32_t CSCR28; /* CSCR28 */ + volatile uint32_t CCBCR28; /* CCBCR28 */ + volatile uint32_t CNBCR28; /* CNBCR28 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR29; /* CECR29 */ + volatile uint32_t CSCR29; /* CSCR29 */ + volatile uint32_t CCBCR29; /* CCBCR29 */ + volatile uint32_t CNBCR29; /* CNBCR29 */ +/* end of struct st_mlb_from_cecr0 */ +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR30; /* CECR30 */ + volatile uint32_t CSCR30; /* CSCR30 */ + volatile uint32_t CCBCR30; /* CCBCR30 */ + volatile uint32_t CNBCR30; /* CNBCR30 */ +/* end of struct st_mlb_from_cecr0 */ + volatile uint8_t dummy158[80]; /* */ +#define MLB_LCBCR0_COUNT 31 + volatile uint32_t LCBCR0; /* LCBCR0 */ + volatile uint32_t LCBCR1; /* LCBCR1 */ + volatile uint32_t LCBCR2; /* LCBCR2 */ + volatile uint32_t LCBCR3; /* LCBCR3 */ + volatile uint32_t LCBCR4; /* LCBCR4 */ + volatile uint32_t LCBCR5; /* LCBCR5 */ + volatile uint32_t LCBCR6; /* LCBCR6 */ + volatile uint32_t LCBCR7; /* LCBCR7 */ + volatile uint32_t LCBCR8; /* LCBCR8 */ + volatile uint32_t LCBCR9; /* LCBCR9 */ + volatile uint32_t LCBCR10; /* LCBCR10 */ + volatile uint32_t LCBCR11; /* LCBCR11 */ + volatile uint32_t LCBCR12; /* LCBCR12 */ + volatile uint32_t LCBCR13; /* LCBCR13 */ + volatile uint32_t LCBCR14; /* LCBCR14 */ + volatile uint32_t LCBCR15; /* LCBCR15 */ + volatile uint32_t LCBCR16; /* LCBCR16 */ + volatile uint32_t LCBCR17; /* LCBCR17 */ + volatile uint32_t LCBCR18; /* LCBCR18 */ + volatile uint32_t LCBCR19; /* LCBCR19 */ + volatile uint32_t LCBCR20; /* LCBCR20 */ + volatile uint32_t LCBCR21; /* LCBCR21 */ + volatile uint32_t LCBCR22; /* LCBCR22 */ + volatile uint32_t LCBCR23; /* LCBCR23 */ + volatile uint32_t LCBCR24; /* LCBCR24 */ + volatile uint32_t LCBCR25; /* LCBCR25 */ + volatile uint32_t LCBCR26; /* LCBCR26 */ + volatile uint32_t LCBCR27; /* LCBCR27 */ + volatile uint32_t LCBCR28; /* LCBCR28 */ + volatile uint32_t LCBCR29; /* LCBCR29 */ + volatile uint32_t LCBCR30; /* LCBCR30 */ +}; + + +struct st_mlb_from_cecr0 +{ + volatile uint32_t CECR0; /* CECR0 */ + volatile uint32_t CSCR0; /* CSCR0 */ + volatile uint32_t CCBCR0; /* CCBCR0 */ + volatile uint32_t CNBCR0; /* CNBCR0 */ +}; + + +#define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */ + + +/* Start of channnel array defines of MLB */ + +/* Channnel array defines of MLB_FROM_CECR0_ARRAY */ +/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */ +#define MLB_FROM_CECR0_ARRAY_COUNT 31 +#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \ + &MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \ + &MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \ + &MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */ +#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */ +#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */ +#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */ +#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */ +#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */ +#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */ +#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */ +#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */ +#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */ +#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */ +#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */ +#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */ +#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */ +#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */ +#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */ +#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */ +#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */ +#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */ +#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */ +#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */ +#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */ +#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */ +#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */ +#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */ +#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */ +#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */ +#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */ +#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */ +#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */ +#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */ + +/* End of channnel array defines of MLB */ + + +#define MLBDCCR MLB.DCCR +#define MLBSSCR MLB.SSCR +#define MLBSDCR MLB.SDCR +#define MLBSMCR MLB.SMCR +#define MLBVCCR MLB.VCCR +#define MLBSBCR MLB.SBCR +#define MLBABCR MLB.ABCR +#define MLBCBCR MLB.CBCR +#define MLBIBCR MLB.IBCR +#define MLBCICR MLB.CICR +#define MLBCECR0 MLB.CECR0 +#define MLBCSCR0 MLB.CSCR0 +#define MLBCCBCR0 MLB.CCBCR0 +#define MLBCNBCR0 MLB.CNBCR0 +#define MLBCECR1 MLB.CECR1 +#define MLBCSCR1 MLB.CSCR1 +#define MLBCCBCR1 MLB.CCBCR1 +#define MLBCNBCR1 MLB.CNBCR1 +#define MLBCECR2 MLB.CECR2 +#define MLBCSCR2 MLB.CSCR2 +#define MLBCCBCR2 MLB.CCBCR2 +#define MLBCNBCR2 MLB.CNBCR2 +#define MLBCECR3 MLB.CECR3 +#define MLBCSCR3 MLB.CSCR3 +#define MLBCCBCR3 MLB.CCBCR3 +#define MLBCNBCR3 MLB.CNBCR3 +#define MLBCECR4 MLB.CECR4 +#define MLBCSCR4 MLB.CSCR4 +#define MLBCCBCR4 MLB.CCBCR4 +#define MLBCNBCR4 MLB.CNBCR4 +#define MLBCECR5 MLB.CECR5 +#define MLBCSCR5 MLB.CSCR5 +#define MLBCCBCR5 MLB.CCBCR5 +#define MLBCNBCR5 MLB.CNBCR5 +#define MLBCECR6 MLB.CECR6 +#define MLBCSCR6 MLB.CSCR6 +#define MLBCCBCR6 MLB.CCBCR6 +#define MLBCNBCR6 MLB.CNBCR6 +#define MLBCECR7 MLB.CECR7 +#define MLBCSCR7 MLB.CSCR7 +#define MLBCCBCR7 MLB.CCBCR7 +#define MLBCNBCR7 MLB.CNBCR7 +#define MLBCECR8 MLB.CECR8 +#define MLBCSCR8 MLB.CSCR8 +#define MLBCCBCR8 MLB.CCBCR8 +#define MLBCNBCR8 MLB.CNBCR8 +#define MLBCECR9 MLB.CECR9 +#define MLBCSCR9 MLB.CSCR9 +#define MLBCCBCR9 MLB.CCBCR9 +#define MLBCNBCR9 MLB.CNBCR9 +#define MLBCECR10 MLB.CECR10 +#define MLBCSCR10 MLB.CSCR10 +#define MLBCCBCR10 MLB.CCBCR10 +#define MLBCNBCR10 MLB.CNBCR10 +#define MLBCECR11 MLB.CECR11 +#define MLBCSCR11 MLB.CSCR11 +#define MLBCCBCR11 MLB.CCBCR11 +#define MLBCNBCR11 MLB.CNBCR11 +#define MLBCECR12 MLB.CECR12 +#define MLBCSCR12 MLB.CSCR12 +#define MLBCCBCR12 MLB.CCBCR12 +#define MLBCNBCR12 MLB.CNBCR12 +#define MLBCECR13 MLB.CECR13 +#define MLBCSCR13 MLB.CSCR13 +#define MLBCCBCR13 MLB.CCBCR13 +#define MLBCNBCR13 MLB.CNBCR13 +#define MLBCECR14 MLB.CECR14 +#define MLBCSCR14 MLB.CSCR14 +#define MLBCCBCR14 MLB.CCBCR14 +#define MLBCNBCR14 MLB.CNBCR14 +#define MLBCECR15 MLB.CECR15 +#define MLBCSCR15 MLB.CSCR15 +#define MLBCCBCR15 MLB.CCBCR15 +#define MLBCNBCR15 MLB.CNBCR15 +#define MLBCECR16 MLB.CECR16 +#define MLBCSCR16 MLB.CSCR16 +#define MLBCCBCR16 MLB.CCBCR16 +#define MLBCNBCR16 MLB.CNBCR16 +#define MLBCECR17 MLB.CECR17 +#define MLBCSCR17 MLB.CSCR17 +#define MLBCCBCR17 MLB.CCBCR17 +#define MLBCNBCR17 MLB.CNBCR17 +#define MLBCECR18 MLB.CECR18 +#define MLBCSCR18 MLB.CSCR18 +#define MLBCCBCR18 MLB.CCBCR18 +#define MLBCNBCR18 MLB.CNBCR18 +#define MLBCECR19 MLB.CECR19 +#define MLBCSCR19 MLB.CSCR19 +#define MLBCCBCR19 MLB.CCBCR19 +#define MLBCNBCR19 MLB.CNBCR19 +#define MLBCECR20 MLB.CECR20 +#define MLBCSCR20 MLB.CSCR20 +#define MLBCCBCR20 MLB.CCBCR20 +#define MLBCNBCR20 MLB.CNBCR20 +#define MLBCECR21 MLB.CECR21 +#define MLBCSCR21 MLB.CSCR21 +#define MLBCCBCR21 MLB.CCBCR21 +#define MLBCNBCR21 MLB.CNBCR21 +#define MLBCECR22 MLB.CECR22 +#define MLBCSCR22 MLB.CSCR22 +#define MLBCCBCR22 MLB.CCBCR22 +#define MLBCNBCR22 MLB.CNBCR22 +#define MLBCECR23 MLB.CECR23 +#define MLBCSCR23 MLB.CSCR23 +#define MLBCCBCR23 MLB.CCBCR23 +#define MLBCNBCR23 MLB.CNBCR23 +#define MLBCECR24 MLB.CECR24 +#define MLBCSCR24 MLB.CSCR24 +#define MLBCCBCR24 MLB.CCBCR24 +#define MLBCNBCR24 MLB.CNBCR24 +#define MLBCECR25 MLB.CECR25 +#define MLBCSCR25 MLB.CSCR25 +#define MLBCCBCR25 MLB.CCBCR25 +#define MLBCNBCR25 MLB.CNBCR25 +#define MLBCECR26 MLB.CECR26 +#define MLBCSCR26 MLB.CSCR26 +#define MLBCCBCR26 MLB.CCBCR26 +#define MLBCNBCR26 MLB.CNBCR26 +#define MLBCECR27 MLB.CECR27 +#define MLBCSCR27 MLB.CSCR27 +#define MLBCCBCR27 MLB.CCBCR27 +#define MLBCNBCR27 MLB.CNBCR27 +#define MLBCECR28 MLB.CECR28 +#define MLBCSCR28 MLB.CSCR28 +#define MLBCCBCR28 MLB.CCBCR28 +#define MLBCNBCR28 MLB.CNBCR28 +#define MLBCECR29 MLB.CECR29 +#define MLBCSCR29 MLB.CSCR29 +#define MLBCCBCR29 MLB.CCBCR29 +#define MLBCNBCR29 MLB.CNBCR29 +#define MLBCECR30 MLB.CECR30 +#define MLBCSCR30 MLB.CSCR30 +#define MLBCCBCR30 MLB.CCBCR30 +#define MLBCNBCR30 MLB.CNBCR30 +#define MLBLCBCR0 MLB.LCBCR0 +#define MLBLCBCR1 MLB.LCBCR1 +#define MLBLCBCR2 MLB.LCBCR2 +#define MLBLCBCR3 MLB.LCBCR3 +#define MLBLCBCR4 MLB.LCBCR4 +#define MLBLCBCR5 MLB.LCBCR5 +#define MLBLCBCR6 MLB.LCBCR6 +#define MLBLCBCR7 MLB.LCBCR7 +#define MLBLCBCR8 MLB.LCBCR8 +#define MLBLCBCR9 MLB.LCBCR9 +#define MLBLCBCR10 MLB.LCBCR10 +#define MLBLCBCR11 MLB.LCBCR11 +#define MLBLCBCR12 MLB.LCBCR12 +#define MLBLCBCR13 MLB.LCBCR13 +#define MLBLCBCR14 MLB.LCBCR14 +#define MLBLCBCR15 MLB.LCBCR15 +#define MLBLCBCR16 MLB.LCBCR16 +#define MLBLCBCR17 MLB.LCBCR17 +#define MLBLCBCR18 MLB.LCBCR18 +#define MLBLCBCR19 MLB.LCBCR19 +#define MLBLCBCR20 MLB.LCBCR20 +#define MLBLCBCR21 MLB.LCBCR21 +#define MLBLCBCR22 MLB.LCBCR22 +#define MLBLCBCR23 MLB.LCBCR23 +#define MLBLCBCR24 MLB.LCBCR24 +#define MLBLCBCR25 MLB.LCBCR25 +#define MLBLCBCR26 MLB.LCBCR26 +#define MLBLCBCR27 MLB.LCBCR27 +#define MLBLCBCR28 MLB.LCBCR28 +#define MLBLCBCR29 MLB.LCBCR29 +#define MLBLCBCR30 MLB.LCBCR30 +/* <-SEC M1.10.1 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mmc_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mmc_iodefine.h new file mode 100644 index 0000000000..43a23670d0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mmc_iodefine.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mmc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef MMC_IODEFINE_H +#define MMC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_mmc +{ /* MMC */ + volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */ + volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */ + volatile uint8_t dummy182[4]; /* */ + volatile uint32_t CE_ARG; /* CE_ARG */ + volatile uint32_t CE_ARG_CMD12; /* CE_ARG_CMD12 */ + volatile uint32_t CE_CMD_CTRL; /* CE_CMD_CTRL */ + volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */ + volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */ + volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */ +#define MMC_CE_RESPn_COUNT 4 + volatile uint32_t CE_RESP3; /* CE_RESP3 */ + volatile uint32_t CE_RESP2; /* CE_RESP2 */ + volatile uint32_t CE_RESP1; /* CE_RESP1 */ + volatile uint32_t CE_RESP0; /* CE_RESP0 */ + volatile uint32_t CE_RESP_CMD12; /* CE_RESP_CMD12 */ + volatile uint32_t CE_DATA; /* CE_DATA */ + volatile uint8_t dummy183[8]; /* */ + volatile uint32_t CE_INT; /* CE_INT */ + volatile uint32_t CE_INT_EN; /* CE_INT_EN */ + volatile uint32_t CE_HOST_STS1; /* CE_HOST_STS1 */ + volatile uint32_t CE_HOST_STS2; /* CE_HOST_STS2 */ + volatile uint8_t dummy184[12]; /* */ + volatile uint32_t CE_DMA_MODE; /* CE_DMA_MODE */ + volatile uint8_t dummy185[16]; /* */ + volatile uint32_t CE_DETECT; /* CE_DETECT */ + volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */ + volatile uint8_t dummy186[4]; /* */ + volatile uint32_t CE_VERSION; /* CE_VERSION */ +}; + + +#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */ + + +#define MMCCE_CMD_SETH MMC.CE_CMD_SETH +#define MMCCE_CMD_SETL MMC.CE_CMD_SETL +#define MMCCE_ARG MMC.CE_ARG +#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12 +#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL +#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET +#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL +#define MMCCE_BUF_ACC MMC.CE_BUF_ACC +#define MMCCE_RESP3 MMC.CE_RESP3 +#define MMCCE_RESP2 MMC.CE_RESP2 +#define MMCCE_RESP1 MMC.CE_RESP1 +#define MMCCE_RESP0 MMC.CE_RESP0 +#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12 +#define MMCCE_DATA MMC.CE_DATA +#define MMCCE_INT MMC.CE_INT +#define MMCCE_INT_EN MMC.CE_INT_EN +#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1 +#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2 +#define MMCCE_DMA_MODE MMC.CE_DMA_MODE +#define MMCCE_DETECT MMC.CE_DETECT +#define MMCCE_ADD_MODE MMC.CE_ADD_MODE +#define MMCCE_VERSION MMC.CE_VERSION +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mtu2_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mtu2_iodefine.h new file mode 100644 index 0000000000..c2d0aeec84 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/mtu2_iodefine.h @@ -0,0 +1,217 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : mtu2_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef MTU2_IODEFINE_H +#define MTU2_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_mtu2 +{ /* MTU2 */ + volatile uint8_t TCR_2; /* TCR_2 */ + volatile uint8_t TMDR_2; /* TMDR_2 */ + volatile uint8_t TIOR_2; /* TIOR_2 */ + volatile uint8_t dummy520[1]; /* */ + volatile uint8_t TIER_2; /* TIER_2 */ + volatile uint8_t TSR_2; /* TSR_2 */ + volatile uint16_t TCNT_2; /* TCNT_2 */ + volatile uint16_t TGRA_2; /* TGRA_2 */ + volatile uint16_t TGRB_2; /* TGRB_2 */ + volatile uint8_t dummy521[500]; /* */ + volatile uint8_t TCR_3; /* TCR_3 */ + volatile uint8_t TCR_4; /* TCR_4 */ + volatile uint8_t TMDR_3; /* TMDR_3 */ + volatile uint8_t TMDR_4; /* TMDR_4 */ + volatile uint8_t TIORH_3; /* TIORH_3 */ + volatile uint8_t TIORL_3; /* TIORL_3 */ + volatile uint8_t TIORH_4; /* TIORH_4 */ + volatile uint8_t TIORL_4; /* TIORL_4 */ + volatile uint8_t TIER_3; /* TIER_3 */ + volatile uint8_t TIER_4; /* TIER_4 */ + volatile uint8_t TOER; /* TOER */ + volatile uint8_t dummy522[2]; /* */ + volatile uint8_t TGCR; /* TGCR */ + volatile uint8_t TOCR1; /* TOCR1 */ + volatile uint8_t TOCR2; /* TOCR2 */ + volatile uint16_t TCNT_3; /* TCNT_3 */ + volatile uint16_t TCNT_4; /* TCNT_4 */ + volatile uint16_t TCDR; /* TCDR */ + volatile uint16_t TDDR; /* TDDR */ + volatile uint16_t TGRA_3; /* TGRA_3 */ + volatile uint16_t TGRB_3; /* TGRB_3 */ + volatile uint16_t TGRA_4; /* TGRA_4 */ + volatile uint16_t TGRB_4; /* TGRB_4 */ + volatile uint16_t TCNTS; /* TCNTS */ + volatile uint16_t TCBR; /* TCBR */ + volatile uint16_t TGRC_3; /* TGRC_3 */ + volatile uint16_t TGRD_3; /* TGRD_3 */ + volatile uint16_t TGRC_4; /* TGRC_4 */ + volatile uint16_t TGRD_4; /* TGRD_4 */ + volatile uint8_t TSR_3; /* TSR_3 */ + volatile uint8_t TSR_4; /* TSR_4 */ + volatile uint8_t dummy523[2]; /* */ + volatile uint8_t TITCR; /* TITCR */ + volatile uint8_t TITCNT; /* TITCNT */ + volatile uint8_t TBTER; /* TBTER */ + volatile uint8_t dummy524[1]; /* */ + volatile uint8_t TDER; /* TDER */ + volatile uint8_t dummy525[1]; /* */ + volatile uint8_t TOLBR; /* TOLBR */ + volatile uint8_t dummy526[1]; /* */ + volatile uint8_t TBTM_3; /* TBTM_3 */ + volatile uint8_t TBTM_4; /* TBTM_4 */ + volatile uint8_t dummy527[6]; /* */ + volatile uint16_t TADCR; /* TADCR */ + volatile uint8_t dummy528[2]; /* */ + volatile uint16_t TADCORA_4; /* TADCORA_4 */ + volatile uint16_t TADCORB_4; /* TADCORB_4 */ + volatile uint16_t TADCOBRA_4; /* TADCOBRA_4 */ + volatile uint16_t TADCOBRB_4; /* TADCOBRB_4 */ + volatile uint8_t dummy529[20]; /* */ + volatile uint8_t TWCR; /* TWCR */ + volatile uint8_t dummy530[31]; /* */ + volatile uint8_t TSTR; /* TSTR */ + volatile uint8_t TSYR; /* TSYR */ + volatile uint8_t dummy531[2]; /* */ + volatile uint8_t TRWER; /* TRWER */ + volatile uint8_t dummy532[123]; /* */ + volatile uint8_t TCR_0; /* TCR_0 */ + volatile uint8_t TMDR_0; /* TMDR_0 */ + volatile uint8_t TIORH_0; /* TIORH_0 */ + volatile uint8_t TIORL_0; /* TIORL_0 */ + volatile uint8_t TIER_0; /* TIER_0 */ + volatile uint8_t TSR_0; /* TSR_0 */ + volatile uint16_t TCNT_0; /* TCNT_0 */ + volatile uint16_t TGRA_0; /* TGRA_0 */ + volatile uint16_t TGRB_0; /* TGRB_0 */ + volatile uint16_t TGRC_0; /* TGRC_0 */ + volatile uint16_t TGRD_0; /* TGRD_0 */ + volatile uint8_t dummy533[16]; /* */ + volatile uint16_t TGRE_0; /* TGRE_0 */ + volatile uint16_t TGRF_0; /* TGRF_0 */ + volatile uint8_t TIER2_0; /* TIER2_0 */ + volatile uint8_t TSR2_0; /* TSR2_0 */ + volatile uint8_t TBTM_0; /* TBTM_0 */ + volatile uint8_t dummy534[89]; /* */ + volatile uint8_t TCR_1; /* TCR_1 */ + volatile uint8_t TMDR_1; /* TMDR_1 */ + volatile uint8_t TIOR_1; /* TIOR_1 */ + volatile uint8_t dummy535[1]; /* */ + volatile uint8_t TIER_1; /* TIER_1 */ + volatile uint8_t TSR_1; /* TSR_1 */ + volatile uint16_t TCNT_1; /* TCNT_1 */ + volatile uint16_t TGRA_1; /* TGRA_1 */ + volatile uint16_t TGRB_1; /* TGRB_1 */ + volatile uint8_t dummy536[4]; /* */ + volatile uint8_t TICCR; /* TICCR */ +}; + + +#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */ + + +#define MTU2TCR_2 MTU2.TCR_2 +#define MTU2TMDR_2 MTU2.TMDR_2 +#define MTU2TIOR_2 MTU2.TIOR_2 +#define MTU2TIER_2 MTU2.TIER_2 +#define MTU2TSR_2 MTU2.TSR_2 +#define MTU2TCNT_2 MTU2.TCNT_2 +#define MTU2TGRA_2 MTU2.TGRA_2 +#define MTU2TGRB_2 MTU2.TGRB_2 +#define MTU2TCR_3 MTU2.TCR_3 +#define MTU2TCR_4 MTU2.TCR_4 +#define MTU2TMDR_3 MTU2.TMDR_3 +#define MTU2TMDR_4 MTU2.TMDR_4 +#define MTU2TIORH_3 MTU2.TIORH_3 +#define MTU2TIORL_3 MTU2.TIORL_3 +#define MTU2TIORH_4 MTU2.TIORH_4 +#define MTU2TIORL_4 MTU2.TIORL_4 +#define MTU2TIER_3 MTU2.TIER_3 +#define MTU2TIER_4 MTU2.TIER_4 +#define MTU2TOER MTU2.TOER +#define MTU2TGCR MTU2.TGCR +#define MTU2TOCR1 MTU2.TOCR1 +#define MTU2TOCR2 MTU2.TOCR2 +#define MTU2TCNT_3 MTU2.TCNT_3 +#define MTU2TCNT_4 MTU2.TCNT_4 +#define MTU2TCDR MTU2.TCDR +#define MTU2TDDR MTU2.TDDR +#define MTU2TGRA_3 MTU2.TGRA_3 +#define MTU2TGRB_3 MTU2.TGRB_3 +#define MTU2TGRA_4 MTU2.TGRA_4 +#define MTU2TGRB_4 MTU2.TGRB_4 +#define MTU2TCNTS MTU2.TCNTS +#define MTU2TCBR MTU2.TCBR +#define MTU2TGRC_3 MTU2.TGRC_3 +#define MTU2TGRD_3 MTU2.TGRD_3 +#define MTU2TGRC_4 MTU2.TGRC_4 +#define MTU2TGRD_4 MTU2.TGRD_4 +#define MTU2TSR_3 MTU2.TSR_3 +#define MTU2TSR_4 MTU2.TSR_4 +#define MTU2TITCR MTU2.TITCR +#define MTU2TITCNT MTU2.TITCNT +#define MTU2TBTER MTU2.TBTER +#define MTU2TDER MTU2.TDER +#define MTU2TOLBR MTU2.TOLBR +#define MTU2TBTM_3 MTU2.TBTM_3 +#define MTU2TBTM_4 MTU2.TBTM_4 +#define MTU2TADCR MTU2.TADCR +#define MTU2TADCORA_4 MTU2.TADCORA_4 +#define MTU2TADCORB_4 MTU2.TADCORB_4 +#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4 +#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4 +#define MTU2TWCR MTU2.TWCR +#define MTU2TSTR MTU2.TSTR +#define MTU2TSYR MTU2.TSYR +#define MTU2TRWER MTU2.TRWER +#define MTU2TCR_0 MTU2.TCR_0 +#define MTU2TMDR_0 MTU2.TMDR_0 +#define MTU2TIORH_0 MTU2.TIORH_0 +#define MTU2TIORL_0 MTU2.TIORL_0 +#define MTU2TIER_0 MTU2.TIER_0 +#define MTU2TSR_0 MTU2.TSR_0 +#define MTU2TCNT_0 MTU2.TCNT_0 +#define MTU2TGRA_0 MTU2.TGRA_0 +#define MTU2TGRB_0 MTU2.TGRB_0 +#define MTU2TGRC_0 MTU2.TGRC_0 +#define MTU2TGRD_0 MTU2.TGRD_0 +#define MTU2TGRE_0 MTU2.TGRE_0 +#define MTU2TGRF_0 MTU2.TGRF_0 +#define MTU2TIER2_0 MTU2.TIER2_0 +#define MTU2TSR2_0 MTU2.TSR2_0 +#define MTU2TBTM_0 MTU2.TBTM_0 +#define MTU2TCR_1 MTU2.TCR_1 +#define MTU2TMDR_1 MTU2.TMDR_1 +#define MTU2TIOR_1 MTU2.TIOR_1 +#define MTU2TIER_1 MTU2.TIER_1 +#define MTU2TSR_1 MTU2.TSR_1 +#define MTU2TCNT_1 MTU2.TCNT_1 +#define MTU2TGRA_1 MTU2.TGRA_1 +#define MTU2TGRB_1 MTU2.TGRB_1 +#define MTU2TICCR MTU2.TICCR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ostm_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ostm_iodefine.h new file mode 100644 index 0000000000..b0aa5587db --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ostm_iodefine.h @@ -0,0 +1,78 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ostm_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef OSTM_IODEFINE_H +#define OSTM_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_ostm +{ /* OSTM */ + volatile uint32_t OSTMnCMP; /* OSTMnCMP */ + volatile uint32_t OSTMnCNT; /* OSTMnCNT */ + volatile uint8_t dummy1[8]; /* */ + volatile uint8_t OSTMnTE; /* OSTMnTE */ + volatile uint8_t dummy2[3]; /* */ + volatile uint8_t OSTMnTS; /* OSTMnTS */ + volatile uint8_t dummy3[3]; /* */ + volatile uint8_t OSTMnTT; /* OSTMnTT */ + volatile uint8_t dummy4[7]; /* */ + volatile uint8_t OSTMnCTL; /* OSTMnCTL */ +}; + + +#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */ +#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */ + + +/* Start of channnel array defines of OSTM */ + +/* Channnel array defines of OSTM */ +/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */ +#define OSTM_COUNT 2 +#define OSTM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &OSTM0, &OSTM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of OSTM */ + + +#define OSTM0CMP OSTM0.OSTMnCMP +#define OSTM0CNT OSTM0.OSTMnCNT +#define OSTM0TE OSTM0.OSTMnTE +#define OSTM0TS OSTM0.OSTMnTS +#define OSTM0TT OSTM0.OSTMnTT +#define OSTM0CTL OSTM0.OSTMnCTL +#define OSTM1CMP OSTM1.OSTMnCMP +#define OSTM1CNT OSTM1.OSTMnCNT +#define OSTM1TE OSTM1.OSTMnTE +#define OSTM1TS OSTM1.OSTMnTS +#define OSTM1TT OSTM1.OSTMnTT +#define OSTM1CTL OSTM1.OSTMnCTL +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pfv_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pfv_iodefine.h new file mode 100644 index 0000000000..230dd62947 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pfv_iodefine.h @@ -0,0 +1,150 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : pfv_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef PFV_IODEFINE_H +#define PFV_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_pfv +{ /* PFV */ + volatile uint32_t PFVCR; /* PFVCR */ + volatile uint32_t PFVICR; /* PFVICR */ + volatile uint32_t PFVISR; /* PFVISR */ + volatile uint8_t dummy1[20]; /* */ +#define PFVID_COUNT 8 + volatile uint32_t PFVID0; /* PFVID0 */ + volatile uint32_t PFVID1; /* PFVID1 */ + volatile uint32_t PFVID2; /* PFVID2 */ + volatile uint32_t PFVID3; /* PFVID3 */ + volatile uint32_t PFVID4; /* PFVID4 */ + volatile uint32_t PFVID5; /* PFVID5 */ + volatile uint32_t PFVID6; /* PFVID6 */ + volatile uint32_t PFVID7; /* PFVID7 */ +#define PFVOD_COUNT 8 + volatile uint32_t PFVOD0; /* PFVOD0 */ + volatile uint32_t PFVOD1; /* PFVOD1 */ + volatile uint32_t PFVOD2; /* PFVOD2 */ + volatile uint32_t PFVOD3; /* PFVOD3 */ + volatile uint32_t PFVOD4; /* PFVOD4 */ + volatile uint32_t PFVOD5; /* PFVOD5 */ + volatile uint32_t PFVOD6; /* PFVOD6 */ + volatile uint32_t PFVOD7; /* PFVOD7 */ + volatile uint8_t dummy2[4]; /* */ + volatile uint32_t PFVIFSR; /* PFVIFSR */ + volatile uint32_t PFVOFSR; /* PFVOFSR */ + volatile uint32_t PFVACR; /* PFVACR */ + volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */ + volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */ + volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */ + volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */ + volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */ + volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */ + volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */ + volatile uint32_t PFVSZR; /* PFVSZR */ +}; + + +#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ +#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ + + +/* Start of channnel array defines of PFV */ + +/* Channnel array defines of PFV */ +/*(Sample) value = PFV[ channel ]->PFVCR; */ +#define PFV_COUNT 2 +#define PFV_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &PFV0, &PFV1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of PFV */ + + +#define PFV0PFVCR PFV0.PFVCR +#define PFV0PFVICR PFV0.PFVICR +#define PFV0PFVISR PFV0.PFVISR +#define PFV0PFVID0 PFV0.PFVID0 +#define PFV0PFVID1 PFV0.PFVID1 +#define PFV0PFVID2 PFV0.PFVID2 +#define PFV0PFVID3 PFV0.PFVID3 +#define PFV0PFVID4 PFV0.PFVID4 +#define PFV0PFVID5 PFV0.PFVID5 +#define PFV0PFVID6 PFV0.PFVID6 +#define PFV0PFVID7 PFV0.PFVID7 +#define PFV0PFVOD0 PFV0.PFVOD0 +#define PFV0PFVOD1 PFV0.PFVOD1 +#define PFV0PFVOD2 PFV0.PFVOD2 +#define PFV0PFVOD3 PFV0.PFVOD3 +#define PFV0PFVOD4 PFV0.PFVOD4 +#define PFV0PFVOD5 PFV0.PFVOD5 +#define PFV0PFVOD6 PFV0.PFVOD6 +#define PFV0PFVOD7 PFV0.PFVOD7 +#define PFV0PFVIFSR PFV0.PFVIFSR +#define PFV0PFVOFSR PFV0.PFVOFSR +#define PFV0PFVACR PFV0.PFVACR +#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE +#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0 +#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1 +#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0 +#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1 +#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0 +#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1 +#define PFV0PFVSZR PFV0.PFVSZR +#define PFV1PFVCR PFV1.PFVCR +#define PFV1PFVICR PFV1.PFVICR +#define PFV1PFVISR PFV1.PFVISR +#define PFV1PFVID0 PFV1.PFVID0 +#define PFV1PFVID1 PFV1.PFVID1 +#define PFV1PFVID2 PFV1.PFVID2 +#define PFV1PFVID3 PFV1.PFVID3 +#define PFV1PFVID4 PFV1.PFVID4 +#define PFV1PFVID5 PFV1.PFVID5 +#define PFV1PFVID6 PFV1.PFVID6 +#define PFV1PFVID7 PFV1.PFVID7 +#define PFV1PFVOD0 PFV1.PFVOD0 +#define PFV1PFVOD1 PFV1.PFVOD1 +#define PFV1PFVOD2 PFV1.PFVOD2 +#define PFV1PFVOD3 PFV1.PFVOD3 +#define PFV1PFVOD4 PFV1.PFVOD4 +#define PFV1PFVOD5 PFV1.PFVOD5 +#define PFV1PFVOD6 PFV1.PFVOD6 +#define PFV1PFVOD7 PFV1.PFVOD7 +#define PFV1PFVIFSR PFV1.PFVIFSR +#define PFV1PFVOFSR PFV1.PFVOFSR +#define PFV1PFVACR PFV1.PFVACR +#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE +#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0 +#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1 +#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0 +#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1 +#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0 +#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1 +#define PFV1PFVSZR PFV1.PFVSZR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pwm_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pwm_iodefine.h new file mode 100644 index 0000000000..a7143d481d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/pwm_iodefine.h @@ -0,0 +1,135 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : pwm_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef PWM_IODEFINE_H +#define PWM_IODEFINE_H +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +union reg16_8_t +{ + volatile uint16_t UINT16; /* 16-bit Access */ + volatile uint8_t UINT8[2]; /* 8-bit Access */ +}; + +struct st_pwm +{ /* PWM */ + volatile uint8_t dummy559[2]; /* */ + union reg16_8_t PWBTCR; /* PWBTCR */ + + volatile uint8_t dummy560[216]; /* */ + +/* start of struct st_pwm_common */ + union reg16_8_t PWCR_1; /* PWCR_1 */ + + volatile uint8_t dummy561[2]; /* */ + union reg16_8_t PWPR_1; /* PWPR_1 */ + + volatile uint16_t PWCYR_1; /* PWCYR_1 */ + volatile uint16_t PWBFR_1A; /* PWBFR_1A */ + volatile uint16_t PWBFR_1C; /* PWBFR_1C */ + volatile uint16_t PWBFR_1E; /* PWBFR_1E */ + volatile uint16_t PWBFR_1G; /* PWBFR_1G */ +/* end of struct st_pwm_common */ + +/* start of struct st_pwm_common */ + union reg16_8_t PWCR_2; /* PWCR_2 */ + + volatile uint8_t dummy562[2]; /* */ + union reg16_8_t PWPR_2; /* PWPR_2 */ + + volatile uint16_t PWCYR_2; /* PWCYR_2 */ + volatile uint16_t PWBFR_2A; /* PWBFR_2A */ + volatile uint16_t PWBFR_2C; /* PWBFR_2C */ + volatile uint16_t PWBFR_2E; /* PWBFR_2E */ + volatile uint16_t PWBFR_2G; /* PWBFR_2G */ +/* end of struct st_pwm_common */ +}; + + +struct st_pwm_common +{ + union reg16_8_t PWCR_1; /* PWCR_1 */ + + volatile uint8_t dummy572[2]; /* */ + union reg16_8_t PWPR_1; /* PWPR_1 */ + + volatile uint16_t PWCYR_1; /* PWCYR_1 */ + volatile uint16_t PWBFR_1A; /* PWBFR_1A */ + volatile uint16_t PWBFR_1C; /* PWBFR_1C */ + volatile uint16_t PWBFR_1E; /* PWBFR_1E */ + volatile uint16_t PWBFR_1G; /* PWBFR_1G */ +}; + + +#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */ + + +/* Start of channnel array defines of PWM */ + +/* Channnel array defines of PWMn */ +/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */ +#define PWMn_COUNT 2 +#define PWMn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &PWM1, &PWM2 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */ +#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */ + +/* End of channnel array defines of PWM */ + + +#define PWMPWBTCR PWM.PWBTCR.UINT16 +#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0] +#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1] +#define PWMPWCR_1 PWM.PWCR_1.UINT16 +#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0] +#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1] +#define PWMPWPR_1 PWM.PWPR_1.UINT16 +#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0] +#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1] +#define PWMPWCYR_1 PWM.PWCYR_1 +#define PWMPWBFR_1A PWM.PWBFR_1A +#define PWMPWBFR_1C PWM.PWBFR_1C +#define PWMPWBFR_1E PWM.PWBFR_1E +#define PWMPWBFR_1G PWM.PWBFR_1G +#define PWMPWCR_2 PWM.PWCR_2.UINT16 +#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0] +#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1] +#define PWMPWPR_2 PWM.PWPR_2.UINT16 +#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0] +#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1] +#define PWMPWCYR_2 PWM.PWCYR_2 +#define PWMPWBFR_2A PWM.PWBFR_2A +#define PWMPWBFR_2C PWM.PWBFR_2C +#define PWMPWBFR_2E PWM.PWBFR_2E +#define PWMPWBFR_2G PWM.PWBFR_2G +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/riic_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/riic_iodefine.h new file mode 100644 index 0000000000..9daefe447a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/riic_iodefine.h @@ -0,0 +1,556 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : riic_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef RIIC_IODEFINE_H +#define RIIC_IODEFINE_H + +#include "reg32_t.h" + +struct st_riic +{ /* RIIC */ +#define RIICnCRm_COUNT 2 + union reg32_t RIICnCR1; /* RIICnCR1 */ + union reg32_t RIICnCR2; /* RIICnCR2 */ +#define RIICnMRm_COUNT 3 + union reg32_t RIICnMR1; /* RIICnMR1 */ + union reg32_t RIICnMR2; /* RIICnMR2 */ + union reg32_t RIICnMR3; /* RIICnMR3 */ + union reg32_t RIICnFER; /* RIICnFER */ + union reg32_t RIICnSER; /* RIICnSER */ + union reg32_t RIICnIER; /* RIICnIER */ +#define RIICnSRm_COUNT 2 + union reg32_t RIICnSR1; /* RIICnSR1 */ + union reg32_t RIICnSR2; /* RIICnSR2 */ +#define RIICnSARm_COUNT 3 + union reg32_t RIICnSAR0; /* RIICnSAR0 */ + union reg32_t RIICnSAR1; /* RIICnSAR1 */ + union reg32_t RIICnSAR2; /* RIICnSAR2 */ + union reg32_t RIICnBRL; /* RIICnBRL */ + union reg32_t RIICnBRH; /* RIICnBRH */ + union reg32_t RIICnDRT; /* RIICnDRT */ + union reg32_t RIICnDRR; /* RIICnDRR */ + +}; + + +#define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */ +#define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */ +#define RIIC2 (*(struct st_riic *)0xFCFEE800uL) /* RIIC2 */ +#define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */ + + +/* Start of channnel array defines of RIIC */ + +/* Channnel array defines of RIIC */ +/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */ +#define RIIC_COUNT 4 +#define RIIC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RIIC0, &RIIC1, &RIIC2, &RIIC3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of RIIC */ + + +#define RIIC0CR1 RIIC0.RIICnCR1.UINT32 +#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L] +#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL] +#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH] +#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H] +#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL] +#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH] +#define RIIC0CR2 RIIC0.RIICnCR2.UINT32 +#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L] +#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL] +#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH] +#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H] +#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL] +#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH] +#define RIIC0MR1 RIIC0.RIICnMR1.UINT32 +#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L] +#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL] +#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH] +#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H] +#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL] +#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH] +#define RIIC0MR2 RIIC0.RIICnMR2.UINT32 +#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L] +#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL] +#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH] +#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H] +#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL] +#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH] +#define RIIC0MR3 RIIC0.RIICnMR3.UINT32 +#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L] +#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL] +#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH] +#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H] +#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL] +#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH] +#define RIIC0FER RIIC0.RIICnFER.UINT32 +#define RIIC0FERL RIIC0.RIICnFER.UINT16[L] +#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL] +#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH] +#define RIIC0FERH RIIC0.RIICnFER.UINT16[H] +#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL] +#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH] +#define RIIC0SER RIIC0.RIICnSER.UINT32 +#define RIIC0SERL RIIC0.RIICnSER.UINT16[L] +#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL] +#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH] +#define RIIC0SERH RIIC0.RIICnSER.UINT16[H] +#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL] +#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH] +#define RIIC0IER RIIC0.RIICnIER.UINT32 +#define RIIC0IERL RIIC0.RIICnIER.UINT16[L] +#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL] +#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH] +#define RIIC0IERH RIIC0.RIICnIER.UINT16[H] +#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL] +#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH] +#define RIIC0SR1 RIIC0.RIICnSR1.UINT32 +#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L] +#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL] +#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH] +#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H] +#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL] +#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH] +#define RIIC0SR2 RIIC0.RIICnSR2.UINT32 +#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L] +#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL] +#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH] +#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H] +#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL] +#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH] +#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32 +#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L] +#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL] +#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH] +#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H] +#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL] +#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH] +#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32 +#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L] +#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL] +#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH] +#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H] +#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL] +#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH] +#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32 +#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L] +#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL] +#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH] +#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H] +#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL] +#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH] +#define RIIC0BRL RIIC0.RIICnBRL.UINT32 +#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L] +#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL] +#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH] +#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H] +#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL] +#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH] +#define RIIC0BRH RIIC0.RIICnBRH.UINT32 +#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L] +#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL] +#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH] +#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H] +#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL] +#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH] +#define RIIC0DRT RIIC0.RIICnDRT.UINT32 +#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L] +#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL] +#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH] +#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H] +#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL] +#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH] +#define RIIC0DRR RIIC0.RIICnDRR.UINT32 +#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L] +#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL] +#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH] +#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H] +#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL] +#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH] +#define RIIC1CR1 RIIC1.RIICnCR1.UINT32 +#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L] +#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL] +#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH] +#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H] +#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL] +#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH] +#define RIIC1CR2 RIIC1.RIICnCR2.UINT32 +#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L] +#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL] +#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH] +#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H] +#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL] +#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH] +#define RIIC1MR1 RIIC1.RIICnMR1.UINT32 +#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L] +#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL] +#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH] +#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H] +#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL] +#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH] +#define RIIC1MR2 RIIC1.RIICnMR2.UINT32 +#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L] +#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL] +#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH] +#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H] +#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL] +#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH] +#define RIIC1MR3 RIIC1.RIICnMR3.UINT32 +#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L] +#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL] +#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH] +#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H] +#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL] +#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH] +#define RIIC1FER RIIC1.RIICnFER.UINT32 +#define RIIC1FERL RIIC1.RIICnFER.UINT16[L] +#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL] +#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH] +#define RIIC1FERH RIIC1.RIICnFER.UINT16[H] +#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL] +#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH] +#define RIIC1SER RIIC1.RIICnSER.UINT32 +#define RIIC1SERL RIIC1.RIICnSER.UINT16[L] +#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL] +#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH] +#define RIIC1SERH RIIC1.RIICnSER.UINT16[H] +#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL] +#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH] +#define RIIC1IER RIIC1.RIICnIER.UINT32 +#define RIIC1IERL RIIC1.RIICnIER.UINT16[L] +#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL] +#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH] +#define RIIC1IERH RIIC1.RIICnIER.UINT16[H] +#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL] +#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH] +#define RIIC1SR1 RIIC1.RIICnSR1.UINT32 +#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L] +#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL] +#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH] +#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H] +#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL] +#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH] +#define RIIC1SR2 RIIC1.RIICnSR2.UINT32 +#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L] +#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL] +#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH] +#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H] +#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL] +#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH] +#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32 +#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L] +#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL] +#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH] +#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H] +#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL] +#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH] +#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32 +#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L] +#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL] +#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH] +#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H] +#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL] +#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH] +#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32 +#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L] +#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL] +#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH] +#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H] +#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL] +#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH] +#define RIIC1BRL RIIC1.RIICnBRL.UINT32 +#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L] +#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL] +#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH] +#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H] +#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL] +#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH] +#define RIIC1BRH RIIC1.RIICnBRH.UINT32 +#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L] +#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL] +#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH] +#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H] +#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL] +#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH] +#define RIIC1DRT RIIC1.RIICnDRT.UINT32 +#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L] +#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL] +#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH] +#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H] +#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL] +#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH] +#define RIIC1DRR RIIC1.RIICnDRR.UINT32 +#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L] +#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL] +#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH] +#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H] +#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL] +#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH] +#define RIIC2CR1 RIIC2.RIICnCR1.UINT32 +#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L] +#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL] +#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH] +#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H] +#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL] +#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH] +#define RIIC2CR2 RIIC2.RIICnCR2.UINT32 +#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L] +#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL] +#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH] +#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H] +#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL] +#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH] +#define RIIC2MR1 RIIC2.RIICnMR1.UINT32 +#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L] +#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL] +#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH] +#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H] +#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL] +#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH] +#define RIIC2MR2 RIIC2.RIICnMR2.UINT32 +#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L] +#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL] +#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH] +#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H] +#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL] +#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH] +#define RIIC2MR3 RIIC2.RIICnMR3.UINT32 +#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L] +#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL] +#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH] +#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H] +#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL] +#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH] +#define RIIC2FER RIIC2.RIICnFER.UINT32 +#define RIIC2FERL RIIC2.RIICnFER.UINT16[L] +#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL] +#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH] +#define RIIC2FERH RIIC2.RIICnFER.UINT16[H] +#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL] +#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH] +#define RIIC2SER RIIC2.RIICnSER.UINT32 +#define RIIC2SERL RIIC2.RIICnSER.UINT16[L] +#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL] +#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH] +#define RIIC2SERH RIIC2.RIICnSER.UINT16[H] +#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL] +#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH] +#define RIIC2IER RIIC2.RIICnIER.UINT32 +#define RIIC2IERL RIIC2.RIICnIER.UINT16[L] +#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL] +#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH] +#define RIIC2IERH RIIC2.RIICnIER.UINT16[H] +#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL] +#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH] +#define RIIC2SR1 RIIC2.RIICnSR1.UINT32 +#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L] +#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL] +#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH] +#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H] +#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL] +#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH] +#define RIIC2SR2 RIIC2.RIICnSR2.UINT32 +#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L] +#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL] +#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH] +#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H] +#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL] +#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH] +#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32 +#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L] +#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL] +#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH] +#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H] +#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL] +#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH] +#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32 +#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L] +#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL] +#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH] +#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H] +#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL] +#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH] +#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32 +#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L] +#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL] +#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH] +#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H] +#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL] +#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH] +#define RIIC2BRL RIIC2.RIICnBRL.UINT32 +#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L] +#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL] +#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH] +#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H] +#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL] +#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH] +#define RIIC2BRH RIIC2.RIICnBRH.UINT32 +#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L] +#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL] +#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH] +#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H] +#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL] +#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH] +#define RIIC2DRT RIIC2.RIICnDRT.UINT32 +#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L] +#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL] +#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH] +#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H] +#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL] +#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH] +#define RIIC2DRR RIIC2.RIICnDRR.UINT32 +#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L] +#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL] +#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH] +#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H] +#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL] +#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH] +#define RIIC3CR1 RIIC3.RIICnCR1.UINT32 +#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L] +#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL] +#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH] +#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H] +#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL] +#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH] +#define RIIC3CR2 RIIC3.RIICnCR2.UINT32 +#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L] +#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL] +#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH] +#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H] +#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL] +#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH] +#define RIIC3MR1 RIIC3.RIICnMR1.UINT32 +#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L] +#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL] +#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH] +#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H] +#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL] +#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH] +#define RIIC3MR2 RIIC3.RIICnMR2.UINT32 +#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L] +#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL] +#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH] +#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H] +#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL] +#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH] +#define RIIC3MR3 RIIC3.RIICnMR3.UINT32 +#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L] +#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL] +#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH] +#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H] +#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL] +#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH] +#define RIIC3FER RIIC3.RIICnFER.UINT32 +#define RIIC3FERL RIIC3.RIICnFER.UINT16[L] +#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL] +#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH] +#define RIIC3FERH RIIC3.RIICnFER.UINT16[H] +#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL] +#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH] +#define RIIC3SER RIIC3.RIICnSER.UINT32 +#define RIIC3SERL RIIC3.RIICnSER.UINT16[L] +#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL] +#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH] +#define RIIC3SERH RIIC3.RIICnSER.UINT16[H] +#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL] +#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH] +#define RIIC3IER RIIC3.RIICnIER.UINT32 +#define RIIC3IERL RIIC3.RIICnIER.UINT16[L] +#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL] +#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH] +#define RIIC3IERH RIIC3.RIICnIER.UINT16[H] +#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL] +#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH] +#define RIIC3SR1 RIIC3.RIICnSR1.UINT32 +#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L] +#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL] +#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH] +#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H] +#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL] +#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH] +#define RIIC3SR2 RIIC3.RIICnSR2.UINT32 +#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L] +#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL] +#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH] +#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H] +#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL] +#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH] +#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32 +#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L] +#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL] +#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH] +#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H] +#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL] +#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH] +#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32 +#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L] +#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL] +#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH] +#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H] +#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL] +#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH] +#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32 +#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L] +#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL] +#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH] +#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H] +#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL] +#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH] +#define RIIC3BRL RIIC3.RIICnBRL.UINT32 +#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L] +#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL] +#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH] +#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H] +#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL] +#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH] +#define RIIC3BRH RIIC3.RIICnBRH.UINT32 +#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L] +#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL] +#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH] +#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H] +#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL] +#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH] +#define RIIC3DRT RIIC3.RIICnDRT.UINT32 +#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L] +#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL] +#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH] +#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H] +#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL] +#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH] +#define RIIC3DRR RIIC3.RIICnDRR.UINT32 +#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L] +#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL] +#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH] +#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H] +#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL] +#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH] +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/romdec_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/romdec_iodefine.h new file mode 100644 index 0000000000..cfcfda568d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/romdec_iodefine.h @@ -0,0 +1,166 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : romdec_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef ROMDEC_IODEFINE_H +#define ROMDEC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_romdec +{ /* ROMDEC */ + volatile uint8_t CROMEN; /* CROMEN */ + volatile uint8_t CROMSY0; /* CROMSY0 */ +#define ROMDEC_CROMCTL0_COUNT 2 + volatile uint8_t CROMCTL0; /* CROMCTL0 */ + volatile uint8_t CROMCTL1; /* CROMCTL1 */ + volatile uint8_t dummy23[1]; /* */ + volatile uint8_t CROMCTL3; /* CROMCTL3 */ + volatile uint8_t CROMCTL4; /* CROMCTL4 */ + volatile uint8_t CROMCTL5; /* CROMCTL5 */ +#define ROMDEC_CROMST0_COUNT 2 + volatile uint8_t CROMST0; /* CROMST0 */ + volatile uint8_t CROMST1; /* CROMST1 */ + volatile uint8_t dummy24[1]; /* */ + volatile uint8_t CROMST3; /* CROMST3 */ + volatile uint8_t CROMST4; /* CROMST4 */ + volatile uint8_t CROMST5; /* CROMST5 */ + volatile uint8_t CROMST6; /* CROMST6 */ + volatile uint8_t dummy25[5]; /* */ +#define ROMDEC_CBUFST0_COUNT 3 + volatile uint8_t CBUFST0; /* CBUFST0 */ + volatile uint8_t CBUFST1; /* CBUFST1 */ + volatile uint8_t CBUFST2; /* CBUFST2 */ + volatile uint8_t dummy26[1]; /* */ +#define ROMDEC_HEAD00_COUNT 4 + volatile uint8_t HEAD00; /* HEAD00 */ + volatile uint8_t HEAD01; /* HEAD01 */ + volatile uint8_t HEAD02; /* HEAD02 */ + volatile uint8_t HEAD03; /* HEAD03 */ +#define ROMDEC_SHEAD00_COUNT 8 + volatile uint8_t SHEAD00; /* SHEAD00 */ + volatile uint8_t SHEAD01; /* SHEAD01 */ + volatile uint8_t SHEAD02; /* SHEAD02 */ + volatile uint8_t SHEAD03; /* SHEAD03 */ + volatile uint8_t SHEAD04; /* SHEAD04 */ + volatile uint8_t SHEAD05; /* SHEAD05 */ + volatile uint8_t SHEAD06; /* SHEAD06 */ + volatile uint8_t SHEAD07; /* SHEAD07 */ +#define ROMDEC_HEAD20_COUNT 4 + volatile uint8_t HEAD20; /* HEAD20 */ + volatile uint8_t HEAD21; /* HEAD21 */ + volatile uint8_t HEAD22; /* HEAD22 */ + volatile uint8_t HEAD23; /* HEAD23 */ +#define ROMDEC_SHEAD20_COUNT 8 + volatile uint8_t SHEAD20; /* SHEAD20 */ + volatile uint8_t SHEAD21; /* SHEAD21 */ + volatile uint8_t SHEAD22; /* SHEAD22 */ + volatile uint8_t SHEAD23; /* SHEAD23 */ + volatile uint8_t SHEAD24; /* SHEAD24 */ + volatile uint8_t SHEAD25; /* SHEAD25 */ + volatile uint8_t SHEAD26; /* SHEAD26 */ + volatile uint8_t SHEAD27; /* SHEAD27 */ + volatile uint8_t dummy27[16]; /* */ +#define ROMDEC_CBUFCTL0_COUNT 4 + volatile uint8_t CBUFCTL0; /* CBUFCTL0 */ + volatile uint8_t CBUFCTL1; /* CBUFCTL1 */ + volatile uint8_t CBUFCTL2; /* CBUFCTL2 */ + volatile uint8_t CBUFCTL3; /* CBUFCTL3 */ + volatile uint8_t dummy28[1]; /* */ + volatile uint8_t CROMST0M; /* CROMST0M */ + volatile uint8_t dummy29[186]; /* */ + volatile uint8_t ROMDECRST; /* ROMDECRST */ + volatile uint8_t RSTSTAT; /* RSTSTAT */ + volatile uint8_t SSI; /* SSI */ + volatile uint8_t dummy30[5]; /* */ + volatile uint8_t INTHOLD; /* INTHOLD */ + volatile uint8_t INHINT; /* INHINT */ + volatile uint8_t dummy31[246]; /* */ +#define ROMDEC_STRMDIN0_COUNT 2 + volatile uint16_t STRMDIN0; /* STRMDIN0 */ + volatile uint16_t STRMDIN2; /* STRMDIN2 */ + volatile uint16_t STRMDOUT0; /* STRMDOUT0 */ +}; + + +#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */ + + +#define ROMDECCROMEN ROMDEC.CROMEN +#define ROMDECCROMSY0 ROMDEC.CROMSY0 +#define ROMDECCROMCTL0 ROMDEC.CROMCTL0 +#define ROMDECCROMCTL1 ROMDEC.CROMCTL1 +#define ROMDECCROMCTL3 ROMDEC.CROMCTL3 +#define ROMDECCROMCTL4 ROMDEC.CROMCTL4 +#define ROMDECCROMCTL5 ROMDEC.CROMCTL5 +#define ROMDECCROMST0 ROMDEC.CROMST0 +#define ROMDECCROMST1 ROMDEC.CROMST1 +#define ROMDECCROMST3 ROMDEC.CROMST3 +#define ROMDECCROMST4 ROMDEC.CROMST4 +#define ROMDECCROMST5 ROMDEC.CROMST5 +#define ROMDECCROMST6 ROMDEC.CROMST6 +#define ROMDECCBUFST0 ROMDEC.CBUFST0 +#define ROMDECCBUFST1 ROMDEC.CBUFST1 +#define ROMDECCBUFST2 ROMDEC.CBUFST2 +#define ROMDECHEAD00 ROMDEC.HEAD00 +#define ROMDECHEAD01 ROMDEC.HEAD01 +#define ROMDECHEAD02 ROMDEC.HEAD02 +#define ROMDECHEAD03 ROMDEC.HEAD03 +#define ROMDECSHEAD00 ROMDEC.SHEAD00 +#define ROMDECSHEAD01 ROMDEC.SHEAD01 +#define ROMDECSHEAD02 ROMDEC.SHEAD02 +#define ROMDECSHEAD03 ROMDEC.SHEAD03 +#define ROMDECSHEAD04 ROMDEC.SHEAD04 +#define ROMDECSHEAD05 ROMDEC.SHEAD05 +#define ROMDECSHEAD06 ROMDEC.SHEAD06 +#define ROMDECSHEAD07 ROMDEC.SHEAD07 +#define ROMDECHEAD20 ROMDEC.HEAD20 +#define ROMDECHEAD21 ROMDEC.HEAD21 +#define ROMDECHEAD22 ROMDEC.HEAD22 +#define ROMDECHEAD23 ROMDEC.HEAD23 +#define ROMDECSHEAD20 ROMDEC.SHEAD20 +#define ROMDECSHEAD21 ROMDEC.SHEAD21 +#define ROMDECSHEAD22 ROMDEC.SHEAD22 +#define ROMDECSHEAD23 ROMDEC.SHEAD23 +#define ROMDECSHEAD24 ROMDEC.SHEAD24 +#define ROMDECSHEAD25 ROMDEC.SHEAD25 +#define ROMDECSHEAD26 ROMDEC.SHEAD26 +#define ROMDECSHEAD27 ROMDEC.SHEAD27 +#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0 +#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1 +#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2 +#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3 +#define ROMDECCROMST0M ROMDEC.CROMST0M +#define ROMDECROMDECRST ROMDEC.ROMDECRST +#define ROMDECRSTSTAT ROMDEC.RSTSTAT +#define ROMDECSSI ROMDEC.SSI +#define ROMDECINTHOLD ROMDEC.INTHOLD +#define ROMDECINHINT ROMDEC.INHINT +#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0 +#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2 +#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0 +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rscan0_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rscan0_iodefine.h new file mode 100644 index 0000000000..1698f027cc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rscan0_iodefine.h @@ -0,0 +1,9038 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rscan0_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef RSCAN0_IODEFINE_H +#define RSCAN0_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_rscan0 +{ /* RSCAN0 */ +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C0CFG; /* C0CFG */ + union iodefine_reg32_t C0CTR; /* C0CTR */ + union iodefine_reg32_t C0STS; /* C0STS */ + union iodefine_reg32_t C0ERFL; /* C0ERFL */ +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C1CFG; /* C1CFG */ + union iodefine_reg32_t C1CTR; /* C1CTR */ + union iodefine_reg32_t C1STS; /* C1STS */ + union iodefine_reg32_t C1ERFL; /* C1ERFL */ +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C2CFG; /* C2CFG */ + union iodefine_reg32_t C2CTR; /* C2CTR */ + union iodefine_reg32_t C2STS; /* C2STS */ + union iodefine_reg32_t C2ERFL; /* C2ERFL */ +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C3CFG; /* C3CFG */ + union iodefine_reg32_t C3CTR; /* C3CTR */ + union iodefine_reg32_t C3STS; /* C3STS */ + union iodefine_reg32_t C3ERFL; /* C3ERFL */ +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C4CFG; /* C4CFG */ + union iodefine_reg32_t C4CTR; /* C4CTR */ + union iodefine_reg32_t C4STS; /* C4STS */ + union iodefine_reg32_t C4ERFL; /* C4ERFL */ +/* end of struct st_rscan_from_rscan0cncfg */ + + volatile uint8_t dummy159[52]; /* */ + union iodefine_reg32_t GCFG; /* GCFG */ + union iodefine_reg32_t GCTR; /* GCTR */ + union iodefine_reg32_t GSTS; /* GSTS */ + union iodefine_reg32_t GERFL; /* GERFL */ + union iodefine_reg32_16_t GTSC; /* GTSC */ + union iodefine_reg32_t GAFLECTR; /* GAFLECTR */ +#define RSCAN0_GAFLCFG0_COUNT 2 + union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */ + union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */ + union iodefine_reg32_t RMNB; /* RMNB */ +#define RSCAN0_RMND0_COUNT 3 + union iodefine_reg32_t RMND0; /* RMND0 */ + union iodefine_reg32_t RMND1; /* RMND1 */ + union iodefine_reg32_t RMND2; /* RMND2 */ + + volatile uint8_t dummy160[4]; /* */ +#define RSCAN0_RFCC0_COUNT 8 + union iodefine_reg32_t RFCC0; /* RFCC0 */ + union iodefine_reg32_t RFCC1; /* RFCC1 */ + union iodefine_reg32_t RFCC2; /* RFCC2 */ + union iodefine_reg32_t RFCC3; /* RFCC3 */ + union iodefine_reg32_t RFCC4; /* RFCC4 */ + union iodefine_reg32_t RFCC5; /* RFCC5 */ + union iodefine_reg32_t RFCC6; /* RFCC6 */ + union iodefine_reg32_t RFCC7; /* RFCC7 */ +#define RSCAN0_RFSTS0_COUNT 8 + union iodefine_reg32_t RFSTS0; /* RFSTS0 */ + union iodefine_reg32_t RFSTS1; /* RFSTS1 */ + union iodefine_reg32_t RFSTS2; /* RFSTS2 */ + union iodefine_reg32_t RFSTS3; /* RFSTS3 */ + union iodefine_reg32_t RFSTS4; /* RFSTS4 */ + union iodefine_reg32_t RFSTS5; /* RFSTS5 */ + union iodefine_reg32_t RFSTS6; /* RFSTS6 */ + union iodefine_reg32_t RFSTS7; /* RFSTS7 */ +#define RSCAN0_RFPCTR0_COUNT 8 + union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */ + union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */ + union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */ + union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */ + union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */ + union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */ + union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */ + union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */ +#define RSCAN0_CFCC0_COUNT 15 + union iodefine_reg32_t CFCC0; /* CFCC0 */ + union iodefine_reg32_t CFCC1; /* CFCC1 */ + union iodefine_reg32_t CFCC2; /* CFCC2 */ + union iodefine_reg32_t CFCC3; /* CFCC3 */ + union iodefine_reg32_t CFCC4; /* CFCC4 */ + union iodefine_reg32_t CFCC5; /* CFCC5 */ + union iodefine_reg32_t CFCC6; /* CFCC6 */ + union iodefine_reg32_t CFCC7; /* CFCC7 */ + union iodefine_reg32_t CFCC8; /* CFCC8 */ + union iodefine_reg32_t CFCC9; /* CFCC9 */ + union iodefine_reg32_t CFCC10; /* CFCC10 */ + union iodefine_reg32_t CFCC11; /* CFCC11 */ + union iodefine_reg32_t CFCC12; /* CFCC12 */ + union iodefine_reg32_t CFCC13; /* CFCC13 */ + union iodefine_reg32_t CFCC14; /* CFCC14 */ + + volatile uint8_t dummy161[36]; /* */ +#define RSCAN0_CFSTS0_COUNT 15 + union iodefine_reg32_t CFSTS0; /* CFSTS0 */ + union iodefine_reg32_t CFSTS1; /* CFSTS1 */ + union iodefine_reg32_t CFSTS2; /* CFSTS2 */ + union iodefine_reg32_t CFSTS3; /* CFSTS3 */ + union iodefine_reg32_t CFSTS4; /* CFSTS4 */ + union iodefine_reg32_t CFSTS5; /* CFSTS5 */ + union iodefine_reg32_t CFSTS6; /* CFSTS6 */ + union iodefine_reg32_t CFSTS7; /* CFSTS7 */ + union iodefine_reg32_t CFSTS8; /* CFSTS8 */ + union iodefine_reg32_t CFSTS9; /* CFSTS9 */ + union iodefine_reg32_t CFSTS10; /* CFSTS10 */ + union iodefine_reg32_t CFSTS11; /* CFSTS11 */ + union iodefine_reg32_t CFSTS12; /* CFSTS12 */ + union iodefine_reg32_t CFSTS13; /* CFSTS13 */ + union iodefine_reg32_t CFSTS14; /* CFSTS14 */ + + volatile uint8_t dummy162[36]; /* */ +#define RSCAN0_CFPCTR0_COUNT 15 + union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */ + union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */ + union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */ + union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */ + union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */ + union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */ + union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */ + union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */ + union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */ + union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */ + union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */ + union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */ + union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */ + union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */ + union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */ + + volatile uint8_t dummy163[36]; /* */ + union iodefine_reg32_t FESTS; /* FESTS */ + union iodefine_reg32_t FFSTS; /* FFSTS */ + union iodefine_reg32_t FMSTS; /* FMSTS */ + union iodefine_reg32_t RFISTS; /* RFISTS */ + union iodefine_reg32_t CFRISTS; /* CFRISTS */ + union iodefine_reg32_t CFTISTS; /* CFTISTS */ + +#define RSCAN0_TMC0_COUNT 80 + volatile uint8_t TMC0; /* TMC0 */ + volatile uint8_t TMC1; /* TMC1 */ + volatile uint8_t TMC2; /* TMC2 */ + volatile uint8_t TMC3; /* TMC3 */ + volatile uint8_t TMC4; /* TMC4 */ + volatile uint8_t TMC5; /* TMC5 */ + volatile uint8_t TMC6; /* TMC6 */ + volatile uint8_t TMC7; /* TMC7 */ + volatile uint8_t TMC8; /* TMC8 */ + volatile uint8_t TMC9; /* TMC9 */ + volatile uint8_t TMC10; /* TMC10 */ + volatile uint8_t TMC11; /* TMC11 */ + volatile uint8_t TMC12; /* TMC12 */ + volatile uint8_t TMC13; /* TMC13 */ + volatile uint8_t TMC14; /* TMC14 */ + volatile uint8_t TMC15; /* TMC15 */ + volatile uint8_t TMC16; /* TMC16 */ + volatile uint8_t TMC17; /* TMC17 */ + volatile uint8_t TMC18; /* TMC18 */ + volatile uint8_t TMC19; /* TMC19 */ + volatile uint8_t TMC20; /* TMC20 */ + volatile uint8_t TMC21; /* TMC21 */ + volatile uint8_t TMC22; /* TMC22 */ + volatile uint8_t TMC23; /* TMC23 */ + volatile uint8_t TMC24; /* TMC24 */ + volatile uint8_t TMC25; /* TMC25 */ + volatile uint8_t TMC26; /* TMC26 */ + volatile uint8_t TMC27; /* TMC27 */ + volatile uint8_t TMC28; /* TMC28 */ + volatile uint8_t TMC29; /* TMC29 */ + volatile uint8_t TMC30; /* TMC30 */ + volatile uint8_t TMC31; /* TMC31 */ + volatile uint8_t TMC32; /* TMC32 */ + volatile uint8_t TMC33; /* TMC33 */ + volatile uint8_t TMC34; /* TMC34 */ + volatile uint8_t TMC35; /* TMC35 */ + volatile uint8_t TMC36; /* TMC36 */ + volatile uint8_t TMC37; /* TMC37 */ + volatile uint8_t TMC38; /* TMC38 */ + volatile uint8_t TMC39; /* TMC39 */ + volatile uint8_t TMC40; /* TMC40 */ + volatile uint8_t TMC41; /* TMC41 */ + volatile uint8_t TMC42; /* TMC42 */ + volatile uint8_t TMC43; /* TMC43 */ + volatile uint8_t TMC44; /* TMC44 */ + volatile uint8_t TMC45; /* TMC45 */ + volatile uint8_t TMC46; /* TMC46 */ + volatile uint8_t TMC47; /* TMC47 */ + volatile uint8_t TMC48; /* TMC48 */ + volatile uint8_t TMC49; /* TMC49 */ + volatile uint8_t TMC50; /* TMC50 */ + volatile uint8_t TMC51; /* TMC51 */ + volatile uint8_t TMC52; /* TMC52 */ + volatile uint8_t TMC53; /* TMC53 */ + volatile uint8_t TMC54; /* TMC54 */ + volatile uint8_t TMC55; /* TMC55 */ + volatile uint8_t TMC56; /* TMC56 */ + volatile uint8_t TMC57; /* TMC57 */ + volatile uint8_t TMC58; /* TMC58 */ + volatile uint8_t TMC59; /* TMC59 */ + volatile uint8_t TMC60; /* TMC60 */ + volatile uint8_t TMC61; /* TMC61 */ + volatile uint8_t TMC62; /* TMC62 */ + volatile uint8_t TMC63; /* TMC63 */ + volatile uint8_t TMC64; /* TMC64 */ + volatile uint8_t TMC65; /* TMC65 */ + volatile uint8_t TMC66; /* TMC66 */ + volatile uint8_t TMC67; /* TMC67 */ + volatile uint8_t TMC68; /* TMC68 */ + volatile uint8_t TMC69; /* TMC69 */ + volatile uint8_t TMC70; /* TMC70 */ + volatile uint8_t TMC71; /* TMC71 */ + volatile uint8_t TMC72; /* TMC72 */ + volatile uint8_t TMC73; /* TMC73 */ + volatile uint8_t TMC74; /* TMC74 */ + volatile uint8_t TMC75; /* TMC75 */ + volatile uint8_t TMC76; /* TMC76 */ + volatile uint8_t TMC77; /* TMC77 */ + volatile uint8_t TMC78; /* TMC78 */ + volatile uint8_t TMC79; /* TMC79 */ + volatile uint8_t dummy164[48]; /* */ +#define RSCAN0_TMSTS0_COUNT 80 + volatile uint8_t TMSTS0; /* TMSTS0 */ + volatile uint8_t TMSTS1; /* TMSTS1 */ + volatile uint8_t TMSTS2; /* TMSTS2 */ + volatile uint8_t TMSTS3; /* TMSTS3 */ + volatile uint8_t TMSTS4; /* TMSTS4 */ + volatile uint8_t TMSTS5; /* TMSTS5 */ + volatile uint8_t TMSTS6; /* TMSTS6 */ + volatile uint8_t TMSTS7; /* TMSTS7 */ + volatile uint8_t TMSTS8; /* TMSTS8 */ + volatile uint8_t TMSTS9; /* TMSTS9 */ + volatile uint8_t TMSTS10; /* TMSTS10 */ + volatile uint8_t TMSTS11; /* TMSTS11 */ + volatile uint8_t TMSTS12; /* TMSTS12 */ + volatile uint8_t TMSTS13; /* TMSTS13 */ + volatile uint8_t TMSTS14; /* TMSTS14 */ + volatile uint8_t TMSTS15; /* TMSTS15 */ + volatile uint8_t TMSTS16; /* TMSTS16 */ + volatile uint8_t TMSTS17; /* TMSTS17 */ + volatile uint8_t TMSTS18; /* TMSTS18 */ + volatile uint8_t TMSTS19; /* TMSTS19 */ + volatile uint8_t TMSTS20; /* TMSTS20 */ + volatile uint8_t TMSTS21; /* TMSTS21 */ + volatile uint8_t TMSTS22; /* TMSTS22 */ + volatile uint8_t TMSTS23; /* TMSTS23 */ + volatile uint8_t TMSTS24; /* TMSTS24 */ + volatile uint8_t TMSTS25; /* TMSTS25 */ + volatile uint8_t TMSTS26; /* TMSTS26 */ + volatile uint8_t TMSTS27; /* TMSTS27 */ + volatile uint8_t TMSTS28; /* TMSTS28 */ + volatile uint8_t TMSTS29; /* TMSTS29 */ + volatile uint8_t TMSTS30; /* TMSTS30 */ + volatile uint8_t TMSTS31; /* TMSTS31 */ + volatile uint8_t TMSTS32; /* TMSTS32 */ + volatile uint8_t TMSTS33; /* TMSTS33 */ + volatile uint8_t TMSTS34; /* TMSTS34 */ + volatile uint8_t TMSTS35; /* TMSTS35 */ + volatile uint8_t TMSTS36; /* TMSTS36 */ + volatile uint8_t TMSTS37; /* TMSTS37 */ + volatile uint8_t TMSTS38; /* TMSTS38 */ + volatile uint8_t TMSTS39; /* TMSTS39 */ + volatile uint8_t TMSTS40; /* TMSTS40 */ + volatile uint8_t TMSTS41; /* TMSTS41 */ + volatile uint8_t TMSTS42; /* TMSTS42 */ + volatile uint8_t TMSTS43; /* TMSTS43 */ + volatile uint8_t TMSTS44; /* TMSTS44 */ + volatile uint8_t TMSTS45; /* TMSTS45 */ + volatile uint8_t TMSTS46; /* TMSTS46 */ + volatile uint8_t TMSTS47; /* TMSTS47 */ + volatile uint8_t TMSTS48; /* TMSTS48 */ + volatile uint8_t TMSTS49; /* TMSTS49 */ + volatile uint8_t TMSTS50; /* TMSTS50 */ + volatile uint8_t TMSTS51; /* TMSTS51 */ + volatile uint8_t TMSTS52; /* TMSTS52 */ + volatile uint8_t TMSTS53; /* TMSTS53 */ + volatile uint8_t TMSTS54; /* TMSTS54 */ + volatile uint8_t TMSTS55; /* TMSTS55 */ + volatile uint8_t TMSTS56; /* TMSTS56 */ + volatile uint8_t TMSTS57; /* TMSTS57 */ + volatile uint8_t TMSTS58; /* TMSTS58 */ + volatile uint8_t TMSTS59; /* TMSTS59 */ + volatile uint8_t TMSTS60; /* TMSTS60 */ + volatile uint8_t TMSTS61; /* TMSTS61 */ + volatile uint8_t TMSTS62; /* TMSTS62 */ + volatile uint8_t TMSTS63; /* TMSTS63 */ + volatile uint8_t TMSTS64; /* TMSTS64 */ + volatile uint8_t TMSTS65; /* TMSTS65 */ + volatile uint8_t TMSTS66; /* TMSTS66 */ + volatile uint8_t TMSTS67; /* TMSTS67 */ + volatile uint8_t TMSTS68; /* TMSTS68 */ + volatile uint8_t TMSTS69; /* TMSTS69 */ + volatile uint8_t TMSTS70; /* TMSTS70 */ + volatile uint8_t TMSTS71; /* TMSTS71 */ + volatile uint8_t TMSTS72; /* TMSTS72 */ + volatile uint8_t TMSTS73; /* TMSTS73 */ + volatile uint8_t TMSTS74; /* TMSTS74 */ + volatile uint8_t TMSTS75; /* TMSTS75 */ + volatile uint8_t TMSTS76; /* TMSTS76 */ + volatile uint8_t TMSTS77; /* TMSTS77 */ + volatile uint8_t TMSTS78; /* TMSTS78 */ + volatile uint8_t TMSTS79; /* TMSTS79 */ + volatile uint8_t dummy165[48]; /* */ +#define RSCAN0_TMTRSTS0_COUNT 3 + union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */ + union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */ + union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */ + + volatile uint8_t dummy166[4]; /* */ +#define RSCAN0_TMTARSTS0_COUNT 3 + union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */ + union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */ + union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */ + + volatile uint8_t dummy167[4]; /* */ +#define RSCAN0_TMTCSTS0_COUNT 3 + union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */ + union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */ + union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */ + + volatile uint8_t dummy168[4]; /* */ +#define RSCAN0_TMTASTS0_COUNT 3 + union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */ + union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */ + union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */ + + volatile uint8_t dummy169[4]; /* */ +#define RSCAN0_TMIEC0_COUNT 3 + union iodefine_reg32_t TMIEC0; /* TMIEC0 */ + union iodefine_reg32_t TMIEC1; /* TMIEC1 */ + union iodefine_reg32_t TMIEC2; /* TMIEC2 */ + + volatile uint8_t dummy170[4]; /* */ +#define RSCAN0_TXQCC0_COUNT 5 + union iodefine_reg32_t TXQCC0; /* TXQCC0 */ + union iodefine_reg32_t TXQCC1; /* TXQCC1 */ + union iodefine_reg32_t TXQCC2; /* TXQCC2 */ + union iodefine_reg32_t TXQCC3; /* TXQCC3 */ + union iodefine_reg32_t TXQCC4; /* TXQCC4 */ + + volatile uint8_t dummy171[12]; /* */ +#define RSCAN0_TXQSTS0_COUNT 5 + union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */ + union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */ + union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */ + union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */ + union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */ + + volatile uint8_t dummy172[12]; /* */ +#define RSCAN0_TXQPCTR0_COUNT 5 + union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */ + union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */ + union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */ + union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */ + union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */ + + volatile uint8_t dummy173[12]; /* */ +#define RSCAN0_THLCC0_COUNT 5 + union iodefine_reg32_t THLCC0; /* THLCC0 */ + union iodefine_reg32_t THLCC1; /* THLCC1 */ + union iodefine_reg32_t THLCC2; /* THLCC2 */ + union iodefine_reg32_t THLCC3; /* THLCC3 */ + union iodefine_reg32_t THLCC4; /* THLCC4 */ + + volatile uint8_t dummy174[12]; /* */ +#define RSCAN0_THLSTS0_COUNT 5 + union iodefine_reg32_t THLSTS0; /* THLSTS0 */ + union iodefine_reg32_t THLSTS1; /* THLSTS1 */ + union iodefine_reg32_t THLSTS2; /* THLSTS2 */ + union iodefine_reg32_t THLSTS3; /* THLSTS3 */ + union iodefine_reg32_t THLSTS4; /* THLSTS4 */ + + volatile uint8_t dummy175[12]; /* */ +#define RSCAN0_THLPCTR0_COUNT 5 + union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */ + union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */ + union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */ + union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */ + union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */ + + volatile uint8_t dummy176[12]; /* */ +#define RSCAN0_GTINTSTS0_COUNT 2 + union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */ + union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */ + union iodefine_reg32_t GTSTCFG; /* GTSTCFG */ + union iodefine_reg32_t GTSTCTR; /* GTSTCTR */ + + volatile uint8_t dummy177[12]; /* */ + union iodefine_reg32_16_t GLOCKK; /* GLOCKK */ + + volatile uint8_t dummy178[128]; /* */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID0; /* GAFLID0 */ + union iodefine_reg32_t GAFLM0; /* GAFLM0 */ + union iodefine_reg32_t GAFLP00; /* GAFLP00 */ + union iodefine_reg32_t GAFLP10; /* GAFLP10 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID1; /* GAFLID1 */ + union iodefine_reg32_t GAFLM1; /* GAFLM1 */ + union iodefine_reg32_t GAFLP01; /* GAFLP01 */ + union iodefine_reg32_t GAFLP11; /* GAFLP11 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID2; /* GAFLID2 */ + union iodefine_reg32_t GAFLM2; /* GAFLM2 */ + union iodefine_reg32_t GAFLP02; /* GAFLP02 */ + union iodefine_reg32_t GAFLP12; /* GAFLP12 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID3; /* GAFLID3 */ + union iodefine_reg32_t GAFLM3; /* GAFLM3 */ + union iodefine_reg32_t GAFLP03; /* GAFLP03 */ + union iodefine_reg32_t GAFLP13; /* GAFLP13 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID4; /* GAFLID4 */ + union iodefine_reg32_t GAFLM4; /* GAFLM4 */ + union iodefine_reg32_t GAFLP04; /* GAFLP04 */ + union iodefine_reg32_t GAFLP14; /* GAFLP14 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID5; /* GAFLID5 */ + union iodefine_reg32_t GAFLM5; /* GAFLM5 */ + union iodefine_reg32_t GAFLP05; /* GAFLP05 */ + union iodefine_reg32_t GAFLP15; /* GAFLP15 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID6; /* GAFLID6 */ + union iodefine_reg32_t GAFLM6; /* GAFLM6 */ + union iodefine_reg32_t GAFLP06; /* GAFLP06 */ + union iodefine_reg32_t GAFLP16; /* GAFLP16 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID7; /* GAFLID7 */ + union iodefine_reg32_t GAFLM7; /* GAFLM7 */ + union iodefine_reg32_t GAFLP07; /* GAFLP07 */ + union iodefine_reg32_t GAFLP17; /* GAFLP17 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID8; /* GAFLID8 */ + union iodefine_reg32_t GAFLM8; /* GAFLM8 */ + union iodefine_reg32_t GAFLP08; /* GAFLP08 */ + union iodefine_reg32_t GAFLP18; /* GAFLP18 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID9; /* GAFLID9 */ + union iodefine_reg32_t GAFLM9; /* GAFLM9 */ + union iodefine_reg32_t GAFLP09; /* GAFLP09 */ + union iodefine_reg32_t GAFLP19; /* GAFLP19 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID10; /* GAFLID10 */ + union iodefine_reg32_t GAFLM10; /* GAFLM10 */ + union iodefine_reg32_t GAFLP010; /* GAFLP010 */ + union iodefine_reg32_t GAFLP110; /* GAFLP110 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID11; /* GAFLID11 */ + union iodefine_reg32_t GAFLM11; /* GAFLM11 */ + union iodefine_reg32_t GAFLP011; /* GAFLP011 */ + union iodefine_reg32_t GAFLP111; /* GAFLP111 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID12; /* GAFLID12 */ + union iodefine_reg32_t GAFLM12; /* GAFLM12 */ + union iodefine_reg32_t GAFLP012; /* GAFLP012 */ + union iodefine_reg32_t GAFLP112; /* GAFLP112 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID13; /* GAFLID13 */ + union iodefine_reg32_t GAFLM13; /* GAFLM13 */ + union iodefine_reg32_t GAFLP013; /* GAFLP013 */ + union iodefine_reg32_t GAFLP113; /* GAFLP113 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID14; /* GAFLID14 */ + union iodefine_reg32_t GAFLM14; /* GAFLM14 */ + union iodefine_reg32_t GAFLP014; /* GAFLP014 */ + union iodefine_reg32_t GAFLP114; /* GAFLP114 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID15; /* GAFLID15 */ + union iodefine_reg32_t GAFLM15; /* GAFLM15 */ + union iodefine_reg32_t GAFLP015; /* GAFLP015 */ + union iodefine_reg32_t GAFLP115; /* GAFLP115 */ +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID0; /* RMID0 */ + union iodefine_reg32_t RMPTR0; /* RMPTR0 */ + union iodefine_reg32_t RMDF00; /* RMDF00 */ + union iodefine_reg32_t RMDF10; /* RMDF10 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID1; /* RMID1 */ + union iodefine_reg32_t RMPTR1; /* RMPTR1 */ + union iodefine_reg32_t RMDF01; /* RMDF01 */ + union iodefine_reg32_t RMDF11; /* RMDF11 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID2; /* RMID2 */ + union iodefine_reg32_t RMPTR2; /* RMPTR2 */ + union iodefine_reg32_t RMDF02; /* RMDF02 */ + union iodefine_reg32_t RMDF12; /* RMDF12 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID3; /* RMID3 */ + union iodefine_reg32_t RMPTR3; /* RMPTR3 */ + union iodefine_reg32_t RMDF03; /* RMDF03 */ + union iodefine_reg32_t RMDF13; /* RMDF13 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID4; /* RMID4 */ + union iodefine_reg32_t RMPTR4; /* RMPTR4 */ + union iodefine_reg32_t RMDF04; /* RMDF04 */ + union iodefine_reg32_t RMDF14; /* RMDF14 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID5; /* RMID5 */ + union iodefine_reg32_t RMPTR5; /* RMPTR5 */ + union iodefine_reg32_t RMDF05; /* RMDF05 */ + union iodefine_reg32_t RMDF15; /* RMDF15 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID6; /* RMID6 */ + union iodefine_reg32_t RMPTR6; /* RMPTR6 */ + union iodefine_reg32_t RMDF06; /* RMDF06 */ + union iodefine_reg32_t RMDF16; /* RMDF16 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID7; /* RMID7 */ + union iodefine_reg32_t RMPTR7; /* RMPTR7 */ + union iodefine_reg32_t RMDF07; /* RMDF07 */ + union iodefine_reg32_t RMDF17; /* RMDF17 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID8; /* RMID8 */ + union iodefine_reg32_t RMPTR8; /* RMPTR8 */ + union iodefine_reg32_t RMDF08; /* RMDF08 */ + union iodefine_reg32_t RMDF18; /* RMDF18 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID9; /* RMID9 */ + union iodefine_reg32_t RMPTR9; /* RMPTR9 */ + union iodefine_reg32_t RMDF09; /* RMDF09 */ + union iodefine_reg32_t RMDF19; /* RMDF19 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID10; /* RMID10 */ + union iodefine_reg32_t RMPTR10; /* RMPTR10 */ + union iodefine_reg32_t RMDF010; /* RMDF010 */ + union iodefine_reg32_t RMDF110; /* RMDF110 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID11; /* RMID11 */ + union iodefine_reg32_t RMPTR11; /* RMPTR11 */ + union iodefine_reg32_t RMDF011; /* RMDF011 */ + union iodefine_reg32_t RMDF111; /* RMDF111 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID12; /* RMID12 */ + union iodefine_reg32_t RMPTR12; /* RMPTR12 */ + union iodefine_reg32_t RMDF012; /* RMDF012 */ + union iodefine_reg32_t RMDF112; /* RMDF112 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID13; /* RMID13 */ + union iodefine_reg32_t RMPTR13; /* RMPTR13 */ + union iodefine_reg32_t RMDF013; /* RMDF013 */ + union iodefine_reg32_t RMDF113; /* RMDF113 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID14; /* RMID14 */ + union iodefine_reg32_t RMPTR14; /* RMPTR14 */ + union iodefine_reg32_t RMDF014; /* RMDF014 */ + union iodefine_reg32_t RMDF114; /* RMDF114 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID15; /* RMID15 */ + union iodefine_reg32_t RMPTR15; /* RMPTR15 */ + union iodefine_reg32_t RMDF015; /* RMDF015 */ + union iodefine_reg32_t RMDF115; /* RMDF115 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID16; /* RMID16 */ + union iodefine_reg32_t RMPTR16; /* RMPTR16 */ + union iodefine_reg32_t RMDF016; /* RMDF016 */ + union iodefine_reg32_t RMDF116; /* RMDF116 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID17; /* RMID17 */ + union iodefine_reg32_t RMPTR17; /* RMPTR17 */ + union iodefine_reg32_t RMDF017; /* RMDF017 */ + union iodefine_reg32_t RMDF117; /* RMDF117 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID18; /* RMID18 */ + union iodefine_reg32_t RMPTR18; /* RMPTR18 */ + union iodefine_reg32_t RMDF018; /* RMDF018 */ + union iodefine_reg32_t RMDF118; /* RMDF118 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID19; /* RMID19 */ + union iodefine_reg32_t RMPTR19; /* RMPTR19 */ + union iodefine_reg32_t RMDF019; /* RMDF019 */ + union iodefine_reg32_t RMDF119; /* RMDF119 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID20; /* RMID20 */ + union iodefine_reg32_t RMPTR20; /* RMPTR20 */ + union iodefine_reg32_t RMDF020; /* RMDF020 */ + union iodefine_reg32_t RMDF120; /* RMDF120 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID21; /* RMID21 */ + union iodefine_reg32_t RMPTR21; /* RMPTR21 */ + union iodefine_reg32_t RMDF021; /* RMDF021 */ + union iodefine_reg32_t RMDF121; /* RMDF121 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID22; /* RMID22 */ + union iodefine_reg32_t RMPTR22; /* RMPTR22 */ + union iodefine_reg32_t RMDF022; /* RMDF022 */ + union iodefine_reg32_t RMDF122; /* RMDF122 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID23; /* RMID23 */ + union iodefine_reg32_t RMPTR23; /* RMPTR23 */ + union iodefine_reg32_t RMDF023; /* RMDF023 */ + union iodefine_reg32_t RMDF123; /* RMDF123 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID24; /* RMID24 */ + union iodefine_reg32_t RMPTR24; /* RMPTR24 */ + union iodefine_reg32_t RMDF024; /* RMDF024 */ + union iodefine_reg32_t RMDF124; /* RMDF124 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID25; /* RMID25 */ + union iodefine_reg32_t RMPTR25; /* RMPTR25 */ + union iodefine_reg32_t RMDF025; /* RMDF025 */ + union iodefine_reg32_t RMDF125; /* RMDF125 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID26; /* RMID26 */ + union iodefine_reg32_t RMPTR26; /* RMPTR26 */ + union iodefine_reg32_t RMDF026; /* RMDF026 */ + union iodefine_reg32_t RMDF126; /* RMDF126 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID27; /* RMID27 */ + union iodefine_reg32_t RMPTR27; /* RMPTR27 */ + union iodefine_reg32_t RMDF027; /* RMDF027 */ + union iodefine_reg32_t RMDF127; /* RMDF127 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID28; /* RMID28 */ + union iodefine_reg32_t RMPTR28; /* RMPTR28 */ + union iodefine_reg32_t RMDF028; /* RMDF028 */ + union iodefine_reg32_t RMDF128; /* RMDF128 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID29; /* RMID29 */ + union iodefine_reg32_t RMPTR29; /* RMPTR29 */ + union iodefine_reg32_t RMDF029; /* RMDF029 */ + union iodefine_reg32_t RMDF129; /* RMDF129 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID30; /* RMID30 */ + union iodefine_reg32_t RMPTR30; /* RMPTR30 */ + union iodefine_reg32_t RMDF030; /* RMDF030 */ + union iodefine_reg32_t RMDF130; /* RMDF130 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID31; /* RMID31 */ + union iodefine_reg32_t RMPTR31; /* RMPTR31 */ + union iodefine_reg32_t RMDF031; /* RMDF031 */ + union iodefine_reg32_t RMDF131; /* RMDF131 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID32; /* RMID32 */ + union iodefine_reg32_t RMPTR32; /* RMPTR32 */ + union iodefine_reg32_t RMDF032; /* RMDF032 */ + union iodefine_reg32_t RMDF132; /* RMDF132 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID33; /* RMID33 */ + union iodefine_reg32_t RMPTR33; /* RMPTR33 */ + union iodefine_reg32_t RMDF033; /* RMDF033 */ + union iodefine_reg32_t RMDF133; /* RMDF133 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID34; /* RMID34 */ + union iodefine_reg32_t RMPTR34; /* RMPTR34 */ + union iodefine_reg32_t RMDF034; /* RMDF034 */ + union iodefine_reg32_t RMDF134; /* RMDF134 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID35; /* RMID35 */ + union iodefine_reg32_t RMPTR35; /* RMPTR35 */ + union iodefine_reg32_t RMDF035; /* RMDF035 */ + union iodefine_reg32_t RMDF135; /* RMDF135 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID36; /* RMID36 */ + union iodefine_reg32_t RMPTR36; /* RMPTR36 */ + union iodefine_reg32_t RMDF036; /* RMDF036 */ + union iodefine_reg32_t RMDF136; /* RMDF136 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID37; /* RMID37 */ + union iodefine_reg32_t RMPTR37; /* RMPTR37 */ + union iodefine_reg32_t RMDF037; /* RMDF037 */ + union iodefine_reg32_t RMDF137; /* RMDF137 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID38; /* RMID38 */ + union iodefine_reg32_t RMPTR38; /* RMPTR38 */ + union iodefine_reg32_t RMDF038; /* RMDF038 */ + union iodefine_reg32_t RMDF138; /* RMDF138 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID39; /* RMID39 */ + union iodefine_reg32_t RMPTR39; /* RMPTR39 */ + union iodefine_reg32_t RMDF039; /* RMDF039 */ + union iodefine_reg32_t RMDF139; /* RMDF139 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID40; /* RMID40 */ + union iodefine_reg32_t RMPTR40; /* RMPTR40 */ + union iodefine_reg32_t RMDF040; /* RMDF040 */ + union iodefine_reg32_t RMDF140; /* RMDF140 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID41; /* RMID41 */ + union iodefine_reg32_t RMPTR41; /* RMPTR41 */ + union iodefine_reg32_t RMDF041; /* RMDF041 */ + union iodefine_reg32_t RMDF141; /* RMDF141 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID42; /* RMID42 */ + union iodefine_reg32_t RMPTR42; /* RMPTR42 */ + union iodefine_reg32_t RMDF042; /* RMDF042 */ + union iodefine_reg32_t RMDF142; /* RMDF142 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID43; /* RMID43 */ + union iodefine_reg32_t RMPTR43; /* RMPTR43 */ + union iodefine_reg32_t RMDF043; /* RMDF043 */ + union iodefine_reg32_t RMDF143; /* RMDF143 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID44; /* RMID44 */ + union iodefine_reg32_t RMPTR44; /* RMPTR44 */ + union iodefine_reg32_t RMDF044; /* RMDF044 */ + union iodefine_reg32_t RMDF144; /* RMDF144 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID45; /* RMID45 */ + union iodefine_reg32_t RMPTR45; /* RMPTR45 */ + union iodefine_reg32_t RMDF045; /* RMDF045 */ + union iodefine_reg32_t RMDF145; /* RMDF145 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID46; /* RMID46 */ + union iodefine_reg32_t RMPTR46; /* RMPTR46 */ + union iodefine_reg32_t RMDF046; /* RMDF046 */ + union iodefine_reg32_t RMDF146; /* RMDF146 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID47; /* RMID47 */ + union iodefine_reg32_t RMPTR47; /* RMPTR47 */ + union iodefine_reg32_t RMDF047; /* RMDF047 */ + union iodefine_reg32_t RMDF147; /* RMDF147 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID48; /* RMID48 */ + union iodefine_reg32_t RMPTR48; /* RMPTR48 */ + union iodefine_reg32_t RMDF048; /* RMDF048 */ + union iodefine_reg32_t RMDF148; /* RMDF148 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID49; /* RMID49 */ + union iodefine_reg32_t RMPTR49; /* RMPTR49 */ + union iodefine_reg32_t RMDF049; /* RMDF049 */ + union iodefine_reg32_t RMDF149; /* RMDF149 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID50; /* RMID50 */ + union iodefine_reg32_t RMPTR50; /* RMPTR50 */ + union iodefine_reg32_t RMDF050; /* RMDF050 */ + union iodefine_reg32_t RMDF150; /* RMDF150 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID51; /* RMID51 */ + union iodefine_reg32_t RMPTR51; /* RMPTR51 */ + union iodefine_reg32_t RMDF051; /* RMDF051 */ + union iodefine_reg32_t RMDF151; /* RMDF151 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID52; /* RMID52 */ + union iodefine_reg32_t RMPTR52; /* RMPTR52 */ + union iodefine_reg32_t RMDF052; /* RMDF052 */ + union iodefine_reg32_t RMDF152; /* RMDF152 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID53; /* RMID53 */ + union iodefine_reg32_t RMPTR53; /* RMPTR53 */ + union iodefine_reg32_t RMDF053; /* RMDF053 */ + union iodefine_reg32_t RMDF153; /* RMDF153 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID54; /* RMID54 */ + union iodefine_reg32_t RMPTR54; /* RMPTR54 */ + union iodefine_reg32_t RMDF054; /* RMDF054 */ + union iodefine_reg32_t RMDF154; /* RMDF154 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID55; /* RMID55 */ + union iodefine_reg32_t RMPTR55; /* RMPTR55 */ + union iodefine_reg32_t RMDF055; /* RMDF055 */ + union iodefine_reg32_t RMDF155; /* RMDF155 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID56; /* RMID56 */ + union iodefine_reg32_t RMPTR56; /* RMPTR56 */ + union iodefine_reg32_t RMDF056; /* RMDF056 */ + union iodefine_reg32_t RMDF156; /* RMDF156 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID57; /* RMID57 */ + union iodefine_reg32_t RMPTR57; /* RMPTR57 */ + union iodefine_reg32_t RMDF057; /* RMDF057 */ + union iodefine_reg32_t RMDF157; /* RMDF157 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID58; /* RMID58 */ + union iodefine_reg32_t RMPTR58; /* RMPTR58 */ + union iodefine_reg32_t RMDF058; /* RMDF058 */ + union iodefine_reg32_t RMDF158; /* RMDF158 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID59; /* RMID59 */ + union iodefine_reg32_t RMPTR59; /* RMPTR59 */ + union iodefine_reg32_t RMDF059; /* RMDF059 */ + union iodefine_reg32_t RMDF159; /* RMDF159 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID60; /* RMID60 */ + union iodefine_reg32_t RMPTR60; /* RMPTR60 */ + union iodefine_reg32_t RMDF060; /* RMDF060 */ + union iodefine_reg32_t RMDF160; /* RMDF160 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID61; /* RMID61 */ + union iodefine_reg32_t RMPTR61; /* RMPTR61 */ + union iodefine_reg32_t RMDF061; /* RMDF061 */ + union iodefine_reg32_t RMDF161; /* RMDF161 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID62; /* RMID62 */ + union iodefine_reg32_t RMPTR62; /* RMPTR62 */ + union iodefine_reg32_t RMDF062; /* RMDF062 */ + union iodefine_reg32_t RMDF162; /* RMDF162 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID63; /* RMID63 */ + union iodefine_reg32_t RMPTR63; /* RMPTR63 */ + union iodefine_reg32_t RMDF063; /* RMDF063 */ + union iodefine_reg32_t RMDF163; /* RMDF163 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID64; /* RMID64 */ + union iodefine_reg32_t RMPTR64; /* RMPTR64 */ + union iodefine_reg32_t RMDF064; /* RMDF064 */ + union iodefine_reg32_t RMDF164; /* RMDF164 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID65; /* RMID65 */ + union iodefine_reg32_t RMPTR65; /* RMPTR65 */ + union iodefine_reg32_t RMDF065; /* RMDF065 */ + union iodefine_reg32_t RMDF165; /* RMDF165 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID66; /* RMID66 */ + union iodefine_reg32_t RMPTR66; /* RMPTR66 */ + union iodefine_reg32_t RMDF066; /* RMDF066 */ + union iodefine_reg32_t RMDF166; /* RMDF166 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID67; /* RMID67 */ + union iodefine_reg32_t RMPTR67; /* RMPTR67 */ + union iodefine_reg32_t RMDF067; /* RMDF067 */ + union iodefine_reg32_t RMDF167; /* RMDF167 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID68; /* RMID68 */ + union iodefine_reg32_t RMPTR68; /* RMPTR68 */ + union iodefine_reg32_t RMDF068; /* RMDF068 */ + union iodefine_reg32_t RMDF168; /* RMDF168 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID69; /* RMID69 */ + union iodefine_reg32_t RMPTR69; /* RMPTR69 */ + union iodefine_reg32_t RMDF069; /* RMDF069 */ + union iodefine_reg32_t RMDF169; /* RMDF169 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID70; /* RMID70 */ + union iodefine_reg32_t RMPTR70; /* RMPTR70 */ + union iodefine_reg32_t RMDF070; /* RMDF070 */ + union iodefine_reg32_t RMDF170; /* RMDF170 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID71; /* RMID71 */ + union iodefine_reg32_t RMPTR71; /* RMPTR71 */ + union iodefine_reg32_t RMDF071; /* RMDF071 */ + union iodefine_reg32_t RMDF171; /* RMDF171 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID72; /* RMID72 */ + union iodefine_reg32_t RMPTR72; /* RMPTR72 */ + union iodefine_reg32_t RMDF072; /* RMDF072 */ + union iodefine_reg32_t RMDF172; /* RMDF172 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID73; /* RMID73 */ + union iodefine_reg32_t RMPTR73; /* RMPTR73 */ + union iodefine_reg32_t RMDF073; /* RMDF073 */ + union iodefine_reg32_t RMDF173; /* RMDF173 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID74; /* RMID74 */ + union iodefine_reg32_t RMPTR74; /* RMPTR74 */ + union iodefine_reg32_t RMDF074; /* RMDF074 */ + union iodefine_reg32_t RMDF174; /* RMDF174 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID75; /* RMID75 */ + union iodefine_reg32_t RMPTR75; /* RMPTR75 */ + union iodefine_reg32_t RMDF075; /* RMDF075 */ + union iodefine_reg32_t RMDF175; /* RMDF175 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID76; /* RMID76 */ + union iodefine_reg32_t RMPTR76; /* RMPTR76 */ + union iodefine_reg32_t RMDF076; /* RMDF076 */ + union iodefine_reg32_t RMDF176; /* RMDF176 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID77; /* RMID77 */ + union iodefine_reg32_t RMPTR77; /* RMPTR77 */ + union iodefine_reg32_t RMDF077; /* RMDF077 */ + union iodefine_reg32_t RMDF177; /* RMDF177 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID78; /* RMID78 */ + union iodefine_reg32_t RMPTR78; /* RMPTR78 */ + union iodefine_reg32_t RMDF078; /* RMDF078 */ + union iodefine_reg32_t RMDF178; /* RMDF178 */ +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID79; /* RMID79 */ + union iodefine_reg32_t RMPTR79; /* RMPTR79 */ + union iodefine_reg32_t RMDF079; /* RMDF079 */ + union iodefine_reg32_t RMDF179; /* RMDF179 */ +/* end of struct st_rscan_from_rscan0rmidp */ + + volatile uint8_t dummy179[768]; /* */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID0; /* RFID0 */ + union iodefine_reg32_t RFPTR0; /* RFPTR0 */ + union iodefine_reg32_t RFDF00; /* RFDF00 */ + union iodefine_reg32_t RFDF10; /* RFDF10 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID1; /* RFID1 */ + union iodefine_reg32_t RFPTR1; /* RFPTR1 */ + union iodefine_reg32_t RFDF01; /* RFDF01 */ + union iodefine_reg32_t RFDF11; /* RFDF11 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID2; /* RFID2 */ + union iodefine_reg32_t RFPTR2; /* RFPTR2 */ + union iodefine_reg32_t RFDF02; /* RFDF02 */ + union iodefine_reg32_t RFDF12; /* RFDF12 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID3; /* RFID3 */ + union iodefine_reg32_t RFPTR3; /* RFPTR3 */ + union iodefine_reg32_t RFDF03; /* RFDF03 */ + union iodefine_reg32_t RFDF13; /* RFDF13 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID4; /* RFID4 */ + union iodefine_reg32_t RFPTR4; /* RFPTR4 */ + union iodefine_reg32_t RFDF04; /* RFDF04 */ + union iodefine_reg32_t RFDF14; /* RFDF14 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID5; /* RFID5 */ + union iodefine_reg32_t RFPTR5; /* RFPTR5 */ + union iodefine_reg32_t RFDF05; /* RFDF05 */ + union iodefine_reg32_t RFDF15; /* RFDF15 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID6; /* RFID6 */ + union iodefine_reg32_t RFPTR6; /* RFPTR6 */ + union iodefine_reg32_t RFDF06; /* RFDF06 */ + union iodefine_reg32_t RFDF16; /* RFDF16 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID7; /* RFID7 */ + union iodefine_reg32_t RFPTR7; /* RFPTR7 */ + union iodefine_reg32_t RFDF07; /* RFDF07 */ + union iodefine_reg32_t RFDF17; /* RFDF17 */ +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID0; /* CFID0 */ + union iodefine_reg32_t CFPTR0; /* CFPTR0 */ + union iodefine_reg32_t CFDF00; /* CFDF00 */ + union iodefine_reg32_t CFDF10; /* CFDF10 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID1; /* CFID1 */ + union iodefine_reg32_t CFPTR1; /* CFPTR1 */ + union iodefine_reg32_t CFDF01; /* CFDF01 */ + union iodefine_reg32_t CFDF11; /* CFDF11 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID2; /* CFID2 */ + union iodefine_reg32_t CFPTR2; /* CFPTR2 */ + union iodefine_reg32_t CFDF02; /* CFDF02 */ + union iodefine_reg32_t CFDF12; /* CFDF12 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID3; /* CFID3 */ + union iodefine_reg32_t CFPTR3; /* CFPTR3 */ + union iodefine_reg32_t CFDF03; /* CFDF03 */ + union iodefine_reg32_t CFDF13; /* CFDF13 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID4; /* CFID4 */ + union iodefine_reg32_t CFPTR4; /* CFPTR4 */ + union iodefine_reg32_t CFDF04; /* CFDF04 */ + union iodefine_reg32_t CFDF14; /* CFDF14 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID5; /* CFID5 */ + union iodefine_reg32_t CFPTR5; /* CFPTR5 */ + union iodefine_reg32_t CFDF05; /* CFDF05 */ + union iodefine_reg32_t CFDF15; /* CFDF15 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID6; /* CFID6 */ + union iodefine_reg32_t CFPTR6; /* CFPTR6 */ + union iodefine_reg32_t CFDF06; /* CFDF06 */ + union iodefine_reg32_t CFDF16; /* CFDF16 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID7; /* CFID7 */ + union iodefine_reg32_t CFPTR7; /* CFPTR7 */ + union iodefine_reg32_t CFDF07; /* CFDF07 */ + union iodefine_reg32_t CFDF17; /* CFDF17 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID8; /* CFID8 */ + union iodefine_reg32_t CFPTR8; /* CFPTR8 */ + union iodefine_reg32_t CFDF08; /* CFDF08 */ + union iodefine_reg32_t CFDF18; /* CFDF18 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID9; /* CFID9 */ + union iodefine_reg32_t CFPTR9; /* CFPTR9 */ + union iodefine_reg32_t CFDF09; /* CFDF09 */ + union iodefine_reg32_t CFDF19; /* CFDF19 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID10; /* CFID10 */ + union iodefine_reg32_t CFPTR10; /* CFPTR10 */ + union iodefine_reg32_t CFDF010; /* CFDF010 */ + union iodefine_reg32_t CFDF110; /* CFDF110 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID11; /* CFID11 */ + union iodefine_reg32_t CFPTR11; /* CFPTR11 */ + union iodefine_reg32_t CFDF011; /* CFDF011 */ + union iodefine_reg32_t CFDF111; /* CFDF111 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID12; /* CFID12 */ + union iodefine_reg32_t CFPTR12; /* CFPTR12 */ + union iodefine_reg32_t CFDF012; /* CFDF012 */ + union iodefine_reg32_t CFDF112; /* CFDF112 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID13; /* CFID13 */ + union iodefine_reg32_t CFPTR13; /* CFPTR13 */ + union iodefine_reg32_t CFDF013; /* CFDF013 */ + union iodefine_reg32_t CFDF113; /* CFDF113 */ +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID14; /* CFID14 */ + union iodefine_reg32_t CFPTR14; /* CFPTR14 */ + union iodefine_reg32_t CFDF014; /* CFDF014 */ + union iodefine_reg32_t CFDF114; /* CFDF114 */ +/* end of struct st_rscan_from_rscan0cfidm */ + + volatile uint8_t dummy180[144]; /* */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID0; /* TMID0 */ + union iodefine_reg32_t TMPTR0; /* TMPTR0 */ + union iodefine_reg32_t TMDF00; /* TMDF00 */ + union iodefine_reg32_t TMDF10; /* TMDF10 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID1; /* TMID1 */ + union iodefine_reg32_t TMPTR1; /* TMPTR1 */ + union iodefine_reg32_t TMDF01; /* TMDF01 */ + union iodefine_reg32_t TMDF11; /* TMDF11 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID2; /* TMID2 */ + union iodefine_reg32_t TMPTR2; /* TMPTR2 */ + union iodefine_reg32_t TMDF02; /* TMDF02 */ + union iodefine_reg32_t TMDF12; /* TMDF12 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID3; /* TMID3 */ + union iodefine_reg32_t TMPTR3; /* TMPTR3 */ + union iodefine_reg32_t TMDF03; /* TMDF03 */ + union iodefine_reg32_t TMDF13; /* TMDF13 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID4; /* TMID4 */ + union iodefine_reg32_t TMPTR4; /* TMPTR4 */ + union iodefine_reg32_t TMDF04; /* TMDF04 */ + union iodefine_reg32_t TMDF14; /* TMDF14 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID5; /* TMID5 */ + union iodefine_reg32_t TMPTR5; /* TMPTR5 */ + union iodefine_reg32_t TMDF05; /* TMDF05 */ + union iodefine_reg32_t TMDF15; /* TMDF15 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID6; /* TMID6 */ + union iodefine_reg32_t TMPTR6; /* TMPTR6 */ + union iodefine_reg32_t TMDF06; /* TMDF06 */ + union iodefine_reg32_t TMDF16; /* TMDF16 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID7; /* TMID7 */ + union iodefine_reg32_t TMPTR7; /* TMPTR7 */ + union iodefine_reg32_t TMDF07; /* TMDF07 */ + union iodefine_reg32_t TMDF17; /* TMDF17 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID8; /* TMID8 */ + union iodefine_reg32_t TMPTR8; /* TMPTR8 */ + union iodefine_reg32_t TMDF08; /* TMDF08 */ + union iodefine_reg32_t TMDF18; /* TMDF18 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID9; /* TMID9 */ + union iodefine_reg32_t TMPTR9; /* TMPTR9 */ + union iodefine_reg32_t TMDF09; /* TMDF09 */ + union iodefine_reg32_t TMDF19; /* TMDF19 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID10; /* TMID10 */ + union iodefine_reg32_t TMPTR10; /* TMPTR10 */ + union iodefine_reg32_t TMDF010; /* TMDF010 */ + union iodefine_reg32_t TMDF110; /* TMDF110 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID11; /* TMID11 */ + union iodefine_reg32_t TMPTR11; /* TMPTR11 */ + union iodefine_reg32_t TMDF011; /* TMDF011 */ + union iodefine_reg32_t TMDF111; /* TMDF111 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID12; /* TMID12 */ + union iodefine_reg32_t TMPTR12; /* TMPTR12 */ + union iodefine_reg32_t TMDF012; /* TMDF012 */ + union iodefine_reg32_t TMDF112; /* TMDF112 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID13; /* TMID13 */ + union iodefine_reg32_t TMPTR13; /* TMPTR13 */ + union iodefine_reg32_t TMDF013; /* TMDF013 */ + union iodefine_reg32_t TMDF113; /* TMDF113 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID14; /* TMID14 */ + union iodefine_reg32_t TMPTR14; /* TMPTR14 */ + union iodefine_reg32_t TMDF014; /* TMDF014 */ + union iodefine_reg32_t TMDF114; /* TMDF114 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID15; /* TMID15 */ + union iodefine_reg32_t TMPTR15; /* TMPTR15 */ + union iodefine_reg32_t TMDF015; /* TMDF015 */ + union iodefine_reg32_t TMDF115; /* TMDF115 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID16; /* TMID16 */ + union iodefine_reg32_t TMPTR16; /* TMPTR16 */ + union iodefine_reg32_t TMDF016; /* TMDF016 */ + union iodefine_reg32_t TMDF116; /* TMDF116 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID17; /* TMID17 */ + union iodefine_reg32_t TMPTR17; /* TMPTR17 */ + union iodefine_reg32_t TMDF017; /* TMDF017 */ + union iodefine_reg32_t TMDF117; /* TMDF117 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID18; /* TMID18 */ + union iodefine_reg32_t TMPTR18; /* TMPTR18 */ + union iodefine_reg32_t TMDF018; /* TMDF018 */ + union iodefine_reg32_t TMDF118; /* TMDF118 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID19; /* TMID19 */ + union iodefine_reg32_t TMPTR19; /* TMPTR19 */ + union iodefine_reg32_t TMDF019; /* TMDF019 */ + union iodefine_reg32_t TMDF119; /* TMDF119 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID20; /* TMID20 */ + union iodefine_reg32_t TMPTR20; /* TMPTR20 */ + union iodefine_reg32_t TMDF020; /* TMDF020 */ + union iodefine_reg32_t TMDF120; /* TMDF120 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID21; /* TMID21 */ + union iodefine_reg32_t TMPTR21; /* TMPTR21 */ + union iodefine_reg32_t TMDF021; /* TMDF021 */ + union iodefine_reg32_t TMDF121; /* TMDF121 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID22; /* TMID22 */ + union iodefine_reg32_t TMPTR22; /* TMPTR22 */ + union iodefine_reg32_t TMDF022; /* TMDF022 */ + union iodefine_reg32_t TMDF122; /* TMDF122 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID23; /* TMID23 */ + union iodefine_reg32_t TMPTR23; /* TMPTR23 */ + union iodefine_reg32_t TMDF023; /* TMDF023 */ + union iodefine_reg32_t TMDF123; /* TMDF123 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID24; /* TMID24 */ + union iodefine_reg32_t TMPTR24; /* TMPTR24 */ + union iodefine_reg32_t TMDF024; /* TMDF024 */ + union iodefine_reg32_t TMDF124; /* TMDF124 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID25; /* TMID25 */ + union iodefine_reg32_t TMPTR25; /* TMPTR25 */ + union iodefine_reg32_t TMDF025; /* TMDF025 */ + union iodefine_reg32_t TMDF125; /* TMDF125 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID26; /* TMID26 */ + union iodefine_reg32_t TMPTR26; /* TMPTR26 */ + union iodefine_reg32_t TMDF026; /* TMDF026 */ + union iodefine_reg32_t TMDF126; /* TMDF126 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID27; /* TMID27 */ + union iodefine_reg32_t TMPTR27; /* TMPTR27 */ + union iodefine_reg32_t TMDF027; /* TMDF027 */ + union iodefine_reg32_t TMDF127; /* TMDF127 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID28; /* TMID28 */ + union iodefine_reg32_t TMPTR28; /* TMPTR28 */ + union iodefine_reg32_t TMDF028; /* TMDF028 */ + union iodefine_reg32_t TMDF128; /* TMDF128 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID29; /* TMID29 */ + union iodefine_reg32_t TMPTR29; /* TMPTR29 */ + union iodefine_reg32_t TMDF029; /* TMDF029 */ + union iodefine_reg32_t TMDF129; /* TMDF129 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID30; /* TMID30 */ + union iodefine_reg32_t TMPTR30; /* TMPTR30 */ + union iodefine_reg32_t TMDF030; /* TMDF030 */ + union iodefine_reg32_t TMDF130; /* TMDF130 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID31; /* TMID31 */ + union iodefine_reg32_t TMPTR31; /* TMPTR31 */ + union iodefine_reg32_t TMDF031; /* TMDF031 */ + union iodefine_reg32_t TMDF131; /* TMDF131 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID32; /* TMID32 */ + union iodefine_reg32_t TMPTR32; /* TMPTR32 */ + union iodefine_reg32_t TMDF032; /* TMDF032 */ + union iodefine_reg32_t TMDF132; /* TMDF132 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID33; /* TMID33 */ + union iodefine_reg32_t TMPTR33; /* TMPTR33 */ + union iodefine_reg32_t TMDF033; /* TMDF033 */ + union iodefine_reg32_t TMDF133; /* TMDF133 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID34; /* TMID34 */ + union iodefine_reg32_t TMPTR34; /* TMPTR34 */ + union iodefine_reg32_t TMDF034; /* TMDF034 */ + union iodefine_reg32_t TMDF134; /* TMDF134 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID35; /* TMID35 */ + union iodefine_reg32_t TMPTR35; /* TMPTR35 */ + union iodefine_reg32_t TMDF035; /* TMDF035 */ + union iodefine_reg32_t TMDF135; /* TMDF135 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID36; /* TMID36 */ + union iodefine_reg32_t TMPTR36; /* TMPTR36 */ + union iodefine_reg32_t TMDF036; /* TMDF036 */ + union iodefine_reg32_t TMDF136; /* TMDF136 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID37; /* TMID37 */ + union iodefine_reg32_t TMPTR37; /* TMPTR37 */ + union iodefine_reg32_t TMDF037; /* TMDF037 */ + union iodefine_reg32_t TMDF137; /* TMDF137 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID38; /* TMID38 */ + union iodefine_reg32_t TMPTR38; /* TMPTR38 */ + union iodefine_reg32_t TMDF038; /* TMDF038 */ + union iodefine_reg32_t TMDF138; /* TMDF138 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID39; /* TMID39 */ + union iodefine_reg32_t TMPTR39; /* TMPTR39 */ + union iodefine_reg32_t TMDF039; /* TMDF039 */ + union iodefine_reg32_t TMDF139; /* TMDF139 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID40; /* TMID40 */ + union iodefine_reg32_t TMPTR40; /* TMPTR40 */ + union iodefine_reg32_t TMDF040; /* TMDF040 */ + union iodefine_reg32_t TMDF140; /* TMDF140 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID41; /* TMID41 */ + union iodefine_reg32_t TMPTR41; /* TMPTR41 */ + union iodefine_reg32_t TMDF041; /* TMDF041 */ + union iodefine_reg32_t TMDF141; /* TMDF141 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID42; /* TMID42 */ + union iodefine_reg32_t TMPTR42; /* TMPTR42 */ + union iodefine_reg32_t TMDF042; /* TMDF042 */ + union iodefine_reg32_t TMDF142; /* TMDF142 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID43; /* TMID43 */ + union iodefine_reg32_t TMPTR43; /* TMPTR43 */ + union iodefine_reg32_t TMDF043; /* TMDF043 */ + union iodefine_reg32_t TMDF143; /* TMDF143 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID44; /* TMID44 */ + union iodefine_reg32_t TMPTR44; /* TMPTR44 */ + union iodefine_reg32_t TMDF044; /* TMDF044 */ + union iodefine_reg32_t TMDF144; /* TMDF144 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID45; /* TMID45 */ + union iodefine_reg32_t TMPTR45; /* TMPTR45 */ + union iodefine_reg32_t TMDF045; /* TMDF045 */ + union iodefine_reg32_t TMDF145; /* TMDF145 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID46; /* TMID46 */ + union iodefine_reg32_t TMPTR46; /* TMPTR46 */ + union iodefine_reg32_t TMDF046; /* TMDF046 */ + union iodefine_reg32_t TMDF146; /* TMDF146 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID47; /* TMID47 */ + union iodefine_reg32_t TMPTR47; /* TMPTR47 */ + union iodefine_reg32_t TMDF047; /* TMDF047 */ + union iodefine_reg32_t TMDF147; /* TMDF147 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID48; /* TMID48 */ + union iodefine_reg32_t TMPTR48; /* TMPTR48 */ + union iodefine_reg32_t TMDF048; /* TMDF048 */ + union iodefine_reg32_t TMDF148; /* TMDF148 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID49; /* TMID49 */ + union iodefine_reg32_t TMPTR49; /* TMPTR49 */ + union iodefine_reg32_t TMDF049; /* TMDF049 */ + union iodefine_reg32_t TMDF149; /* TMDF149 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID50; /* TMID50 */ + union iodefine_reg32_t TMPTR50; /* TMPTR50 */ + union iodefine_reg32_t TMDF050; /* TMDF050 */ + union iodefine_reg32_t TMDF150; /* TMDF150 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID51; /* TMID51 */ + union iodefine_reg32_t TMPTR51; /* TMPTR51 */ + union iodefine_reg32_t TMDF051; /* TMDF051 */ + union iodefine_reg32_t TMDF151; /* TMDF151 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID52; /* TMID52 */ + union iodefine_reg32_t TMPTR52; /* TMPTR52 */ + union iodefine_reg32_t TMDF052; /* TMDF052 */ + union iodefine_reg32_t TMDF152; /* TMDF152 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID53; /* TMID53 */ + union iodefine_reg32_t TMPTR53; /* TMPTR53 */ + union iodefine_reg32_t TMDF053; /* TMDF053 */ + union iodefine_reg32_t TMDF153; /* TMDF153 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID54; /* TMID54 */ + union iodefine_reg32_t TMPTR54; /* TMPTR54 */ + union iodefine_reg32_t TMDF054; /* TMDF054 */ + union iodefine_reg32_t TMDF154; /* TMDF154 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID55; /* TMID55 */ + union iodefine_reg32_t TMPTR55; /* TMPTR55 */ + union iodefine_reg32_t TMDF055; /* TMDF055 */ + union iodefine_reg32_t TMDF155; /* TMDF155 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID56; /* TMID56 */ + union iodefine_reg32_t TMPTR56; /* TMPTR56 */ + union iodefine_reg32_t TMDF056; /* TMDF056 */ + union iodefine_reg32_t TMDF156; /* TMDF156 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID57; /* TMID57 */ + union iodefine_reg32_t TMPTR57; /* TMPTR57 */ + union iodefine_reg32_t TMDF057; /* TMDF057 */ + union iodefine_reg32_t TMDF157; /* TMDF157 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID58; /* TMID58 */ + union iodefine_reg32_t TMPTR58; /* TMPTR58 */ + union iodefine_reg32_t TMDF058; /* TMDF058 */ + union iodefine_reg32_t TMDF158; /* TMDF158 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID59; /* TMID59 */ + union iodefine_reg32_t TMPTR59; /* TMPTR59 */ + union iodefine_reg32_t TMDF059; /* TMDF059 */ + union iodefine_reg32_t TMDF159; /* TMDF159 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID60; /* TMID60 */ + union iodefine_reg32_t TMPTR60; /* TMPTR60 */ + union iodefine_reg32_t TMDF060; /* TMDF060 */ + union iodefine_reg32_t TMDF160; /* TMDF160 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID61; /* TMID61 */ + union iodefine_reg32_t TMPTR61; /* TMPTR61 */ + union iodefine_reg32_t TMDF061; /* TMDF061 */ + union iodefine_reg32_t TMDF161; /* TMDF161 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID62; /* TMID62 */ + union iodefine_reg32_t TMPTR62; /* TMPTR62 */ + union iodefine_reg32_t TMDF062; /* TMDF062 */ + union iodefine_reg32_t TMDF162; /* TMDF162 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID63; /* TMID63 */ + union iodefine_reg32_t TMPTR63; /* TMPTR63 */ + union iodefine_reg32_t TMDF063; /* TMDF063 */ + union iodefine_reg32_t TMDF163; /* TMDF163 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID64; /* TMID64 */ + union iodefine_reg32_t TMPTR64; /* TMPTR64 */ + union iodefine_reg32_t TMDF064; /* TMDF064 */ + union iodefine_reg32_t TMDF164; /* TMDF164 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID65; /* TMID65 */ + union iodefine_reg32_t TMPTR65; /* TMPTR65 */ + union iodefine_reg32_t TMDF065; /* TMDF065 */ + union iodefine_reg32_t TMDF165; /* TMDF165 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID66; /* TMID66 */ + union iodefine_reg32_t TMPTR66; /* TMPTR66 */ + union iodefine_reg32_t TMDF066; /* TMDF066 */ + union iodefine_reg32_t TMDF166; /* TMDF166 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID67; /* TMID67 */ + union iodefine_reg32_t TMPTR67; /* TMPTR67 */ + union iodefine_reg32_t TMDF067; /* TMDF067 */ + union iodefine_reg32_t TMDF167; /* TMDF167 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID68; /* TMID68 */ + union iodefine_reg32_t TMPTR68; /* TMPTR68 */ + union iodefine_reg32_t TMDF068; /* TMDF068 */ + union iodefine_reg32_t TMDF168; /* TMDF168 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID69; /* TMID69 */ + union iodefine_reg32_t TMPTR69; /* TMPTR69 */ + union iodefine_reg32_t TMDF069; /* TMDF069 */ + union iodefine_reg32_t TMDF169; /* TMDF169 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID70; /* TMID70 */ + union iodefine_reg32_t TMPTR70; /* TMPTR70 */ + union iodefine_reg32_t TMDF070; /* TMDF070 */ + union iodefine_reg32_t TMDF170; /* TMDF170 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID71; /* TMID71 */ + union iodefine_reg32_t TMPTR71; /* TMPTR71 */ + union iodefine_reg32_t TMDF071; /* TMDF071 */ + union iodefine_reg32_t TMDF171; /* TMDF171 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID72; /* TMID72 */ + union iodefine_reg32_t TMPTR72; /* TMPTR72 */ + union iodefine_reg32_t TMDF072; /* TMDF072 */ + union iodefine_reg32_t TMDF172; /* TMDF172 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID73; /* TMID73 */ + union iodefine_reg32_t TMPTR73; /* TMPTR73 */ + union iodefine_reg32_t TMDF073; /* TMDF073 */ + union iodefine_reg32_t TMDF173; /* TMDF173 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID74; /* TMID74 */ + union iodefine_reg32_t TMPTR74; /* TMPTR74 */ + union iodefine_reg32_t TMDF074; /* TMDF074 */ + union iodefine_reg32_t TMDF174; /* TMDF174 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID75; /* TMID75 */ + union iodefine_reg32_t TMPTR75; /* TMPTR75 */ + union iodefine_reg32_t TMDF075; /* TMDF075 */ + union iodefine_reg32_t TMDF175; /* TMDF175 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID76; /* TMID76 */ + union iodefine_reg32_t TMPTR76; /* TMPTR76 */ + union iodefine_reg32_t TMDF076; /* TMDF076 */ + union iodefine_reg32_t TMDF176; /* TMDF176 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID77; /* TMID77 */ + union iodefine_reg32_t TMPTR77; /* TMPTR77 */ + union iodefine_reg32_t TMDF077; /* TMDF077 */ + union iodefine_reg32_t TMDF177; /* TMDF177 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID78; /* TMID78 */ + union iodefine_reg32_t TMPTR78; /* TMPTR78 */ + union iodefine_reg32_t TMDF078; /* TMDF078 */ + union iodefine_reg32_t TMDF178; /* TMDF178 */ +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID79; /* TMID79 */ + union iodefine_reg32_t TMPTR79; /* TMPTR79 */ + union iodefine_reg32_t TMDF079; /* TMDF079 */ + union iodefine_reg32_t TMDF179; /* TMDF179 */ +/* end of struct st_rscan_from_rscan0tmidp */ + + volatile uint8_t dummy181[768]; /* */ +#define RSCAN0_THLACC0_COUNT 5 + union iodefine_reg32_t THLACC0; /* THLACC0 */ + union iodefine_reg32_t THLACC1; /* THLACC1 */ + union iodefine_reg32_t THLACC2; /* THLACC2 */ + union iodefine_reg32_t THLACC3; /* THLACC3 */ + union iodefine_reg32_t THLACC4; /* THLACC4 */ + +}; + + +struct st_rscan_from_rscan0cncfg +{ + union iodefine_reg32_t CnCFG; /* CnCFG */ + union iodefine_reg32_t CnCTR; /* CnCTR */ + union iodefine_reg32_t CnSTS; /* CnSTS */ + union iodefine_reg32_t CnERFL; /* CnERFL */ +}; + + +struct st_rscan_from_rscan0gaflidj +{ + union iodefine_reg32_t GAFLIDj; /* GAFLIDj */ + union iodefine_reg32_t GAFLMj; /* GAFLMj */ + union iodefine_reg32_t GAFLP0j; /* GAFLP0j */ + union iodefine_reg32_t GAFLP1j; /* GAFLP1j */ +}; + + +struct st_rscan_from_rscan0rmidp +{ + union iodefine_reg32_t RMIDp; /* RMIDp */ + union iodefine_reg32_t RMPTRp; /* RMPTRp */ + union iodefine_reg32_t RMDF0p; /* RMDF0p */ + union iodefine_reg32_t RMDF1p; /* RMDF1p */ +}; + + +struct st_rscan_from_rscan0rfidm +{ + union iodefine_reg32_t RFIDm; /* RFIDm */ + union iodefine_reg32_t RFPTRm; /* RFPTRm */ + union iodefine_reg32_t RFDF0m; /* RFDF0m */ + union iodefine_reg32_t RFDF1m; /* RFDF1m */ +}; + + +struct st_rscan_from_rscan0tmidp +{ + union iodefine_reg32_t TMIDp; /* TMIDp */ + union iodefine_reg32_t TMPTRp; /* TMPTRp */ + union iodefine_reg32_t TMDF0p; /* TMDF0p */ + union iodefine_reg32_t TMDF1p; /* TMDF1p */ +}; + + +struct st_rscan_from_rscan0cfidm +{ + union iodefine_reg32_t CFIDm; /* CFIDm */ + union iodefine_reg32_t CFPTRm; /* CFPTRm */ + union iodefine_reg32_t CFDF0m; /* CFDF0m */ + union iodefine_reg32_t CFDF1m; /* CFDF1m */ +}; + + +#define RSCAN0 (*(struct st_rscan0 *)0xE803A000uL) /* RSCAN0 */ + + +/* Start of channnel array defines of RSCAN0 */ + +/* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0CFIDm_COUNT 15 +#define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \ + &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0CFID0 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID0) /* RSCAN_FROM_RSCAN0CFID0 */ +#define RSCAN_FROM_RSCAN0CFID1 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID1) /* RSCAN_FROM_RSCAN0CFID1 */ +#define RSCAN_FROM_RSCAN0CFID2 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID2) /* RSCAN_FROM_RSCAN0CFID2 */ +#define RSCAN_FROM_RSCAN0CFID3 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID3) /* RSCAN_FROM_RSCAN0CFID3 */ +#define RSCAN_FROM_RSCAN0CFID4 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID4) /* RSCAN_FROM_RSCAN0CFID4 */ +#define RSCAN_FROM_RSCAN0CFID5 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID5) /* RSCAN_FROM_RSCAN0CFID5 */ +#define RSCAN_FROM_RSCAN0CFID6 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID6) /* RSCAN_FROM_RSCAN0CFID6 */ +#define RSCAN_FROM_RSCAN0CFID7 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID7) /* RSCAN_FROM_RSCAN0CFID7 */ +#define RSCAN_FROM_RSCAN0CFID8 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID8) /* RSCAN_FROM_RSCAN0CFID8 */ +#define RSCAN_FROM_RSCAN0CFID9 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID9) /* RSCAN_FROM_RSCAN0CFID9 */ +#define RSCAN_FROM_RSCAN0CFID10 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID10) /* RSCAN_FROM_RSCAN0CFID10 */ +#define RSCAN_FROM_RSCAN0CFID11 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID11) /* RSCAN_FROM_RSCAN0CFID11 */ +#define RSCAN_FROM_RSCAN0CFID12 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID12) /* RSCAN_FROM_RSCAN0CFID12 */ +#define RSCAN_FROM_RSCAN0CFID13 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID13) /* RSCAN_FROM_RSCAN0CFID13 */ +#define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */ + + +/* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0TMIDp_COUNT 80 +#define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \ + &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \ + &RSCAN_FROM_RSCAN0TMID16, &RSCAN_FROM_RSCAN0TMID17, &RSCAN_FROM_RSCAN0TMID18, &RSCAN_FROM_RSCAN0TMID19, &RSCAN_FROM_RSCAN0TMID20, &RSCAN_FROM_RSCAN0TMID21, &RSCAN_FROM_RSCAN0TMID22, &RSCAN_FROM_RSCAN0TMID23, \ + &RSCAN_FROM_RSCAN0TMID24, &RSCAN_FROM_RSCAN0TMID25, &RSCAN_FROM_RSCAN0TMID26, &RSCAN_FROM_RSCAN0TMID27, &RSCAN_FROM_RSCAN0TMID28, &RSCAN_FROM_RSCAN0TMID29, &RSCAN_FROM_RSCAN0TMID30, &RSCAN_FROM_RSCAN0TMID31, \ + &RSCAN_FROM_RSCAN0TMID32, &RSCAN_FROM_RSCAN0TMID33, &RSCAN_FROM_RSCAN0TMID34, &RSCAN_FROM_RSCAN0TMID35, &RSCAN_FROM_RSCAN0TMID36, &RSCAN_FROM_RSCAN0TMID37, &RSCAN_FROM_RSCAN0TMID38, &RSCAN_FROM_RSCAN0TMID39, \ + &RSCAN_FROM_RSCAN0TMID40, &RSCAN_FROM_RSCAN0TMID41, &RSCAN_FROM_RSCAN0TMID42, &RSCAN_FROM_RSCAN0TMID43, &RSCAN_FROM_RSCAN0TMID44, &RSCAN_FROM_RSCAN0TMID45, &RSCAN_FROM_RSCAN0TMID46, &RSCAN_FROM_RSCAN0TMID47, \ + &RSCAN_FROM_RSCAN0TMID48, &RSCAN_FROM_RSCAN0TMID49, &RSCAN_FROM_RSCAN0TMID50, &RSCAN_FROM_RSCAN0TMID51, &RSCAN_FROM_RSCAN0TMID52, &RSCAN_FROM_RSCAN0TMID53, &RSCAN_FROM_RSCAN0TMID54, &RSCAN_FROM_RSCAN0TMID55, \ + &RSCAN_FROM_RSCAN0TMID56, &RSCAN_FROM_RSCAN0TMID57, &RSCAN_FROM_RSCAN0TMID58, &RSCAN_FROM_RSCAN0TMID59, &RSCAN_FROM_RSCAN0TMID60, &RSCAN_FROM_RSCAN0TMID61, &RSCAN_FROM_RSCAN0TMID62, &RSCAN_FROM_RSCAN0TMID63, \ + &RSCAN_FROM_RSCAN0TMID64, &RSCAN_FROM_RSCAN0TMID65, &RSCAN_FROM_RSCAN0TMID66, &RSCAN_FROM_RSCAN0TMID67, &RSCAN_FROM_RSCAN0TMID68, &RSCAN_FROM_RSCAN0TMID69, &RSCAN_FROM_RSCAN0TMID70, &RSCAN_FROM_RSCAN0TMID71, \ + &RSCAN_FROM_RSCAN0TMID72, &RSCAN_FROM_RSCAN0TMID73, &RSCAN_FROM_RSCAN0TMID74, &RSCAN_FROM_RSCAN0TMID75, &RSCAN_FROM_RSCAN0TMID76, &RSCAN_FROM_RSCAN0TMID77, &RSCAN_FROM_RSCAN0TMID78, &RSCAN_FROM_RSCAN0TMID79 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0TMID0 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID0) /* RSCAN_FROM_RSCAN0TMID0 */ +#define RSCAN_FROM_RSCAN0TMID1 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID1) /* RSCAN_FROM_RSCAN0TMID1 */ +#define RSCAN_FROM_RSCAN0TMID2 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID2) /* RSCAN_FROM_RSCAN0TMID2 */ +#define RSCAN_FROM_RSCAN0TMID3 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID3) /* RSCAN_FROM_RSCAN0TMID3 */ +#define RSCAN_FROM_RSCAN0TMID4 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID4) /* RSCAN_FROM_RSCAN0TMID4 */ +#define RSCAN_FROM_RSCAN0TMID5 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID5) /* RSCAN_FROM_RSCAN0TMID5 */ +#define RSCAN_FROM_RSCAN0TMID6 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID6) /* RSCAN_FROM_RSCAN0TMID6 */ +#define RSCAN_FROM_RSCAN0TMID7 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID7) /* RSCAN_FROM_RSCAN0TMID7 */ +#define RSCAN_FROM_RSCAN0TMID8 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID8) /* RSCAN_FROM_RSCAN0TMID8 */ +#define RSCAN_FROM_RSCAN0TMID9 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID9) /* RSCAN_FROM_RSCAN0TMID9 */ +#define RSCAN_FROM_RSCAN0TMID10 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID10) /* RSCAN_FROM_RSCAN0TMID10 */ +#define RSCAN_FROM_RSCAN0TMID11 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID11) /* RSCAN_FROM_RSCAN0TMID11 */ +#define RSCAN_FROM_RSCAN0TMID12 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID12) /* RSCAN_FROM_RSCAN0TMID12 */ +#define RSCAN_FROM_RSCAN0TMID13 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID13) /* RSCAN_FROM_RSCAN0TMID13 */ +#define RSCAN_FROM_RSCAN0TMID14 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID14) /* RSCAN_FROM_RSCAN0TMID14 */ +#define RSCAN_FROM_RSCAN0TMID15 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID15) /* RSCAN_FROM_RSCAN0TMID15 */ +#define RSCAN_FROM_RSCAN0TMID16 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID16) /* RSCAN_FROM_RSCAN0TMID16 */ +#define RSCAN_FROM_RSCAN0TMID17 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID17) /* RSCAN_FROM_RSCAN0TMID17 */ +#define RSCAN_FROM_RSCAN0TMID18 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID18) /* RSCAN_FROM_RSCAN0TMID18 */ +#define RSCAN_FROM_RSCAN0TMID19 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID19) /* RSCAN_FROM_RSCAN0TMID19 */ +#define RSCAN_FROM_RSCAN0TMID20 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID20) /* RSCAN_FROM_RSCAN0TMID20 */ +#define RSCAN_FROM_RSCAN0TMID21 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID21) /* RSCAN_FROM_RSCAN0TMID21 */ +#define RSCAN_FROM_RSCAN0TMID22 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID22) /* RSCAN_FROM_RSCAN0TMID22 */ +#define RSCAN_FROM_RSCAN0TMID23 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID23) /* RSCAN_FROM_RSCAN0TMID23 */ +#define RSCAN_FROM_RSCAN0TMID24 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID24) /* RSCAN_FROM_RSCAN0TMID24 */ +#define RSCAN_FROM_RSCAN0TMID25 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID25) /* RSCAN_FROM_RSCAN0TMID25 */ +#define RSCAN_FROM_RSCAN0TMID26 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID26) /* RSCAN_FROM_RSCAN0TMID26 */ +#define RSCAN_FROM_RSCAN0TMID27 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID27) /* RSCAN_FROM_RSCAN0TMID27 */ +#define RSCAN_FROM_RSCAN0TMID28 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID28) /* RSCAN_FROM_RSCAN0TMID28 */ +#define RSCAN_FROM_RSCAN0TMID29 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID29) /* RSCAN_FROM_RSCAN0TMID29 */ +#define RSCAN_FROM_RSCAN0TMID30 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID30) /* RSCAN_FROM_RSCAN0TMID30 */ +#define RSCAN_FROM_RSCAN0TMID31 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID31) /* RSCAN_FROM_RSCAN0TMID31 */ +#define RSCAN_FROM_RSCAN0TMID32 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID32) /* RSCAN_FROM_RSCAN0TMID32 */ +#define RSCAN_FROM_RSCAN0TMID33 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID33) /* RSCAN_FROM_RSCAN0TMID33 */ +#define RSCAN_FROM_RSCAN0TMID34 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID34) /* RSCAN_FROM_RSCAN0TMID34 */ +#define RSCAN_FROM_RSCAN0TMID35 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID35) /* RSCAN_FROM_RSCAN0TMID35 */ +#define RSCAN_FROM_RSCAN0TMID36 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID36) /* RSCAN_FROM_RSCAN0TMID36 */ +#define RSCAN_FROM_RSCAN0TMID37 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID37) /* RSCAN_FROM_RSCAN0TMID37 */ +#define RSCAN_FROM_RSCAN0TMID38 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID38) /* RSCAN_FROM_RSCAN0TMID38 */ +#define RSCAN_FROM_RSCAN0TMID39 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID39) /* RSCAN_FROM_RSCAN0TMID39 */ +#define RSCAN_FROM_RSCAN0TMID40 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID40) /* RSCAN_FROM_RSCAN0TMID40 */ +#define RSCAN_FROM_RSCAN0TMID41 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID41) /* RSCAN_FROM_RSCAN0TMID41 */ +#define RSCAN_FROM_RSCAN0TMID42 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID42) /* RSCAN_FROM_RSCAN0TMID42 */ +#define RSCAN_FROM_RSCAN0TMID43 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID43) /* RSCAN_FROM_RSCAN0TMID43 */ +#define RSCAN_FROM_RSCAN0TMID44 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID44) /* RSCAN_FROM_RSCAN0TMID44 */ +#define RSCAN_FROM_RSCAN0TMID45 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID45) /* RSCAN_FROM_RSCAN0TMID45 */ +#define RSCAN_FROM_RSCAN0TMID46 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID46) /* RSCAN_FROM_RSCAN0TMID46 */ +#define RSCAN_FROM_RSCAN0TMID47 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID47) /* RSCAN_FROM_RSCAN0TMID47 */ +#define RSCAN_FROM_RSCAN0TMID48 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID48) /* RSCAN_FROM_RSCAN0TMID48 */ +#define RSCAN_FROM_RSCAN0TMID49 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID49) /* RSCAN_FROM_RSCAN0TMID49 */ +#define RSCAN_FROM_RSCAN0TMID50 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID50) /* RSCAN_FROM_RSCAN0TMID50 */ +#define RSCAN_FROM_RSCAN0TMID51 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID51) /* RSCAN_FROM_RSCAN0TMID51 */ +#define RSCAN_FROM_RSCAN0TMID52 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID52) /* RSCAN_FROM_RSCAN0TMID52 */ +#define RSCAN_FROM_RSCAN0TMID53 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID53) /* RSCAN_FROM_RSCAN0TMID53 */ +#define RSCAN_FROM_RSCAN0TMID54 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID54) /* RSCAN_FROM_RSCAN0TMID54 */ +#define RSCAN_FROM_RSCAN0TMID55 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID55) /* RSCAN_FROM_RSCAN0TMID55 */ +#define RSCAN_FROM_RSCAN0TMID56 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID56) /* RSCAN_FROM_RSCAN0TMID56 */ +#define RSCAN_FROM_RSCAN0TMID57 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID57) /* RSCAN_FROM_RSCAN0TMID57 */ +#define RSCAN_FROM_RSCAN0TMID58 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID58) /* RSCAN_FROM_RSCAN0TMID58 */ +#define RSCAN_FROM_RSCAN0TMID59 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID59) /* RSCAN_FROM_RSCAN0TMID59 */ +#define RSCAN_FROM_RSCAN0TMID60 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID60) /* RSCAN_FROM_RSCAN0TMID60 */ +#define RSCAN_FROM_RSCAN0TMID61 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID61) /* RSCAN_FROM_RSCAN0TMID61 */ +#define RSCAN_FROM_RSCAN0TMID62 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID62) /* RSCAN_FROM_RSCAN0TMID62 */ +#define RSCAN_FROM_RSCAN0TMID63 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID63) /* RSCAN_FROM_RSCAN0TMID63 */ +#define RSCAN_FROM_RSCAN0TMID64 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID64) /* RSCAN_FROM_RSCAN0TMID64 */ +#define RSCAN_FROM_RSCAN0TMID65 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID65) /* RSCAN_FROM_RSCAN0TMID65 */ +#define RSCAN_FROM_RSCAN0TMID66 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID66) /* RSCAN_FROM_RSCAN0TMID66 */ +#define RSCAN_FROM_RSCAN0TMID67 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID67) /* RSCAN_FROM_RSCAN0TMID67 */ +#define RSCAN_FROM_RSCAN0TMID68 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID68) /* RSCAN_FROM_RSCAN0TMID68 */ +#define RSCAN_FROM_RSCAN0TMID69 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID69) /* RSCAN_FROM_RSCAN0TMID69 */ +#define RSCAN_FROM_RSCAN0TMID70 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID70) /* RSCAN_FROM_RSCAN0TMID70 */ +#define RSCAN_FROM_RSCAN0TMID71 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID71) /* RSCAN_FROM_RSCAN0TMID71 */ +#define RSCAN_FROM_RSCAN0TMID72 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID72) /* RSCAN_FROM_RSCAN0TMID72 */ +#define RSCAN_FROM_RSCAN0TMID73 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID73) /* RSCAN_FROM_RSCAN0TMID73 */ +#define RSCAN_FROM_RSCAN0TMID74 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID74) /* RSCAN_FROM_RSCAN0TMID74 */ +#define RSCAN_FROM_RSCAN0TMID75 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID75) /* RSCAN_FROM_RSCAN0TMID75 */ +#define RSCAN_FROM_RSCAN0TMID76 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID76) /* RSCAN_FROM_RSCAN0TMID76 */ +#define RSCAN_FROM_RSCAN0TMID77 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID77) /* RSCAN_FROM_RSCAN0TMID77 */ +#define RSCAN_FROM_RSCAN0TMID78 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID78) /* RSCAN_FROM_RSCAN0TMID78 */ +#define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */ + + +/* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0RFIDm_COUNT 8 +#define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0RFID0 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID0) /* RSCAN_FROM_RSCAN0RFID0 */ +#define RSCAN_FROM_RSCAN0RFID1 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID1) /* RSCAN_FROM_RSCAN0RFID1 */ +#define RSCAN_FROM_RSCAN0RFID2 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID2) /* RSCAN_FROM_RSCAN0RFID2 */ +#define RSCAN_FROM_RSCAN0RFID3 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID3) /* RSCAN_FROM_RSCAN0RFID3 */ +#define RSCAN_FROM_RSCAN0RFID4 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID4) /* RSCAN_FROM_RSCAN0RFID4 */ +#define RSCAN_FROM_RSCAN0RFID5 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID5) /* RSCAN_FROM_RSCAN0RFID5 */ +#define RSCAN_FROM_RSCAN0RFID6 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID6) /* RSCAN_FROM_RSCAN0RFID6 */ +#define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */ + + +/* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0RMIDp_COUNT 80 +#define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \ + &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \ + &RSCAN_FROM_RSCAN0RMID16, &RSCAN_FROM_RSCAN0RMID17, &RSCAN_FROM_RSCAN0RMID18, &RSCAN_FROM_RSCAN0RMID19, &RSCAN_FROM_RSCAN0RMID20, &RSCAN_FROM_RSCAN0RMID21, &RSCAN_FROM_RSCAN0RMID22, &RSCAN_FROM_RSCAN0RMID23, \ + &RSCAN_FROM_RSCAN0RMID24, &RSCAN_FROM_RSCAN0RMID25, &RSCAN_FROM_RSCAN0RMID26, &RSCAN_FROM_RSCAN0RMID27, &RSCAN_FROM_RSCAN0RMID28, &RSCAN_FROM_RSCAN0RMID29, &RSCAN_FROM_RSCAN0RMID30, &RSCAN_FROM_RSCAN0RMID31, \ + &RSCAN_FROM_RSCAN0RMID32, &RSCAN_FROM_RSCAN0RMID33, &RSCAN_FROM_RSCAN0RMID34, &RSCAN_FROM_RSCAN0RMID35, &RSCAN_FROM_RSCAN0RMID36, &RSCAN_FROM_RSCAN0RMID37, &RSCAN_FROM_RSCAN0RMID38, &RSCAN_FROM_RSCAN0RMID39, \ + &RSCAN_FROM_RSCAN0RMID40, &RSCAN_FROM_RSCAN0RMID41, &RSCAN_FROM_RSCAN0RMID42, &RSCAN_FROM_RSCAN0RMID43, &RSCAN_FROM_RSCAN0RMID44, &RSCAN_FROM_RSCAN0RMID45, &RSCAN_FROM_RSCAN0RMID46, &RSCAN_FROM_RSCAN0RMID47, \ + &RSCAN_FROM_RSCAN0RMID48, &RSCAN_FROM_RSCAN0RMID49, &RSCAN_FROM_RSCAN0RMID50, &RSCAN_FROM_RSCAN0RMID51, &RSCAN_FROM_RSCAN0RMID52, &RSCAN_FROM_RSCAN0RMID53, &RSCAN_FROM_RSCAN0RMID54, &RSCAN_FROM_RSCAN0RMID55, \ + &RSCAN_FROM_RSCAN0RMID56, &RSCAN_FROM_RSCAN0RMID57, &RSCAN_FROM_RSCAN0RMID58, &RSCAN_FROM_RSCAN0RMID59, &RSCAN_FROM_RSCAN0RMID60, &RSCAN_FROM_RSCAN0RMID61, &RSCAN_FROM_RSCAN0RMID62, &RSCAN_FROM_RSCAN0RMID63, \ + &RSCAN_FROM_RSCAN0RMID64, &RSCAN_FROM_RSCAN0RMID65, &RSCAN_FROM_RSCAN0RMID66, &RSCAN_FROM_RSCAN0RMID67, &RSCAN_FROM_RSCAN0RMID68, &RSCAN_FROM_RSCAN0RMID69, &RSCAN_FROM_RSCAN0RMID70, &RSCAN_FROM_RSCAN0RMID71, \ + &RSCAN_FROM_RSCAN0RMID72, &RSCAN_FROM_RSCAN0RMID73, &RSCAN_FROM_RSCAN0RMID74, &RSCAN_FROM_RSCAN0RMID75, &RSCAN_FROM_RSCAN0RMID76, &RSCAN_FROM_RSCAN0RMID77, &RSCAN_FROM_RSCAN0RMID78, &RSCAN_FROM_RSCAN0RMID79 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0RMID0 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID0) /* RSCAN_FROM_RSCAN0RMID0 */ +#define RSCAN_FROM_RSCAN0RMID1 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID1) /* RSCAN_FROM_RSCAN0RMID1 */ +#define RSCAN_FROM_RSCAN0RMID2 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID2) /* RSCAN_FROM_RSCAN0RMID2 */ +#define RSCAN_FROM_RSCAN0RMID3 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID3) /* RSCAN_FROM_RSCAN0RMID3 */ +#define RSCAN_FROM_RSCAN0RMID4 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID4) /* RSCAN_FROM_RSCAN0RMID4 */ +#define RSCAN_FROM_RSCAN0RMID5 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID5) /* RSCAN_FROM_RSCAN0RMID5 */ +#define RSCAN_FROM_RSCAN0RMID6 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID6) /* RSCAN_FROM_RSCAN0RMID6 */ +#define RSCAN_FROM_RSCAN0RMID7 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID7) /* RSCAN_FROM_RSCAN0RMID7 */ +#define RSCAN_FROM_RSCAN0RMID8 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID8) /* RSCAN_FROM_RSCAN0RMID8 */ +#define RSCAN_FROM_RSCAN0RMID9 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID9) /* RSCAN_FROM_RSCAN0RMID9 */ +#define RSCAN_FROM_RSCAN0RMID10 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID10) /* RSCAN_FROM_RSCAN0RMID10 */ +#define RSCAN_FROM_RSCAN0RMID11 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID11) /* RSCAN_FROM_RSCAN0RMID11 */ +#define RSCAN_FROM_RSCAN0RMID12 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID12) /* RSCAN_FROM_RSCAN0RMID12 */ +#define RSCAN_FROM_RSCAN0RMID13 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID13) /* RSCAN_FROM_RSCAN0RMID13 */ +#define RSCAN_FROM_RSCAN0RMID14 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID14) /* RSCAN_FROM_RSCAN0RMID14 */ +#define RSCAN_FROM_RSCAN0RMID15 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID15) /* RSCAN_FROM_RSCAN0RMID15 */ +#define RSCAN_FROM_RSCAN0RMID16 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID16) /* RSCAN_FROM_RSCAN0RMID16 */ +#define RSCAN_FROM_RSCAN0RMID17 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID17) /* RSCAN_FROM_RSCAN0RMID17 */ +#define RSCAN_FROM_RSCAN0RMID18 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID18) /* RSCAN_FROM_RSCAN0RMID18 */ +#define RSCAN_FROM_RSCAN0RMID19 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID19) /* RSCAN_FROM_RSCAN0RMID19 */ +#define RSCAN_FROM_RSCAN0RMID20 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID20) /* RSCAN_FROM_RSCAN0RMID20 */ +#define RSCAN_FROM_RSCAN0RMID21 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID21) /* RSCAN_FROM_RSCAN0RMID21 */ +#define RSCAN_FROM_RSCAN0RMID22 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID22) /* RSCAN_FROM_RSCAN0RMID22 */ +#define RSCAN_FROM_RSCAN0RMID23 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID23) /* RSCAN_FROM_RSCAN0RMID23 */ +#define RSCAN_FROM_RSCAN0RMID24 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID24) /* RSCAN_FROM_RSCAN0RMID24 */ +#define RSCAN_FROM_RSCAN0RMID25 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID25) /* RSCAN_FROM_RSCAN0RMID25 */ +#define RSCAN_FROM_RSCAN0RMID26 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID26) /* RSCAN_FROM_RSCAN0RMID26 */ +#define RSCAN_FROM_RSCAN0RMID27 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID27) /* RSCAN_FROM_RSCAN0RMID27 */ +#define RSCAN_FROM_RSCAN0RMID28 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID28) /* RSCAN_FROM_RSCAN0RMID28 */ +#define RSCAN_FROM_RSCAN0RMID29 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID29) /* RSCAN_FROM_RSCAN0RMID29 */ +#define RSCAN_FROM_RSCAN0RMID30 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID30) /* RSCAN_FROM_RSCAN0RMID30 */ +#define RSCAN_FROM_RSCAN0RMID31 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID31) /* RSCAN_FROM_RSCAN0RMID31 */ +#define RSCAN_FROM_RSCAN0RMID32 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID32) /* RSCAN_FROM_RSCAN0RMID32 */ +#define RSCAN_FROM_RSCAN0RMID33 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID33) /* RSCAN_FROM_RSCAN0RMID33 */ +#define RSCAN_FROM_RSCAN0RMID34 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID34) /* RSCAN_FROM_RSCAN0RMID34 */ +#define RSCAN_FROM_RSCAN0RMID35 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID35) /* RSCAN_FROM_RSCAN0RMID35 */ +#define RSCAN_FROM_RSCAN0RMID36 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID36) /* RSCAN_FROM_RSCAN0RMID36 */ +#define RSCAN_FROM_RSCAN0RMID37 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID37) /* RSCAN_FROM_RSCAN0RMID37 */ +#define RSCAN_FROM_RSCAN0RMID38 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID38) /* RSCAN_FROM_RSCAN0RMID38 */ +#define RSCAN_FROM_RSCAN0RMID39 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID39) /* RSCAN_FROM_RSCAN0RMID39 */ +#define RSCAN_FROM_RSCAN0RMID40 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID40) /* RSCAN_FROM_RSCAN0RMID40 */ +#define RSCAN_FROM_RSCAN0RMID41 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID41) /* RSCAN_FROM_RSCAN0RMID41 */ +#define RSCAN_FROM_RSCAN0RMID42 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID42) /* RSCAN_FROM_RSCAN0RMID42 */ +#define RSCAN_FROM_RSCAN0RMID43 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID43) /* RSCAN_FROM_RSCAN0RMID43 */ +#define RSCAN_FROM_RSCAN0RMID44 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID44) /* RSCAN_FROM_RSCAN0RMID44 */ +#define RSCAN_FROM_RSCAN0RMID45 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID45) /* RSCAN_FROM_RSCAN0RMID45 */ +#define RSCAN_FROM_RSCAN0RMID46 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID46) /* RSCAN_FROM_RSCAN0RMID46 */ +#define RSCAN_FROM_RSCAN0RMID47 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID47) /* RSCAN_FROM_RSCAN0RMID47 */ +#define RSCAN_FROM_RSCAN0RMID48 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID48) /* RSCAN_FROM_RSCAN0RMID48 */ +#define RSCAN_FROM_RSCAN0RMID49 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID49) /* RSCAN_FROM_RSCAN0RMID49 */ +#define RSCAN_FROM_RSCAN0RMID50 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID50) /* RSCAN_FROM_RSCAN0RMID50 */ +#define RSCAN_FROM_RSCAN0RMID51 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID51) /* RSCAN_FROM_RSCAN0RMID51 */ +#define RSCAN_FROM_RSCAN0RMID52 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID52) /* RSCAN_FROM_RSCAN0RMID52 */ +#define RSCAN_FROM_RSCAN0RMID53 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID53) /* RSCAN_FROM_RSCAN0RMID53 */ +#define RSCAN_FROM_RSCAN0RMID54 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID54) /* RSCAN_FROM_RSCAN0RMID54 */ +#define RSCAN_FROM_RSCAN0RMID55 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID55) /* RSCAN_FROM_RSCAN0RMID55 */ +#define RSCAN_FROM_RSCAN0RMID56 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID56) /* RSCAN_FROM_RSCAN0RMID56 */ +#define RSCAN_FROM_RSCAN0RMID57 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID57) /* RSCAN_FROM_RSCAN0RMID57 */ +#define RSCAN_FROM_RSCAN0RMID58 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID58) /* RSCAN_FROM_RSCAN0RMID58 */ +#define RSCAN_FROM_RSCAN0RMID59 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID59) /* RSCAN_FROM_RSCAN0RMID59 */ +#define RSCAN_FROM_RSCAN0RMID60 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID60) /* RSCAN_FROM_RSCAN0RMID60 */ +#define RSCAN_FROM_RSCAN0RMID61 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID61) /* RSCAN_FROM_RSCAN0RMID61 */ +#define RSCAN_FROM_RSCAN0RMID62 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID62) /* RSCAN_FROM_RSCAN0RMID62 */ +#define RSCAN_FROM_RSCAN0RMID63 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID63) /* RSCAN_FROM_RSCAN0RMID63 */ +#define RSCAN_FROM_RSCAN0RMID64 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID64) /* RSCAN_FROM_RSCAN0RMID64 */ +#define RSCAN_FROM_RSCAN0RMID65 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID65) /* RSCAN_FROM_RSCAN0RMID65 */ +#define RSCAN_FROM_RSCAN0RMID66 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID66) /* RSCAN_FROM_RSCAN0RMID66 */ +#define RSCAN_FROM_RSCAN0RMID67 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID67) /* RSCAN_FROM_RSCAN0RMID67 */ +#define RSCAN_FROM_RSCAN0RMID68 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID68) /* RSCAN_FROM_RSCAN0RMID68 */ +#define RSCAN_FROM_RSCAN0RMID69 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID69) /* RSCAN_FROM_RSCAN0RMID69 */ +#define RSCAN_FROM_RSCAN0RMID70 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID70) /* RSCAN_FROM_RSCAN0RMID70 */ +#define RSCAN_FROM_RSCAN0RMID71 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID71) /* RSCAN_FROM_RSCAN0RMID71 */ +#define RSCAN_FROM_RSCAN0RMID72 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID72) /* RSCAN_FROM_RSCAN0RMID72 */ +#define RSCAN_FROM_RSCAN0RMID73 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID73) /* RSCAN_FROM_RSCAN0RMID73 */ +#define RSCAN_FROM_RSCAN0RMID74 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID74) /* RSCAN_FROM_RSCAN0RMID74 */ +#define RSCAN_FROM_RSCAN0RMID75 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID75) /* RSCAN_FROM_RSCAN0RMID75 */ +#define RSCAN_FROM_RSCAN0RMID76 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID76) /* RSCAN_FROM_RSCAN0RMID76 */ +#define RSCAN_FROM_RSCAN0RMID77 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID77) /* RSCAN_FROM_RSCAN0RMID77 */ +#define RSCAN_FROM_RSCAN0RMID78 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID78) /* RSCAN_FROM_RSCAN0RMID78 */ +#define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */ + + +/* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */ +/*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */ +#define RSCAN_FROM_RSCAN0GAFLIDj_COUNT 16 +#define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \ + &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0GAFLID0 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID0) /* RSCAN_FROM_RSCAN0GAFLID0 */ +#define RSCAN_FROM_RSCAN0GAFLID1 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID1) /* RSCAN_FROM_RSCAN0GAFLID1 */ +#define RSCAN_FROM_RSCAN0GAFLID2 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID2) /* RSCAN_FROM_RSCAN0GAFLID2 */ +#define RSCAN_FROM_RSCAN0GAFLID3 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID3) /* RSCAN_FROM_RSCAN0GAFLID3 */ +#define RSCAN_FROM_RSCAN0GAFLID4 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID4) /* RSCAN_FROM_RSCAN0GAFLID4 */ +#define RSCAN_FROM_RSCAN0GAFLID5 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID5) /* RSCAN_FROM_RSCAN0GAFLID5 */ +#define RSCAN_FROM_RSCAN0GAFLID6 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID6) /* RSCAN_FROM_RSCAN0GAFLID6 */ +#define RSCAN_FROM_RSCAN0GAFLID7 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID7) /* RSCAN_FROM_RSCAN0GAFLID7 */ +#define RSCAN_FROM_RSCAN0GAFLID8 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID8) /* RSCAN_FROM_RSCAN0GAFLID8 */ +#define RSCAN_FROM_RSCAN0GAFLID9 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID9) /* RSCAN_FROM_RSCAN0GAFLID9 */ +#define RSCAN_FROM_RSCAN0GAFLID10 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID10) /* RSCAN_FROM_RSCAN0GAFLID10 */ +#define RSCAN_FROM_RSCAN0GAFLID11 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID11) /* RSCAN_FROM_RSCAN0GAFLID11 */ +#define RSCAN_FROM_RSCAN0GAFLID12 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID12) /* RSCAN_FROM_RSCAN0GAFLID12 */ +#define RSCAN_FROM_RSCAN0GAFLID13 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID13) /* RSCAN_FROM_RSCAN0GAFLID13 */ +#define RSCAN_FROM_RSCAN0GAFLID14 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID14) /* RSCAN_FROM_RSCAN0GAFLID14 */ +#define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */ + + +/* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */ +/*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */ +#define RSCAN_FROM_RSCAN0CnCFG_COUNT 5 +#define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define RSCAN_FROM_RSCAN0C0CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C0CFG) /* RSCAN_FROM_RSCAN0C0CFG */ +#define RSCAN_FROM_RSCAN0C1CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C1CFG) /* RSCAN_FROM_RSCAN0C1CFG */ +#define RSCAN_FROM_RSCAN0C2CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C2CFG) /* RSCAN_FROM_RSCAN0C2CFG */ +#define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */ +#define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */ + +/* End of channnel array defines of RSCAN0 */ + + +#define RSCAN0C0CFG RSCAN0.C0CFG.UINT32 +#define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L] +#define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL] +#define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH] +#define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H] +#define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL] +#define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH] +#define RSCAN0C0CTR RSCAN0.C0CTR.UINT32 +#define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L] +#define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL] +#define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH] +#define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H] +#define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL] +#define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH] +#define RSCAN0C0STS RSCAN0.C0STS.UINT32 +#define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L] +#define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL] +#define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH] +#define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H] +#define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL] +#define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH] +#define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32 +#define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L] +#define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL] +#define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH] +#define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H] +#define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL] +#define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH] +#define RSCAN0C1CFG RSCAN0.C1CFG.UINT32 +#define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L] +#define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL] +#define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH] +#define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H] +#define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL] +#define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH] +#define RSCAN0C1CTR RSCAN0.C1CTR.UINT32 +#define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L] +#define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL] +#define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH] +#define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H] +#define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL] +#define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH] +#define RSCAN0C1STS RSCAN0.C1STS.UINT32 +#define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L] +#define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL] +#define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH] +#define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H] +#define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL] +#define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH] +#define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32 +#define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L] +#define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL] +#define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH] +#define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H] +#define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL] +#define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH] +#define RSCAN0C2CFG RSCAN0.C2CFG.UINT32 +#define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L] +#define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL] +#define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH] +#define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H] +#define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL] +#define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH] +#define RSCAN0C2CTR RSCAN0.C2CTR.UINT32 +#define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L] +#define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL] +#define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH] +#define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H] +#define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL] +#define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH] +#define RSCAN0C2STS RSCAN0.C2STS.UINT32 +#define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L] +#define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL] +#define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH] +#define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H] +#define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL] +#define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH] +#define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32 +#define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L] +#define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL] +#define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH] +#define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H] +#define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL] +#define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH] +#define RSCAN0C3CFG RSCAN0.C3CFG.UINT32 +#define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L] +#define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL] +#define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH] +#define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H] +#define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL] +#define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH] +#define RSCAN0C3CTR RSCAN0.C3CTR.UINT32 +#define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L] +#define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL] +#define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH] +#define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H] +#define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL] +#define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH] +#define RSCAN0C3STS RSCAN0.C3STS.UINT32 +#define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L] +#define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL] +#define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH] +#define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H] +#define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL] +#define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH] +#define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32 +#define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L] +#define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL] +#define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH] +#define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H] +#define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL] +#define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH] +#define RSCAN0C4CFG RSCAN0.C4CFG.UINT32 +#define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L] +#define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL] +#define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH] +#define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H] +#define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL] +#define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH] +#define RSCAN0C4CTR RSCAN0.C4CTR.UINT32 +#define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L] +#define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL] +#define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH] +#define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H] +#define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL] +#define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH] +#define RSCAN0C4STS RSCAN0.C4STS.UINT32 +#define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L] +#define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL] +#define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH] +#define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H] +#define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL] +#define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH] +#define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32 +#define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L] +#define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL] +#define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH] +#define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H] +#define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL] +#define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH] +#define RSCAN0GCFG RSCAN0.GCFG.UINT32 +#define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L] +#define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL] +#define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH] +#define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H] +#define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL] +#define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH] +#define RSCAN0GCTR RSCAN0.GCTR.UINT32 +#define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L] +#define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL] +#define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH] +#define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H] +#define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL] +#define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH] +#define RSCAN0GSTS RSCAN0.GSTS.UINT32 +#define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L] +#define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL] +#define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH] +#define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H] +#define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL] +#define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH] +#define RSCAN0GERFL RSCAN0.GERFL.UINT32 +#define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L] +#define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL] +#define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH] +#define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H] +#define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL] +#define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH] +#define RSCAN0GTSC RSCAN0.GTSC.UINT32 +#define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L] +#define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H] +#define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32 +#define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L] +#define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL] +#define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH] +#define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H] +#define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL] +#define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH] +#define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32 +#define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L] +#define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL] +#define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH] +#define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H] +#define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL] +#define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH] +#define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32 +#define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L] +#define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL] +#define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH] +#define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H] +#define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL] +#define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH] +#define RSCAN0RMNB RSCAN0.RMNB.UINT32 +#define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L] +#define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL] +#define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH] +#define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H] +#define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL] +#define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH] +#define RSCAN0RMND0 RSCAN0.RMND0.UINT32 +#define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L] +#define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL] +#define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH] +#define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H] +#define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL] +#define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH] +#define RSCAN0RMND1 RSCAN0.RMND1.UINT32 +#define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L] +#define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL] +#define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH] +#define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H] +#define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL] +#define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH] +#define RSCAN0RMND2 RSCAN0.RMND2.UINT32 +#define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L] +#define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL] +#define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH] +#define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H] +#define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL] +#define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH] +#define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32 +#define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L] +#define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL] +#define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH] +#define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H] +#define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL] +#define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH] +#define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32 +#define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L] +#define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL] +#define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH] +#define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H] +#define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL] +#define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH] +#define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32 +#define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L] +#define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL] +#define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH] +#define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H] +#define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL] +#define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH] +#define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32 +#define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L] +#define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL] +#define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH] +#define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H] +#define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL] +#define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH] +#define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32 +#define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L] +#define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL] +#define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH] +#define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H] +#define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL] +#define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH] +#define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32 +#define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L] +#define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL] +#define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH] +#define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H] +#define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL] +#define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH] +#define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32 +#define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L] +#define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL] +#define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH] +#define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H] +#define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL] +#define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH] +#define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32 +#define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L] +#define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL] +#define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH] +#define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H] +#define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL] +#define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH] +#define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32 +#define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L] +#define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL] +#define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH] +#define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H] +#define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL] +#define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH] +#define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32 +#define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L] +#define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL] +#define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH] +#define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H] +#define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL] +#define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH] +#define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32 +#define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L] +#define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL] +#define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH] +#define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H] +#define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL] +#define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH] +#define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32 +#define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L] +#define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL] +#define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH] +#define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H] +#define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL] +#define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH] +#define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32 +#define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L] +#define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL] +#define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH] +#define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H] +#define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL] +#define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH] +#define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32 +#define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L] +#define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL] +#define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH] +#define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H] +#define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL] +#define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH] +#define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32 +#define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L] +#define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL] +#define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH] +#define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H] +#define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL] +#define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH] +#define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32 +#define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L] +#define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL] +#define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH] +#define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H] +#define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL] +#define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH] +#define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32 +#define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L] +#define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL] +#define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH] +#define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H] +#define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL] +#define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH] +#define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32 +#define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L] +#define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL] +#define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH] +#define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H] +#define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL] +#define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH] +#define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32 +#define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L] +#define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL] +#define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH] +#define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H] +#define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL] +#define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH] +#define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32 +#define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L] +#define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL] +#define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH] +#define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H] +#define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL] +#define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH] +#define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32 +#define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L] +#define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL] +#define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH] +#define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H] +#define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL] +#define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH] +#define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32 +#define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L] +#define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL] +#define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH] +#define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H] +#define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL] +#define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH] +#define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32 +#define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L] +#define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL] +#define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH] +#define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H] +#define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL] +#define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH] +#define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32 +#define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L] +#define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL] +#define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH] +#define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H] +#define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL] +#define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH] +#define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32 +#define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L] +#define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL] +#define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH] +#define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H] +#define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL] +#define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH] +#define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32 +#define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L] +#define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL] +#define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH] +#define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H] +#define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL] +#define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH] +#define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32 +#define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L] +#define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL] +#define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH] +#define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H] +#define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL] +#define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH] +#define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32 +#define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L] +#define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL] +#define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH] +#define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H] +#define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL] +#define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH] +#define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32 +#define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L] +#define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL] +#define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH] +#define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H] +#define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL] +#define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH] +#define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32 +#define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L] +#define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL] +#define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH] +#define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H] +#define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL] +#define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH] +#define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32 +#define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L] +#define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL] +#define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH] +#define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H] +#define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL] +#define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH] +#define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32 +#define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L] +#define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL] +#define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH] +#define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H] +#define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL] +#define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH] +#define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32 +#define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L] +#define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL] +#define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH] +#define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H] +#define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL] +#define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH] +#define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32 +#define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L] +#define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL] +#define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH] +#define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H] +#define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL] +#define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH] +#define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32 +#define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L] +#define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL] +#define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH] +#define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H] +#define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL] +#define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH] +#define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32 +#define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L] +#define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL] +#define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH] +#define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H] +#define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL] +#define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH] +#define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32 +#define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L] +#define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL] +#define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH] +#define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H] +#define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL] +#define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH] +#define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32 +#define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L] +#define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL] +#define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH] +#define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H] +#define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL] +#define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH] +#define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32 +#define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L] +#define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL] +#define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH] +#define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H] +#define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL] +#define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH] +#define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32 +#define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L] +#define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL] +#define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH] +#define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H] +#define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL] +#define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH] +#define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32 +#define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L] +#define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL] +#define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH] +#define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H] +#define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL] +#define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH] +#define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32 +#define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L] +#define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL] +#define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH] +#define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H] +#define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL] +#define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH] +#define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32 +#define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L] +#define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL] +#define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH] +#define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H] +#define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL] +#define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH] +#define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32 +#define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L] +#define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL] +#define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH] +#define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H] +#define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL] +#define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH] +#define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32 +#define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L] +#define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL] +#define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH] +#define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H] +#define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL] +#define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH] +#define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32 +#define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L] +#define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL] +#define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH] +#define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H] +#define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL] +#define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH] +#define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32 +#define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L] +#define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL] +#define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH] +#define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H] +#define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL] +#define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH] +#define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32 +#define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L] +#define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL] +#define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH] +#define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H] +#define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL] +#define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH] +#define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32 +#define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L] +#define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL] +#define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH] +#define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H] +#define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL] +#define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH] +#define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32 +#define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L] +#define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL] +#define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH] +#define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H] +#define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL] +#define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH] +#define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32 +#define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L] +#define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL] +#define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH] +#define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H] +#define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL] +#define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH] +#define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32 +#define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L] +#define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL] +#define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH] +#define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H] +#define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL] +#define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH] +#define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32 +#define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L] +#define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL] +#define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH] +#define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H] +#define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL] +#define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH] +#define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32 +#define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L] +#define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL] +#define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH] +#define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H] +#define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL] +#define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH] +#define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32 +#define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L] +#define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL] +#define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH] +#define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H] +#define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL] +#define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH] +#define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32 +#define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L] +#define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL] +#define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH] +#define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H] +#define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL] +#define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH] +#define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32 +#define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L] +#define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL] +#define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH] +#define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H] +#define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL] +#define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH] +#define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32 +#define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L] +#define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL] +#define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH] +#define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H] +#define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL] +#define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH] +#define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32 +#define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L] +#define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL] +#define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH] +#define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H] +#define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL] +#define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH] +#define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32 +#define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L] +#define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL] +#define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH] +#define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H] +#define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL] +#define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH] +#define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32 +#define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L] +#define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL] +#define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH] +#define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H] +#define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL] +#define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH] +#define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32 +#define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L] +#define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL] +#define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH] +#define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H] +#define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL] +#define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH] +#define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32 +#define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L] +#define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL] +#define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH] +#define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H] +#define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL] +#define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH] +#define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32 +#define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L] +#define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL] +#define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH] +#define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H] +#define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL] +#define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH] +#define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32 +#define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L] +#define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL] +#define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH] +#define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H] +#define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL] +#define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH] +#define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32 +#define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L] +#define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL] +#define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH] +#define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H] +#define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL] +#define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH] +#define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32 +#define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L] +#define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL] +#define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH] +#define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H] +#define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL] +#define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH] +#define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32 +#define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L] +#define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL] +#define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH] +#define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H] +#define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL] +#define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH] +#define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32 +#define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L] +#define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL] +#define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH] +#define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H] +#define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL] +#define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH] +#define RSCAN0FESTS RSCAN0.FESTS.UINT32 +#define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L] +#define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL] +#define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH] +#define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H] +#define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL] +#define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH] +#define RSCAN0FFSTS RSCAN0.FFSTS.UINT32 +#define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L] +#define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL] +#define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH] +#define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H] +#define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL] +#define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH] +#define RSCAN0FMSTS RSCAN0.FMSTS.UINT32 +#define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L] +#define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL] +#define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH] +#define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H] +#define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL] +#define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH] +#define RSCAN0RFISTS RSCAN0.RFISTS.UINT32 +#define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L] +#define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL] +#define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH] +#define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H] +#define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL] +#define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH] +#define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32 +#define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L] +#define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL] +#define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH] +#define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H] +#define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL] +#define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH] +#define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32 +#define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L] +#define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL] +#define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH] +#define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H] +#define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL] +#define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH] +#define RSCAN0TMC0 RSCAN0.TMC0 +#define RSCAN0TMC1 RSCAN0.TMC1 +#define RSCAN0TMC2 RSCAN0.TMC2 +#define RSCAN0TMC3 RSCAN0.TMC3 +#define RSCAN0TMC4 RSCAN0.TMC4 +#define RSCAN0TMC5 RSCAN0.TMC5 +#define RSCAN0TMC6 RSCAN0.TMC6 +#define RSCAN0TMC7 RSCAN0.TMC7 +#define RSCAN0TMC8 RSCAN0.TMC8 +#define RSCAN0TMC9 RSCAN0.TMC9 +#define RSCAN0TMC10 RSCAN0.TMC10 +#define RSCAN0TMC11 RSCAN0.TMC11 +#define RSCAN0TMC12 RSCAN0.TMC12 +#define RSCAN0TMC13 RSCAN0.TMC13 +#define RSCAN0TMC14 RSCAN0.TMC14 +#define RSCAN0TMC15 RSCAN0.TMC15 +#define RSCAN0TMC16 RSCAN0.TMC16 +#define RSCAN0TMC17 RSCAN0.TMC17 +#define RSCAN0TMC18 RSCAN0.TMC18 +#define RSCAN0TMC19 RSCAN0.TMC19 +#define RSCAN0TMC20 RSCAN0.TMC20 +#define RSCAN0TMC21 RSCAN0.TMC21 +#define RSCAN0TMC22 RSCAN0.TMC22 +#define RSCAN0TMC23 RSCAN0.TMC23 +#define RSCAN0TMC24 RSCAN0.TMC24 +#define RSCAN0TMC25 RSCAN0.TMC25 +#define RSCAN0TMC26 RSCAN0.TMC26 +#define RSCAN0TMC27 RSCAN0.TMC27 +#define RSCAN0TMC28 RSCAN0.TMC28 +#define RSCAN0TMC29 RSCAN0.TMC29 +#define RSCAN0TMC30 RSCAN0.TMC30 +#define RSCAN0TMC31 RSCAN0.TMC31 +#define RSCAN0TMC32 RSCAN0.TMC32 +#define RSCAN0TMC33 RSCAN0.TMC33 +#define RSCAN0TMC34 RSCAN0.TMC34 +#define RSCAN0TMC35 RSCAN0.TMC35 +#define RSCAN0TMC36 RSCAN0.TMC36 +#define RSCAN0TMC37 RSCAN0.TMC37 +#define RSCAN0TMC38 RSCAN0.TMC38 +#define RSCAN0TMC39 RSCAN0.TMC39 +#define RSCAN0TMC40 RSCAN0.TMC40 +#define RSCAN0TMC41 RSCAN0.TMC41 +#define RSCAN0TMC42 RSCAN0.TMC42 +#define RSCAN0TMC43 RSCAN0.TMC43 +#define RSCAN0TMC44 RSCAN0.TMC44 +#define RSCAN0TMC45 RSCAN0.TMC45 +#define RSCAN0TMC46 RSCAN0.TMC46 +#define RSCAN0TMC47 RSCAN0.TMC47 +#define RSCAN0TMC48 RSCAN0.TMC48 +#define RSCAN0TMC49 RSCAN0.TMC49 +#define RSCAN0TMC50 RSCAN0.TMC50 +#define RSCAN0TMC51 RSCAN0.TMC51 +#define RSCAN0TMC52 RSCAN0.TMC52 +#define RSCAN0TMC53 RSCAN0.TMC53 +#define RSCAN0TMC54 RSCAN0.TMC54 +#define RSCAN0TMC55 RSCAN0.TMC55 +#define RSCAN0TMC56 RSCAN0.TMC56 +#define RSCAN0TMC57 RSCAN0.TMC57 +#define RSCAN0TMC58 RSCAN0.TMC58 +#define RSCAN0TMC59 RSCAN0.TMC59 +#define RSCAN0TMC60 RSCAN0.TMC60 +#define RSCAN0TMC61 RSCAN0.TMC61 +#define RSCAN0TMC62 RSCAN0.TMC62 +#define RSCAN0TMC63 RSCAN0.TMC63 +#define RSCAN0TMC64 RSCAN0.TMC64 +#define RSCAN0TMC65 RSCAN0.TMC65 +#define RSCAN0TMC66 RSCAN0.TMC66 +#define RSCAN0TMC67 RSCAN0.TMC67 +#define RSCAN0TMC68 RSCAN0.TMC68 +#define RSCAN0TMC69 RSCAN0.TMC69 +#define RSCAN0TMC70 RSCAN0.TMC70 +#define RSCAN0TMC71 RSCAN0.TMC71 +#define RSCAN0TMC72 RSCAN0.TMC72 +#define RSCAN0TMC73 RSCAN0.TMC73 +#define RSCAN0TMC74 RSCAN0.TMC74 +#define RSCAN0TMC75 RSCAN0.TMC75 +#define RSCAN0TMC76 RSCAN0.TMC76 +#define RSCAN0TMC77 RSCAN0.TMC77 +#define RSCAN0TMC78 RSCAN0.TMC78 +#define RSCAN0TMC79 RSCAN0.TMC79 +#define RSCAN0TMSTS0 RSCAN0.TMSTS0 +#define RSCAN0TMSTS1 RSCAN0.TMSTS1 +#define RSCAN0TMSTS2 RSCAN0.TMSTS2 +#define RSCAN0TMSTS3 RSCAN0.TMSTS3 +#define RSCAN0TMSTS4 RSCAN0.TMSTS4 +#define RSCAN0TMSTS5 RSCAN0.TMSTS5 +#define RSCAN0TMSTS6 RSCAN0.TMSTS6 +#define RSCAN0TMSTS7 RSCAN0.TMSTS7 +#define RSCAN0TMSTS8 RSCAN0.TMSTS8 +#define RSCAN0TMSTS9 RSCAN0.TMSTS9 +#define RSCAN0TMSTS10 RSCAN0.TMSTS10 +#define RSCAN0TMSTS11 RSCAN0.TMSTS11 +#define RSCAN0TMSTS12 RSCAN0.TMSTS12 +#define RSCAN0TMSTS13 RSCAN0.TMSTS13 +#define RSCAN0TMSTS14 RSCAN0.TMSTS14 +#define RSCAN0TMSTS15 RSCAN0.TMSTS15 +#define RSCAN0TMSTS16 RSCAN0.TMSTS16 +#define RSCAN0TMSTS17 RSCAN0.TMSTS17 +#define RSCAN0TMSTS18 RSCAN0.TMSTS18 +#define RSCAN0TMSTS19 RSCAN0.TMSTS19 +#define RSCAN0TMSTS20 RSCAN0.TMSTS20 +#define RSCAN0TMSTS21 RSCAN0.TMSTS21 +#define RSCAN0TMSTS22 RSCAN0.TMSTS22 +#define RSCAN0TMSTS23 RSCAN0.TMSTS23 +#define RSCAN0TMSTS24 RSCAN0.TMSTS24 +#define RSCAN0TMSTS25 RSCAN0.TMSTS25 +#define RSCAN0TMSTS26 RSCAN0.TMSTS26 +#define RSCAN0TMSTS27 RSCAN0.TMSTS27 +#define RSCAN0TMSTS28 RSCAN0.TMSTS28 +#define RSCAN0TMSTS29 RSCAN0.TMSTS29 +#define RSCAN0TMSTS30 RSCAN0.TMSTS30 +#define RSCAN0TMSTS31 RSCAN0.TMSTS31 +#define RSCAN0TMSTS32 RSCAN0.TMSTS32 +#define RSCAN0TMSTS33 RSCAN0.TMSTS33 +#define RSCAN0TMSTS34 RSCAN0.TMSTS34 +#define RSCAN0TMSTS35 RSCAN0.TMSTS35 +#define RSCAN0TMSTS36 RSCAN0.TMSTS36 +#define RSCAN0TMSTS37 RSCAN0.TMSTS37 +#define RSCAN0TMSTS38 RSCAN0.TMSTS38 +#define RSCAN0TMSTS39 RSCAN0.TMSTS39 +#define RSCAN0TMSTS40 RSCAN0.TMSTS40 +#define RSCAN0TMSTS41 RSCAN0.TMSTS41 +#define RSCAN0TMSTS42 RSCAN0.TMSTS42 +#define RSCAN0TMSTS43 RSCAN0.TMSTS43 +#define RSCAN0TMSTS44 RSCAN0.TMSTS44 +#define RSCAN0TMSTS45 RSCAN0.TMSTS45 +#define RSCAN0TMSTS46 RSCAN0.TMSTS46 +#define RSCAN0TMSTS47 RSCAN0.TMSTS47 +#define RSCAN0TMSTS48 RSCAN0.TMSTS48 +#define RSCAN0TMSTS49 RSCAN0.TMSTS49 +#define RSCAN0TMSTS50 RSCAN0.TMSTS50 +#define RSCAN0TMSTS51 RSCAN0.TMSTS51 +#define RSCAN0TMSTS52 RSCAN0.TMSTS52 +#define RSCAN0TMSTS53 RSCAN0.TMSTS53 +#define RSCAN0TMSTS54 RSCAN0.TMSTS54 +#define RSCAN0TMSTS55 RSCAN0.TMSTS55 +#define RSCAN0TMSTS56 RSCAN0.TMSTS56 +#define RSCAN0TMSTS57 RSCAN0.TMSTS57 +#define RSCAN0TMSTS58 RSCAN0.TMSTS58 +#define RSCAN0TMSTS59 RSCAN0.TMSTS59 +#define RSCAN0TMSTS60 RSCAN0.TMSTS60 +#define RSCAN0TMSTS61 RSCAN0.TMSTS61 +#define RSCAN0TMSTS62 RSCAN0.TMSTS62 +#define RSCAN0TMSTS63 RSCAN0.TMSTS63 +#define RSCAN0TMSTS64 RSCAN0.TMSTS64 +#define RSCAN0TMSTS65 RSCAN0.TMSTS65 +#define RSCAN0TMSTS66 RSCAN0.TMSTS66 +#define RSCAN0TMSTS67 RSCAN0.TMSTS67 +#define RSCAN0TMSTS68 RSCAN0.TMSTS68 +#define RSCAN0TMSTS69 RSCAN0.TMSTS69 +#define RSCAN0TMSTS70 RSCAN0.TMSTS70 +#define RSCAN0TMSTS71 RSCAN0.TMSTS71 +#define RSCAN0TMSTS72 RSCAN0.TMSTS72 +#define RSCAN0TMSTS73 RSCAN0.TMSTS73 +#define RSCAN0TMSTS74 RSCAN0.TMSTS74 +#define RSCAN0TMSTS75 RSCAN0.TMSTS75 +#define RSCAN0TMSTS76 RSCAN0.TMSTS76 +#define RSCAN0TMSTS77 RSCAN0.TMSTS77 +#define RSCAN0TMSTS78 RSCAN0.TMSTS78 +#define RSCAN0TMSTS79 RSCAN0.TMSTS79 +#define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32 +#define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L] +#define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL] +#define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH] +#define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H] +#define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL] +#define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH] +#define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32 +#define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L] +#define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL] +#define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH] +#define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H] +#define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL] +#define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH] +#define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32 +#define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L] +#define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL] +#define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH] +#define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H] +#define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL] +#define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH] +#define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32 +#define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L] +#define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL] +#define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH] +#define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H] +#define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL] +#define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH] +#define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32 +#define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L] +#define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL] +#define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH] +#define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H] +#define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL] +#define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH] +#define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32 +#define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L] +#define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL] +#define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH] +#define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H] +#define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL] +#define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH] +#define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32 +#define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L] +#define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL] +#define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH] +#define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H] +#define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL] +#define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH] +#define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32 +#define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L] +#define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL] +#define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH] +#define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H] +#define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL] +#define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH] +#define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32 +#define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L] +#define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL] +#define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH] +#define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H] +#define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL] +#define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH] +#define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32 +#define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L] +#define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL] +#define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH] +#define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H] +#define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL] +#define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH] +#define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32 +#define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L] +#define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL] +#define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH] +#define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H] +#define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL] +#define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH] +#define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32 +#define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L] +#define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL] +#define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH] +#define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H] +#define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL] +#define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH] +#define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32 +#define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L] +#define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL] +#define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH] +#define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H] +#define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL] +#define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH] +#define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32 +#define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L] +#define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL] +#define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH] +#define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H] +#define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL] +#define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH] +#define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32 +#define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L] +#define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL] +#define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH] +#define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H] +#define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL] +#define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH] +#define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32 +#define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L] +#define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL] +#define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH] +#define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H] +#define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL] +#define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH] +#define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32 +#define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L] +#define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL] +#define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH] +#define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H] +#define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL] +#define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH] +#define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32 +#define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L] +#define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL] +#define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH] +#define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H] +#define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL] +#define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH] +#define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32 +#define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L] +#define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL] +#define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH] +#define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H] +#define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL] +#define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH] +#define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32 +#define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L] +#define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL] +#define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH] +#define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H] +#define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL] +#define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH] +#define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32 +#define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L] +#define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL] +#define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH] +#define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H] +#define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL] +#define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH] +#define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32 +#define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L] +#define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL] +#define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH] +#define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H] +#define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL] +#define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH] +#define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32 +#define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L] +#define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL] +#define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH] +#define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H] +#define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL] +#define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH] +#define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32 +#define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L] +#define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL] +#define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH] +#define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H] +#define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL] +#define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH] +#define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32 +#define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L] +#define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL] +#define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH] +#define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H] +#define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL] +#define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH] +#define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32 +#define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L] +#define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL] +#define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH] +#define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H] +#define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL] +#define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH] +#define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32 +#define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L] +#define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL] +#define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH] +#define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H] +#define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL] +#define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH] +#define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32 +#define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L] +#define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL] +#define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH] +#define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H] +#define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL] +#define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH] +#define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32 +#define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L] +#define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL] +#define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH] +#define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H] +#define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL] +#define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH] +#define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32 +#define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L] +#define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL] +#define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH] +#define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H] +#define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL] +#define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH] +#define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32 +#define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L] +#define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL] +#define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH] +#define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H] +#define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL] +#define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH] +#define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32 +#define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L] +#define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL] +#define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH] +#define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H] +#define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL] +#define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH] +#define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32 +#define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L] +#define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL] +#define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH] +#define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H] +#define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL] +#define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH] +#define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32 +#define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L] +#define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL] +#define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH] +#define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H] +#define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL] +#define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH] +#define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32 +#define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L] +#define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL] +#define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH] +#define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H] +#define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL] +#define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH] +#define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32 +#define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L] +#define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL] +#define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH] +#define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H] +#define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL] +#define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH] +#define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32 +#define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L] +#define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL] +#define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH] +#define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H] +#define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL] +#define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH] +#define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32 +#define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L] +#define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL] +#define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH] +#define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H] +#define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL] +#define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH] +#define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32 +#define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L] +#define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL] +#define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH] +#define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H] +#define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL] +#define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH] +#define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32 +#define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L] +#define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL] +#define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH] +#define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H] +#define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL] +#define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH] +#define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32 +#define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L] +#define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL] +#define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH] +#define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H] +#define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL] +#define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH] +#define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32 +#define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L] +#define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL] +#define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH] +#define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H] +#define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL] +#define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH] +#define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32 +#define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L] +#define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL] +#define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH] +#define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H] +#define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL] +#define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH] +#define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32 +#define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L] +#define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL] +#define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH] +#define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H] +#define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL] +#define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH] +#define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32 +#define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L] +#define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL] +#define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH] +#define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H] +#define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL] +#define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH] +#define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32 +#define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L] +#define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL] +#define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH] +#define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H] +#define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL] +#define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH] +#define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32 +#define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L] +#define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL] +#define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH] +#define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H] +#define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL] +#define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH] +#define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32 +#define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L] +#define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL] +#define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH] +#define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H] +#define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL] +#define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH] +#define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32 +#define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L] +#define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL] +#define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH] +#define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H] +#define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL] +#define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH] +#define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32 +#define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L] +#define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H] +#define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32 +#define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L] +#define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL] +#define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH] +#define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H] +#define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL] +#define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH] +#define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32 +#define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L] +#define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL] +#define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH] +#define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H] +#define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL] +#define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH] +#define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32 +#define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L] +#define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL] +#define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH] +#define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H] +#define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL] +#define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH] +#define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32 +#define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L] +#define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL] +#define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH] +#define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H] +#define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL] +#define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH] +#define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32 +#define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L] +#define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL] +#define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH] +#define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H] +#define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL] +#define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH] +#define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32 +#define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L] +#define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL] +#define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH] +#define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H] +#define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL] +#define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH] +#define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32 +#define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L] +#define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL] +#define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH] +#define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H] +#define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL] +#define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH] +#define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32 +#define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L] +#define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL] +#define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH] +#define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H] +#define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL] +#define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH] +#define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32 +#define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L] +#define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL] +#define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH] +#define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H] +#define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL] +#define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH] +#define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32 +#define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L] +#define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL] +#define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH] +#define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H] +#define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL] +#define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH] +#define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32 +#define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L] +#define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL] +#define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH] +#define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H] +#define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL] +#define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH] +#define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32 +#define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L] +#define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL] +#define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH] +#define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H] +#define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL] +#define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH] +#define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32 +#define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L] +#define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL] +#define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH] +#define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H] +#define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL] +#define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH] +#define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32 +#define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L] +#define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL] +#define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH] +#define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H] +#define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL] +#define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH] +#define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32 +#define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L] +#define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL] +#define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH] +#define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H] +#define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL] +#define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH] +#define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32 +#define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L] +#define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL] +#define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH] +#define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H] +#define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL] +#define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH] +#define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32 +#define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L] +#define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL] +#define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH] +#define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H] +#define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL] +#define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH] +#define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32 +#define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L] +#define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL] +#define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH] +#define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H] +#define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL] +#define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH] +#define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32 +#define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L] +#define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL] +#define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH] +#define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H] +#define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL] +#define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH] +#define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32 +#define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L] +#define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL] +#define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH] +#define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H] +#define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL] +#define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH] +#define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32 +#define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L] +#define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL] +#define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH] +#define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H] +#define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL] +#define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH] +#define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32 +#define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L] +#define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL] +#define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH] +#define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H] +#define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL] +#define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH] +#define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32 +#define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L] +#define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL] +#define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH] +#define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H] +#define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL] +#define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH] +#define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32 +#define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L] +#define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL] +#define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH] +#define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H] +#define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL] +#define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH] +#define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32 +#define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L] +#define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL] +#define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH] +#define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H] +#define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL] +#define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH] +#define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32 +#define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L] +#define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL] +#define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH] +#define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H] +#define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL] +#define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH] +#define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32 +#define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L] +#define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL] +#define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH] +#define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H] +#define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL] +#define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH] +#define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32 +#define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L] +#define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL] +#define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH] +#define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H] +#define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL] +#define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH] +#define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32 +#define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L] +#define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL] +#define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH] +#define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H] +#define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL] +#define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH] +#define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32 +#define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L] +#define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL] +#define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH] +#define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H] +#define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL] +#define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH] +#define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32 +#define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L] +#define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL] +#define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH] +#define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H] +#define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL] +#define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH] +#define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32 +#define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L] +#define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL] +#define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH] +#define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H] +#define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL] +#define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH] +#define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32 +#define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L] +#define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL] +#define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH] +#define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H] +#define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL] +#define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH] +#define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32 +#define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L] +#define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL] +#define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH] +#define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H] +#define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL] +#define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH] +#define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32 +#define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L] +#define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL] +#define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH] +#define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H] +#define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL] +#define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH] +#define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32 +#define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L] +#define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL] +#define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH] +#define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H] +#define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL] +#define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH] +#define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32 +#define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L] +#define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL] +#define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH] +#define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H] +#define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL] +#define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH] +#define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32 +#define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L] +#define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL] +#define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH] +#define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H] +#define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL] +#define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH] +#define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32 +#define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L] +#define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL] +#define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH] +#define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H] +#define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL] +#define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH] +#define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32 +#define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L] +#define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL] +#define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH] +#define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H] +#define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL] +#define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH] +#define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32 +#define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L] +#define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL] +#define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH] +#define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H] +#define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL] +#define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH] +#define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32 +#define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L] +#define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL] +#define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH] +#define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H] +#define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL] +#define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH] +#define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32 +#define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L] +#define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL] +#define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH] +#define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H] +#define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL] +#define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH] +#define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32 +#define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L] +#define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL] +#define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH] +#define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H] +#define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL] +#define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH] +#define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32 +#define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L] +#define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL] +#define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH] +#define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H] +#define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL] +#define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH] +#define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32 +#define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L] +#define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL] +#define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH] +#define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H] +#define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL] +#define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH] +#define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32 +#define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L] +#define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL] +#define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH] +#define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H] +#define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL] +#define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH] +#define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32 +#define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L] +#define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL] +#define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH] +#define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H] +#define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL] +#define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH] +#define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32 +#define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L] +#define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL] +#define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH] +#define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H] +#define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL] +#define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH] +#define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32 +#define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L] +#define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL] +#define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH] +#define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H] +#define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL] +#define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH] +#define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32 +#define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L] +#define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL] +#define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH] +#define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H] +#define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL] +#define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH] +#define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32 +#define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L] +#define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL] +#define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH] +#define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H] +#define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL] +#define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH] +#define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32 +#define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L] +#define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL] +#define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH] +#define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H] +#define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL] +#define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH] +#define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32 +#define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L] +#define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL] +#define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH] +#define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H] +#define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL] +#define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH] +#define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32 +#define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L] +#define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL] +#define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH] +#define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H] +#define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL] +#define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH] +#define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32 +#define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L] +#define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL] +#define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH] +#define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H] +#define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL] +#define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH] +#define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32 +#define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L] +#define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL] +#define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH] +#define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H] +#define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL] +#define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH] +#define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32 +#define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L] +#define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL] +#define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH] +#define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H] +#define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL] +#define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH] +#define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32 +#define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L] +#define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL] +#define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH] +#define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H] +#define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL] +#define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH] +#define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32 +#define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L] +#define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL] +#define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH] +#define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H] +#define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL] +#define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH] +#define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32 +#define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L] +#define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL] +#define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH] +#define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H] +#define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL] +#define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH] +#define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32 +#define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L] +#define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL] +#define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH] +#define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H] +#define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL] +#define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH] +#define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32 +#define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L] +#define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL] +#define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH] +#define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H] +#define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL] +#define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH] +#define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32 +#define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L] +#define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL] +#define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH] +#define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H] +#define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL] +#define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH] +#define RSCAN0RMID0 RSCAN0.RMID0.UINT32 +#define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L] +#define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL] +#define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH] +#define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H] +#define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL] +#define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH] +#define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32 +#define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L] +#define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL] +#define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH] +#define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H] +#define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL] +#define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH] +#define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32 +#define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L] +#define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL] +#define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH] +#define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H] +#define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL] +#define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH] +#define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32 +#define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L] +#define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL] +#define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH] +#define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H] +#define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL] +#define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH] +#define RSCAN0RMID1 RSCAN0.RMID1.UINT32 +#define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L] +#define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL] +#define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH] +#define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H] +#define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL] +#define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH] +#define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32 +#define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L] +#define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL] +#define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH] +#define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H] +#define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL] +#define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH] +#define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32 +#define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L] +#define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL] +#define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH] +#define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H] +#define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL] +#define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH] +#define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32 +#define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L] +#define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL] +#define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH] +#define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H] +#define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL] +#define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH] +#define RSCAN0RMID2 RSCAN0.RMID2.UINT32 +#define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L] +#define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL] +#define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH] +#define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H] +#define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL] +#define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH] +#define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32 +#define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L] +#define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL] +#define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH] +#define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H] +#define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL] +#define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH] +#define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32 +#define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L] +#define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL] +#define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH] +#define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H] +#define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL] +#define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH] +#define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32 +#define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L] +#define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL] +#define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH] +#define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H] +#define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL] +#define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH] +#define RSCAN0RMID3 RSCAN0.RMID3.UINT32 +#define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L] +#define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL] +#define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH] +#define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H] +#define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL] +#define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH] +#define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32 +#define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L] +#define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL] +#define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH] +#define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H] +#define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL] +#define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH] +#define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32 +#define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L] +#define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL] +#define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH] +#define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H] +#define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL] +#define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH] +#define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32 +#define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L] +#define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL] +#define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH] +#define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H] +#define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL] +#define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH] +#define RSCAN0RMID4 RSCAN0.RMID4.UINT32 +#define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L] +#define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL] +#define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH] +#define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H] +#define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL] +#define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH] +#define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32 +#define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L] +#define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL] +#define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH] +#define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H] +#define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL] +#define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH] +#define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32 +#define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L] +#define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL] +#define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH] +#define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H] +#define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL] +#define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH] +#define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32 +#define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L] +#define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL] +#define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH] +#define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H] +#define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL] +#define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH] +#define RSCAN0RMID5 RSCAN0.RMID5.UINT32 +#define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L] +#define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL] +#define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH] +#define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H] +#define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL] +#define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH] +#define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32 +#define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L] +#define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL] +#define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH] +#define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H] +#define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL] +#define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH] +#define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32 +#define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L] +#define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL] +#define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH] +#define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H] +#define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL] +#define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH] +#define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32 +#define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L] +#define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL] +#define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH] +#define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H] +#define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL] +#define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH] +#define RSCAN0RMID6 RSCAN0.RMID6.UINT32 +#define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L] +#define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL] +#define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH] +#define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H] +#define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL] +#define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH] +#define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32 +#define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L] +#define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL] +#define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH] +#define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H] +#define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL] +#define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH] +#define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32 +#define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L] +#define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL] +#define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH] +#define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H] +#define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL] +#define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH] +#define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32 +#define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L] +#define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL] +#define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH] +#define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H] +#define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL] +#define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH] +#define RSCAN0RMID7 RSCAN0.RMID7.UINT32 +#define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L] +#define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL] +#define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH] +#define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H] +#define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL] +#define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH] +#define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32 +#define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L] +#define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL] +#define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH] +#define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H] +#define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL] +#define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH] +#define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32 +#define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L] +#define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL] +#define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH] +#define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H] +#define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL] +#define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH] +#define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32 +#define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L] +#define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL] +#define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH] +#define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H] +#define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL] +#define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH] +#define RSCAN0RMID8 RSCAN0.RMID8.UINT32 +#define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L] +#define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL] +#define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH] +#define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H] +#define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL] +#define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH] +#define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32 +#define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L] +#define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL] +#define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH] +#define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H] +#define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL] +#define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH] +#define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32 +#define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L] +#define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL] +#define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH] +#define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H] +#define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL] +#define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH] +#define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32 +#define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L] +#define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL] +#define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH] +#define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H] +#define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL] +#define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH] +#define RSCAN0RMID9 RSCAN0.RMID9.UINT32 +#define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L] +#define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL] +#define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH] +#define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H] +#define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL] +#define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH] +#define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32 +#define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L] +#define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL] +#define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH] +#define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H] +#define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL] +#define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH] +#define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32 +#define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L] +#define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL] +#define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH] +#define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H] +#define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL] +#define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH] +#define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32 +#define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L] +#define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL] +#define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH] +#define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H] +#define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL] +#define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH] +#define RSCAN0RMID10 RSCAN0.RMID10.UINT32 +#define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L] +#define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL] +#define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH] +#define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H] +#define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL] +#define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH] +#define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32 +#define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L] +#define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL] +#define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH] +#define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H] +#define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL] +#define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH] +#define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32 +#define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L] +#define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL] +#define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH] +#define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H] +#define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL] +#define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH] +#define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32 +#define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L] +#define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL] +#define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH] +#define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H] +#define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL] +#define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH] +#define RSCAN0RMID11 RSCAN0.RMID11.UINT32 +#define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L] +#define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL] +#define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH] +#define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H] +#define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL] +#define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH] +#define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32 +#define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L] +#define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL] +#define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH] +#define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H] +#define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL] +#define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH] +#define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32 +#define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L] +#define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL] +#define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH] +#define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H] +#define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL] +#define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH] +#define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32 +#define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L] +#define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL] +#define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH] +#define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H] +#define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL] +#define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH] +#define RSCAN0RMID12 RSCAN0.RMID12.UINT32 +#define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L] +#define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL] +#define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH] +#define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H] +#define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL] +#define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH] +#define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32 +#define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L] +#define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL] +#define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH] +#define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H] +#define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL] +#define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH] +#define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32 +#define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L] +#define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL] +#define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH] +#define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H] +#define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL] +#define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH] +#define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32 +#define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L] +#define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL] +#define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH] +#define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H] +#define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL] +#define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH] +#define RSCAN0RMID13 RSCAN0.RMID13.UINT32 +#define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L] +#define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL] +#define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH] +#define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H] +#define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL] +#define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH] +#define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32 +#define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L] +#define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL] +#define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH] +#define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H] +#define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL] +#define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH] +#define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32 +#define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L] +#define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL] +#define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH] +#define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H] +#define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL] +#define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH] +#define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32 +#define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L] +#define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL] +#define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH] +#define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H] +#define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL] +#define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH] +#define RSCAN0RMID14 RSCAN0.RMID14.UINT32 +#define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L] +#define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL] +#define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH] +#define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H] +#define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL] +#define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH] +#define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32 +#define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L] +#define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL] +#define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH] +#define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H] +#define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL] +#define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH] +#define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32 +#define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L] +#define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL] +#define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH] +#define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H] +#define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL] +#define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH] +#define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32 +#define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L] +#define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL] +#define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH] +#define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H] +#define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL] +#define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH] +#define RSCAN0RMID15 RSCAN0.RMID15.UINT32 +#define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L] +#define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL] +#define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH] +#define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H] +#define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL] +#define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH] +#define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32 +#define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L] +#define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL] +#define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH] +#define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H] +#define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL] +#define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH] +#define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32 +#define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L] +#define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL] +#define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH] +#define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H] +#define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL] +#define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH] +#define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32 +#define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L] +#define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL] +#define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH] +#define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H] +#define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL] +#define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH] +#define RSCAN0RMID16 RSCAN0.RMID16.UINT32 +#define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L] +#define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL] +#define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH] +#define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H] +#define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL] +#define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH] +#define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32 +#define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L] +#define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL] +#define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH] +#define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H] +#define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL] +#define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH] +#define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32 +#define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L] +#define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL] +#define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH] +#define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H] +#define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL] +#define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH] +#define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32 +#define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L] +#define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL] +#define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH] +#define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H] +#define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL] +#define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH] +#define RSCAN0RMID17 RSCAN0.RMID17.UINT32 +#define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L] +#define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL] +#define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH] +#define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H] +#define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL] +#define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH] +#define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32 +#define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L] +#define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL] +#define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH] +#define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H] +#define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL] +#define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH] +#define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32 +#define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L] +#define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL] +#define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH] +#define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H] +#define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL] +#define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH] +#define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32 +#define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L] +#define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL] +#define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH] +#define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H] +#define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL] +#define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH] +#define RSCAN0RMID18 RSCAN0.RMID18.UINT32 +#define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L] +#define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL] +#define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH] +#define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H] +#define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL] +#define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH] +#define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32 +#define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L] +#define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL] +#define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH] +#define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H] +#define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL] +#define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH] +#define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32 +#define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L] +#define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL] +#define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH] +#define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H] +#define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL] +#define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH] +#define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32 +#define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L] +#define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL] +#define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH] +#define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H] +#define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL] +#define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH] +#define RSCAN0RMID19 RSCAN0.RMID19.UINT32 +#define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L] +#define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL] +#define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH] +#define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H] +#define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL] +#define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH] +#define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32 +#define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L] +#define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL] +#define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH] +#define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H] +#define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL] +#define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH] +#define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32 +#define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L] +#define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL] +#define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH] +#define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H] +#define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL] +#define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH] +#define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32 +#define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L] +#define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL] +#define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH] +#define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H] +#define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL] +#define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH] +#define RSCAN0RMID20 RSCAN0.RMID20.UINT32 +#define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L] +#define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL] +#define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH] +#define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H] +#define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL] +#define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH] +#define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32 +#define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L] +#define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL] +#define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH] +#define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H] +#define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL] +#define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH] +#define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32 +#define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L] +#define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL] +#define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH] +#define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H] +#define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL] +#define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH] +#define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32 +#define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L] +#define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL] +#define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH] +#define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H] +#define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL] +#define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH] +#define RSCAN0RMID21 RSCAN0.RMID21.UINT32 +#define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L] +#define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL] +#define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH] +#define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H] +#define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL] +#define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH] +#define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32 +#define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L] +#define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL] +#define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH] +#define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H] +#define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL] +#define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH] +#define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32 +#define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L] +#define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL] +#define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH] +#define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H] +#define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL] +#define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH] +#define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32 +#define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L] +#define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL] +#define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH] +#define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H] +#define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL] +#define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH] +#define RSCAN0RMID22 RSCAN0.RMID22.UINT32 +#define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L] +#define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL] +#define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH] +#define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H] +#define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL] +#define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH] +#define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32 +#define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L] +#define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL] +#define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH] +#define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H] +#define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL] +#define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH] +#define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32 +#define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L] +#define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL] +#define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH] +#define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H] +#define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL] +#define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH] +#define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32 +#define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L] +#define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL] +#define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH] +#define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H] +#define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL] +#define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH] +#define RSCAN0RMID23 RSCAN0.RMID23.UINT32 +#define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L] +#define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL] +#define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH] +#define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H] +#define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL] +#define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH] +#define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32 +#define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L] +#define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL] +#define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH] +#define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H] +#define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL] +#define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH] +#define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32 +#define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L] +#define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL] +#define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH] +#define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H] +#define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL] +#define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH] +#define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32 +#define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L] +#define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL] +#define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH] +#define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H] +#define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL] +#define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH] +#define RSCAN0RMID24 RSCAN0.RMID24.UINT32 +#define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L] +#define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL] +#define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH] +#define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H] +#define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL] +#define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH] +#define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32 +#define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L] +#define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL] +#define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH] +#define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H] +#define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL] +#define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH] +#define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32 +#define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L] +#define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL] +#define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH] +#define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H] +#define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL] +#define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH] +#define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32 +#define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L] +#define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL] +#define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH] +#define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H] +#define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL] +#define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH] +#define RSCAN0RMID25 RSCAN0.RMID25.UINT32 +#define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L] +#define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL] +#define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH] +#define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H] +#define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL] +#define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH] +#define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32 +#define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L] +#define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL] +#define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH] +#define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H] +#define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL] +#define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH] +#define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32 +#define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L] +#define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL] +#define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH] +#define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H] +#define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL] +#define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH] +#define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32 +#define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L] +#define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL] +#define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH] +#define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H] +#define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL] +#define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH] +#define RSCAN0RMID26 RSCAN0.RMID26.UINT32 +#define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L] +#define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL] +#define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH] +#define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H] +#define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL] +#define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH] +#define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32 +#define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L] +#define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL] +#define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH] +#define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H] +#define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL] +#define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH] +#define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32 +#define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L] +#define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL] +#define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH] +#define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H] +#define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL] +#define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH] +#define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32 +#define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L] +#define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL] +#define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH] +#define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H] +#define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL] +#define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH] +#define RSCAN0RMID27 RSCAN0.RMID27.UINT32 +#define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L] +#define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL] +#define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH] +#define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H] +#define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL] +#define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH] +#define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32 +#define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L] +#define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL] +#define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH] +#define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H] +#define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL] +#define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH] +#define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32 +#define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L] +#define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL] +#define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH] +#define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H] +#define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL] +#define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH] +#define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32 +#define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L] +#define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL] +#define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH] +#define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H] +#define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL] +#define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH] +#define RSCAN0RMID28 RSCAN0.RMID28.UINT32 +#define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L] +#define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL] +#define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH] +#define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H] +#define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL] +#define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH] +#define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32 +#define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L] +#define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL] +#define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH] +#define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H] +#define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL] +#define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH] +#define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32 +#define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L] +#define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL] +#define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH] +#define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H] +#define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL] +#define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH] +#define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32 +#define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L] +#define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL] +#define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH] +#define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H] +#define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL] +#define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH] +#define RSCAN0RMID29 RSCAN0.RMID29.UINT32 +#define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L] +#define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL] +#define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH] +#define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H] +#define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL] +#define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH] +#define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32 +#define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L] +#define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL] +#define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH] +#define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H] +#define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL] +#define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH] +#define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32 +#define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L] +#define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL] +#define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH] +#define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H] +#define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL] +#define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH] +#define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32 +#define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L] +#define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL] +#define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH] +#define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H] +#define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL] +#define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH] +#define RSCAN0RMID30 RSCAN0.RMID30.UINT32 +#define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L] +#define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL] +#define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH] +#define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H] +#define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL] +#define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH] +#define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32 +#define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L] +#define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL] +#define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH] +#define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H] +#define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL] +#define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH] +#define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32 +#define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L] +#define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL] +#define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH] +#define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H] +#define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL] +#define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH] +#define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32 +#define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L] +#define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL] +#define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH] +#define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H] +#define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL] +#define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH] +#define RSCAN0RMID31 RSCAN0.RMID31.UINT32 +#define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L] +#define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL] +#define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH] +#define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H] +#define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL] +#define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH] +#define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32 +#define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L] +#define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL] +#define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH] +#define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H] +#define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL] +#define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH] +#define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32 +#define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L] +#define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL] +#define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH] +#define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H] +#define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL] +#define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH] +#define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32 +#define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L] +#define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL] +#define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH] +#define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H] +#define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL] +#define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH] +#define RSCAN0RMID32 RSCAN0.RMID32.UINT32 +#define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L] +#define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL] +#define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH] +#define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H] +#define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL] +#define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH] +#define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32 +#define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L] +#define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL] +#define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH] +#define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H] +#define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL] +#define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH] +#define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32 +#define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L] +#define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL] +#define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH] +#define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H] +#define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL] +#define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH] +#define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32 +#define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L] +#define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL] +#define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH] +#define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H] +#define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL] +#define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH] +#define RSCAN0RMID33 RSCAN0.RMID33.UINT32 +#define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L] +#define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL] +#define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH] +#define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H] +#define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL] +#define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH] +#define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32 +#define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L] +#define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL] +#define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH] +#define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H] +#define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL] +#define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH] +#define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32 +#define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L] +#define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL] +#define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH] +#define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H] +#define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL] +#define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH] +#define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32 +#define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L] +#define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL] +#define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH] +#define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H] +#define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL] +#define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH] +#define RSCAN0RMID34 RSCAN0.RMID34.UINT32 +#define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L] +#define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL] +#define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH] +#define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H] +#define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL] +#define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH] +#define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32 +#define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L] +#define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL] +#define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH] +#define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H] +#define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL] +#define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH] +#define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32 +#define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L] +#define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL] +#define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH] +#define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H] +#define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL] +#define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH] +#define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32 +#define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L] +#define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL] +#define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH] +#define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H] +#define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL] +#define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH] +#define RSCAN0RMID35 RSCAN0.RMID35.UINT32 +#define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L] +#define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL] +#define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH] +#define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H] +#define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL] +#define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH] +#define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32 +#define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L] +#define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL] +#define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH] +#define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H] +#define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL] +#define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH] +#define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32 +#define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L] +#define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL] +#define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH] +#define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H] +#define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL] +#define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH] +#define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32 +#define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L] +#define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL] +#define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH] +#define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H] +#define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL] +#define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH] +#define RSCAN0RMID36 RSCAN0.RMID36.UINT32 +#define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L] +#define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL] +#define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH] +#define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H] +#define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL] +#define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH] +#define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32 +#define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L] +#define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL] +#define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH] +#define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H] +#define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL] +#define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH] +#define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32 +#define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L] +#define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL] +#define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH] +#define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H] +#define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL] +#define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH] +#define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32 +#define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L] +#define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL] +#define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH] +#define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H] +#define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL] +#define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH] +#define RSCAN0RMID37 RSCAN0.RMID37.UINT32 +#define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L] +#define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL] +#define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH] +#define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H] +#define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL] +#define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH] +#define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32 +#define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L] +#define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL] +#define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH] +#define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H] +#define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL] +#define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH] +#define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32 +#define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L] +#define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL] +#define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH] +#define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H] +#define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL] +#define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH] +#define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32 +#define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L] +#define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL] +#define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH] +#define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H] +#define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL] +#define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH] +#define RSCAN0RMID38 RSCAN0.RMID38.UINT32 +#define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L] +#define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL] +#define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH] +#define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H] +#define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL] +#define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH] +#define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32 +#define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L] +#define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL] +#define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH] +#define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H] +#define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL] +#define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH] +#define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32 +#define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L] +#define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL] +#define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH] +#define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H] +#define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL] +#define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH] +#define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32 +#define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L] +#define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL] +#define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH] +#define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H] +#define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL] +#define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH] +#define RSCAN0RMID39 RSCAN0.RMID39.UINT32 +#define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L] +#define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL] +#define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH] +#define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H] +#define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL] +#define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH] +#define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32 +#define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L] +#define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL] +#define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH] +#define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H] +#define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL] +#define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH] +#define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32 +#define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L] +#define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL] +#define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH] +#define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H] +#define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL] +#define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH] +#define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32 +#define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L] +#define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL] +#define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH] +#define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H] +#define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL] +#define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH] +#define RSCAN0RMID40 RSCAN0.RMID40.UINT32 +#define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L] +#define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL] +#define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH] +#define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H] +#define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL] +#define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH] +#define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32 +#define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L] +#define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL] +#define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH] +#define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H] +#define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL] +#define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH] +#define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32 +#define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L] +#define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL] +#define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH] +#define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H] +#define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL] +#define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH] +#define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32 +#define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L] +#define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL] +#define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH] +#define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H] +#define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL] +#define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH] +#define RSCAN0RMID41 RSCAN0.RMID41.UINT32 +#define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L] +#define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL] +#define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH] +#define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H] +#define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL] +#define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH] +#define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32 +#define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L] +#define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL] +#define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH] +#define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H] +#define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL] +#define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH] +#define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32 +#define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L] +#define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL] +#define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH] +#define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H] +#define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL] +#define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH] +#define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32 +#define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L] +#define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL] +#define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH] +#define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H] +#define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL] +#define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH] +#define RSCAN0RMID42 RSCAN0.RMID42.UINT32 +#define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L] +#define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL] +#define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH] +#define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H] +#define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL] +#define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH] +#define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32 +#define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L] +#define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL] +#define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH] +#define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H] +#define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL] +#define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH] +#define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32 +#define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L] +#define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL] +#define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH] +#define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H] +#define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL] +#define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH] +#define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32 +#define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L] +#define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL] +#define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH] +#define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H] +#define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL] +#define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH] +#define RSCAN0RMID43 RSCAN0.RMID43.UINT32 +#define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L] +#define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL] +#define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH] +#define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H] +#define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL] +#define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH] +#define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32 +#define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L] +#define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL] +#define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH] +#define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H] +#define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL] +#define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH] +#define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32 +#define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L] +#define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL] +#define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH] +#define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H] +#define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL] +#define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH] +#define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32 +#define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L] +#define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL] +#define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH] +#define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H] +#define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL] +#define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH] +#define RSCAN0RMID44 RSCAN0.RMID44.UINT32 +#define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L] +#define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL] +#define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH] +#define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H] +#define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL] +#define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH] +#define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32 +#define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L] +#define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL] +#define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH] +#define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H] +#define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL] +#define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH] +#define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32 +#define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L] +#define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL] +#define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH] +#define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H] +#define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL] +#define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH] +#define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32 +#define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L] +#define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL] +#define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH] +#define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H] +#define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL] +#define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH] +#define RSCAN0RMID45 RSCAN0.RMID45.UINT32 +#define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L] +#define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL] +#define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH] +#define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H] +#define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL] +#define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH] +#define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32 +#define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L] +#define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL] +#define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH] +#define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H] +#define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL] +#define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH] +#define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32 +#define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L] +#define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL] +#define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH] +#define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H] +#define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL] +#define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH] +#define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32 +#define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L] +#define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL] +#define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH] +#define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H] +#define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL] +#define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH] +#define RSCAN0RMID46 RSCAN0.RMID46.UINT32 +#define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L] +#define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL] +#define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH] +#define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H] +#define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL] +#define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH] +#define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32 +#define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L] +#define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL] +#define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH] +#define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H] +#define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL] +#define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH] +#define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32 +#define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L] +#define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL] +#define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH] +#define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H] +#define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL] +#define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH] +#define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32 +#define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L] +#define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL] +#define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH] +#define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H] +#define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL] +#define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH] +#define RSCAN0RMID47 RSCAN0.RMID47.UINT32 +#define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L] +#define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL] +#define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH] +#define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H] +#define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL] +#define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH] +#define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32 +#define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L] +#define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL] +#define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH] +#define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H] +#define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL] +#define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH] +#define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32 +#define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L] +#define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL] +#define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH] +#define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H] +#define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL] +#define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH] +#define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32 +#define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L] +#define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL] +#define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH] +#define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H] +#define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL] +#define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH] +#define RSCAN0RMID48 RSCAN0.RMID48.UINT32 +#define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L] +#define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL] +#define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH] +#define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H] +#define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL] +#define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH] +#define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32 +#define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L] +#define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL] +#define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH] +#define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H] +#define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL] +#define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH] +#define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32 +#define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L] +#define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL] +#define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH] +#define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H] +#define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL] +#define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH] +#define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32 +#define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L] +#define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL] +#define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH] +#define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H] +#define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL] +#define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH] +#define RSCAN0RMID49 RSCAN0.RMID49.UINT32 +#define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L] +#define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL] +#define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH] +#define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H] +#define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL] +#define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH] +#define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32 +#define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L] +#define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL] +#define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH] +#define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H] +#define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL] +#define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH] +#define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32 +#define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L] +#define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL] +#define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH] +#define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H] +#define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL] +#define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH] +#define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32 +#define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L] +#define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL] +#define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH] +#define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H] +#define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL] +#define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH] +#define RSCAN0RMID50 RSCAN0.RMID50.UINT32 +#define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L] +#define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL] +#define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH] +#define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H] +#define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL] +#define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH] +#define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32 +#define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L] +#define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL] +#define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH] +#define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H] +#define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL] +#define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH] +#define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32 +#define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L] +#define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL] +#define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH] +#define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H] +#define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL] +#define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH] +#define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32 +#define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L] +#define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL] +#define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH] +#define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H] +#define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL] +#define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH] +#define RSCAN0RMID51 RSCAN0.RMID51.UINT32 +#define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L] +#define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL] +#define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH] +#define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H] +#define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL] +#define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH] +#define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32 +#define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L] +#define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL] +#define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH] +#define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H] +#define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL] +#define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH] +#define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32 +#define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L] +#define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL] +#define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH] +#define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H] +#define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL] +#define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH] +#define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32 +#define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L] +#define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL] +#define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH] +#define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H] +#define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL] +#define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH] +#define RSCAN0RMID52 RSCAN0.RMID52.UINT32 +#define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L] +#define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL] +#define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH] +#define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H] +#define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL] +#define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH] +#define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32 +#define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L] +#define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL] +#define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH] +#define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H] +#define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL] +#define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH] +#define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32 +#define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L] +#define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL] +#define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH] +#define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H] +#define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL] +#define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH] +#define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32 +#define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L] +#define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL] +#define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH] +#define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H] +#define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL] +#define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH] +#define RSCAN0RMID53 RSCAN0.RMID53.UINT32 +#define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L] +#define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL] +#define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH] +#define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H] +#define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL] +#define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH] +#define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32 +#define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L] +#define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL] +#define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH] +#define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H] +#define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL] +#define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH] +#define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32 +#define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L] +#define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL] +#define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH] +#define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H] +#define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL] +#define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH] +#define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32 +#define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L] +#define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL] +#define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH] +#define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H] +#define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL] +#define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH] +#define RSCAN0RMID54 RSCAN0.RMID54.UINT32 +#define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L] +#define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL] +#define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH] +#define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H] +#define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL] +#define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH] +#define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32 +#define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L] +#define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL] +#define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH] +#define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H] +#define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL] +#define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH] +#define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32 +#define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L] +#define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL] +#define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH] +#define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H] +#define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL] +#define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH] +#define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32 +#define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L] +#define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL] +#define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH] +#define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H] +#define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL] +#define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH] +#define RSCAN0RMID55 RSCAN0.RMID55.UINT32 +#define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L] +#define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL] +#define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH] +#define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H] +#define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL] +#define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH] +#define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32 +#define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L] +#define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL] +#define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH] +#define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H] +#define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL] +#define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH] +#define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32 +#define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L] +#define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL] +#define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH] +#define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H] +#define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL] +#define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH] +#define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32 +#define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L] +#define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL] +#define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH] +#define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H] +#define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL] +#define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH] +#define RSCAN0RMID56 RSCAN0.RMID56.UINT32 +#define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L] +#define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL] +#define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH] +#define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H] +#define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL] +#define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH] +#define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32 +#define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L] +#define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL] +#define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH] +#define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H] +#define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL] +#define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH] +#define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32 +#define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L] +#define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL] +#define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH] +#define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H] +#define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL] +#define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH] +#define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32 +#define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L] +#define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL] +#define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH] +#define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H] +#define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL] +#define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH] +#define RSCAN0RMID57 RSCAN0.RMID57.UINT32 +#define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L] +#define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL] +#define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH] +#define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H] +#define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL] +#define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH] +#define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32 +#define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L] +#define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL] +#define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH] +#define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H] +#define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL] +#define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH] +#define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32 +#define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L] +#define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL] +#define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH] +#define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H] +#define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL] +#define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH] +#define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32 +#define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L] +#define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL] +#define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH] +#define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H] +#define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL] +#define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH] +#define RSCAN0RMID58 RSCAN0.RMID58.UINT32 +#define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L] +#define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL] +#define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH] +#define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H] +#define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL] +#define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH] +#define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32 +#define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L] +#define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL] +#define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH] +#define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H] +#define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL] +#define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH] +#define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32 +#define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L] +#define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL] +#define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH] +#define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H] +#define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL] +#define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH] +#define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32 +#define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L] +#define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL] +#define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH] +#define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H] +#define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL] +#define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH] +#define RSCAN0RMID59 RSCAN0.RMID59.UINT32 +#define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L] +#define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL] +#define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH] +#define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H] +#define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL] +#define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH] +#define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32 +#define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L] +#define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL] +#define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH] +#define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H] +#define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL] +#define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH] +#define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32 +#define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L] +#define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL] +#define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH] +#define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H] +#define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL] +#define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH] +#define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32 +#define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L] +#define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL] +#define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH] +#define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H] +#define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL] +#define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH] +#define RSCAN0RMID60 RSCAN0.RMID60.UINT32 +#define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L] +#define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL] +#define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH] +#define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H] +#define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL] +#define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH] +#define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32 +#define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L] +#define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL] +#define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH] +#define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H] +#define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL] +#define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH] +#define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32 +#define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L] +#define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL] +#define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH] +#define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H] +#define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL] +#define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH] +#define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32 +#define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L] +#define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL] +#define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH] +#define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H] +#define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL] +#define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH] +#define RSCAN0RMID61 RSCAN0.RMID61.UINT32 +#define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L] +#define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL] +#define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH] +#define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H] +#define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL] +#define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH] +#define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32 +#define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L] +#define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL] +#define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH] +#define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H] +#define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL] +#define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH] +#define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32 +#define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L] +#define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL] +#define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH] +#define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H] +#define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL] +#define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH] +#define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32 +#define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L] +#define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL] +#define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH] +#define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H] +#define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL] +#define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH] +#define RSCAN0RMID62 RSCAN0.RMID62.UINT32 +#define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L] +#define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL] +#define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH] +#define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H] +#define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL] +#define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH] +#define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32 +#define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L] +#define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL] +#define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH] +#define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H] +#define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL] +#define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH] +#define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32 +#define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L] +#define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL] +#define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH] +#define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H] +#define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL] +#define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH] +#define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32 +#define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L] +#define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL] +#define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH] +#define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H] +#define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL] +#define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH] +#define RSCAN0RMID63 RSCAN0.RMID63.UINT32 +#define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L] +#define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL] +#define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH] +#define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H] +#define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL] +#define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH] +#define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32 +#define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L] +#define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL] +#define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH] +#define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H] +#define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL] +#define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH] +#define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32 +#define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L] +#define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL] +#define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH] +#define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H] +#define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL] +#define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH] +#define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32 +#define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L] +#define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL] +#define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH] +#define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H] +#define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL] +#define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH] +#define RSCAN0RMID64 RSCAN0.RMID64.UINT32 +#define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L] +#define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL] +#define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH] +#define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H] +#define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL] +#define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH] +#define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32 +#define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L] +#define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL] +#define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH] +#define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H] +#define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL] +#define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH] +#define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32 +#define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L] +#define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL] +#define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH] +#define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H] +#define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL] +#define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH] +#define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32 +#define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L] +#define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL] +#define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH] +#define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H] +#define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL] +#define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH] +#define RSCAN0RMID65 RSCAN0.RMID65.UINT32 +#define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L] +#define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL] +#define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH] +#define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H] +#define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL] +#define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH] +#define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32 +#define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L] +#define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL] +#define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH] +#define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H] +#define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL] +#define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH] +#define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32 +#define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L] +#define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL] +#define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH] +#define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H] +#define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL] +#define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH] +#define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32 +#define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L] +#define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL] +#define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH] +#define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H] +#define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL] +#define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH] +#define RSCAN0RMID66 RSCAN0.RMID66.UINT32 +#define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L] +#define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL] +#define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH] +#define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H] +#define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL] +#define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH] +#define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32 +#define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L] +#define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL] +#define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH] +#define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H] +#define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL] +#define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH] +#define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32 +#define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L] +#define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL] +#define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH] +#define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H] +#define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL] +#define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH] +#define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32 +#define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L] +#define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL] +#define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH] +#define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H] +#define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL] +#define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH] +#define RSCAN0RMID67 RSCAN0.RMID67.UINT32 +#define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L] +#define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL] +#define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH] +#define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H] +#define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL] +#define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH] +#define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32 +#define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L] +#define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL] +#define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH] +#define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H] +#define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL] +#define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH] +#define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32 +#define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L] +#define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL] +#define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH] +#define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H] +#define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL] +#define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH] +#define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32 +#define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L] +#define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL] +#define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH] +#define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H] +#define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL] +#define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH] +#define RSCAN0RMID68 RSCAN0.RMID68.UINT32 +#define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L] +#define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL] +#define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH] +#define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H] +#define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL] +#define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH] +#define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32 +#define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L] +#define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL] +#define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH] +#define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H] +#define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL] +#define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH] +#define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32 +#define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L] +#define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL] +#define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH] +#define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H] +#define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL] +#define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH] +#define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32 +#define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L] +#define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL] +#define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH] +#define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H] +#define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL] +#define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH] +#define RSCAN0RMID69 RSCAN0.RMID69.UINT32 +#define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L] +#define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL] +#define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH] +#define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H] +#define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL] +#define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH] +#define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32 +#define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L] +#define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL] +#define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH] +#define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H] +#define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL] +#define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH] +#define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32 +#define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L] +#define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL] +#define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH] +#define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H] +#define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL] +#define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH] +#define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32 +#define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L] +#define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL] +#define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH] +#define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H] +#define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL] +#define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH] +#define RSCAN0RMID70 RSCAN0.RMID70.UINT32 +#define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L] +#define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL] +#define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH] +#define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H] +#define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL] +#define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH] +#define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32 +#define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L] +#define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL] +#define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH] +#define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H] +#define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL] +#define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH] +#define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32 +#define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L] +#define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL] +#define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH] +#define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H] +#define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL] +#define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH] +#define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32 +#define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L] +#define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL] +#define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH] +#define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H] +#define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL] +#define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH] +#define RSCAN0RMID71 RSCAN0.RMID71.UINT32 +#define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L] +#define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL] +#define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH] +#define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H] +#define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL] +#define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH] +#define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32 +#define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L] +#define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL] +#define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH] +#define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H] +#define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL] +#define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH] +#define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32 +#define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L] +#define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL] +#define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH] +#define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H] +#define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL] +#define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH] +#define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32 +#define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L] +#define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL] +#define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH] +#define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H] +#define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL] +#define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH] +#define RSCAN0RMID72 RSCAN0.RMID72.UINT32 +#define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L] +#define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL] +#define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH] +#define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H] +#define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL] +#define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH] +#define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32 +#define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L] +#define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL] +#define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH] +#define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H] +#define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL] +#define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH] +#define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32 +#define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L] +#define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL] +#define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH] +#define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H] +#define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL] +#define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH] +#define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32 +#define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L] +#define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL] +#define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH] +#define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H] +#define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL] +#define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH] +#define RSCAN0RMID73 RSCAN0.RMID73.UINT32 +#define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L] +#define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL] +#define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH] +#define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H] +#define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL] +#define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH] +#define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32 +#define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L] +#define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL] +#define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH] +#define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H] +#define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL] +#define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH] +#define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32 +#define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L] +#define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL] +#define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH] +#define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H] +#define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL] +#define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH] +#define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32 +#define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L] +#define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL] +#define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH] +#define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H] +#define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL] +#define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH] +#define RSCAN0RMID74 RSCAN0.RMID74.UINT32 +#define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L] +#define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL] +#define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH] +#define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H] +#define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL] +#define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH] +#define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32 +#define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L] +#define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL] +#define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH] +#define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H] +#define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL] +#define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH] +#define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32 +#define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L] +#define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL] +#define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH] +#define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H] +#define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL] +#define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH] +#define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32 +#define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L] +#define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL] +#define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH] +#define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H] +#define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL] +#define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH] +#define RSCAN0RMID75 RSCAN0.RMID75.UINT32 +#define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L] +#define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL] +#define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH] +#define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H] +#define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL] +#define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH] +#define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32 +#define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L] +#define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL] +#define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH] +#define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H] +#define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL] +#define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH] +#define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32 +#define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L] +#define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL] +#define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH] +#define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H] +#define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL] +#define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH] +#define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32 +#define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L] +#define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL] +#define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH] +#define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H] +#define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL] +#define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH] +#define RSCAN0RMID76 RSCAN0.RMID76.UINT32 +#define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L] +#define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL] +#define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH] +#define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H] +#define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL] +#define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH] +#define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32 +#define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L] +#define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL] +#define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH] +#define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H] +#define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL] +#define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH] +#define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32 +#define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L] +#define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL] +#define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH] +#define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H] +#define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL] +#define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH] +#define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32 +#define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L] +#define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL] +#define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH] +#define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H] +#define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL] +#define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH] +#define RSCAN0RMID77 RSCAN0.RMID77.UINT32 +#define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L] +#define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL] +#define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH] +#define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H] +#define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL] +#define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH] +#define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32 +#define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L] +#define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL] +#define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH] +#define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H] +#define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL] +#define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH] +#define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32 +#define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L] +#define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL] +#define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH] +#define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H] +#define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL] +#define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH] +#define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32 +#define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L] +#define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL] +#define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH] +#define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H] +#define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL] +#define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH] +#define RSCAN0RMID78 RSCAN0.RMID78.UINT32 +#define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L] +#define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL] +#define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH] +#define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H] +#define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL] +#define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH] +#define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32 +#define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L] +#define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL] +#define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH] +#define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H] +#define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL] +#define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH] +#define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32 +#define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L] +#define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL] +#define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH] +#define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H] +#define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL] +#define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH] +#define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32 +#define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L] +#define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL] +#define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH] +#define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H] +#define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL] +#define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH] +#define RSCAN0RMID79 RSCAN0.RMID79.UINT32 +#define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L] +#define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL] +#define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH] +#define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H] +#define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL] +#define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH] +#define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32 +#define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L] +#define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL] +#define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH] +#define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H] +#define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL] +#define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH] +#define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32 +#define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L] +#define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL] +#define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH] +#define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H] +#define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL] +#define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH] +#define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32 +#define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L] +#define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL] +#define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH] +#define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H] +#define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL] +#define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH] +#define RSCAN0RFID0 RSCAN0.RFID0.UINT32 +#define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L] +#define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL] +#define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH] +#define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H] +#define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL] +#define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH] +#define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32 +#define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L] +#define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL] +#define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH] +#define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H] +#define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL] +#define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH] +#define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32 +#define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L] +#define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL] +#define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH] +#define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H] +#define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL] +#define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH] +#define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32 +#define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L] +#define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL] +#define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH] +#define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H] +#define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL] +#define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH] +#define RSCAN0RFID1 RSCAN0.RFID1.UINT32 +#define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L] +#define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL] +#define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH] +#define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H] +#define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL] +#define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH] +#define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32 +#define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L] +#define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL] +#define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH] +#define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H] +#define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL] +#define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH] +#define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32 +#define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L] +#define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL] +#define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH] +#define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H] +#define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL] +#define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH] +#define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32 +#define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L] +#define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL] +#define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH] +#define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H] +#define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL] +#define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH] +#define RSCAN0RFID2 RSCAN0.RFID2.UINT32 +#define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L] +#define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL] +#define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH] +#define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H] +#define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL] +#define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH] +#define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32 +#define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L] +#define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL] +#define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH] +#define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H] +#define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL] +#define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH] +#define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32 +#define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L] +#define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL] +#define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH] +#define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H] +#define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL] +#define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH] +#define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32 +#define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L] +#define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL] +#define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH] +#define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H] +#define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL] +#define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH] +#define RSCAN0RFID3 RSCAN0.RFID3.UINT32 +#define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L] +#define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL] +#define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH] +#define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H] +#define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL] +#define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH] +#define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32 +#define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L] +#define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL] +#define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH] +#define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H] +#define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL] +#define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH] +#define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32 +#define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L] +#define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL] +#define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH] +#define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H] +#define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL] +#define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH] +#define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32 +#define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L] +#define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL] +#define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH] +#define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H] +#define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL] +#define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH] +#define RSCAN0RFID4 RSCAN0.RFID4.UINT32 +#define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L] +#define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL] +#define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH] +#define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H] +#define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL] +#define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH] +#define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32 +#define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L] +#define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL] +#define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH] +#define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H] +#define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL] +#define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH] +#define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32 +#define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L] +#define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL] +#define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH] +#define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H] +#define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL] +#define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH] +#define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32 +#define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L] +#define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL] +#define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH] +#define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H] +#define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL] +#define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH] +#define RSCAN0RFID5 RSCAN0.RFID5.UINT32 +#define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L] +#define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL] +#define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH] +#define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H] +#define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL] +#define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH] +#define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32 +#define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L] +#define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL] +#define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH] +#define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H] +#define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL] +#define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH] +#define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32 +#define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L] +#define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL] +#define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH] +#define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H] +#define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL] +#define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH] +#define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32 +#define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L] +#define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL] +#define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH] +#define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H] +#define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL] +#define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH] +#define RSCAN0RFID6 RSCAN0.RFID6.UINT32 +#define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L] +#define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL] +#define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH] +#define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H] +#define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL] +#define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH] +#define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32 +#define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L] +#define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL] +#define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH] +#define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H] +#define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL] +#define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH] +#define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32 +#define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L] +#define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL] +#define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH] +#define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H] +#define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL] +#define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH] +#define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32 +#define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L] +#define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL] +#define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH] +#define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H] +#define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL] +#define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH] +#define RSCAN0RFID7 RSCAN0.RFID7.UINT32 +#define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L] +#define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL] +#define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH] +#define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H] +#define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL] +#define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH] +#define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32 +#define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L] +#define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL] +#define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH] +#define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H] +#define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL] +#define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH] +#define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32 +#define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L] +#define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL] +#define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH] +#define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H] +#define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL] +#define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH] +#define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32 +#define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L] +#define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL] +#define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH] +#define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H] +#define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL] +#define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH] +#define RSCAN0CFID0 RSCAN0.CFID0.UINT32 +#define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L] +#define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL] +#define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH] +#define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H] +#define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL] +#define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH] +#define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32 +#define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L] +#define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL] +#define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH] +#define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H] +#define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL] +#define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH] +#define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32 +#define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L] +#define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL] +#define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH] +#define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H] +#define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL] +#define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH] +#define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32 +#define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L] +#define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL] +#define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH] +#define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H] +#define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL] +#define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH] +#define RSCAN0CFID1 RSCAN0.CFID1.UINT32 +#define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L] +#define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL] +#define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH] +#define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H] +#define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL] +#define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH] +#define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32 +#define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L] +#define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL] +#define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH] +#define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H] +#define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL] +#define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH] +#define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32 +#define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L] +#define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL] +#define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH] +#define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H] +#define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL] +#define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH] +#define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32 +#define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L] +#define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL] +#define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH] +#define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H] +#define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL] +#define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH] +#define RSCAN0CFID2 RSCAN0.CFID2.UINT32 +#define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L] +#define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL] +#define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH] +#define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H] +#define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL] +#define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH] +#define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32 +#define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L] +#define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL] +#define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH] +#define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H] +#define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL] +#define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH] +#define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32 +#define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L] +#define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL] +#define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH] +#define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H] +#define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL] +#define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH] +#define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32 +#define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L] +#define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL] +#define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH] +#define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H] +#define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL] +#define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH] +#define RSCAN0CFID3 RSCAN0.CFID3.UINT32 +#define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L] +#define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL] +#define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH] +#define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H] +#define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL] +#define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH] +#define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32 +#define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L] +#define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL] +#define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH] +#define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H] +#define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL] +#define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH] +#define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32 +#define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L] +#define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL] +#define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH] +#define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H] +#define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL] +#define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH] +#define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32 +#define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L] +#define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL] +#define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH] +#define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H] +#define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL] +#define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH] +#define RSCAN0CFID4 RSCAN0.CFID4.UINT32 +#define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L] +#define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL] +#define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH] +#define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H] +#define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL] +#define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH] +#define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32 +#define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L] +#define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL] +#define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH] +#define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H] +#define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL] +#define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH] +#define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32 +#define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L] +#define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL] +#define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH] +#define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H] +#define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL] +#define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH] +#define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32 +#define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L] +#define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL] +#define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH] +#define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H] +#define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL] +#define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH] +#define RSCAN0CFID5 RSCAN0.CFID5.UINT32 +#define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L] +#define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL] +#define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH] +#define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H] +#define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL] +#define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH] +#define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32 +#define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L] +#define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL] +#define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH] +#define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H] +#define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL] +#define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH] +#define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32 +#define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L] +#define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL] +#define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH] +#define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H] +#define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL] +#define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH] +#define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32 +#define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L] +#define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL] +#define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH] +#define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H] +#define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL] +#define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH] +#define RSCAN0CFID6 RSCAN0.CFID6.UINT32 +#define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L] +#define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL] +#define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH] +#define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H] +#define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL] +#define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH] +#define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32 +#define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L] +#define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL] +#define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH] +#define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H] +#define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL] +#define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH] +#define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32 +#define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L] +#define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL] +#define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH] +#define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H] +#define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL] +#define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH] +#define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32 +#define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L] +#define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL] +#define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH] +#define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H] +#define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL] +#define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH] +#define RSCAN0CFID7 RSCAN0.CFID7.UINT32 +#define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L] +#define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL] +#define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH] +#define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H] +#define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL] +#define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH] +#define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32 +#define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L] +#define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL] +#define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH] +#define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H] +#define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL] +#define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH] +#define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32 +#define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L] +#define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL] +#define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH] +#define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H] +#define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL] +#define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH] +#define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32 +#define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L] +#define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL] +#define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH] +#define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H] +#define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL] +#define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH] +#define RSCAN0CFID8 RSCAN0.CFID8.UINT32 +#define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L] +#define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL] +#define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH] +#define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H] +#define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL] +#define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH] +#define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32 +#define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L] +#define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL] +#define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH] +#define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H] +#define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL] +#define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH] +#define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32 +#define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L] +#define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL] +#define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH] +#define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H] +#define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL] +#define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH] +#define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32 +#define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L] +#define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL] +#define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH] +#define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H] +#define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL] +#define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH] +#define RSCAN0CFID9 RSCAN0.CFID9.UINT32 +#define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L] +#define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL] +#define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH] +#define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H] +#define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL] +#define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH] +#define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32 +#define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L] +#define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL] +#define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH] +#define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H] +#define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL] +#define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH] +#define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32 +#define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L] +#define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL] +#define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH] +#define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H] +#define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL] +#define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH] +#define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32 +#define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L] +#define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL] +#define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH] +#define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H] +#define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL] +#define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH] +#define RSCAN0CFID10 RSCAN0.CFID10.UINT32 +#define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L] +#define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL] +#define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH] +#define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H] +#define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL] +#define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH] +#define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32 +#define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L] +#define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL] +#define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH] +#define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H] +#define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL] +#define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH] +#define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32 +#define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L] +#define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL] +#define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH] +#define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H] +#define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL] +#define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH] +#define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32 +#define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L] +#define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL] +#define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH] +#define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H] +#define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL] +#define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH] +#define RSCAN0CFID11 RSCAN0.CFID11.UINT32 +#define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L] +#define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL] +#define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH] +#define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H] +#define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL] +#define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH] +#define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32 +#define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L] +#define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL] +#define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH] +#define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H] +#define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL] +#define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH] +#define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32 +#define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L] +#define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL] +#define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH] +#define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H] +#define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL] +#define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH] +#define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32 +#define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L] +#define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL] +#define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH] +#define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H] +#define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL] +#define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH] +#define RSCAN0CFID12 RSCAN0.CFID12.UINT32 +#define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L] +#define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL] +#define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH] +#define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H] +#define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL] +#define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH] +#define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32 +#define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L] +#define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL] +#define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH] +#define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H] +#define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL] +#define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH] +#define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32 +#define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L] +#define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL] +#define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH] +#define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H] +#define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL] +#define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH] +#define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32 +#define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L] +#define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL] +#define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH] +#define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H] +#define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL] +#define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH] +#define RSCAN0CFID13 RSCAN0.CFID13.UINT32 +#define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L] +#define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL] +#define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH] +#define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H] +#define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL] +#define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH] +#define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32 +#define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L] +#define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL] +#define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH] +#define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H] +#define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL] +#define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH] +#define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32 +#define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L] +#define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL] +#define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH] +#define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H] +#define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL] +#define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH] +#define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32 +#define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L] +#define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL] +#define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH] +#define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H] +#define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL] +#define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH] +#define RSCAN0CFID14 RSCAN0.CFID14.UINT32 +#define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L] +#define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL] +#define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH] +#define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H] +#define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL] +#define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH] +#define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32 +#define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L] +#define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL] +#define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH] +#define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H] +#define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL] +#define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH] +#define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32 +#define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L] +#define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL] +#define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH] +#define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H] +#define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL] +#define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH] +#define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32 +#define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L] +#define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL] +#define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH] +#define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H] +#define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL] +#define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH] +#define RSCAN0TMID0 RSCAN0.TMID0.UINT32 +#define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L] +#define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL] +#define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH] +#define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H] +#define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL] +#define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH] +#define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32 +#define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L] +#define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL] +#define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH] +#define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H] +#define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL] +#define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH] +#define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32 +#define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L] +#define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL] +#define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH] +#define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H] +#define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL] +#define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH] +#define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32 +#define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L] +#define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL] +#define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH] +#define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H] +#define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL] +#define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH] +#define RSCAN0TMID1 RSCAN0.TMID1.UINT32 +#define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L] +#define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL] +#define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH] +#define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H] +#define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL] +#define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH] +#define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32 +#define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L] +#define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL] +#define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH] +#define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H] +#define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL] +#define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH] +#define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32 +#define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L] +#define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL] +#define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH] +#define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H] +#define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL] +#define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH] +#define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32 +#define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L] +#define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL] +#define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH] +#define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H] +#define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL] +#define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH] +#define RSCAN0TMID2 RSCAN0.TMID2.UINT32 +#define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L] +#define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL] +#define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH] +#define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H] +#define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL] +#define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH] +#define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32 +#define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L] +#define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL] +#define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH] +#define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H] +#define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL] +#define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH] +#define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32 +#define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L] +#define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL] +#define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH] +#define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H] +#define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL] +#define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH] +#define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32 +#define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L] +#define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL] +#define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH] +#define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H] +#define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL] +#define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH] +#define RSCAN0TMID3 RSCAN0.TMID3.UINT32 +#define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L] +#define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL] +#define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH] +#define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H] +#define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL] +#define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH] +#define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32 +#define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L] +#define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL] +#define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH] +#define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H] +#define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL] +#define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH] +#define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32 +#define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L] +#define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL] +#define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH] +#define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H] +#define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL] +#define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH] +#define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32 +#define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L] +#define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL] +#define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH] +#define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H] +#define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL] +#define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH] +#define RSCAN0TMID4 RSCAN0.TMID4.UINT32 +#define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L] +#define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL] +#define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH] +#define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H] +#define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL] +#define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH] +#define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32 +#define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L] +#define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL] +#define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH] +#define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H] +#define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL] +#define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH] +#define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32 +#define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L] +#define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL] +#define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH] +#define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H] +#define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL] +#define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH] +#define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32 +#define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L] +#define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL] +#define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH] +#define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H] +#define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL] +#define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH] +#define RSCAN0TMID5 RSCAN0.TMID5.UINT32 +#define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L] +#define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL] +#define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH] +#define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H] +#define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL] +#define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH] +#define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32 +#define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L] +#define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL] +#define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH] +#define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H] +#define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL] +#define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH] +#define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32 +#define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L] +#define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL] +#define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH] +#define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H] +#define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL] +#define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH] +#define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32 +#define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L] +#define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL] +#define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH] +#define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H] +#define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL] +#define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH] +#define RSCAN0TMID6 RSCAN0.TMID6.UINT32 +#define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L] +#define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL] +#define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH] +#define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H] +#define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL] +#define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH] +#define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32 +#define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L] +#define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL] +#define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH] +#define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H] +#define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL] +#define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH] +#define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32 +#define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L] +#define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL] +#define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH] +#define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H] +#define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL] +#define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH] +#define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32 +#define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L] +#define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL] +#define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH] +#define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H] +#define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL] +#define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH] +#define RSCAN0TMID7 RSCAN0.TMID7.UINT32 +#define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L] +#define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL] +#define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH] +#define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H] +#define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL] +#define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH] +#define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32 +#define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L] +#define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL] +#define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH] +#define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H] +#define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL] +#define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH] +#define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32 +#define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L] +#define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL] +#define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH] +#define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H] +#define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL] +#define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH] +#define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32 +#define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L] +#define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL] +#define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH] +#define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H] +#define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL] +#define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH] +#define RSCAN0TMID8 RSCAN0.TMID8.UINT32 +#define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L] +#define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL] +#define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH] +#define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H] +#define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL] +#define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH] +#define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32 +#define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L] +#define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL] +#define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH] +#define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H] +#define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL] +#define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH] +#define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32 +#define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L] +#define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL] +#define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH] +#define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H] +#define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL] +#define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH] +#define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32 +#define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L] +#define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL] +#define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH] +#define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H] +#define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL] +#define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH] +#define RSCAN0TMID9 RSCAN0.TMID9.UINT32 +#define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L] +#define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL] +#define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH] +#define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H] +#define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL] +#define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH] +#define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32 +#define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L] +#define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL] +#define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH] +#define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H] +#define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL] +#define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH] +#define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32 +#define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L] +#define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL] +#define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH] +#define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H] +#define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL] +#define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH] +#define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32 +#define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L] +#define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL] +#define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH] +#define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H] +#define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL] +#define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH] +#define RSCAN0TMID10 RSCAN0.TMID10.UINT32 +#define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L] +#define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL] +#define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH] +#define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H] +#define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL] +#define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH] +#define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32 +#define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L] +#define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL] +#define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH] +#define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H] +#define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL] +#define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH] +#define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32 +#define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L] +#define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL] +#define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH] +#define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H] +#define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL] +#define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH] +#define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32 +#define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L] +#define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL] +#define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH] +#define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H] +#define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL] +#define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH] +#define RSCAN0TMID11 RSCAN0.TMID11.UINT32 +#define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L] +#define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL] +#define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH] +#define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H] +#define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL] +#define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH] +#define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32 +#define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L] +#define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL] +#define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH] +#define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H] +#define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL] +#define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH] +#define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32 +#define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L] +#define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL] +#define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH] +#define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H] +#define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL] +#define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH] +#define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32 +#define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L] +#define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL] +#define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH] +#define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H] +#define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL] +#define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH] +#define RSCAN0TMID12 RSCAN0.TMID12.UINT32 +#define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L] +#define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL] +#define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH] +#define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H] +#define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL] +#define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH] +#define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32 +#define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L] +#define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL] +#define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH] +#define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H] +#define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL] +#define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH] +#define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32 +#define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L] +#define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL] +#define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH] +#define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H] +#define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL] +#define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH] +#define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32 +#define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L] +#define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL] +#define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH] +#define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H] +#define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL] +#define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH] +#define RSCAN0TMID13 RSCAN0.TMID13.UINT32 +#define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L] +#define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL] +#define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH] +#define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H] +#define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL] +#define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH] +#define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32 +#define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L] +#define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL] +#define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH] +#define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H] +#define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL] +#define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH] +#define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32 +#define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L] +#define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL] +#define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH] +#define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H] +#define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL] +#define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH] +#define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32 +#define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L] +#define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL] +#define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH] +#define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H] +#define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL] +#define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH] +#define RSCAN0TMID14 RSCAN0.TMID14.UINT32 +#define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L] +#define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL] +#define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH] +#define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H] +#define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL] +#define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH] +#define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32 +#define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L] +#define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL] +#define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH] +#define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H] +#define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL] +#define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH] +#define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32 +#define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L] +#define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL] +#define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH] +#define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H] +#define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL] +#define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH] +#define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32 +#define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L] +#define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL] +#define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH] +#define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H] +#define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL] +#define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH] +#define RSCAN0TMID15 RSCAN0.TMID15.UINT32 +#define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L] +#define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL] +#define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH] +#define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H] +#define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL] +#define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH] +#define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32 +#define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L] +#define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL] +#define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH] +#define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H] +#define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL] +#define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH] +#define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32 +#define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L] +#define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL] +#define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH] +#define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H] +#define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL] +#define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH] +#define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32 +#define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L] +#define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL] +#define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH] +#define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H] +#define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL] +#define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH] +#define RSCAN0TMID16 RSCAN0.TMID16.UINT32 +#define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L] +#define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL] +#define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH] +#define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H] +#define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL] +#define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH] +#define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32 +#define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L] +#define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL] +#define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH] +#define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H] +#define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL] +#define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH] +#define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32 +#define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L] +#define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL] +#define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH] +#define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H] +#define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL] +#define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH] +#define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32 +#define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L] +#define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL] +#define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH] +#define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H] +#define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL] +#define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH] +#define RSCAN0TMID17 RSCAN0.TMID17.UINT32 +#define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L] +#define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL] +#define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH] +#define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H] +#define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL] +#define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH] +#define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32 +#define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L] +#define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL] +#define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH] +#define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H] +#define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL] +#define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH] +#define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32 +#define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L] +#define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL] +#define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH] +#define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H] +#define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL] +#define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH] +#define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32 +#define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L] +#define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL] +#define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH] +#define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H] +#define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL] +#define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH] +#define RSCAN0TMID18 RSCAN0.TMID18.UINT32 +#define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L] +#define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL] +#define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH] +#define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H] +#define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL] +#define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH] +#define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32 +#define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L] +#define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL] +#define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH] +#define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H] +#define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL] +#define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH] +#define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32 +#define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L] +#define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL] +#define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH] +#define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H] +#define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL] +#define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH] +#define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32 +#define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L] +#define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL] +#define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH] +#define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H] +#define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL] +#define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH] +#define RSCAN0TMID19 RSCAN0.TMID19.UINT32 +#define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L] +#define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL] +#define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH] +#define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H] +#define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL] +#define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH] +#define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32 +#define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L] +#define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL] +#define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH] +#define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H] +#define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL] +#define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH] +#define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32 +#define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L] +#define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL] +#define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH] +#define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H] +#define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL] +#define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH] +#define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32 +#define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L] +#define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL] +#define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH] +#define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H] +#define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL] +#define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH] +#define RSCAN0TMID20 RSCAN0.TMID20.UINT32 +#define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L] +#define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL] +#define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH] +#define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H] +#define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL] +#define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH] +#define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32 +#define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L] +#define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL] +#define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH] +#define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H] +#define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL] +#define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH] +#define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32 +#define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L] +#define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL] +#define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH] +#define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H] +#define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL] +#define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH] +#define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32 +#define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L] +#define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL] +#define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH] +#define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H] +#define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL] +#define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH] +#define RSCAN0TMID21 RSCAN0.TMID21.UINT32 +#define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L] +#define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL] +#define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH] +#define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H] +#define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL] +#define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH] +#define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32 +#define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L] +#define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL] +#define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH] +#define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H] +#define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL] +#define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH] +#define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32 +#define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L] +#define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL] +#define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH] +#define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H] +#define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL] +#define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH] +#define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32 +#define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L] +#define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL] +#define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH] +#define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H] +#define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL] +#define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH] +#define RSCAN0TMID22 RSCAN0.TMID22.UINT32 +#define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L] +#define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL] +#define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH] +#define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H] +#define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL] +#define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH] +#define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32 +#define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L] +#define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL] +#define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH] +#define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H] +#define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL] +#define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH] +#define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32 +#define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L] +#define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL] +#define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH] +#define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H] +#define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL] +#define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH] +#define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32 +#define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L] +#define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL] +#define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH] +#define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H] +#define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL] +#define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH] +#define RSCAN0TMID23 RSCAN0.TMID23.UINT32 +#define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L] +#define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL] +#define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH] +#define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H] +#define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL] +#define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH] +#define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32 +#define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L] +#define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL] +#define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH] +#define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H] +#define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL] +#define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH] +#define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32 +#define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L] +#define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL] +#define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH] +#define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H] +#define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL] +#define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH] +#define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32 +#define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L] +#define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL] +#define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH] +#define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H] +#define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL] +#define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH] +#define RSCAN0TMID24 RSCAN0.TMID24.UINT32 +#define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L] +#define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL] +#define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH] +#define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H] +#define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL] +#define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH] +#define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32 +#define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L] +#define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL] +#define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH] +#define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H] +#define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL] +#define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH] +#define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32 +#define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L] +#define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL] +#define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH] +#define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H] +#define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL] +#define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH] +#define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32 +#define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L] +#define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL] +#define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH] +#define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H] +#define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL] +#define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH] +#define RSCAN0TMID25 RSCAN0.TMID25.UINT32 +#define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L] +#define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL] +#define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH] +#define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H] +#define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL] +#define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH] +#define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32 +#define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L] +#define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL] +#define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH] +#define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H] +#define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL] +#define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH] +#define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32 +#define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L] +#define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL] +#define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH] +#define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H] +#define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL] +#define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH] +#define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32 +#define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L] +#define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL] +#define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH] +#define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H] +#define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL] +#define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH] +#define RSCAN0TMID26 RSCAN0.TMID26.UINT32 +#define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L] +#define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL] +#define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH] +#define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H] +#define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL] +#define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH] +#define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32 +#define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L] +#define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL] +#define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH] +#define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H] +#define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL] +#define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH] +#define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32 +#define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L] +#define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL] +#define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH] +#define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H] +#define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL] +#define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH] +#define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32 +#define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L] +#define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL] +#define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH] +#define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H] +#define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL] +#define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH] +#define RSCAN0TMID27 RSCAN0.TMID27.UINT32 +#define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L] +#define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL] +#define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH] +#define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H] +#define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL] +#define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH] +#define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32 +#define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L] +#define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL] +#define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH] +#define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H] +#define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL] +#define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH] +#define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32 +#define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L] +#define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL] +#define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH] +#define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H] +#define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL] +#define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH] +#define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32 +#define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L] +#define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL] +#define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH] +#define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H] +#define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL] +#define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH] +#define RSCAN0TMID28 RSCAN0.TMID28.UINT32 +#define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L] +#define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL] +#define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH] +#define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H] +#define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL] +#define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH] +#define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32 +#define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L] +#define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL] +#define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH] +#define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H] +#define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL] +#define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH] +#define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32 +#define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L] +#define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL] +#define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH] +#define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H] +#define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL] +#define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH] +#define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32 +#define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L] +#define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL] +#define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH] +#define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H] +#define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL] +#define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH] +#define RSCAN0TMID29 RSCAN0.TMID29.UINT32 +#define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L] +#define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL] +#define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH] +#define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H] +#define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL] +#define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH] +#define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32 +#define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L] +#define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL] +#define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH] +#define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H] +#define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL] +#define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH] +#define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32 +#define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L] +#define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL] +#define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH] +#define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H] +#define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL] +#define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH] +#define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32 +#define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L] +#define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL] +#define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH] +#define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H] +#define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL] +#define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH] +#define RSCAN0TMID30 RSCAN0.TMID30.UINT32 +#define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L] +#define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL] +#define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH] +#define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H] +#define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL] +#define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH] +#define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32 +#define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L] +#define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL] +#define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH] +#define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H] +#define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL] +#define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH] +#define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32 +#define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L] +#define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL] +#define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH] +#define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H] +#define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL] +#define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH] +#define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32 +#define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L] +#define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL] +#define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH] +#define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H] +#define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL] +#define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH] +#define RSCAN0TMID31 RSCAN0.TMID31.UINT32 +#define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L] +#define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL] +#define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH] +#define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H] +#define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL] +#define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH] +#define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32 +#define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L] +#define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL] +#define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH] +#define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H] +#define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL] +#define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH] +#define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32 +#define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L] +#define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL] +#define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH] +#define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H] +#define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL] +#define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH] +#define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32 +#define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L] +#define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL] +#define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH] +#define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H] +#define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL] +#define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH] +#define RSCAN0TMID32 RSCAN0.TMID32.UINT32 +#define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L] +#define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL] +#define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH] +#define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H] +#define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL] +#define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH] +#define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32 +#define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L] +#define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL] +#define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH] +#define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H] +#define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL] +#define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH] +#define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32 +#define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L] +#define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL] +#define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH] +#define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H] +#define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL] +#define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH] +#define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32 +#define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L] +#define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL] +#define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH] +#define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H] +#define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL] +#define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH] +#define RSCAN0TMID33 RSCAN0.TMID33.UINT32 +#define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L] +#define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL] +#define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH] +#define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H] +#define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL] +#define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH] +#define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32 +#define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L] +#define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL] +#define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH] +#define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H] +#define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL] +#define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH] +#define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32 +#define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L] +#define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL] +#define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH] +#define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H] +#define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL] +#define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH] +#define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32 +#define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L] +#define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL] +#define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH] +#define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H] +#define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL] +#define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH] +#define RSCAN0TMID34 RSCAN0.TMID34.UINT32 +#define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L] +#define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL] +#define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH] +#define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H] +#define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL] +#define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH] +#define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32 +#define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L] +#define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL] +#define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH] +#define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H] +#define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL] +#define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH] +#define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32 +#define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L] +#define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL] +#define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH] +#define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H] +#define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL] +#define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH] +#define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32 +#define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L] +#define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL] +#define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH] +#define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H] +#define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL] +#define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH] +#define RSCAN0TMID35 RSCAN0.TMID35.UINT32 +#define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L] +#define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL] +#define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH] +#define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H] +#define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL] +#define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH] +#define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32 +#define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L] +#define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL] +#define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH] +#define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H] +#define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL] +#define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH] +#define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32 +#define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L] +#define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL] +#define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH] +#define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H] +#define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL] +#define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH] +#define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32 +#define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L] +#define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL] +#define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH] +#define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H] +#define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL] +#define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH] +#define RSCAN0TMID36 RSCAN0.TMID36.UINT32 +#define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L] +#define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL] +#define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH] +#define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H] +#define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL] +#define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH] +#define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32 +#define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L] +#define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL] +#define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH] +#define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H] +#define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL] +#define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH] +#define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32 +#define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L] +#define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL] +#define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH] +#define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H] +#define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL] +#define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH] +#define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32 +#define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L] +#define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL] +#define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH] +#define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H] +#define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL] +#define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH] +#define RSCAN0TMID37 RSCAN0.TMID37.UINT32 +#define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L] +#define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL] +#define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH] +#define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H] +#define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL] +#define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH] +#define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32 +#define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L] +#define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL] +#define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH] +#define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H] +#define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL] +#define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH] +#define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32 +#define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L] +#define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL] +#define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH] +#define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H] +#define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL] +#define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH] +#define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32 +#define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L] +#define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL] +#define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH] +#define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H] +#define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL] +#define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH] +#define RSCAN0TMID38 RSCAN0.TMID38.UINT32 +#define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L] +#define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL] +#define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH] +#define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H] +#define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL] +#define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH] +#define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32 +#define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L] +#define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL] +#define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH] +#define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H] +#define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL] +#define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH] +#define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32 +#define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L] +#define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL] +#define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH] +#define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H] +#define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL] +#define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH] +#define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32 +#define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L] +#define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL] +#define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH] +#define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H] +#define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL] +#define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH] +#define RSCAN0TMID39 RSCAN0.TMID39.UINT32 +#define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L] +#define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL] +#define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH] +#define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H] +#define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL] +#define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH] +#define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32 +#define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L] +#define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL] +#define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH] +#define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H] +#define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL] +#define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH] +#define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32 +#define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L] +#define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL] +#define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH] +#define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H] +#define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL] +#define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH] +#define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32 +#define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L] +#define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL] +#define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH] +#define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H] +#define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL] +#define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH] +#define RSCAN0TMID40 RSCAN0.TMID40.UINT32 +#define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L] +#define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL] +#define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH] +#define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H] +#define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL] +#define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH] +#define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32 +#define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L] +#define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL] +#define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH] +#define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H] +#define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL] +#define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH] +#define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32 +#define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L] +#define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL] +#define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH] +#define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H] +#define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL] +#define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH] +#define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32 +#define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L] +#define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL] +#define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH] +#define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H] +#define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL] +#define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH] +#define RSCAN0TMID41 RSCAN0.TMID41.UINT32 +#define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L] +#define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL] +#define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH] +#define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H] +#define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL] +#define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH] +#define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32 +#define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L] +#define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL] +#define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH] +#define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H] +#define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL] +#define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH] +#define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32 +#define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L] +#define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL] +#define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH] +#define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H] +#define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL] +#define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH] +#define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32 +#define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L] +#define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL] +#define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH] +#define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H] +#define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL] +#define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH] +#define RSCAN0TMID42 RSCAN0.TMID42.UINT32 +#define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L] +#define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL] +#define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH] +#define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H] +#define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL] +#define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH] +#define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32 +#define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L] +#define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL] +#define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH] +#define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H] +#define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL] +#define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH] +#define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32 +#define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L] +#define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL] +#define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH] +#define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H] +#define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL] +#define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH] +#define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32 +#define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L] +#define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL] +#define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH] +#define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H] +#define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL] +#define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH] +#define RSCAN0TMID43 RSCAN0.TMID43.UINT32 +#define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L] +#define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL] +#define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH] +#define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H] +#define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL] +#define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH] +#define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32 +#define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L] +#define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL] +#define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH] +#define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H] +#define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL] +#define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH] +#define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32 +#define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L] +#define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL] +#define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH] +#define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H] +#define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL] +#define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH] +#define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32 +#define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L] +#define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL] +#define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH] +#define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H] +#define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL] +#define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH] +#define RSCAN0TMID44 RSCAN0.TMID44.UINT32 +#define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L] +#define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL] +#define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH] +#define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H] +#define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL] +#define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH] +#define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32 +#define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L] +#define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL] +#define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH] +#define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H] +#define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL] +#define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH] +#define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32 +#define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L] +#define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL] +#define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH] +#define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H] +#define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL] +#define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH] +#define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32 +#define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L] +#define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL] +#define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH] +#define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H] +#define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL] +#define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH] +#define RSCAN0TMID45 RSCAN0.TMID45.UINT32 +#define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L] +#define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL] +#define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH] +#define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H] +#define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL] +#define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH] +#define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32 +#define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L] +#define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL] +#define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH] +#define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H] +#define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL] +#define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH] +#define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32 +#define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L] +#define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL] +#define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH] +#define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H] +#define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL] +#define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH] +#define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32 +#define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L] +#define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL] +#define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH] +#define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H] +#define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL] +#define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH] +#define RSCAN0TMID46 RSCAN0.TMID46.UINT32 +#define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L] +#define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL] +#define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH] +#define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H] +#define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL] +#define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH] +#define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32 +#define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L] +#define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL] +#define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH] +#define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H] +#define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL] +#define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH] +#define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32 +#define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L] +#define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL] +#define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH] +#define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H] +#define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL] +#define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH] +#define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32 +#define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L] +#define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL] +#define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH] +#define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H] +#define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL] +#define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH] +#define RSCAN0TMID47 RSCAN0.TMID47.UINT32 +#define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L] +#define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL] +#define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH] +#define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H] +#define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL] +#define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH] +#define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32 +#define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L] +#define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL] +#define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH] +#define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H] +#define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL] +#define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH] +#define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32 +#define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L] +#define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL] +#define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH] +#define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H] +#define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL] +#define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH] +#define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32 +#define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L] +#define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL] +#define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH] +#define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H] +#define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL] +#define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH] +#define RSCAN0TMID48 RSCAN0.TMID48.UINT32 +#define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L] +#define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL] +#define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH] +#define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H] +#define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL] +#define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH] +#define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32 +#define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L] +#define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL] +#define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH] +#define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H] +#define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL] +#define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH] +#define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32 +#define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L] +#define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL] +#define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH] +#define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H] +#define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL] +#define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH] +#define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32 +#define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L] +#define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL] +#define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH] +#define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H] +#define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL] +#define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH] +#define RSCAN0TMID49 RSCAN0.TMID49.UINT32 +#define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L] +#define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL] +#define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH] +#define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H] +#define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL] +#define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH] +#define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32 +#define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L] +#define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL] +#define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH] +#define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H] +#define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL] +#define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH] +#define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32 +#define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L] +#define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL] +#define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH] +#define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H] +#define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL] +#define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH] +#define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32 +#define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L] +#define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL] +#define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH] +#define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H] +#define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL] +#define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH] +#define RSCAN0TMID50 RSCAN0.TMID50.UINT32 +#define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L] +#define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL] +#define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH] +#define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H] +#define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL] +#define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH] +#define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32 +#define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L] +#define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL] +#define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH] +#define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H] +#define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL] +#define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH] +#define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32 +#define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L] +#define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL] +#define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH] +#define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H] +#define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL] +#define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH] +#define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32 +#define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L] +#define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL] +#define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH] +#define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H] +#define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL] +#define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH] +#define RSCAN0TMID51 RSCAN0.TMID51.UINT32 +#define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L] +#define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL] +#define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH] +#define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H] +#define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL] +#define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH] +#define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32 +#define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L] +#define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL] +#define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH] +#define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H] +#define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL] +#define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH] +#define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32 +#define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L] +#define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL] +#define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH] +#define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H] +#define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL] +#define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH] +#define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32 +#define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L] +#define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL] +#define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH] +#define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H] +#define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL] +#define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH] +#define RSCAN0TMID52 RSCAN0.TMID52.UINT32 +#define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L] +#define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL] +#define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH] +#define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H] +#define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL] +#define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH] +#define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32 +#define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L] +#define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL] +#define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH] +#define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H] +#define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL] +#define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH] +#define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32 +#define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L] +#define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL] +#define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH] +#define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H] +#define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL] +#define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH] +#define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32 +#define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L] +#define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL] +#define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH] +#define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H] +#define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL] +#define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH] +#define RSCAN0TMID53 RSCAN0.TMID53.UINT32 +#define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L] +#define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL] +#define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH] +#define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H] +#define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL] +#define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH] +#define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32 +#define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L] +#define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL] +#define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH] +#define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H] +#define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL] +#define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH] +#define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32 +#define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L] +#define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL] +#define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH] +#define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H] +#define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL] +#define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH] +#define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32 +#define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L] +#define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL] +#define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH] +#define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H] +#define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL] +#define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH] +#define RSCAN0TMID54 RSCAN0.TMID54.UINT32 +#define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L] +#define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL] +#define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH] +#define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H] +#define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL] +#define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH] +#define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32 +#define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L] +#define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL] +#define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH] +#define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H] +#define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL] +#define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH] +#define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32 +#define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L] +#define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL] +#define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH] +#define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H] +#define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL] +#define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH] +#define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32 +#define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L] +#define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL] +#define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH] +#define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H] +#define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL] +#define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH] +#define RSCAN0TMID55 RSCAN0.TMID55.UINT32 +#define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L] +#define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL] +#define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH] +#define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H] +#define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL] +#define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH] +#define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32 +#define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L] +#define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL] +#define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH] +#define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H] +#define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL] +#define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH] +#define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32 +#define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L] +#define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL] +#define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH] +#define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H] +#define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL] +#define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH] +#define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32 +#define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L] +#define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL] +#define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH] +#define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H] +#define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL] +#define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH] +#define RSCAN0TMID56 RSCAN0.TMID56.UINT32 +#define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L] +#define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL] +#define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH] +#define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H] +#define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL] +#define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH] +#define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32 +#define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L] +#define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL] +#define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH] +#define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H] +#define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL] +#define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH] +#define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32 +#define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L] +#define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL] +#define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH] +#define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H] +#define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL] +#define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH] +#define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32 +#define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L] +#define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL] +#define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH] +#define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H] +#define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL] +#define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH] +#define RSCAN0TMID57 RSCAN0.TMID57.UINT32 +#define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L] +#define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL] +#define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH] +#define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H] +#define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL] +#define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH] +#define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32 +#define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L] +#define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL] +#define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH] +#define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H] +#define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL] +#define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH] +#define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32 +#define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L] +#define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL] +#define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH] +#define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H] +#define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL] +#define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH] +#define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32 +#define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L] +#define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL] +#define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH] +#define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H] +#define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL] +#define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH] +#define RSCAN0TMID58 RSCAN0.TMID58.UINT32 +#define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L] +#define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL] +#define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH] +#define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H] +#define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL] +#define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH] +#define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32 +#define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L] +#define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL] +#define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH] +#define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H] +#define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL] +#define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH] +#define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32 +#define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L] +#define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL] +#define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH] +#define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H] +#define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL] +#define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH] +#define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32 +#define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L] +#define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL] +#define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH] +#define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H] +#define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL] +#define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH] +#define RSCAN0TMID59 RSCAN0.TMID59.UINT32 +#define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L] +#define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL] +#define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH] +#define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H] +#define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL] +#define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH] +#define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32 +#define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L] +#define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL] +#define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH] +#define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H] +#define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL] +#define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH] +#define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32 +#define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L] +#define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL] +#define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH] +#define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H] +#define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL] +#define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH] +#define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32 +#define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L] +#define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL] +#define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH] +#define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H] +#define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL] +#define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH] +#define RSCAN0TMID60 RSCAN0.TMID60.UINT32 +#define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L] +#define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL] +#define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH] +#define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H] +#define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL] +#define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH] +#define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32 +#define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L] +#define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL] +#define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH] +#define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H] +#define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL] +#define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH] +#define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32 +#define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L] +#define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL] +#define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH] +#define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H] +#define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL] +#define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH] +#define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32 +#define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L] +#define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL] +#define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH] +#define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H] +#define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL] +#define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH] +#define RSCAN0TMID61 RSCAN0.TMID61.UINT32 +#define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L] +#define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL] +#define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH] +#define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H] +#define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL] +#define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH] +#define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32 +#define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L] +#define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL] +#define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH] +#define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H] +#define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL] +#define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH] +#define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32 +#define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L] +#define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL] +#define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH] +#define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H] +#define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL] +#define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH] +#define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32 +#define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L] +#define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL] +#define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH] +#define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H] +#define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL] +#define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH] +#define RSCAN0TMID62 RSCAN0.TMID62.UINT32 +#define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L] +#define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL] +#define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH] +#define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H] +#define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL] +#define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH] +#define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32 +#define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L] +#define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL] +#define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH] +#define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H] +#define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL] +#define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH] +#define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32 +#define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L] +#define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL] +#define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH] +#define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H] +#define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL] +#define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH] +#define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32 +#define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L] +#define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL] +#define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH] +#define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H] +#define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL] +#define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH] +#define RSCAN0TMID63 RSCAN0.TMID63.UINT32 +#define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L] +#define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL] +#define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH] +#define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H] +#define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL] +#define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH] +#define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32 +#define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L] +#define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL] +#define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH] +#define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H] +#define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL] +#define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH] +#define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32 +#define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L] +#define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL] +#define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH] +#define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H] +#define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL] +#define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH] +#define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32 +#define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L] +#define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL] +#define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH] +#define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H] +#define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL] +#define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH] +#define RSCAN0TMID64 RSCAN0.TMID64.UINT32 +#define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L] +#define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL] +#define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH] +#define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H] +#define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL] +#define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH] +#define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32 +#define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L] +#define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL] +#define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH] +#define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H] +#define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL] +#define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH] +#define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32 +#define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L] +#define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL] +#define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH] +#define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H] +#define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL] +#define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH] +#define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32 +#define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L] +#define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL] +#define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH] +#define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H] +#define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL] +#define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH] +#define RSCAN0TMID65 RSCAN0.TMID65.UINT32 +#define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L] +#define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL] +#define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH] +#define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H] +#define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL] +#define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH] +#define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32 +#define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L] +#define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL] +#define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH] +#define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H] +#define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL] +#define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH] +#define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32 +#define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L] +#define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL] +#define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH] +#define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H] +#define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL] +#define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH] +#define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32 +#define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L] +#define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL] +#define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH] +#define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H] +#define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL] +#define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH] +#define RSCAN0TMID66 RSCAN0.TMID66.UINT32 +#define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L] +#define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL] +#define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH] +#define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H] +#define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL] +#define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH] +#define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32 +#define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L] +#define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL] +#define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH] +#define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H] +#define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL] +#define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH] +#define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32 +#define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L] +#define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL] +#define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH] +#define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H] +#define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL] +#define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH] +#define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32 +#define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L] +#define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL] +#define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH] +#define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H] +#define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL] +#define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH] +#define RSCAN0TMID67 RSCAN0.TMID67.UINT32 +#define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L] +#define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL] +#define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH] +#define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H] +#define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL] +#define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH] +#define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32 +#define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L] +#define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL] +#define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH] +#define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H] +#define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL] +#define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH] +#define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32 +#define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L] +#define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL] +#define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH] +#define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H] +#define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL] +#define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH] +#define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32 +#define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L] +#define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL] +#define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH] +#define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H] +#define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL] +#define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH] +#define RSCAN0TMID68 RSCAN0.TMID68.UINT32 +#define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L] +#define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL] +#define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH] +#define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H] +#define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL] +#define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH] +#define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32 +#define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L] +#define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL] +#define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH] +#define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H] +#define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL] +#define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH] +#define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32 +#define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L] +#define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL] +#define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH] +#define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H] +#define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL] +#define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH] +#define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32 +#define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L] +#define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL] +#define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH] +#define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H] +#define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL] +#define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH] +#define RSCAN0TMID69 RSCAN0.TMID69.UINT32 +#define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L] +#define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL] +#define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH] +#define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H] +#define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL] +#define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH] +#define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32 +#define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L] +#define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL] +#define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH] +#define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H] +#define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL] +#define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH] +#define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32 +#define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L] +#define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL] +#define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH] +#define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H] +#define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL] +#define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH] +#define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32 +#define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L] +#define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL] +#define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH] +#define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H] +#define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL] +#define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH] +#define RSCAN0TMID70 RSCAN0.TMID70.UINT32 +#define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L] +#define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL] +#define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH] +#define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H] +#define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL] +#define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH] +#define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32 +#define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L] +#define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL] +#define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH] +#define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H] +#define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL] +#define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH] +#define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32 +#define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L] +#define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL] +#define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH] +#define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H] +#define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL] +#define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH] +#define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32 +#define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L] +#define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL] +#define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH] +#define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H] +#define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL] +#define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH] +#define RSCAN0TMID71 RSCAN0.TMID71.UINT32 +#define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L] +#define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL] +#define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH] +#define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H] +#define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL] +#define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH] +#define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32 +#define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L] +#define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL] +#define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH] +#define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H] +#define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL] +#define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH] +#define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32 +#define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L] +#define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL] +#define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH] +#define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H] +#define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL] +#define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH] +#define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32 +#define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L] +#define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL] +#define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH] +#define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H] +#define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL] +#define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH] +#define RSCAN0TMID72 RSCAN0.TMID72.UINT32 +#define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L] +#define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL] +#define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH] +#define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H] +#define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL] +#define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH] +#define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32 +#define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L] +#define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL] +#define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH] +#define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H] +#define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL] +#define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH] +#define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32 +#define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L] +#define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL] +#define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH] +#define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H] +#define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL] +#define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH] +#define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32 +#define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L] +#define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL] +#define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH] +#define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H] +#define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL] +#define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH] +#define RSCAN0TMID73 RSCAN0.TMID73.UINT32 +#define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L] +#define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL] +#define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH] +#define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H] +#define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL] +#define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH] +#define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32 +#define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L] +#define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL] +#define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH] +#define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H] +#define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL] +#define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH] +#define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32 +#define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L] +#define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL] +#define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH] +#define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H] +#define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL] +#define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH] +#define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32 +#define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L] +#define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL] +#define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH] +#define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H] +#define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL] +#define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH] +#define RSCAN0TMID74 RSCAN0.TMID74.UINT32 +#define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L] +#define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL] +#define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH] +#define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H] +#define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL] +#define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH] +#define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32 +#define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L] +#define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL] +#define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH] +#define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H] +#define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL] +#define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH] +#define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32 +#define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L] +#define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL] +#define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH] +#define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H] +#define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL] +#define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH] +#define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32 +#define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L] +#define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL] +#define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH] +#define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H] +#define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL] +#define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH] +#define RSCAN0TMID75 RSCAN0.TMID75.UINT32 +#define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L] +#define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL] +#define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH] +#define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H] +#define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL] +#define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH] +#define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32 +#define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L] +#define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL] +#define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH] +#define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H] +#define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL] +#define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH] +#define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32 +#define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L] +#define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL] +#define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH] +#define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H] +#define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL] +#define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH] +#define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32 +#define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L] +#define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL] +#define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH] +#define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H] +#define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL] +#define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH] +#define RSCAN0TMID76 RSCAN0.TMID76.UINT32 +#define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L] +#define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL] +#define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH] +#define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H] +#define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL] +#define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH] +#define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32 +#define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L] +#define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL] +#define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH] +#define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H] +#define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL] +#define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH] +#define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32 +#define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L] +#define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL] +#define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH] +#define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H] +#define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL] +#define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH] +#define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32 +#define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L] +#define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL] +#define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH] +#define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H] +#define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL] +#define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH] +#define RSCAN0TMID77 RSCAN0.TMID77.UINT32 +#define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L] +#define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL] +#define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH] +#define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H] +#define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL] +#define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH] +#define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32 +#define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L] +#define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL] +#define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH] +#define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H] +#define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL] +#define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH] +#define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32 +#define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L] +#define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL] +#define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH] +#define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H] +#define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL] +#define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH] +#define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32 +#define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L] +#define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL] +#define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH] +#define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H] +#define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL] +#define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH] +#define RSCAN0TMID78 RSCAN0.TMID78.UINT32 +#define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L] +#define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL] +#define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH] +#define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H] +#define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL] +#define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH] +#define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32 +#define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L] +#define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL] +#define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH] +#define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H] +#define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL] +#define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH] +#define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32 +#define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L] +#define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL] +#define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH] +#define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H] +#define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL] +#define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH] +#define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32 +#define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L] +#define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL] +#define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH] +#define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H] +#define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL] +#define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH] +#define RSCAN0TMID79 RSCAN0.TMID79.UINT32 +#define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L] +#define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL] +#define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH] +#define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H] +#define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL] +#define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH] +#define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32 +#define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L] +#define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL] +#define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH] +#define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H] +#define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL] +#define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH] +#define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32 +#define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L] +#define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL] +#define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH] +#define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H] +#define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL] +#define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH] +#define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32 +#define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L] +#define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL] +#define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH] +#define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H] +#define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL] +#define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH] +#define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32 +#define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L] +#define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL] +#define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH] +#define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H] +#define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL] +#define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH] +#define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32 +#define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L] +#define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL] +#define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH] +#define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H] +#define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL] +#define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH] +#define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32 +#define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L] +#define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL] +#define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH] +#define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H] +#define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL] +#define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH] +#define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32 +#define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L] +#define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL] +#define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH] +#define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H] +#define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL] +#define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH] +#define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32 +#define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L] +#define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL] +#define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH] +#define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H] +#define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL] +#define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH] +/* <-SEC M1.10.1 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rspi_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rspi_iodefine.h new file mode 100644 index 0000000000..0fbd14e702 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rspi_iodefine.h @@ -0,0 +1,204 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rspi_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef RSPI_IODEFINE_H +#define RSPI_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +#include "reg32_t.h" + +struct st_rspi +{ /* RSPI */ + volatile uint8_t SPCR; /* SPCR */ + volatile uint8_t SSLP; /* SSLP */ + volatile uint8_t SPPCR; /* SPPCR */ + volatile uint8_t SPSR; /* SPSR */ + union reg32_t SPDR; /* SPDR */ + + volatile uint8_t SPSCR; /* SPSCR */ + volatile uint8_t SPSSR; /* SPSSR */ + volatile uint8_t SPBR; /* SPBR */ + volatile uint8_t SPDCR; /* SPDCR */ + volatile uint8_t SPCKD; /* SPCKD */ + volatile uint8_t SSLND; /* SSLND */ + volatile uint8_t SPND; /* SPND */ + volatile uint8_t dummy1[1]; /* */ +#define SPCMD_COUNT 4 + volatile uint16_t SPCMD0; /* SPCMD0 */ + volatile uint16_t SPCMD1; /* SPCMD1 */ + volatile uint16_t SPCMD2; /* SPCMD2 */ + volatile uint16_t SPCMD3; /* SPCMD3 */ + volatile uint8_t dummy2[8]; /* */ + volatile uint8_t SPBFCR; /* SPBFCR */ + volatile uint8_t dummy3[1]; /* */ + volatile uint16_t SPBFDR; /* SPBFDR */ +}; + + +#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ +#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ +#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ +#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ +#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ + + +/* Start of channnel array defines of RSPI */ + +/* Channnel array defines of RSPI */ +/*(Sample) value = RSPI[ channel ]->SPCR; */ +#define RSPI_COUNT 5 +#define RSPI_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of RSPI */ + + +#define SPCR_0 RSPI0.SPCR +#define SSLP_0 RSPI0.SSLP +#define SPPCR_0 RSPI0.SPPCR +#define SPSR_0 RSPI0.SPSR +#define SPDR_0 RSPI0.SPDR.UINT32 +#define SPDR_0L RSPI0.SPDR.UINT16[L] +#define SPDR_0H RSPI0.SPDR.UINT16[H] +#define SPDR_0LL RSPI0.SPDR.UINT8[LL] +#define SPDR_0LH RSPI0.SPDR.UINT8[LH] +#define SPDR_0HL RSPI0.SPDR.UINT8[HL] +#define SPDR_0HH RSPI0.SPDR.UINT8[HH] +#define SPSCR_0 RSPI0.SPSCR +#define SPSSR_0 RSPI0.SPSSR +#define SPBR_0 RSPI0.SPBR +#define SPDCR_0 RSPI0.SPDCR +#define SPCKD_0 RSPI0.SPCKD +#define SSLND_0 RSPI0.SSLND +#define SPND_0 RSPI0.SPND +#define SPCMD0_0 RSPI0.SPCMD0 +#define SPCMD1_0 RSPI0.SPCMD1 +#define SPCMD2_0 RSPI0.SPCMD2 +#define SPCMD3_0 RSPI0.SPCMD3 +#define SPBFCR_0 RSPI0.SPBFCR +#define SPBFDR_0 RSPI0.SPBFDR +#define SPCR_1 RSPI1.SPCR +#define SSLP_1 RSPI1.SSLP +#define SPPCR_1 RSPI1.SPPCR +#define SPSR_1 RSPI1.SPSR +#define SPDR_1 RSPI1.SPDR.UINT32 +#define SPDR_1L RSPI1.SPDR.UINT16[L] +#define SPDR_1H RSPI1.SPDR.UINT16[H] +#define SPDR_1LL RSPI1.SPDR.UINT8[LL] +#define SPDR_1LH RSPI1.SPDR.UINT8[LH] +#define SPDR_1HL RSPI1.SPDR.UINT8[HL] +#define SPDR_1HH RSPI1.SPDR.UINT8[HH] +#define SPSCR_1 RSPI1.SPSCR +#define SPSSR_1 RSPI1.SPSSR +#define SPBR_1 RSPI1.SPBR +#define SPDCR_1 RSPI1.SPDCR +#define SPCKD_1 RSPI1.SPCKD +#define SSLND_1 RSPI1.SSLND +#define SPND_1 RSPI1.SPND +#define SPCMD0_1 RSPI1.SPCMD0 +#define SPCMD1_1 RSPI1.SPCMD1 +#define SPCMD2_1 RSPI1.SPCMD2 +#define SPCMD3_1 RSPI1.SPCMD3 +#define SPBFCR_1 RSPI1.SPBFCR +#define SPBFDR_1 RSPI1.SPBFDR +#define SPCR_2 RSPI2.SPCR +#define SSLP_2 RSPI2.SSLP +#define SPPCR_2 RSPI2.SPPCR +#define SPSR_2 RSPI2.SPSR +#define SPDR_2 RSPI2.SPDR.UINT32 +#define SPDR_2L RSPI2.SPDR.UINT16[L] +#define SPDR_2H RSPI2.SPDR.UINT16[H] +#define SPDR_2LL RSPI2.SPDR.UINT8[LL] +#define SPDR_2LH RSPI2.SPDR.UINT8[LH] +#define SPDR_2HL RSPI2.SPDR.UINT8[HL] +#define SPDR_2HH RSPI2.SPDR.UINT8[HH] +#define SPSCR_2 RSPI2.SPSCR +#define SPSSR_2 RSPI2.SPSSR +#define SPBR_2 RSPI2.SPBR +#define SPDCR_2 RSPI2.SPDCR +#define SPCKD_2 RSPI2.SPCKD +#define SSLND_2 RSPI2.SSLND +#define SPND_2 RSPI2.SPND +#define SPCMD0_2 RSPI2.SPCMD0 +#define SPCMD1_2 RSPI2.SPCMD1 +#define SPCMD2_2 RSPI2.SPCMD2 +#define SPCMD3_2 RSPI2.SPCMD3 +#define SPBFCR_2 RSPI2.SPBFCR +#define SPBFDR_2 RSPI2.SPBFDR +#define SPCR_3 RSPI3.SPCR +#define SSLP_3 RSPI3.SSLP +#define SPPCR_3 RSPI3.SPPCR +#define SPSR_3 RSPI3.SPSR +#define SPDR_3 RSPI3.SPDR.UINT32 +#define SPDR_3L RSPI3.SPDR.UINT16[L] +#define SPDR_3H RSPI3.SPDR.UINT16[H] +#define SPDR_3LL RSPI3.SPDR.UINT8[LL] +#define SPDR_3LH RSPI3.SPDR.UINT8[LH] +#define SPDR_3HL RSPI3.SPDR.UINT8[HL] +#define SPDR_3HH RSPI3.SPDR.UINT8[HH] +#define SPSCR_3 RSPI3.SPSCR +#define SPSSR_3 RSPI3.SPSSR +#define SPBR_3 RSPI3.SPBR +#define SPDCR_3 RSPI3.SPDCR +#define SPCKD_3 RSPI3.SPCKD +#define SSLND_3 RSPI3.SSLND +#define SPND_3 RSPI3.SPND +#define SPCMD0_3 RSPI3.SPCMD0 +#define SPCMD1_3 RSPI3.SPCMD1 +#define SPCMD2_3 RSPI3.SPCMD2 +#define SPCMD3_3 RSPI3.SPCMD3 +#define SPBFCR_3 RSPI3.SPBFCR +#define SPBFDR_3 RSPI3.SPBFDR +#define SPCR_4 RSPI4.SPCR +#define SSLP_4 RSPI4.SSLP +#define SPPCR_4 RSPI4.SPPCR +#define SPSR_4 RSPI4.SPSR +#define SPDR_4 RSPI4.SPDR.UINT32 +#define SPDR_4L RSPI4.SPDR.UINT16[L] +#define SPDR_4H RSPI4.SPDR.UINT16[H] +#define SPDR_4LL RSPI4.SPDR.UINT8[LL] +#define SPDR_4LH RSPI4.SPDR.UINT8[LH] +#define SPDR_4HL RSPI4.SPDR.UINT8[HL] +#define SPDR_4HH RSPI4.SPDR.UINT8[HH] +#define SPSCR_4 RSPI4.SPSCR +#define SPSSR_4 RSPI4.SPSSR +#define SPBR_4 RSPI4.SPBR +#define SPDCR_4 RSPI4.SPDCR +#define SPCKD_4 RSPI4.SPCKD +#define SSLND_4 RSPI4.SSLND +#define SPND_4 RSPI4.SPND +#define SPCMD0_4 RSPI4.SPCMD0 +#define SPCMD1_4 RSPI4.SPCMD1 +#define SPCMD2_4 RSPI4.SPCMD2 +#define SPCMD3_4 RSPI4.SPCMD3 +#define SPBFCR_4 RSPI4.SPBFCR +#define SPBFDR_4 RSPI4.SPBFDR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rtc_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rtc_iodefine.h new file mode 100644 index 0000000000..6cfb46dde3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/rtc_iodefine.h @@ -0,0 +1,102 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : rtc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef RTC_IODEFINE_H +#define RTC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_rtc +{ /* RTC */ + volatile uint8_t R64CNT; /* R64CNT */ + volatile uint8_t dummy537[1]; /* */ + volatile uint8_t RSECCNT; /* RSECCNT */ + volatile uint8_t dummy538[1]; /* */ + volatile uint8_t RMINCNT; /* RMINCNT */ + volatile uint8_t dummy539[1]; /* */ + volatile uint8_t RHRCNT; /* RHRCNT */ + volatile uint8_t dummy540[1]; /* */ + volatile uint8_t RWKCNT; /* RWKCNT */ + volatile uint8_t dummy541[1]; /* */ + volatile uint8_t RDAYCNT; /* RDAYCNT */ + volatile uint8_t dummy542[1]; /* */ + volatile uint8_t RMONCNT; /* RMONCNT */ + volatile uint8_t dummy543[1]; /* */ + volatile uint16_t RYRCNT; /* RYRCNT */ + volatile uint8_t RSECAR; /* RSECAR */ + volatile uint8_t dummy544[1]; /* */ + volatile uint8_t RMINAR; /* RMINAR */ + volatile uint8_t dummy545[1]; /* */ + volatile uint8_t RHRAR; /* RHRAR */ + volatile uint8_t dummy546[1]; /* */ + volatile uint8_t RWKAR; /* RWKAR */ + volatile uint8_t dummy547[1]; /* */ + volatile uint8_t RDAYAR; /* RDAYAR */ + volatile uint8_t dummy548[1]; /* */ + volatile uint8_t RMONAR; /* RMONAR */ + volatile uint8_t dummy549[1]; /* */ + volatile uint8_t RCR1; /* RCR1 */ + volatile uint8_t dummy550[1]; /* */ + volatile uint8_t RCR2; /* RCR2 */ + volatile uint8_t dummy551[1]; /* */ + volatile uint16_t RYRAR; /* RYRAR */ + volatile uint8_t dummy552[2]; /* */ + volatile uint8_t RCR3; /* RCR3 */ + volatile uint8_t dummy553[1]; /* */ + volatile uint8_t RCR5; /* RCR5 */ + volatile uint8_t dummy554[3]; /* */ + volatile uint16_t RFRH; /* RFRH */ + volatile uint16_t RFRL; /* RFRL */ +}; + + +#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */ + + +#define RTCR64CNT RTC.R64CNT +#define RTCRSECCNT RTC.RSECCNT +#define RTCRMINCNT RTC.RMINCNT +#define RTCRHRCNT RTC.RHRCNT +#define RTCRWKCNT RTC.RWKCNT +#define RTCRDAYCNT RTC.RDAYCNT +#define RTCRMONCNT RTC.RMONCNT +#define RTCRYRCNT RTC.RYRCNT +#define RTCRSECAR RTC.RSECAR +#define RTCRMINAR RTC.RMINAR +#define RTCRHRAR RTC.RHRAR +#define RTCRWKAR RTC.RWKAR +#define RTCRDAYAR RTC.RDAYAR +#define RTCRMONAR RTC.RMONAR +#define RTCRCR1 RTC.RCR1 +#define RTCRCR2 RTC.RCR2 +#define RTCRYRAR RTC.RYRAR +#define RTCRCR3 RTC.RCR3 +#define RTCRCR5 RTC.RCR5 +#define RTCRFRH RTC.RFRH +#define RTCRFRL RTC.RFRL +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scif_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scif_iodefine.h new file mode 100644 index 0000000000..9a710604ce --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scif_iodefine.h @@ -0,0 +1,182 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scif_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SCIF_IODEFINE_H +#define SCIF_IODEFINE_H +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_scif +{ /* SCIF */ + volatile uint16_t SCSMR; /* SCSMR */ + volatile uint8_t dummy1[2]; /* */ + volatile uint8_t SCBRR; /* SCBRR */ + volatile uint8_t dummy2[3]; /* */ + volatile uint16_t SCSCR; /* SCSCR */ + volatile uint8_t dummy3[2]; /* */ + volatile uint8_t SCFTDR; /* SCFTDR */ + volatile uint8_t dummy4[3]; /* */ + volatile uint16_t SCFSR; /* SCFSR */ + volatile uint8_t dummy5[2]; /* */ + volatile uint8_t SCFRDR; /* SCFRDR */ + volatile uint8_t dummy6[3]; /* */ + volatile uint16_t SCFCR; /* SCFCR */ + volatile uint8_t dummy7[2]; /* */ + volatile uint16_t SCFDR; /* SCFDR */ + volatile uint8_t dummy8[2]; /* */ + volatile uint16_t SCSPTR; /* SCSPTR */ + volatile uint8_t dummy9[2]; /* */ + volatile uint16_t SCLSR; /* SCLSR */ + volatile uint8_t dummy10[2]; /* */ + volatile uint16_t SCEMR; /* SCEMR */ +}; + + +#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */ +#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */ +#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */ +#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */ +#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */ +#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */ +#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */ +#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */ + +#define P_SCIF0 (0xE8007000uL) /* SCIF0 */ +#define P_SCIF1 (0xE8007800uL) /* SCIF1 */ +#define P_SCIF2 (0xE8008000uL) /* SCIF2 */ +#define P_SCIF3 (0xE8008800uL) /* SCIF3 */ +#define P_SCIF4 (0xE8009000uL) /* SCIF4 */ +#define P_SCIF5 (0xE8009800uL) /* SCIF5 */ +#define P_SCIF6 (0xE800A000uL) /* SCIF6 */ +#define P_SCIF7 (0xE800A800uL) /* SCIF7 */ + + +/* Start of channnel array defines of SCIF */ + +/* Channnel array defines of SCIF */ +/*(Sample) value = SCIF[ channel ]->SCSMR; */ +#define SCIF_COUNT 8 +#define SCIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of SCIF */ + + +#define SCSMR_0 SCIF0.SCSMR +#define SCBRR_0 SCIF0.SCBRR +#define SCSCR_0 SCIF0.SCSCR +#define SCFTDR_0 SCIF0.SCFTDR +#define SCFSR_0 SCIF0.SCFSR +#define SCFRDR_0 SCIF0.SCFRDR +#define SCFCR_0 SCIF0.SCFCR +#define SCFDR_0 SCIF0.SCFDR +#define SCSPTR_0 SCIF0.SCSPTR +#define SCLSR_0 SCIF0.SCLSR +#define SCEMR_0 SCIF0.SCEMR +#define SCSMR_1 SCIF1.SCSMR +#define SCBRR_1 SCIF1.SCBRR +#define SCSCR_1 SCIF1.SCSCR +#define SCFTDR_1 SCIF1.SCFTDR +#define SCFSR_1 SCIF1.SCFSR +#define SCFRDR_1 SCIF1.SCFRDR +#define SCFCR_1 SCIF1.SCFCR +#define SCFDR_1 SCIF1.SCFDR +#define SCSPTR_1 SCIF1.SCSPTR +#define SCLSR_1 SCIF1.SCLSR +#define SCEMR_1 SCIF1.SCEMR +#define SCSMR_2 SCIF2.SCSMR +#define SCBRR_2 SCIF2.SCBRR +#define SCSCR_2 SCIF2.SCSCR +#define SCFTDR_2 SCIF2.SCFTDR +#define SCFSR_2 SCIF2.SCFSR +#define SCFRDR_2 SCIF2.SCFRDR +#define SCFCR_2 SCIF2.SCFCR +#define SCFDR_2 SCIF2.SCFDR +#define SCSPTR_2 SCIF2.SCSPTR +#define SCLSR_2 SCIF2.SCLSR +#define SCEMR_2 SCIF2.SCEMR +#define SCSMR_3 SCIF3.SCSMR +#define SCBRR_3 SCIF3.SCBRR +#define SCSCR_3 SCIF3.SCSCR +#define SCFTDR_3 SCIF3.SCFTDR +#define SCFSR_3 SCIF3.SCFSR +#define SCFRDR_3 SCIF3.SCFRDR +#define SCFCR_3 SCIF3.SCFCR +#define SCFDR_3 SCIF3.SCFDR +#define SCSPTR_3 SCIF3.SCSPTR +#define SCLSR_3 SCIF3.SCLSR +#define SCEMR_3 SCIF3.SCEMR +#define SCSMR_4 SCIF4.SCSMR +#define SCBRR_4 SCIF4.SCBRR +#define SCSCR_4 SCIF4.SCSCR +#define SCFTDR_4 SCIF4.SCFTDR +#define SCFSR_4 SCIF4.SCFSR +#define SCFRDR_4 SCIF4.SCFRDR +#define SCFCR_4 SCIF4.SCFCR +#define SCFDR_4 SCIF4.SCFDR +#define SCSPTR_4 SCIF4.SCSPTR +#define SCLSR_4 SCIF4.SCLSR +#define SCEMR_4 SCIF4.SCEMR +#define SCSMR_5 SCIF5.SCSMR +#define SCBRR_5 SCIF5.SCBRR +#define SCSCR_5 SCIF5.SCSCR +#define SCFTDR_5 SCIF5.SCFTDR +#define SCFSR_5 SCIF5.SCFSR +#define SCFRDR_5 SCIF5.SCFRDR +#define SCFCR_5 SCIF5.SCFCR +#define SCFDR_5 SCIF5.SCFDR +#define SCSPTR_5 SCIF5.SCSPTR +#define SCLSR_5 SCIF5.SCLSR +#define SCEMR_5 SCIF5.SCEMR +#define SCSMR_6 SCIF6.SCSMR +#define SCBRR_6 SCIF6.SCBRR +#define SCSCR_6 SCIF6.SCSCR +#define SCFTDR_6 SCIF6.SCFTDR +#define SCFSR_6 SCIF6.SCFSR +#define SCFRDR_6 SCIF6.SCFRDR +#define SCFCR_6 SCIF6.SCFCR +#define SCFDR_6 SCIF6.SCFDR +#define SCSPTR_6 SCIF6.SCSPTR +#define SCLSR_6 SCIF6.SCLSR +#define SCEMR_6 SCIF6.SCEMR +#define SCSMR_7 SCIF7.SCSMR +#define SCBRR_7 SCIF7.SCBRR +#define SCSCR_7 SCIF7.SCSCR +#define SCFTDR_7 SCIF7.SCFTDR +#define SCFSR_7 SCIF7.SCFSR +#define SCFRDR_7 SCIF7.SCFRDR +#define SCFCR_7 SCIF7.SCFCR +#define SCFDR_7 SCIF7.SCFDR +#define SCSPTR_7 SCIF7.SCSPTR +#define SCLSR_7 SCIF7.SCLSR +#define SCEMR_7 SCIF7.SCEMR +/* <-SEC M1.10.1 */ +/* <-QAC 0857 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scim_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scim_iodefine.h new file mode 100644 index 0000000000..2ddf1e61d9 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scim_iodefine.h @@ -0,0 +1,87 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scim_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SCIM_IODEFINE_H +#define SCIM_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_scim +{ /* SCIM */ + volatile uint8_t SMR; /* SMR */ + volatile uint8_t BRR; /* BRR */ + volatile uint8_t SCR; /* SCR */ + volatile uint8_t TDR; /* TDR */ + volatile uint8_t SSR; /* SSR */ + volatile uint8_t RDR; /* RDR */ + volatile uint8_t SCMR; /* SCMR */ + volatile uint8_t SEMR; /* SEMR */ + volatile uint8_t SNFR; /* SNFR */ + volatile uint8_t dummy1[4]; /* */ + volatile uint8_t SECR; /* SECR */ +}; + + +#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ +#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ + + +/* Start of channnel array defines of SCIM */ + +/* Channnel array defines of SCIM */ +/*(Sample) value = SCIM[ channel ]->SMR; */ +#define SCIM_COUNT 2 +#define SCIM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIM0, &SCIM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of SCIM */ + + +#define SMR0 SCIM0.SMR +#define BRR0 SCIM0.BRR +#define SCR0 SCIM0.SCR +#define TDR0 SCIM0.TDR +#define SSR0 SCIM0.SSR +#define RDR0 SCIM0.RDR +#define SCMR0 SCIM0.SCMR +#define SEMR0 SCIM0.SEMR +#define SNFR0 SCIM0.SNFR +#define SECR0 SCIM0.SECR +#define SMR1 SCIM1.SMR +#define BRR1 SCIM1.BRR +#define SCR1 SCIM1.SCR +#define TDR1 SCIM1.TDR +#define SSR1 SCIM1.SSR +#define RDR1 SCIM1.RDR +#define SCMR1 SCIM1.SCMR +#define SEMR1 SCIM1.SEMR +#define SNFR1 SCIM1.SNFR +#define SECR1 SCIM1.SECR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scux_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scux_iodefine.h new file mode 100644 index 0000000000..a6d5646dcc --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/scux_iodefine.h @@ -0,0 +1,808 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : scux_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SCUX_IODEFINE_H +#define SCUX_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_scux +{ /* SCUX */ +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ + volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ + volatile uint8_t dummy259[248]; /* */ +/* end of struct st_scux_from_ipcir_ipc0_n */ +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */ + volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */ + volatile uint8_t dummy260[248]; /* */ +/* end of struct st_scux_from_ipcir_ipc0_n */ +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */ + volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */ + volatile uint8_t dummy261[248]; /* */ +/* end of struct st_scux_from_ipcir_ipc0_n */ +/* start of struct st_scux_from_ipcir_ipc0_n */ + volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */ + volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */ + volatile uint8_t dummy262[248]; /* */ +/* end of struct st_scux_from_ipcir_ipc0_n */ +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ + volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ + volatile uint8_t dummy263[248]; /* */ +/* end of struct st_scux_from_opcir_opc0_n */ +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */ + volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */ + volatile uint8_t dummy264[248]; /* */ +/* end of struct st_scux_from_opcir_opc0_n */ +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */ + volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */ + volatile uint8_t dummy265[248]; /* */ +/* end of struct st_scux_from_opcir_opc0_n */ +/* start of struct st_scux_from_opcir_opc0_n */ + volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */ + volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */ + volatile uint8_t dummy266[248]; /* */ +/* end of struct st_scux_from_opcir_opc0_n */ +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ + volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ + volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ + volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ + volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ + volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ + volatile uint8_t dummy267[4]; /* */ + volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy268[224]; /* */ +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */ + volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */ + volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */ + volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */ + volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */ + volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */ + volatile uint8_t dummy269[4]; /* */ + volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */ +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy270[224]; /* */ +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */ + volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */ + volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */ + volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */ + volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */ + volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */ + volatile uint8_t dummy271[4]; /* */ + volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */ +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy272[224]; /* */ +/* start of struct st_scux_from_ffdir_ffd0_n */ + volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */ + volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */ + volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */ + volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */ + volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */ + volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */ + volatile uint8_t dummy273[4]; /* */ + volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */ +/* end of struct st_scux_from_ffdir_ffd0_n */ + volatile uint8_t dummy274[224]; /* */ +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ + volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ + volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ + volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ + volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ + volatile uint8_t dummy275[4]; /* */ + volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy276[228]; /* */ +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */ + volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */ + volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */ + volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */ + volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */ + volatile uint8_t dummy277[4]; /* */ + volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */ +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy278[228]; /* */ +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */ + volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */ + volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */ + volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */ + volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */ + volatile uint8_t dummy279[4]; /* */ + volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */ +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy280[228]; /* */ +/* start of struct st_scux_from_ffuir_ffu0_n */ + volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */ + volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */ + volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */ + volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */ + volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */ + volatile uint8_t dummy281[4]; /* */ + volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */ +/* end of struct st_scux_from_ffuir_ffu0_n */ + volatile uint8_t dummy282[228]; /* */ +/* start of struct st_scux_from_srcir0_2src0_n */ + volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ + volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ + volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ + volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ + volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ + volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ + volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ + volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ + volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ + volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ + volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ + volatile uint8_t dummy283[4]; /* */ + volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ + volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ + volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ + volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ + volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ + volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ + volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ + volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ + volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ + volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ + volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ + volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ + volatile uint8_t dummy284[4]; /* */ + volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ + volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ +/* end of struct st_scux_from_srcir0_2src0_n */ + volatile uint8_t dummy285[148]; /* */ +/* start of struct st_scux_from_srcir0_2src0_n */ + volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */ + volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */ + volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */ + volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */ + volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */ + volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */ + volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */ + volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */ + volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */ + volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */ + volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */ + volatile uint8_t dummy286[4]; /* */ + volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */ + volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */ + volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */ + volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */ + volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */ + volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */ + volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */ + volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */ + volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */ + volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */ + volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */ + volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */ + volatile uint8_t dummy287[4]; /* */ + volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */ + volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */ +/* end of struct st_scux_from_srcir0_2src0_n */ + volatile uint8_t dummy288[148]; /* */ +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ + volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ + volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ + volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ + volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ + volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ + volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ + volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ + volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ + volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ + volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ + volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ + volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ + volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ + volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ + volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ + volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ + volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ + volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ + volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ + volatile uint8_t dummy289[4]; /* */ + volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy290[168]; /* */ +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */ + volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */ + volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */ + volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */ + volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */ + volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */ + volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */ + volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */ + volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */ + volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */ + volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */ + volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */ + volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */ + volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */ + volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */ + volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */ + volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */ + volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */ + volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */ + volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */ + volatile uint8_t dummy291[4]; /* */ + volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */ +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy292[168]; /* */ +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */ + volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */ + volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */ + volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */ + volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */ + volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */ + volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */ + volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */ + volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */ + volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */ + volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */ + volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */ + volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */ + volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */ + volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */ + volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */ + volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */ + volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */ + volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */ + volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */ + volatile uint8_t dummy293[4]; /* */ + volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */ +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy294[168]; /* */ +/* start of struct st_scux_from_dvuir_dvu0_n */ + volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */ + volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */ + volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */ + volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */ + volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */ + volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */ + volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */ + volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */ + volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */ + volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */ + volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */ + volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */ + volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */ + volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */ + volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */ + volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */ + volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */ + volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */ + volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */ + volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */ + volatile uint8_t dummy295[4]; /* */ + volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */ +/* end of struct st_scux_from_dvuir_dvu0_n */ + volatile uint8_t dummy296[168]; /* */ + volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */ + volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */ + volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */ + volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */ + volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */ + volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */ + volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */ + volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */ + volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */ + volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */ + volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */ + volatile uint8_t dummy297[212]; /* */ + volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */ + volatile uint32_t DMACR_CIM; /* DMACR_CIM */ +#define SCUX_DMATDn_CIM_COUNT 4 + union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */ + union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */ + union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */ + union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */ +#define SCUX_DMATUn_CIM_COUNT 4 + union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */ + union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */ + union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */ + union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */ + + volatile uint8_t dummy298[16]; /* */ + volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */ +#define SCUX_FDTSELn_CIM_COUNT 4 + volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */ + volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */ + volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */ + volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */ +#define SCUX_FUTSELn_CIM_COUNT 4 + volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */ + volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */ + volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */ + volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */ + volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */ + volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */ +#define SCUX_SRCRSELn_CIM_COUNT 4 + volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */ + volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */ + volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */ + volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */ + volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */ +}; + + +struct st_scux_from_ipcir_ipc0_n +{ + volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ + volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ + volatile uint8_t dummy1[248]; /* */ +}; + + +struct st_scux_from_opcir_opc0_n +{ + volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ + volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ + volatile uint8_t dummy1[248]; /* */ +}; + + +struct st_scux_from_ffdir_ffd0_n +{ + volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ + volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ + volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ + volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */ + volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */ + volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ +}; + + +struct st_scux_from_ffuir_ffu0_n +{ + volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ + volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ + volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ + volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */ + volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ +}; + + +struct st_scux_from_srcir0_2src0_n +{ + volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ + volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ + volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ + volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */ + volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */ + volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */ + volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */ + volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */ + volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */ + volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */ + volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */ + volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */ + volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */ + volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */ + volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */ + volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */ + volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */ + volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */ + volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */ + volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */ + volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */ + volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */ + volatile uint8_t dummy2[4]; /* */ + volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ + volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ +}; + + +struct st_scux_from_dvuir_dvu0_n +{ + volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ + volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ + volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ + volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */ + volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */ + volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */ + volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */ + volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */ + volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */ + volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */ + volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */ + volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */ + volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */ + volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */ + volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */ + volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */ + volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */ + volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */ + volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */ + volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ + volatile uint8_t dummy1[4]; /* */ + volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ +}; + + +#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ + + +/* Start of channnel array defines of SCUX */ + +/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4 +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ +#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ +#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ +#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ + + +/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2 +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ +#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ + + +/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4 +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ +#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ +#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ +#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ + + +/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4 +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ +#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ +#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ +#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ + + +/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4 +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ +#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ +#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ +#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ + + +/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4 +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ +#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ +#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ +#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ + +/* End of channnel array defines of SCUX */ + + +#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0 +#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0 +#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1 +#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1 +#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2 +#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2 +#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3 +#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3 +#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0 +#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0 +#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1 +#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1 +#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2 +#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2 +#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3 +#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3 +#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0 +#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0 +#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0 +#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0 +#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0 +#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0 +#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0 +#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1 +#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1 +#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1 +#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1 +#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1 +#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1 +#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1 +#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2 +#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2 +#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2 +#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2 +#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2 +#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2 +#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2 +#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3 +#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3 +#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3 +#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3 +#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3 +#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3 +#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3 +#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0 +#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0 +#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0 +#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0 +#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0 +#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0 +#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1 +#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1 +#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1 +#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1 +#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1 +#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1 +#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2 +#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2 +#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2 +#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2 +#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2 +#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2 +#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3 +#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3 +#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3 +#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3 +#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3 +#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3 +#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0 +#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0 +#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0 +#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0 +#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0 +#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0 +#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0 +#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0 +#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0 +#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0 +#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0 +#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0 +#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0 +#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0 +#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0 +#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0 +#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0 +#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0 +#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0 +#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0 +#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0 +#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0 +#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0 +#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0 +#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0 +#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1 +#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1 +#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1 +#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1 +#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1 +#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1 +#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1 +#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1 +#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1 +#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1 +#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1 +#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1 +#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1 +#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1 +#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1 +#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1 +#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1 +#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1 +#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1 +#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1 +#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1 +#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1 +#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1 +#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1 +#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1 +#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0 +#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0 +#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0 +#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0 +#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0 +#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0 +#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0 +#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0 +#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0 +#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0 +#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0 +#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0 +#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0 +#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0 +#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0 +#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0 +#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0 +#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0 +#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0 +#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0 +#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0 +#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1 +#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1 +#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1 +#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1 +#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1 +#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1 +#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1 +#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1 +#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1 +#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1 +#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1 +#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1 +#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1 +#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1 +#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1 +#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1 +#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1 +#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1 +#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1 +#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1 +#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1 +#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2 +#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2 +#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2 +#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2 +#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2 +#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2 +#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2 +#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2 +#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2 +#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2 +#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2 +#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2 +#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2 +#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2 +#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2 +#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2 +#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2 +#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2 +#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2 +#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2 +#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2 +#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3 +#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3 +#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3 +#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3 +#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3 +#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3 +#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3 +#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3 +#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3 +#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3 +#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3 +#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3 +#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3 +#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3 +#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3 +#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3 +#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3 +#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3 +#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3 +#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3 +#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3 +#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0 +#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0 +#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0 +#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0 +#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0 +#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0 +#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0 +#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0 +#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0 +#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0 +#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0 +#define SCUXSWRSR_CIM SCUX.SWRSR_CIM +#define SCUXDMACR_CIM SCUX.DMACR_CIM +#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32 +#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L] +#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H] +#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32 +#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L] +#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H] +#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32 +#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L] +#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H] +#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32 +#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L] +#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H] +#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32 +#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L] +#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H] +#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32 +#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L] +#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H] +#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32 +#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L] +#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H] +#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32 +#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L] +#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H] +#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM +#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM +#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM +#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM +#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM +#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM +#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM +#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM +#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM +#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM +#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM +#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM +#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM +#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM +#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM +#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/sdg_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/sdg_iodefine.h new file mode 100644 index 0000000000..78abfc08e8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/sdg_iodefine.h @@ -0,0 +1,86 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : sdg_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SDG_IODEFINE_H +#define SDG_IODEFINE_H + +struct st_sdg +{ /* SDG */ + volatile uint8_t SGCR1; /* SGCR1 */ + volatile uint8_t SGCSR; /* SGCSR */ + volatile uint8_t SGCR2; /* SGCR2 */ + volatile uint8_t SGLR; /* SGLR */ + volatile uint8_t SGTFR; /* SGTFR */ + volatile uint8_t SGSFR; /* SGSFR */ +}; + + +#define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */ +#define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */ +#define SDG2 (*(struct st_sdg *)0xFCFF4C00uL) /* SDG2 */ +#define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */ + + +/* Start of channnel array defines of SDG */ + +/* Channnel array defines of SDG */ +/*(Sample) value = SDG[ channel ]->SGCR1; */ +#define SDG_COUNT 4 +#define SDG_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SDG0, &SDG1, &SDG2, &SDG3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of SDG */ + + +#define SGCR1_0 SDG0.SGCR1 +#define SGCSR_0 SDG0.SGCSR +#define SGCR2_0 SDG0.SGCR2 +#define SGLR_0 SDG0.SGLR +#define SGTFR_0 SDG0.SGTFR +#define SGSFR_0 SDG0.SGSFR +#define SGCR1_1 SDG1.SGCR1 +#define SGCSR_1 SDG1.SGCSR +#define SGCR2_1 SDG1.SGCR2 +#define SGLR_1 SDG1.SGLR +#define SGTFR_1 SDG1.SGTFR +#define SGSFR_1 SDG1.SGSFR +#define SGCR1_2 SDG2.SGCR1 +#define SGCSR_2 SDG2.SGCSR +#define SGCR2_2 SDG2.SGCR2 +#define SGLR_2 SDG2.SGLR +#define SGTFR_2 SDG2.SGTFR +#define SGSFR_2 SDG2.SGSFR +#define SGCR1_3 SDG3.SGCR1 +#define SGCSR_3 SDG3.SGCSR +#define SGCR2_3 SDG3.SGCR2 +#define SGLR_3 SDG3.SGLR +#define SGTFR_3 SDG3.SGTFR +#define SGSFR_3 SDG3.SGSFR +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spdif_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spdif_iodefine.h new file mode 100644 index 0000000000..6f69f80850 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spdif_iodefine.h @@ -0,0 +1,68 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : spdif_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SPDIF_IODEFINE_H +#define SPDIF_IODEFINE_H + +struct st_spdif +{ /* SPDIF */ + volatile uint32_t TLCA; /* TLCA */ + volatile uint32_t TRCA; /* TRCA */ + volatile uint32_t TLCS; /* TLCS */ + volatile uint32_t TRCS; /* TRCS */ + volatile uint32_t TUI; /* TUI */ + volatile uint32_t RLCA; /* RLCA */ + volatile uint32_t RRCA; /* RRCA */ + volatile uint32_t RLCS; /* RLCS */ + volatile uint32_t RRCS; /* RRCS */ + volatile uint32_t RUI; /* RUI */ + volatile uint32_t CTRL; /* CTRL */ + volatile uint32_t STAT; /* STAT */ + volatile uint32_t TDAD; /* TDAD */ + volatile uint32_t RDAD; /* RDAD */ +}; + + +#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */ + + +#define SPDIFTLCA SPDIF.TLCA +#define SPDIFTRCA SPDIF.TRCA +#define SPDIFTLCS SPDIF.TLCS +#define SPDIFTRCS SPDIF.TRCS +#define SPDIFTUI SPDIF.TUI +#define SPDIFRLCA SPDIF.RLCA +#define SPDIFRRCA SPDIF.RRCA +#define SPDIFRLCS SPDIF.RLCS +#define SPDIFRRCS SPDIF.RRCS +#define SPDIFRUI SPDIF.RUI +#define SPDIFCTRL SPDIF.CTRL +#define SPDIFSTAT SPDIF.STAT +#define SPDIFTDAD SPDIF.TDAD +#define SPDIFRDAD SPDIF.RDAD +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spibsc_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spibsc_iodefine.h new file mode 100644 index 0000000000..d25b903b89 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/spibsc_iodefine.h @@ -0,0 +1,173 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : spibsc_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SPIBSC_IODEFINE_H +#define SPIBSC_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_spibsc +{ /* SPIBSC */ + volatile uint32_t CMNCR; /* CMNCR */ + volatile uint32_t SSLDR; /* SSLDR */ + volatile uint32_t SPBCR; /* SPBCR */ + volatile uint32_t DRCR; /* DRCR */ + volatile uint32_t DRCMR; /* DRCMR */ + volatile uint32_t DREAR; /* DREAR */ + volatile uint32_t DROPR; /* DROPR */ + volatile uint32_t DRENR; /* DRENR */ + volatile uint32_t SMCR; /* SMCR */ + volatile uint32_t SMCMR; /* SMCMR */ + volatile uint32_t SMADR; /* SMADR */ + volatile uint32_t SMOPR; /* SMOPR */ + volatile uint32_t SMENR; /* SMENR */ + volatile uint8_t dummy1[4]; /* */ + union iodefine_reg32_t SMRDR0; /* SMRDR0 */ + union iodefine_reg32_t SMRDR1; /* SMRDR1 */ + union iodefine_reg32_t SMWDR0; /* SMWDR0 */ + union iodefine_reg32_t SMWDR1; /* SMWDR1 */ + + volatile uint32_t CMNSR; /* CMNSR */ + volatile uint8_t dummy2[12]; /* */ + volatile uint32_t DRDMCR; /* DRDMCR */ + volatile uint32_t DRDRENR; /* DRDRENR */ + volatile uint32_t SMDMCR; /* SMDMCR */ + volatile uint32_t SMDRENR; /* SMDRENR */ +}; + + +#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */ +#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */ + + +/* Start of channnel array defines of SPIBSC */ + +/* Channnel array defines of SPIBSC */ +/*(Sample) value = SPIBSC[ channel ]->CMNCR; */ +#define SPIBSC_COUNT 2 +#define SPIBSC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SPIBSC0, &SPIBSC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of SPIBSC */ + + +#define CMNCR_0 SPIBSC0.CMNCR +#define SSLDR_0 SPIBSC0.SSLDR +#define SPBCR_0 SPIBSC0.SPBCR +#define DRCR_0 SPIBSC0.DRCR +#define DRCMR_0 SPIBSC0.DRCMR +#define DREAR_0 SPIBSC0.DREAR +#define DROPR_0 SPIBSC0.DROPR +#define DRENR_0 SPIBSC0.DRENR +#define SMCR_0 SPIBSC0.SMCR +#define SMCMR_0 SPIBSC0.SMCMR +#define SMADR_0 SPIBSC0.SMADR +#define SMOPR_0 SPIBSC0.SMOPR +#define SMENR_0 SPIBSC0.SMENR +#define SMRDR0_0 SPIBSC0.SMRDR0.UINT32 +#define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L] +#define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H] +#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL] +#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH] +#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL] +#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH] +#define SMRDR1_0 SPIBSC0.SMRDR1.UINT32 +#define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L] +#define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H] +#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL] +#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH] +#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL] +#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH] +#define SMWDR0_0 SPIBSC0.SMWDR0.UINT32 +#define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L] +#define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H] +#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL] +#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH] +#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL] +#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH] +#define SMWDR1_0 SPIBSC0.SMWDR1.UINT32 +#define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L] +#define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H] +#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL] +#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH] +#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL] +#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH] +#define CMNSR_0 SPIBSC0.CMNSR +#define DRDMCR_0 SPIBSC0.DRDMCR +#define DRDRENR_0 SPIBSC0.DRDRENR +#define SMDMCR_0 SPIBSC0.SMDMCR +#define SMDRENR_0 SPIBSC0.SMDRENR +#define CMNCR_1 SPIBSC1.CMNCR +#define SSLDR_1 SPIBSC1.SSLDR +#define SPBCR_1 SPIBSC1.SPBCR +#define DRCR_1 SPIBSC1.DRCR +#define DRCMR_1 SPIBSC1.DRCMR +#define DREAR_1 SPIBSC1.DREAR +#define DROPR_1 SPIBSC1.DROPR +#define DRENR_1 SPIBSC1.DRENR +#define SMCR_1 SPIBSC1.SMCR +#define SMCMR_1 SPIBSC1.SMCMR +#define SMADR_1 SPIBSC1.SMADR +#define SMOPR_1 SPIBSC1.SMOPR +#define SMENR_1 SPIBSC1.SMENR +#define SMRDR0_1 SPIBSC1.SMRDR0.UINT32 +#define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L] +#define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H] +#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL] +#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH] +#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL] +#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH] +#define SMRDR1_1 SPIBSC1.SMRDR1.UINT32 +#define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L] +#define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H] +#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL] +#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH] +#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL] +#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH] +#define SMWDR0_1 SPIBSC1.SMWDR0.UINT32 +#define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L] +#define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H] +#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL] +#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH] +#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL] +#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH] +#define SMWDR1_1 SPIBSC1.SMWDR1.UINT32 +#define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L] +#define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H] +#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL] +#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH] +#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL] +#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH] +#define CMNSR_1 SPIBSC1.CMNSR +#define DRDMCR_1 SPIBSC1.DRDMCR +#define DRDRENR_1 SPIBSC1.DRDRENR +#define SMDMCR_1 SPIBSC1.SMDMCR +#define SMDRENR_1 SPIBSC1.SMDRENR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ssif_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ssif_iodefine.h new file mode 100644 index 0000000000..045551c9f2 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/ssif_iodefine.h @@ -0,0 +1,131 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : ssif_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef SSIF_IODEFINE_H +#define SSIF_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_ssif +{ /* SSIF */ + volatile uint32_t SSICR; /* SSICR */ + volatile uint32_t SSISR; /* SSISR */ + volatile uint8_t dummy1[8]; /* */ + volatile uint32_t SSIFCR; /* SSIFCR */ + volatile uint32_t SSIFSR; /* SSIFSR */ + volatile uint32_t SSIFTDR; /* SSIFTDR */ + volatile uint32_t SSIFRDR; /* SSIFRDR */ + volatile uint32_t SSITDMR; /* SSITDMR */ + volatile uint32_t SSIFCCR; /* SSIFCCR */ + volatile uint32_t SSIFCMR; /* SSIFCMR */ + volatile uint32_t SSIFCSR; /* SSIFCSR */ +}; + + +#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */ +#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */ +#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */ +#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */ +#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */ +#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */ + + +/* Start of channnel array defines of SSIF */ + +/* Channnel array defines of SSIF */ +/*(Sample) value = SSIF[ channel ]->SSICR; */ +#define SSIF_COUNT 6 +#define SSIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channnel array defines of SSIF */ + + +#define SSICR_0 SSIF0.SSICR +#define SSISR_0 SSIF0.SSISR +#define SSIFCR_0 SSIF0.SSIFCR +#define SSIFSR_0 SSIF0.SSIFSR +#define SSIFTDR_0 SSIF0.SSIFTDR +#define SSIFRDR_0 SSIF0.SSIFRDR +#define SSITDMR_0 SSIF0.SSITDMR +#define SSIFCCR_0 SSIF0.SSIFCCR +#define SSIFCMR_0 SSIF0.SSIFCMR +#define SSIFCSR_0 SSIF0.SSIFCSR +#define SSICR_1 SSIF1.SSICR +#define SSISR_1 SSIF1.SSISR +#define SSIFCR_1 SSIF1.SSIFCR +#define SSIFSR_1 SSIF1.SSIFSR +#define SSIFTDR_1 SSIF1.SSIFTDR +#define SSIFRDR_1 SSIF1.SSIFRDR +#define SSITDMR_1 SSIF1.SSITDMR +#define SSIFCCR_1 SSIF1.SSIFCCR +#define SSIFCMR_1 SSIF1.SSIFCMR +#define SSIFCSR_1 SSIF1.SSIFCSR +#define SSICR_2 SSIF2.SSICR +#define SSISR_2 SSIF2.SSISR +#define SSIFCR_2 SSIF2.SSIFCR +#define SSIFSR_2 SSIF2.SSIFSR +#define SSIFTDR_2 SSIF2.SSIFTDR +#define SSIFRDR_2 SSIF2.SSIFRDR +#define SSITDMR_2 SSIF2.SSITDMR +#define SSIFCCR_2 SSIF2.SSIFCCR +#define SSIFCMR_2 SSIF2.SSIFCMR +#define SSIFCSR_2 SSIF2.SSIFCSR +#define SSICR_3 SSIF3.SSICR +#define SSISR_3 SSIF3.SSISR +#define SSIFCR_3 SSIF3.SSIFCR +#define SSIFSR_3 SSIF3.SSIFSR +#define SSIFTDR_3 SSIF3.SSIFTDR +#define SSIFRDR_3 SSIF3.SSIFRDR +#define SSITDMR_3 SSIF3.SSITDMR +#define SSIFCCR_3 SSIF3.SSIFCCR +#define SSIFCMR_3 SSIF3.SSIFCMR +#define SSIFCSR_3 SSIF3.SSIFCSR +#define SSICR_4 SSIF4.SSICR +#define SSISR_4 SSIF4.SSISR +#define SSIFCR_4 SSIF4.SSIFCR +#define SSIFSR_4 SSIF4.SSIFSR +#define SSIFTDR_4 SSIF4.SSIFTDR +#define SSIFRDR_4 SSIF4.SSIFRDR +#define SSITDMR_4 SSIF4.SSITDMR +#define SSIFCCR_4 SSIF4.SSIFCCR +#define SSIFCMR_4 SSIF4.SSIFCMR +#define SSIFCSR_4 SSIF4.SSIFCSR +#define SSICR_5 SSIF5.SSICR +#define SSISR_5 SSIF5.SSISR +#define SSIFCR_5 SSIF5.SSIFCR +#define SSIFSR_5 SSIF5.SSIFSR +#define SSIFTDR_5 SSIF5.SSIFTDR +#define SSIFRDR_5 SSIF5.SSIFRDR +#define SSITDMR_5 SSIF5.SSITDMR +#define SSIFCCR_5 SSIF5.SSIFCCR +#define SSIFCMR_5 SSIF5.SSIFCMR +#define SSIFCSR_5 SSIF5.SSIFCSR +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/usb20_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/usb20_iodefine.h new file mode 100644 index 0000000000..97e15c8455 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/usb20_iodefine.h @@ -0,0 +1,546 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : usb20_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef USB20_IODEFINE_H +#define USB20_IODEFINE_H +/* ->SEC M1.10.1 : Not magic number */ + +struct st_usb20 +{ /* USB20 */ + volatile uint16_t SYSCFG0; /* SYSCFG0 */ + volatile uint16_t BUSWAIT; /* BUSWAIT */ + volatile uint16_t SYSSTS0; /* SYSSTS0 */ + volatile uint8_t dummy1[2]; /* */ + volatile uint16_t DVSTCTR0; /* DVSTCTR0 */ + volatile uint8_t dummy2[2]; /* */ + volatile uint16_t TESTMODE; /* TESTMODE */ + volatile uint8_t dummy3[2]; /* */ +#define USB20_D0FBCFG_COUNT 2 + volatile uint16_t D0FBCFG; /* D0FBCFG */ + volatile uint16_t D1FBCFG; /* D1FBCFG */ + union iodefine_reg32_t CFIFO; /* CFIFO */ +#define USB20_D0FIFO_COUNT 2 + union iodefine_reg32_t D0FIFO; /* D0FIFO */ + union iodefine_reg32_t D1FIFO; /* D1FIFO */ + + volatile uint16_t CFIFOSEL; /* CFIFOSEL */ + volatile uint16_t CFIFOCTR; /* CFIFOCTR */ + volatile uint8_t dummy4[4]; /* */ +/* start of struct st_usb20_from_d0fifosel */ + volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ + volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ +/* end of struct st_usb20_from_d0fifosel */ +/* start of struct st_usb20_from_d0fifosel */ + volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */ + volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */ +/* end of struct st_usb20_from_d0fifosel */ +#define USB20_INTENB0_COUNT 2 + volatile uint16_t INTENB0; /* INTENB0 */ + volatile uint16_t INTENB1; /* INTENB1 */ + volatile uint8_t dummy5[2]; /* */ + volatile uint16_t BRDYENB; /* BRDYENB */ + volatile uint16_t NRDYENB; /* NRDYENB */ + volatile uint16_t BEMPENB; /* BEMPENB */ + volatile uint16_t SOFCFG; /* SOFCFG */ + volatile uint8_t dummy6[2]; /* */ +#define USB20_INTSTS0_COUNT 2 + volatile uint16_t INTSTS0; /* INTSTS0 */ + volatile uint16_t INTSTS1; /* INTSTS1 */ + volatile uint8_t dummy7[2]; /* */ + volatile uint16_t BRDYSTS; /* BRDYSTS */ + volatile uint16_t NRDYSTS; /* NRDYSTS */ + volatile uint16_t BEMPSTS; /* BEMPSTS */ + volatile uint16_t FRMNUM; /* FRMNUM */ + volatile uint16_t UFRMNUM; /* UFRMNUM */ + volatile uint16_t USBADDR; /* USBADDR */ + volatile uint8_t dummy8[2]; /* */ + volatile uint16_t USBREQ; /* USBREQ */ + volatile uint16_t USBVAL; /* USBVAL */ + volatile uint16_t USBINDX; /* USBINDX */ + volatile uint16_t USBLENG; /* USBLENG */ + volatile uint16_t DCPCFG; /* DCPCFG */ + volatile uint16_t DCPMAXP; /* DCPMAXP */ + volatile uint16_t DCPCTR; /* DCPCTR */ + volatile uint8_t dummy9[2]; /* */ + volatile uint16_t PIPESEL; /* PIPESEL */ + volatile uint8_t dummy10[2]; /* */ + volatile uint16_t PIPECFG; /* PIPECFG */ + volatile uint16_t PIPEBUF; /* PIPEBUF */ + volatile uint16_t PIPEMAXP; /* PIPEMAXP */ + volatile uint16_t PIPEPERI; /* PIPEPERI */ +#define USB20_PIPE1CTR_COUNT 0xF + volatile uint16_t PIPE1CTR; /* PIPE1CTR */ + volatile uint16_t PIPE2CTR; /* PIPE2CTR */ + volatile uint16_t PIPE3CTR; /* PIPE3CTR */ + volatile uint16_t PIPE4CTR; /* PIPE4CTR */ + volatile uint16_t PIPE5CTR; /* PIPE5CTR */ + volatile uint16_t PIPE6CTR; /* PIPE6CTR */ + volatile uint16_t PIPE7CTR; /* PIPE7CTR */ + volatile uint16_t PIPE8CTR; /* PIPE8CTR */ + volatile uint16_t PIPE9CTR; /* PIPE9CTR */ + volatile uint16_t PIPEACTR; /* PIPEACTR */ + volatile uint16_t PIPEBCTR; /* PIPEBCTR */ + volatile uint16_t PIPECCTR; /* PIPECCTR */ + volatile uint16_t PIPEDCTR; /* PIPEDCTR */ + volatile uint16_t PIPEECTR; /* PIPEECTR */ + volatile uint16_t PIPEFCTR; /* PIPEFCTR */ + volatile uint8_t dummy11[2]; /* */ +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE1TRE; /* PIPE1TRE */ + volatile uint16_t PIPE1TRN; /* PIPE1TRN */ +/* end of struct st_usb20_from_pipe1tre */ +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE2TRE; /* PIPE2TRE */ + volatile uint16_t PIPE2TRN; /* PIPE2TRN */ +/* end of struct st_usb20_from_pipe1tre */ +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE3TRE; /* PIPE3TRE */ + volatile uint16_t PIPE3TRN; /* PIPE3TRN */ +/* end of struct st_usb20_from_pipe1tre */ +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE4TRE; /* PIPE4TRE */ + volatile uint16_t PIPE4TRN; /* PIPE4TRN */ +/* end of struct st_usb20_from_pipe1tre */ +/* start of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPE5TRE; /* PIPE5TRE */ + volatile uint16_t PIPE5TRN; /* PIPE5TRN */ +/* end of struct st_usb20_from_pipe1tre */ + volatile uint16_t PIPEBTRE; /* PIPEBTRE */ + volatile uint16_t PIPEBTRN; /* PIPEBTRN */ + volatile uint16_t PIPECTRE; /* PIPECTRE */ + volatile uint16_t PIPECTRN; /* PIPECTRN */ + volatile uint16_t PIPEDTRE; /* PIPEDTRE */ + volatile uint16_t PIPEDTRN; /* PIPEDTRN */ + volatile uint16_t PIPEETRE; /* PIPEETRE */ + volatile uint16_t PIPEETRN; /* PIPEETRN */ + volatile uint16_t PIPEFTRE; /* PIPEFTRE */ + volatile uint16_t PIPEFTRN; /* PIPEFTRN */ + volatile uint16_t PIPE9TRE; /* PIPE9TRE */ + volatile uint16_t PIPE9TRN; /* PIPE9TRN */ + volatile uint16_t PIPEATRE; /* PIPEATRE */ + volatile uint16_t PIPEATRN; /* PIPEATRN */ + volatile uint8_t dummy12[16]; /* */ +#define USB20_DEVADD0_COUNT 0xB + volatile uint16_t DEVADD0; /* DEVADD0 */ + volatile uint16_t DEVADD1; /* DEVADD1 */ + volatile uint16_t DEVADD2; /* DEVADD2 */ + volatile uint16_t DEVADD3; /* DEVADD3 */ + volatile uint16_t DEVADD4; /* DEVADD4 */ + volatile uint16_t DEVADD5; /* DEVADD5 */ + volatile uint16_t DEVADD6; /* DEVADD6 */ + volatile uint16_t DEVADD7; /* DEVADD7 */ + volatile uint16_t DEVADD8; /* DEVADD8 */ + volatile uint16_t DEVADD9; /* DEVADD9 */ + volatile uint16_t DEVADDA; /* DEVADDA */ + volatile uint8_t dummy13[28]; /* */ + volatile uint16_t SUSPMODE; /* SUSPMODE */ + volatile uint8_t dummy14[92]; /* */ +/* start of struct st_usb20_from_dmfifob0 */ + volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ + volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ + volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ + volatile uint32_t D0FIFOB3; /* D0FIFOB3 */ + volatile uint32_t D0FIFOB4; /* D0FIFOB4 */ + volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ + volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ + volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ +/* end of struct st_usb20_from_dmfifob0 */ +/* start of struct st_usb20_from_dmfifob0 */ + volatile uint32_t D1FIFOB0; /* D1FIFOB0 */ + volatile uint32_t D1FIFOB1; /* D1FIFOB1 */ + volatile uint32_t D1FIFOB2; /* D1FIFOB2 */ + volatile uint32_t D1FIFOB3; /* D1FIFOB3 */ + volatile uint32_t D1FIFOB4; /* D1FIFOB4 */ + volatile uint32_t D1FIFOB5; /* D1FIFOB5 */ + volatile uint32_t D1FIFOB6; /* D1FIFOB6 */ + volatile uint32_t D1FIFOB7; /* D1FIFOB7 */ +/* end of struct st_usb20_from_dmfifob0 */ +}; + + +struct st_usb20_from_d0fifosel +{ + volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ + volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ +}; + + +struct st_usb20_from_pipe1tre +{ + volatile uint16_t PIPE1TRE; /* PIPE1TRE */ + volatile uint16_t PIPE1TRN; /* PIPE1TRN */ +}; + + +struct st_usb20_from_dmfifob0 +{ +#define USB20_D0FIFOB0_COUNT 0x8 + volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ + volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ + volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ + volatile uint32_t D0FIFOB3; /* D0FIFOB3 */ + volatile uint32_t D0FIFOB4; /* D0FIFOB4 */ + volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ + volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ + volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ +}; + + +#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */ +#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */ + + +/* Start of channnel array defines of USB20 */ + +/* Channnel array defines of USB20 */ +/*(Sample) value = USB20[ channel ]->SYSCFG0; */ +#define USB20_COUNT 2 +#define USB20_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &USB200, &USB201 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channnel array defines of USB20_FROM_D0FIFOB0 */ +/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */ +#define USB20_FROM_D0FIFOB0_COUNT 2 +#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \ + &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */ +#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */ +#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */ +#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */ + + + + +/* Channnel array defines of USB20_FROM_PIPE1ATRE */ +/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */ +#define USB20_FROM_PIPE1ATRE_COUNT 5 +#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \ + &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */ +#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */ +#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */ +#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */ +#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */ +#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */ +#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */ +#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */ +#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */ +#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */ + + + + +/* Channnel array defines of USB20_FROM_D0FIFOSEL */ +/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */ +#define USB20_FROM_D0FIFOSEL_COUNT 2 +#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \ + &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */ +#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */ +#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */ +#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */ + + +/* End of channnel array defines of USB20 */ + + +#define SYSCFG0_0 USB200.SYSCFG0 +#define BUSWAIT_0 USB200.BUSWAIT +#define SYSSTS0_0 USB200.SYSSTS0 +#define DVSTCTR0_0 USB200.DVSTCTR0 +#define TESTMODE_0 USB200.TESTMODE +#define D0FBCFG_0 USB200.D0FBCFG +#define D1FBCFG_0 USB200.D1FBCFG +#define CFIFO_0 USB200.CFIFO.UINT32 +#define CFIFO_0L USB200.CFIFO.UINT16[L] +#define CFIFO_0H USB200.CFIFO.UINT16[H] +#define CFIFO_0LL USB200.CFIFO.UINT8[LL] +#define CFIFO_0LH USB200.CFIFO.UINT8[LH] +#define CFIFO_0HL USB200.CFIFO.UINT8[HL] +#define CFIFO_0HH USB200.CFIFO.UINT8[HH] +#define D0FIFO_0 USB200.D0FIFO.UINT32 +#define D0FIFO_0L USB200.D0FIFO.UINT16[L] +#define D0FIFO_0H USB200.D0FIFO.UINT16[H] +#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL] +#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH] +#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL] +#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH] +#define D1FIFO_0 USB200.D1FIFO.UINT32 +#define D1FIFO_0L USB200.D1FIFO.UINT16[L] +#define D1FIFO_0H USB200.D1FIFO.UINT16[H] +#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL] +#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH] +#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL] +#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH] +#define CFIFOSEL_0 USB200.CFIFOSEL +#define CFIFOCTR_0 USB200.CFIFOCTR +#define D0FIFOSEL_0 USB200.D0FIFOSEL +#define D0FIFOCTR_0 USB200.D0FIFOCTR +#define D1FIFOSEL_0 USB200.D1FIFOSEL +#define D1FIFOCTR_0 USB200.D1FIFOCTR +#define INTENB0_0 USB200.INTENB0 +#define INTENB1_0 USB200.INTENB1 +#define BRDYENB_0 USB200.BRDYENB +#define NRDYENB_0 USB200.NRDYENB +#define BEMPENB_0 USB200.BEMPENB +#define SOFCFG_0 USB200.SOFCFG +#define INTSTS0_0 USB200.INTSTS0 +#define INTSTS1_0 USB200.INTSTS1 +#define BRDYSTS_0 USB200.BRDYSTS +#define NRDYSTS_0 USB200.NRDYSTS +#define BEMPSTS_0 USB200.BEMPSTS +#define FRMNUM_0 USB200.FRMNUM +#define UFRMNUM_0 USB200.UFRMNUM +#define USBADDR_0 USB200.USBADDR +#define USBREQ_0 USB200.USBREQ +#define USBVAL_0 USB200.USBVAL +#define USBINDX_0 USB200.USBINDX +#define USBLENG_0 USB200.USBLENG +#define DCPCFG_0 USB200.DCPCFG +#define DCPMAXP_0 USB200.DCPMAXP +#define DCPCTR_0 USB200.DCPCTR +#define PIPESEL_0 USB200.PIPESEL +#define PIPECFG_0 USB200.PIPECFG +#define PIPEBUF_0 USB200.PIPEBUF +#define PIPEMAXP_0 USB200.PIPEMAXP +#define PIPEPERI_0 USB200.PIPEPERI +#define PIPE1CTR_0 USB200.PIPE1CTR +#define PIPE2CTR_0 USB200.PIPE2CTR +#define PIPE3CTR_0 USB200.PIPE3CTR +#define PIPE4CTR_0 USB200.PIPE4CTR +#define PIPE5CTR_0 USB200.PIPE5CTR +#define PIPE6CTR_0 USB200.PIPE6CTR +#define PIPE7CTR_0 USB200.PIPE7CTR +#define PIPE8CTR_0 USB200.PIPE8CTR +#define PIPE9CTR_0 USB200.PIPE9CTR +#define PIPEACTR_0 USB200.PIPEACTR +#define PIPEBCTR_0 USB200.PIPEBCTR +#define PIPECCTR_0 USB200.PIPECCTR +#define PIPEDCTR_0 USB200.PIPEDCTR +#define PIPEECTR_0 USB200.PIPEECTR +#define PIPEFCTR_0 USB200.PIPEFCTR +#define PIPE1TRE_0 USB200.PIPE1TRE +#define PIPE1TRN_0 USB200.PIPE1TRN +#define PIPE2TRE_0 USB200.PIPE2TRE +#define PIPE2TRN_0 USB200.PIPE2TRN +#define PIPE3TRE_0 USB200.PIPE3TRE +#define PIPE3TRN_0 USB200.PIPE3TRN +#define PIPE4TRE_0 USB200.PIPE4TRE +#define PIPE4TRN_0 USB200.PIPE4TRN +#define PIPE5TRE_0 USB200.PIPE5TRE +#define PIPE5TRN_0 USB200.PIPE5TRN +#define PIPEBTRE_0 USB200.PIPEBTRE +#define PIPEBTRN_0 USB200.PIPEBTRN +#define PIPECTRE_0 USB200.PIPECTRE +#define PIPECTRN_0 USB200.PIPECTRN +#define PIPEDTRE_0 USB200.PIPEDTRE +#define PIPEDTRN_0 USB200.PIPEDTRN +#define PIPEETRE_0 USB200.PIPEETRE +#define PIPEETRN_0 USB200.PIPEETRN +#define PIPEFTRE_0 USB200.PIPEFTRE +#define PIPEFTRN_0 USB200.PIPEFTRN +#define PIPE9TRE_0 USB200.PIPE9TRE +#define PIPE9TRN_0 USB200.PIPE9TRN +#define PIPEATRE_0 USB200.PIPEATRE +#define PIPEATRN_0 USB200.PIPEATRN +#define DEVADD0_0 USB200.DEVADD0 +#define DEVADD1_0 USB200.DEVADD1 +#define DEVADD2_0 USB200.DEVADD2 +#define DEVADD3_0 USB200.DEVADD3 +#define DEVADD4_0 USB200.DEVADD4 +#define DEVADD5_0 USB200.DEVADD5 +#define DEVADD6_0 USB200.DEVADD6 +#define DEVADD7_0 USB200.DEVADD7 +#define DEVADD8_0 USB200.DEVADD8 +#define DEVADD9_0 USB200.DEVADD9 +#define DEVADDA_0 USB200.DEVADDA +#define SUSPMODE_0 USB200.SUSPMODE +#define D0FIFOB0_0 USB200.D0FIFOB0 +#define D0FIFOB1_0 USB200.D0FIFOB1 +#define D0FIFOB2_0 USB200.D0FIFOB2 +#define D0FIFOB3_0 USB200.D0FIFOB3 +#define D0FIFOB4_0 USB200.D0FIFOB4 +#define D0FIFOB5_0 USB200.D0FIFOB5 +#define D0FIFOB6_0 USB200.D0FIFOB6 +#define D0FIFOB7_0 USB200.D0FIFOB7 +#define D1FIFOB0_0 USB200.D1FIFOB0 +#define D1FIFOB1_0 USB200.D1FIFOB1 +#define D1FIFOB2_0 USB200.D1FIFOB2 +#define D1FIFOB3_0 USB200.D1FIFOB3 +#define D1FIFOB4_0 USB200.D1FIFOB4 +#define D1FIFOB5_0 USB200.D1FIFOB5 +#define D1FIFOB6_0 USB200.D1FIFOB6 +#define D1FIFOB7_0 USB200.D1FIFOB7 +#define SYSCFG0_1 USB201.SYSCFG0 +#define BUSWAIT_1 USB201.BUSWAIT +#define SYSSTS0_1 USB201.SYSSTS0 +#define DVSTCTR0_1 USB201.DVSTCTR0 +#define TESTMODE_1 USB201.TESTMODE +#define D0FBCFG_1 USB201.D0FBCFG +#define D1FBCFG_1 USB201.D1FBCFG +#define CFIFO_1 USB201.CFIFO.UINT32 +#define CFIFO_1L USB201.CFIFO.UINT16[L] +#define CFIFO_1H USB201.CFIFO.UINT16[H] +#define CFIFO_1LL USB201.CFIFO.UINT8[LL] +#define CFIFO_1LH USB201.CFIFO.UINT8[LH] +#define CFIFO_1HL USB201.CFIFO.UINT8[HL] +#define CFIFO_1HH USB201.CFIFO.UINT8[HH] +#define D0FIFO_1 USB201.D0FIFO.UINT32 +#define D0FIFO_1L USB201.D0FIFO.UINT16[L] +#define D0FIFO_1H USB201.D0FIFO.UINT16[H] +#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL] +#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH] +#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL] +#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH] +#define D1FIFO_1 USB201.D1FIFO.UINT32 +#define D1FIFO_1L USB201.D1FIFO.UINT16[L] +#define D1FIFO_1H USB201.D1FIFO.UINT16[H] +#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL] +#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH] +#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL] +#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH] +#define CFIFOSEL_1 USB201.CFIFOSEL +#define CFIFOCTR_1 USB201.CFIFOCTR +#define D0FIFOSEL_1 USB201.D0FIFOSEL +#define D0FIFOCTR_1 USB201.D0FIFOCTR +#define D1FIFOSEL_1 USB201.D1FIFOSEL +#define D1FIFOCTR_1 USB201.D1FIFOCTR +#define INTENB0_1 USB201.INTENB0 +#define INTENB1_1 USB201.INTENB1 +#define BRDYENB_1 USB201.BRDYENB +#define NRDYENB_1 USB201.NRDYENB +#define BEMPENB_1 USB201.BEMPENB +#define SOFCFG_1 USB201.SOFCFG +#define INTSTS0_1 USB201.INTSTS0 +#define INTSTS1_1 USB201.INTSTS1 +#define BRDYSTS_1 USB201.BRDYSTS +#define NRDYSTS_1 USB201.NRDYSTS +#define BEMPSTS_1 USB201.BEMPSTS +#define FRMNUM_1 USB201.FRMNUM +#define UFRMNUM_1 USB201.UFRMNUM +#define USBADDR_1 USB201.USBADDR +#define USBREQ_1 USB201.USBREQ +#define USBVAL_1 USB201.USBVAL +#define USBINDX_1 USB201.USBINDX +#define USBLENG_1 USB201.USBLENG +#define DCPCFG_1 USB201.DCPCFG +#define DCPMAXP_1 USB201.DCPMAXP +#define DCPCTR_1 USB201.DCPCTR +#define PIPESEL_1 USB201.PIPESEL +#define PIPECFG_1 USB201.PIPECFG +#define PIPEBUF_1 USB201.PIPEBUF +#define PIPEMAXP_1 USB201.PIPEMAXP +#define PIPEPERI_1 USB201.PIPEPERI +#define PIPE1CTR_1 USB201.PIPE1CTR +#define PIPE2CTR_1 USB201.PIPE2CTR +#define PIPE3CTR_1 USB201.PIPE3CTR +#define PIPE4CTR_1 USB201.PIPE4CTR +#define PIPE5CTR_1 USB201.PIPE5CTR +#define PIPE6CTR_1 USB201.PIPE6CTR +#define PIPE7CTR_1 USB201.PIPE7CTR +#define PIPE8CTR_1 USB201.PIPE8CTR +#define PIPE9CTR_1 USB201.PIPE9CTR +#define PIPEACTR_1 USB201.PIPEACTR +#define PIPEBCTR_1 USB201.PIPEBCTR +#define PIPECCTR_1 USB201.PIPECCTR +#define PIPEDCTR_1 USB201.PIPEDCTR +#define PIPEECTR_1 USB201.PIPEECTR +#define PIPEFCTR_1 USB201.PIPEFCTR +#define PIPE1TRE_1 USB201.PIPE1TRE +#define PIPE1TRN_1 USB201.PIPE1TRN +#define PIPE2TRE_1 USB201.PIPE2TRE +#define PIPE2TRN_1 USB201.PIPE2TRN +#define PIPE3TRE_1 USB201.PIPE3TRE +#define PIPE3TRN_1 USB201.PIPE3TRN +#define PIPE4TRE_1 USB201.PIPE4TRE +#define PIPE4TRN_1 USB201.PIPE4TRN +#define PIPE5TRE_1 USB201.PIPE5TRE +#define PIPE5TRN_1 USB201.PIPE5TRN +#define PIPEBTRE_1 USB201.PIPEBTRE +#define PIPEBTRN_1 USB201.PIPEBTRN +#define PIPECTRE_1 USB201.PIPECTRE +#define PIPECTRN_1 USB201.PIPECTRN +#define PIPEDTRE_1 USB201.PIPEDTRE +#define PIPEDTRN_1 USB201.PIPEDTRN +#define PIPEETRE_1 USB201.PIPEETRE +#define PIPEETRN_1 USB201.PIPEETRN +#define PIPEFTRE_1 USB201.PIPEFTRE +#define PIPEFTRN_1 USB201.PIPEFTRN +#define PIPE9TRE_1 USB201.PIPE9TRE +#define PIPE9TRN_1 USB201.PIPE9TRN +#define PIPEATRE_1 USB201.PIPEATRE +#define PIPEATRN_1 USB201.PIPEATRN +#define DEVADD0_1 USB201.DEVADD0 +#define DEVADD1_1 USB201.DEVADD1 +#define DEVADD2_1 USB201.DEVADD2 +#define DEVADD3_1 USB201.DEVADD3 +#define DEVADD4_1 USB201.DEVADD4 +#define DEVADD5_1 USB201.DEVADD5 +#define DEVADD6_1 USB201.DEVADD6 +#define DEVADD7_1 USB201.DEVADD7 +#define DEVADD8_1 USB201.DEVADD8 +#define DEVADD9_1 USB201.DEVADD9 +#define DEVADDA_1 USB201.DEVADDA +#define SUSPMODE_1 USB201.SUSPMODE +#define D0FIFOB0_1 USB201.D0FIFOB0 +#define D0FIFOB1_1 USB201.D0FIFOB1 +#define D0FIFOB2_1 USB201.D0FIFOB2 +#define D0FIFOB3_1 USB201.D0FIFOB3 +#define D0FIFOB4_1 USB201.D0FIFOB4 +#define D0FIFOB5_1 USB201.D0FIFOB5 +#define D0FIFOB6_1 USB201.D0FIFOB6 +#define D0FIFOB7_1 USB201.D0FIFOB7 +#define D1FIFOB0_1 USB201.D1FIFOB0 +#define D1FIFOB1_1 USB201.D1FIFOB1 +#define D1FIFOB2_1 USB201.D1FIFOB2 +#define D1FIFOB3_1 USB201.D1FIFOB3 +#define D1FIFOB4_1 USB201.D1FIFOB4 +#define D1FIFOB5_1 USB201.D1FIFOB5 +#define D1FIFOB6_1 USB201.D1FIFOB6 +#define D1FIFOB7_1 USB201.D1FIFOB7 +/* <-SEC M1.10.1 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/vdc5_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/vdc5_iodefine.h new file mode 100644 index 0000000000..d20922524e --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/vdc5_iodefine.h @@ -0,0 +1,1596 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : vdc5_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef VDC5_IODEFINE_H +#define VDC5_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->SEC M1.10.1 : Not magic number */ + +struct st_vdc5 +{ /* VDC5 */ + volatile uint32_t INP_UPDATE; /* INP_UPDATE */ + volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */ + volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */ + volatile uint32_t INP_VSYNC_PH_ADJ; /* INP_VSYNC_PH_ADJ */ + volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */ + volatile uint8_t dummy1[108]; /* */ + volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */ +#define VDC5_IMGCNT_NR_CNT0_COUNT 2 + volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */ + volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */ + volatile uint8_t dummy2[20]; /* */ + volatile uint32_t IMGCNT_MTX_MODE; /* IMGCNT_MTX_MODE */ + volatile uint32_t IMGCNT_MTX_YG_ADJ0; /* IMGCNT_MTX_YG_ADJ0 */ + volatile uint32_t IMGCNT_MTX_YG_ADJ1; /* IMGCNT_MTX_YG_ADJ1 */ + volatile uint32_t IMGCNT_MTX_CBB_ADJ0; /* IMGCNT_MTX_CBB_ADJ0 */ + volatile uint32_t IMGCNT_MTX_CBB_ADJ1; /* IMGCNT_MTX_CBB_ADJ1 */ + volatile uint32_t IMGCNT_MTX_CRR_ADJ0; /* IMGCNT_MTX_CRR_ADJ0 */ + volatile uint32_t IMGCNT_MTX_CRR_ADJ1; /* IMGCNT_MTX_CRR_ADJ1 */ + volatile uint8_t dummy3[4]; /* */ + volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */ + volatile uint8_t dummy4[60]; /* */ +/* start of struct st_vdc5_from_sc0_scl0_update */ + volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ +#define VDC5_SC0_SCL0_FRC1_COUNT 7 + volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ + volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ + volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ + volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */ + volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */ + volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */ + volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */ + volatile uint8_t dummy5[4]; /* */ + volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ + volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ + volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ +#define VDC5_SC0_SCL0_DS1_COUNT 7 + volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ + volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ + volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ + volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */ + volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ + volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ + volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ +#define VDC5_SC0_SCL0_US1_COUNT 8 + volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ + volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ + volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ + volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */ + volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */ + volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */ + volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */ + volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */ + volatile uint8_t dummy6[4]; /* */ + volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */ + volatile uint8_t dummy7[16]; /* */ + volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ + volatile uint8_t dummy8[4]; /* */ +#define VDC5_SC0_SCL1_WR1_COUNT 4 + volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ + volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ + volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ + volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */ + volatile uint8_t dummy9[4]; /* */ + volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */ + volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */ + volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */ + volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ + volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ + volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ +/* end of struct st_vdc5_from_sc0_scl0_update */ + volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */ + volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */ +/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ +#define VDC5_SC0_SCL1_PBUF0_COUNT 4 + volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ + volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ + volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ + volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ + volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ + volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ +/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ + volatile uint8_t dummy10[44]; /* */ +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ + volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ +#define VDC5_GR0_FLM1_COUNT 6 + volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ + volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ + volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ + volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ + volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ + volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ +#define VDC5_GR0_AB1_COUNT 3 + volatile uint32_t GR0_AB1; /* GR0_AB1 */ + volatile uint32_t GR0_AB2; /* GR0_AB2 */ + volatile uint32_t GR0_AB3; /* GR0_AB3 */ +/* end of struct st_vdc5_from_gr0_update */ + volatile uint8_t dummy11[12]; /* */ +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR0_AB7; /* GR0_AB7 */ + volatile uint32_t GR0_AB8; /* GR0_AB8 */ + volatile uint32_t GR0_AB9; /* GR0_AB9 */ + volatile uint32_t GR0_AB10; /* GR0_AB10 */ + volatile uint32_t GR0_AB11; /* GR0_AB11 */ + volatile uint32_t GR0_BASE; /* GR0_BASE */ +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR0_CLUT; /* GR0_CLUT */ + volatile uint8_t dummy12[44]; /* */ +/* start of struct st_vdc5_from_adj0_update */ + volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ + volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ +#define VDC5_ADJ0_ENH_TIM1_COUNT 3 + volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ + volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ + volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ +#define VDC5_ADJ0_ENH_SHP1_COUNT 6 + volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ + volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ + volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ + volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ + volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ + volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ +#define VDC5_ADJ0_ENH_LTI1_COUNT 2 + volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ + volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ + volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ + volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */ + volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */ + volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */ + volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ + volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ + volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ +/* end of struct st_vdc5_from_adj0_update */ + volatile uint8_t dummy13[48]; /* */ +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */ + volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */ +#define VDC5_GR2_FLM1_COUNT 6 + volatile uint32_t GR2_FLM1; /* GR2_FLM1 */ + volatile uint32_t GR2_FLM2; /* GR2_FLM2 */ + volatile uint32_t GR2_FLM3; /* GR2_FLM3 */ + volatile uint32_t GR2_FLM4; /* GR2_FLM4 */ + volatile uint32_t GR2_FLM5; /* GR2_FLM5 */ + volatile uint32_t GR2_FLM6; /* GR2_FLM6 */ +#define VDC5_GR2_AB1_COUNT 3 + volatile uint32_t GR2_AB1; /* GR2_AB1 */ + volatile uint32_t GR2_AB2; /* GR2_AB2 */ + volatile uint32_t GR2_AB3; /* GR2_AB3 */ +/* end of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR2_AB4; /* GR2_AB4 */ + volatile uint32_t GR2_AB5; /* GR2_AB5 */ + volatile uint32_t GR2_AB6; /* GR2_AB6 */ +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR2_AB7; /* GR2_AB7 */ + volatile uint32_t GR2_AB8; /* GR2_AB8 */ + volatile uint32_t GR2_AB9; /* GR2_AB9 */ + volatile uint32_t GR2_AB10; /* GR2_AB10 */ + volatile uint32_t GR2_AB11; /* GR2_AB11 */ + volatile uint32_t GR2_BASE; /* GR2_BASE */ +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR2_CLUT; /* GR2_CLUT */ + volatile uint32_t GR2_MON; /* GR2_MON */ + volatile uint8_t dummy14[40]; /* */ +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */ + volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */ +#define VDC5_GR3_FLM1_COUNT 6 + volatile uint32_t GR3_FLM1; /* GR3_FLM1 */ + volatile uint32_t GR3_FLM2; /* GR3_FLM2 */ + volatile uint32_t GR3_FLM3; /* GR3_FLM3 */ + volatile uint32_t GR3_FLM4; /* GR3_FLM4 */ + volatile uint32_t GR3_FLM5; /* GR3_FLM5 */ + volatile uint32_t GR3_FLM6; /* GR3_FLM6 */ +#define VDC5_GR3_AB1_COUNT 3 + volatile uint32_t GR3_AB1; /* GR3_AB1 */ + volatile uint32_t GR3_AB2; /* GR3_AB2 */ + volatile uint32_t GR3_AB3; /* GR3_AB3 */ +/* end of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR3_AB4; /* GR3_AB4 */ + volatile uint32_t GR3_AB5; /* GR3_AB5 */ + volatile uint32_t GR3_AB6; /* GR3_AB6 */ +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR3_AB7; /* GR3_AB7 */ + volatile uint32_t GR3_AB8; /* GR3_AB8 */ + volatile uint32_t GR3_AB9; /* GR3_AB9 */ + volatile uint32_t GR3_AB10; /* GR3_AB10 */ + volatile uint32_t GR3_AB11; /* GR3_AB11 */ + volatile uint32_t GR3_BASE; /* GR3_BASE */ +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */ + volatile uint32_t GR3_MON; /* GR3_MON */ + volatile uint8_t dummy15[40]; /* */ + volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */ + volatile uint32_t GAM_SW; /* GAM_SW */ +#define VDC5_GAM_G_LUT1_COUNT 16 + volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */ + volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */ + volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */ + volatile uint32_t GAM_G_LUT4; /* GAM_G_LUT4 */ + volatile uint32_t GAM_G_LUT5; /* GAM_G_LUT5 */ + volatile uint32_t GAM_G_LUT6; /* GAM_G_LUT6 */ + volatile uint32_t GAM_G_LUT7; /* GAM_G_LUT7 */ + volatile uint32_t GAM_G_LUT8; /* GAM_G_LUT8 */ + volatile uint32_t GAM_G_LUT9; /* GAM_G_LUT9 */ + volatile uint32_t GAM_G_LUT10; /* GAM_G_LUT10 */ + volatile uint32_t GAM_G_LUT11; /* GAM_G_LUT11 */ + volatile uint32_t GAM_G_LUT12; /* GAM_G_LUT12 */ + volatile uint32_t GAM_G_LUT13; /* GAM_G_LUT13 */ + volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */ + volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */ + volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */ +#define VDC5_GAM_G_AREA1_COUNT 8 + volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */ + volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */ + volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */ + volatile uint32_t GAM_G_AREA4; /* GAM_G_AREA4 */ + volatile uint32_t GAM_G_AREA5; /* GAM_G_AREA5 */ + volatile uint32_t GAM_G_AREA6; /* GAM_G_AREA6 */ + volatile uint32_t GAM_G_AREA7; /* GAM_G_AREA7 */ + volatile uint32_t GAM_G_AREA8; /* GAM_G_AREA8 */ + volatile uint8_t dummy16[24]; /* */ + volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */ + volatile uint8_t dummy17[4]; /* */ +#define VDC5_GAM_B_LUT1_COUNT 16 + volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */ + volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */ + volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */ + volatile uint32_t GAM_B_LUT4; /* GAM_B_LUT4 */ + volatile uint32_t GAM_B_LUT5; /* GAM_B_LUT5 */ + volatile uint32_t GAM_B_LUT6; /* GAM_B_LUT6 */ + volatile uint32_t GAM_B_LUT7; /* GAM_B_LUT7 */ + volatile uint32_t GAM_B_LUT8; /* GAM_B_LUT8 */ + volatile uint32_t GAM_B_LUT9; /* GAM_B_LUT9 */ + volatile uint32_t GAM_B_LUT10; /* GAM_B_LUT10 */ + volatile uint32_t GAM_B_LUT11; /* GAM_B_LUT11 */ + volatile uint32_t GAM_B_LUT12; /* GAM_B_LUT12 */ + volatile uint32_t GAM_B_LUT13; /* GAM_B_LUT13 */ + volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */ + volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */ + volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */ +#define VDC5_GAM_B_AREA1_COUNT 8 + volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */ + volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */ + volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */ + volatile uint32_t GAM_B_AREA4; /* GAM_B_AREA4 */ + volatile uint32_t GAM_B_AREA5; /* GAM_B_AREA5 */ + volatile uint32_t GAM_B_AREA6; /* GAM_B_AREA6 */ + volatile uint32_t GAM_B_AREA7; /* GAM_B_AREA7 */ + volatile uint32_t GAM_B_AREA8; /* GAM_B_AREA8 */ + volatile uint8_t dummy18[24]; /* */ + volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */ + volatile uint8_t dummy19[4]; /* */ +#define VDC5_GAM_R_LUT1_COUNT 16 + volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */ + volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */ + volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */ + volatile uint32_t GAM_R_LUT4; /* GAM_R_LUT4 */ + volatile uint32_t GAM_R_LUT5; /* GAM_R_LUT5 */ + volatile uint32_t GAM_R_LUT6; /* GAM_R_LUT6 */ + volatile uint32_t GAM_R_LUT7; /* GAM_R_LUT7 */ + volatile uint32_t GAM_R_LUT8; /* GAM_R_LUT8 */ + volatile uint32_t GAM_R_LUT9; /* GAM_R_LUT9 */ + volatile uint32_t GAM_R_LUT10; /* GAM_R_LUT10 */ + volatile uint32_t GAM_R_LUT11; /* GAM_R_LUT11 */ + volatile uint32_t GAM_R_LUT12; /* GAM_R_LUT12 */ + volatile uint32_t GAM_R_LUT13; /* GAM_R_LUT13 */ + volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */ + volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */ + volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */ +#define VDC5_GAM_R_AREA1_COUNT 8 + volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */ + volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */ + volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */ + volatile uint32_t GAM_R_AREA4; /* GAM_R_AREA4 */ + volatile uint32_t GAM_R_AREA5; /* GAM_R_AREA5 */ + volatile uint32_t GAM_R_AREA6; /* GAM_R_AREA6 */ + volatile uint32_t GAM_R_AREA7; /* GAM_R_AREA7 */ + volatile uint32_t GAM_R_AREA8; /* GAM_R_AREA8 */ + volatile uint8_t dummy20[24]; /* */ + volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */ + volatile uint32_t TCON_TIM; /* TCON_TIM */ +#define VDC5_TCON_TIM_STVA1_COUNT 2 + volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */ + volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */ +#define VDC5_TCON_TIM_STVB1_COUNT 2 + volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */ + volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */ +#define VDC5_TCON_TIM_STH1_COUNT 2 + volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */ + volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */ +#define VDC5_TCON_TIM_STB1_COUNT 2 + volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */ + volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */ +#define VDC5_TCON_TIM_CPV1_COUNT 2 + volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */ + volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */ +#define VDC5_TCON_TIM_POLA1_COUNT 2 + volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */ + volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */ +#define VDC5_TCON_TIM_POLB1_COUNT 2 + volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */ + volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */ + volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */ + volatile uint8_t dummy21[60]; /* */ + volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */ + volatile uint32_t OUT_SET; /* OUT_SET */ +#define VDC5_OUT_BRIGHT1_COUNT 2 + volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */ + volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */ + volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */ + volatile uint32_t OUT_PDTHA; /* OUT_PDTHA */ + volatile uint8_t dummy22[12]; /* */ + volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */ + volatile uint8_t dummy23[88]; /* */ +#define VDC5_SYSCNT_INT1_COUNT 6 + volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */ + volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */ + volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */ + volatile uint32_t SYSCNT_INT4; /* SYSCNT_INT4 */ + volatile uint32_t SYSCNT_INT5; /* SYSCNT_INT5 */ + volatile uint32_t SYSCNT_INT6; /* SYSCNT_INT6 */ + volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */ + volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */ + volatile uint8_t dummy24[356]; /* */ +/* start of struct st_vdc5_from_sc0_scl0_update */ + volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */ +#define VDC5_SC1_SCL0_FRC1_COUNT 7 + volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */ + volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */ + volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */ + volatile uint32_t SC1_SCL0_FRC4; /* SC1_SCL0_FRC4 */ + volatile uint32_t SC1_SCL0_FRC5; /* SC1_SCL0_FRC5 */ + volatile uint32_t SC1_SCL0_FRC6; /* SC1_SCL0_FRC6 */ + volatile uint32_t SC1_SCL0_FRC7; /* SC1_SCL0_FRC7 */ + volatile uint8_t dummy25[4]; /* */ + volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */ + volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */ + volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */ +#define VDC5_SC1_SC1_SCL0_DS1_COUNT 7 + volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */ + volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */ + volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */ + volatile uint32_t SC1_SCL0_DS4; /* SC1_SCL0_DS4 */ + volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */ + volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */ + volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */ +#define VDC5_SC1_SC1_SCL0_US1_COUNT 8 + volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */ + volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */ + volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */ + volatile uint32_t SC1_SCL0_US4; /* SC1_SCL0_US4 */ + volatile uint32_t SC1_SCL0_US5; /* SC1_SCL0_US5 */ + volatile uint32_t SC1_SCL0_US6; /* SC1_SCL0_US6 */ + volatile uint32_t SC1_SCL0_US7; /* SC1_SCL0_US7 */ + volatile uint32_t SC1_SCL0_US8; /* SC1_SCL0_US8 */ + volatile uint8_t dummy26[4]; /* */ + volatile uint32_t SC1_SCL0_OVR1; /* SC1_SCL0_OVR1 */ + volatile uint8_t dummy27[16]; /* */ + volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */ + volatile uint8_t dummy28[4]; /* */ +#define VDC5_SC1_SCL1_WR1_COUNT 4 + volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */ + volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */ + volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */ + volatile uint32_t SC1_SCL1_WR4; /* SC1_SCL1_WR4 */ + volatile uint8_t dummy29[4]; /* */ + volatile uint32_t SC1_SCL1_WR5; /* SC1_SCL1_WR5 */ + volatile uint32_t SC1_SCL1_WR6; /* SC1_SCL1_WR6 */ + volatile uint32_t SC1_SCL1_WR7; /* SC1_SCL1_WR7 */ + volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */ + volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */ + volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */ +/* end of struct st_vdc5_from_sc0_scl0_update */ + volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */ + volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */ +/* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ +#define VDC5_SC1_SCL1_PBUF0_COUNT 4 + volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */ + volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */ + volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */ + volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */ + volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */ + volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */ +/* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ + volatile uint8_t dummy30[44]; /* */ +/* start of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */ + volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */ +#define VDC5_GR1_FLM1_COUNT 6 + volatile uint32_t GR1_FLM1; /* GR1_FLM1 */ + volatile uint32_t GR1_FLM2; /* GR1_FLM2 */ + volatile uint32_t GR1_FLM3; /* GR1_FLM3 */ + volatile uint32_t GR1_FLM4; /* GR1_FLM4 */ + volatile uint32_t GR1_FLM5; /* GR1_FLM5 */ + volatile uint32_t GR1_FLM6; /* GR1_FLM6 */ +#define VDC5_GR1_AB1_COUNT 3 + volatile uint32_t GR1_AB1; /* GR1_AB1 */ + volatile uint32_t GR1_AB2; /* GR1_AB2 */ + volatile uint32_t GR1_AB3; /* GR1_AB3 */ +/* end of struct st_vdc5_from_gr0_update */ + volatile uint32_t GR1_AB4; /* GR1_AB4 */ + volatile uint32_t GR1_AB5; /* GR1_AB5 */ + volatile uint32_t GR1_AB6; /* GR1_AB6 */ +/* start of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR1_AB7; /* GR1_AB7 */ + volatile uint32_t GR1_AB8; /* GR1_AB8 */ + volatile uint32_t GR1_AB9; /* GR1_AB9 */ + volatile uint32_t GR1_AB10; /* GR1_AB10 */ + volatile uint32_t GR1_AB11; /* GR1_AB11 */ + volatile uint32_t GR1_BASE; /* GR1_BASE */ +/* end of struct st_vdc5_from_gr0_ab7 */ + volatile uint32_t GR1_CLUT; /* GR1_CLUT */ + volatile uint32_t GR1_MON; /* GR1_MON */ + volatile uint8_t dummy31[40]; /* */ +/* start of struct st_vdc5_from_adj0_update */ + volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */ + volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */ +#define VDC5_ADJ1_ENH_TIM1_COUNT 3 + volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */ + volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */ + volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */ +#define VDC5_ADJ1_ENH_SHP1_COUNT 6 + volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */ + volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */ + volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */ + volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */ + volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */ + volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */ +#define VDC5_ADJ1_ENH_LTI1_COUNT 2 + volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */ + volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */ + volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */ + volatile uint32_t ADJ1_MTX_YG_ADJ0; /* ADJ1_MTX_YG_ADJ0 */ + volatile uint32_t ADJ1_MTX_YG_ADJ1; /* ADJ1_MTX_YG_ADJ1 */ + volatile uint32_t ADJ1_MTX_CBB_ADJ0; /* ADJ1_MTX_CBB_ADJ0 */ + volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */ + volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */ + volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */ +/* end of struct st_vdc5_from_adj0_update */ + volatile uint8_t dummy32[48]; /* */ + volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */ + volatile uint8_t dummy33[28]; /* */ +#define VDC5_GR_VIN_AB1_COUNT 7 + volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */ + volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */ + volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */ + volatile uint32_t GR_VIN_AB4; /* GR_VIN_AB4 */ + volatile uint32_t GR_VIN_AB5; /* GR_VIN_AB5 */ + volatile uint32_t GR_VIN_AB6; /* GR_VIN_AB6 */ + volatile uint32_t GR_VIN_AB7; /* GR_VIN_AB7 */ + volatile uint8_t dummy34[16]; /* */ + volatile uint32_t GR_VIN_BASE; /* GR_VIN_BASE */ + volatile uint8_t dummy35[4]; /* */ + volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */ + volatile uint8_t dummy36[40]; /* */ + volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */ +#define VDC5_OIR_SCL0_FRC1_COUNT 7 + volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */ + volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */ + volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */ + volatile uint32_t OIR_SCL0_FRC4; /* OIR_SCL0_FRC4 */ + volatile uint32_t OIR_SCL0_FRC5; /* OIR_SCL0_FRC5 */ + volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */ + volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */ + volatile uint8_t dummy37[12]; /* */ +#define VDC5_OIR_SCL0_DS1_COUNT 3 + volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */ + volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */ + volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */ + volatile uint8_t dummy38[12]; /* */ + volatile uint32_t OIR_SCL0_DS7; /* OIR_SCL0_DS7 */ + volatile uint32_t OIR_SCL0_US1; /* OIR_SCL0_US1 */ + volatile uint32_t OIR_SCL0_US2; /* OIR_SCL0_US2 */ + volatile uint32_t OIR_SCL0_US3; /* OIR_SCL0_US3 */ + volatile uint8_t dummy39[16]; /* */ + volatile uint32_t OIR_SCL0_US8; /* OIR_SCL0_US8 */ + volatile uint8_t dummy40[4]; /* */ + volatile uint32_t OIR_SCL0_OVR1; /* OIR_SCL0_OVR1 */ + volatile uint8_t dummy41[16]; /* */ + volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */ + volatile uint8_t dummy42[4]; /* */ +#define VDC5_OIR_SCL1_WR1_COUNT 4 + volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */ + volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */ + volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */ + volatile uint32_t OIR_SCL1_WR4; /* OIR_SCL1_WR4 */ + volatile uint8_t dummy43[4]; /* */ + volatile uint32_t OIR_SCL1_WR5; /* OIR_SCL1_WR5 */ + volatile uint32_t OIR_SCL1_WR6; /* OIR_SCL1_WR6 */ + volatile uint32_t OIR_SCL1_WR7; /* OIR_SCL1_WR7 */ + volatile uint8_t dummy44[88]; /* */ + volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */ + volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */ +#define VDC5_GR_OIR_FLM1_COUNT 6 + volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */ + volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */ + volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */ + volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */ + volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */ + volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */ +#define VDC5_GR_OIR_AB1_COUNT 3 + volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */ + volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */ + volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */ + volatile uint8_t dummy45[12]; /* */ + volatile uint32_t GR_OIR_AB7; /* GR_OIR_AB7 */ + volatile uint32_t GR_OIR_AB8; /* GR_OIR_AB8 */ + volatile uint32_t GR_OIR_AB9; /* GR_OIR_AB9 */ + volatile uint32_t GR_OIR_AB10; /* GR_OIR_AB10 */ + volatile uint32_t GR_OIR_AB11; /* GR_OIR_AB11 */ + volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */ + volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */ + volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */ +}; + + +struct st_vdc5_from_gr0_update +{ + volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ + volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ + volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ + volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ + volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ + volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ + volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ + volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ + volatile uint32_t GR0_AB1; /* GR0_AB1 */ + volatile uint32_t GR0_AB2; /* GR0_AB2 */ + volatile uint32_t GR0_AB3; /* GR0_AB3 */ +}; + + +struct st_vdc5_from_gr0_ab7 +{ + volatile uint32_t GR0_AB7; /* GR0_AB7 */ + volatile uint32_t GR0_AB8; /* GR0_AB8 */ + volatile uint32_t GR0_AB9; /* GR0_AB9 */ + volatile uint32_t GR0_AB10; /* GR0_AB10 */ + volatile uint32_t GR0_AB11; /* GR0_AB11 */ + volatile uint32_t GR0_BASE; /* GR0_BASE */ +}; + + +struct st_vdc5_from_adj0_update +{ + volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ + volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ + volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ + volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ + volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ + volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ + volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ + volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ + volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ + volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ + volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ + volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ + volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ + volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ + volatile uint32_t ADJ0_MTX_YG_ADJ0; /* ADJ0_MTX_YG_ADJ0 */ + volatile uint32_t ADJ0_MTX_YG_ADJ1; /* ADJ0_MTX_YG_ADJ1 */ + volatile uint32_t ADJ0_MTX_CBB_ADJ0; /* ADJ0_MTX_CBB_ADJ0 */ + volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ + volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ + volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ +}; + + +struct st_vdc5_from_sc0_scl0_update +{ + volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ + volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ + volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ + volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ + volatile uint32_t SC0_SCL0_FRC4; /* SC0_SCL0_FRC4 */ + volatile uint32_t SC0_SCL0_FRC5; /* SC0_SCL0_FRC5 */ + volatile uint32_t SC0_SCL0_FRC6; /* SC0_SCL0_FRC6 */ + volatile uint32_t SC0_SCL0_FRC7; /* SC0_SCL0_FRC7 */ + volatile uint8_t dummy5[4]; /* */ + volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ + volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ + volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ + volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ + volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ + volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ + volatile uint32_t SC0_SCL0_DS4; /* SC0_SCL0_DS4 */ + volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ + volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ + volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ + volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ + volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ + volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ + volatile uint32_t SC0_SCL0_US4; /* SC0_SCL0_US4 */ + volatile uint32_t SC0_SCL0_US5; /* SC0_SCL0_US5 */ + volatile uint32_t SC0_SCL0_US6; /* SC0_SCL0_US6 */ + volatile uint32_t SC0_SCL0_US7; /* SC0_SCL0_US7 */ + volatile uint32_t SC0_SCL0_US8; /* SC0_SCL0_US8 */ + volatile uint8_t dummy6[4]; /* */ + volatile uint32_t SC0_SCL0_OVR1; /* SC0_SCL0_OVR1 */ + volatile uint8_t dummy7[16]; /* */ + volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ + volatile uint8_t dummy8[4]; /* */ + volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ + volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ + volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ + volatile uint32_t SC0_SCL1_WR4; /* SC0_SCL1_WR4 */ + volatile uint8_t dummy9[4]; /* */ + volatile uint32_t SC0_SCL1_WR5; /* SC0_SCL1_WR5 */ + volatile uint32_t SC0_SCL1_WR6; /* SC0_SCL1_WR6 */ + volatile uint32_t SC0_SCL1_WR7; /* SC0_SCL1_WR7 */ + volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ + volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ + volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ +}; + + +struct st_vdc5_from_sc0_scl1_pbuf0 +{ + volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ + volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ + volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ + volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ + volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ + volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ +}; + + +#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ +#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ + + +/* Start of channnel array defines of VDC5 */ + +/* Channnel array defines of VDC5 */ +/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ +#define VDC5_COUNT 2 +#define VDC5_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &VDC50, &VDC51 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */ +/*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2 +#define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ + &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ +#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ +#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ +#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ + + + + +/* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */ +/*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2 +#define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ + &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ +#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ +#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ +#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ + + + + +/* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */ +/*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ +#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2 +#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ + &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ +#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ +#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ +#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ + + + + +/* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */ +/*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ +#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2 +#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ + &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ +#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ +#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ +#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ + + + + +/* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */ +/*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ +#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2 +#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ + &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ +#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ +#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ +#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ + + + + +/* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */ +/*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2 +#define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ + &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ +#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ +#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ +#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ + + + + +/* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */ +/*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2 +#define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ + &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ +#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ +#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ +#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ + + +/* End of channnel array defines of VDC5 */ + + +#define VDC50INP_UPDATE VDC50.INP_UPDATE +#define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT +#define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT +#define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ +#define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ +#define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE +#define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0 +#define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1 +#define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE +#define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0 +#define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1 +#define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0 +#define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1 +#define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0 +#define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1 +#define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG +#define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE +#define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1 +#define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2 +#define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3 +#define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4 +#define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5 +#define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6 +#define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7 +#define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9 +#define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0 +#define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT +#define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1 +#define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2 +#define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3 +#define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4 +#define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5 +#define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6 +#define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7 +#define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1 +#define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2 +#define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3 +#define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4 +#define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5 +#define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6 +#define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7 +#define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8 +#define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1 +#define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE +#define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1 +#define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2 +#define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3 +#define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4 +#define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5 +#define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6 +#define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7 +#define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8 +#define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9 +#define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10 +#define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11 +#define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1 +#define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0 +#define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1 +#define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2 +#define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3 +#define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD +#define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT +#define VDC50GR0_UPDATE VDC50.GR0_UPDATE +#define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD +#define VDC50GR0_FLM1 VDC50.GR0_FLM1 +#define VDC50GR0_FLM2 VDC50.GR0_FLM2 +#define VDC50GR0_FLM3 VDC50.GR0_FLM3 +#define VDC50GR0_FLM4 VDC50.GR0_FLM4 +#define VDC50GR0_FLM5 VDC50.GR0_FLM5 +#define VDC50GR0_FLM6 VDC50.GR0_FLM6 +#define VDC50GR0_AB1 VDC50.GR0_AB1 +#define VDC50GR0_AB2 VDC50.GR0_AB2 +#define VDC50GR0_AB3 VDC50.GR0_AB3 +#define VDC50GR0_AB7 VDC50.GR0_AB7 +#define VDC50GR0_AB8 VDC50.GR0_AB8 +#define VDC50GR0_AB9 VDC50.GR0_AB9 +#define VDC50GR0_AB10 VDC50.GR0_AB10 +#define VDC50GR0_AB11 VDC50.GR0_AB11 +#define VDC50GR0_BASE VDC50.GR0_BASE +#define VDC50GR0_CLUT VDC50.GR0_CLUT +#define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE +#define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET +#define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1 +#define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2 +#define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3 +#define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1 +#define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2 +#define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3 +#define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4 +#define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5 +#define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6 +#define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1 +#define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2 +#define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE +#define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0 +#define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1 +#define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0 +#define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1 +#define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0 +#define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1 +#define VDC50GR2_UPDATE VDC50.GR2_UPDATE +#define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD +#define VDC50GR2_FLM1 VDC50.GR2_FLM1 +#define VDC50GR2_FLM2 VDC50.GR2_FLM2 +#define VDC50GR2_FLM3 VDC50.GR2_FLM3 +#define VDC50GR2_FLM4 VDC50.GR2_FLM4 +#define VDC50GR2_FLM5 VDC50.GR2_FLM5 +#define VDC50GR2_FLM6 VDC50.GR2_FLM6 +#define VDC50GR2_AB1 VDC50.GR2_AB1 +#define VDC50GR2_AB2 VDC50.GR2_AB2 +#define VDC50GR2_AB3 VDC50.GR2_AB3 +#define VDC50GR2_AB4 VDC50.GR2_AB4 +#define VDC50GR2_AB5 VDC50.GR2_AB5 +#define VDC50GR2_AB6 VDC50.GR2_AB6 +#define VDC50GR2_AB7 VDC50.GR2_AB7 +#define VDC50GR2_AB8 VDC50.GR2_AB8 +#define VDC50GR2_AB9 VDC50.GR2_AB9 +#define VDC50GR2_AB10 VDC50.GR2_AB10 +#define VDC50GR2_AB11 VDC50.GR2_AB11 +#define VDC50GR2_BASE VDC50.GR2_BASE +#define VDC50GR2_CLUT VDC50.GR2_CLUT +#define VDC50GR2_MON VDC50.GR2_MON +#define VDC50GR3_UPDATE VDC50.GR3_UPDATE +#define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD +#define VDC50GR3_FLM1 VDC50.GR3_FLM1 +#define VDC50GR3_FLM2 VDC50.GR3_FLM2 +#define VDC50GR3_FLM3 VDC50.GR3_FLM3 +#define VDC50GR3_FLM4 VDC50.GR3_FLM4 +#define VDC50GR3_FLM5 VDC50.GR3_FLM5 +#define VDC50GR3_FLM6 VDC50.GR3_FLM6 +#define VDC50GR3_AB1 VDC50.GR3_AB1 +#define VDC50GR3_AB2 VDC50.GR3_AB2 +#define VDC50GR3_AB3 VDC50.GR3_AB3 +#define VDC50GR3_AB4 VDC50.GR3_AB4 +#define VDC50GR3_AB5 VDC50.GR3_AB5 +#define VDC50GR3_AB6 VDC50.GR3_AB6 +#define VDC50GR3_AB7 VDC50.GR3_AB7 +#define VDC50GR3_AB8 VDC50.GR3_AB8 +#define VDC50GR3_AB9 VDC50.GR3_AB9 +#define VDC50GR3_AB10 VDC50.GR3_AB10 +#define VDC50GR3_AB11 VDC50.GR3_AB11 +#define VDC50GR3_BASE VDC50.GR3_BASE +#define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT +#define VDC50GR3_MON VDC50.GR3_MON +#define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE +#define VDC50GAM_SW VDC50.GAM_SW +#define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1 +#define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2 +#define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3 +#define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4 +#define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5 +#define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6 +#define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7 +#define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8 +#define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9 +#define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10 +#define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11 +#define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12 +#define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13 +#define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14 +#define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15 +#define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16 +#define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1 +#define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2 +#define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3 +#define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4 +#define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5 +#define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6 +#define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7 +#define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8 +#define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE +#define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1 +#define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2 +#define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3 +#define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4 +#define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5 +#define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6 +#define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7 +#define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8 +#define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9 +#define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10 +#define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11 +#define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12 +#define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13 +#define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14 +#define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15 +#define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16 +#define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1 +#define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2 +#define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3 +#define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4 +#define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5 +#define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6 +#define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7 +#define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8 +#define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE +#define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1 +#define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2 +#define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3 +#define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4 +#define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5 +#define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6 +#define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7 +#define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8 +#define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9 +#define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10 +#define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11 +#define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12 +#define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13 +#define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14 +#define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15 +#define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16 +#define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1 +#define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2 +#define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3 +#define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4 +#define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5 +#define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6 +#define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7 +#define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8 +#define VDC50TCON_UPDATE VDC50.TCON_UPDATE +#define VDC50TCON_TIM VDC50.TCON_TIM +#define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1 +#define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2 +#define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1 +#define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2 +#define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1 +#define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2 +#define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1 +#define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2 +#define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1 +#define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2 +#define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1 +#define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2 +#define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1 +#define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2 +#define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE +#define VDC50OUT_UPDATE VDC50.OUT_UPDATE +#define VDC50OUT_SET VDC50.OUT_SET +#define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1 +#define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2 +#define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST +#define VDC50OUT_PDTHA VDC50.OUT_PDTHA +#define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE +#define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1 +#define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2 +#define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3 +#define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4 +#define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5 +#define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6 +#define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK +#define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT +#define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE +#define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1 +#define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2 +#define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3 +#define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4 +#define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5 +#define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6 +#define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7 +#define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9 +#define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0 +#define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT +#define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1 +#define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2 +#define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3 +#define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4 +#define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5 +#define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6 +#define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7 +#define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1 +#define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2 +#define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3 +#define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4 +#define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5 +#define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6 +#define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7 +#define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8 +#define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1 +#define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE +#define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1 +#define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2 +#define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3 +#define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4 +#define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5 +#define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6 +#define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7 +#define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8 +#define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9 +#define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10 +#define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11 +#define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1 +#define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0 +#define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1 +#define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2 +#define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3 +#define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD +#define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT +#define VDC50GR1_UPDATE VDC50.GR1_UPDATE +#define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD +#define VDC50GR1_FLM1 VDC50.GR1_FLM1 +#define VDC50GR1_FLM2 VDC50.GR1_FLM2 +#define VDC50GR1_FLM3 VDC50.GR1_FLM3 +#define VDC50GR1_FLM4 VDC50.GR1_FLM4 +#define VDC50GR1_FLM5 VDC50.GR1_FLM5 +#define VDC50GR1_FLM6 VDC50.GR1_FLM6 +#define VDC50GR1_AB1 VDC50.GR1_AB1 +#define VDC50GR1_AB2 VDC50.GR1_AB2 +#define VDC50GR1_AB3 VDC50.GR1_AB3 +#define VDC50GR1_AB4 VDC50.GR1_AB4 +#define VDC50GR1_AB5 VDC50.GR1_AB5 +#define VDC50GR1_AB6 VDC50.GR1_AB6 +#define VDC50GR1_AB7 VDC50.GR1_AB7 +#define VDC50GR1_AB8 VDC50.GR1_AB8 +#define VDC50GR1_AB9 VDC50.GR1_AB9 +#define VDC50GR1_AB10 VDC50.GR1_AB10 +#define VDC50GR1_AB11 VDC50.GR1_AB11 +#define VDC50GR1_BASE VDC50.GR1_BASE +#define VDC50GR1_CLUT VDC50.GR1_CLUT +#define VDC50GR1_MON VDC50.GR1_MON +#define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE +#define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET +#define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1 +#define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2 +#define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3 +#define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1 +#define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2 +#define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3 +#define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4 +#define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5 +#define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6 +#define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1 +#define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2 +#define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE +#define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0 +#define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1 +#define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0 +#define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1 +#define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0 +#define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1 +#define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE +#define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1 +#define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2 +#define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3 +#define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4 +#define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5 +#define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6 +#define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7 +#define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE +#define VDC50GR_VIN_MON VDC50.GR_VIN_MON +#define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE +#define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1 +#define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2 +#define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3 +#define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4 +#define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5 +#define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6 +#define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7 +#define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1 +#define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2 +#define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3 +#define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7 +#define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1 +#define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2 +#define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3 +#define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8 +#define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1 +#define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE +#define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1 +#define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2 +#define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3 +#define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4 +#define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5 +#define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6 +#define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7 +#define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE +#define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD +#define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1 +#define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2 +#define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3 +#define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4 +#define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5 +#define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6 +#define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1 +#define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2 +#define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3 +#define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7 +#define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8 +#define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9 +#define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10 +#define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11 +#define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE +#define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT +#define VDC50GR_OIR_MON VDC50.GR_OIR_MON +#define VDC51INP_UPDATE VDC51.INP_UPDATE +#define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT +#define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT +#define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ +#define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ +#define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE +#define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0 +#define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1 +#define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE +#define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0 +#define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1 +#define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0 +#define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1 +#define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0 +#define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1 +#define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG +#define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE +#define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1 +#define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2 +#define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3 +#define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4 +#define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5 +#define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6 +#define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7 +#define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9 +#define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0 +#define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT +#define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1 +#define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2 +#define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3 +#define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4 +#define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5 +#define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6 +#define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7 +#define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1 +#define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2 +#define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3 +#define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4 +#define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5 +#define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6 +#define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7 +#define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8 +#define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1 +#define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE +#define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1 +#define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2 +#define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3 +#define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4 +#define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5 +#define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6 +#define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7 +#define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8 +#define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9 +#define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10 +#define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11 +#define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1 +#define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0 +#define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1 +#define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2 +#define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3 +#define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD +#define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT +#define VDC51GR0_UPDATE VDC51.GR0_UPDATE +#define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD +#define VDC51GR0_FLM1 VDC51.GR0_FLM1 +#define VDC51GR0_FLM2 VDC51.GR0_FLM2 +#define VDC51GR0_FLM3 VDC51.GR0_FLM3 +#define VDC51GR0_FLM4 VDC51.GR0_FLM4 +#define VDC51GR0_FLM5 VDC51.GR0_FLM5 +#define VDC51GR0_FLM6 VDC51.GR0_FLM6 +#define VDC51GR0_AB1 VDC51.GR0_AB1 +#define VDC51GR0_AB2 VDC51.GR0_AB2 +#define VDC51GR0_AB3 VDC51.GR0_AB3 +#define VDC51GR0_AB7 VDC51.GR0_AB7 +#define VDC51GR0_AB8 VDC51.GR0_AB8 +#define VDC51GR0_AB9 VDC51.GR0_AB9 +#define VDC51GR0_AB10 VDC51.GR0_AB10 +#define VDC51GR0_AB11 VDC51.GR0_AB11 +#define VDC51GR0_BASE VDC51.GR0_BASE +#define VDC51GR0_CLUT VDC51.GR0_CLUT +#define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE +#define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET +#define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1 +#define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2 +#define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3 +#define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1 +#define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2 +#define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3 +#define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4 +#define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5 +#define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6 +#define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1 +#define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2 +#define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE +#define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0 +#define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1 +#define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0 +#define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1 +#define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0 +#define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1 +#define VDC51GR2_UPDATE VDC51.GR2_UPDATE +#define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD +#define VDC51GR2_FLM1 VDC51.GR2_FLM1 +#define VDC51GR2_FLM2 VDC51.GR2_FLM2 +#define VDC51GR2_FLM3 VDC51.GR2_FLM3 +#define VDC51GR2_FLM4 VDC51.GR2_FLM4 +#define VDC51GR2_FLM5 VDC51.GR2_FLM5 +#define VDC51GR2_FLM6 VDC51.GR2_FLM6 +#define VDC51GR2_AB1 VDC51.GR2_AB1 +#define VDC51GR2_AB2 VDC51.GR2_AB2 +#define VDC51GR2_AB3 VDC51.GR2_AB3 +#define VDC51GR2_AB4 VDC51.GR2_AB4 +#define VDC51GR2_AB5 VDC51.GR2_AB5 +#define VDC51GR2_AB6 VDC51.GR2_AB6 +#define VDC51GR2_AB7 VDC51.GR2_AB7 +#define VDC51GR2_AB8 VDC51.GR2_AB8 +#define VDC51GR2_AB9 VDC51.GR2_AB9 +#define VDC51GR2_AB10 VDC51.GR2_AB10 +#define VDC51GR2_AB11 VDC51.GR2_AB11 +#define VDC51GR2_BASE VDC51.GR2_BASE +#define VDC51GR2_CLUT VDC51.GR2_CLUT +#define VDC51GR2_MON VDC51.GR2_MON +#define VDC51GR3_UPDATE VDC51.GR3_UPDATE +#define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD +#define VDC51GR3_FLM1 VDC51.GR3_FLM1 +#define VDC51GR3_FLM2 VDC51.GR3_FLM2 +#define VDC51GR3_FLM3 VDC51.GR3_FLM3 +#define VDC51GR3_FLM4 VDC51.GR3_FLM4 +#define VDC51GR3_FLM5 VDC51.GR3_FLM5 +#define VDC51GR3_FLM6 VDC51.GR3_FLM6 +#define VDC51GR3_AB1 VDC51.GR3_AB1 +#define VDC51GR3_AB2 VDC51.GR3_AB2 +#define VDC51GR3_AB3 VDC51.GR3_AB3 +#define VDC51GR3_AB4 VDC51.GR3_AB4 +#define VDC51GR3_AB5 VDC51.GR3_AB5 +#define VDC51GR3_AB6 VDC51.GR3_AB6 +#define VDC51GR3_AB7 VDC51.GR3_AB7 +#define VDC51GR3_AB8 VDC51.GR3_AB8 +#define VDC51GR3_AB9 VDC51.GR3_AB9 +#define VDC51GR3_AB10 VDC51.GR3_AB10 +#define VDC51GR3_AB11 VDC51.GR3_AB11 +#define VDC51GR3_BASE VDC51.GR3_BASE +#define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT +#define VDC51GR3_MON VDC51.GR3_MON +#define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE +#define VDC51GAM_SW VDC51.GAM_SW +#define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1 +#define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2 +#define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3 +#define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4 +#define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5 +#define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6 +#define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7 +#define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8 +#define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9 +#define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10 +#define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11 +#define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12 +#define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13 +#define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14 +#define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15 +#define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16 +#define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1 +#define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2 +#define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3 +#define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4 +#define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5 +#define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6 +#define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7 +#define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8 +#define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE +#define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1 +#define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2 +#define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3 +#define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4 +#define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5 +#define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6 +#define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7 +#define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8 +#define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9 +#define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10 +#define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11 +#define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12 +#define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13 +#define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14 +#define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15 +#define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16 +#define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1 +#define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2 +#define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3 +#define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4 +#define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5 +#define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6 +#define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7 +#define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8 +#define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE +#define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1 +#define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2 +#define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3 +#define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4 +#define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5 +#define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6 +#define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7 +#define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8 +#define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9 +#define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10 +#define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11 +#define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12 +#define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13 +#define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14 +#define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15 +#define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16 +#define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1 +#define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2 +#define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3 +#define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4 +#define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5 +#define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6 +#define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7 +#define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8 +#define VDC51TCON_UPDATE VDC51.TCON_UPDATE +#define VDC51TCON_TIM VDC51.TCON_TIM +#define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1 +#define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2 +#define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1 +#define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2 +#define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1 +#define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2 +#define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1 +#define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2 +#define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1 +#define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2 +#define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1 +#define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2 +#define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1 +#define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2 +#define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE +#define VDC51OUT_UPDATE VDC51.OUT_UPDATE +#define VDC51OUT_SET VDC51.OUT_SET +#define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1 +#define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2 +#define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST +#define VDC51OUT_PDTHA VDC51.OUT_PDTHA +#define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE +#define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1 +#define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2 +#define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3 +#define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4 +#define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5 +#define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6 +#define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK +#define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT +#define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE +#define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1 +#define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2 +#define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3 +#define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4 +#define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5 +#define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6 +#define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7 +#define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9 +#define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0 +#define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT +#define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1 +#define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2 +#define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3 +#define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4 +#define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5 +#define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6 +#define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7 +#define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1 +#define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2 +#define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3 +#define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4 +#define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5 +#define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6 +#define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7 +#define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8 +#define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1 +#define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE +#define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1 +#define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2 +#define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3 +#define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4 +#define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5 +#define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6 +#define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7 +#define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8 +#define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9 +#define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10 +#define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11 +#define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1 +#define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0 +#define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1 +#define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2 +#define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3 +#define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD +#define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT +#define VDC51GR1_UPDATE VDC51.GR1_UPDATE +#define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD +#define VDC51GR1_FLM1 VDC51.GR1_FLM1 +#define VDC51GR1_FLM2 VDC51.GR1_FLM2 +#define VDC51GR1_FLM3 VDC51.GR1_FLM3 +#define VDC51GR1_FLM4 VDC51.GR1_FLM4 +#define VDC51GR1_FLM5 VDC51.GR1_FLM5 +#define VDC51GR1_FLM6 VDC51.GR1_FLM6 +#define VDC51GR1_AB1 VDC51.GR1_AB1 +#define VDC51GR1_AB2 VDC51.GR1_AB2 +#define VDC51GR1_AB3 VDC51.GR1_AB3 +#define VDC51GR1_AB4 VDC51.GR1_AB4 +#define VDC51GR1_AB5 VDC51.GR1_AB5 +#define VDC51GR1_AB6 VDC51.GR1_AB6 +#define VDC51GR1_AB7 VDC51.GR1_AB7 +#define VDC51GR1_AB8 VDC51.GR1_AB8 +#define VDC51GR1_AB9 VDC51.GR1_AB9 +#define VDC51GR1_AB10 VDC51.GR1_AB10 +#define VDC51GR1_AB11 VDC51.GR1_AB11 +#define VDC51GR1_BASE VDC51.GR1_BASE +#define VDC51GR1_CLUT VDC51.GR1_CLUT +#define VDC51GR1_MON VDC51.GR1_MON +#define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE +#define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET +#define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1 +#define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2 +#define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3 +#define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1 +#define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2 +#define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3 +#define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4 +#define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5 +#define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6 +#define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1 +#define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2 +#define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE +#define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0 +#define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1 +#define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0 +#define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1 +#define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0 +#define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1 +#define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE +#define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1 +#define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2 +#define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3 +#define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4 +#define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5 +#define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6 +#define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7 +#define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE +#define VDC51GR_VIN_MON VDC51.GR_VIN_MON +#define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE +#define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1 +#define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2 +#define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3 +#define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4 +#define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5 +#define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6 +#define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7 +#define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1 +#define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2 +#define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3 +#define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7 +#define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1 +#define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2 +#define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3 +#define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8 +#define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1 +#define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE +#define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1 +#define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2 +#define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3 +#define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4 +#define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5 +#define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6 +#define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7 +#define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE +#define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD +#define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1 +#define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2 +#define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3 +#define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4 +#define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5 +#define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6 +#define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1 +#define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2 +#define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3 +#define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7 +#define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8 +#define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9 +#define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10 +#define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11 +#define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE +#define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT +#define VDC51GR_OIR_MON VDC51.GR_OIR_MON +/* <-SEC M1.10.1 */ +/* <-QAC 0639 */ +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/wdt_iodefine.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/wdt_iodefine.h new file mode 100644 index 0000000000..0ee2a53210 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/wdt_iodefine.h @@ -0,0 +1,46 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : wdt_iodefine.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register (V1.00a) +******************************************************************************/ +#ifndef WDT_IODEFINE_H +#define WDT_IODEFINE_H + +struct st_wdt +{ /* WDT */ + volatile uint16_t WTCSR; /* WTCSR */ + volatile uint16_t WTCNT; /* WTCNT */ + volatile uint16_t WRCSR; /* WRCSR */ +}; + + +#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */ + + +#define WDTWTCSR WDT.WTCSR +#define WDTWTCNT WDT.WTCNT +#define WDTWRCSR WDT.WRCSR +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/reg32_t.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/reg32_t.h new file mode 100644 index 0000000000..0d40bbc749 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/reg32_t.h @@ -0,0 +1,11 @@ +#ifndef __REG32_T +#define __REG32_T + +union reg32_t { + volatile uint32_t UINT32; + volatile uint16_t UINT16[2]; + volatile uint8_t UINT8[4]; +}; + + +#endif diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c new file mode 100644 index 0000000000..e54f3080c4 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mbed_sf_boot.c @@ -0,0 +1,1047 @@ +#pragma arm section rodata = "BOOT_LOADER" +const char boot_loader[] __attribute__((used)) = +{ + 0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5, + 0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5,0x18,0xF0,0x9F,0xE5, + 0x00,0x40,0x00,0x18,0x74,0x40,0x00,0x18,0x78,0x40,0x00,0x18,0x7C,0x40,0x00,0x18, + 0x80,0x40,0x00,0x18,0x84,0x40,0x00,0x18,0x88,0x40,0x00,0x18,0x8C,0x40,0x00,0x18, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3,0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5, + 0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1,0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4, + 0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4,0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0xBA, + 0x10,0x80,0xBD,0xE8,0x97,0x28,0x00,0x00,0x00,0x04,0x00,0x18,0x00,0x02,0x02,0x20, + 0x70,0x40,0x2D,0xE9,0x02,0x29,0xA0,0xE3,0xC8,0x40,0x9F,0xE5,0x0F,0x10,0xA0,0xE3, + 0x04,0x00,0xA0,0xE1,0x4C,0x00,0x00,0xEB,0x01,0x00,0x50,0xE3,0x06,0x00,0x00,0x1A, + 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1, + 0x33,0x00,0x00,0xEB,0x08,0x00,0x44,0xE2,0xB8,0x00,0xD0,0xE1,0x01,0x34,0xA0,0xE3, + 0x94,0x50,0x9F,0xE5,0x18,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1, + 0x32,0x00,0x00,0xEB,0x3C,0x40,0x85,0xE2,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x04,0x00,0xA0,0xE1,0x3C,0x00,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A, + 0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x36,0x00,0x00,0xEB, + 0x01,0x00,0x50,0xE3,0xF9,0xFF,0xFF,0x1A,0x00,0x00,0xA0,0xE3,0x4C,0x10,0x9F,0xE5, + 0x04,0x00,0x81,0xE5,0x00,0x20,0xA0,0xE1,0x44,0x40,0x9F,0xE5,0x00,0x10,0xA0,0xE1, + 0x03,0x30,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x1C,0x00,0x00,0xEB,0xFF,0x3C,0xA0,0xE3, + 0x08,0x20,0xA0,0xE3,0x02,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0x17,0x00,0x00,0xEB, + 0x05,0x00,0xA0,0xE1,0x01,0x3C,0xA0,0xE3,0x70,0x40,0xBD,0xE8,0x08,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x11,0x00,0x00,0xEA,0x08,0x18,0xFF,0xFC,0x0C,0xA0,0xEF,0x3F, + 0x00,0xA0,0xEF,0x3F,0x08,0xA0,0xEF,0x3F,0x10,0x40,0x2D,0xE9,0x00,0x40,0xD0,0xE5, + 0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0x00,0x10,0xC0,0xE5, + 0x10,0x80,0xBD,0xE8,0x10,0x40,0x2D,0xE9,0xB0,0x40,0xD0,0xE1,0x11,0x12,0xA0,0xE1, + 0x03,0x20,0xC4,0xE1,0x02,0x10,0x81,0xE1,0xB0,0x10,0xC0,0xE1,0x10,0x80,0xBD,0xE8, + 0x10,0x40,0x2D,0xE9,0x00,0x40,0x90,0xE5,0x11,0x12,0xA0,0xE1,0x03,0x20,0xC4,0xE1, + 0x02,0x10,0x81,0xE1,0x00,0x10,0x80,0xE5,0x10,0x80,0xBD,0xE8,0x00,0x00,0xD0,0xE5, + 0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0xB0,0x00,0xD0,0xE1, + 0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x90,0xE5, + 0x02,0x00,0x00,0xE0,0x30,0x01,0xA0,0xE1,0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0xFF,0x2F,0xE1,0x10,0x40,0x2D,0xE9,0x00,0x00,0xA0,0xE3,0x7D,0x03,0x00,0xEB, + 0x2C,0x10,0x9F,0xE5,0x00,0x00,0xA0,0xE3,0x7B,0x03,0x00,0xEB,0x20,0x20,0x9F,0xE5, + 0x00,0x10,0xA0,0xE3,0x01,0x00,0xA0,0xE1,0x51,0x03,0x00,0xEB,0x00,0x00,0x50,0xE3, + 0x00,0x00,0x00,0x0A,0xFE,0xFF,0xFF,0xEA,0x10,0x40,0xBD,0xE8,0x04,0x00,0x9F,0xE5, + 0xEE,0xFF,0xFF,0xEA,0x94,0x2A,0x02,0x20,0x00,0x80,0x00,0x18,0xF0,0x41,0x2D,0xE9, + 0x00,0x40,0xA0,0xE1,0x03,0x70,0xA0,0xE1,0x02,0x50,0xA0,0xE1,0x18,0x60,0x9D,0xE5, + 0x01,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE1,0xD9,0x01,0x00,0xEB,0x00,0x00,0x50,0xE3, + 0xF0,0x81,0xBD,0x18,0x00,0x00,0xA0,0xE3,0x01,0x20,0xA0,0xE3,0x0F,0x00,0x56,0xE3, + 0x54,0x16,0x9F,0xE5,0x18,0x30,0x81,0xE2,0x00,0x00,0x81,0xE5,0x08,0x00,0x81,0xE5, + 0x14,0x20,0x81,0xE5,0xD8,0x20,0xA0,0x13,0x41,0x00,0x83,0xE8,0xDC,0x20,0xA0,0x03, + 0x20,0x00,0x81,0xE5,0x01,0x00,0x55,0xE3,0x24,0x00,0x81,0xE5,0x28,0x00,0x81,0xE5, + 0x2C,0x00,0x81,0xE5,0x30,0x00,0x81,0xE5,0x46,0x20,0xC1,0xE5,0xA4,0x20,0xA0,0x01, + 0x48,0x20,0x81,0x05,0x48,0x40,0x81,0x15,0x34,0x00,0x81,0xE5,0x38,0x00,0x81,0xE5, + 0x3C,0x00,0x81,0xE5,0x40,0x00,0x81,0xE5,0x08,0x00,0xA0,0xE1,0xF8,0x15,0x9F,0xE5, + 0x91,0x08,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x07,0x20,0xA0,0xE1, + 0x05,0x10,0xA0,0xE1,0x08,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,0x9E,0x01,0x00,0xEA, + 0xFF,0x5F,0x2D,0xE9,0x00,0xB0,0xA0,0xE1,0x02,0x70,0xA0,0xE1,0x01,0x60,0xA0,0xE1, + 0x0C,0x00,0x9D,0xE5,0x40,0x80,0x9D,0xE5,0x3C,0x90,0x9D,0xE5,0x38,0xA0,0x9D,0xE5, + 0xAB,0x01,0x00,0xEB,0x00,0x00,0x50,0xE3,0x7A,0x00,0x00,0x1A,0x00,0x50,0xA0,0xE3, + 0xA4,0x45,0x9F,0xE5,0x01,0x00,0xA0,0xE3,0x00,0x00,0x59,0xE3,0x14,0x10,0x84,0xE2, + 0x00,0x50,0x84,0xE5,0x08,0x50,0x84,0xE5,0x21,0x01,0x81,0xE8,0x28,0x10,0x84,0xE2, + 0x20,0x50,0x84,0xE5,0x24,0x50,0x84,0xE5,0x21,0x00,0x81,0xE8,0x30,0x50,0x84,0xE5, + 0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5, + 0x22,0x00,0x00,0x0A,0x0F,0x00,0x58,0xE3,0x34,0x00,0xA0,0x03,0x32,0x00,0xA0,0x13, + 0x01,0x00,0x5A,0xE3,0x50,0x15,0x9F,0xE5,0x46,0x00,0xC4,0xE5,0xAB,0x00,0xA0,0x01, + 0x48,0x00,0x84,0x05,0x48,0xB0,0x84,0x15,0x0C,0x00,0x9D,0xE5,0x62,0x08,0x00,0xEB, + 0x00,0x00,0x50,0xE3,0x5B,0x00,0x00,0x1A,0x14,0x50,0x84,0xE5,0x10,0x90,0x84,0xE5, + 0x01,0x30,0xA0,0xE3,0x18,0x50,0x84,0xE5,0x01,0x00,0x5A,0xE3,0x1C,0x50,0x84,0xE5, + 0x0F,0x00,0xA0,0xE3,0x20,0x50,0x84,0xE5,0x08,0x10,0xA0,0xE3,0x30,0x30,0x84,0xE5, + 0x0C,0x20,0xA0,0xE3,0x2C,0x50,0x84,0xE5,0x0C,0x00,0x00,0x0A,0x03,0x00,0x17,0xE3, + 0x20,0x00,0x00,0x0A,0x01,0x00,0x17,0xE3,0x23,0x00,0x00,0x0A,0x00,0x00,0x57,0xE3, + 0x01,0x80,0xA0,0xE3,0x24,0x10,0x84,0xE5,0x42,0x00,0x00,0xDA,0x2C,0x00,0x00,0xEA, + 0x0F,0x00,0x58,0xE3,0x02,0x00,0xA0,0x13,0x12,0x00,0xA0,0x03,0xDB,0xFF,0xFF,0xEA, + 0x07,0x00,0x17,0xE3,0x09,0x00,0x00,0x0A,0x03,0x00,0x17,0xE3,0x0C,0x00,0x00,0x0A, + 0x01,0x00,0x17,0xE3,0x00,0x00,0xE0,0x13,0x3A,0x00,0x00,0x1A,0x00,0x00,0x57,0xE3, + 0x02,0x80,0xA0,0xE3,0x24,0x10,0x84,0xE5,0x1F,0x00,0x00,0xCA,0x31,0x00,0x00,0xEA, + 0x00,0x00,0x57,0xE3,0x08,0x80,0xA0,0xE3,0x24,0x00,0x84,0xE5,0x1E,0x00,0x00,0xCA, + 0x2C,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,0x04,0x80,0xA0,0xE3,0x24,0x20,0x84,0xE5, + 0x17,0x00,0x00,0xCA,0x27,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3,0x04,0x80,0xA0,0xE3, + 0x24,0x00,0x84,0xE5,0x12,0x00,0x00,0xCA,0x22,0x00,0x00,0xEA,0x00,0x00,0x57,0xE3, + 0x02,0x80,0xA0,0xE3,0x24,0x20,0x84,0xE5,0x0B,0x00,0x00,0xCA,0x1D,0x00,0x00,0xEA, + 0x01,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,0x02,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A, + 0x04,0x00,0x58,0xE3,0x06,0x00,0x00,0x0A,0x08,0x00,0x58,0xE3,0x0A,0x00,0x00,0x1A, + 0x05,0x00,0x00,0xEA,0x00,0x00,0xD6,0xE5,0x06,0x00,0x00,0xEA,0xB0,0x00,0xD6,0xE1, + 0x04,0x00,0x00,0xEA,0x00,0x00,0x96,0xE5,0x02,0x00,0x00,0xEA,0x00,0x10,0x96,0xE5, + 0x5C,0x10,0x84,0xE5,0x04,0x00,0x96,0xE5,0x58,0x00,0x84,0xE5,0x08,0x70,0x47,0xE0, + 0x00,0x00,0x57,0xE3,0xF0,0x13,0x9F,0xE5,0x28,0x50,0x84,0xD5,0x08,0x60,0x86,0xE0, + 0x0C,0x00,0x9D,0xE5,0x0C,0x08,0x00,0xEB,0x00,0x00,0x50,0xE3,0x05,0x00,0x00,0x1A, + 0x00,0x00,0x57,0xE3,0xE1,0xFF,0xFF,0xCA,0x0C,0x00,0x9D,0xE5,0x09,0x20,0xA0,0xE1, + 0x0A,0x10,0xA0,0xE1,0x18,0x01,0x00,0xEB,0x10,0xD0,0x8D,0xE2,0xF0,0x9F,0xBD,0xE8, + 0xF0,0x47,0x2D,0xE9,0x01,0x50,0xA0,0xE1,0xAC,0x43,0x9F,0xE5,0x00,0x70,0xA0,0xE3, + 0x24,0x10,0x9D,0xE5,0x01,0x80,0xA0,0xE3,0x20,0x90,0x9D,0xE5,0x02,0x60,0xA0,0xE1, + 0x1C,0x20,0x84,0xE2,0x03,0xA0,0xA0,0xE1,0x00,0x70,0x84,0xE5,0x0F,0x00,0x51,0xE3, + 0x08,0x70,0x84,0xE5,0x14,0x80,0x84,0xE5,0x18,0x70,0x84,0xE5,0x82,0x00,0x82,0xE8, + 0x24,0x20,0x84,0xE2,0x6C,0x10,0xA0,0x03,0x6B,0x10,0xA0,0x13,0x80,0x01,0x82,0xE8, + 0x01,0x00,0x59,0xE3,0x2C,0x70,0x84,0xE5,0xA0,0x00,0xA0,0x01,0x30,0x70,0x84,0xE5, + 0x46,0x10,0xC4,0xE5,0x07,0x10,0xA0,0xE3,0x34,0x80,0x84,0xE5,0x44,0x70,0xC4,0xE5, + 0x45,0x10,0xC4,0xE5,0x38,0x70,0x84,0xE5,0x3C,0x70,0x84,0xE5,0x38,0x13,0x9F,0xE5, + 0x40,0x70,0x84,0xE5,0x48,0x00,0x84,0xE5,0x03,0x00,0xA0,0xE1,0xDE,0x07,0x00,0xEB, + 0x00,0x00,0x50,0xE3,0xF0,0x87,0xBD,0x18,0x02,0x30,0xA0,0xE3,0x10,0xC0,0x84,0xE2, + 0x01,0x00,0x59,0xE3,0x0F,0x00,0xA0,0xE3,0x08,0x10,0xA0,0xE3,0x88,0x00,0x8C,0xE8, + 0x0C,0x20,0xA0,0xE3,0x18,0x70,0x84,0xE5,0x1C,0x70,0x84,0xE5,0x20,0x70,0x84,0xE5, + 0x2C,0x80,0x84,0xE5,0x30,0x70,0x84,0xE5,0x34,0x70,0x84,0xE5,0x04,0x00,0x00,0x0A, + 0x04,0x00,0x56,0xE3,0x1F,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,0x1F,0x00,0x00,0x0A, + 0x06,0x00,0x00,0xEA,0x08,0x00,0x56,0xE3,0x1A,0x00,0x00,0x0A,0x04,0x00,0x56,0xE3, + 0x1A,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3,0x00,0x00,0xE0,0x13,0xF0,0x87,0xBD,0x18, + 0x24,0x10,0x84,0xE5,0x0A,0x00,0xA0,0xE1,0x28,0x70,0x84,0xE5,0xA8,0x12,0x9F,0xE5, + 0xBD,0x07,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x87,0xBD,0x18,0x01,0x00,0x56,0xE3, + 0x50,0x00,0xD4,0x05,0x00,0x00,0xC5,0x05,0x12,0x00,0x00,0x0A,0x02,0x00,0x56,0xE3, + 0xB0,0x05,0xD4,0x01,0xB0,0x00,0xC5,0x01,0x0E,0x00,0x00,0x0A,0x04,0x00,0x56,0xE3, + 0x50,0x00,0x94,0x05,0x00,0x00,0x85,0x05,0x0A,0x00,0x00,0x0A,0x08,0x00,0x56,0xE3, + 0x04,0x00,0x00,0x0A,0x07,0x00,0x00,0xEA,0x24,0x00,0x84,0xE5,0xE8,0xFF,0xFF,0xEA, + 0x24,0x20,0x84,0xE5,0xE6,0xFF,0xFF,0xEA,0x54,0x00,0x94,0xE5,0x00,0x00,0x85,0xE5, + 0x50,0x00,0x94,0xE5,0x04,0x00,0x85,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x87,0xBD,0xE8, + 0xF0,0x5F,0x2D,0xE9,0x01,0x60,0xA0,0xE1,0x2C,0x42,0x9F,0xE5,0x00,0x50,0xA0,0xE3, + 0x2C,0x10,0x9D,0xE5,0x01,0x80,0xA0,0xE3,0x28,0xA0,0x9D,0xE5,0x02,0x70,0xA0,0xE1, + 0x1C,0x20,0x84,0xE2,0x0C,0x90,0xA0,0xE3,0x00,0x50,0x84,0xE5,0x0F,0x00,0x51,0xE3, + 0x08,0x50,0x84,0xE5,0x03,0xB0,0xA0,0xE1,0x14,0x80,0x84,0xE5,0x18,0x50,0x84,0xE5, + 0x22,0x00,0x82,0xE8,0x24,0x20,0x84,0xE2,0x0B,0x10,0xA0,0x13,0x20,0x01,0x82,0xE8, + 0x2C,0x50,0x84,0xE5,0x30,0x50,0x84,0xE5,0x46,0x90,0xC4,0x05,0x46,0x10,0xC4,0x15, + 0x07,0x10,0xA0,0xE3,0x34,0x80,0x84,0xE5,0x01,0x00,0x5A,0xE3,0x44,0x50,0xC4,0xE5, + 0xA0,0x00,0xA0,0x01,0x45,0x10,0xC4,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5, + 0xB4,0x11,0x9F,0xE5,0x40,0x50,0x84,0xE5,0x48,0x00,0x84,0xE5,0x03,0x00,0xA0,0xE1, + 0x7D,0x07,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x9F,0xBD,0x18,0x0F,0x00,0xA0,0xE3, + 0x01,0x00,0x5A,0xE3,0x08,0x10,0xA0,0xE3,0x10,0x50,0x84,0xE5,0x14,0x50,0x84,0xE5, + 0x18,0x50,0x84,0xE5,0x1C,0x50,0x84,0xE5,0x20,0x50,0x84,0xE5,0x2C,0x80,0x84,0xE5, + 0x30,0x50,0x84,0xE5,0x34,0x50,0x84,0xE5,0x04,0x00,0x00,0x0A,0x04,0x00,0x57,0xE3, + 0x1F,0x00,0x00,0x0A,0x02,0x00,0x57,0xE3,0x1F,0x00,0x00,0x0A,0x06,0x00,0x00,0xEA, + 0x08,0x00,0x57,0xE3,0x1A,0x00,0x00,0x0A,0x04,0x00,0x57,0xE3,0x1A,0x00,0x00,0x0A, + 0x02,0x00,0x57,0xE3,0x00,0x00,0xE0,0x13,0xF0,0x9F,0xBD,0x18,0x24,0x10,0x84,0xE5, + 0x0B,0x00,0xA0,0xE1,0x28,0x50,0x84,0xE5,0x2C,0x11,0x9F,0xE5,0x5E,0x07,0x00,0xEB, + 0x00,0x00,0x50,0xE3,0xF0,0x9F,0xBD,0x18,0x01,0x00,0x57,0xE3,0x50,0x00,0xD4,0x05, + 0x00,0x00,0xC6,0x05,0x12,0x00,0x00,0x0A,0x02,0x00,0x57,0xE3,0xB0,0x05,0xD4,0x01, + 0xB0,0x00,0xC6,0x01,0x0E,0x00,0x00,0x0A,0x04,0x00,0x57,0xE3,0x50,0x00,0x94,0x05, + 0x00,0x00,0x86,0x05,0x0A,0x00,0x00,0x0A,0x08,0x00,0x57,0xE3,0x04,0x00,0x00,0x0A, + 0x07,0x00,0x00,0xEA,0x24,0x00,0x84,0xE5,0xE8,0xFF,0xFF,0xEA,0x24,0x90,0x84,0xE5, + 0xE6,0xFF,0xFF,0xEA,0x54,0x00,0x94,0xE5,0x00,0x00,0x86,0xE5,0x50,0x00,0x94,0xE5, + 0x04,0x00,0x86,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x9F,0xBD,0xE8,0xFC,0x5F,0x2D,0xE9, + 0x00,0x80,0xA0,0xE1,0x30,0x00,0x8D,0xE2,0x03,0xB0,0xA0,0xE1,0x38,0x90,0x9D,0xE5, + 0x02,0x50,0xA0,0xE1,0x40,0x04,0x90,0xE8,0x01,0x70,0xA0,0xE1,0x01,0x00,0x56,0xE3, + 0x00,0x00,0xA0,0xE3,0x05,0x00,0x00,0x0A,0x03,0x00,0x15,0xE3,0x0D,0x00,0x00,0x0A, + 0x01,0x00,0x15,0xE3,0x01,0x40,0xA0,0x13,0x08,0x00,0x00,0x0A,0x0A,0x00,0x00,0xEA, + 0x07,0x00,0x15,0xE3,0x08,0x40,0xA0,0x03,0x07,0x00,0x00,0x0A,0x03,0x00,0x15,0xE3, + 0x04,0x00,0x00,0x0A,0x01,0x00,0x15,0xE3,0x00,0x00,0xE0,0x13,0x11,0x00,0x00,0x1A, + 0x02,0x40,0xA0,0xE3,0x00,0x00,0x00,0xEA,0x04,0x40,0xA0,0xE3,0x00,0x00,0x55,0xE3, + 0x0C,0x00,0x00,0xDA,0x00,0x00,0x5A,0xE3,0x40,0x02,0x8D,0xE8,0x0B,0x30,0xA0,0xE1, + 0x04,0x20,0xA0,0xE1,0x07,0x10,0xA0,0xE1,0x08,0x00,0xA0,0xE1,0x06,0x00,0x00,0x0A, + 0x1A,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x04,0x80,0x88,0x00,0x04,0x70,0x87,0x00, + 0x04,0x50,0x45,0x00,0xF0,0xFF,0xFF,0x0A,0xFC,0x9F,0xBD,0xE8,0x73,0xFF,0xFF,0xEB, + 0xF7,0xFF,0xFF,0xEA,0x14,0x07,0x00,0xEA,0xB1,0x00,0x00,0xEA,0xA4,0x2A,0x02,0x20, + 0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x64,0x45,0x9F,0xE5,0x03,0x60,0xB0,0xE1, + 0x00,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE3,0x01,0x70,0xA0,0xE1,0x08,0x10,0xA0,0xE3, + 0x14,0x30,0x84,0xE2,0x00,0x50,0x84,0xE5,0x10,0x50,0x84,0xE5,0x21,0x00,0x83,0xE8, + 0x1C,0x50,0x84,0xE5,0x24,0x10,0x84,0xE5,0x05,0x10,0xA0,0xE3,0x20,0x50,0x84,0xE5, + 0x2C,0x00,0x84,0xE5,0x28,0x50,0x84,0xE5,0x30,0x00,0x84,0xE5,0x02,0x00,0xA0,0xE1, + 0x46,0x10,0xC4,0xE5,0x00,0x10,0x84,0xE2,0x58,0x50,0x84,0xE5,0x5C,0x50,0x84,0xE5, + 0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5, + 0xDF,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x00,0x00,0x56,0xE3, + 0x50,0x10,0xD4,0xE5,0x00,0x10,0xC8,0xE5,0xB0,0x15,0xD4,0x11,0x21,0x14,0xA0,0x11, + 0x00,0x10,0xC7,0x15,0x00,0x50,0xC7,0x05,0xF0,0x81,0xBD,0xE8,0xFE,0x40,0x2D,0xE9, + 0x02,0x50,0xA0,0xE1,0x01,0x40,0xA0,0xE1,0x00,0x60,0xA0,0xE1,0x04,0x30,0xA0,0xE1, + 0x06,0x20,0xA0,0xE1,0x08,0x10,0x8D,0xE2,0x04,0x00,0x8D,0xE2,0x00,0x50,0x8D,0xE5, + 0xCE,0xFF,0xFF,0xEB,0x01,0x00,0x54,0xE3,0x04,0x10,0xDD,0x05,0x08,0x20,0xDD,0x05, + 0x02,0x10,0x81,0x01,0x03,0x00,0x00,0x0A,0x00,0x00,0x54,0xE3,0x04,0x10,0xDD,0x05, + 0x00,0x00,0xE0,0x13,0x01,0x00,0x00,0x1A,0x01,0x00,0x11,0xE3,0xEE,0xFF,0xFF,0x1A, + 0xFE,0x80,0xBD,0xE8,0x78,0x14,0x9F,0xE5,0x00,0x20,0xA0,0xE3,0x01,0x30,0xA0,0xE3, + 0x00,0x20,0x81,0xE5,0x14,0x30,0x81,0xE5,0x06,0x30,0xA0,0xE3,0x18,0x20,0x81,0xE5, + 0x1C,0x20,0x81,0xE5,0x20,0x20,0x81,0xE5,0x24,0x20,0x81,0xE5,0x28,0x20,0x81,0xE5, + 0x2C,0x20,0x81,0xE5,0x30,0x20,0x81,0xE5,0x46,0x30,0xC1,0xE5,0x34,0x20,0x81,0xE5, + 0x38,0x20,0x81,0xE5,0x3C,0x20,0x81,0xE5,0x40,0x20,0x81,0xE5,0xAC,0xFF,0xFF,0xEA, + 0xF0,0x41,0x2D,0xE9,0x80,0x00,0x10,0xE3,0x03,0x60,0xA0,0xE1,0x02,0x70,0xA0,0xE1, + 0x18,0x80,0x9D,0xE5,0x01,0x50,0xA0,0xE1,0x00,0x40,0xA0,0xE1,0x07,0x00,0x00,0x0A, + 0x80,0x40,0xC4,0xE3,0x06,0x20,0xA0,0xE1,0x08,0x30,0xA0,0xE1,0x07,0x10,0xA0,0xE1, + 0x04,0x00,0xA0,0xE1,0x7F,0x00,0x00,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18, + 0x07,0x00,0xA0,0xE1,0xDA,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18, + 0x00,0x10,0xA0,0xE3,0x01,0x20,0xA0,0xE3,0x0C,0x30,0xA0,0xE3,0xD0,0x03,0x9F,0xE5, + 0x1C,0xC0,0x80,0xE2,0x00,0x10,0x80,0xE5,0x0C,0x10,0x80,0xE5,0x14,0x20,0x80,0xE5, + 0x18,0x10,0x80,0xE5,0x0A,0x00,0x8C,0xE8,0x24,0x10,0x80,0xE5,0x28,0x10,0x80,0xE5, + 0x2C,0x10,0x80,0xE5,0x30,0x10,0x80,0xE5,0x46,0x20,0xC0,0xE5,0x4C,0x40,0xC0,0xE5, + 0x4D,0x50,0xC0,0xE5,0x4E,0x10,0xC0,0xE5,0x4F,0x10,0xC0,0xE5,0x34,0x10,0x80,0xE5, + 0x38,0x10,0x80,0xE5,0x3C,0x10,0x80,0xE5,0x40,0x10,0x80,0xE5,0x00,0x10,0x80,0xE2, + 0x07,0x00,0xA0,0xE1,0x7E,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18, + 0x08,0x20,0xA0,0xE1,0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8, + 0xA1,0xFF,0xFF,0xEA,0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x50,0x43,0x9F,0xE5, + 0x03,0x60,0xB0,0xE1,0x00,0x80,0xA0,0xE1,0x01,0x00,0xA0,0xE3,0x01,0x70,0xA0,0xE1, + 0x08,0x10,0xA0,0xE3,0x14,0x30,0x84,0xE2,0x00,0x50,0x84,0xE5,0x10,0x50,0x84,0xE5, + 0x21,0x00,0x83,0xE8,0x1C,0x50,0x84,0xE5,0x24,0x10,0x84,0xE5,0x35,0x10,0xA0,0xE3, + 0x20,0x50,0x84,0xE5,0x2C,0x00,0x84,0xE5,0x28,0x50,0x84,0xE5,0x30,0x00,0x84,0xE5, + 0x02,0x00,0xA0,0xE1,0x46,0x10,0xC4,0xE5,0x00,0x10,0x84,0xE2,0x58,0x50,0x84,0xE5, + 0x5C,0x50,0x84,0xE5,0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5, + 0x40,0x50,0x84,0xE5,0x5A,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18, + 0x00,0x00,0x56,0xE3,0x50,0x10,0xD4,0xE5,0x00,0x10,0xC8,0xE5,0xB0,0x15,0xD4,0x11, + 0x21,0x14,0xA0,0x11,0x00,0x10,0xC7,0x15,0x00,0x50,0xC7,0x05,0xF0,0x81,0xBD,0xE8, + 0x38,0x40,0x2D,0xE9,0x10,0x40,0x9D,0xE5,0x00,0x40,0x8D,0xE5,0x57,0x00,0x00,0xEB, + 0x38,0x80,0xBD,0xE8,0xF0,0x40,0x2D,0xE9,0x03,0x40,0xA0,0xE1,0x14,0xD0,0x4D,0xE2, + 0x00,0x50,0xA0,0xE1,0x02,0x60,0xA0,0xE1,0x01,0x70,0xA0,0xE1,0x00,0x30,0x8D,0xE5, + 0x02,0x30,0xA0,0xE1,0x01,0x20,0xA0,0xE1,0x0C,0x10,0x8D,0xE2,0x04,0x00,0x8D,0xE2, + 0x42,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x1C,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1, + 0x07,0x20,0xA0,0xE1,0x10,0x10,0x8D,0xE2,0x08,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5, + 0xBF,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x14,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1, + 0x08,0x00,0xDD,0xE5,0x07,0x20,0xA0,0xE1,0x00,0x40,0x8D,0xE5,0x01,0x10,0xC0,0xE3, + 0x04,0x00,0xDD,0xE5,0x81,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x1A, + 0x01,0x00,0x55,0xE3,0x04,0x00,0xDD,0xE5,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1, + 0x00,0x40,0x8D,0xE5,0x1C,0x00,0x80,0x13,0x1C,0x00,0xC0,0x03,0x04,0x00,0xCD,0xE5, + 0x08,0x00,0xDD,0xE5,0x01,0x10,0x80,0xE3,0x04,0x00,0xDD,0xE5,0x73,0xFF,0xFF,0xEB, + 0x14,0xD0,0x8D,0xE2,0xF0,0x80,0xBD,0xE8,0xF0,0x41,0x2D,0xE9,0x00,0x40,0xA0,0xE1, + 0x03,0x50,0xA0,0xE1,0x02,0x60,0xA0,0xE1,0x01,0x70,0xA0,0xE1,0x01,0x00,0xA0,0xE1, + 0x57,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x00,0x10,0xA0,0xE3, + 0x01,0x20,0xA0,0xE3,0x08,0x30,0xA0,0xE3,0xC4,0x01,0x9F,0xE5,0x1C,0x80,0x80,0xE2, + 0x00,0x10,0x80,0xE5,0x0C,0x10,0x80,0xE5,0x14,0x20,0x80,0xE5,0x18,0x10,0x80,0xE5, + 0x0A,0x00,0x88,0xE8,0x24,0x10,0x80,0xE5,0x28,0x10,0x80,0xE5,0x2C,0x10,0x80,0xE5, + 0x30,0x10,0x80,0xE5,0x46,0x20,0xC0,0xE5,0x4C,0x40,0xC0,0xE5,0x4D,0x10,0xC0,0xE5, + 0x4E,0x10,0xC0,0xE5,0x4F,0x10,0xC0,0xE5,0x34,0x10,0x80,0xE5,0x38,0x10,0x80,0xE5, + 0x3C,0x10,0x80,0xE5,0x40,0x10,0x80,0xE5,0x00,0x10,0x80,0xE2,0x07,0x00,0xA0,0xE1, + 0xFB,0xFE,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF0,0x81,0xBD,0x18,0x05,0x20,0xA0,0xE1, + 0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0xF0,0x41,0xBD,0xE8,0x1E,0xFF,0xFF,0xEA, + 0xF0,0x40,0x2D,0xE9,0x03,0x40,0xA0,0xE1,0x1C,0xD0,0x4D,0xE2,0x02,0x50,0xA0,0xE1, + 0x01,0x60,0xA0,0xE1,0x00,0x70,0xA0,0xE1,0x00,0x20,0xA0,0xE1,0x00,0x30,0x8D,0xE5, + 0x01,0x30,0xA0,0xE1,0x0C,0x10,0x8D,0xE2,0x08,0x00,0x8D,0xE2,0xEB,0xFE,0xFF,0xEB, + 0x00,0x00,0x50,0xE3,0x1F,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1, + 0x10,0x10,0x8D,0xE2,0x04,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5,0x68,0xFF,0xFF,0xEB, + 0x00,0x00,0x50,0xE3,0x17,0x00,0x00,0x1A,0x06,0x30,0xA0,0xE1,0x07,0x20,0xA0,0xE1, + 0x18,0x10,0x8D,0xE2,0x14,0x00,0x8D,0xE2,0x00,0x40,0x8D,0xE5,0x13,0x00,0x00,0xEB, + 0x00,0x00,0x50,0xE3,0x0F,0x00,0x00,0x1A,0x02,0x00,0x55,0xE3,0x04,0x00,0xDD,0x05, + 0x02,0x00,0xC0,0x03,0x04,0x00,0x00,0x0A,0x03,0x00,0x55,0xE3,0x04,0x00,0xDD,0x05, + 0x02,0x00,0x80,0x03,0x00,0x00,0xE0,0x13,0x06,0x00,0x00,0x1A,0x3F,0x10,0x00,0xE2, + 0x08,0x00,0xDD,0xE5,0x06,0x30,0xA0,0xE1,0x04,0x10,0xCD,0xE5,0x07,0x20,0xA0,0xE1, + 0x00,0x40,0x8D,0xE5,0x19,0xFF,0xFF,0xEB,0x1C,0xD0,0x8D,0xE2,0xF0,0x80,0xBD,0xE8, + 0xF0,0x41,0x2D,0xE9,0x00,0x50,0xA0,0xE3,0x84,0x40,0x9F,0xE5,0x03,0x80,0xA0,0xE1, + 0x00,0x70,0xA0,0xE1,0x01,0x00,0xA0,0xE3,0x01,0x60,0xA0,0xE1,0x08,0x10,0xA0,0xE3, + 0x14,0x30,0x84,0xE2,0x00,0x50,0x84,0xE5,0x10,0x50,0x84,0xE5,0x21,0x00,0x83,0xE8, + 0x24,0x30,0x84,0xE2,0x1C,0x50,0x84,0xE5,0x20,0x50,0x84,0xE5,0x22,0x00,0x83,0xE8, + 0x16,0x10,0xA0,0xE3,0x2C,0x00,0x84,0xE5,0x30,0x00,0x84,0xE5,0x02,0x00,0xA0,0xE1, + 0x46,0x10,0xC4,0xE5,0x00,0x10,0x84,0xE2,0x58,0x50,0x84,0xE5,0x5C,0x50,0x84,0xE5, + 0x34,0x50,0x84,0xE5,0x38,0x50,0x84,0xE5,0x3C,0x50,0x84,0xE5,0x40,0x50,0x84,0xE5, + 0xA7,0xFE,0xFF,0xEB,0x50,0x10,0xD4,0xE5,0x00,0x00,0x58,0xE3,0x00,0x10,0xC7,0xE5, + 0xB0,0x15,0xD4,0x11,0x00,0x50,0xC6,0x05,0x21,0x14,0xA0,0x11,0x00,0x10,0xC6,0x15, + 0xF0,0x81,0xBD,0xE8,0xA4,0x2A,0x02,0x20,0x89,0x05,0x00,0xEA,0x9D,0x05,0x00,0xEA, + 0x73,0x05,0x00,0xEA,0xF8,0x40,0x2D,0xE9,0x02,0x40,0xA0,0xE1,0x18,0x20,0x8D,0xE2, + 0x03,0xC0,0xA0,0xE1,0x01,0x60,0xA0,0xE1,0x00,0x70,0xA0,0xE1,0x28,0x00,0x92,0xE8, + 0x0C,0x20,0xA0,0xE1,0x00,0x40,0x8D,0xE5,0x2E,0x04,0x00,0xEB,0x00,0x00,0x50,0xE3, + 0x0B,0x00,0x00,0x1A,0x00,0x00,0x54,0xE3,0x02,0x20,0xA0,0x03,0x03,0x00,0x00,0x0A, + 0x02,0x00,0x54,0xE3,0x03,0x20,0xA0,0x03,0x00,0x00,0xE0,0x13,0x04,0x00,0x00,0x1A, + 0x04,0x30,0xA0,0xE1,0x06,0x10,0xA0,0xE1,0x07,0x00,0xA0,0xE1,0x00,0x50,0x8D,0xE5, + 0x32,0xFF,0xFF,0xEB,0xF8,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3, + 0x02,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x00,0x00,0xE0,0x83,0x70,0x80,0xBD,0x88, + 0x00,0x00,0x51,0xE3,0x00,0x10,0xA0,0x03,0x01,0x10,0xA0,0x13,0x0B,0x20,0xD4,0xE5, + 0xE9,0x03,0x00,0xEB,0x00,0x00,0x50,0xE3,0x70,0x80,0xBD,0x18,0x04,0x10,0xA0,0xE1, + 0x05,0x00,0xA0,0xE1,0x70,0x40,0xBD,0xE8,0x9D,0x04,0x00,0xEA,0x01,0x20,0xD1,0xE5, + 0x02,0x00,0x52,0xE3,0x0E,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,0x12,0x00,0x00,0x8A, + 0x06,0x00,0xD1,0xE5,0x0F,0x00,0x50,0xE3,0x07,0x00,0xD1,0x95,0x02,0x00,0x50,0x93, + 0x0D,0x00,0x00,0x8A,0x08,0x00,0xD1,0xE5,0x07,0x00,0x50,0xE3,0x09,0x00,0xD1,0x95, + 0x01,0x00,0x50,0x93,0x08,0x00,0x00,0x8A,0x0A,0x00,0xD1,0xE5,0x02,0x00,0x50,0xE3, + 0x0B,0x00,0xD1,0x95,0x02,0x00,0x50,0x93,0x03,0x00,0x00,0x8A,0x0D,0x00,0xD1,0xE5, + 0x03,0x00,0x50,0xE3,0x00,0x00,0xA0,0x93,0x1E,0xFF,0x2F,0x91,0x00,0x00,0xE0,0xE3, + 0x1E,0xFF,0x2F,0xE1,0xF8,0x40,0x2D,0xE9,0x01,0x50,0xA0,0xE1,0x02,0x40,0xA0,0xE1, + 0x00,0x60,0xA0,0xE1,0x02,0x10,0xA0,0xE1,0xDF,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3, + 0x1B,0x00,0x00,0x1A,0x05,0x10,0xA0,0xE1,0x0B,0x00,0xD4,0xE5,0x00,0x00,0x8D,0xE5, + 0x06,0x00,0xA0,0xE1,0x0D,0x30,0xD4,0xE5,0x0C,0x20,0xD4,0xE5,0xE5,0x03,0x00,0xEB, + 0x00,0x00,0x50,0xE3,0x12,0x00,0x00,0x1A,0x0B,0x30,0xD4,0xE5,0x00,0x00,0x53,0xE3, + 0x02,0x20,0xA0,0x03,0x03,0x00,0x00,0x0A,0x02,0x00,0x53,0xE3,0x03,0x20,0xA0,0x03, + 0x00,0x00,0xE0,0x13,0x0A,0x00,0x00,0x1A,0x05,0x10,0xA0,0xE1,0x0F,0x00,0xD4,0xE5, + 0x00,0x00,0x8D,0xE5,0x06,0x00,0xA0,0xE1,0xE8,0xFE,0xFF,0xEB,0x00,0x00,0x50,0xE3, + 0x03,0x00,0x00,0x1A,0x04,0x20,0xA0,0xE1,0x05,0x10,0xA0,0xE1,0x06,0x00,0xA0,0xE1, + 0xB0,0xFF,0xFF,0xEB,0xF8,0x80,0xBD,0xE8,0x52,0x04,0x00,0xEA,0x70,0x40,0x2D,0xE9, + 0x01,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x7F,0x06,0x00,0xEB,0x04,0x10,0xA0,0xE1, + 0x05,0x00,0xA0,0xE1,0x70,0x40,0xBD,0xE8,0xB7,0xFF,0xFF,0xEA,0xF7,0x4F,0x2D,0xE9, + 0x01,0x00,0x50,0xE3,0x01,0x40,0xA0,0xE1,0x00,0x00,0xE0,0x83,0x92,0x03,0x00,0x8A, + 0x00,0x00,0x50,0xE3,0xE5,0x00,0x00,0x0A,0x01,0x3A,0xA0,0xE3,0x3C,0x5E,0x9F,0xE5, + 0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x38,0xFC,0xFF,0xEB, + 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0x62,0x85,0xE1, + 0x06,0x00,0xA0,0xE1,0x32,0xFC,0xFF,0xEB,0x3D,0x7C,0x45,0xE2,0x01,0x3A,0xA0,0xE3, + 0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x2C,0xFC,0xFF,0xEB, + 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0x82,0x87,0xE0, + 0x08,0x00,0xA0,0xE1,0x26,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x02,0x93,0x26,0xE0,0x09,0x00,0xA0,0xE1,0x20,0xFC,0xFF,0xEB, + 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1, + 0x1B,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x82,0xA3,0x27,0xE0,0x0A,0x00,0xA0,0xE1,0x15,0xFC,0xFF,0xEB,0x01,0x10,0xA0,0xE3, + 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0xB4,0x8A,0xE0,0x0B,0x00,0xA0,0xE1, + 0x0F,0xFC,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x82,0x03,0x88,0xE0,0x0A,0xFC,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x05,0xFC,0xFF,0xEB,0x01,0x3A,0xA0,0xE3, + 0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x00,0xFC,0xFF,0xEB, + 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1, + 0xFB,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x06,0x00,0xA0,0xE1,0xF6,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xF1,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3, + 0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xEC,0xFB,0xFF,0xEB, + 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1, + 0xE7,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x06,0x00,0xA0,0xE1,0xE2,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0xDD,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3, + 0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xD8,0xFB,0xFF,0xEB, + 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0xC3,0x01,0x8B,0xE0, + 0xD3,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x09,0x00,0xA0,0xE1,0xCE,0xFB,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xC9,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3, + 0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xC4,0xFB,0xFF,0xEB, + 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1, + 0xBF,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x07,0x00,0xA0,0xE1,0xBA,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xB5,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3, + 0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xB0,0xFB,0xFF,0xEB, + 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1, + 0xAB,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x0A,0x00,0xA0,0xE1,0xA6,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xA1,0xFB,0xFF,0xEB,0x0E,0x20,0xA0,0xE3, + 0x01,0x39,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x03,0x87,0xE0,0x9C,0xFB,0xFF,0xEB, + 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1, + 0x97,0xFB,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x08,0x00,0xA0,0xE1,0x92,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x8D,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3, + 0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x88,0xFB,0xFF,0xEB, + 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1, + 0x83,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x08,0x00,0xA0,0xE1,0x7E,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x79,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3, + 0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x74,0xFB,0xFF,0xEB, + 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1, + 0x6F,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x0B,0x00,0xA0,0xE1,0x6A,0xFB,0xFF,0xEB,0x0F,0x20,0xA0,0xE3,0x02,0x39,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x02,0x04,0x2A,0xE0,0x65,0xFB,0xFF,0xEB,0x02,0x39,0xA0,0xE3, + 0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x60,0xFB,0xFF,0xEB, + 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1, + 0x5B,0xFB,0xFF,0xEB,0x02,0x00,0x54,0xE3,0x3B,0x02,0x00,0x0A,0xA9,0x02,0x00,0xEA, + 0xAC,0x5A,0x9F,0xE5,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x05,0x00,0xA0,0xE1,0x52,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x82,0x63,0x85,0xE1,0x06,0x00,0xA0,0xE1,0x4C,0xFB,0xFF,0xEB, + 0x3D,0x7C,0x45,0xE2,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x07,0x00,0xA0,0xE1,0x46,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x82,0x83,0x87,0xE0,0x08,0x00,0xA0,0xE1,0x40,0xFB,0xFF,0xEB, + 0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x93,0x86,0xE0, + 0x09,0x00,0xA0,0xE1,0x3A,0xFB,0xFF,0xEB,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x35,0xFB,0xFF,0xEB,0x01,0x10,0xA0,0xE3, + 0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0xA4,0x88,0xE1,0x0A,0x00,0xA0,0xE1, + 0x2F,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3,0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x82,0xB3,0x8A,0xE0,0x0B,0x00,0xA0,0xE1,0x29,0xFB,0xFF,0xEB,0x02,0x20,0xA0,0xE3, + 0x04,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x82,0x04,0x8B,0xE0,0x24,0xFB,0xFF,0xEB, + 0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1, + 0x1F,0xFB,0xFF,0xEB,0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x08,0x00,0xA0,0xE1,0x1A,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x15,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3, + 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x10,0xFB,0xFF,0xEB, + 0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1, + 0x0B,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x08,0x00,0xA0,0xE1,0x06,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x01,0xFB,0xFF,0xEB,0x08,0x30,0xA0,0xE3, + 0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xFC,0xFA,0xFF,0xEB, + 0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1, + 0xF7,0xFA,0xFF,0xEB,0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x0B,0x00,0xA0,0xE1,0xF2,0xFA,0xFF,0xEB,0x03,0x20,0xA0,0xE3,0x08,0x30,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x82,0x04,0x88,0xE0,0xED,0xFA,0xFF,0xEB,0x08,0x30,0xA0,0xE3, + 0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xE8,0xFA,0xFF,0xEB, + 0x08,0x30,0xA0,0xE3,0x03,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1, + 0xE3,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x05,0x00,0xA0,0xE1,0xDE,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xD9,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3, + 0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xD4,0xFA,0xFF,0xEB, + 0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1, + 0xCF,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x09,0x00,0xA0,0xE1,0xCA,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0xC5,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3, + 0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0xC0,0xFA,0xFF,0xEB, + 0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1, + 0xBB,0xFA,0xFF,0xEB,0x04,0x20,0xA0,0xE3,0x10,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x02,0x04,0x8B,0xE0,0xB6,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xB1,0xFA,0xFF,0xEB,0x10,0x30,0xA0,0xE3, + 0x04,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xAC,0xFA,0xFF,0xEB, + 0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1, + 0xA7,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x06,0x00,0xA0,0xE1,0xA2,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x9D,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3, + 0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x98,0xFA,0xFF,0xEB, + 0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1, + 0x93,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x06,0x00,0xA0,0xE1,0x8E,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x89,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3, + 0x05,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0x84,0xFA,0xFF,0xEB, + 0x05,0x20,0xA0,0xE3,0x20,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x02,0x04,0x8A,0xE0, + 0x7F,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x09,0x00,0xA0,0xE1,0x7A,0xFA,0xFF,0xEB,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x75,0xFA,0xFF,0xEB,0x02,0x00,0x54,0xE3, + 0xC4,0x01,0x00,0x1A,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x05,0x00,0xA0,0xE1,0x6E,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x69,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3, + 0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x64,0xFA,0xFF,0xEB, + 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1, + 0x5F,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x09,0x00,0xA0,0xE1,0x5A,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x55,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3, + 0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x50,0xFA,0xFF,0xEB, + 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1, + 0x4B,0xFA,0xFF,0xEB,0x06,0x20,0xA0,0xE3,0x40,0x30,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x02,0x44,0x88,0xE0,0x04,0x00,0xA0,0xE1,0x45,0xFA,0xFF,0xEB,0x40,0x30,0xA0,0xE3, + 0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x40,0xFA,0xFF,0xEB, + 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1, + 0x3B,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x05,0x00,0xA0,0xE1,0x36,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x31,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3, + 0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x2C,0xFA,0xFF,0xEB, + 0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1, + 0x27,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x09,0x00,0xA0,0xE1,0x22,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x1D,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3, + 0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x18,0xFA,0xFF,0xEB, + 0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1, + 0x13,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x04,0x00,0xA0,0xE1,0x0E,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3,0x07,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x09,0xFA,0xFF,0xEB,0x80,0x30,0xA0,0xE3, + 0x07,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x04,0xFA,0xFF,0xEB, + 0x08,0x00,0x9D,0xE5,0x01,0x00,0x50,0xE3,0x52,0x01,0x00,0x1A,0x1C,0x40,0x45,0xE2, + 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1, + 0xFB,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x43,0x52,0x84,0xE1,0x05,0x00,0xA0,0xE1,0xF5,0xF9,0xFF,0xEB,0x3D,0x6C,0x44,0xE2, + 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1, + 0xEF,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x43,0x72,0x86,0xE0,0x07,0x00,0xA0,0xE1,0xE9,0xF9,0xFF,0xEB,0x0C,0x20,0xA0,0xE3, + 0x01,0x3A,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x02,0x83,0x25,0xE0,0x08,0x00,0xA0,0xE1, + 0xE3,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x05,0x00,0xA0,0xE1,0xDE,0xF9,0xFF,0xEB,0x01,0x10,0xA0,0xE3,0x01,0x3A,0xA0,0xE3, + 0x0C,0x20,0xA0,0xE3,0x01,0x94,0x87,0xE1,0x09,0x00,0xA0,0xE1,0xD8,0xF9,0xFF,0xEB, + 0x01,0x10,0xA0,0xE3,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0xA4,0x89,0xE0, + 0x0A,0x00,0xA0,0xE1,0xD2,0xF9,0xFF,0xEB,0x0C,0x20,0xA0,0xE3,0x01,0x3A,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x82,0xB3,0x87,0xE0,0x0B,0x00,0xA0,0xE1,0xCC,0xF9,0xFF,0xEB, + 0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1, + 0xC7,0xF9,0xFF,0xEB,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x07,0x00,0xA0,0xE1,0xC2,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0xBD,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3, + 0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xB8,0xF9,0xFF,0xEB, + 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1, + 0xB3,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x07,0x00,0xA0,0xE1,0xAE,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xA9,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3, + 0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xA4,0xF9,0xFF,0xEB, + 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1, + 0x9F,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x0A,0x00,0xA0,0xE1,0x9A,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0x95,0xF9,0xFF,0xEB,0x02,0x3A,0xA0,0xE3, + 0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x90,0xF9,0xFF,0xEB, + 0x02,0x3A,0xA0,0xE3,0x0D,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1, + 0x8B,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x04,0x00,0xA0,0xE1,0x86,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x81,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3, + 0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x7C,0xF9,0xFF,0xEB, + 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1, + 0x77,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x08,0x00,0xA0,0xE1,0x72,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x6D,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3, + 0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x68,0xF9,0xFF,0xEB, + 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1, + 0x63,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x0B,0x00,0xA0,0xE1,0x5E,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x59,0xF9,0xFF,0xEB,0x01,0x39,0xA0,0xE3, + 0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x54,0xF9,0xFF,0xEB, + 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1, + 0x4F,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x05,0x00,0xA0,0xE1,0x4A,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1,0x45,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3, + 0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x40,0xF9,0xFF,0xEB, + 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1, + 0x3B,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x05,0x00,0xA0,0xE1,0x36,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x31,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3, + 0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0A,0x00,0xA0,0xE1,0x2C,0xF9,0xFF,0xEB, + 0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1, + 0x27,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x08,0x00,0xA0,0xE1,0x22,0xF9,0xFF,0xEB,0x02,0x39,0xA0,0xE3,0x0F,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x6D,0x00,0x00,0xEA,0x01,0x3B,0xA0,0xE3, + 0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0x18,0xF9,0xFF,0xEB, + 0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1, + 0x13,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x07,0x00,0xA0,0xE1,0x0E,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0x09,0xF9,0xFF,0xEB,0x01,0x3B,0xA0,0xE3, + 0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0x04,0xF9,0xFF,0xEB, + 0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1, + 0xFF,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x0A,0x00,0xA0,0xE1,0xFA,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xF5,0xF8,0xFF,0xEB,0x24,0x41,0x9F,0xE5, + 0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1, + 0xEF,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x09,0x00,0xA0,0xE1,0xEA,0xF8,0xFF,0xEB,0x01,0x3B,0xA0,0xE3,0x0A,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xE5,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3, + 0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x05,0x00,0xA0,0xE1,0xE0,0xF8,0xFF,0xEB, + 0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1, + 0xDB,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x07,0x00,0xA0,0xE1,0xD6,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x08,0x00,0xA0,0xE1,0xD1,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3, + 0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1,0xCC,0xF8,0xFF,0xEB, + 0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x06,0x00,0xA0,0xE1, + 0xC7,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x0A,0x00,0xA0,0xE1,0xC2,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x0B,0x00,0xA0,0xE1,0xBD,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3, + 0x0B,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0xA0,0xE1,0xB8,0xF8,0xFF,0xEB, + 0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x09,0x00,0xA0,0xE1, + 0xB3,0xF8,0xFF,0xEB,0x02,0x3B,0xA0,0xE3,0x0B,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x08,0x00,0xA0,0xE1,0xAE,0xF8,0xFF,0xEB,0x00,0x00,0xA0,0xE3,0xFE,0x8F,0xBD,0xE8, + 0x20,0x70,0xFE,0xFC,0x24,0x70,0xFE,0xFC,0x20,0x3A,0xFE,0xFC,0xF0,0x41,0x2D,0xE9, + 0x01,0x00,0x50,0xE3,0x02,0x70,0xA0,0xE1,0x01,0x50,0xA0,0xE1,0x00,0x40,0xA0,0xE1, + 0x15,0x00,0x00,0x8A,0x54,0x6B,0x9F,0xE5,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x04,0x01,0x96,0xE7,0x48,0x00,0x80,0xE2,0xB3,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3, + 0x0D,0x00,0x00,0x1A,0x04,0x01,0x96,0xE7,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0xAD,0xF8,0xFF,0xEB,0x05,0x00,0x50,0xE1,0x14,0x00,0x00,0x0A,0x01,0x00,0x55,0xE3, + 0x07,0x00,0x00,0x1A,0x05,0x20,0xA0,0xE1,0x07,0x10,0xA0,0xE1,0x04,0x00,0xA0,0xE1, + 0x49,0xFC,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0xAA,0x00,0x00,0xE0,0xE3, + 0xF0,0x81,0xBD,0xE8,0x04,0x01,0x96,0xE7,0x03,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3, + 0x05,0x10,0xA0,0xE1,0x8D,0xF8,0xFF,0xEB,0x04,0x01,0x96,0xE7,0x02,0x3C,0xA0,0xE3, + 0x09,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,0x87,0xF8,0xFF,0xEB, + 0x00,0x00,0xA0,0xE3,0xF0,0x81,0xBD,0xE8,0xF0,0x47,0x2D,0xE9,0x01,0x00,0x50,0xE3, + 0x03,0x70,0xA0,0xE1,0x02,0x80,0xA0,0xE1,0x20,0x60,0x9D,0xE5,0x01,0x90,0xA0,0xE1, + 0x00,0x40,0xA0,0xE1,0x71,0x00,0x00,0x8A,0x01,0x20,0xA0,0xE1,0x06,0x10,0xA0,0xE1, + 0x2D,0xFC,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x6C,0x00,0x00,0xBA,0x01,0x20,0xA0,0xE3, + 0x88,0x5A,0x9F,0xE5,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x48,0x00,0x80,0xE2, + 0x81,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x64,0x00,0x00,0x1A,0x04,0x01,0x95,0xE7, + 0x03,0x35,0xA0,0xE3,0x16,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x6B,0xF8,0xFF,0xEB, + 0x04,0x01,0x95,0xE7,0x03,0x36,0xA0,0xE3,0x14,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3, + 0x66,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x37,0xA0,0xE3,0x12,0x20,0xA0,0xE3, + 0x03,0x10,0xA0,0xE3,0x61,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x38,0xA0,0xE3, + 0x10,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x5C,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7, + 0x03,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3,0x57,0xF8,0xFF,0xEB, + 0x04,0x01,0x95,0xE7,0x03,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE3, + 0x52,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x03,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3, + 0x03,0x10,0xA0,0xE3,0x4D,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x34,0xA0,0xE3, + 0x18,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x48,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7, + 0x40,0x30,0xA0,0xE3,0x06,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x43,0xF8,0xFF,0xEB, + 0x04,0x01,0x95,0xE7,0x20,0x30,0xA0,0xE3,0x05,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x3E,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x39,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x08,0x30,0xA0,0xE3, + 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x34,0xF8,0xFF,0xEB,0x06,0x20,0xA0,0xE1, + 0x09,0x10,0xA0,0xE1,0x04,0x00,0xA0,0xE1,0x7F,0xFF,0xFF,0xEB,0x04,0x01,0x95,0xE7, + 0x07,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x00,0x80,0xE2, + 0x2A,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x07,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x04,0x00,0x80,0xE2,0x24,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7, + 0x00,0x20,0xA0,0xE3,0x07,0x30,0xA0,0xE3,0x02,0x10,0xA0,0xE1,0x04,0x00,0x80,0xE2, + 0x1E,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0xFF,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3, + 0x08,0x10,0xA0,0xE1,0x08,0x00,0x80,0xE2,0x18,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7, + 0x03,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,0x07,0x10,0xA0,0xE1,0x08,0x00,0x80,0xE2, + 0x12,0xF8,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x48,0x00,0x80,0xE2,0x1C,0xF8,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A, + 0x00,0x00,0xE0,0xE3,0xF0,0x87,0xBD,0xE8,0x04,0x11,0x95,0xE7,0x08,0x05,0x0A,0xE3, + 0x50,0x00,0x81,0xE5,0x04,0x11,0x95,0xE7,0xC4,0x08,0x9F,0xE5,0x68,0x00,0x81,0xE5, + 0x00,0x00,0xA0,0xE3,0xF0,0x87,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1, + 0xA8,0x58,0x9F,0xE5,0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7, + 0x48,0x00,0x80,0xE2,0x08,0xF8,0xFF,0xEB,0x01,0x00,0x50,0xE3,0xF8,0xFF,0xFF,0x1A, + 0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,0x01,0x60,0xA0,0xE1, + 0x00,0x40,0xA0,0xE1,0x07,0x00,0x00,0x8A,0x01,0x20,0xA0,0xE3,0x6C,0x58,0x9F,0xE5, + 0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x48,0x00,0x80,0xE2,0xFA,0xF7,0xFF,0xEB, + 0x01,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,0x00,0x00,0xE0,0xE3,0x70,0x80,0xBD,0xE8, + 0x04,0x01,0x95,0xE7,0x02,0x31,0xA0,0xE3,0x1F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0xE2,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x0F,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2,0xDC,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7, + 0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x0C,0x00,0x80,0xE2, + 0xD6,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3, + 0x03,0x10,0xA0,0xE1,0x0C,0x00,0x80,0xE2,0xD0,0xF7,0xFF,0xEB,0x00,0x10,0xD6,0xE5, + 0xFF,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x10,0x20,0xA0,0xE3,0x10,0x00,0x80,0xE2, + 0xCA,0xF7,0xFF,0xEB,0x01,0x10,0xD6,0xE5,0x03,0x31,0xA0,0xE3,0x04,0x01,0x95,0xE7, + 0x1E,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xC4,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7, + 0x01,0x39,0xA0,0xE3,0x0E,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2, + 0xBE,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0xFF,0x30,0xA0,0xE3, + 0x02,0x10,0xA0,0xE1,0x10,0x00,0x80,0xE2,0xB8,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7, + 0x03,0x32,0xA0,0xE3,0x1C,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2, + 0xB2,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x3A,0xA0,0xE3,0x0C,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xAC,0xF7,0xFF,0xEB,0x0E,0x10,0xD6,0xE5, + 0x03,0x34,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x18,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2, + 0xA6,0xF7,0xFF,0xEB,0x0F,0x10,0xD6,0xE5,0x0F,0x3C,0xA0,0xE3,0x04,0x01,0x95,0xE7, + 0x08,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0xA0,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7, + 0xFF,0x38,0xA0,0xE3,0x10,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x14,0x00,0x80,0xE2, + 0x9A,0xF7,0xFF,0xEB,0x02,0x10,0xD6,0xE5,0xFF,0x34,0xA0,0xE3,0x04,0x01,0x95,0xE7, + 0x18,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,0x94,0xF7,0xFF,0xEB,0x03,0x10,0xD6,0xE5, + 0xFF,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x10,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2, + 0x8E,0xF7,0xFF,0xEB,0x04,0x10,0xD6,0xE5,0xFF,0x3C,0xA0,0xE3,0x04,0x01,0x95,0xE7, + 0x08,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2,0x88,0xF7,0xFF,0xEB,0x05,0x10,0xD6,0xE5, + 0xFF,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x18,0x00,0x80,0xE2, + 0x82,0xF7,0xFF,0xEB,0x07,0x10,0xD6,0xE5,0x03,0x36,0xA0,0xE3,0x04,0x01,0x95,0xE7, + 0x14,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0x7C,0xF7,0xFF,0xEB,0x06,0x10,0xD6,0xE5, + 0xF0,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x04,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2, + 0x76,0xF7,0xFF,0xEB,0x0B,0x10,0xD6,0xE5,0x03,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7, + 0x10,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2,0x70,0xF7,0xFF,0xEB,0x09,0x10,0xD6,0xE5, + 0x02,0x39,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x0F,0x20,0xA0,0xE3,0x1C,0x00,0x80,0xE2, + 0x6A,0xF7,0xFF,0xEB,0x0A,0x10,0xD6,0xE5,0x03,0x38,0xA0,0xE3,0x04,0x01,0x95,0xE7, + 0x10,0x20,0xA0,0xE3,0x58,0x00,0x80,0xE2,0x64,0xF7,0xFF,0xEB,0x08,0x10,0xD6,0xE5, + 0x07,0x30,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x58,0x00,0x80,0xE2, + 0x5E,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x01,0x3C,0xA0,0xE3,0x08,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x5C,0x00,0x80,0xE2,0x58,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7, + 0x10,0x30,0xA0,0xE3,0x04,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x5C,0x00,0x80,0xE2, + 0x52,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x00,0x20,0xA0,0xE3,0x01,0x30,0xA0,0xE3, + 0x02,0x10,0xA0,0xE1,0x5C,0x00,0x80,0xE2,0x4C,0xF7,0xFF,0xEB,0x00,0x00,0xA0,0xE3, + 0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x01,0x00,0x50,0xE3,0x00,0x40,0xA0,0xE1, + 0x00,0x00,0xE0,0x83,0x70,0x80,0xBD,0x88,0x01,0x34,0xA0,0xE3,0x18,0x20,0xA0,0xE3, + 0x01,0x10,0xA0,0xE3,0xB4,0x55,0x9F,0xE5,0x04,0x01,0x95,0xE7,0x0C,0x00,0x80,0xE2, + 0x3E,0xF7,0xFF,0xEB,0x04,0x01,0x95,0xE7,0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3, + 0x48,0x00,0x80,0xE2,0x48,0xF7,0xFF,0xEB,0x00,0x00,0x50,0xE3,0xF8,0xFF,0xFF,0x1A, + 0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1,0x7C,0x55,0x9F,0xE5, + 0x02,0x21,0xA0,0xE3,0x1F,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x3E,0xF7,0xFF,0xEB, + 0x00,0x00,0x50,0xE3,0x09,0x00,0x00,0x0A,0x04,0x00,0xA0,0xE1,0xE0,0xFF,0xFF,0xEB, + 0x00,0x00,0x50,0xE3,0x00,0x00,0xE0,0xB3,0x70,0x80,0xBD,0xB8,0x02,0x31,0xA0,0xE3, + 0x1F,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7,0x23,0xF7,0xFF,0xEB, + 0x00,0x00,0xA0,0xE3,0x70,0x80,0xBD,0xE8,0x70,0x40,0x2D,0xE9,0x00,0x40,0xA0,0xE1, + 0x28,0x55,0x9F,0xE5,0x02,0x21,0xA0,0xE3,0x1F,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7, + 0x29,0xF7,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x09,0x00,0x00,0x0A,0x04,0x00,0xA0,0xE1, + 0xCB,0xFF,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x00,0x00,0xE0,0xB3,0x70,0x80,0xBD,0xB8, + 0x02,0x31,0xA0,0xE3,0x1F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x04,0x01,0x95,0xE7, + 0x0E,0xF7,0xFF,0xEB,0x00,0x00,0xA0,0xE3,0x70,0x80,0xBD,0xE8,0xF0,0x41,0x2D,0xE9, + 0x01,0x00,0x50,0xE3,0x01,0x40,0xA0,0xE1,0x00,0x50,0xA0,0xE1,0x19,0x00,0x00,0x8A, + 0x02,0x21,0xA0,0xE3,0xC4,0x64,0x9F,0xE5,0x1F,0x10,0xA0,0xE3,0x05,0x01,0x96,0xE7, + 0x11,0xF7,0xFF,0xEB,0x01,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7, + 0x02,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0x48,0x00,0x80,0xE2,0x0A,0xF7,0xFF,0xEB, + 0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x1A,0x05,0x01,0x96,0xE7,0x02,0x31,0xA0,0xE3, + 0x1F,0x20,0xA0,0xE3,0x01,0x10,0xA0,0xE3,0xF4,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7, + 0x01,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x48,0x00,0x80,0xE2,0xFE,0xF6,0xFF,0xEB, + 0x01,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A,0x00,0x00,0xE0,0xE3,0xF0,0x81,0xBD,0xE8, + 0x05,0x01,0x96,0xE7,0x01,0x39,0xA0,0xE3,0x14,0x10,0x94,0xE5,0x0E,0x20,0xA0,0xE3, + 0x30,0x00,0x80,0xE2,0xE5,0xF6,0xFF,0xEB,0x14,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3, + 0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,0x46,0x10,0xD4,0xE5,0xFF,0x38,0xA0,0xE3, + 0x24,0x00,0x80,0xE2,0x10,0x20,0xA0,0xE3,0xDC,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7, + 0x03,0x31,0xA0,0xE3,0x00,0x10,0x94,0xE5,0x1E,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2, + 0xD6,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3A,0xA0,0xE3,0x18,0x10,0x94,0xE5, + 0x0C,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xD0,0xF6,0xFF,0xEB,0x18,0x00,0x94,0xE5, + 0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7,0x47,0x10,0xD4,0xE5, + 0xFF,0x30,0xA0,0xE3,0x24,0x00,0x80,0xE2,0x00,0x20,0xA0,0xE3,0xC7,0xF6,0xFF,0xEB, + 0x05,0x01,0x96,0xE7,0x03,0x32,0xA0,0xE3,0x04,0x10,0x94,0xE5,0x1C,0x20,0xA0,0xE3, + 0x30,0x00,0x80,0xE2,0xC1,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x0F,0x3C,0xA0,0xE3, + 0x1C,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xBB,0xF6,0xFF,0xEB, + 0x1C,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7, + 0x48,0x10,0x94,0xE5,0x00,0x30,0xE0,0xE3,0x00,0x20,0xA0,0xE3,0x28,0x00,0x80,0xE2, + 0xB2,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x03,0x34,0xA0,0xE3,0x08,0x10,0x94,0xE5, + 0x18,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0xAC,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7, + 0xF0,0x30,0xA0,0xE3,0x20,0x10,0x94,0xE5,0x04,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2, + 0xA6,0xF6,0xFF,0xEB,0x20,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x1D,0x00,0x00,0x0A, + 0x05,0x01,0x96,0xE7,0x4C,0x10,0xD4,0xE5,0xFF,0x34,0xA0,0xE3,0x2C,0x00,0x80,0xE2, + 0x18,0x20,0xA0,0xE3,0x9D,0xF6,0xFF,0xEB,0x4D,0x10,0xD4,0xE5,0xFF,0x38,0xA0,0xE3, + 0x05,0x01,0x96,0xE7,0x10,0x20,0xA0,0xE3,0x2C,0x00,0x80,0xE2,0x97,0xF6,0xFF,0xEB, + 0x4E,0x10,0xD4,0xE5,0xFF,0x3C,0xA0,0xE3,0x05,0x01,0x96,0xE7,0x08,0x20,0xA0,0xE3, + 0x2C,0x00,0x80,0xE2,0x91,0xF6,0xFF,0xEB,0x4F,0x10,0xD4,0xE5,0xFF,0x30,0xA0,0xE3, + 0x05,0x01,0x96,0xE7,0x00,0x20,0xA0,0xE3,0x2C,0x00,0x80,0xE2,0x8B,0xF6,0xFF,0xEB, + 0x05,0x01,0x96,0xE7,0x03,0x36,0xA0,0xE3,0x0C,0x10,0x94,0xE5,0x14,0x20,0xA0,0xE3, + 0x30,0x00,0x80,0xE2,0x85,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x02,0x39,0xA0,0xE3, + 0x34,0x10,0x94,0xE5,0x0F,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2,0x7F,0xF6,0xFF,0xEB, + 0x34,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x00,0x00,0x0A,0x05,0x01,0x96,0xE7, + 0x44,0x10,0xD4,0xE5,0x03,0x38,0xA0,0xE3,0x60,0x00,0x80,0xE2,0x10,0x20,0xA0,0xE3, + 0x76,0xF6,0xFF,0xEB,0x45,0x10,0xD4,0xE5,0x07,0x30,0xA0,0xE3,0x05,0x01,0x96,0xE7, + 0x00,0x20,0xA0,0xE3,0x60,0x00,0x80,0xE2,0x70,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7, + 0x0F,0x30,0xA0,0xE3,0x24,0x10,0x94,0xE5,0x00,0x20,0xA0,0xE3,0x30,0x00,0x80,0xE2, + 0x6A,0xF6,0xFF,0xEB,0x24,0x00,0x94,0xE5,0x58,0x72,0x9F,0xE5,0x00,0x00,0x50,0xE3, + 0x2C,0x00,0x00,0x0A,0x08,0x00,0x50,0xE3,0x04,0x00,0x00,0x0A,0x0C,0x00,0x50,0xE3, + 0x0C,0x00,0x00,0x0A,0x0F,0x00,0x50,0xE3,0x14,0x00,0x00,0x0A,0x1F,0x00,0x00,0xEA, + 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x6A,0xF6,0xFF,0xEB, + 0x00,0x00,0x50,0xE3,0x58,0x00,0xD4,0x05,0x05,0x11,0x96,0x07,0x40,0x00,0xC1,0x05, + 0x06,0x00,0x00,0x1A,0x15,0x00,0x00,0xEA,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x07,0x00,0xA0,0xE1,0x60,0xF6,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x53,0x00,0x00,0x1A, + 0x05,0x11,0x96,0xE7,0xB8,0x05,0xD4,0xE1,0xB0,0x04,0xC1,0xE1,0x0B,0x00,0x00,0xEA, + 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x56,0xF6,0xFF,0xEB, + 0x00,0x00,0x50,0xE3,0x49,0x00,0x00,0x0A,0x05,0x11,0x96,0xE7,0x58,0x00,0x94,0xE5, + 0x40,0x00,0x81,0xE5,0x05,0x01,0x96,0xE7,0x5C,0x10,0x94,0xE5,0x44,0x10,0x80,0xE5, + 0x03,0x38,0xA0,0xE3,0x05,0x01,0x96,0xE7,0x10,0x20,0xA0,0xE3,0x10,0x10,0x94,0xE5, + 0x30,0x00,0x80,0xE2,0x39,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3C,0xA0,0xE3, + 0x28,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x20,0x00,0x80,0xE2,0x33,0xF6,0xFF,0xEB, + 0x10,0x00,0x94,0xE5,0x00,0x00,0x50,0xE3,0x24,0x00,0x94,0x15,0x00,0x00,0x50,0x13, + 0x04,0x00,0x00,0x0A,0x2C,0x00,0x94,0xE5,0x01,0x00,0x50,0xE3,0x30,0x00,0x94,0x05, + 0x01,0x00,0x50,0x03,0x3B,0xFF,0xFF,0x0A,0x05,0x01,0x96,0xE7,0x2C,0x10,0x94,0xE5, + 0x04,0x30,0xA0,0xE3,0x02,0x20,0xA0,0xE3,0x20,0x00,0x80,0xE2,0x23,0xF6,0xFF,0xEB, + 0x05,0x01,0x96,0xE7,0x02,0x30,0xA0,0xE3,0x30,0x10,0x94,0xE5,0x01,0x20,0xA0,0xE3, + 0x20,0x00,0x80,0xE2,0x1D,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x3C,0xA0,0xE3, + 0x38,0x10,0x94,0xE5,0x08,0x20,0xA0,0xE3,0x64,0x00,0x80,0xE2,0x17,0xF6,0xFF,0xEB, + 0x05,0x01,0x96,0xE7,0x10,0x30,0xA0,0xE3,0x3C,0x10,0x94,0xE5,0x04,0x20,0xA0,0xE3, + 0x64,0x00,0x80,0xE2,0x11,0xF6,0xFF,0xEB,0x05,0x01,0x96,0xE7,0x01,0x30,0xA0,0xE3, + 0x40,0x10,0x94,0xE5,0x00,0x20,0xA0,0xE3,0x64,0x00,0x80,0xE2,0x0B,0xF6,0xFF,0xEB, + 0x05,0x01,0x96,0xE7,0x01,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3,0x03,0x10,0xA0,0xE1, + 0x20,0x00,0x80,0xE2,0x05,0xF6,0xFF,0xEB,0x05,0x00,0xA0,0xE1,0xAD,0xF9,0xFF,0xEB, + 0x24,0x00,0x94,0xE5,0x08,0x00,0x50,0xE3,0x08,0x00,0x00,0x0A,0x0C,0x00,0x50,0xE3, + 0x11,0x00,0x00,0x0A,0x0F,0x00,0x50,0xE3,0x16,0x00,0x00,0x0A,0x21,0x00,0x00,0xEA, + 0x05,0x11,0x96,0xE7,0x58,0x00,0x94,0xE5,0x40,0x00,0x81,0xE5,0xB7,0xFF,0xFF,0xEA, + 0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0x02,0xF6,0xFF,0xEB, + 0x00,0x00,0x50,0xE3,0x05,0x01,0x96,0x07,0x38,0x00,0xD0,0x05,0x19,0x00,0x00,0x0A, + 0x05,0x01,0x96,0xE7,0xB8,0x03,0xD0,0xE1,0x16,0x00,0x00,0xEA,0x03,0x20,0xA0,0xE3, + 0x00,0x10,0xA0,0xE3,0x07,0x00,0xA0,0xE1,0xF7,0xF5,0xFF,0xEB,0x00,0x00,0x50,0xE3, + 0x0E,0x00,0x00,0x1A,0xF5,0xFF,0xFF,0xEA,0x03,0x20,0xA0,0xE3,0x00,0x10,0xA0,0xE3, + 0x07,0x00,0xA0,0xE1,0xF0,0xF5,0xFF,0xEB,0x00,0x00,0x50,0xE3,0x07,0x00,0x00,0x0A, + 0x05,0x01,0x96,0xE7,0x38,0x00,0x90,0xE5,0x50,0x00,0x84,0xE5,0x05,0x01,0x96,0xE7, + 0x3C,0x00,0x90,0xE5,0x54,0x00,0x84,0xE5,0x00,0x00,0xA0,0xE3,0xF0,0x81,0xBD,0xE8, + 0x05,0x01,0x96,0xE7,0x38,0x00,0x90,0xE5,0x50,0x00,0x84,0xE5,0xF9,0xFF,0xFF,0xEA, + 0x8C,0x2A,0x02,0x20,0x63,0x63,0x00,0xA5,0x00,0xA0,0xEF,0x3F,0xF0,0x40,0x2D,0xE9, + 0xEB,0xC0,0xA0,0xE3,0x00,0xC0,0xC1,0xE5,0x08,0x70,0xA0,0xE3,0x06,0x70,0xC1,0xE5, + 0x03,0x60,0xA0,0xE3,0x08,0x60,0xC1,0xE5,0x55,0x50,0xA0,0xE3,0x02,0x50,0xC1,0xE5, + 0x01,0x40,0xA0,0xE3,0x09,0x40,0xC1,0xE5,0x02,0x30,0xA0,0xE3,0x0E,0x30,0xC1,0xE5, + 0x00,0x20,0xA0,0xE3,0x07,0x30,0xC1,0xE5,0x00,0x00,0x50,0xE3,0x0B,0x30,0xC1,0xE5, + 0x07,0x00,0xA0,0xE3,0x01,0x20,0xC1,0xE5,0x03,0x20,0xC1,0xE5,0x04,0x20,0xC1,0xE5, + 0x05,0x20,0xC1,0xE5,0x0A,0x20,0xC1,0xE5,0x0C,0x40,0xC1,0x05,0x0C,0x30,0xC1,0x15, + 0x0D,0x20,0xC1,0xE5,0x0F,0x00,0xC1,0xE5,0xF0,0x80,0xBD,0xE8,0x00,0xA0,0xEF,0x3F, + 0x00,0xB0,0xEF,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x5C,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0x00,0x10,0x80,0xE5,0x00,0x00,0x90,0xE5, + 0x50,0x00,0x9F,0xE5,0x35,0x10,0x01,0xE3,0xB0,0x10,0xC0,0xE1,0x00,0x00,0x90,0xE5, + 0x44,0x00,0x9F,0xE5,0x01,0x10,0xA0,0xE3,0xB0,0x10,0xC0,0xE1,0x00,0x00,0x90,0xE5, + 0x10,0x0F,0x11,0xEE,0x02,0x0A,0xC0,0xE3,0x01,0x0A,0xC0,0xE3,0x04,0x00,0xC0,0xE3, + 0x01,0x00,0xC0,0xE3,0x10,0x0F,0x01,0xEE,0x26,0x00,0x00,0xEB,0x1C,0xD0,0x9F,0xE5, + 0x14,0x00,0x00,0xEB,0x0D,0x00,0x00,0xEB,0x0E,0x00,0x00,0xEB,0x0F,0x00,0x00,0xEB, + 0xFE,0xFF,0xFF,0xEA,0x80,0xFF,0xFF,0x3F,0x10,0x00,0xFE,0xFC,0x14,0x00,0xFE,0xFC, + 0x00,0x00,0x03,0x20,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA, + 0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA, + 0x04,0xF0,0x1F,0xE5,0x40,0x00,0x02,0x20,0x04,0xF0,0x1F,0xE5,0x00,0x00,0x02,0x20, + 0x04,0xF0,0x1F,0xE5,0x04,0x02,0x02,0x20,0x2C,0x30,0x9F,0xE5,0x00,0x20,0xA0,0xE3, + 0x28,0x10,0x9F,0xE5,0x28,0x00,0x9F,0xE5,0x10,0x40,0x2D,0xE9,0x23,0x31,0xA0,0xE1, + 0x02,0x00,0x00,0xEA,0x04,0x40,0x91,0xE4,0x01,0x20,0x82,0xE2,0x04,0x40,0x80,0xE4, + 0x03,0x00,0x52,0xE1,0xFA,0xFF,0xFF,0xBA,0x10,0x80,0xBD,0xE8,0xAF,0x01,0x00,0x00, + 0x00,0x02,0x00,0x18,0x00,0x00,0x02,0x20,0x04,0x00,0x9F,0xE5,0x10,0x0F,0x0C,0xEE, + 0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; +#pragma arm section + + diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c new file mode 100644 index 0000000000..b5611b4316 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/mmu_Renesas_RZ_A1.c @@ -0,0 +1,162 @@ +/**************************************************************************//** + * @file mmu_Renesas_RZ_A1.c + * @brief MMU Startup File for + * mmu_Renesas_RZ_A1 Device Series + * @version V1.01 + * @date 2 Aug 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ +#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ +#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ +#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings. +//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors place all memory in domain 0 +//There are no restrictions by privilege level (PL0 can access all memory) + +#include +#include "MBRZA1H.h" + +//Import symbols from linker +extern uint32_t Image$$VECTORS$$Base; +extern uint32_t Image$$RO_DATA$$Base; +extern uint32_t Image$$RW_DATA$$Base; +extern uint32_t Image$$ZI_DATA$$Base; +extern uint32_t Image$$TTB$$ZI$$Base; + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +void create_translation_table(void) +{ + mmu_region_attributes_Type region; + + /* + * Generate descriptors. Refer to MBRZA1H.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + section_normal_nc(Sect_Normal_NC, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Create 4GB of faulting entries + __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); + + // R7S72100 memory map. + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); + + //Define Image + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, 1, Sect_Normal_Cod); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, 1, Sect_Normal_RO); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, 1, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, 1, Sect_Normal_RW); + __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x0 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x1 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x1 (Inner WB WA) */ + __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); +} + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c new file mode 100644 index 0000000000..0bcb985cbf --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c @@ -0,0 +1,128 @@ +/**************************************************************************//** + * @file pl310.c + * @brief Implementation of pl310 functions + * @version + * @date 11 June 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ +#include "MBRZA1H.h" + +//Cache Sync operation +void PL310_Sync(void) +{ + PL310->CACHE_SYNC = 0x0; +} + +//return Cache controller cache ID +int PL310_GetID (void) +{ + return PL310->CACHE_ID; +} + +//return Cache controller cache Type +int PL310_GetType (void) +{ + return PL310->CACHE_TYPE; +} + +//Invalidate all cache by way +void PL310_InvAllByWay (void) +{ + unsigned int assoc; + + if (PL310->AUX_CNT & (1<<16)) + assoc = 16; + else + assoc = 8; + + PL310->INV_WAY = (1 << assoc) - 1; + while(PL310->INV_WAY && ((1 << assoc) - 1)); //poll invalidate + + PL310_Sync(); +} + +//Clean and Invalidate all cache by way +void PL310_CleanInvAllByWay (void) +{ + unsigned int assoc; + + if (PL310->AUX_CNT & (1<<16)) + assoc = 16; + else + assoc = 8; + + PL310->CLEAN_INV_WAY = (1 << assoc) - 1; + while(PL310->CLEAN_INV_WAY && ((1 << assoc) - 1)); //poll invalidate + + PL310_Sync(); +} + +//Enable Cache +void PL310_Enable(void) +{ + PL310->CONTROL = 0; + PL310->INTERRUPT_CLEAR = 0; + PL310->DEBUG_CONTROL = 0; + PL310->DATA_LOCK_0_WAY = 0; + PL310->CACHE_SYNC = 0; + + PL310->CONTROL = 0x01; + PL310_Sync(); +} +//Disable Cache +void PL310_Disable(void) +{ + PL310->CONTROL = 0x00; + PL310_Sync(); +} + +//Invalidate cache by physical address +void PL310_InvPa (void *pa) +{ + PL310->INV_LINE_PA = (unsigned int)pa; + PL310_Sync(); +} + +//Clean cache by physical address +void PL310_CleanPa (void *pa) +{ + PL310->CLEAN_LINE_PA = (unsigned int)pa; + PL310_Sync(); +} + +//Clean and invalidate cache by physical address +void PL310_CleanInvPa (void *pa) +{ + PL310->CLEAN_INV_LINE_PA = (unsigned int)pa; + PL310_Sync(); +} + + diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.h new file mode 100644 index 0000000000..0960a4d1f3 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.h @@ -0,0 +1,114 @@ +/**************************************************************************//** + * @file pl310.h + * @brief Implementation of pl310 functions + * @version + * @date 11 June 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef __PL310 +#define __PL310 + +typedef struct +{ + __I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */ + __I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */ + uint32_t RESERVED0[0x3e]; + __IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */ + __IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */ + uint32_t RESERVED1[0x3e]; + __IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */ + __IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */ + __IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */ + uint32_t RESERVED2[0x2]; + __IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */ + __I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */ + __I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */ + __O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */ + uint32_t RESERVED3[0x143]; + __IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */ + uint32_t RESERVED4[0xf]; + __IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */ + uint32_t RESERVED6[2]; + __IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */ + uint32_t RESERVED5[0xc]; + __IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */ + uint32_t RESERVED7[1]; + __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */ + __IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */ + uint32_t RESERVED8[0xc]; + __IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */ + uint32_t RESERVED9[1]; + __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */ + __IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */ + uint32_t RESERVED10[0x40]; + __IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */ + __IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */ + __IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */ + __IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */ + __IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */ + __IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */ + __IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */ + __IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */ + __IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */ + __IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */ + __IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */ + __IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */ + __IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */ + __IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */ + __IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */ + __IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */ + uint32_t RESERVED11[0x4]; + __IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */ + __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */ + uint32_t RESERVED12[0xaa]; + __IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */ + __IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */ + uint32_t RESERVED13[0xce]; + __IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */ + +} PL310_TypeDef; + +#define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */ + +extern int PL310_GetID (void); +extern int PL310_GetType (void); +extern void PL310_InvAllByWay (void); +extern void PL310_CleanInvAllByWay(void); +extern void PL310_Enable(void); +extern void PL310_Disable(void); +extern void PL310_InvPa (void *); +extern void PL310_CleanPa (void *); +extern void PL310_CleanInvPa (void *); + +#endif + + diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/r_typedefs.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/r_typedefs.h new file mode 100644 index 0000000000..188c22218d --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/r_typedefs.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright (C) 2012 - 2013 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : r_typedefs.h +* $Rev: 788 $ +* $Date:: 2014-04-07 18:57:13 +0900#$ +* Description : basic type definition +******************************************************************************/ +#ifndef R_TYPEDEFS_H +#define R_TYPEDEFS_H + +/****************************************************************************** +Includes , "Project Includes" +******************************************************************************/ +#include +#include +#include + +#if defined(__ARM_NEON__) + +#include + +#else /* __ARM_NEON__ */ + +typedef float float32_t; +typedef double float64_t; + +#endif /* __ARM_NEON__ */ + +/****************************************************************************** +Typedef definitions +******************************************************************************/ +typedef char char_t; +typedef int bool_t; +typedef int int_t; +typedef long double float128_t; +typedef signed long long_t; +typedef unsigned long ulong_t; + +#endif /* R_TYPEDEFS_H */ + diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c new file mode 100644 index 0000000000..bb6de42aa7 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c @@ -0,0 +1,298 @@ +/**************************************************************************//** + * @file system_Renesas_RZ_A1.c + * @brief CMSIS Device System Source File for + * ARMCA9 Device Series + * @version V1.00 + * @date 19 Sept 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#include +#include "MBRZA1H.h" +#include "RZ_A1_Init.h" + + +extern void $Super$$main(void); +__asm void FPUEnable(void); + +uint32_t IRQNestLevel; + + +/** + * Initialize the cache. + * + * @param none + * @return none + * + * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode. + */ +#pragma push +#pragma arm + +void InitMemorySubsystem(void) { + + /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before + * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. + * You are not required to invalidate the main TLB, even though it is recommended for safety + * reasons. This ensures compatibility with future revisions of the processor. */ + + unsigned int l2_id; + + /* Invalidate undefined data */ + __ca9u_inv_tlb_all(); + __v7_inv_icache_all(); + __v7_inv_dcache_all(); + __v7_inv_btac(); + + /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and + * invalidate in order to flush the valid data to the next level cache. + */ + __enable_mmu(); + + /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ + __enable_caches(); + __enable_btac(); + + /* If present, you may also need to Invalidate and Enable L2 cache here */ + l2_id = PL310_GetID(); + if (l2_id) + { + PL310_InvAllByWay(); + PL310_Enable(); + } +} +#pragma pop + +IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; + +uint32_t IRQCount = sizeof IRQTable / 4; + +uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) +{ + if (irq < IRQCount) { + IRQTable[irq] = handler; + return 0; + } + else { + return 1; + } +} + +uint32_t InterruptHandlerUnregister (IRQn_Type irq) +{ + if (irq < IRQCount) { + IRQTable[irq] = 0; + return 0; + } + else { + return 1; + } +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System. + */ +void SystemInit (void) +{ + IRQNestLevel = 0; +/* do not use global variables because this function is called before + reaching pre-main. RW section maybe overwritten afterwards. */ + RZ_A1_InitClock(); + RZ_A1_InitBus(); + + //Configure GIC ICDICFR GIC_SetICDICFR() + GIC_Enable(); + __enable_irq(); + +} + + +//Fault Status Register (IFSR/DFSR) definitions +#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup +#define FSR_INSTRUCTION_CACHE_MAINTAINANCE 0x04 //DFSR only - async/external +#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external +#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external +#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external +#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external +#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal +#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal +#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal +#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal +#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal +#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal +#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal +#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal +#define FSR_DEBUG_EVENT 0x02 //internal +#define FSR_SYNC_EXT_ABORT 0x08 //sync/external +#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external +#define FSR_LOCKDOWN 0x14 //internal +#define FSR_COPROCESSOR_ABORT 0x1a //internal +#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external +#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external +#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external + +void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { + uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status + + switch(FS) { + //Synchronous parity errors - retry + case FSR_SYNC_PARITY_ERROR: + case FSR_SYNC_PARITY_TTB_WALK_FIRST: + case FSR_SYNC_PARITY_TTB_WALK_SECOND: + return; + + //Your code here. Value in DFAR is invalid for some fault statuses. + case FSR_ALIGNMENT_FAULT: + case FSR_INSTRUCTION_CACHE_MAINTAINANCE: + case FSR_SYNC_EXT_TTB_WALK_FIRST: + case FSR_SYNC_EXT_TTB_WALK_SECOND: + case FSR_TRANSLATION_FAULT_FIRST: + case FSR_TRANSLATION_FAULT_SECOND: + case FSR_ACCESS_FLAG_FAULT_FIRST: + case FSR_ACCESS_FLAG_FAULT_SECOND: + case FSR_DOMAIN_FAULT_FIRST: + case FSR_DOMAIN_FAULT_SECOND: + case FSR_PERMISION_FAULT_FIRST: + case FSR_PERMISION_FAULT_SECOND: + case FSR_DEBUG_EVENT: + case FSR_SYNC_EXT_ABORT: + case FSR_TLB_CONFLICT_ABORT: + case FSR_LOCKDOWN: + case FSR_COPROCESSOR_ABORT: + case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid + case FSR_ASYNC_PARITY_ERROR: //DFAR invalid + default: + while(1); + } +} + +void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { + uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status + + switch(FS) { + //Synchronous parity errors - retry + case FSR_SYNC_PARITY_ERROR: + case FSR_SYNC_PARITY_TTB_WALK_FIRST: + case FSR_SYNC_PARITY_TTB_WALK_SECOND: + return; + + //Your code here. Value in IFAR is invalid for some fault statuses. + case FSR_SYNC_EXT_TTB_WALK_FIRST: + case FSR_SYNC_EXT_TTB_WALK_SECOND: + case FSR_TRANSLATION_FAULT_FIRST: + case FSR_TRANSLATION_FAULT_SECOND: + case FSR_ACCESS_FLAG_FAULT_FIRST: + case FSR_ACCESS_FLAG_FAULT_SECOND: + case FSR_DOMAIN_FAULT_FIRST: + case FSR_DOMAIN_FAULT_SECOND: + case FSR_PERMISION_FAULT_FIRST: + case FSR_PERMISION_FAULT_SECOND: + case FSR_DEBUG_EVENT: //IFAR invalid + case FSR_SYNC_EXT_ABORT: + case FSR_TLB_CONFLICT_ABORT: + case FSR_LOCKDOWN: + case FSR_COPROCESSOR_ABORT: + default: + while(1); + } +} + +//returns amount to decrement lr by +//this will be 0 when we have emulated the instruction and simply want to execute the next instruction +//this will be 2 when we have performed some maintenance and want to retry the instruction in thumb (state == 2) +//this will be 4 when we have performed some maintenance and want to retry the instruction in arm (state == 4) +uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { + const int THUMB = 2; + const int ARM = 4; + //Lazy VFP/NEON initialisation and switching + if ((state == ARM && ((opcode & 0x0C000000)) >> 26 == 0x03) || + (state == THUMB && ((opcode & 0xEC000000)) >> 26 == 0x3B)) { + if (((opcode & 0x00000E00) >> 9) == 5) { //fp instruction? + FPUEnable(); + return state; + } + } + + //Add code here for other Undef cases + while(1); +} + +#pragma push +#pragma arm +//Critical section, called from undef handler, so systick is disabled +__asm void FPUEnable(void) { + ARM + + //Permit access to VFP registers by modifying CPACR + MRC p15,0,R1,c1,c0,2 + ORR R1,R1,#0x00F00000 + MCR p15,0,R1,c1,c0,2 + + //Enable VFP + VMRS R1,FPEXC + ORR R1,R1,#0x40000000 + VMSR FPEXC,R1 + + //Initialise VFP registers to 0 + MOV R2,#0 + VMOV D0, R2,R2 + VMOV D1, R2,R2 + VMOV D2, R2,R2 + VMOV D3, R2,R2 + VMOV D4, R2,R2 + VMOV D5, R2,R2 + VMOV D6, R2,R2 + VMOV D7, R2,R2 + VMOV D8, R2,R2 + VMOV D9, R2,R2 + VMOV D10,R2,R2 + VMOV D11,R2,R2 + VMOV D12,R2,R2 + VMOV D13,R2,R2 + VMOV D14,R2,R2 + VMOV D15,R2,R2 + + //Initialise FPSCR to a known state + VMRS R2,FPSCR + LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + AND R2,R2,R3 + VMSR FPSCR,R2 + + BX LR +} +#pragma pop diff --git a/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h new file mode 100644 index 0000000000..832e58bb91 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.h @@ -0,0 +1,65 @@ +/**************************************************************************//** + * @file system_MBRZA1H.h + * @brief CMSIS Device System Header File for + * ARMCA9 Device Series + * @version V1.00 + * @date 11 June 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __SYSTEM_MBRZA1H +#define __SYSTEM_MBRZA1H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void(*IRQHandler)(); +uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); +uint32_t InterruptHandlerUnregister(IRQn_Type); + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the Systd short int16_t;emCoreClock variable. + */ +extern void SystemInit (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_MBRZA1H */ diff --git a/libraries/mbed/targets/cmsis/core_ca9.h b/libraries/mbed/targets/cmsis/core_ca9.h new file mode 100644 index 0000000000..bae5f6508e --- /dev/null +++ b/libraries/mbed/targets/cmsis/core_ca9.h @@ -0,0 +1,271 @@ +/**************************************************************************//** + * @file core_ca9.h + * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version + * @date 25 March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CA9_H_GENERIC +#define __CORE_CA9_H_GENERIC + + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_A9 + @{ + */ + +/* CMSIS CA9 definitions */ +#define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \ + __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_A (0x09) /*!< Cortex-A Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + #define __STATIC_ASM static __asm + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + #define __STATIC_ASM static __asm + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + #define __STATIC_ASM static __asm + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + #define __STATIC_ASM static __asm + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + #define __STATIC_ASM static __asm + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /*!< standard types definitions */ +#include "core_caInstr.h" /*!< Core Instruction Access */ +#include "core_caFunc.h" /*!< Core Function Access */ +#include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CA9_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA9_H_DEPENDANT +#define __CORE_CA9_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA9_REV + #define __CA9_REV 0x0000 + #warning "__CA9_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 1 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 1 + #endif + + #if __Vendor_SysTickConfig == 0 + #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_A9 */ + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-A processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t reserved1:7; /*!< bit: 20..23 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/*@} end of group CMSIS_CORE */ + +/*@} end of CMSIS_Core_FPUFunctions */ + + +#endif /* __CORE_CA9_H_GENERIC */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} + + +#endif diff --git a/libraries/mbed/targets/cmsis/core_caFunc.h b/libraries/mbed/targets/cmsis/core_caFunc.h new file mode 100644 index 0000000000..237c539b16 --- /dev/null +++ b/libraries/mbed/targets/cmsis/core_caFunc.h @@ -0,0 +1,592 @@ +/**************************************************************************//** + * @file core_caFunc.h + * @brief CMSIS Cortex-A Core Function Access Header File + * @version V3.10 + * @date 9 May 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CAFUNC_H__ +#define __CORE_CAFUNC_H__ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +#define MODE_USR 0x10 +#define MODE_FIQ 0x11 +#define MODE_IRQ 0x12 +#define MODE_SVC 0x13 +#define MODE_MON 0x16 +#define MODE_ABT 0x17 +#define MODE_HYP 0x1A +#define MODE_UND 0x1B +#define MODE_SYS 0x1F + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get CPSR Register + + This function returns the content of the CPSR Register. + + \return CPSR Register value + */ +__STATIC_INLINE uint32_t __get_CPSR(void) +{ + register uint32_t __regCPSR __ASM("cpsr"); + return(__regCPSR); +} + +/** \brief Set Stack Pointer + + This function assigns the given value to the current stack pointer. + + \param [in] topOfStack Stack Pointer value to set + */ +register uint32_t __regSP __ASM("sp"); +__STATIC_INLINE void __set_SP(uint32_t topOfStack) +{ + __regSP = topOfStack; +} + + +/** \brief Get link register + + This function returns the value of the link register + + \return Value of link register + */ +register uint32_t __reglr __ASM("lr"); +__STATIC_INLINE uint32_t __get_LR(void) +{ + return(__reglr); +} + +/** \brief Set link register + + This function sets the value of the link register + + \param [in] lr LR value to set + */ +__STATIC_INLINE void __set_LR(uint32_t lr) +{ + __reglr = lr; +} + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the USR/SYS Stack Pointer (PSP). + + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_ASM void __set_PSP(uint32_t topOfProcStack) +{ + ARM + PRESERVE8 + + BIC R0, R0, #7 ;ensure stack is 8-byte aligned + MRS R1, CPSR + CPS #MODE_SYS ;no effect in USR mode + MOV SP, R0 + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR + +} + +/** \brief Set User Mode + + This function changes the processor state to User Mode + + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_ASM void __set_CPS_USR(void) +{ + ARM + + CPS #MODE_USR + BX LR +} + + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +/** \brief Get FPEXC + + This function returns the current value of the Floating Point Exception Control register. + + \return Floating Point Exception Control register value + */ +__STATIC_INLINE uint32_t __get_FPEXC(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + return(__regfpexc); +#else + return(0); +#endif +} + + +/** \brief Set FPEXC + + This function assigns the given value to the Floating Point Exception Control register. + + \param [in] fpscr Floating Point Exception Control value to set + */ +__STATIC_INLINE void __set_FPEXC(uint32_t fpexc) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpexc __ASM("fpexc"); + __regfpexc = (fpexc); +#endif +} + +/** \brief Get CPACR + + This function returns the current value of the Coprocessor Access Control register. + + \return Coprocessor Access Control register value + */ +__STATIC_INLINE uint32_t __get_CPACR(void) +{ + register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); + return __regCPACR; +} + +/** \brief Set CPACR + + This function assigns the given value to the Coprocessor Access Control register. + + \param [in] cpacr Coporcessor Acccess Control value to set + */ +__STATIC_INLINE void __set_CPACR(uint32_t cpacr) +{ + register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2"); + __regCPACR = cpacr; + __ISB(); +} + +/** \brief Get CBAR + + This function returns the value of the Configuration Base Address register. + + \return Configuration Base Address register value + */ +__STATIC_INLINE uint32_t __get_CBAR() { + register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0"); + return(__regCBAR); +} + +/** \brief Get TTBR0 + + This function returns the value of the Configuration Base Address register. + + \return Translation Table Base Register 0 value + */ +__STATIC_INLINE uint32_t __get_TTBR0() { + register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); + return(__regTTBR0); +} + +/** \brief Set TTBR0 + + This function assigns the given value to the Coprocessor Access Control register. + + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) { + register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0"); + __regTTBR0 = ttbr0; + __ISB(); +} + +/** \brief Get DACR + + This function returns the value of the Domain Access Control Register. + + \return Domain Access Control Register value + */ +__STATIC_INLINE uint32_t __get_DACR() { + register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); + return(__regDACR); +} + +/** \brief Set DACR + + This function assigns the given value to the Coprocessor Access Control register. + + \param [in] dacr Domain Access Control Register value to set + */ +__STATIC_INLINE void __set_DACR(uint32_t dacr) { + register uint32_t __regDACR __ASM("cp15:0:c3:c0:0"); + __regDACR = dacr; + __ISB(); +} + +/******************************** Cache and BTAC enable ****************************************************/ + +/** \brief Set SCTLR + + This function assigns the given value to the System Control Register. + + \param [in] sctlr System Control Register, value to set + */ +__STATIC_INLINE void __set_SCTLR(uint32_t sctlr) +{ + register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); + __regSCTLR = sctlr; +} + +/** \brief Get SCTLR + + This function returns the value of the System Control Register. + + \return System Control Register value + */ +__STATIC_INLINE uint32_t __get_SCTLR() { + register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0"); + return(__regSCTLR); +} + +/** \brief Enable Caches + + Enable Caches + */ +__STATIC_INLINE void __enable_caches(void) { + // Set I bit 12 to enable I Cache + // Set C bit 2 to enable D Cache + __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2)); +} + +/** \brief Disable Caches + + Disable Caches + */ +__STATIC_INLINE void __disable_caches(void) { + // Clear I bit 12 to disable I Cache + // Clear C bit 2 to disable D Cache + __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2)); + __ISB(); +} + +/** \brief Enable BTAC + + Enable BTAC + */ +__STATIC_INLINE void __enable_btac(void) { + // Set Z bit 11 to enable branch prediction + __set_SCTLR( __get_SCTLR() | (1 << 11)); + __ISB(); +} + +/** \brief Disable BTAC + + Disable BTAC + */ +__STATIC_INLINE void __disable_btac(void) { + // Clear Z bit 11 to disable branch prediction + __set_SCTLR( __get_SCTLR() & ~(1 << 11)); +} + + +/** \brief Enable MMU + + Enable MMU + */ +__STATIC_INLINE void __enable_mmu(void) { + // Set M bit 0 to enable the MMU + // Set AFE bit to enable simplified access permissions model + // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking + __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29)); + __ISB(); +} + +/** \brief Enable MMU + + Enable MMU + */ +__STATIC_INLINE void __disable_mmu(void) { + // Clear M bit 0 to disable the MMU + __set_SCTLR( __get_SCTLR() & ~1); + __ISB(); +} + +/******************************** TLB maintenance operations ************************************************/ +/** \brief Invalidate the whole tlb + + TLBIALL. Invalidate the whole tlb + */ + +__STATIC_INLINE void __ca9u_inv_tlb_all(void) { + register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0"); + __TLBIALL = 0; + __DSB(); + __ISB(); +} + +/******************************** BTB maintenance operations ************************************************/ +/** \brief Invalidate entire branch predictor array + + BPIALL. Branch Predictor Invalidate All. + */ + +__STATIC_INLINE void __v7_inv_btac(void) { + register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6"); + __BPIALL = 0; + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new state +} + + +/******************************** L1 cache operations ******************************************************/ + +/** \brief Invalidate the whole I$ + + ICIALLU. Instruction Cache Invalidate All to PoU + */ +__STATIC_INLINE void __v7_inv_icache_all(void) { + register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0"); + __ICIALLU = 0; + __DSB(); //ensure completion of the invalidation + __ISB(); //ensure instruction fetch path sees new I cache state +} + +/** \brief Clean D$ by MVA + + DCCMVAC. Data cache clean by MVA to PoC + */ +__STATIC_INLINE void __v7_clean_dcache_mva(void *va) { + register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1"); + __DCCMVAC = (uint32_t)va; + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Invalidate D$ by MVA + + DCIMVAC. Data cache invalidate by MVA to PoC + */ +__STATIC_INLINE void __v7_inv_dcache_mva(void *va) { + register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1"); + __DCIMVAC = (uint32_t)va; + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief Clean and Invalidate D$ by MVA + + DCCIMVAC. Data cache clean and invalidate by MVA to PoC + */ +__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) { + register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1"); + __DCCIMVAC = (uint32_t)va; + __DMB(); //ensure the ordering of data cache maintenance operations and their effects +} + +/** \brief + * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency. + */ +#pragma push +#pragma arm +__STATIC_ASM void __v7_all_cache(uint32_t op) { + ARM + + PUSH {R4-R11} + + MRC p15, 1, R6, c0, c0, 1 // Read CLIDR + ANDS R3, R6, #0x07000000 // Extract coherency level + MOV R3, R3, LSR #23 // Total cache levels << 1 + BEQ Finished // If 0, no need to clean + + MOV R10, #0 // R10 holds current cache level << 1 +Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position + MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level + AND R1, R1, #7 // Isolate those lower 3 bits + CMP R1, #2 + BLT Skip // No cache or only instruction cache at this level + + MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register + ISB // ISB to sync the change to the CacheSizeID reg + MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register + AND R2, R1, #7 // Extract the line length field + ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes) + LDR R4, =0x3FF + ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned) + CLZ R5, R4 // R5 is the bit position of the way size increment + LDR R7, =0x7FFF + ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned) + +Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned) + +Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11 + ORR R11, R11, R7, LSL R2 // Factor in the Set number + CMP R0, #0 + BNE Dccsw + MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way + B cont +Dccsw CMP R0, #1 + BNE Dccisw + MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way + B cont +Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way +cont SUBS R9, R9, #1 // Decrement the Way number + BGE Loop3 + SUBS R7, R7, #1 // Decrement the Set number + BGE Loop2 +Skip ADD R10, R10, #2 // increment the cache number + CMP R3, R10 + BGT Loop1 + +Finished + DSB + POP {R4-R11} + BX lr + +} +#pragma pop + +/** \brief __v7_all_cache - helper function + + */ + +/** \brief Invalidate the whole D$ + + DCISW. Invalidate by Set/Way + */ + +__STATIC_INLINE void __v7_inv_dcache_all(void) { + __v7_all_cache(0); +} + +/** \brief Clean the whole D$ + + DCCSW. Clean by Set/Way + */ + +__STATIC_INLINE void __v7_clean_dcache_all(void) { + __v7_all_cache(1); +} + +/** \brief Clean and invalidate the whole D$ + + DCCISW. Clean and Invalidate by Set/Way + */ + +__STATIC_INLINE void __v7_clean_inv_dcache_all(void) { + __v7_all_cache(2); +} + +#include "core_ca_mmu.h" + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ + +#error IAR Compiler support not implemented for Cortex-A + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ + +//#error GNU Compiler support not implemented for Cortex-A + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ + +#error TASKING Compiler support not implemented for Cortex-A + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CAFUNC_H__ */ diff --git a/libraries/mbed/targets/cmsis/core_caInstr.h b/libraries/mbed/targets/cmsis/core_caInstr.h new file mode 100644 index 0000000000..b1d3435765 --- /dev/null +++ b/libraries/mbed/targets/cmsis/core_caInstr.h @@ -0,0 +1,45 @@ +/**************************************************************************//** + * @file core_caInstr.h + * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version + * @date 04. December 2012 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2012 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef __CORE_CAINSTR_H__ +#define __CORE_CAINSTR_H__ + +#define __CORTEX_M 0x3 +#include "core_cmInstr.h" +#undef __CORTEX_M + +#endif + diff --git a/libraries/mbed/targets/cmsis/core_ca_mmu.h b/libraries/mbed/targets/cmsis/core_ca_mmu.h new file mode 100644 index 0000000000..1fb99c5e7e --- /dev/null +++ b/libraries/mbed/targets/cmsis/core_ca_mmu.h @@ -0,0 +1,848 @@ +;/**************************************************************************//** +; * @file core_ca_mmu.h +; * @brief MMU Startup File for +; * VE_A9_MP Device Series +; * @version V1.01 +; * @date 25 March 2013 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef _MMU_FUNC_H +#define _MMU_FUNC_H + +#define SECTION_DESCRIPTOR (0x2) +#define SECTION_MASK (0xFFFFFFFC) + +#define SECTION_TEXCB_MASK (0xFFFF8FF3) +#define SECTION_B_SHIFT (2) +#define SECTION_C_SHIFT (3) +#define SECTION_TEX0_SHIFT (12) +#define SECTION_TEX1_SHIFT (13) +#define SECTION_TEX2_SHIFT (14) + +#define SECTION_XN_MASK (0xFFFFFFEF) +#define SECTION_XN_SHIFT (4) + +#define SECTION_DOMAIN_MASK (0xFFFFFE1F) +#define SECTION_DOMAIN_SHIFT (5) + +#define SECTION_P_MASK (0xFFFFFDFF) +#define SECTION_P_SHIFT (9) + +#define SECTION_AP_MASK (0xFFFF73FF) +#define SECTION_AP_SHIFT (10) +#define SECTION_AP2_SHIFT (15) + +#define SECTION_S_MASK (0xFFFEFFFF) +#define SECTION_S_SHIFT (16) + +#define SECTION_NG_MASK (0xFFFDFFFF) +#define SECTION_NG_SHIFT (17) + +#define SECTION_NS_MASK (0xFFF7FFFF) +#define SECTION_NS_SHIFT (19) + + +#define PAGE_L1_DESCRIPTOR (0x1) +#define PAGE_L1_MASK (0xFFFFFFFC) + +#define PAGE_L2_4K_DESC (0x2) +#define PAGE_L2_4K_MASK (0xFFFFFFFD) + +#define PAGE_L2_64K_DESC (0x1) +#define PAGE_L2_64K_MASK (0xFFFFFFFC) + +#define PAGE_4K_TEXCB_MASK (0xFFFFFE33) +#define PAGE_4K_B_SHIFT (2) +#define PAGE_4K_C_SHIFT (3) +#define PAGE_4K_TEX0_SHIFT (6) +#define PAGE_4K_TEX1_SHIFT (7) +#define PAGE_4K_TEX2_SHIFT (8) + +#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_64K_B_SHIFT (2) +#define PAGE_64K_C_SHIFT (3) +#define PAGE_64K_TEX0_SHIFT (12) +#define PAGE_64K_TEX1_SHIFT (13) +#define PAGE_64K_TEX2_SHIFT (14) + +#define PAGE_TEXCB_MASK (0xFFFF8FF3) +#define PAGE_B_SHIFT (2) +#define PAGE_C_SHIFT (3) +#define PAGE_TEX_SHIFT (12) + +#define PAGE_XN_4K_MASK (0xFFFFFFFE) +#define PAGE_XN_4K_SHIFT (0) +#define PAGE_XN_64K_MASK (0xFFFF7FFF) +#define PAGE_XN_64K_SHIFT (15) + + +#define PAGE_DOMAIN_MASK (0xFFFFFE1F) +#define PAGE_DOMAIN_SHIFT (5) + +#define PAGE_P_MASK (0xFFFFFDFF) +#define PAGE_P_SHIFT (9) + +#define PAGE_AP_MASK (0xFFFFFDCF) +#define PAGE_AP_SHIFT (4) +#define PAGE_AP2_SHIFT (9) + +#define PAGE_S_MASK (0xFFFFFBFF) +#define PAGE_S_SHIFT (10) + +#define PAGE_NG_MASK (0xFFFFF7FF) +#define PAGE_NG_SHIFT (11) + +#define PAGE_NS_MASK (0xFFFFFFF7) +#define PAGE_NS_SHIFT (3) + +#define OFFSET_1M (0x00100000) +#define OFFSET_64K (0x00010000) +#define OFFSET_4K (0x00001000) + +#define DESCRIPTOR_FAULT (0x00000000) + +/* ########################### MMU Function Access ########################### */ +/** \ingroup MMU_FunctionInterface + \defgroup MMU_Functions MMU Functions Interface + @{ + */ + +/* Attributes enumerations */ + +/* Region size attributes */ +typedef enum +{ + SECTION, + PAGE_4k, + PAGE_64k, +} mmu_region_size_Type; + +/* Region type attributes */ +typedef enum +{ + NORMAL, + DEVICE, + SHARED_DEVICE, + NON_SHARED_DEVICE, + STRONGLY_ORDERED +} mmu_memory_Type; + +/* Region cacheability attributes */ +typedef enum +{ + NON_CACHEABLE, + WB_WA, + WT, + WB_NO_WA, +} mmu_cacheability_Type; + +/* Region parity check attributes */ +typedef enum +{ + ECC_DISABLED, + ECC_ENABLED, +} mmu_ecc_check_Type; + +/* Region execution attributes */ +typedef enum +{ + EXECUTE, + NON_EXECUTE, +} mmu_execute_Type; + +/* Region global attributes */ +typedef enum +{ + GLOBAL, + NON_GLOBAL, +} mmu_global_Type; + +/* Region shareability attributes */ +typedef enum +{ + NON_SHARED, + SHARED, +} mmu_shared_Type; + +/* Region security attributes */ +typedef enum +{ + SECURE, + NON_SECURE, +} mmu_secure_Type; + +/* Region access attributes */ +typedef enum +{ + NO_ACCESS, + RW, + READ, +} mmu_access_Type; + +/* Memory Region definition */ +typedef struct RegionStruct { + mmu_region_size_Type rg_t; + mmu_memory_Type mem_t; + uint8_t domain; + mmu_cacheability_Type inner_norm_t; + mmu_cacheability_Type outer_norm_t; + mmu_ecc_check_Type e_t; + mmu_execute_Type xn_t; + mmu_global_Type g_t; + mmu_secure_Type sec_t; + mmu_access_Type priv_t; + mmu_access_Type user_t; + mmu_shared_Type sh_t; + +} mmu_region_attributes_Type; + +/** \brief Set section execution-never attribute + + The function sets section execution-never attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE. + + \return 0 + */ +__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn) +{ + *descriptor_l1 &= SECTION_XN_MASK; + *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT); + return 0; +} + +/** \brief Set section domain + + The function sets section domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Section domain + + \return 0 + */ +__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= SECTION_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set section parity check + + The function sets section parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 + */ +__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set section access privileges + + The function sets section access privileges + + \param [out] descriptor_l1 L1 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 + */ +__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l1 &= SECTION_AP_MASK; + *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT; + *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT; + + return 0; +} + +/** \brief Set section shareability + + The function sets section shareability + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section shareability: NON_SHARED, SHARED + + \return 0 + */ +__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit) +{ + *descriptor_l1 &= SECTION_S_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT); + return 0; +} + +/** \brief Set section Global attribute + + The function sets section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL + + \return 0 + */ +__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit) +{ + *descriptor_l1 &= SECTION_NG_MASK; + *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT); + return 0; +} + +/** \brief Set section Security attribute + + The function sets section Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit Section Security attribute: SECURE, NON_SECURE + + \return 0 + */ +__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= SECTION_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT); + return 0; +} + +/* Page 4k or 64k */ +/** \brief Set 4k/64k page execution-never attribute + + The function sets 4k/64k page execution-never attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE. + \param [in] page Page size: PAGE_4k, PAGE_64k, + + \return 0 + */ +__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page) +{ + if (page == PAGE_4k) + { + *descriptor_l2 &= PAGE_XN_4K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT); + } + else + { + *descriptor_l2 &= PAGE_XN_64K_MASK; + *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT); + } + return 0; +} + +/** \brief Set 4k/64k page domain + + The function sets 4k/64k page domain + + \param [out] descriptor_l1 L1 descriptor. + \param [in] domain Page domain + + \return 0 + */ +__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain) +{ + *descriptor_l1 &= PAGE_DOMAIN_MASK; + *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page parity check + + The function sets 4k/64k page parity check + + \param [out] descriptor_l1 L1 descriptor. + \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED + + \return 0 + */ +__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit) +{ + *descriptor_l1 &= SECTION_P_MASK; + *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page access privileges + + The function sets 4k/64k page access privileges + + \param [out] descriptor_l2 L2 descriptor. + \param [in] user User Level Access: NO_ACCESS, RW, READ + \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ + \param [in] afe Access flag enable + + \return 0 + */ +__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe) +{ + uint32_t ap = 0; + + if (afe == 0) { //full access + if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; } + else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == READ)) { ap = 0x2; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x6; } + } + + else { //Simplified access + if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; } + else if ((priv == RW) && (user == RW)) { ap = 0x3; } + else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; } + else if ((priv == READ) && (user == READ)) { ap = 0x7; } + } + + *descriptor_l2 &= PAGE_AP_MASK; + *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT; + *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT; + + return 0; +} + +/** \brief Set 4k/64k page shareability + + The function sets 4k/64k page shareability + + \param [out] descriptor_l2 L2 descriptor. + \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED + + \return 0 + */ +__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit) +{ + *descriptor_l2 &= PAGE_S_MASK; + *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Global attribute + + The function sets 4k/64k page Global attribute + + \param [out] descriptor_l2 L2 descriptor. + \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL + + \return 0 + */ +__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit) +{ + *descriptor_l2 &= PAGE_NG_MASK; + *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT); + return 0; +} + +/** \brief Set 4k/64k page Security attribute + + The function sets 4k/64k page Global attribute + + \param [out] descriptor_l1 L1 descriptor. + \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE + + \return 0 + */ +__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit) +{ + *descriptor_l1 &= PAGE_NS_MASK; + *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT); + return 0; +} + + +/** \brief Set Section memory attributes + + The function sets section memory attributes + + \param [out] descriptor_l1 L1 descriptor. + \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 + */ +__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner) +{ + *descriptor_l1 &= SECTION_TEXCB_MASK; + + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT); + break; + case WT: + *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT); + break; + } + } + + return 0; +} + +/** \brief Set 4k/64k page memory attributes + + The function sets 4k/64k page memory attributes + + \param [out] descriptor_l2 L2 descriptor. + \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED + \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA, + + \return 0 + */ +__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page) +{ + *descriptor_l2 &= PAGE_4K_TEXCB_MASK; + + if (page == PAGE_64k) + { + //same as section + __memory_section(descriptor_l2, mem, outer, inner); + } + else + { + if (STRONGLY_ORDERED == mem) + { + return 0; + } + else if (SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + } + else if (NON_SHARED_DEVICE == mem) + { + *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT); + } + else if (NORMAL == mem) + { + *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT; + switch(inner) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT); + break; + } + switch(outer) + { + case NON_CACHEABLE: + break; + case WB_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT); + break; + case WT: + *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT; + break; + case WB_NO_WA: + *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT); + break; + } + } + } + + return 0; +} + +/** \brief Create a L1 section descriptor + + The function creates a section descriptor. + + Assumptions: + - 16MB super sections not suported + - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor + - Functions always return 0 + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg Section attributes + + \return 0 + */ +__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + + __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t); + __xn_section(descriptor,reg.xn_t); + __domain_section(descriptor, reg.domain); + __p_section(descriptor, reg.e_t); + __ap_section(descriptor, reg.priv_t, reg.user_t, 1); + __shared_section(descriptor,reg.sh_t); + __global_section(descriptor,reg.g_t); + __secure_section(descriptor,reg.sec_t); + *descriptor &= SECTION_MASK; + *descriptor |= SECTION_DESCRIPTOR; + + return 0; + +} + + +/** \brief Create a L1 and L2 4k/64k page descriptor + + The function creates a 4k/64k page descriptor. + Assumptions: + - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor + - Functions always return 0 + + \param [out] descriptor L1 descriptor + \param [out] descriptor2 L2 descriptor + \param [in] reg 4k/64k page attributes + + \return 0 + */ +__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg) +{ + *descriptor = 0; + *descriptor2 = 0; + + switch (reg.rg_t) + { + case PAGE_4k: + __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k); + __xn_page(descriptor2, reg.xn_t, PAGE_4k); + __domain_page(descriptor, reg.domain); + __p_page(descriptor, reg.e_t); + __ap_page(descriptor2, reg.priv_t, reg.user_t, 1); + __shared_page(descriptor2,reg.sh_t); + __global_page(descriptor2,reg.g_t); + __secure_page(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_4K_MASK; + *descriptor2 |= PAGE_L2_4K_DESC; + break; + + case PAGE_64k: + __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k); + __xn_page(descriptor2, reg.xn_t, PAGE_64k); + __domain_page(descriptor, reg.domain); + __p_page(descriptor, reg.e_t); + __ap_page(descriptor2, reg.priv_t, reg.user_t, 1); + __shared_page(descriptor2,reg.sh_t); + __global_page(descriptor2,reg.g_t); + __secure_page(descriptor,reg.sec_t); + *descriptor &= PAGE_L1_MASK; + *descriptor |= PAGE_L1_DESCRIPTOR; + *descriptor2 &= PAGE_L2_64K_MASK; + *descriptor2 |= PAGE_L2_64K_DESC; + break; + + case SECTION: + //error + break; + + } + + return 0; + +} + +/** \brief Create a 1MB Section + + \param [in] ttb Translation table base address + \param [in] base_address Section base address + \param [in] count Number of sections to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + + */ +__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1) +{ + uint32_t offset; + uint32_t entry; + uint32_t i; + + offset = base_address >> 20; + entry = (base_address & 0xFFF00000) | descriptor_l1; + + //4 bytes aligned + ttb = ttb + offset; + + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb++ = entry; + entry += OFFSET_1M; + } +} + +/** \brief Create a 4k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 4k base address + \param [in] count Number of 4k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + + */ +__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFFF000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_4K; + } +} + +/** \brief Create a 64k page entry + + \param [in] ttb L1 table base address + \param [in] base_address 64k base address + \param [in] count Number of 64k pages to create + \param [in] descriptor_l1 L1 descriptor (region attributes) + \param [in] ttb_l2 L2 table base address + \param [in] descriptor_l2 L2 descriptor (region attributes) + + */ +__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 ) +{ + uint32_t offset, offset2; + uint32_t entry, entry2; + uint32_t i,j; + + + offset = base_address >> 20; + entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1; + + //4 bytes aligned + ttb += offset; + //create l1_entry + *ttb = entry; + + offset2 = (base_address & 0xff000) >> 12; + ttb_l2 += offset2; + entry2 = (base_address & 0xFFFF0000) | descriptor_l2; + for (i = 0; i < count; i++ ) + { + //create 16 entries + for (j = 0; j < 16; j++) + //4 bytes aligned + *ttb_l2++ = entry2; + entry2 += OFFSET_64K; + } +} + +/*@} end of MMU_Functions */ +#endif + +#ifdef __cplusplus +} +#endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h new file mode 100644 index 0000000000..a2aed587d6 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PeripheralNames.h @@ -0,0 +1,128 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + UART0, + UART1, + UART2, + UART3, +} UARTName; + +// PWMType & 1 == 1 then have to use PWDTR[12] == 1 +typedef enum { + PWM1A = 0, + PWM1B, + PWM1C, + PWM1D, + PWM1E, + PWM1F, + PWM1G, + PWM1H, + PWM2A = 0x10, + PWM2B, + PWM2C, + PWM2D, + PWM2E, + PWM2F, + PWM2G, + PWM2H, +} PWMType; + +#define PTM_SHIFT 8 +typedef enum { + PWM0_PIN = (1 << PTM_SHIFT) | PWM2E, // LED_R (through MTU2) TIOC4A [T.B.D] + PWM1_PIN = (0 << PTM_SHIFT) | PWM2F, // LED_G + PWM2_PIN = (0 << PTM_SHIFT) | PWM2G, // LED_B + PWM3_PIN = (0 << PTM_SHIFT) | PWM2H, // LED_USER (not explicitly supported) + PWM4_PIN = (0 << PTM_SHIFT) | PWM1G, // D9 + PWM5_PIN = (0 << PTM_SHIFT) | PWM1H, // D8 not explicitly supported + PWM6_PIN = (0 << PTM_SHIFT) | PWM1F, // D7 not explicitly supported + PWM7_PIN = (0 << PTM_SHIFT) | PWM1D, // D6 +} PWMName; + +typedef enum { + AN0= 0, + AN1= 1, + AN2= 2, + AN3= 3, + AN4= 4, + AN5= 5, + AN6= 6, + AN7= 7, +} ADCName; + +typedef enum { + SPI_0 = 0, + SPI_1, +} SPIName; + +typedef enum { + I2C_0 = 0, + I2C_1, + I2C_2, + I2C_3 +} I2CName; + + +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX +#define STDIO_UART P_SCIF2 + +// Default peripherals +#define MBED_SPI0 p5, p6, p7, p8 +#define MBED_SPI1 p11, p12, p13, p14 + +#define MBED_UART0 p9, p10 +#define MBED_UART1 p13, p14 +#define MBED_UART2 p28, p27 +#define MBED_UARTUSB USBTX, USBRX + +#define MBED_I2C0 p28, p27 +#define MBED_I2C1 p9, p10 + +#define MBED_CAN0 p30, p29 + +#define MBED_ANALOGOUT0 p18 + +#define MBED_ANALOGIN0 p15 +#define MBED_ANALOGIN1 p16 +#define MBED_ANALOGIN2 p17 +#define MBED_ANALOGIN3 p18 +#define MBED_ANALOGIN4 p19 +#define MBED_ANALOGIN5 p20 + +#define MBED_PWMOUT0 p26 +#define MBED_PWMOUT1 p25 +#define MBED_PWMOUT2 p24 +#define MBED_PWMOUT3 p23 +#define MBED_PWMOUT4 p22 +#define MBED_PWMOUT5 p21 + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h new file mode 100644 index 0000000000..85ad4da8bb --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PinNames.h @@ -0,0 +1,119 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 4 + +typedef enum { + P0_0 = 0, + P0_1, P0_2, P0_3, P0_4, P0_5,_P0_6,_P0_7,_P0_8,_P0_9,_P0_10,_P0_11,_P0_12,_P0_13,_P0_14,_P0_15, + P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, + P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, + P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, + P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, + P5_0, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10, P5_11, P5_12, P5_13, P5_14, P5_15, + P6_0, P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, P6_8, P6_9, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15, + P7_0, P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, P7_8, P7_9, P7_10, P7_11, P7_12, P7_13, P7_14, P7_15, + P8_0, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, P8_8, P8_9, P8_10, P8_11, P8_12, P8_13, P8_14, P8_15, + P9_0, P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7, P9_8, P9_9, P9_10, P9_11, P9_12, P9_13, P9_14, P9_15, + P10_0,P10_1,P10_2,P10_3,P10_4,P10_5,P10_6,P10_7,P10_8,P10_9,P10_10,P10_11,P10_12,P10_13,P10_14,P10_15, + P11_0,P11_1,P11_2,P11_3,P11_4,P11_5,P11_6,P11_7,P11_8,P11_9,P11_10,P11_11,P11_12,P11_13,P11_14,P11_15, + + // mbed DIP Pin Names + p10 = P0_1, + p21 = P2_5, + p22 = P2_4, + p23 = P2_3, + p24 = P2_2, + p25 = P2_1, + p26 = P2_0, + p29 = P0_5, + p30 = P0_4, + + // Other mbed Pin Names + LED1 = P4_4, + LED2 = P4_5, + LED3 = P4_6, + LED4 = P4_7, + + LED_RED = LED1, + LED_GREEN= LED2, + LED_BLUE = LED3, + LED_USER = LED4, + + USBTX = P6_3, + USBRX = P6_2, + + // Arduiono Pin Names + D0 = P2_15, + D1 = P2_14, + D2 = P11_15, + D3 = P11_14, + D4 = P11_13, + D5 = P11_12, + D6 = P8_11, + D7 = P8_13, + D8 = P8_15, + D9 = P8_14, + D10 = P10_13, + D11 = P10_14, + D12 = P10_15, + D13 = P10_12, + D14 = P1_3, + D15 = P1_2, + + A0 = P1_8, + A1 = P1_9, + A2 = P1_10, + A3 = P1_11, + A4 = P1_13, + A5 = P1_15, + + I2C_SCL = D15, + I2C_SDA = D14, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +typedef enum { + PullUp = 0, + PullDown = 3, + PullNone = 2, + OpenDrain = 4, + PullDefault = PullDown +} PinMode; + +#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f) +#define PINNO(pin) ((pin)&0x0f) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h new file mode 100644 index 0000000000..270cdeecb0 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/PortNames.h @@ -0,0 +1,34 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + Port0 = 0, + Port1 = 1, + Port2 = 2, + Port3 = 3, + Port4 = 4 +} PortName; + +#ifdef __cplusplus +} +#endif +#endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h new file mode 100644 index 0000000000..10d094ce32 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/TARGET_MBED_MBRZA1H/reserved_pins.h @@ -0,0 +1,6 @@ +#ifndef RESERVED_PINS_H +#define RESERVED_PINS_H + +#define TARGET_RESERVED_PINS {} + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c new file mode 100644 index 0000000000..8307996f9f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/analogin_api.c @@ -0,0 +1,117 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "analogin_api.h" + +#include "cmsis.h" +#include "pinmap.h" + +#include "adc_iodefine.h" +#include "cpg_iodefine.h" + +#define ANALOGIN_MEDIAN_FILTER 1 + +#define ADC_12BIT_RANGE 0xFFF + +static const PinMap PinMap_ADC[] = { + {P1_8, AN0, 1}, + {P1_9, AN1, 1}, + {P1_10, AN2, 1}, + {P1_11, AN3, 1}, + {P1_13, AN5, 1}, + {P1_15, AN7, 1}, + {NC, NC, 0} +}; + +static volatile uint16_t *ADCDR[] = { + &ADCADDRA, + &ADCADDRB, + &ADCADDRC, + &ADCADDRD, + &ADCADDRE, + &ADCADDRF, + &ADCADDRG, + &ADCADDRH, +}; + +#define ADC_RANGE ADC_12BIT_RANGE + +void analogin_init(analogin_t *obj, PinName pin) { + obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName)NC); + + CPGSTBCR3 &= ~(1 << 1); + CPGSTBCR6 &= ~(1 << 7); + + // 000_0 000_1 11_00 0_xxx + // 15: ADFlag 14: IntEn 13: start, [12:9] Triger..0 + // [8:6] CLK 100 :: 12-bit 1054tclk + // [5:3] scanmode 000 :: single mode + // [2:0] channel select + ADCADCSR = 0x0100 | (obj->adc&0xf); + + pinmap_pinout(pin, PinMap_ADC); +} + +static inline uint32_t adc_read(analogin_t *obj) { + // Select the appropriate channel and start conversion + ADCADCSR |= (1 << 13 | (obj->adc&0xf)); + + // Repeatedly get the sample data until DONE bit +#define nothing + while ((ADCADCSR & (1 << 15)) == 0 || (ADCADCSR & (1<<13)) != 0) nothing; + + // clear flag + ADCADCSR &= ~(1 << 15); + + return ((*(ADCDR[obj->adc]))>>4) & ADC_RANGE; // 12 bit +} + +static inline void order(uint32_t *a, uint32_t *b) { + if (*a > *b) { + uint32_t t = *a; + *a = *b; + *b = t; + } +} + +static inline uint32_t adc_read_u32(analogin_t *obj) { + uint32_t value; +#if ANALOGIN_MEDIAN_FILTER + uint32_t v1 = adc_read(obj); + uint32_t v2 = adc_read(obj); + uint32_t v3 = adc_read(obj); + order(&v1, &v2); + order(&v2, &v3); + order(&v1, &v2); + value = v2; +#else + value = adc_read(obj); +#endif + return value; +} + +uint16_t analogin_read_u16(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + + return value; + //(value << 4) | ((value >> 8) & 0x000F); // 12 bit +} + +float analogin_read(analogin_t *obj) { + uint32_t value = adc_read_u32(obj); + return (float)value * (1.0f / (float)ADC_RANGE); +} diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h new file mode 100644 index 0000000000..23089470a2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/device.h @@ -0,0 +1,60 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#define DEVICE_PORTIN 1 +#define DEVICE_PORTOUT 1 +#define DEVICE_PORTINOUT 1 + +#define DEVICE_INTERRUPTIN 1 + +#define DEVICE_ANALOGIN 1 +#define DEVICE_ANALOGOUT 0 + +#define DEVICE_SERIAL 1 +#define DEVICE_SERIAL_FC 1 + +#define DEVICE_I2C 1 +#define DEVICE_I2CSLAVE 1 + +#define DEVICE_SPI 1 +#define DEVICE_SPISLAVE 1 + +#define DEVICE_CAN 0 + +#define DEVICE_RTC 0 + +#define DEVICE_ETHERNET 0 + +#define DEVICE_PWMOUT 1 + +#define DEVICE_SEMIHOST 0 +#define DEVICE_LOCALFILESYSTEM 0 +#define DEVICE_ID_LENGTH 32 +#define DEVICE_MAC_OFFSET 20 + +#define DEVICE_SLEEP 0 + +#define DEVICE_DEBUG_AWARENESS 0 + +#define DEVICE_STDIO_MESSAGES 0 + +#define DEVICE_ERROR_PATTERN 0 + +#include "objects.h" + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_addrdefine.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_addrdefine.h new file mode 100644 index 0000000000..3865c03ec2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_addrdefine.h @@ -0,0 +1,22 @@ +#ifndef __GPIO_ADDRDEFINE__ +#define __GPIO_ADDRDEFINE__ + +#define GPIO_BASE ((long)0xFCFE3000uL) /* GPIO */ + +#define PORT(n) (volatile unsigned short *)(GPIO_BASE + 0x000 + ((n)*4)) +#define PSR(n) (volatile unsigned long *)(GPIO_BASE + 0x100 + ((n)*4)) +#define PPR(n) (volatile unsigned short *)(GPIO_BASE + 0x200 + ((n)*4)) +#define PM(n) (volatile unsigned short *)(GPIO_BASE + 0x300 + ((n)*4)) +#define PMC(n) (volatile unsigned short *)(GPIO_BASE + 0x400 + ((n)*4)) +#define PFC(n) (volatile unsigned short *)(GPIO_BASE + 0x500 + ((n)*4)) +#define PFCE(n) (volatile unsigned short *)(GPIO_BASE + 0x600 + ((n)*4)) +#define PNOT(n) (volatile unsigned short *)(GPIO_BASE + 0x700 + ((n)*4)) +#define PMSR(n) (volatile unsigned long *)(GPIO_BASE + 0x800 + ((n)*4)) +#define PMCSR(n) (volatile unsigned long *)(GPIO_BASE + 0x900 + ((n)*4)) +#define PFCAE(n) (volatile unsigned short *)(GPIO_BASE + 0xa00 + ((n)*4)) +#define PIBC(n) (volatile unsigned short *)(GPIO_BASE + 0x4000 +((n)*4)) +#define PBDC(n) (volatile unsigned short *)(GPIO_BASE + 0x4100 +((n)*4)) +#define PIPC(n) (volatile unsigned short *)(GPIO_BASE + 0x4200 +((n)*4)) + +#endif/*__GPIO_ADDRDEFINE__*/ + diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c new file mode 100644 index 0000000000..14831bd688 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_api.c @@ -0,0 +1,53 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "gpio_api.h" +#include "pinmap.h" +#include "gpio_addrdefine.h" + + +uint32_t gpio_set(PinName pin) { + pin_function(pin, 0); + return (1 << PINNO(pin)); +} + +void gpio_init(gpio_t *obj, PinName pin) { + int group ; + if(pin == NC) return; + + obj->pin = pin; + obj->mask = gpio_set(pin); + + group = PINGROUP(pin); + if (group > 11) return; + + obj->reg_set = (volatile uint32_t *)PORT(group); + obj->reg_in = (volatile uint32_t *) PPR(group); + obj->reg_dir = (volatile uint32_t *) PM(group); + obj->reg_buf = (volatile uint32_t *)PIBC(group); +} + +void gpio_mode(gpio_t *obj, PinMode mode) { +// pullup, pulldown, open...etc +} + +void gpio_dir(gpio_t *obj, PinDirection direction) { + switch (direction) { + case PIN_INPUT : *obj->reg_dir |= obj->mask; + *obj->reg_buf |= obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir &= ~obj->mask; + *obj->reg_buf &= ~obj->mask; break; + } +} diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h new file mode 100644 index 0000000000..6eb8d80402 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/gpio_object.h @@ -0,0 +1,48 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + + __IO uint32_t *reg_dir; + __IO uint32_t *reg_set; + __I uint32_t *reg_in; + __IO uint32_t *reg_buf; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) { + if (value) + *obj->reg_set |= obj->mask; + else + *obj->reg_set &= ~obj->mask; +} + +static inline int gpio_read(gpio_t *obj) { + return ((*obj->reg_in & obj->mask) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c new file mode 100644 index 0000000000..0ec6bc68e2 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/i2c_api.c @@ -0,0 +1,357 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "i2c_api.h" +#include "cmsis.h" +#include "pinmap.h" + + +#include "riic_iodefine.h" + +volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; + +#define REG(N) \ + RIIC[obj->i2c]->RIICn##N + +#define NACKF (1 << 4) + +static const PinMap PinMap_I2C_SDA[] = { + {P1_1 , I2C_0, 1}, + {P1_3 , I2C_1, 1}, + {P1_7 , I2C_3, 1}, + {NC , NC , 0} +}; + +static const PinMap PinMap_I2C_SCL[] = { + {P1_0 , I2C_0, 1}, + {P1_2 , I2C_1, 1}, + {P1_6 , I2C_3, 1}, + {NC , NC, 0} +}; + +// Clear the Transmit data Empty TDRE +static inline int i2c_addressed(i2c_t *obj) { + volatile int sar0 = (REG(SR1.UINT8[0])&1), + trs = (REG(CR2.UINT8[0])&0x20) >> 5; + return sar0 | (trs <<1); +} + +static inline int i2c_status(i2c_t *obj) { + return REG(SR2.UINT8[0]); +} + +static inline void i2c_clear_TDRE(i2c_t *obj) { + REG(SR2.UINT32) &= ~(1 << 7); +} + +static inline void i2c_wait_RDRF(i2c_t *obj) { + while (!(i2c_status(obj) & (1 << 5))) ; +} + +// Wait until the Trans Data Empty (TDRE) is set +static int i2c_wait_TDRE(i2c_t *obj) { + int timeout = 0; + + while (!(i2c_status(obj) & (1 << 7))) { + if (timeout > 100000) return -1; + } + + return 0; +} + +static inline void i2c_power_enable(i2c_t *obj) { + volatile uint8_t dummy; + switch ((int)obj->i2c) { + case I2C_0: CPGSTBCR9 &= ~(0x80); break; + case I2C_1: CPGSTBCR9 &= ~(0x40); break; + case I2C_2: CPGSTBCR9 &= ~(0x20); break; + case I2C_3: CPGSTBCR9 &= ~(0x10); break; + } + dummy = CPGSTBCR9; +} + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + // determine the SPI to use + I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); + I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c = pinmap_merge(i2c_sda, i2c_scl); + obj->dummy = 1; + MBED_ASSERT((int)obj->i2c != NC); + + // enable power + i2c_power_enable(obj); + + // full reset + REG(CR1.UINT8[0]) &= ~(1 << 7); // CR1.ICE off + REG(CR1.UINT8[0]) |= (1 << 6); // CR1.IICRST on + REG(CR1.UINT8[0]) |= (1 << 7); // CR1.ICE on + + REG(MR1.UINT8[0]) = 0x08; // P_phi /8 9bit (including Ack) + REG(SER.UINT8[0]) = 0x00; // no slave addr enabled + + // set default frequency at 100k + i2c_frequency(obj, 100000); + + REG(MR2.UINT8[0]) = 0x07; + REG(MR3.UINT8[0]) = 0x00; + + REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT + REG(IER.UINT8[0]) = 0x00; // no interrupt + + REG(CR1.UINT32) &= ~(1 << 6); // CR1.IICRST negate reset + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); +} + +inline int i2c_start(i2c_t *obj) { + if (REG(CR2.UINT32) & (1 << 7)) { // BBSY check + return 0xff; + } + REG(CR2.UINT8[0]) |= 0x62; // start + + return 0x10; +} + +inline int i2c_stop(i2c_t *obj) { + int timeout = 0; + + // write the stop bit + REG(CR2.UINT32) |= (1 << 3); + + // wait for SP bit to reset + while(REG(CR2.UINT32) & (1 << 3)) { + timeout ++; + if (timeout > 100000) return 1; + } + + obj->dummy = 1; + REG(CR2.UINT32) &= ~ (1 << 3); + return 0; +} + +static inline int i2c_do_write(i2c_t *obj, int value) { + // write the data + if (!(i2c_status(obj) & NACKF)) { // NACF=0 + i2c_wait_TDRE(obj); + REG(DRT.UINT32) = value; + } else { + return 0xff; + } + return i2c_status(obj); +} + +static inline int i2c_do_read(i2c_t *obj, int last) { + if (obj->dummy) { + volatile int dummy = REG(DRR.UINT32); + obj->dummy = 0; + } + if (last) { + // send a NOT ACK + REG(MR2.UINT32) |= (1 <<6); + } else { + // send a ACK + REG(MR2.UINT32) &= ~(1 <<6); + } + // wait for it to arrive + i2c_wait_RDRF(obj); + + // return the data + return (REG(DRR.UINT32) & 0xFF); +} + +void i2c_frequency(i2c_t *obj, int hz) { + uint32_t PCLK = 6666666; + + uint32_t pulse = PCLK / (hz * 2); + + // I2C Rate + REG(BRL.UINT32) = pulse; + REG(BRH.UINT32) = pulse; +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { + int count, status; + + status = i2c_start(obj); + + if (status == 0xff) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + status = i2c_do_write(obj, (address | 0x01)); + if (status & 0x01) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Read in all except last byte + for (count = 0; count < (length - 1); count++) { + int value = i2c_do_read(obj, 0); + status = i2c_status(obj); + if (status & 0x10) { + i2c_stop(obj); + return count; + } + data[count] = (char) value; + } + + // read in last byte + int value = i2c_do_read(obj, 1); + status = i2c_status(obj); + if (status & 0x10) { + i2c_stop(obj); + return length - 1; + } + + data[count] = (char) value; + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { + int i, status; + + status = i2c_start(obj); + + if ((status == 0xff)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + status = i2c_do_write(obj, address); + if (status & 0x10) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + for (i=0; idummy) { + volatile int dummy = REG(DRR.UINT32) ; + obj->dummy = 0; + } + + do { + i2c_wait_RDRF(obj); + status = i2c_status(obj); + if(!(status & 0x10)) { + data[count] = REG(DRR.UINT32) & 0xFF; + } + count++; + } while ( !(status & 0x10) && (count < length) ); + + if(status & 0x10) { + i2c_stop(obj); + } + + //i2c_clear_TDRE(obj); + + return count; +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) { + int count = 0; + int status; + + if(length <= 0) { + return(0); + } + + do { + status = i2c_do_write(obj, data[count]); + count++; + } while ((count < length) && !(status & 0x10)); + + if (!(status & 0x10)) { + i2c_stop(obj); + } + + i2c_clear_TDRE(obj); + + return(count); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { + REG(SAR0.UINT32) = address & 0xfe; +} diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h new file mode 100644 index 0000000000..db8ed0d8d3 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/objects.h @@ -0,0 +1,73 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "gpio_object.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct i2c_s { + uint32_t i2c; + uint32_t dummy; +}; + +struct spi_s { + uint32_t spi; +}; + +struct gpio_irq_s { + uint32_t port; + uint32_t pin; + uint32_t ch; +}; + +struct port_s { + __IO uint32_t *reg_dir; + __IO uint32_t *reg_out; + __I uint32_t *reg_in; + PortName port; + uint32_t mask; +}; + +struct serial_s { + struct st_scif *uart; + int index; +}; + +struct pwmout_s { + __IO uint16_t *MR; + __IO uint16_t *CY; + uint16_t flag; + PWMName pwm; +}; + +struct analogin_s { + ADCName adc; +}; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c new file mode 100644 index 0000000000..4480b83a73 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pinmap.c @@ -0,0 +1,47 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "pinmap.h" +#include "mbed_error.h" +#include "gpio_addrdefine.h" + +void pin_function(PinName pin, int function) { + if (pin == (PinName)NC) return; + + int n = pin >> 4; + int bitmask = 1<<(pin & 0xf); + + if (function == 0) { + // means GPIO mode + *PMC(n) &= ~bitmask; + } else { + // alt-function mode + *PMC(n) |= bitmask; + --function; + + if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;} + if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;} + if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;} + *PIPC(n) |= bitmask; + + if (P1_0 <= pin && pin <= P1_7 && function == 0) { + *PBDC(n) |= bitmask; + } + } +} + +void pin_mode(PinName pin, PinMode mode) { +// if (pin == (PinName)NC) { return; } +} diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/port_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/port_api.c new file mode 100644 index 0000000000..5f9f16e4d5 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/port_api.c @@ -0,0 +1,65 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "port_api.h" +#include "pinmap.h" +#include "gpio_api.h" + +PinName port_pin(PortName port, int pin_n) { + return (PinName)(0); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { + obj->port = port; + obj->mask = mask; + + // Do not use masking, because it prevents the use of the unmasked pins + // port_reg->FIOMASK = ~mask; + + uint32_t i; + // The function is set per pin: reuse gpio logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i)); + } + } + + port_dir(obj, dir); +} + +void port_mode(port_t *obj, PinMode mode) { + uint32_t i; + // The mode is set per pin: reuse pinmap logic + for (i=0; i<32; i++) { + if (obj->mask & (1<port, i), mode); + } + } +} + +void port_dir(port_t *obj, PinDirection dir) { + switch (dir) { + case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break; + case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break; + } +} + +void port_write(port_t *obj, int value) { + *obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask); +} + +int port_read(port_t *obj) { + return (*obj->reg_in & obj->mask); +} diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c new file mode 100644 index 0000000000..e1fe139962 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c @@ -0,0 +1,174 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include "pwmout_api.h" +#include "cmsis.h" +#include "pinmap.h" + +#include "cpg_iodefine.h" +#include "pwm_iodefine.h" + +#define TCR_CNT_EN 0x00000001 +#define TCR_RESET 0x00000002 + +// PORT ID, PWM ID, Pin function +static const PinMap PinMap_PWM[] = { + {LED_RED , 0, 4}, + {LED_GREEN, 1, 4}, + {LED_BLUE , 2, 4}, + {P4_7 , 3, 4}, + {P8_14 , 4, 6}, + {P8_15 , 5, 6}, + {P8_13 , 6, 6}, + {P8_11 , 7, 6}, + {NC, NC, 0} +}; + +static __IO uint16_t PORT[] = { + PWM2E, + PWM2F, + PWM2G, + PWM2H, + PWM1G, + PWM1H, + PWM1F, + PWM1D, +}; +static __IO uint16_t *PWM_MATCH[] = { + &PWMPWBFR_2E, + &PWMPWBFR_2E, + &PWMPWBFR_2G, + &PWMPWBFR_2G, + &PWMPWBFR_1G, + &PWMPWBFR_1G, + &PWMPWBFR_1E, + &PWMPWBFR_1C, +}; + +#define TCR_PWM_EN 0x00000008 + +static unsigned int pwm_clock_mhz; + +void pwmout_init(pwmout_t* obj, PinName pin) { + // determine the channel + PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT(pwm != (PWMName)NC); + + obj->pwm = pwm; + obj->MR = PWM_MATCH[pwm]; + obj->flag = (PORT[pwm]&1)<<12; + + // power on + CPGSTBCR3 &= ~(1<<0); + + // clk mode settings PWM mode + PWMPWCR_1_BYTE_L = 0xc4; + PWMPWCR_2_BYTE_L = 0xc4; + + // output settings + PWMPWPR_1_BYTE_L = 0x00; + PWMPWPR_2_BYTE_L = 0x00; + + // cycle reg. + PWMPWCYR_1 = 0x3ff; + PWMPWCYR_2 = 0x3ff; + + //pwm_clock_mhz = SystemCoreClock / 4000000; + + PWMPWCR_1_BYTE_L = 0xcc; + PWMPWCR_2_BYTE_L = 0xcc; + // default to 20ms: standard for servos, and fine for e.g. brightness control + //pwmout_period_ms(obj, 20); + //pwmout_write (obj, 0); + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); + +} + +void pwmout_free(pwmout_t* obj) { + // [TODO] +} + +void pwmout_write(pwmout_t* obj, float value) { + if (value < 0.0f) { + value = 0.0; + } else if (value > 1.0f) { + value = 1.0; + } + + // set channel match to percentage + uint16_t v = (uint32_t)((float)0x3ff* value); + + v |= (obj->flag); + + // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout + *obj->MR = v; + + // accept on next period start + //LPC_PWM1->LER |= 1 << obj->pwm; +} + +float pwmout_read(pwmout_t* obj) { + float v = (float)((*obj->MR&0x3ff)) / 0x3ff; + return (v > 1.0f) ? (1.0f) : (v); +} + +void pwmout_period(pwmout_t* obj, float seconds) { + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) { + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) { + // calculate number of ticks + uint16_t ticks = 0x3ff * us; + + // stop timer + *obj->MR = ticks; + + // Scale the pulse width to preserve the duty ratio + + // set the channel latch to update value at next period start +// LPC_PWM1->LER |= 1 << 0; + + // enable counter and pwm, clear reset + // LPC_PWM1->TCR = TCR_CNT_EN | TCR_PWM_EN; +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) { + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) { + // calculate number of ticks + uint32_t v = pwm_clock_mhz * us; + + // workaround for PWM1[1] - Never make it equal MR0, else we get 1 cycle dropout + + // set the match register value + *obj->MR = v; + + // set the channel latch to update value at next period start + //LPC_PWM1->LER |= 1 << obj->pwm; +} diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c new file mode 100644 index 0000000000..d738af2c41 --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c @@ -0,0 +1,357 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +// math.h required for floating point operations for baud rate calculation +#include "mbed_assert.h" +#include +#include +#include + +#include "serial_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "gpio_api.h" + +#include "scif_iodefine.h" +typedef struct st_scif SCIF_TypeDef; +#include "cpg_iodefine.h" + +/****************************************************************************** + * INITIALIZATION + ******************************************************************************/ +#define UART_NUM 6 + +static const PinMap PinMap_UART_TX[] = { + {P6_3 , P_SCIF2, 7}, + {P2_14, P_SCIF0, 6}, + {P5_0 , P_SCIF4, 5}, + {P5_3 , P_SCIF3, 5}, + {P5_6 , P_SCIF6, 5}, + {P2_5 , P_SCIF1, 6}, + {P8_14, P_SCIF4, 7}, + {P8_13, P_SCIF5, 5}, + {P7_5 , P_SCIF7, 4}, + {NC , NC , 0} +}; + +static const PinMap PinMap_UART_RX[] = { + {P6_2 , P_SCIF2, 7}, + {P2_15, P_SCIF0, 6}, + {P5_1 , P_SCIF4, 5}, + {P5_4 , P_SCIF3, 5}, + {P5_7 , P_SCIF6, 5}, + {P2_6 , P_SCIF1, 6}, + {P8_15, P_SCIF4, 7}, + {P8_11, P_SCIF5, 5}, + {P7_4 , P_SCIF7, 4}, + {NC , NC , 0} +}; + +/* [TODO] impliment hardware Flow Control, interrupt +static const PinMap PinMap_UART_RTS[] = { + {P7_7, (int)P_SCIF7, 4}, + {P2_7 , (int)P_SCIF1, 6}, + {NC, NC, 0} +}; + +static const PinMap PinMap_UART_CTS[] = { + {P7_6, (int)P_SCIF7, 4}, + {P2_3, (int)P_SCIF1, 6}, + {NC, NC, 0} +};*/ + +static uart_irq_handler irq_handler; + +int stdio_uart_inited = 0; +serial_t stdio_uart; + +struct serial_global_data_s { + uint32_t serial_irq_id; + gpio_t sw_rts, sw_cts; + uint8_t count, rx_irq_set_flow, rx_irq_set_api; +}; + +static struct serial_global_data_s uart_data[UART_NUM]; + +void serial_init(serial_t *obj, PinName tx, PinName rx) { + int is_stdio_uart = 0; + + // determine the UART to use + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + uint32_t uart = pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)uart != NC); + + obj->uart = (SCIF_TypeDef *)uart; + // enable power + switch (uart) { + case P_SCIF0: CPG.STBCR4 &= ~(1 << 7); break; + case P_SCIF1: CPG.STBCR4 &= ~(1 << 6); break; + case P_SCIF2: CPG.STBCR4 &= ~(1 << 5); break; + case P_SCIF3: CPG.STBCR4 &= ~(1 << 4); break; + case P_SCIF4: CPG.STBCR4 &= ~(1 << 3); break; + case P_SCIF5: CPG.STBCR4 &= ~(1 << 2); break; + case P_SCIF6: CPG.STBCR4 &= ~(1 << 1); break; + case P_SCIF7: CPG.STBCR4 &= ~(1 << 0); break; + } + volatile uint8_t dummy ; + dummy = CPG.STBCR4; + + /* ==== SCIF initial setting ==== */ + /* ---- Serial control register (SCSCR) setting ---- */ + /* B'00 : Internal CLK */ + obj->uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */ + + /* ---- FIFO control register (SCFCR) setting ---- */ + /* Transmit FIFO reset & Receive FIFO data register reset */ + obj->uart->SCFCR = 0x0006; + + /* ---- Serial status register (SCFSR) setting ---- */ + obj->uart->SCFSR &= 0xFF6Cu; /* ER,BRK,DR bit clear */ + + /* ---- Line status register (SCLSR) setting ---- */ + /* ORER bit clear */ + obj->uart->SCLSR = 0; + + /* ---- Serial extension mode register (SCEMR) setting ---- + b7 BGDM - Baud rate generator double-speed mode : Normal mode + b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */ + obj->uart->SCEMR = 0x0000u; + + /* ---- Bit rate register (SCBRR) setting ---- */ + serial_baud (obj, 9600); + serial_format(obj, 8, ParityNone, 1); + + /* ---- FIFO control register (SCFCR) setting ---- */ + obj->uart->SCFCR = 0x0030u; + + /* ---- Serial port register (SCSPTR) setting ---- + b1 SPB2IO - Serial port break output : disabled + b0 SPB2DT - Serial port break data : High-level */ + //obj->uart->SCSPTR |= 0x0000u; + + obj->uart->SCSCR = 0x0030; + + // pinout the chosen uart + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + switch (uart) { + case P_SCIF0: obj->index = 0; break; + case P_SCIF1: obj->index = 1; break; + case P_SCIF2: obj->index = 2; break; + case P_SCIF3: obj->index = 3; break; + case P_SCIF4: obj->index = 4; break; + case P_SCIF5: obj->index = 5; break; + case P_SCIF6: obj->index = 6; break; + } + uart_data[obj->index].sw_rts.pin = NC; + uart_data[obj->index].sw_cts.pin = NC; + serial_set_flow_control(obj, FlowControlNone, NC, NC); + + is_stdio_uart = (uart == STDIO_UART) ? (1) : (0); + + if (is_stdio_uart) { + stdio_uart_inited = 1; + memcpy(&stdio_uart, obj, sizeof(serial_t)); + } +} + +void serial_free(serial_t *obj) { + uart_data[obj->index].serial_irq_id = 0; +} + +// serial_baud +// set the baud rate, taking in to account the current SystemFrequency +void serial_baud(serial_t *obj, int baudrate) { + + uint32_t PCLK = 66666666; + + uint16_t DL = (PCLK / (32 * baudrate)) -1; + + // set LCR[DLAB] to enable writing to divider registers + obj->uart->SCBRR = DL; +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits + MBED_ASSERT((data_bits > 6) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || + (parity == ParityForced1) || (parity == ParityForced0)); + + stop_bits = (stop_bits == 1)? 0: + (stop_bits == 2)? 1: + 0; // must not to be + + data_bits = (data_bits == 8)? 0: + (data_bits == 7)? 1: + 0; // must not to be + + int parity_enable, parity_select; + switch (parity) { + case ParityNone: parity_enable = 0; parity_select = 0; break; + case ParityOdd : parity_enable = 1; parity_select = 0; break; + case ParityEven: parity_enable = 1; parity_select = 1; break; + default: + parity_enable = 0, parity_select = 0; + break; + } + + obj->uart->SCSMR = data_bits << 6 + | parity_enable << 5 + | parity_select << 4 + | stop_bits << 3; +} + +/****************************************************************************** + * INTERRUPTS HANDLING + ******************************************************************************/ + +void uart0_irq() {irq_handler(0, RxIrq);//dummy call + } +void uart1_irq() {/*uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_UART_TypeDef*)LPC_UART1);*/} +void uart2_irq() {/*uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2, (LPC_UART_TypeDef*)LPC_UART2);*/} +void uart3_irq() {/*uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3, (LPC_UART_TypeDef*)LPC_UART3);*/} + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { + irq_handler = handler; + uart_data[obj->index].serial_irq_id = id; +} + +static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { +/* IRQn_Type irq_n = (IRQn_Type)0; + uint32_t vector = 0; + switch ((int)obj->uart) { + case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; + case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; + case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; + case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break; + } + + if (enable) { + obj->uart->IER |= 1 << irq; + //NVIC_SetVector(irq_n, vector); + //NVIC_EnableIRQ(irq_n); + } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable + int all_disabled = 0; + SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); + obj->uart->IER &= ~(1 << irq); + all_disabled = (obj->uart->IER & (1 << other_irq)) == 0; + if (all_disabled) ; + //NVIC_DisableIRQ(irq_n); + }*/ +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + if (RxIrq == irq) + uart_data[obj->index].rx_irq_set_api = enable; + serial_irq_set_internal(obj, irq, enable); +} + +static void serial_flow_irq_set(serial_t *obj, uint32_t enable) { + uart_data[obj->index].rx_irq_set_flow = enable; + serial_irq_set_internal(obj, RxIrq, enable); +} + +/****************************************************************************** + * READ/WRITE + ******************************************************************************/ +int serial_getc(serial_t *obj) { + if (obj->uart->SCFSR & 0x93) { obj->uart->SCFSR = ~0x93;} + while (!serial_readable(obj)); + int data = obj->uart->SCFRDR & 0xff; + /* Clear DR,RDF */ + obj->uart->SCFSR &= 0xfffc; + return data; +} + +void serial_putc(serial_t *obj, int c) { + while (!serial_writable(obj)); + obj->uart->SCFTDR = c; + obj->uart->SCFSR &= 0xff9f; // Clear TEND/TDFE + uart_data[obj->index].count++; +} + +int serial_readable(serial_t *obj) { + return obj->uart->SCFSR & 0x02; // RDF +} + +int serial_writable(serial_t *obj) { + return obj->uart->SCFSR & 0x20; // TDFE +} + +void serial_clear(serial_t *obj) { + obj->uart->SCFCR = 0x06; + obj->uart->SCFCR = 0x06; +} + +void serial_pinout_tx(PinName tx) { + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) { + //obj->uart->LCR |= (1 << 6); +} + +void serial_break_clear(serial_t *obj) { + //obj->uart->LCR &= ~(1 << 6); +} + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { + serial_flow_irq_set(obj, 0); + // Only UART1 has hardware flow control on LPC176x + /*LPC_UART1_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)LPC_UART1 ? LPC_UART1 : NULL; + int index = obj->index; + + // First, disable flow control completely + if (uart1) + uart1->MCR = uart1->MCR & ~UART_MCR_FLOWCTRL_MASK; + uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC; + serial_flow_irq_set(obj, 0); + if (FlowControlNone == type) + return; + // Check type(s) of flow control to use + UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS); + UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS); + if (((FlowControlCTS == type) || (FlowControlRTSCTS == type)) && (NC != txflow)) { + // Can this be enabled in hardware? + if ((UART_1 == uart_cts) && (NULL != uart1)) { + // Enable auto-CTS mode + uart1->MCR |= UART_MCR_CTSEN_MASK; + pinmap_pinout(txflow, PinMap_UART_CTS); + } else { + // Can't enable in hardware, use software emulation + gpio_init_in(&uart_data[index].sw_cts, txflow); + } + } + if (((FlowControlRTS == type) || (FlowControlRTSCTS == type)) && (NC != rxflow)) { + // Enable FIFOs, trigger level of 1 char on RX FIFO + obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled + | 1 << 1 // Rx Fifo Reset + | 1 << 2 // Tx Fifo Reset + | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars + // Can this be enabled in hardware? + if ((UART_1 == uart_rts) && (NULL != uart1)) { + // Enable auto-RTS mode + uart1->MCR |= UART_MCR_RTSEN_MASK; + pinmap_pinout(rxflow, PinMap_UART_RTS); + } else { // can't enable in hardware, use software emulation + gpio_init_out_ex(&uart_data[index].sw_rts, rxflow, 0); + // Enable RX interrupt + serial_flow_irq_set(obj, 1); + } + }*/ +} + diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c new file mode 100644 index 0000000000..4aaafc1b7f --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c @@ -0,0 +1,234 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "mbed_assert.h" +#include + +#include "spi_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "mbed_error.h" + + +#include "rspi_iodefine.h" + +static const PinMap PinMap_SPI_SCLK[] = { + {P10_12, SPI_0, 4}, + {P11_12, SPI_1, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_SSEL[] = { + {P10_13, SPI_0, 4}, + {P11_13, SPI_1, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MOSI[] = { + {P10_14, SPI_0, 4}, + {P11_14, SPI_1, 2}, + {NC , NC , 0} +}; + +static const PinMap PinMap_SPI_MISO[] = { + {P10_15, SPI_0, 4}, + {P11_15, SPI_1, 2}, + {NC , NC , 0} +}; + +struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST; + +static inline void spi_disable(spi_t *obj); +static inline void spi_enable(spi_t *obj); +static inline int spi_readable(spi_t *obj); +static inline void spi_write(spi_t *obj, int value); +static inline int spi_writable(spi_t *obj); +static inline int spi_read(spi_t *obj); + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { + // determine the SPI to use + SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); + SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); + SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); + SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); + //SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); + //SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); + obj->spi = spi_mosi; //pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi != NC); + + // enable power and clocking + volatile uint8_t dummy; + switch ((int)obj->spi) { + case SPI_0: CPGSTBCR10 &= ~(0x80); break; + case SPI_1: CPGSTBCR10 &= ~(0x40); break; + } + dummy = CPGSTBCR10; + + RSPI[obj->spi]->SPCR = 0x00; // CTRL to 0 + RSPI[obj->spi]->SPSCR = 0x00; // no sequential operation + RSPI[obj->spi]->SSLP = 0x00; // SSL 'L' active + RSPI[obj->spi]->SPDCR = 0x20; // byte access + RSPI[obj->spi]->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK + RSPI[obj->spi]->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK + RSPI[obj->spi]->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK + RSPI[obj->spi]->SPPCR = 0x20; // + + RSPI[obj->spi]->SPBFCR= 0xf0; // and set trigger count: read 1, write 1 + RSPI[obj->spi]->SPBFCR= 0x30; // and reset buffer + + // set default format and frequency + if (ssel == NC) { + spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master + } else { + spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave + } + spi_frequency(obj, 1000000); + + // enable the ssp channel + spi_enable(obj); + + // pin out the spi pins + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + if (ssel != NC) { + pinmap_pinout(ssel, PinMap_SPI_SSEL); + } +} + +void spi_free(spi_t *obj) {} + +void spi_format(spi_t *obj, int bits, int mode, int slave) { + spi_disable(obj); + MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3)); + + int polarity = (mode & 0x2) ? 1 : 0; + int phase = (mode & 0x1) ? 1 : 0; + uint16_t tmp = 0, mask = 0xf03; + + tmp |= phase; + tmp |= polarity << 1; + + int DSS; // DSS (data select size) + switch (bits) { + case 8: + DSS = 0x7; break; + case 16: + DSS = 0xf; break; + case 32: + DSS = 0x2; break; + default: + error("SPI module don't support other than 8/16/32bits"); + return ; + } + tmp |= (DSS << 8); + + // set it up + RSPI[obj->spi]->SPCMD0 &= ~mask; + RSPI[obj->spi]->SPCMD0 |= (mask & tmp); + + if (slave) { + RSPI[obj->spi]->SPCR &=~(1 << 3); + } else { + RSPI[obj->spi]->SPCR |= (1 << 3); + } + + spi_enable(obj); +} + +void spi_frequency(spi_t *obj, int hz) { + spi_disable(obj); + const int P1CLK = 66666666; // 66.6666MHz + uint8_t div, brdv; + uint16_t mask = 0x000c0; + + if (hz <= P1CLK/2 && hz >= P1CLK/255) { + div = (P1CLK / hz / 2) -1; + brdv = 0x0 << 2; + } else if (hz >= P1CLK/255/2) { + div = (P1CLK / hz / 2 /2) -1; + brdv = 0x1 << 2; + } else if (hz >= P1CLK/255/4) { + div = (P1CLK / hz / 2 /4) -1; + brdv = 0x2 << 2; + } else if (hz >= P1CLK/255/8) { + div = (P1CLK / hz / 2 /8) -1; + brdv = 0x3 << 2; + } else { + error("Couldn't setup requested SPI frequency"); + return; + } + + RSPI[obj->spi]->SPBR = div; + + RSPI[obj->spi]->SPCMD0 &= ~mask; + RSPI[obj->spi]->SPCMD0 |= (mask & brdv); + + + spi_enable(obj); +} + +static inline void spi_disable(spi_t *obj) { + RSPI[obj->spi]->SPCR &= ~(1 << 6); // SPE to 0 +} + +static inline void spi_enable(spi_t *obj) { + RSPI[obj->spi]->SPCR |= (1 << 6); // SPE to 1 +} + +static inline int spi_readable(spi_t *obj) { + return RSPI[obj->spi]->SPSR & (1 << 7); +} + +static inline int spi_tend(spi_t *obj) { + return RSPI[obj->spi]->SPSR & (1 << 6); +} + +static inline int spi_writable(spi_t *obj) { + return RSPI[obj->spi]->SPSR & (1 << 5); +} + +static inline void spi_write(spi_t *obj, int value) { + while (!spi_writable(obj)); + RSPI[obj->spi]->SPDR.UINT8[0] = value; +} + +static inline int spi_read(spi_t *obj) { + //while (!spi_readable(obj)); + return RSPI[obj->spi]->SPDR.UINT8[0]; +} + +int spi_master_write(spi_t *obj, int value) { + spi_write(obj, value); + while(!spi_tend(obj)); + return spi_read(obj); +} + +int spi_slave_receive(spi_t *obj) { + return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0); +} + +int spi_slave_read(spi_t *obj) { + return RSPI[obj->spi]->SPDR.UINT8[0]; +} + +void spi_slave_write(spi_t *obj, int value) { + while (spi_writable(obj) == 0) ; + RSPI[obj->spi]->SPDR.UINT8[0] = value; +} + +int spi_busy(spi_t *obj) { + return (RSPI[obj->spi]->SPSR & (1 << 6)) ? (0) : (1); +} diff --git a/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c new file mode 100644 index 0000000000..9d432530df --- /dev/null +++ b/libraries/mbed/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c @@ -0,0 +1,96 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include +#include "us_ticker_api.h" +#include "PeripheralNames.h" +#include "mtu2_iodefine.h" + +#define US_TICKER_TIMER (OSTM0.OSTMnCMP) +#define US_TICKER_TIMER_IRQn TIMER3_IRQn + +int us_ticker_inited = 0; + +void us_ticker_interrupt(void) { + us_ticker_irq_handler(); + GIC_EndInterrupt(TGI2A_IRQn); +} + +void us_ticker_init(void) { + if (us_ticker_inited) return; + us_ticker_inited = 1; + + /* Power Control for Peripherals */ + CPGSTBCR3 &= ~ 0x8; // turn on MTU2 + + // timer settings + MTU2.TSYR = 0x6; // cascading T_1-T_2 + + MTU2.TCR_2 = 0x03; // divider 1/64 + MTU2.TCR_1 = 0x07; // count-up from T_2 pulse(cascade) + + MTU2.TCNT_1 = 0x00; // counter value set to 0 + MTU2.TCNT_2 = 0x00; // + + MTU2.TSTR |= 0x06; // + MTU2.TSR_2 = 0xc0; // timer start + + // INTC settings + InterruptHandlerRegister(TGI2A_IRQn, (void (*)(uint32_t))us_ticker_interrupt); + GIC_SetPriority(TGI2A_IRQn, 5); + GIC_EnableIRQ(TGI2A_IRQn); + __enable_irq(); +} + +//static const float PCLK =33.33, // dummy + //PRESCALE =64.0; // dummy +static const float FACTOR_C2U = 1.9201920192019204, //(PRESCALE/PCLK) + FACTOR_U2C = 0.52078125; //(PCLK/PRESCALE) + +#define F_CLK2us(val) ((uint32_t)((val)*FACTOR_C2U)) +#define F_us2CLK(val) ((uint32_t)((val)*FACTOR_U2C)) + + +uint32_t us_ticker_read() { + static uint32_t max_val = 0x8551eb85; //*F_us2CLK(0xffffffff)+1; + uint32_t val; + if (!us_ticker_inited) + us_ticker_init(); + + val = MTU2.TCNT_1<<16 | MTU2.TCNT_2; // concat cascaded Counters + if (val > max_val) { // if overflow (in us-timer) + val -= max_val; // correct value + MTU2.TCNT_1 = 0; // reset counter + MTU2.TCNT_2 = val; + } + val = F_CLK2us(val); + return val; +} + +void us_ticker_set_interrupt(timestamp_t timestamp) { + // set match value + timestamp = F_us2CLK(timestamp); + MTU2.TGRA_2 = timestamp & 0xffff; + // enable match interrupt + MTU2.TIER_2 = 0x01; +} + +void us_ticker_disable_interrupt(void) { + MTU2.TIER_2 &= ~(0xc0); +} + +void us_ticker_clear_interrupt(void) { + MTU2.TSR_2 &= 0xc0; +} diff --git a/libraries/rtos/rtos/Thread.cpp b/libraries/rtos/rtos/Thread.cpp index 527484137a..fc361593e5 100644 --- a/libraries/rtos/rtos/Thread.cpp +++ b/libraries/rtos/rtos/Thread.cpp @@ -31,6 +31,7 @@ Thread::Thread(void (*task)(void const *argument), void *argument, _thread_def.pthread = task; _thread_def.tpriority = priority; _thread_def.stacksize = stack_size; +#ifndef __MBED_CMSIS_RTOS_CA9 if (stack_pointer != NULL) { _thread_def.stack_pointer = stack_pointer; _dynamic_stack = false; @@ -40,6 +41,7 @@ Thread::Thread(void (*task)(void const *argument), void *argument, error("Error allocating the stack memory\n"); _dynamic_stack = true; } +#endif #endif _tid = osThreadCreate(&_thread_def, argument); } @@ -61,7 +63,13 @@ int32_t Thread::signal_set(int32_t signals) { } Thread::State Thread::get_state() { +#ifndef __MBED_CMSIS_RTOS_CA9 return ((State)_thread_def.tcb.state); +#else + uint8_t status; + status = osThreadGetState(_tid); + return ((State)status); +#endif } osEvent Thread::signal_wait(int32_t signals, uint32_t millisec) { @@ -82,9 +90,11 @@ osThreadId Thread::gettid() { Thread::~Thread() { terminate(); +#ifndef __MBED_CMSIS_RTOS_CA9 if (_dynamic_stack) { delete[] (_thread_def.stack_pointer); } +#endif } } diff --git a/libraries/rtos/rtx_ca/ARM/HAL_CA9.c b/libraries/rtos/rtx_ca/ARM/HAL_CA9.c new file mode 100644 index 0000000000..51fe18e506 --- /dev/null +++ b/libraries/rtos/rtx_ca/ARM/HAL_CA9.c @@ -0,0 +1,416 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: HAL_CA9.c + * Purpose: Hardware Abstraction Layer for Cortex-A9 + * Rev.: 3 Sept 2013 + *---------------------------------------------------------------------------- + * + * Copyright (c) 2012 - 2013 ARM Limited + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_System.h" +#include "rt_Task.h" +#include "rt_List.h" +#include "rt_MemBox.h" +#include "rt_HAL_CA.h" + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + +//For A-class, set USR/SYS stack +__asm void rt_set_PSP (U32 stack) { + ARM + + MRS R1, CPSR + CPS #MODE_SYS ;no effect in USR mode + ISB + MOV SP, R0 + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR + +} + +//For A-class, get USR/SYS stack +__asm U32 rt_get_PSP (void) { + ARM + + MRS R1, CPSR + CPS #MODE_SYS ;no effect in USR mode + ISB + MOV R0, SP + MSR CPSR_c, R1 ;no effect in USR mode + ISB + BX LR +} + +/*--------------------------- _alloc_box ------------------------------------*/ +__asm void *_alloc_box (void *box_mem) { + /* Function wrapper for Unprivileged/Privileged mode. */ + ARM + + LDR R12,=__cpp(rt_alloc_box) + MRS R2, CPSR + LSLS R2, #28 + BXNE R12 + SVC 0 + BX LR +} + + +/*--------------------------- _free_box -------------------------------------*/ +__asm int _free_box (void *box_mem, void *box) { + /* Function wrapper for Unprivileged/Privileged mode. */ + ARM + + LDR R12,=__cpp(rt_free_box) + MRS R2, CPSR + LSLS R2, #28 + BXNE R12 + SVC 0 + BX LR + +} + +/*-------------------------- SVC_Handler -----------------------------------*/ + +#pragma push +#pragma arm +__asm void SVC_Handler (void) { + PRESERVE8 + ARM + + IMPORT rt_tsk_lock + IMPORT rt_tsk_unlock + IMPORT SVC_Count + IMPORT SVC_Table + IMPORT rt_stk_check + IMPORT FPUEnable + +Mode_SVC EQU 0x13 + + SRSFD SP!, #Mode_SVC ; Push LR_SVC and SPRS_SVC onto SVC mode stack + PUSH {R4} ; Push R4 so we can use it as a temp + + MRS R4,SPSR ; Get SPSR + TST R4,#CPSR_T_BIT ; Check Thumb Bit + LDRNEH R4,[LR,#-2] ; Thumb: Load Halfword + BICNE R4,R4,#0xFF00 ; Extract SVC Number + LDREQ R4,[LR,#-4] ; ARM: Load Word + BICEQ R4,R4,#0xFF000000 ; Extract SVC Number + + /* Lock out systick and re-enable interrupts */ + PUSH {R0-R3,R12,LR} + + AND R12, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR to SVC stack + + BLX rt_tsk_lock + CPSIE i + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R3,R12,LR} + + CMP R4,#0 + BNE SVC_User + + MRS R4,SPSR + PUSH {R4} ; Push R4 so we can use it as a temp + AND R4, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R4 ; Adjust stack + PUSH {R4, LR} ; Store stack adjustment and dummy LR + BLX R12 + POP {R4, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R4 ; Unadjust stack + POP {R4} ; Restore R4 + MSR SPSR_CXSF,R4 + + /* Here we will be in SVC mode (even if coming in from PendSV_Handler or OS_Tick_Handler) */ +Sys_Switch + LDR LR,=__cpp(&os_tsk) + LDM LR,{R4,LR} ; os_tsk.run, os_tsk.new + CMP R4,LR + BNE switching + + PUSH {R0-R3,R12,LR} + + AND R12, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR to SVC stack + + CPSID i + BLX rt_tsk_unlock + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R3,R12,LR} + POP {R4} + RFEFD SP! ; Return from exception, no task switch + +switching + CLREX + CMP R4,#0 + ADDEQ SP,SP,#12 ; Original R4, LR & SPSR do not need to be popped when we are paging in a different task + BEQ SVC_Next ; Runtask deleted? + + + PUSH {R8-R11} //R4 and LR already stacked + MOV R10,R4 ; Preserve os_tsk.run + MOV R11,LR ; Preserve os_tsk.new + + ADD R8,SP,#16 ; Unstack R4,LR + LDMIA R8,{R4,LR} + + SUB SP,SP,#4 ; Make space on the stack for the next instn + STMIA SP,{SP}^ ; Put User SP onto stack + POP {R8} ; Pop User SP into R8 + + MRS R9,SPSR + STMDB R8!,{R9} ; User CPSR + STMDB R8!,{LR} ; User PC + STMDB R8,{LR}^ ; User LR + SUB R8,R8,#4 ; No writeback for store of User LR + STMDB R8!,{R0-R3,R12} ; User R0-R3,R12 + MOV R3,R10 ; os_tsk.run + MOV LR,R11 ; os_tsk.new + POP {R9-R12} + ADD SP,SP,#12 ; Fix up SP for unstack of R4, LR & SPSR + STMDB R8!,{R4-R7,R9-R12} ; User R4-R11 + + //If applicable, stack VFP state + MRC p15,0,R1,c1,c0,2 ; VFP/NEON access enabled? (CPACR) + AND R2,R1,#0x00F00000 + CMP R2,#0x00F00000 + BNE no_outgoing_vfp + VMRS R2,FPSCR + STMDB R8!,{R2,R4} ; Push FPSCR, maintain 8-byte alignment + VSTMDB R8!,{S0-S31} + LDRB R2,[R3,#TCB_STACKF] ; Record in TCB that VFP state is stacked + ORR R2,#2 + STRB R2,[R3,#TCB_STACKF] + +no_outgoing_vfp + STR R8,[R3,#TCB_TSTACK] + MOV R4,LR + + PUSH {R4} ; Push R4 so we can use it as a temp + AND R4, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R4 ; Adjust stack + PUSH {R4, LR} ; Store stack adjustment and dummy LR to SVC stack + + BLX rt_stk_check + + POP {R4, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R4 ; Unadjust stack + POP {R4} ; Restore R4 + + MOV LR,R4 + +SVC_Next //R4 == os_tsk.run, LR == os_tsk.new, R0-R3, R5-R12 corruptible + LDR R1,=__cpp(&os_tsk) ; os_tsk.run = os_tsk.new + STR LR,[R1] + LDRB R1,[LR,#TCB_TID] ; os_tsk.run->task_id + LSL R1,#8 ; Store PROCID + MCR p15,0,R1,c13,c0,1 ; Write CONTEXTIDR + + LDR R0,[LR,#TCB_TSTACK] ; os_tsk.run->tsk_stack + + //Does incoming task have VFP state in stack? + LDRB R3,[LR,#TCB_STACKF] + TST R3,#0x2 + MRC p15,0,R1,c1,c0,2 ; Read CPACR + ANDEQ R1,R1,#0xFF0FFFFF ; Disable VFP access if incoming task does not have stacked VFP state + ORRNE R1,R1,#0x00F00000 ; Enable VFP access if incoming task does have stacked VFP state + MCR p15,0,R1,c1,c0,2 ; Write CPACR + BEQ no_incoming_vfp + ISB ; We only need the sync if we enabled, otherwise we will context switch before next VFP instruction anyway + VLDMIA R0!,{S0-S31} + LDR R2,[R0] + VMSR FPSCR,R2 + ADD R0,R0,#8 + +no_incoming_vfp + LDR R1,[R0,#60] ; Restore User CPSR + MSR SPSR_CXSF,R1 + LDMIA R0!,{R4-R11} ; Restore User R4-R11 + ADD R0,R0,#4 ; Restore User R1-R3,R12 + LDMIA R0!,{R1-R3,R12} + LDMIA R0,{LR}^ ; Restore User LR + ADD R0,R0,#4 ; No writeback for load to user LR + LDMIA R0!,{LR} ; Restore User PC + ADD R0,R0,#4 ; Correct User SP for unstacked user CPSR + + PUSH {R0} ; Push R0 onto stack + LDMIA SP,{SP}^ ; Get R0 off stack into User SP + ADD SP,SP,#4 ; Put SP back + + LDR R0,[R0,#-32] ; Restore R0 + + PUSH {R0-R3,R12,LR} + + AND R12, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R12 ; Adjust stack + PUSH {R12, LR} ; Store stack adjustment and dummy LR to SVC stack + + CPSID i + BLX rt_tsk_unlock + + POP {R12, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R12 ; Unadjust stack + + POP {R0-R3,R12,LR} + + MOVS PC,LR ; Return from exception + + + /*------------------- User SVC -------------------------------*/ + +SVC_User + LDR R12,=SVC_Count + LDR R12,[R12] + CMP R4,R12 ; Check for overflow + BHI SVC_Done + + LDR R12,=SVC_Table-4 + LDR R12,[R12,R4,LSL #2] ; Load SVC Function Address + MRS R4,SPSR ; Save SPSR + PUSH {R4} ; Push R4 so we can use it as a temp + AND R4, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R4 ; Adjust stack + PUSH {R4, LR} ; Store stack adjustment and dummy LR + BLX R12 ; Call SVC Function + POP {R4, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R4 ; Unadjust stack + POP {R4} ; Restore R4 + MSR SPSR_CXSF,R4 ; Restore SPSR + +SVC_Done + PUSH {R0-R3,R12,LR} + + PUSH {R4} ; Push R4 so we can use it as a temp + AND R4, SP, #4 ; Ensure stack is 8-byte aligned + SUB SP, SP, R4 ; Adjust stack + PUSH {R4, LR} ; Store stack adjustment and dummy LR + + CPSID i + BLX rt_tsk_unlock + + POP {R4, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R4 ; Unadjust stack + POP {R4} ; Restore R4 + + POP {R0-R3,R12,LR} + POP {R4} + RFEFD SP! ; Return from exception +} +#pragma pop + +#pragma push +#pragma arm +__asm void PendSV_Handler (U32 IRQn) { + ARM + + IMPORT rt_tsk_lock + IMPORT IRQNestLevel + + ADD SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment) + + //Disable systick interrupts, then write EOIR. We want interrupts disabled before we enter the context switcher. + PUSH {R0, R1} + BLX rt_tsk_lock + POP {R0, R1} + LDR R1, =__cpp(&GICInterface_BASE) + LDR R1, [R1, #0] + STR R0, [R1, #0x10] + + LDR R0, =IRQNestLevel ; Get address of nesting counter + LDR R1, [R0] + SUB R1, R1, #1 ; Decrement nesting counter + STR R1, [R0] + + BLX __cpp(rt_pop_req) + + POP {R1, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R1 ; Unadjust stack + + LDR R0,[SP,#24] + MSR SPSR_CXSF,R0 + POP {R0-R3,R12} ; Leave SPSR & LR on the stack + PUSH {R4} + B Sys_Switch +} +#pragma pop + + +#pragma push +#pragma arm +__asm void OS_Tick_Handler (U32 IRQn) { + ARM + + IMPORT rt_tsk_lock + IMPORT IRQNestLevel + + ADD SP,SP,#8 //fix up stack pointer (R0 has been pushed and will never be popped, R1 was pushed for stack alignment) + + PUSH {R0, R1} + BLX rt_tsk_lock + POP {R0, R1} + LDR R1, =__cpp(&GICInterface_BASE) + LDR R1, [R1, #0] + STR R0, [R1, #0x10] + + LDR R0, =IRQNestLevel ; Get address of nesting counter + LDR R1, [R0] + SUB R1, R1, #1 ; Decrement nesting counter + STR R1, [R0] + + BLX __cpp(os_tick_irqack) + BLX __cpp(rt_systick) + + POP {R1, LR} ; Get stack adjustment & discard dummy LR + ADD SP, SP, R1 ; Unadjust stack + + LDR R0,[SP,#24] + MSR SPSR_CXSF,R0 + POP {R0-R3,R12} ; Leave SPSR & LR on the stack + PUSH {R4} + B Sys_Switch +} +#pragma pop + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx_ca/ARM/SVC_Table.s b/libraries/rtos/rtx_ca/ARM/SVC_Table.s new file mode 100644 index 0000000000..eb88d03495 --- /dev/null +++ b/libraries/rtos/rtx_ca/ARM/SVC_Table.s @@ -0,0 +1,57 @@ +;/*---------------------------------------------------------------------------- +; * RL-ARM - RTX +; *---------------------------------------------------------------------------- +; * Name: SVC_TABLE.S +; * Purpose: Pre-defined SVC Table for Cortex-M +; * Rev.: V4.60 +; *---------------------------------------------------------------------------- +; * +; * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH +; * All rights reserved. +; * Redistribution and use in source and binary forms, with or without +; * modification, are permitted provided that the following conditions are met: +; * - Redistributions of source code must retain the above copyright +; * notice, this list of conditions and the following disclaimer. +; * - Redistributions in binary form must reproduce the above copyright +; * notice, this list of conditions and the following disclaimer in the +; * documentation and/or other materials provided with the distribution. +; * - Neither the name of ARM nor the names of its contributors may be used +; * to endorse or promote products derived from this software without +; * specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; * POSSIBILITY OF SUCH DAMAGE. +; *---------------------------------------------------------------------------*/ + + + AREA SVC_TABLE, CODE, READONLY + + EXPORT SVC_Count + +SVC_Cnt EQU (SVC_End-SVC_Table)/4 +SVC_Count DCD SVC_Cnt + +; Import user SVC functions here. +; IMPORT __SVC_1 + + EXPORT SVC_Table +SVC_Table +; Insert user SVC functions here. SVC 0 used by RTL Kernel. +; DCD __SVC_1 ; InitMemorySubsystem + +SVC_End + + END + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx_ca/HAL_CA.c b/libraries/rtos/rtx_ca/HAL_CA.c new file mode 100644 index 0000000000..e05921f39e --- /dev/null +++ b/libraries/rtos/rtx_ca/HAL_CA.c @@ -0,0 +1,126 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: HAL_CA.C + * Purpose: Hardware Abstraction Layer for Cortex-A + * Rev.: + *---------------------------------------------------------------------------- + * + * Copyright (c) 2012 ARM Limited + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_HAL_CA.h" + +/*--------------------------- os_init_context -------------------------------*/ + +void rt_init_stack (P_TCB p_TCB, FUNCP task_body) { + /* Prepare TCB and saved context for a first time start of a task. */ + U32 *stk,i,size; + + /* Prepare a complete interrupt frame for first task start */ + size = p_TCB->priv_stack >> 2; + if (size == 0) { + size = (U16)os_stackinfo >> 2; + } + /* Write to the top of stack. */ + stk = &p_TCB->stack[size]; + + /* Auto correct to 8-byte ARM stack alignment. */ + if ((U32)stk & 0x04) { + stk--; + } + + stk -= 16; + + /* Initial PC and default CPSR */ + stk[14] = (U32)task_body; + /* Task run mode is inherited from the startup file. */ + /* (non-privileged USER or privileged SYSTEM mode) */ + stk[15] = (os_flags & 1) ? INIT_CPSR_SYS : INIT_CPSR_USER; + /* Set T-bit if task function in Thumb mode. */ + if ((U32)task_body & 1) { + stk[15] |= CPSR_T_BIT; + } + /* Assign a void pointer to R0. */ + stk[8] = (U32)p_TCB->msg; + /* Clear R1-R12,LR registers. */ + for (i = 0; i < 8; i++) { + stk[i] = 0; + } + for (i = 9; i < 14; i++) { + stk[i] = 0; + } + + /* Initial Task stack pointer. */ + p_TCB->tsk_stack = (U32)stk; + + /* Task entry point. */ + p_TCB->ptask = task_body; + + /* Set a magic word for checking of stack overflow. */ + p_TCB->stack[0] = MAGIC_WORD; +} + + +/*--------------------------- rt_ret_val ----------------------------------*/ + +static __inline U32 *rt_ret_regs (P_TCB p_TCB) { + /* Get pointer to task return value registers (R0..R3) in Stack */ +#if (__TARGET_FPU_VFP) + if (p_TCB->stack_frame & 0x2) { + /* Extended Stack Frame: S0-31,FPSCR,Reserved,R4-R11,R0-R3,R12,LR,PC,xPSR */ + return (U32 *)(p_TCB->tsk_stack + 8*4 + 34*4); + } else { + /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */ + return (U32 *)(p_TCB->tsk_stack + 8*4); + } +#else + /* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */ + return (U32 *)(p_TCB->tsk_stack + 8*4); +#endif +} + +void rt_ret_val (P_TCB p_TCB, U32 v0) { + U32 *ret; + + ret = rt_ret_regs(p_TCB); + ret[0] = v0; +} + +void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) { + U32 *ret; + + ret = rt_ret_regs(p_TCB); + ret[0] = v0; + ret[1] = v1; +} + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx_ca/HAL_CM.c b/libraries/rtos/rtx_ca/HAL_CM.c new file mode 100644 index 0000000000..f9dfce6d57 --- /dev/null +++ b/libraries/rtos/rtx_ca/HAL_CM.c @@ -0,0 +1,168 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: HAL_CM.C + * Purpose: Hardware Abstraction Layer for Cortex-M + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_HAL_CM.h" + + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +#ifdef DBG_MSG +BIT dbg_msg; +#endif + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_init_stack ---------------------------------*/ + +void rt_init_stack (P_TCB p_TCB, FUNCP task_body) { + /* Prepare TCB and saved context for a first time start of a task. */ + U32 *stk,i,size; + + /* Prepare a complete interrupt frame for first task start */ + size = p_TCB->priv_stack >> 2; + if (size == 0) { + size = (U16)os_stackinfo >> 2; + } + + /* Write to the top of stack. */ + stk = &p_TCB->stack[size]; + + /* Auto correct to 8-byte ARM stack alignment. */ + if ((U32)stk & 0x04) { + stk--; + } + + stk -= 16; + + /* Default xPSR and initial PC */ + stk[15] = INITIAL_xPSR; + stk[14] = (U32)task_body; + + /* Clear R4-R11,R0-R3,R12,LR registers. */ + for (i = 0; i < 14; i++) { + stk[i] = 0; + } + + /* Assign a void pointer to R0. */ + stk[8] = (U32)p_TCB->msg; + + /* Initial Task stack pointer. */ + p_TCB->tsk_stack = (U32)stk; + + /* Task entry point. */ + p_TCB->ptask = task_body; + + /* Set a magic word for checking of stack overflow. */ + p_TCB->stack[0] = MAGIC_WORD; +} + + +/*--------------------------- rt_ret_val ----------------------------------*/ + +static __inline U32 *rt_ret_regs (P_TCB p_TCB) { + /* Get pointer to task return value registers (R0..R3) in Stack */ +#if (__TARGET_FPU_VFP) + if (p_TCB->stack_frame) { + /* Extended Stack Frame: R4-R11,S16-S31,R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR */ + return (U32 *)(p_TCB->tsk_stack + 8*4 + 16*4); + } else { + /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */ + return (U32 *)(p_TCB->tsk_stack + 8*4); + } +#else + /* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */ + return (U32 *)(p_TCB->tsk_stack + 8*4); +#endif +} + +void rt_ret_val (P_TCB p_TCB, U32 v0) { + U32 *ret; + + ret = rt_ret_regs(p_TCB); + ret[0] = v0; +} + +void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) { + U32 *ret; + + ret = rt_ret_regs(p_TCB); + ret[0] = v0; + ret[1] = v1; +} + + +/*--------------------------- dbg_init --------------------------------------*/ + +#ifdef DBG_MSG +void dbg_init (void) { + if ((DEMCR & DEMCR_TRCENA) && + (ITM_CONTROL & ITM_ITMENA) && + (ITM_ENABLE & (1UL << 31))) { + dbg_msg = __TRUE; + } +} +#endif + +/*--------------------------- dbg_task_notify -------------------------------*/ + +#ifdef DBG_MSG +void dbg_task_notify (P_TCB p_tcb, BOOL create) { + while (ITM_PORT31_U32 == 0); + ITM_PORT31_U32 = (U32)p_tcb->ptask; + while (ITM_PORT31_U32 == 0); + ITM_PORT31_U16 = (create << 8) | p_tcb->task_id; +} +#endif + +/*--------------------------- dbg_task_switch -------------------------------*/ + +#ifdef DBG_MSG +void dbg_task_switch (U32 task_id) { + while (ITM_PORT31_U32 == 0); + ITM_PORT31_U8 = task_id; +} +#endif + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/RTX_CM_lib.h b/libraries/rtos/rtx_ca/RTX_CM_lib.h new file mode 100644 index 0000000000..4e2aeef8b6 --- /dev/null +++ b/libraries/rtos/rtx_ca/RTX_CM_lib.h @@ -0,0 +1,423 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_CM_LIB.H + * Purpose: RTX Kernel System Configuration + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#if defined (__CC_ARM) +#pragma O3 +#define __USED __attribute__((used)) +#elif defined (__GNUC__) +#pragma GCC optimize ("O3") +#define __USED __attribute__((used)) +#elif defined (__ICCARM__) +#define __USED __root +#endif + + +/*---------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +#define _declare_box(pool,size,cnt) uint32_t pool[(((size)+3)/4)*(cnt) + 3] +#define _declare_box8(pool,size,cnt) uint64_t pool[(((size)+7)/8)*(cnt) + 2] + +#define OS_TCB_SIZE 48 +#define OS_TMR_SIZE 8 + +#if defined (__CC_ARM) && !defined (__MICROLIB) + +typedef void *OS_ID; +typedef uint32_t OS_TID; +typedef uint32_t OS_MUT[3]; +typedef uint32_t OS_RESULT; + +#define runtask_id() rt_tsk_self() +#define mutex_init(m) rt_mut_init(m) +#define mutex_wait(m) os_mut_wait(m,0xFFFF) +#define mutex_rel(m) os_mut_release(m) + +extern OS_TID rt_tsk_self (void); +extern void rt_mut_init (OS_ID mutex); +extern OS_RESULT rt_mut_release (OS_ID mutex); +extern OS_RESULT rt_mut_wait (OS_ID mutex, uint16_t timeout); + +#define os_mut_wait(mutex,timeout) _os_mut_wait((uint32_t)rt_mut_wait,mutex,timeout) +#define os_mut_release(mutex) _os_mut_release((uint32_t)rt_mut_release,mutex) + +OS_RESULT _os_mut_release (uint32_t p, OS_ID mutex) __svc_indirect(0); +OS_RESULT _os_mut_wait (uint32_t p, OS_ID mutex, uint16_t timeout) __svc_indirect(0); + +#endif + + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +#if (OS_TIMERS != 0) +#define OS_TASK_CNT (OS_TASKCNT + 1) +#define OS_PRIV_CNT (OS_PRIVCNT + 2) +#define OS_STACK_SZ (4*(OS_PRIVSTKSIZE+OS_MAINSTKSIZE+OS_TIMERSTKSZ)) +#else +#define OS_TASK_CNT OS_TASKCNT +#define OS_PRIV_CNT (OS_PRIVCNT + 1) +#define OS_STACK_SZ (4*(OS_PRIVSTKSIZE+OS_MAINSTKSIZE)) +#endif + +uint16_t const os_maxtaskrun = OS_TASK_CNT; +uint32_t const os_stackinfo = (OS_STKCHECK<<24)| (OS_PRIV_CNT<<16) | (OS_STKSIZE*4); +uint32_t const os_rrobin = (OS_ROBIN << 16) | OS_ROBINTOUT; +uint32_t const os_trv = OS_TRV; +uint8_t const os_flags = OS_RUNPRIV; + +/* Export following defines to uVision debugger. */ +__USED uint32_t const os_clockrate = OS_TICK; +__USED uint32_t const os_timernum = 0; + +/* Memory pool for TCB allocation */ +_declare_box (mp_tcb, OS_TCB_SIZE, OS_TASK_CNT); +uint16_t const mp_tcb_size = sizeof(mp_tcb); + +/* Memory pool for System stack allocation (+os_idle_demon). */ +_declare_box8 (mp_stk, OS_STKSIZE*4, OS_TASK_CNT-OS_PRIV_CNT+1); +uint32_t const mp_stk_size = sizeof(mp_stk); + +/* Memory pool for user specified stack allocation (+main, +timer) */ +uint64_t os_stack_mem[2+OS_PRIV_CNT+(OS_STACK_SZ/8)]; +uint32_t const os_stack_sz = sizeof(os_stack_mem); + +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +/* Fifo Queue buffer for ISR requests.*/ +uint32_t os_fifo[OS_FIFOSZ*2+1]; +uint8_t const os_fifo_size = OS_FIFOSZ; + +/* An array of Active task pointers. */ +void *os_active_TCB[OS_TASK_CNT]; + +/* User Timers Resources */ +#if (OS_TIMERS != 0) +extern void osTimerThread (void const *argument); +#if defined (__MBED_CMSIS_RTOS_CA9) +osThreadDef(osTimerThread, (osPriority)(OS_TIMERPRIO-3), 4*OS_TIMERSTKSZ); +#else +osThreadDef(osTimerThread, (osPriority)(OS_TIMERPRIO-3), 1, 4*OS_TIMERSTKSZ); +#endif +osThreadId osThreadId_osTimerThread; +osMessageQDef(osTimerMessageQ, OS_TIMERCBQS, void *); +osMessageQId osMessageQId_osTimerMessageQ; +#else +osThreadDef_t os_thread_def_osTimerThread = { NULL }; +osThreadId osThreadId_osTimerThread; +osMessageQDef(osTimerMessageQ, 0, void *); +osMessageQId osMessageQId_osTimerMessageQ; +#endif + +/* Legacy RTX User Timers not used */ +uint32_t os_tmr = 0; +uint32_t const *m_tmr = NULL; +uint16_t const mp_tmr_size = 0; + +#if defined (__CC_ARM) && !defined (__MICROLIB) + /* A memory space for arm standard library. */ + static uint32_t std_libspace[OS_TASK_CNT][96/4]; + static OS_MUT std_libmutex[OS_MUTEXCNT]; + static uint32_t nr_mutex; + extern void *__libspace_start; +#endif + + +/*---------------------------------------------------------------------------- + * RTX Optimizations (empty functions) + *---------------------------------------------------------------------------*/ + +#if OS_ROBIN == 0 + void rt_init_robin (void) {;} + void rt_chk_robin (void) {;} +#endif + +#if OS_STKCHECK == 0 + void rt_stk_check (void) {;} +#endif + + +/*---------------------------------------------------------------------------- + * Standard Library multithreading interface + *---------------------------------------------------------------------------*/ + +#if defined (__CC_ARM) && !defined (__MICROLIB) + +/*--------------------------- __user_perthread_libspace ---------------------*/ + +void *__user_perthread_libspace (void) { + /* Provide a separate libspace for each task. */ + uint32_t idx; + + idx = runtask_id (); + if (idx == 0) { + /* RTX not running yet. */ + return (&__libspace_start); + } + return ((void *)&std_libspace[idx-1]); +} + +/*--------------------------- _mutex_initialize -----------------------------*/ + +int _mutex_initialize (OS_ID *mutex) { + /* Allocate and initialize a system mutex. */ + + if (nr_mutex >= OS_MUTEXCNT) { + /* If you are here, you need to increase the number OS_MUTEXCNT. */ + for (;;); + } + *mutex = &std_libmutex[nr_mutex++]; + mutex_init (*mutex); + return (1); +} + + +/*--------------------------- _mutex_acquire --------------------------------*/ + +__attribute__((used)) void _mutex_acquire (OS_ID *mutex) { + /* Acquire a system mutex, lock stdlib resources. */ + if (runtask_id ()) { + /* RTX running, acquire a mutex. */ + mutex_wait (*mutex); + } +} + + +/*--------------------------- _mutex_release --------------------------------*/ + +__attribute__((used)) void _mutex_release (OS_ID *mutex) { + /* Release a system mutex, unlock stdlib resources. */ + if (runtask_id ()) { + /* RTX running, release a mutex. */ + mutex_rel (*mutex); + } +} + +#endif + + +/*---------------------------------------------------------------------------- + * RTX Startup + *---------------------------------------------------------------------------*/ + +/* Main Thread definition */ +extern int main (void); +osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 1, 4*OS_MAINSTKSIZE }; + + +#if defined (__CC_ARM) + +#ifdef __MICROLIB +void _main_init (void) __attribute__((section(".ARM.Collect$$$$000000FF"))); +#if __TARGET_ARCH_ARM +#pragma push +#pragma arm +#endif +void _main_init (void) { + osKernelInitialize(); + osThreadCreate(&os_thread_def_main, NULL); + osKernelStart(); + for (;;); +} +#if __TARGET_ARCH_ARM +#pragma pop +#endif +#else +#if 0 +//#ifdef __MBED_CMSIS_RTOS_CA9 +__asm void __rt_entry (void) { + + IMPORT __user_setup_stackheap + IMPORT __rt_lib_init + IMPORT os_thread_def_main + IMPORT osKernelInitialize + IMPORT osKernelStart + IMPORT osThreadCreate + IMPORT InterruptHandlerRegister + IMPORT PendSV_Handler + IMPORT OS_Tick_Handler + IMPORT exit + + BL __user_setup_stackheap + MOV R1,R2 + BL __rt_lib_init + BL osKernelInitialize + LDR R0,=os_thread_def_main + MOVS R1,#0 + BL osThreadCreate + BL osKernelStart + MOVS R0,#0 + LDR R1,=PendSV_Handler + BL InterruptHandlerRegister + MOVS R0,#134 + LDR R1,=OS_Tick_Handler + BL InterruptHandlerRegister + BL exit + + ALIGN +} +#else +__asm void __rt_entry (void) { + + IMPORT __user_setup_stackheap + IMPORT __rt_lib_init + IMPORT os_thread_def_main + IMPORT osKernelInitialize + IMPORT osKernelStart + IMPORT osThreadCreate + IMPORT exit + + BL __user_setup_stackheap + MOV R1,R2 + BL __rt_lib_init + BL osKernelInitialize + LDR R0,=os_thread_def_main + MOVS R1,#0 + BL osThreadCreate + BL osKernelStart + BL exit + + ALIGN +} +#endif +#endif + +#elif defined (__GNUC__) + +#ifdef __CS3__ + +/* CS3 start_c routine. + * + * Copyright (c) 2006, 2007 CodeSourcery Inc + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ + +#include "cs3.h" + +extern void __libc_init_array (void); + +__attribute ((noreturn)) void __cs3_start_c (void){ + unsigned regions = __cs3_region_num; + const struct __cs3_region *rptr = __cs3_regions; + + /* Initialize memory */ + for (regions = __cs3_region_num, rptr = __cs3_regions; regions--; rptr++) { + long long *src = (long long *)rptr->init; + long long *dst = (long long *)rptr->data; + unsigned limit = rptr->init_size; + unsigned count; + + if (src != dst) + for (count = 0; count != limit; count += sizeof (long long)) + *dst++ = *src++; + else + dst = (long long *)((char *)dst + limit); + limit = rptr->zero_size; + for (count = 0; count != limit; count += sizeof (long long)) + *dst++ = 0; + } + + /* Run initializers. */ + __libc_init_array (); + + osKernelInitialize(); + osThreadCreate(&os_thread_def_main, NULL); + osKernelStart(); + for (;;); +} + +#else + +__attribute__((naked)) void software_init_hook (void) { + __asm ( + ".syntax unified\n" + ".thumb\n" + "movs r0,#0\n" + "movs r1,#0\n" + "mov r4,r0\n" + "mov r5,r1\n" + "ldr r0,= __libc_fini_array\n" + "bl atexit\n" + "bl __libc_init_array\n" + "mov r0,r4\n" + "mov r1,r5\n" + "bl osKernelInitialize\n" + "ldr r0,=os_thread_def_main\n" + "movs r1,#0\n" + "bl osThreadCreate\n" + "bl osKernelStart\n" + "bl exit\n" + ); +} + +#endif + +#elif defined (__ICCARM__) + +extern int __low_level_init(void); +extern void __iar_data_init3(void); +extern void exit(int arg); + +__noreturn __stackless void __cmain(void) { + int a; + + if (__low_level_init() != 0) { + __iar_data_init3(); + } + osKernelInitialize(); + osThreadCreate(&os_thread_def_main, NULL); + a = osKernelStart(); + exit(a); +} + +#endif + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/RTX_Conf_CA.c b/libraries/rtos/rtx_ca/RTX_Conf_CA.c new file mode 100644 index 0000000000..37fa755ce6 --- /dev/null +++ b/libraries/rtos/rtx_ca/RTX_Conf_CA.c @@ -0,0 +1,319 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_Conf_CM.C + * Purpose: Configuration of CMSIS RTX Kernel + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "cmsis_os.h" + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Thread Configuration +// ======================= +// +// Number of concurrent running threads <0-250> +// Defines max. number of threads that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 25 +#endif + +// Default Thread stack size [bytes] <64-4096:8><#/4> +// Defines default stack size for threads with osThreadDef stacksz = 0 +// Default: 200 +#ifndef OS_STKSIZE + #define OS_STKSIZE 200 +#endif + +// Main Thread stack size [bytes] <64-4096:8><#/4> +// Defines stack size for main thread. +// Default: 200 +#ifndef OS_MAINSTKSIZE + #define OS_MAINSTKSIZE 512 +#endif + +// Number of threads with user-provided stack size <0-250> +// Defines the number of threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 8 +#endif + +// Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4> +// Defines the combined stack size for threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVSTKSIZE + #define OS_PRIVSTKSIZE 4096 +#endif + +// Check for stack overflow +// Includes the stack checking code for stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Processor mode for thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 0 +#endif + +// + +// RTX Kernel Timer Tick Configuration +// ====================================== +// Use Cortex-M SysTick timer as RTX Kernel Timer +// Use the Cortex-M SysTick timer as a time-base for RTX. +#ifndef OS_SYSTICK + #define OS_SYSTICK 0 +#endif +// +// Timer clock value [Hz] <1-1000000000> +// Defines the timer clock value. +// Default: 12000000 (12MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 12000000 +#endif + +// Timer tick value [us] <1-1000000> +// Defines the timer tick value. +// Default: 1000 (1ms) +#ifndef OS_TICK + #define OS_TICK 1000 +#endif + +// + +// System Configuration +// ======================= +// +// Round-Robin Thread switching +// =============================== +// +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Defines how long a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// User Timers +// ============== +// Enables user Timers +#ifndef OS_TIMERS + #define OS_TIMERS 1 +#endif + +// Timer Thread Priority +// <1=> Low +// <2=> Below Normal <3=> Normal <4=> Above Normal +// <5=> High +// <6=> Realtime (highest) +// Defines priority for Timer Thread +// Default: High +#ifndef OS_TIMERPRIO + #define OS_TIMERPRIO 5 +#endif + +// Timer Thread stack size [bytes] <64-4096:8><#/4> +// Defines stack size for Timer thread. +// Default: 200 +#ifndef OS_TIMERSTKSZ + #define OS_TIMERSTKSZ 400 +#endif + +// Timer Callback Queue size <1-32> +// Number of concurrent active timer callback functions. +// Default: 4 +#ifndef OS_TIMERCBQS + #define OS_TIMERCBQS 4 +#endif + +// + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the interrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +void os_idle_demon (void) { + /* The idle demon is a system thread, running when no other thread is */ + /* ready to run. */ + + for (;;) { + /* HERE: include optional user code to be executed when no thread runs.*/ +#if 0 + __DSB(); + __WFI(); +#endif + } +} + +#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer + +/*--------------------------- os_tick_init ----------------------------------*/ +#ifdef TARGET_RZ_A1H +#define OSTM0 (0xFCFEC000uL) /* OSTM0 */ +#define OSTM1 (0xFCFEC400uL) /* OSTM1 */ +#define CPG (0xFCFE0410uL) /* CPG */ + +#define CPGSTBCR5 (*((volatile unsigned char*)(CPG + 0x00000018uL))) + +#define OSTM0CMP (*((volatile unsigned long*)(OSTM0 + 0x00000000uL))) +#define OSTM0CNT (*((volatile unsigned long*)(OSTM0 + 0x00000004uL))) +#define OSTM0TE (*((volatile unsigned char*)(OSTM0 + 0x00000010uL))) +#define OSTM0TS (*((volatile unsigned char*)(OSTM0 + 0x00000014uL))) +#define OSTM0TT (*((volatile unsigned char*)(OSTM0 + 0x00000018uL))) +#define OSTM0CTL (*((volatile unsigned char*)(OSTM0 + 0x00000020uL))) + +#define OSTM1CMP (*((volatile unsigned long*)(OSTM1 + 0x00000000uL))) +#define OSTM1CNT (*((volatile unsigned long*)(OSTM1 + 0x00000004uL))) +#define OSTM1TE (*((volatile unsigned char*)(OSTM1 + 0x00000010uL))) +#define OSTM1TS (*((volatile unsigned char*)(OSTM1 + 0x00000014uL))) +#define OSTM1TT (*((volatile unsigned char*)(OSTM1 + 0x00000018uL))) +#define OSTM1CTL (*((volatile unsigned char*)(OSTM1 + 0x00000020uL))) + +#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ +#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) +#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) + +typedef enum +{ + IRQ_SGI0 = 0, + IRQ_OSTMI0TINT = 134 +} IRQn_Type; + +typedef void(*IRQHandler)(); + +extern void PendSV_Handler(uint32_t); +extern void OS_Tick_Handler(uint32_t); +extern uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler); +#endif + +// Initialize alternative hardware timer as RTX kernel timer +// Return: IRQ number of the alternative hardware timer +int os_tick_init (void) { +#ifdef TARGET_RZ_A1H + CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); /* enable OSTM0 clock */ + + OSTM0TT = 0x1; /* Stop the counter and clears the OSTM0TE bit. */ + OSTM0CTL = 0x1; /* Interval timer mode. Interrupt enabled */ + + OSTM0CMP = (uint32_t)(((double)CM0_RENESAS_RZ_A1_P0_CLK*(double)OS_TICK)/1E6); + + OSTM0TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */ + + InterruptHandlerRegister(IRQ_SGI0 , (IRQHandler)PendSV_Handler); + InterruptHandlerRegister(IRQ_OSTMI0TINT, (IRQHandler)OS_Tick_Handler); + + + return IRQ_OSTMI0TINT; /* Return IRQ number of timer (0..239) */ + /* RTX will set and configure the interrupt */ +#endif +} + +/*--------------------------- os_tick_irqack --------------------------------*/ + +// Acknowledge alternative hardware timer interrupt +void os_tick_irqack (void) { + /* ... */ +} + +#endif // (OS_SYSTICK == 0) + +/*--------------------------- os_error --------------------------------------*/ +extern void mbed_die(void); + +void os_error (uint32_t err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + mbed_die(); + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include "RTX_CM_lib.h" + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx_ca/RTX_Config.h b/libraries/rtos/rtx_ca/RTX_Config.h new file mode 100644 index 0000000000..266b56180a --- /dev/null +++ b/libraries/rtos/rtx_ca/RTX_Config.h @@ -0,0 +1,76 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_CONFIG.H + * Purpose: Exported functions of RTX_Config.c + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + + +/* Error Codes */ +#define OS_ERR_STK_OVF 1 +#define OS_ERR_FIFO_OVF 2 +#define OS_ERR_MBX_OVF 3 + +/* Definitions */ +#define BOX_ALIGN_8 0x80000000 +#define _declare_box(pool,size,cnt) U32 pool[(((size)+3)/4)*(cnt) + 3] +#define _declare_box8(pool,size,cnt) U64 pool[(((size)+7)/8)*(cnt) + 2] +#define _init_box8(pool,size,bsize) _init_box (pool,size,(bsize) | BOX_ALIGN_8) + +/* Variables */ +extern U32 mp_tcb[]; +extern U64 mp_stk[]; +extern U32 os_fifo[]; +extern void *os_active_TCB[]; + +/* Constants */ +extern U16 const os_maxtaskrun; +extern U32 const os_trv; +extern U8 const os_flags; +extern U32 const os_stackinfo; +extern U32 const os_rrobin; +extern U32 const os_clockrate; +extern U32 const os_timernum; +extern U16 const mp_tcb_size; +extern U32 const mp_stk_size; +extern U32 const *m_tmr; +extern U16 const mp_tmr_size; +extern U8 const os_fifo_size; + +/* Functions */ +extern void os_idle_demon (void); +extern int os_tick_init (void); +extern void os_tick_irqack (void); +extern void os_tmr_call (U16 info); +extern void os_error (U32 err_code); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx_ca/cmsis_os.h b/libraries/rtos/rtx_ca/cmsis_os.h new file mode 100644 index 0000000000..acb31333dc --- /dev/null +++ b/libraries/rtos/rtx_ca/cmsis_os.h @@ -0,0 +1,803 @@ +/* ---------------------------------------------------------------------- + * $Date: 5. June 2012 + * $Revision: V1.01 + * + * Project: CMSIS-RTOS API + * Title: cmsis_os.h RTX header file + * + * Version 0.02 + * Initial Proposal Phase + * Version 0.03 + * osKernelStart added, optional feature: main started as thread + * osSemaphores have standard behavior + * osTimerCreate does not start the timer, added osTimerStart + * osThreadPass is renamed to osThreadYield + * Version 1.01 + * Support for C++ interface + * - const attribute removed from the osXxxxDef_t typedef's + * - const attribute added to the osXxxxDef macros + * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete + * Added: osKernelInitialize + *---------------------------------------------------------------------------- + * + * Copyright (c) 2012 ARM LIMITED + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/** +\page cmsis_os_h Header File Template: cmsis_os.h + +The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS). +Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents +its implementation. + +The file cmsis_os.h contains: + - CMSIS-RTOS API function definitions + - struct definitions for parameters and return types + - status and priority values used by CMSIS-RTOS API functions + - macros for defining threads and other kernel objects + + +Name conventions and header file modifications + +All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions. +Definitions that are prefixed \b os_ are not used in the application code but local to this header file. +All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread. + +Definitions that are marked with CAN BE CHANGED can be adapted towards the needs of the actual CMSIS-RTOS implementation. +These definitions can be specific to the underlying RTOS kernel. + +Definitions that are marked with MUST REMAIN UNCHANGED cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer +compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation. + + +Function calls from interrupt service routines + +The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR): + - \ref osSignalSet + - \ref osSemaphoreRelease + - \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree + - \ref osMessagePut, \ref osMessageGet + - \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree + +Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called +from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector. + +Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time. +If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive. + + +Define and reference object definitions + +With \#define osObjectsExternal objects are defined as external symbols. This allows to create a consistent header file +that is used throughout a project as shown below: + +Header File +\code +#include // CMSIS RTOS header file + +// Thread definition +extern void thread_sample (void const *argument); // function prototype +osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100); + +// Pool definition +osPoolDef(MyPool, 10, long); +\endcode + + +This header file defines all objects when included in a C/C++ source file. When \#define osObjectsExternal is +present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be +used throughout the whole project. + +Example +\code +#include "osObjects.h" // Definition of the CMSIS-RTOS objects +\endcode + +\code +#define osObjectExternal // Objects will be defined as external symbols +#include "osObjects.h" // Reference to the CMSIS-RTOS objects +\endcode + +*/ + +#ifndef _CMSIS_OS_H +#define _CMSIS_OS_H + +/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version. +#define osCMSIS 0x10001 ///< API version (main [31:16] .sub [15:0]) + +/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number. +#define osCMSIS_RTX ((4<<16)|61) ///< RTOS identification and version (main [31:16] .sub [15:0]) + +/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS. +#define osKernelSystemId "RTX V4.61" ///< RTOS identification string + +#define CMSIS_OS_RTX +#define CMSIS_OS_RTX_CA /* new define for Coretex-A */ + +// The stack space occupied is mainly dependent on the underling C standard library +#if defined(TOOLCHAIN_GCC) || defined(TOOLCHAIN_ARM_STD) +# define WORDS_STACK_SIZE 512 +#elif defined(TOOLCHAIN_ARM_MICRO) +# define WORDS_STACK_SIZE 128 +#endif + +#define DEFAULT_STACK_SIZE (WORDS_STACK_SIZE*4) + +/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS. +#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available +#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available +#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available +#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available +#define osFeature_Signals 16 ///< maximum number of Signal Flags available per thread +#define osFeature_Semaphore 65535 ///< maximum count for \ref osSemaphoreCreate function +#define osFeature_Wait 0 ///< osWait function: 1=available, 0=not available + +#if defined (__CC_ARM) +#define os_InRegs __value_in_regs // Compiler specific: force struct in registers +#else +#define os_InRegs +#endif + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + + +// ==== Enumeration, structures, defines ==== + +/// Priority used for thread control. +/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS. +typedef enum { + osPriorityIdle = -3, ///< priority: idle (lowest) + osPriorityLow = -2, ///< priority: low + osPriorityBelowNormal = -1, ///< priority: below normal + osPriorityNormal = 0, ///< priority: normal (default) + osPriorityAboveNormal = +1, ///< priority: above normal + osPriorityHigh = +2, ///< priority: high + osPriorityRealtime = +3, ///< priority: realtime (highest) + osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority +} osPriority; + +/// Timeout value. +/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS. +#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value + +/// Status code values returned by CMSIS-RTOS functions. +/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS. +typedef enum { + osOK = 0, ///< function completed; no error or event occurred. + osEventSignal = 0x08, ///< function completed; signal event occurred. + osEventMessage = 0x10, ///< function completed; message event occurred. + osEventMail = 0x20, ///< function completed; mail event occurred. + osEventTimeout = 0x40, ///< function completed; timeout occurred. + osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object. + osErrorResource = 0x81, ///< resource not available: a specified resource was not available. + osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period. + osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines. + osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object. + osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority. + osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation. + osErrorValue = 0x86, ///< value of a parameter is out of range. + osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits. + os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization. +} osStatus; + + +/// Timer type value for the timer definition. +/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS. +typedef enum { + osTimerOnce = 0, ///< one-shot timer + osTimerPeriodic = 1 ///< repeating timer +} os_timer_type; + +/// Entry point of a thread. +/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS. +typedef void (*os_pthread) (void const *argument); + +/// Entry point of a timer call back function. +/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS. +typedef void (*os_ptimer) (void const *argument); + +// >>> the following data type definitions may shall adapted towards a specific RTOS + +/// Thread ID identifies the thread (pointer to a thread control block). +/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_cb *osThreadId; + +/// Timer ID identifies the timer (pointer to a timer control block). +/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_cb *osTimerId; + +/// Mutex ID identifies the mutex (pointer to a mutex control block). +/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_cb *osMutexId; + +/// Semaphore ID identifies the semaphore (pointer to a semaphore control block). +/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_cb *osSemaphoreId; + +/// Pool ID identifies the memory pool (pointer to a memory pool control block). +/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_cb *osPoolId; + +/// Message ID identifies the message queue (pointer to a message queue control block). +/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_cb *osMessageQId; + +/// Mail ID identifies the mail queue (pointer to a mail queue control block). +/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_cb *osMailQId; + + +/// Thread Definition structure contains startup information of a thread. +/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS. +typedef struct os_thread_def { + os_pthread pthread; ///< start address of thread function + osPriority tpriority; ///< initial thread priority + uint32_t instances; ///< maximum number of instances of that thread function + uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size +} osThreadDef_t; + +/// Timer Definition structure contains timer parameters. +/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS. +typedef struct os_timer_def { + os_ptimer ptimer; ///< start address of a timer function + void *timer; ///< pointer to internal data +} osTimerDef_t; + +/// Mutex Definition structure contains setup information for a mutex. +/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mutex_def { + void *mutex; ///< pointer to internal data +} osMutexDef_t; + +/// Semaphore Definition structure contains setup information for a semaphore. +/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS. +typedef struct os_semaphore_def { + void *semaphore; ///< pointer to internal data +} osSemaphoreDef_t; + +/// Definition structure for memory block allocation. +/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS. +typedef struct os_pool_def { + uint32_t pool_sz; ///< number of items (elements) in the pool + uint32_t item_sz; ///< size of an item + void *pool; ///< pointer to memory for pool +} osPoolDef_t; + +/// Definition structure for message queue. +/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_messageQ_def { + uint32_t queue_sz; ///< number of elements in the queue + void *pool; ///< memory array for messages +} osMessageQDef_t; + +/// Definition structure for mail queue. +/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS. +typedef struct os_mailQ_def { + uint32_t queue_sz; ///< number of elements in the queue + uint32_t item_sz; ///< size of an item + void *pool; ///< memory array for mail +} osMailQDef_t; + +/// Event structure contains detailed information about an event. +/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS. +/// However the struct may be extended at the end. +typedef struct { + osStatus status; ///< status code: event or error information + union { + uint32_t v; ///< message as 32-bit value + void *p; ///< message or mail as void pointer + int32_t signals; ///< signal flags + } value; ///< event value + union { + osMailQId mail_id; ///< mail id obtained by \ref osMailCreate + osMessageQId message_id; ///< message id obtained by \ref osMessageCreate + } def; ///< event definition +} osEvent; + + +// ==== Kernel Control Functions ==== + +/// Initialize the RTOS Kernel for creating objects. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS. +osStatus osKernelInitialize (void); + +/// Start the RTOS Kernel. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS. +osStatus osKernelStart (void); + +/// Check if the RTOS kernel is already started. +/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS. +/// \return 0 RTOS is not started, 1 RTOS is started. +int32_t osKernelRunning(void); + + +// ==== Thread Management ==== + +/// Create a Thread Definition with function, priority, and stack requirements. +/// \param name name of the thread function. +/// \param priority initial priority of the thread function. +/// \param instances number of possible thread instances. +/// \param stacksz stack size (in bytes) requirements for the thread function. +/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osThreadDef(name, priority, instances, stacksz) \ +extern const osThreadDef_t os_thread_def_##name +#else // define the object +#if defined (__MBED_CMSIS_RTOS_CA9) +#define osThreadDef(name, priority, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), 1, (stacksz) } +#else +#define osThreadDef(name, priority, instances, stacksz) \ +const osThreadDef_t os_thread_def_##name = \ +{ (name), (priority), (instances), (stacksz) } +#endif +#endif + +/// Access a Thread definition. +/// \param name name of the thread definition object. +/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osThread(name) \ +&os_thread_def_##name + +/// Create a thread and add it to Active Threads and set it to state READY. +/// \param[in] thread_def thread definition referenced with \ref osThread. +/// \param[in] argument pointer that is passed to the thread function as start argument. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS. +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument); + +/// Return the thread ID of the current running thread. +/// \return thread ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS. +osThreadId osThreadGetId (void); + +/// Terminate execution of a thread and remove it from Active Threads. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS. +osStatus osThreadTerminate (osThreadId thread_id); + +/// Pass control to next thread that is in state \b READY. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS. +osStatus osThreadYield (void); + +/// Change priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] priority new priority value for the thread function. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS. +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority); + +/// Get current priority of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return current priority value of the thread function. +/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS. +osPriority osThreadGetPriority (osThreadId thread_id); + +#ifdef __MBED_CMSIS_RTOS_CA9 +/// Get current thread state. +uint8_t osThreadGetState (osThreadId thread_id); +#endif + +// ==== Generic Wait Functions ==== + +/// Wait for Timeout (Time Delay). +/// \param[in] millisec time delay value +/// \return status code that indicates the execution status of the function. +osStatus osDelay (uint32_t millisec); + +#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available + +/// Wait for Signal, Message, Mail, or Timeout. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains signal, message, or mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS. +os_InRegs osEvent osWait (uint32_t millisec); + +#endif // Generic Wait available + + +// ==== Timer Management Functions ==== +/// Define a Timer object. +/// \param name name of the timer object. +/// \param function name of the timer call back function. +/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osTimerDef(name, function) \ +extern const osTimerDef_t os_timer_def_##name +#else // define the object +#define osTimerDef(name, function) \ +uint32_t os_timer_cb_##name[5]; \ +const osTimerDef_t os_timer_def_##name = \ +{ (function), (os_timer_cb_##name) } +#endif + +/// Access a Timer definition. +/// \param name name of the timer object. +/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osTimer(name) \ +&os_timer_def_##name + +/// Create a timer. +/// \param[in] timer_def timer object referenced with \ref osTimer. +/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior. +/// \param[in] argument argument to the timer call back function. +/// \return timer ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS. +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument); + +/// Start or restart a timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \param[in] millisec time delay value of the timer. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS. +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec); + +/// Stop the timer. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS. +osStatus osTimerStop (osTimerId timer_id); + +/// Delete a timer that was created by \ref osTimerCreate. +/// \param[in] timer_id timer ID obtained by \ref osTimerCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS. +osStatus osTimerDelete (osTimerId timer_id); + + +// ==== Signal Management ==== + +/// Set the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that should be set. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS. +int32_t osSignalSet (osThreadId thread_id, int32_t signals); + +/// Clear the specified Signal Flags of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \param[in] signals specifies the signal flags of the thread that shall be cleared. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS. +int32_t osSignalClear (osThreadId thread_id, int32_t signals); + +/// Get Signal Flags status of an active thread. +/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId. +/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSignalGet shall be consistent in every CMSIS-RTOS. +int32_t osSignalGet (osThreadId thread_id); + +/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread. +/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event flag information or error code. +/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS. +os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec); + + +// ==== Mutex Management ==== + +/// Define a Mutex. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMutexDef(name) \ +extern const osMutexDef_t os_mutex_def_##name +#else // define the object +#define osMutexDef(name) \ +uint32_t os_mutex_cb_##name[3]; \ +const osMutexDef_t os_mutex_def_##name = { (os_mutex_cb_##name) } +#endif + +/// Access a Mutex definition. +/// \param name name of the mutex object. +/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMutex(name) \ +&os_mutex_def_##name + +/// Create and Initialize a Mutex object. +/// \param[in] mutex_def mutex definition referenced with \ref osMutex. +/// \return mutex ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS. +osMutexId osMutexCreate (const osMutexDef_t *mutex_def); + +/// Wait until a Mutex becomes available. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS. +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec); + +/// Release a Mutex that was obtained by \ref osMutexWait. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS. +osStatus osMutexRelease (osMutexId mutex_id); + +/// Delete a Mutex that was created by \ref osMutexCreate. +/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS. +osStatus osMutexDelete (osMutexId mutex_id); + + +// ==== Semaphore Management Functions ==== + +#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available + +/// Define a Semaphore object. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osSemaphoreDef(name) \ +extern const osSemaphoreDef_t os_semaphore_def_##name +#else // define the object +#define osSemaphoreDef(name) \ +uint32_t os_semaphore_cb_##name[2]; \ +const osSemaphoreDef_t os_semaphore_def_##name = { (os_semaphore_cb_##name) } +#endif + +/// Access a Semaphore definition. +/// \param name name of the semaphore object. +/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osSemaphore(name) \ +&os_semaphore_def_##name + +/// Create and Initialize a Semaphore object used for managing resources. +/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore. +/// \param[in] count number of available resources. +/// \return semaphore ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS. +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count); + +/// Wait until a Semaphore token becomes available. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return number of available tokens, or -1 in case of incorrect parameters. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS. +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec); + +/// Release a Semaphore token. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id); + +/// Delete a Semaphore that was created by \ref osSemaphoreCreate. +/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS. +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id); + +#endif // Semaphore available + + +// ==== Memory Pool Management Functions ==== + +#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available + +/// \brief Define a Memory Pool. +/// \param name name of the memory pool. +/// \param no maximum number of blocks (objects) in the memory pool. +/// \param type data type of a single block (object). +/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osPoolDef(name, no, type) \ +extern const osPoolDef_t os_pool_def_##name +#else // define the object +#define osPoolDef(name, no, type) \ +uint32_t os_pool_m_##name[3+((sizeof(type)+3)/4)*(no)]; \ +const osPoolDef_t os_pool_def_##name = \ +{ (no), sizeof(type), (os_pool_m_##name) } +#endif + +/// \brief Access a Memory Pool definition. +/// \param name name of the memory pool +/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osPool(name) \ +&os_pool_def_##name + +/// Create and Initialize a memory pool. +/// \param[in] pool_def memory pool definition referenced with \ref osPool. +/// \return memory pool ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS. +osPoolId osPoolCreate (const osPoolDef_t *pool_def); + +/// Allocate a memory block from a memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolAlloc (osPoolId pool_id); + +/// Allocate a memory block from a memory pool and set memory block to zero. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \return address of the allocated memory block or NULL in case of no memory available. +/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS. +void *osPoolCAlloc (osPoolId pool_id); + +/// Return an allocated memory block back to a specific memory pool. +/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate. +/// \param[in] block address of the allocated memory block that is returned to the memory pool. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS. +osStatus osPoolFree (osPoolId pool_id, void *block); + +#endif // Memory Pool Management available + + +// ==== Message Queue Management Functions ==== + +#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available + +/// \brief Create a Message Queue Definition. +/// \param name name of the queue. +/// \param queue_sz maximum number of messages in the queue. +/// \param type data type of a single message element (for debugger). +/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMessageQDef(name, queue_sz, type) \ +extern const osMessageQDef_t os_messageQ_def_##name +#else // define the object +#define osMessageQDef(name, queue_sz, type) \ +uint32_t os_messageQ_q_##name[4+(queue_sz)]; \ +const osMessageQDef_t os_messageQ_def_##name = \ +{ (queue_sz), (os_messageQ_q_##name) } +#endif + +/// \brief Access a Message Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMessageQ(name) \ +&os_messageQ_def_##name + +/// Create and Initialize a Message Queue. +/// \param[in] queue_def queue definition referenced with \ref osMessageQ. +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return message queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS. +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +/// Put a Message to a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] info message information. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS. +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Get a Message or Wait for a Message from a Queue. +/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out. +/// \return event information that includes status code. +/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS. +os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec); + +#endif // Message Queues available + + +// ==== Mail Queue Management Functions ==== + +#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available + +/// \brief Create a Mail Queue Definition. +/// \param name name of the queue +/// \param queue_sz maximum number of messages in queue +/// \param type data type of a single message element +/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#if defined (osObjectsExternal) // object is external +#define osMailQDef(name, queue_sz, type) \ +extern const osMailQDef_t os_mailQ_def_##name +#else // define the object +#define osMailQDef(name, queue_sz, type) \ +uint32_t os_mailQ_q_##name[4+(queue_sz)]; \ +uint32_t os_mailQ_m_##name[3+((sizeof(type)+3)/4)*(queue_sz)]; \ +void * os_mailQ_p_##name[2] = { (os_mailQ_q_##name), os_mailQ_m_##name }; \ +const osMailQDef_t os_mailQ_def_##name = \ +{ (queue_sz), sizeof(type), (os_mailQ_p_##name) } +#endif + +/// \brief Access a Mail Queue Definition. +/// \param name name of the queue +/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the +/// macro body is implementation specific in every CMSIS-RTOS. +#define osMailQ(name) \ +&os_mailQ_def_##name + +/// Create and Initialize mail queue. +/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ +/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL. +/// \return mail queue ID for reference by other functions or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS. +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id); + +/// Allocate a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS. +void *osMailAlloc (osMailQId queue_id, uint32_t millisec); + +/// Allocate a memory block from a mail and set memory block to zero. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return pointer to memory block that can be filled with mail or NULL in case of error. +/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS. +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec); + +/// Put a mail to a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS. +osStatus osMailPut (osMailQId queue_id, void *mail); + +/// Get a mail from a queue. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] millisec timeout value or 0 in case of no time-out +/// \return event that contains mail information or error code. +/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS. +os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec); + +/// Free a memory block from a mail. +/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate. +/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet. +/// \return status code that indicates the execution status of the function. +/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS. +osStatus osMailFree (osMailQId queue_id, void *mail); + +#endif // Mail Queues available + + +#ifdef __cplusplus +} +#endif + +#endif // _CMSIS_OS_H diff --git a/libraries/rtos/rtx_ca/rt_CMSIS.c b/libraries/rtos/rtx_ca/rt_CMSIS.c new file mode 100644 index 0000000000..00ce2c8563 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_CMSIS.c @@ -0,0 +1,1978 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: rt_CMSIS.c + * Purpose: CMSIS RTOS API + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#define __CMSIS_GENERIC + +#if defined (__CORTEX_M4) || defined (__CORTEX_M4F) + #include "core_cm4.h" +#elif defined (__CORTEX_M3) + #include "core_cm3.h" +#elif defined (__CORTEX_M0) + #include "core_cm0.h" +#elif defined (__CORTEX_A9) + #include "core_ca9.h" +#else + #error "Missing __CORTEX_xx definition" +#endif + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_System.h" +#include "rt_Task.h" +#include "rt_Event.h" +#include "rt_List.h" +#include "rt_Time.h" +#include "rt_Mutex.h" +#include "rt_Semaphore.h" +#include "rt_Mailbox.h" +#include "rt_MemBox.h" +#include "rt_Memory.h" +#include "rt_HAL_CM.h" + +#define os_thread_cb OS_TCB + +#include "cmsis_os.h" + +#if (osFeature_Signals != 16) +#error Invalid "osFeature_Signals" value! +#endif +#if (osFeature_Semaphore > 65535) +#error Invalid "osFeature_Semaphore" value! +#endif +#if (osFeature_Wait != 0) +#error osWait not supported! +#endif + + +// ==== Enumeration, structures, defines ==== + +// Service Calls defines + +#if defined (__CC_ARM) /* ARM Compiler */ + +#define __NO_RETURN __declspec(noreturn) + +#define osEvent_type osEvent +#define osEvent_ret_status ret +#define osEvent_ret_value ret +#define osEvent_ret_msg ret +#define osEvent_ret_mail ret + +#define osCallback_type osCallback +#define osCallback_ret ret + +#define SVC_0_1(f,t,...) \ +__svc_indirect(0) t _##f (t(*)()); \ + t f (void); \ +__attribute__((always_inline)) \ +static __inline t __##f (void) { \ + return _##f(f); \ +} + +#define SVC_1_1(f,t,t1,...) \ +__svc_indirect(0) t _##f (t(*)(t1),t1); \ + t f (t1 a1); \ +__attribute__((always_inline)) \ +static __inline t __##f (t1 a1) { \ + return _##f(f,a1); \ +} + +#define SVC_2_1(f,t,t1,t2,...) \ +__svc_indirect(0) t _##f (t(*)(t1,t2),t1,t2); \ + t f (t1 a1, t2 a2); \ +__attribute__((always_inline)) \ +static __inline t __##f (t1 a1, t2 a2) { \ + return _##f(f,a1,a2); \ +} + +#define SVC_3_1(f,t,t1,t2,t3,...) \ +__svc_indirect(0) t _##f (t(*)(t1,t2,t3),t1,t2,t3); \ + t f (t1 a1, t2 a2, t3 a3); \ +__attribute__((always_inline)) \ +static __inline t __##f (t1 a1, t2 a2, t3 a3) { \ + return _##f(f,a1,a2,a3); \ +} + +#define SVC_4_1(f,t,t1,t2,t3,t4,...) \ +__svc_indirect(0) t _##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \ + t f (t1 a1, t2 a2, t3 a3, t4 a4); \ +__attribute__((always_inline)) \ +static __inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + return _##f(f,a1,a2,a3,a4); \ +} + +#define SVC_1_2 SVC_1_1 +#define SVC_1_3 SVC_1_1 +#define SVC_2_3 SVC_2_1 + +#elif defined (__GNUC__) /* GNU Compiler */ + +#define __NO_RETURN __attribute__((noreturn)) + +typedef uint32_t __attribute__((vector_size(8))) ret64; +typedef uint32_t __attribute__((vector_size(16))) ret128; + +#define RET_pointer __r0 +#define RET_int32_t __r0 +#define RET_osStatus __r0 +#define RET_osPriority __r0 +#define RET_osEvent {(osStatus)__r0, {(uint32_t)__r1}, {(void *)__r2}} +#define RET_osCallback {(void *)__r0, (void *)__r1} + +#define osEvent_type ret128 +#define osEvent_ret_status (ret128){ret.status} +#define osEvent_ret_value (ret128){ret.status, ret.value.v} +#define osEvent_ret_msg (ret128){ret.status, ret.value.v, (uint32_t)ret.def.message_id} +#define osEvent_ret_mail (ret128){ret.status, ret.value.v, (uint32_t)ret.def.mail_id} + +#define osCallback_type ret64 +#define osCallback_ret (ret64) {(uint32_t)ret.fp, (uint32_t)ret.arg} + +#define SVC_ArgN(n) \ + register int __r##n __asm("r"#n); + +#define SVC_ArgR(n,t,a) \ + register t __r##n __asm("r"#n) = a; + +#define SVC_Arg0() \ + SVC_ArgN(0) \ + SVC_ArgN(1) \ + SVC_ArgN(2) \ + SVC_ArgN(3) + +#define SVC_Arg1(t1) \ + SVC_ArgR(0,t1,a1) \ + SVC_ArgN(1) \ + SVC_ArgN(2) \ + SVC_ArgN(3) + +#define SVC_Arg2(t1,t2) \ + SVC_ArgR(0,t1,a1) \ + SVC_ArgR(1,t2,a2) \ + SVC_ArgN(2) \ + SVC_ArgN(3) + +#define SVC_Arg3(t1,t2,t3) \ + SVC_ArgR(0,t1,a1) \ + SVC_ArgR(1,t2,a2) \ + SVC_ArgR(2,t3,a3) \ + SVC_ArgN(3) + +#define SVC_Arg4(t1,t2,t3,t4) \ + SVC_ArgR(0,t1,a1) \ + SVC_ArgR(1,t2,a2) \ + SVC_ArgR(2,t3,a3) \ + SVC_ArgR(3,t4,a4) + +#if (defined (__CORTEX_M0)) +#define SVC_Call(f) \ + __asm volatile \ + ( \ + "ldr r7,="#f"\n\t" \ + "mov r12,r7\n\t" \ + "svc 0" \ + : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \ + : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \ + : "r7", "r12", "lr", "cc" \ + ); +#else +#define SVC_Call(f) \ + __asm volatile \ + ( \ + "ldr r12,="#f"\n\t" \ + "svc 0" \ + : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \ + : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \ + : "r12", "lr", "cc" \ + ); +#endif + +#define SVC_0_1(f,t,rv) \ +__attribute__((always_inline)) \ +static inline t __##f (void) { \ + SVC_Arg0(); \ + SVC_Call(f); \ + return (t) rv; \ +} + +#define SVC_1_1(f,t,t1,rv) \ +__attribute__((always_inline)) \ +static inline t __##f (t1 a1) { \ + SVC_Arg1(t1); \ + SVC_Call(f); \ + return (t) rv; \ +} + +#define SVC_2_1(f,t,t1,t2,rv) \ +__attribute__((always_inline)) \ +static inline t __##f (t1 a1, t2 a2) { \ + SVC_Arg2(t1,t2); \ + SVC_Call(f); \ + return (t) rv; \ +} + +#define SVC_3_1(f,t,t1,t2,t3,rv) \ +__attribute__((always_inline)) \ +static inline t __##f (t1 a1, t2 a2, t3 a3) { \ + SVC_Arg3(t1,t2,t3); \ + SVC_Call(f); \ + return (t) rv; \ +} + +#define SVC_4_1(f,t,t1,t2,t3,t4,rv) \ +__attribute__((always_inline)) \ +static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_Arg4(t1,t2,t3,t4); \ + SVC_Call(f); \ + return (t) rv; \ +} + +#define SVC_1_2 SVC_1_1 +#define SVC_1_3 SVC_1_1 +#define SVC_2_3 SVC_2_1 + +#elif defined (__ICCARM__) /* IAR Compiler */ + +#define __NO_RETURN __noreturn + +#define RET_osEvent "=r"(ret.status), "=r"(ret.value), "=r"(ret.def) +#define RET_osCallback "=r"(ret.fp), "=r"(ret.arg) + +#define osEvent_type osEvent +#define osEvent_ret_status ret +#define osEvent_ret_value ret +#define osEvent_ret_msg ret +#define osEvent_ret_mail ret + +#define osCallback_type uint64_t +#define osCallback_ret ((uint64_t)ret.fp | ((uint64_t)ret.arg)<<32) + +#define SVC_Setup(f) \ + __asm( \ + "mov r12,%0\n" \ + :: "r"(&f): "r12" \ + ); + +#define SVC_Ret3() \ + __asm( \ + "ldr r0,[sp,#0]\n" \ + "ldr r1,[sp,#4]\n" \ + "ldr r2,[sp,#8]\n" \ + ); + +#define SVC_0_1(f,t,...) \ +t f (void); \ +_Pragma("swi_number=0") __swi t _##f (void); \ +static inline t __##f (void) { \ + SVC_Setup(f); \ + return _##f(); \ +} + +#define SVC_1_1(f,t,t1,...) \ +t f (t1 a1); \ +_Pragma("swi_number=0") __swi t _##f (t1 a1); \ +static inline t __##f (t1 a1) { \ + SVC_Setup(f); \ + return _##f(a1); \ +} + +#define SVC_2_1(f,t,t1,t2,...) \ +t f (t1 a1, t2 a2); \ +_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2); \ +static inline t __##f (t1 a1, t2 a2) { \ + SVC_Setup(f); \ + return _##f(a1,a2); \ +} + +#define SVC_3_1(f,t,t1,t2,t3,...) \ +t f (t1 a1, t2 a2, t3 a3); \ +_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3); \ +static inline t __##f (t1 a1, t2 a2, t3 a3) { \ + SVC_Setup(f); \ + return _##f(a1,a2,a3); \ +} + +#define SVC_4_1(f,t,t1,t2,t3,t4,...) \ +t f (t1 a1, t2 a2, t3 a3, t4 a4); \ +_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3, t4 a4); \ +static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \ + SVC_Setup(f); \ + return _##f(a1,a2,a3,a4); \ +} + +#define SVC_1_2(f,t,t1,rr) \ +uint64_t f (t1 a1); \ +_Pragma("swi_number=0") __swi uint64_t _##f (t1 a1); \ +static inline t __##f (t1 a1) { \ + t ret; \ + SVC_Setup(f); \ + _##f(a1); \ + __asm("" : rr : :); \ + return ret; \ +} + +#define SVC_1_3(f,t,t1,rr) \ +t f (t1 a1); \ +void f##_ (t1 a1) { \ + f(a1); \ + SVC_Ret3(); \ +} \ +_Pragma("swi_number=0") __swi void _##f (t1 a1); \ +static inline t __##f (t1 a1) { \ + t ret; \ + SVC_Setup(f##_); \ + _##f(a1); \ + __asm("" : rr : :); \ + return ret; \ +} + +#define SVC_2_3(f,t,t1,t2,rr) \ +t f (t1 a1, t2 a2); \ +void f##_ (t1 a1, t2 a2) { \ + f(a1,a2); \ + SVC_Ret3(); \ +} \ +_Pragma("swi_number=0") __swi void _##f (t1 a1, t2 a2); \ +static inline t __##f (t1 a1, t2 a2) { \ + t ret; \ + SVC_Setup(f##_); \ + _##f(a1,a2); \ + __asm("" : rr : :); \ + return ret; \ +} + +#endif + + +// Callback structure +typedef struct { + void *fp; // Function pointer + void *arg; // Function argument +} osCallback; + + +// OS Section definitions +#ifdef OS_SECTIONS_LINK_INFO +extern const uint32_t os_section_id$$Base; +extern const uint32_t os_section_id$$Limit; +#endif + +// OS Stack Memory for Threads definitions +extern uint64_t os_stack_mem[]; +extern const uint32_t os_stack_sz; + +// OS Timers external resources +extern const osThreadDef_t os_thread_def_osTimerThread; +extern osThreadId osThreadId_osTimerThread; +extern const osMessageQDef_t os_messageQ_def_osTimerMessageQ; +extern osMessageQId osMessageQId_osTimerMessageQ; + +extern U32 IRQNestLevel; /* Indicates whether inside an ISR, and the depth of nesting. 0 = not in ISR. */ + + +// ==== Helper Functions ==== + +/// Convert timeout in millisec to system ticks +static uint32_t rt_ms2tick (uint32_t millisec) { + uint32_t tick; + + if (millisec == osWaitForever) return 0xFFFF; // Indefinite timeout + if (millisec > 4000000) return 0xFFFE; // Max ticks supported + + tick = ((1000 * millisec) + os_clockrate - 1) / os_clockrate; + if (tick > 0xFFFE) return 0xFFFE; + + return tick; +} + +/// Convert Thread ID to TCB pointer +static P_TCB rt_tid2ptcb (osThreadId thread_id) { + P_TCB ptcb; + + if (thread_id == NULL) return NULL; + + if ((uint32_t)thread_id & 3) return NULL; + +#ifdef OS_SECTIONS_LINK_INFO + if ((os_section_id$$Base != 0) && (os_section_id$$Limit != 0)) { + if (thread_id < (osThreadId)os_section_id$$Base) return NULL; + if (thread_id >= (osThreadId)os_section_id$$Limit) return NULL; + } +#endif + + ptcb = thread_id; + + if (ptcb->cb_type != TCB) return NULL; + + return ptcb; +} + +/// Convert ID pointer to Object pointer +static void *rt_id2obj (void *id) { + + if ((uint32_t)id & 3) return NULL; + +#ifdef OS_SECTIONS_LINK_INFO + if ((os_section_id$$Base != 0) && (os_section_id$$Limit != 0)) { + if (id < (void *)os_section_id$$Base) return NULL; + if (id >= (void *)os_section_id$$Limit) return NULL; + } +#endif + + return id; +} + +// === Helper functions for system call interface === + +static __inline char __get_mode(void) { + return (char)(__get_CPSR() & 0x1f); +} + +static __inline char __exceptional_mode(void) { + switch(__get_mode()) { + case MODE_USR: + case MODE_SYS: + return 0; + case MODE_SVC: + if (IRQNestLevel == 0) + return 0; /* handling a regular service call */ + else + return 1; /* handling an ISR in SVC mode */ + default: + return 1; + } +} + +// ==== Kernel Control ==== + +uint8_t os_initialized; // Kernel Initialized flag +uint8_t os_running; // Kernel Running flag + +// Kernel Control Service Calls declarations +SVC_0_1(svcKernelInitialize, osStatus, RET_osStatus) +SVC_0_1(svcKernelStart, osStatus, RET_osStatus) +SVC_0_1(svcKernelRunning, int32_t, RET_int32_t) + +static void sysThreadError (osStatus status); +osThreadId svcThreadCreate (const osThreadDef_t *thread_def, void *argument); +osMessageQId svcMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id); + +// Kernel Control Service Calls + +/// Initialize the RTOS Kernel for creating objects +osStatus svcKernelInitialize (void) { + int ret; + + if (!os_initialized) { + + // Init Thread Stack Memory (must be 8-byte aligned) + if ((uint32_t)os_stack_mem & 7) return osErrorNoMemory; + ret = rt_init_mem(os_stack_mem, os_stack_sz); + if (ret != 0) return osErrorNoMemory; + + rt_sys_init(); // RTX System Initialization + } + + os_tsk.run->prio = 255; // Highest priority + + if (!os_initialized) { + // Create OS Timers resources (Message Queue & Thread) + osMessageQId_osTimerMessageQ = svcMessageCreate (&os_messageQ_def_osTimerMessageQ, NULL); + osThreadId_osTimerThread = svcThreadCreate(&os_thread_def_osTimerThread, NULL); + } + + sysThreadError(osOK); + + os_initialized = 1; + + return osOK; +} + +/// Start the RTOS Kernel +osStatus svcKernelStart (void) { + + if (os_running) return osOK; + + rt_tsk_prio(0, 0); // Lowest priority + __set_PSP(os_tsk.run->tsk_stack + 8*4); // New context + os_tsk.run = NULL; // Force context switch + + rt_sys_start(); + + os_running = 1; + + return osOK; +} + +/// Check if the RTOS kernel is already started +int32_t svcKernelRunning(void) { + return os_running; +} + +// Kernel Control Public API + +/// Initialize the RTOS Kernel for creating objects +osStatus osKernelInitialize (void) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + if (__get_mode() != MODE_USR) { + return svcKernelInitialize(); + } else { + return __svcKernelInitialize(); + } +} + +/// Start the RTOS Kernel +osStatus osKernelStart (void) { + char mode = __get_mode(); + + switch(mode) { + case MODE_USR: + if (os_flags & 1) return osErrorOS; // Privileged Thread mode requested from Unprivileged + break; + case MODE_SYS: + if (!(os_flags & 1)) { + __set_CPS_USR(); + } + break; + default: + return osErrorISR; // Not allowed in ISR + } + return __svcKernelStart(); +} + +/// Check if the RTOS kernel is already started +int32_t osKernelRunning(void) { + if(__get_mode() != MODE_USR) { + return os_running; + } else { + return __svcKernelRunning(); + } +} + + +// ==== Thread Management ==== + +/// Set Thread Error (for Create functions which return IDs) +static void sysThreadError (osStatus status) { + // To Do +} + +__NO_RETURN void osThreadExit (void); + +// Thread Service Calls declarations +SVC_2_1(svcThreadCreate, osThreadId, const osThreadDef_t *, void *, RET_pointer) +SVC_0_1(svcThreadGetId, osThreadId, RET_pointer) +SVC_1_1(svcThreadTerminate, osStatus, osThreadId, RET_osStatus) +SVC_0_1(svcThreadYield, osStatus, RET_osStatus) +SVC_2_1(svcThreadSetPriority, osStatus, osThreadId, osPriority, RET_osStatus) +SVC_1_1(svcThreadGetPriority, osPriority, osThreadId, RET_osPriority) + +// Thread Service Calls + +/// Create a thread and add it to Active Threads and set it to state READY +osThreadId svcThreadCreate (const osThreadDef_t *thread_def, void *argument) { + P_TCB ptcb; + OS_TID tsk; + void *stk; + + if ((thread_def == NULL) || + (thread_def->pthread == NULL) || + (thread_def->tpriority < osPriorityIdle) || + (thread_def->tpriority > osPriorityRealtime)) { + sysThreadError(osErrorParameter); + return NULL; + } + + if (thread_def->stacksize != 0) { // Custom stack size + stk = rt_alloc_mem( // Allocate stack + os_stack_mem, + thread_def->stacksize + ); + if (stk == NULL) { + sysThreadError(osErrorNoMemory); // Out of memory + return NULL; + } + } else { // Default stack size + stk = NULL; + } + + tsk = rt_tsk_create( // Create task + (FUNCP)thread_def->pthread, // Task function pointer + (thread_def->tpriority-osPriorityIdle+1) | // Task priority + (thread_def->stacksize << 8), // Task stack size in bytes + stk, // Pointer to task's stack + argument // Argument to the task + ); + + if (tsk == 0) { // Invalid task ID + if (stk != NULL) { + rt_free_mem(os_stack_mem, stk); // Free allocated stack + } + sysThreadError(osErrorNoMemory); // Create task failed (Out of memory) + return NULL; + } + + ptcb = (P_TCB)os_active_TCB[tsk - 1]; // TCB pointer + + *((uint32_t *)ptcb->tsk_stack + 13) = (uint32_t)osThreadExit; + + return ptcb; +} + +/// Return the thread ID of the current running thread +osThreadId svcThreadGetId (void) { + OS_TID tsk; + + tsk = rt_tsk_self(); + if (tsk == 0) return NULL; + return (P_TCB)os_active_TCB[tsk - 1]; +} + +/// Terminate execution of a thread and remove it from ActiveThreads +osStatus svcThreadTerminate (osThreadId thread_id) { + OS_RESULT res; + P_TCB ptcb; + void *stk; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return osErrorParameter; + + stk = ptcb->priv_stack ? ptcb->stack : NULL; // Private stack + + res = rt_tsk_delete(ptcb->task_id); // Delete task + + if (res == OS_R_NOK) return osErrorResource; // Delete task failed + + if (stk != NULL) { + rt_free_mem(os_stack_mem, stk); // Free private stack + } + + return osOK; +} + +/// Pass control to next thread that is in state READY +osStatus svcThreadYield (void) { + rt_tsk_pass(); // Pass control to next task + return osOK; +} + +/// Change priority of an active thread +osStatus svcThreadSetPriority (osThreadId thread_id, osPriority priority) { + OS_RESULT res; + P_TCB ptcb; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return osErrorParameter; + + if ((priority < osPriorityIdle) || (priority > osPriorityRealtime)) { + return osErrorValue; + } + + res = rt_tsk_prio( // Change task priority + ptcb->task_id, // Task ID + priority - osPriorityIdle + 1 // New task priority + ); + + if (res == OS_R_NOK) return osErrorResource; // Change task priority failed + + return osOK; +} + +/// Get current priority of an active thread +osPriority svcThreadGetPriority (osThreadId thread_id) { + P_TCB ptcb; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return osPriorityError; + + return (osPriority)(ptcb->prio - 1 + osPriorityIdle); +} + + +// Thread Public API + +/// Create a thread and add it to Active Threads and set it to state READY +osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) { + if (__exceptional_mode()) return NULL; // Not allowed in ISR + if ((__get_mode() != MODE_USR) && (os_running == 0)) { + // Privileged and not running + return svcThreadCreate(thread_def, argument); + } else { + return __svcThreadCreate(thread_def, argument); + } +} + +/// Return the thread ID of the current running thread +osThreadId osThreadGetId (void) { + if (__exceptional_mode()) return NULL; // Not allowed in ISR + return __svcThreadGetId(); +} + +/// Terminate execution of a thread and remove it from ActiveThreads +osStatus osThreadTerminate (osThreadId thread_id) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcThreadTerminate(thread_id); +} + +/// Pass control to next thread that is in state READY +osStatus osThreadYield (void) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcThreadYield(); +} + +/// Change priority of an active thread +osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcThreadSetPriority(thread_id, priority); +} + +/// Get current priority of an active thread +osPriority osThreadGetPriority (osThreadId thread_id) { + if (__exceptional_mode()) return osPriorityError;// Not allowed in ISR + return __svcThreadGetPriority(thread_id); +} + +/// INTERNAL - Not Public +/// Auto Terminate Thread on exit (used implicitly when thread exists) +__NO_RETURN void osThreadExit (void) { + __svcThreadTerminate(__svcThreadGetId()); + for (;;); // Should never come here +} + +#ifdef __MBED_CMSIS_RTOS_CA9 +/// Get current thread state +uint8_t osThreadGetState (osThreadId thread_id) { + P_TCB ptcb; + + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return osErrorParameter; + + return ptcb->state; +} +#endif + +// ==== Generic Wait Functions ==== + +// Generic Wait Service Calls declarations +SVC_1_1(svcDelay, osStatus, uint32_t, RET_osStatus) +#if osFeature_Wait != 0 +SVC_1_3(svcWait, os_InRegs osEvent, uint32_t, RET_osEvent) +#endif + +// Generic Wait Service Calls + +/// Wait for Timeout (Time Delay) +osStatus svcDelay (uint32_t millisec) { + if (millisec == 0) return osOK; + rt_dly_wait(rt_ms2tick(millisec)); + return osEventTimeout; +} + +/// Wait for Signal, Message, Mail, or Timeout +#if osFeature_Wait != 0 +os_InRegs osEvent_type svcWait (uint32_t millisec) { + osEvent ret; + + if (millisec == 0) { + ret.status = osOK; + return osEvent_ret_status; + } + + /* To Do: osEventSignal, osEventMessage, osEventMail */ + rt_dly_wait(rt_ms2tick(millisec)); + ret.status = osEventTimeout; + + return osEvent_ret_status; +} +#endif + + +// Generic Wait API + +/// Wait for Timeout (Time Delay) +osStatus osDelay (uint32_t millisec) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcDelay(millisec); +} + +/// Wait for Signal, Message, Mail, or Timeout +os_InRegs osEvent osWait (uint32_t millisec) { + osEvent ret; + +#if osFeature_Wait == 0 + ret.status = osErrorOS; + return ret; +#else + if (__exceptional_mode()) { // Not allowed in ISR + ret.status = osErrorISR; + return ret; + } + return __svcWait(millisec); +#endif +} + + +// ==== Timer Management ==== + +// Timer definitions +#define osTimerInvalid 0 +#define osTimerStopped 1 +#define osTimerRunning 2 + +// Timer structures + +typedef struct os_timer_cb_ { // Timer Control Block + struct os_timer_cb_ *next; // Pointer to next active Timer + uint8_t state; // Timer State + uint8_t type; // Timer Type (Periodic/One-shot) + uint16_t reserved; // Reserved + uint16_t tcnt; // Timer Delay Count + uint16_t icnt; // Timer Initial Count + void *arg; // Timer Function Argument + const osTimerDef_t *timer; // Pointer to Timer definition +} os_timer_cb; + +// Timer variables +os_timer_cb *os_timer_head; // Pointer to first active Timer + + +// Timer Helper Functions + +// Insert Timer into the list sorted by time +static void rt_timer_insert (os_timer_cb *pt, uint32_t tcnt) { + os_timer_cb *p, *prev; + + prev = NULL; + p = os_timer_head; + while (p != NULL) { + if (tcnt < p->tcnt) break; + tcnt -= p->tcnt; + prev = p; + p = p->next; + } + pt->next = p; + pt->tcnt = (uint16_t)tcnt; + if (p != NULL) { + p->tcnt -= pt->tcnt; + } + if (prev != NULL) { + prev->next = pt; + } else { + os_timer_head = pt; + } +} + +// Remove Timer from the list +static int rt_timer_remove (os_timer_cb *pt) { + os_timer_cb *p, *prev; + + prev = NULL; + p = os_timer_head; + while (p != NULL) { + if (p == pt) break; + prev = p; + p = p->next; + } + if (p == NULL) return -1; + if (prev != NULL) { + prev->next = pt->next; + } else { + os_timer_head = pt->next; + } + if (pt->next != NULL) { + pt->next->tcnt += pt->tcnt; + } + + return 0; +} + + +// Timer Service Calls declarations +SVC_3_1(svcTimerCreate, osTimerId, const osTimerDef_t *, os_timer_type, void *, RET_pointer) +SVC_2_1(svcTimerStart, osStatus, osTimerId, uint32_t, RET_osStatus) +SVC_1_1(svcTimerStop, osStatus, osTimerId, RET_osStatus) +SVC_1_1(svcTimerDelete, osStatus, osTimerId, RET_osStatus) +SVC_1_2(svcTimerCall, os_InRegs osCallback, osTimerId, RET_osCallback) + +// Timer Management Service Calls + +/// Create timer +osTimerId svcTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) { + os_timer_cb *pt; + + if ((timer_def == NULL) || (timer_def->ptimer == NULL)) { + sysThreadError(osErrorParameter); + return NULL; + } + + pt = timer_def->timer; + if (pt == NULL) { + sysThreadError(osErrorParameter); + return NULL; + } + + if ((type != osTimerOnce) && (type != osTimerPeriodic)) { + sysThreadError(osErrorValue); + return NULL; + } + + if (osThreadId_osTimerThread == NULL) { + sysThreadError(osErrorResource); + return NULL; + } + + if (pt->state != osTimerInvalid){ + sysThreadError(osErrorResource); + return NULL; + } + + pt->state = osTimerStopped; + pt->type = (uint8_t)type; + pt->arg = argument; + pt->timer = timer_def; + + return (osTimerId)pt; +} + +/// Start or restart timer +osStatus svcTimerStart (osTimerId timer_id, uint32_t millisec) { + os_timer_cb *pt; + uint32_t tcnt; + + pt = rt_id2obj(timer_id); + if (pt == NULL) return osErrorParameter; + + tcnt = rt_ms2tick(millisec); + if (tcnt == 0) return osErrorValue; + + switch (pt->state) { + case osTimerRunning: + if (rt_timer_remove(pt) != 0) { + return osErrorResource; + } + break; + case osTimerStopped: + pt->state = osTimerRunning; + pt->icnt = (uint16_t)tcnt; + break; + default: + return osErrorResource; + } + + rt_timer_insert(pt, tcnt); + + return osOK; +} + +/// Stop timer +osStatus svcTimerStop (osTimerId timer_id) { + os_timer_cb *pt; + + pt = rt_id2obj(timer_id); + if (pt == NULL) return osErrorParameter; + + if (pt->state != osTimerRunning) return osErrorResource; + + pt->state = osTimerStopped; + + if (rt_timer_remove(pt) != 0) { + return osErrorResource; + } + + return osOK; +} + +/// Delete timer +osStatus svcTimerDelete (osTimerId timer_id) { + os_timer_cb *pt; + + pt = rt_id2obj(timer_id); + if (pt == NULL) return osErrorParameter; + + switch (pt->state) { + case osTimerRunning: + rt_timer_remove(pt); + break; + case osTimerStopped: + break; + default: + return osErrorResource; + } + + pt->state = osTimerInvalid; + + return osOK; +} + +/// Get timer callback parameters +os_InRegs osCallback_type svcTimerCall (osTimerId timer_id) { + os_timer_cb *pt; + osCallback ret; + + pt = rt_id2obj(timer_id); + if (pt == NULL) { + ret.fp = NULL; + ret.arg = NULL; + return osCallback_ret; + } + + ret.fp = (void *)pt->timer->ptimer; + ret.arg = pt->arg; + + return osCallback_ret; +} + +static __INLINE osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec); + +/// Timer Tick (called each SysTick) +void sysTimerTick (void) { + os_timer_cb *pt, *p; + + p = os_timer_head; + if (p == NULL) return; + + p->tcnt--; + while ((p != NULL) && (p->tcnt == 0)) { + pt = p; + p = p->next; + os_timer_head = p; + isrMessagePut(osMessageQId_osTimerMessageQ, (uint32_t)pt, 0); + if (pt->type == osTimerPeriodic) { + rt_timer_insert(pt, pt->icnt); + } else { + pt->state = osTimerStopped; + } + } +} + + +// Timer Management Public API + +/// Create timer +osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) { + if (__exceptional_mode()) return NULL; // Not allowed in ISR + if ((__get_mode() != MODE_USR) && (os_running == 0)) { + // Privileged and not running + return svcTimerCreate(timer_def, type, argument); + } else { + return __svcTimerCreate(timer_def, type, argument); + } +} + +/// Start or restart timer +osStatus osTimerStart (osTimerId timer_id, uint32_t millisec) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcTimerStart(timer_id, millisec); +} + +/// Stop timer +osStatus osTimerStop (osTimerId timer_id) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcTimerStop(timer_id); +} + +/// Delete timer +osStatus osTimerDelete (osTimerId timer_id) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcTimerDelete(timer_id); +} + +/// INTERNAL - Not Public +/// Get timer callback parameters (used by OS Timer Thread) +os_InRegs osCallback osTimerCall (osTimerId timer_id) { + return __svcTimerCall(timer_id); +} + + +// Timer Thread +__NO_RETURN void osTimerThread (void const *argument) { + osCallback cb; + osEvent evt; + + for (;;) { + evt = osMessageGet(osMessageQId_osTimerMessageQ, osWaitForever); + if (evt.status == osEventMessage) { + cb = osTimerCall(evt.value.p); + if (cb.fp != NULL) { + (*(os_ptimer)cb.fp)(cb.arg); + } + } + } +} + + +// ==== Signal Management ==== + +// Signal Service Calls declarations +SVC_2_1(svcSignalSet, int32_t, osThreadId, int32_t, RET_int32_t) +SVC_2_1(svcSignalClear, int32_t, osThreadId, int32_t, RET_int32_t) +SVC_1_1(svcSignalGet, int32_t, osThreadId, RET_int32_t) +SVC_2_3(svcSignalWait, os_InRegs osEvent, int32_t, uint32_t, RET_osEvent) + +// Signal Service Calls + +/// Set the specified Signal Flags of an active thread +int32_t svcSignalSet (osThreadId thread_id, int32_t signals) { + P_TCB ptcb; + int32_t sig; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return 0x80000000; + + if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000; + + sig = ptcb->events; // Previous signal flags + + rt_evt_set(signals, ptcb->task_id); // Set event flags + + return sig; +} + +/// Clear the specified Signal Flags of an active thread +int32_t svcSignalClear (osThreadId thread_id, int32_t signals) { + P_TCB ptcb; + int32_t sig; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return 0x80000000; + + if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000; + + sig = ptcb->events; // Previous signal flags + + rt_evt_clr(signals, ptcb->task_id); // Clear event flags + + return sig; +} + +/// Get Signal Flags status of an active thread +int32_t svcSignalGet (osThreadId thread_id) { + P_TCB ptcb; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return 0x80000000; + + return ptcb->events; // Return event flags +} + +/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread +os_InRegs osEvent_type svcSignalWait (int32_t signals, uint32_t millisec) { + OS_RESULT res; + osEvent ret; + + if (signals & (0xFFFFFFFF << osFeature_Signals)) { + ret.status = osErrorValue; + return osEvent_ret_status; + } + + if (signals != 0) { // Wait for all specified signals + res = rt_evt_wait(signals, rt_ms2tick(millisec), __TRUE); + } else { // Wait for any signal + res = rt_evt_wait(0xFFFF, rt_ms2tick(millisec), __FALSE); + } + + if (res == OS_R_EVT) { + ret.status = osEventSignal; + ret.value.signals = signals ? signals : os_tsk.run->waits; + } else { + ret.status = millisec ? osEventTimeout : osOK; + ret.value.signals = 0; + } + + return osEvent_ret_value; +} + + +// Signal ISR Calls + +/// Set the specified Signal Flags of an active thread +static __INLINE int32_t isrSignalSet (osThreadId thread_id, int32_t signals) { + P_TCB ptcb; + int32_t sig; + + ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer + if (ptcb == NULL) return 0x80000000; + + if (signals & (0xFFFFFFFF << osFeature_Signals)) return 0x80000000; + + sig = ptcb->events; // Previous signal flags + + isr_evt_set(signals, ptcb->task_id); // Set event flags + + return sig; +} + + +// Signal Public API + +/// Set the specified Signal Flags of an active thread +int32_t osSignalSet (osThreadId thread_id, int32_t signals) { + if (__exceptional_mode()) { // in ISR + return isrSignalSet(thread_id, signals); + } else { // in Thread + return __svcSignalSet(thread_id, signals); + } +} + +/// Clear the specified Signal Flags of an active thread +int32_t osSignalClear (osThreadId thread_id, int32_t signals) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcSignalClear(thread_id, signals); +} + +/// Get Signal Flags status of an active thread +int32_t osSignalGet (osThreadId thread_id) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcSignalGet(thread_id); +} + +/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread +os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) { + osEvent ret; + + if (__exceptional_mode()) { // Not allowed in ISR + ret.status = osErrorISR; + return ret; + } + return __svcSignalWait(signals, millisec); +} + + +// ==== Mutex Management ==== + +// Mutex Service Calls declarations +SVC_1_1(svcMutexCreate, osMutexId, const osMutexDef_t *, RET_pointer) +SVC_2_1(svcMutexWait, osStatus, osMutexId, uint32_t, RET_osStatus) +SVC_1_1(svcMutexRelease, osStatus, osMutexId, RET_osStatus) +SVC_1_1(svcMutexDelete, osStatus, osMutexId, RET_osStatus) + +// Mutex Service Calls + +/// Create and Initialize a Mutex object +osMutexId svcMutexCreate (const osMutexDef_t *mutex_def) { + OS_ID mut; + + if (mutex_def == NULL) { + sysThreadError(osErrorParameter); + return NULL; + } + + mut = mutex_def->mutex; + if (mut == NULL) { + sysThreadError(osErrorParameter); + return NULL; + } + + if (((P_MUCB)mut)->cb_type != 0) { + sysThreadError(osErrorParameter); + return NULL; + } + + rt_mut_init(mut); // Initialize Mutex + + return mut; +} + +/// Wait until a Mutex becomes available +osStatus svcMutexWait (osMutexId mutex_id, uint32_t millisec) { + OS_ID mut; + OS_RESULT res; + + mut = rt_id2obj(mutex_id); + if (mut == NULL) return osErrorParameter; + + if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter; + + res = rt_mut_wait(mut, rt_ms2tick(millisec)); // Wait for Mutex + + if (res == OS_R_TMO) { + return (millisec ? osErrorTimeoutResource : osErrorResource); + } + + return osOK; +} + +/// Release a Mutex that was obtained with osMutexWait +osStatus svcMutexRelease (osMutexId mutex_id) { + OS_ID mut; + OS_RESULT res; + + mut = rt_id2obj(mutex_id); + if (mut == NULL) return osErrorParameter; + + if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter; + + res = rt_mut_release(mut); // Release Mutex + + if (res == OS_R_NOK) return osErrorResource; // Thread not owner or Zero Counter + + return osOK; +} + +/// Delete a Mutex that was created by osMutexCreate +osStatus svcMutexDelete (osMutexId mutex_id) { + OS_ID mut; + + mut = rt_id2obj(mutex_id); + if (mut == NULL) return osErrorParameter; + + if (((P_MUCB)mut)->cb_type != MUCB) return osErrorParameter; + + rt_mut_delete(mut); // Release Mutex + + return osOK; +} + + +// Mutex Public API + +/// Create and Initialize a Mutex object +osMutexId osMutexCreate (const osMutexDef_t *mutex_def) { + if (__exceptional_mode()) return NULL; // Not allowed in ISR + if ((__get_mode() != MODE_USR) && (os_running == 0)) { + // Privileged and not running + return svcMutexCreate(mutex_def); + } else { + return __svcMutexCreate(mutex_def); + } +} + +/// Wait until a Mutex becomes available +osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcMutexWait(mutex_id, millisec); +} + +/// Release a Mutex that was obtained with osMutexWait +osStatus osMutexRelease (osMutexId mutex_id) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcMutexRelease(mutex_id); +} + +/// Delete a Mutex that was created by osMutexCreate +osStatus osMutexDelete (osMutexId mutex_id) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcMutexDelete(mutex_id); +} + + +// ==== Semaphore Management ==== + +// Semaphore Service Calls declarations +SVC_2_1(svcSemaphoreCreate, osSemaphoreId, const osSemaphoreDef_t *, int32_t, RET_pointer) +SVC_2_1(svcSemaphoreWait, int32_t, osSemaphoreId, uint32_t, RET_int32_t) +SVC_1_1(svcSemaphoreRelease, osStatus, osSemaphoreId, RET_osStatus) +SVC_1_1(svcSemaphoreDelete, osStatus, osSemaphoreId, RET_osStatus) + +// Semaphore Service Calls + +/// Create and Initialize a Semaphore object +osSemaphoreId svcSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) { + OS_ID sem; + + if (semaphore_def == NULL) { + sysThreadError(osErrorParameter); + return NULL; + } + + sem = semaphore_def->semaphore; + if (sem == NULL) { + sysThreadError(osErrorParameter); + return NULL; + } + + if (((P_SCB)sem)->cb_type != 0) { + sysThreadError(osErrorParameter); + return NULL; + } + + if (count > osFeature_Semaphore) { + sysThreadError(osErrorValue); + return NULL; + } + + rt_sem_init(sem, count); // Initialize Semaphore + + return sem; +} + +/// Wait until a Semaphore becomes available +int32_t svcSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { + OS_ID sem; + OS_RESULT res; + + sem = rt_id2obj(semaphore_id); + if (sem == NULL) return -1; + + if (((P_SCB)sem)->cb_type != SCB) return -1; + + res = rt_sem_wait(sem, rt_ms2tick(millisec)); // Wait for Semaphore + + if (res == OS_R_TMO) return 0; // Timeout + + return (((P_SCB)sem)->tokens + 1); +} + +/// Release a Semaphore +osStatus svcSemaphoreRelease (osSemaphoreId semaphore_id) { + OS_ID sem; + + sem = rt_id2obj(semaphore_id); + if (sem == NULL) return osErrorParameter; + + if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter; + + if (((P_SCB)sem)->tokens == osFeature_Semaphore) return osErrorResource; + + rt_sem_send(sem); // Release Semaphore + + return osOK; +} + +/// Delete a Semaphore that was created by osSemaphoreCreate +osStatus svcSemaphoreDelete (osSemaphoreId semaphore_id) { + OS_ID sem; + + sem = rt_id2obj(semaphore_id); + if (sem == NULL) return osErrorParameter; + + if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter; + + rt_sem_delete(sem); // Delete Semaphore + + return osOK; +} + + +// Semaphore ISR Calls + +/// Release a Semaphore +static __INLINE osStatus isrSemaphoreRelease (osSemaphoreId semaphore_id) { + OS_ID sem; + + sem = rt_id2obj(semaphore_id); + if (sem == NULL) return osErrorParameter; + + if (((P_SCB)sem)->cb_type != SCB) return osErrorParameter; + + if (((P_SCB)sem)->tokens == osFeature_Semaphore) return osErrorResource; + + isr_sem_send(sem); // Release Semaphore + + return osOK; +} + + +// Semaphore Public API + +/// Create and Initialize a Semaphore object +osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) { + if (__exceptional_mode()) return NULL; // Not allowed in ISR + if ((__get_mode() != MODE_USR) && (os_running == 0)) { + // Privileged and not running + return svcSemaphoreCreate(semaphore_def, count); + } else { + return __svcSemaphoreCreate(semaphore_def, count); + } +} + +/// Wait until a Semaphore becomes available +int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) { + if (__exceptional_mode()) return -1; // Not allowed in ISR + return __svcSemaphoreWait(semaphore_id, millisec); +} + +/// Release a Semaphore +osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) { + if (__exceptional_mode()) { // in ISR + return isrSemaphoreRelease(semaphore_id); + } else { // in Thread + return __svcSemaphoreRelease(semaphore_id); + } +} + +/// Delete a Semaphore that was created by osSemaphoreCreate +osStatus osSemaphoreDelete (osSemaphoreId semaphore_id) { + if (__exceptional_mode()) return osErrorISR; // Not allowed in ISR + return __svcSemaphoreDelete(semaphore_id); +} + + +// ==== Memory Management Functions ==== + +// Memory Management Helper Functions + +// Clear Memory Box (Zero init) +static void rt_clr_box (void *box_mem, void *box) { + uint32_t *p, n; + + if (box) { + p = box; + for (n = ((P_BM)box_mem)->blk_size; n; n -= 4) { + *p++ = 0; + } + } +} + +// Memory Management Service Calls declarations +SVC_1_1(svcPoolCreate, osPoolId, const osPoolDef_t *, RET_pointer) +SVC_2_1(sysPoolAlloc, void *, osPoolId, uint32_t, RET_pointer) +SVC_2_1(sysPoolFree, osStatus, osPoolId, void *, RET_osStatus) + +// Memory Management Service & ISR Calls + +/// Create and Initialize memory pool +osPoolId svcPoolCreate (const osPoolDef_t *pool_def) { + uint32_t blk_sz; + + if ((pool_def == NULL) || + (pool_def->pool_sz == 0) || + (pool_def->item_sz == 0) || + (pool_def->pool == NULL)) { + sysThreadError(osErrorParameter); + return NULL; + } + + blk_sz = (pool_def->item_sz + 3) & ~3; + + _init_box(pool_def->pool, sizeof(struct OS_BM) + pool_def->pool_sz * blk_sz, blk_sz); + + return pool_def->pool; +} + +/// Allocate a memory block from a memory pool +void *sysPoolAlloc (osPoolId pool_id, uint32_t clr) { + void *ptr; + + if (pool_id == NULL) return NULL; + + ptr = rt_alloc_box(pool_id); + if (clr) { + rt_clr_box(pool_id, ptr); + } + + return ptr; +} + +/// Return an allocated memory block back to a specific memory pool +osStatus sysPoolFree (osPoolId pool_id, void *block) { + int32_t res; + + if (pool_id == NULL) return osErrorParameter; + + res = rt_free_box(pool_id, block); + if (res != 0) return osErrorValue; + + return osOK; +} + + +// Memory Management Public API + +/// Create and Initialize memory pool +osPoolId osPoolCreate (const osPoolDef_t *pool_def) { + if (__exceptional_mode()) return NULL; // Not allowed in ISR + if ((__get_mode() != MODE_USR) && (os_running == 0)) { + // Privileged and not running + return svcPoolCreate(pool_def); + } else { + return __svcPoolCreate(pool_def); + } +} + +/// Allocate a memory block from a memory pool +void *osPoolAlloc (osPoolId pool_id) { + if (__get_mode() != MODE_USR) { // in ISR or Privileged + return sysPoolAlloc(pool_id, 0); + } else { // in Thread + return __sysPoolAlloc(pool_id, 0); + } +} + +/// Allocate a memory block from a memory pool and set memory block to zero +void *osPoolCAlloc (osPoolId pool_id) { + if (__get_mode() != MODE_USR) { // in ISR or Privileged + return sysPoolAlloc(pool_id, 1); + } else { // in Thread + return __sysPoolAlloc(pool_id, 1); + } +} + +/// Return an allocated memory block back to a specific memory pool +osStatus osPoolFree (osPoolId pool_id, void *block) { + if (__get_mode() != MODE_USR) { // in ISR or Privileged + return sysPoolFree(pool_id, block); + } else { // in Thread + return __sysPoolFree(pool_id, block); + } +} + + +// ==== Message Queue Management Functions ==== + +// Message Queue Management Service Calls declarations +SVC_2_1(svcMessageCreate, osMessageQId, const osMessageQDef_t *, osThreadId, RET_pointer) +SVC_3_1(svcMessagePut, osStatus, osMessageQId, uint32_t, uint32_t, RET_osStatus) +SVC_2_3(svcMessageGet, os_InRegs osEvent, osMessageQId, uint32_t, RET_osEvent) + +// Message Queue Service Calls + +/// Create and Initialize Message Queue +osMessageQId svcMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { + + if ((queue_def == NULL) || + (queue_def->queue_sz == 0) || + (queue_def->pool == NULL)) { + sysThreadError(osErrorParameter); + return NULL; + } + + if (((P_MCB)queue_def->pool)->cb_type != 0) { + sysThreadError(osErrorParameter); + return NULL; + } + + rt_mbx_init(queue_def->pool, 4*(queue_def->queue_sz + 4)); + + return queue_def->pool; +} + +/// Put a Message to a Queue +osStatus svcMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { + OS_RESULT res; + + if (queue_id == NULL) return osErrorParameter; + + if (((P_MCB)queue_id)->cb_type != MCB) return osErrorParameter; + + res = rt_mbx_send(queue_id, (void *)info, rt_ms2tick(millisec)); + + if (res == OS_R_TMO) { + return (millisec ? osErrorTimeoutResource : osErrorResource); + } + + return osOK; +} + +/// Get a Message or Wait for a Message from a Queue +os_InRegs osEvent_type svcMessageGet (osMessageQId queue_id, uint32_t millisec) { + OS_RESULT res; + osEvent ret; + + if (queue_id == NULL) { + ret.status = osErrorParameter; + return osEvent_ret_status; + } + + if (((P_MCB)queue_id)->cb_type != MCB) { + ret.status = osErrorParameter; + return osEvent_ret_status; + } + + res = rt_mbx_wait(queue_id, &ret.value.p, rt_ms2tick(millisec)); + + if (res == OS_R_TMO) { + ret.status = millisec ? osEventTimeout : osOK; + return osEvent_ret_value; + } + + ret.status = osEventMessage; + + return osEvent_ret_value; +} + + +// Message Queue ISR Calls + +/// Put a Message to a Queue +static __INLINE osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { + + if ((queue_id == NULL) || (millisec != 0)) { + return osErrorParameter; + } + + if (((P_MCB)queue_id)->cb_type != MCB) return osErrorParameter; + + if (rt_mbx_check(queue_id) == 0) { // Check if Queue is full + return osErrorResource; + } + + isr_mbx_send(queue_id, (void *)info); + + return osOK; +} + +/// Get a Message or Wait for a Message from a Queue +static __INLINE os_InRegs osEvent isrMessageGet (osMessageQId queue_id, uint32_t millisec) { + OS_RESULT res; + osEvent ret; + + if ((queue_id == NULL) || (millisec != 0)) { + ret.status = osErrorParameter; + return ret; + } + + if (((P_MCB)queue_id)->cb_type != MCB) { + ret.status = osErrorParameter; + return ret; + } + + res = isr_mbx_receive(queue_id, &ret.value.p); + + if (res != OS_R_MBX) { + ret.status = osOK; + return ret; + } + + ret.status = osEventMessage; + + return ret; +} + + +// Message Queue Management Public API + +/// Create and Initialize Message Queue +osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { + if (__exceptional_mode()) return NULL; // Not allowed in ISR + if ((__get_mode() != MODE_USR) && (os_running == 0)) { + // Privileged and not running + return svcMessageCreate(queue_def, thread_id); + } else { + return __svcMessageCreate(queue_def, thread_id); + } +} + +/// Put a Message to a Queue +osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) { + if (__exceptional_mode()) { // in ISR + return isrMessagePut(queue_id, info, millisec); + } else { // in Thread + return __svcMessagePut(queue_id, info, millisec); + } +} + +/// Get a Message or Wait for a Message from a Queue +os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) { + if (__exceptional_mode()) { // in ISR + return isrMessageGet(queue_id, millisec); + } else { // in Thread + return __svcMessageGet(queue_id, millisec); + } +} + + +// ==== Mail Queue Management Functions ==== + +// Mail Queue Management Service Calls declarations +SVC_2_1(svcMailCreate, osMailQId, const osMailQDef_t *, osThreadId, RET_pointer) +SVC_4_1(sysMailAlloc, void *, osMailQId, uint32_t, uint32_t, uint32_t, RET_pointer) +SVC_3_1(sysMailFree, osStatus, osMailQId, void *, uint32_t, RET_osStatus) + +// Mail Queue Management Service & ISR Calls + +/// Create and Initialize mail queue +osMailQId svcMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) { + uint32_t blk_sz; + P_MCB pmcb; + void *pool; + + if ((queue_def == NULL) || + (queue_def->queue_sz == 0) || + (queue_def->item_sz == 0) || + (queue_def->pool == NULL)) { + sysThreadError(osErrorParameter); + return NULL; + } + + pmcb = *(((void **)queue_def->pool) + 0); + pool = *(((void **)queue_def->pool) + 1); + + if ((pool == NULL) || (pmcb == NULL) || (pmcb->cb_type != 0)) { + sysThreadError(osErrorParameter); + return NULL; + } + + blk_sz = (queue_def->item_sz + 3) & ~3; + + _init_box(pool, sizeof(struct OS_BM) + queue_def->queue_sz * blk_sz, blk_sz); + + rt_mbx_init(pmcb, 4*(queue_def->queue_sz + 4)); + + + return queue_def->pool; +} + +/// Allocate a memory block from a mail +void *sysMailAlloc (osMailQId queue_id, uint32_t millisec, uint32_t isr, uint32_t clr) { + P_MCB pmcb; + void *pool; + void *mem; + + if (queue_id == NULL) return NULL; + + pmcb = *(((void **)queue_id) + 0); + pool = *(((void **)queue_id) + 1); + + if ((pool == NULL) || (pmcb == NULL)) return NULL; + + if (isr && (millisec != 0)) return NULL; + + mem = rt_alloc_box(pool); + if (clr) { + rt_clr_box(pool, mem); + } + + if ((mem == NULL) && (millisec != 0)) { + // Put Task to sleep when Memory not available + if (pmcb->p_lnk != NULL) { + rt_put_prio((P_XCB)pmcb, os_tsk.run); + } else { + pmcb->p_lnk = os_tsk.run; + os_tsk.run->p_lnk = NULL; + os_tsk.run->p_rlnk = (P_TCB)pmcb; + // Task is waiting to allocate a message + pmcb->state = 3; + } + rt_block(rt_ms2tick(millisec), WAIT_MBX); + } + + return mem; +} + +/// Free a memory block from a mail +osStatus sysMailFree (osMailQId queue_id, void *mail, uint32_t isr) { + P_MCB pmcb; + P_TCB ptcb; + void *pool; + void *mem; + int32_t res; + + if (queue_id == NULL) return osErrorParameter; + + pmcb = *(((void **)queue_id) + 0); + pool = *(((void **)queue_id) + 1); + + if ((pmcb == NULL) || (pool == NULL)) return osErrorParameter; + + res = rt_free_box(pool, mail); + + if (res != 0) return osErrorValue; + + if (pmcb->state == 3) { + // Task is waiting to allocate a message + if (isr) { + rt_psq_enq (pmcb, (U32)pool); + rt_psh_req (); + } else { + mem = rt_alloc_box(pool); + if (mem != NULL) { + ptcb = rt_get_first((P_XCB)pmcb); + if (pmcb->p_lnk == NULL) { + pmcb->state = 0; + } + rt_ret_val(ptcb, (U32)mem); + rt_rmv_dly(ptcb); + rt_dispatch(ptcb); + } + } + } + + return osOK; +} + + +// Mail Queue Management Public API + +/// Create and Initialize mail queue +osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) { + if (__exceptional_mode()) return NULL; // Not allowed in ISR + if ((__get_mode() != MODE_USR) && (os_running == 0)) { + // Privileged and not running + return svcMailCreate(queue_def, thread_id); + } else { + return __svcMailCreate(queue_def, thread_id); + } +} + +/// Allocate a memory block from a mail +void *osMailAlloc (osMailQId queue_id, uint32_t millisec) { + if (__exceptional_mode()) { // in ISR + return sysMailAlloc(queue_id, millisec, 1, 0); + } else { // in Thread + return __sysMailAlloc(queue_id, millisec, 0, 0); + } +} + +/// Allocate a memory block from a mail and set memory block to zero +void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) { + if (__exceptional_mode()) { // in ISR + return sysMailAlloc(queue_id, millisec, 1, 1); + } else { // in Thread + return __sysMailAlloc(queue_id, millisec, 0, 1); + } +} + +/// Free a memory block from a mail +osStatus osMailFree (osMailQId queue_id, void *mail) { + if (__exceptional_mode()) { // in ISR + return sysMailFree(queue_id, mail, 1); + } else { // in Thread + return __sysMailFree(queue_id, mail, 0); + } +} + +/// Put a mail to a queue +osStatus osMailPut (osMailQId queue_id, void *mail) { + if (queue_id == NULL) return osErrorParameter; + if (mail == NULL) return osErrorValue; + return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0); +} + +/// Get a mail from a queue +os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) { + osEvent ret; + + if (queue_id == NULL) { + ret.status = osErrorParameter; + return ret; + } + + ret = osMessageGet(*((void **)queue_id), millisec); + if (ret.status == osEventMessage) ret.status = osEventMail; + + return ret; +} diff --git a/libraries/rtos/rtx_ca/rt_Event.c b/libraries/rtos/rtx_ca/rt_Event.c new file mode 100644 index 0000000000..85a80041ac --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Event.c @@ -0,0 +1,194 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_EVENT.C + * Purpose: Implements waits and wake-ups for event flags + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_System.h" +#include "rt_Event.h" +#include "rt_List.h" +#include "rt_Task.h" +#ifdef __CORTEX_A9 +#include "rt_HAL_CA.h" +#else +#include "rt_HAL_CM.h" +#endif + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_evt_wait -----------------------------------*/ + +OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait) { + /* Wait for one or more event flags with optional time-out. */ + /* "wait_flags" identifies the flags to wait for. */ + /* "timeout" is the time-out limit in system ticks (0xffff if no time-out) */ + /* "and_wait" specifies the AND-ing of "wait_flags" as condition to be met */ + /* to complete the wait. (OR-ing if set to 0). */ + U32 block_state; + + if (and_wait) { + /* Check for AND-connected events */ + if ((os_tsk.run->events & wait_flags) == wait_flags) { + os_tsk.run->events &= ~wait_flags; + return (OS_R_EVT); + } + block_state = WAIT_AND; + } + else { + /* Check for OR-connected events */ + if (os_tsk.run->events & wait_flags) { + os_tsk.run->waits = os_tsk.run->events & wait_flags; + os_tsk.run->events &= ~wait_flags; + return (OS_R_EVT); + } + block_state = WAIT_OR; + } + /* Task has to wait */ + os_tsk.run->waits = wait_flags; + rt_block (timeout, (U8)block_state); + return (OS_R_TMO); +} + + +/*--------------------------- rt_evt_set ------------------------------------*/ + +void rt_evt_set (U16 event_flags, OS_TID task_id) { + /* Set one or more event flags of a selectable task. */ + P_TCB p_tcb; + + p_tcb = os_active_TCB[task_id-1]; + if (p_tcb == NULL) { + return; + } + p_tcb->events |= event_flags; + event_flags = p_tcb->waits; + /* If the task is not waiting for an event, it should not be put */ + /* to ready state. */ + if (p_tcb->state == WAIT_AND) { + /* Check for AND-connected events */ + if ((p_tcb->events & event_flags) == event_flags) { + goto wkup; + } + } + if (p_tcb->state == WAIT_OR) { + /* Check for OR-connected events */ + if (p_tcb->events & event_flags) { + p_tcb->waits &= p_tcb->events; +wkup: p_tcb->events &= ~event_flags; + rt_rmv_dly (p_tcb); + p_tcb->state = READY; +#ifdef __CMSIS_RTOS + rt_ret_val2(p_tcb, 0x08/*osEventSignal*/, p_tcb->waits); +#else + rt_ret_val (p_tcb, OS_R_EVT); +#endif + rt_dispatch (p_tcb); + } + } +} + + +/*--------------------------- rt_evt_clr ------------------------------------*/ + +void rt_evt_clr (U16 clear_flags, OS_TID task_id) { + /* Clear one or more event flags (identified by "clear_flags") of a */ + /* selectable task (identified by "task"). */ + P_TCB task = os_active_TCB[task_id-1]; + + if (task == NULL) { + return; + } + task->events &= ~clear_flags; +} + + +/*--------------------------- isr_evt_set -----------------------------------*/ + +void isr_evt_set (U16 event_flags, OS_TID task_id) { + /* Same function as "os_evt_set", but to be called by ISRs. */ + P_TCB p_tcb = os_active_TCB[task_id-1]; + + if (p_tcb == NULL) { + return; + } + rt_psq_enq (p_tcb, event_flags); + rt_psh_req (); +} + + +/*--------------------------- rt_evt_get ------------------------------------*/ + +U16 rt_evt_get (void) { + /* Get events of a running task after waiting for OR connected events. */ + return (os_tsk.run->waits); +} + + +/*--------------------------- rt_evt_psh ------------------------------------*/ + +void rt_evt_psh (P_TCB p_CB, U16 set_flags) { + /* Check if task has to be waken up */ + U16 event_flags; + + p_CB->events |= set_flags; + event_flags = p_CB->waits; + if (p_CB->state == WAIT_AND) { + /* Check for AND-connected events */ + if ((p_CB->events & event_flags) == event_flags) { + goto rdy; + } + } + if (p_CB->state == WAIT_OR) { + /* Check for OR-connected events */ + if (p_CB->events & event_flags) { + p_CB->waits &= p_CB->events; +rdy: p_CB->events &= ~event_flags; + rt_rmv_dly (p_CB); + p_CB->state = READY; +#ifdef __CMSIS_RTOS + rt_ret_val2(p_CB, 0x08/*osEventSignal*/, p_CB->waits); +#else + rt_ret_val (p_CB, OS_R_EVT); +#endif + rt_put_prio (&os_rdy, p_CB); + } + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx_ca/rt_Event.h b/libraries/rtos/rtx_ca/rt_Event.h new file mode 100644 index 0000000000..7081f370c3 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Event.h @@ -0,0 +1,46 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_EVENT.H + * Purpose: Implements waits and wake-ups for event flags + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Functions */ +extern OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait); +extern void rt_evt_set (U16 event_flags, OS_TID task_id); +extern void rt_evt_clr (U16 clear_flags, OS_TID task_id); +extern void isr_evt_set (U16 event_flags, OS_TID task_id); +extern U16 rt_evt_get (void); +extern void rt_evt_psh (P_TCB p_CB, U16 set_flags); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_HAL_CA.h b/libraries/rtos/rtx_ca/rt_HAL_CA.h new file mode 100644 index 0000000000..11879bb67d --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_HAL_CA.h @@ -0,0 +1,199 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_HAL_CM.H + * Purpose: Hardware Abstraction Layer for Cortex-A definitions + * Rev.: 21 Aug 2013 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Definitions */ +#define INIT_CPSR_SYS 0x4000001F +#define INIT_CPSR_USER 0x40000010 + +#define CPSR_T_BIT 0x20 +#define CPSR_I_BIT 0x80 +#define CPSR_F_BIT 0x40 + +#define MODE_USR 0x10 +#define MODE_FIQ 0x11 +#define MODE_IRQ 0x12 +#define MODE_SVC 0x13 +#define MODE_ABT 0x17 +#define MODE_UND 0x1B +#define MODE_SYS 0x1F + +#define MAGIC_WORD 0xE25A2EA5 + +#include "core_ca9.h" + +#if defined (__CC_ARM) /* ARM Compiler */ + +#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M || __TARGET_ARCH_7_A) && !NO_EXCLUSIVE_ACCESS) + #define __USE_EXCLUSIVE_ACCESS +#else + #undef __USE_EXCLUSIVE_ACCESS +#endif + +#elif defined (__GNUC__) /* GNU Compiler */ + +#error GNU Compiler support not implemented for Cortex-A + +#elif defined (__ICCARM__) /* IAR Compiler */ + +#error IAR Compiler support not implemented for Cortex-A + +#endif + +static U8 priority = 0xff; + +extern const U32 GICDistributor_BASE; +extern const U32 GICInterface_BASE; + +/* GIC registers - Distributor */ +#define GICD_ICDICER0 (*((volatile U32 *)(GICDistributor_BASE + 0x180))) /* - RW - Interrupt Clear-Enable Registers */ +#define GICD_ICDISER0 (*((volatile U32 *)(GICDistributor_BASE + 0x100))) /* - RW - Interrupt Set-Enable Registers */ +#define GICD_ICDIPR0 (*((volatile U32 *)(GICDistributor_BASE + 0x400))) /* - RW - Interrupt Priority Registers */ +#define GICD_ICDSGIR (*((volatile U32 *)(GICDistributor_BASE + 0xf00))) /* - RW - Interrupt Software Interrupt Register */ +#define GICD_ICDICERx(irq) *(volatile U32 *)(&GICD_ICDICER0 + irq/32) +#define GICD_ICDISERx(irq) *(volatile U32 *)(&GICD_ICDISER0 + irq/32) + +/* GIC register - CPU Interface */ +#define GICI_ICCPMR (*((volatile U32 *)(GICInterface_BASE + 0x004))) /* - RW - Interrupt Priority Mask Register */ + +#define SGI_PENDSV 0 /* SGI0 */ +#define SGI_PENDSV_BIT ((U32)(1 << (SGI_PENDSV & 0xf))) + +//Increase priority filter to prevent timer and PendSV interrupts signaling. Guarantees that interrupts will not be forwarded. +#define OS_LOCK() int irq_dis = __disable_irq();\ + priority = GICI_ICCPMR; \ + GICI_ICCPMR = 0xff; \ + GICI_ICCPMR = GICI_ICCPMR - 1; \ + while(GICI_ICCPMR > priority);\ + __DSB();\ + if(!irq_dis) __enable_irq(); \ + +//Restore priority filter. Re-enable timer and PendSV signaling +#define OS_UNLOCK() __DSB(); \ + GICI_ICCPMR = priority; \ + +#define OS_PEND_IRQ() GICD_ICDSGIR = 0x0010000 | SGI_PENDSV +#define OS_PEND(fl,p) if(p) OS_PEND_IRQ(); +#define OS_UNPEND(fl) + +/* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- + * OS_X_INIT enables the IRQ n in the GIC */ +#define OS_X_INIT(n) char *reg; \ + reg = (char *)(&GICD_ICDIPR0 + n / 4); \ + reg += n % 4; \ + *reg = (char)0xff; \ + *reg = *reg - 1; \ + GICD_ICDISERx(n) = (U32)(1 << n % 32); +#define OS_X_LOCK(n) OS_LOCK() +#define OS_X_UNLOCK(n) OS_UNLOCK() +#define OS_X_PEND_IRQ() OS_PEND_IRQ() +#define OS_X_PEND(fl,p) if(p) OS_X_PEND_IRQ(); +#define OS_X_UNPEND(fl) + + +/* Functions */ +#ifdef __USE_EXCLUSIVE_ACCESS + #define rt_inc(p) while(__strex((__ldrex(p)+1),p)) + #define rt_dec(p) while(__strex((__ldrex(p)-1),p)) +#else + #define rt_inc(p) { int irq_dis = __disable_irq();(*p)++;if(!irq_dis) __enable_irq(); } + #define rt_dec(p) { int irq_dis = __disable_irq();(*p)--;if(!irq_dis) __enable_irq(); } +#endif + +__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) { + U32 cnt,c2; +#ifdef __USE_EXCLUSIVE_ACCESS + do { + if ((cnt = __ldrex(count)) == size) { + __clrex(); + return (cnt); } + } while (__strex(cnt+1, count)); + do { + c2 = (cnt = __ldrex(first)) + 1; + if (c2 == size) c2 = 0; + } while (__strex(c2, first)); +#else + int irq_dis; + irq_dis = __disable_irq(); + if ((cnt = *count) < size) { + *count = cnt+1; + c2 = (cnt = *first) + 1; + if (c2 == size) c2 = 0; + *first = c2; + } + if(!irq_dis) __enable_irq (); +#endif + return (cnt); +} + +__inline static void rt_systick_init (void) { + /* Cortex-A doesn't have a Systick. User needs to provide an alternative timer using RTX_Conf_CM configuration */ + /* HW initialization needs to be done in os_tick_init (void) -RTX_Conf_CM.c- */ +} + +__inline static void rt_svc_init (void) { + /* Register pendSV - through SGI */ + char *reg; + + reg = (char *)(&GICD_ICDIPR0 + SGI_PENDSV/4); + reg += SGI_PENDSV % 4; + /* Write 0xff to read priority level */ + *reg = (char)0xff; + /* Read priority level and set the lowest possible*/ + *reg = *reg - 1; + + GICD_ICDISERx(SGI_PENDSV) = (U32)SGI_PENDSV_BIT; +} + +extern void rt_set_PSP (U32 stack); +extern U32 rt_get_PSP (void); +extern void os_set_env (P_TCB p_TCB); +extern void *_alloc_box (void *box_mem); +extern int _free_box (void *box_mem, void *box); + +extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body); +extern void rt_ret_val (P_TCB p_TCB, U32 v0); +extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1); + +extern void dbg_init (void); +extern void dbg_task_notify (P_TCB p_tcb, BOOL create); +extern void dbg_task_switch (U32 task_id); + +#define DBG_INIT() +#define DBG_TASK_NOTIFY(p_tcb,create) +#define DBG_TASK_SWITCH(task_id) + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_HAL_CM.h b/libraries/rtos/rtx_ca/rt_HAL_CM.h new file mode 100644 index 0000000000..cde7317d9d --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_HAL_CM.h @@ -0,0 +1,276 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_HAL_CM.H + * Purpose: Hardware Abstraction Layer for Cortex-M definitions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Definitions */ +#define INITIAL_xPSR 0x01000000 +#define DEMCR_TRCENA 0x01000000 +#define ITM_ITMENA 0x00000001 +#define MAGIC_WORD 0xE25A2EA5 + +#if defined (__CC_ARM) /* ARM Compiler */ + +#if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS) + #define __USE_EXCLUSIVE_ACCESS +#else + #undef __USE_EXCLUSIVE_ACCESS +#endif + +#elif defined (__GNUC__) /* GNU Compiler */ + +#undef __USE_EXCLUSIVE_ACCESS + +#if defined (__CORTEX_M0) +#define __TARGET_ARCH_6S_M 1 +#else +#define __TARGET_ARCH_6S_M 0 +#endif + +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#define __TARGET_FPU_VFP 1 +#else +#define __TARGET_FPU_VFP 0 +#endif + +#define __inline inline +#define __weak __attribute__((weak)) + +#ifndef __CMSIS_GENERIC + +__attribute__((always_inline)) static inline void __enable_irq(void) +{ + __asm volatile ("cpsie i"); +} + +__attribute__((always_inline)) static inline U32 __disable_irq(void) +{ + U32 result; + + __asm volatile ("mrs %0, primask" : "=r" (result)); + __asm volatile ("cpsid i"); + return(result & 1); +} + +#endif + +__attribute__(( always_inline)) static inline U8 __clz(U32 value) +{ + U8 result; + + __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value)); + return(result); +} + +#elif defined (__ICCARM__) /* IAR Compiler */ + +#undef __USE_EXCLUSIVE_ACCESS + +#if (__CORE__ == __ARM6M__) +#define __TARGET_ARCH_6S_M 1 +#else +#define __TARGET_ARCH_6S_M 0 +#endif + +#if defined __ARMVFP__ +#define __TARGET_FPU_VFP 1 +#else +#define __TARGET_FPU_VFP 0 +#endif + +#define __inline inline + +#ifndef __CMSIS_GENERIC + +static inline void __enable_irq(void) +{ + __asm volatile ("cpsie i"); +} + +static inline U32 __disable_irq(void) +{ + U32 result; + + __asm volatile ("mrs %0, primask" : "=r" (result)); + __asm volatile ("cpsid i"); + return(result & 1); +} + +#endif + +static inline U8 __clz(U32 value) +{ + U8 result; + + __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value)); + return(result); +} + +#endif + +/* NVIC registers */ +#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010)) +#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014)) +#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018)) +#define NVIC_ISER ((volatile U32 *)0xE000E100) +#define NVIC_ICER ((volatile U32 *)0xE000E180) +#if (__TARGET_ARCH_6S_M) +#define NVIC_IP ((volatile U32 *)0xE000E400) +#else +#define NVIC_IP ((volatile U8 *)0xE000E400) +#endif +#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04)) +#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C)) +#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C)) +#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20)) + +#define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28) +#define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1)) +#define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25 +#define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26 +#define OS_LOCK() NVIC_ST_CTRL = 0x0005 +#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007 + +#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1) +#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27 +#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28 +#if (__TARGET_ARCH_6S_M) +#define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \ + NVIC_ISER[n>>5] = 1 << (n & 0x1F) +#else +#define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \ + NVIC_ISER[n>>5] = 1 << (n & 0x1F) +#endif +#define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F) +#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F) + +/* Core Debug registers */ +#define DEMCR (*((volatile U32 *)0xE000EDFC)) + +/* ITM registers */ +#define ITM_CONTROL (*((volatile U32 *)0xE0000E80)) +#define ITM_ENABLE (*((volatile U32 *)0xE0000E00)) +#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078)) +#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C)) +#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C)) +#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C)) + +/* Variables */ +extern BIT dbg_msg; + +/* Functions */ +#ifdef __USE_EXCLUSIVE_ACCESS + #define rt_inc(p) while(__strex((__ldrex(p)+1),p)) + #define rt_dec(p) while(__strex((__ldrex(p)-1),p)) +#else + #define rt_inc(p) __disable_irq();(*p)++;__enable_irq(); + #define rt_dec(p) __disable_irq();(*p)--;__enable_irq(); +#endif + +__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) { + U32 cnt,c2; +#ifdef __USE_EXCLUSIVE_ACCESS + do { + if ((cnt = __ldrex(count)) == size) { + __clrex(); + return (cnt); } + } while (__strex(cnt+1, count)); + do { + c2 = (cnt = __ldrex(first)) + 1; + if (c2 == size) c2 = 0; + } while (__strex(c2, first)); +#else + __disable_irq(); + if ((cnt = *count) < size) { + *count = cnt+1; + c2 = (cnt = *first) + 1; + if (c2 == size) c2 = 0; + *first = c2; + } + __enable_irq (); +#endif + return (cnt); +} + +__inline static void rt_systick_init (void) { + NVIC_ST_RELOAD = os_trv; + NVIC_ST_CURRENT = 0; + NVIC_ST_CTRL = 0x0007; + NVIC_SYS_PRI3 |= 0xFF000000; +} + +__inline static void rt_svc_init (void) { +#if !(__TARGET_ARCH_6S_M) + int sh,prigroup; +#endif + NVIC_SYS_PRI3 |= 0x00FF0000; +#if (__TARGET_ARCH_6S_M) + NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000; +#else + sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000)); + prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07); + if (prigroup >= sh) { + sh = prigroup + 1; + } + NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF); +#endif +} + +extern void rt_set_PSP (U32 stack); +extern U32 rt_get_PSP (void); +extern void os_set_env (void); +extern void *_alloc_box (void *box_mem); +extern int _free_box (void *box_mem, void *box); + +extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body); +extern void rt_ret_val (P_TCB p_TCB, U32 v0); +extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1); + +extern void dbg_init (void); +extern void dbg_task_notify (P_TCB p_tcb, BOOL create); +extern void dbg_task_switch (U32 task_id); + +#ifdef DBG_MSG +#define DBG_INIT() dbg_init() +#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create) +#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new!=os_tsk.run)) \ + dbg_task_switch(task_id) +#else +#define DBG_INIT() +#define DBG_TASK_NOTIFY(p_tcb,create) +#define DBG_TASK_SWITCH(task_id) +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_List.c b/libraries/rtos/rtx_ca/rt_List.c new file mode 100644 index 0000000000..a337c86656 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_List.c @@ -0,0 +1,324 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_LIST.C + * Purpose: Functions for the management of different lists + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_System.h" +#include "rt_List.h" +#include "rt_Task.h" +#include "rt_Time.h" +#ifdef __CORTEX_A9 +#include "rt_HAL_CA.h" +#else +#include "rt_HAL_CM.h" +#endif + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +/* List head of chained ready tasks */ +struct OS_XCB os_rdy; +/* List head of chained delay tasks */ +struct OS_XCB os_dly; + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_put_prio -----------------------------------*/ + +void rt_put_prio (P_XCB p_CB, P_TCB p_task) { + /* Put task identified with "p_task" into list ordered by priority. */ + /* "p_CB" points to head of list; list has always an element at end with */ + /* a priority less than "p_task->prio". */ + P_TCB p_CB2; + U32 prio; + BOOL sem_mbx = __FALSE; + + if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) { + sem_mbx = __TRUE; + } + prio = p_task->prio; + p_CB2 = p_CB->p_lnk; + /* Search for an entry in the list */ + while (p_CB2 != NULL && prio <= p_CB2->prio) { + p_CB = (P_XCB)p_CB2; + p_CB2 = p_CB2->p_lnk; + } + /* Entry found, insert the task into the list */ + p_task->p_lnk = p_CB2; + p_CB->p_lnk = p_task; + if (sem_mbx) { + if (p_CB2 != NULL) { + p_CB2->p_rlnk = p_task; + } + p_task->p_rlnk = (P_TCB)p_CB; + } + else { + p_task->p_rlnk = NULL; + } +} + + +/*--------------------------- rt_get_first ----------------------------------*/ + +P_TCB rt_get_first (P_XCB p_CB) { + /* Get task at head of list: it is the task with highest priority. */ + /* "p_CB" points to head of list. */ + P_TCB p_first; + + p_first = p_CB->p_lnk; + p_CB->p_lnk = p_first->p_lnk; + if (p_CB->cb_type == SCB || p_CB->cb_type == MCB || p_CB->cb_type == MUCB) { + if (p_first->p_lnk != NULL) { + p_first->p_lnk->p_rlnk = (P_TCB)p_CB; + p_first->p_lnk = NULL; + } + p_first->p_rlnk = NULL; + } + else { + p_first->p_lnk = NULL; + } + return (p_first); +} + + +/*--------------------------- rt_put_rdy_first ------------------------------*/ + +void rt_put_rdy_first (P_TCB p_task) { + /* Put task identified with "p_task" at the head of the ready list. The */ + /* task must have at least a priority equal to highest priority in list. */ + p_task->p_lnk = os_rdy.p_lnk; + p_task->p_rlnk = NULL; + os_rdy.p_lnk = p_task; +} + + +/*--------------------------- rt_get_same_rdy_prio --------------------------*/ + +P_TCB rt_get_same_rdy_prio (void) { + /* Remove a task of same priority from ready list if any exists. Other- */ + /* wise return NULL. */ + P_TCB p_first; + + p_first = os_rdy.p_lnk; + if (p_first->prio == os_tsk.run->prio) { + os_rdy.p_lnk = os_rdy.p_lnk->p_lnk; + return (p_first); + } + return (NULL); +} + + +/*--------------------------- rt_resort_prio --------------------------------*/ + +void rt_resort_prio (P_TCB p_task) { + /* Re-sort ordered lists after the priority of 'p_task' has changed. */ + P_TCB p_CB; + + if (p_task->p_rlnk == NULL) { + if (p_task->state == READY) { + /* Task is chained into READY list. */ + p_CB = (P_TCB)&os_rdy; + goto res; + } + } + else { + p_CB = p_task->p_rlnk; + while (p_CB->cb_type == TCB) { + /* Find a header of this task chain list. */ + p_CB = p_CB->p_rlnk; + } +res:rt_rmv_list (p_task); + rt_put_prio ((P_XCB)p_CB, p_task); + } +} + + +/*--------------------------- rt_put_dly ------------------------------------*/ + +void rt_put_dly (P_TCB p_task, U16 delay) { + /* Put a task identified with "p_task" into chained delay wait list using */ + /* a delay value of "delay". */ + P_TCB p; + U32 delta,idelay = delay; + + p = (P_TCB)&os_dly; + if (p->p_dlnk == NULL) { + /* Delay list empty */ + delta = 0; + goto last; + } + delta = os_dly.delta_time; + while (delta < idelay) { + if (p->p_dlnk == NULL) { + /* End of list found */ +last: p_task->p_dlnk = NULL; + p->p_dlnk = p_task; + p_task->p_blnk = p; + p->delta_time = (U16)(idelay - delta); + p_task->delta_time = 0; + return; + } + p = p->p_dlnk; + delta += p->delta_time; + } + /* Right place found */ + p_task->p_dlnk = p->p_dlnk; + p->p_dlnk = p_task; + p_task->p_blnk = p; + if (p_task->p_dlnk != NULL) { + p_task->p_dlnk->p_blnk = p_task; + } + p_task->delta_time = (U16)(delta - idelay); + p->delta_time -= p_task->delta_time; +} + + +/*--------------------------- rt_dec_dly ------------------------------------*/ + +void rt_dec_dly (void) { + /* Decrement delta time of list head: remove tasks having a value of zero.*/ + P_TCB p_rdy; + + if (os_dly.p_dlnk == NULL) { + return; + } + os_dly.delta_time--; + while ((os_dly.delta_time == 0) && (os_dly.p_dlnk != NULL)) { + p_rdy = os_dly.p_dlnk; + if (p_rdy->p_rlnk != NULL) { + /* Task is really enqueued, remove task from semaphore/mailbox */ + /* timeout waiting list. */ + p_rdy->p_rlnk->p_lnk = p_rdy->p_lnk; + if (p_rdy->p_lnk != NULL) { + p_rdy->p_lnk->p_rlnk = p_rdy->p_rlnk; + p_rdy->p_lnk = NULL; + } + p_rdy->p_rlnk = NULL; + } + rt_put_prio (&os_rdy, p_rdy); + os_dly.delta_time = p_rdy->delta_time; + if (p_rdy->state == WAIT_ITV) { + /* Calculate the next time for interval wait. */ + p_rdy->delta_time = p_rdy->interval_time + (U16)os_time; + } + p_rdy->state = READY; + os_dly.p_dlnk = p_rdy->p_dlnk; + if (p_rdy->p_dlnk != NULL) { + p_rdy->p_dlnk->p_blnk = (P_TCB)&os_dly; + p_rdy->p_dlnk = NULL; + } + p_rdy->p_blnk = NULL; + } +} + + +/*--------------------------- rt_rmv_list -----------------------------------*/ + +void rt_rmv_list (P_TCB p_task) { + /* Remove task identified with "p_task" from ready, semaphore or mailbox */ + /* waiting list if enqueued. */ + P_TCB p_b; + + if (p_task->p_rlnk != NULL) { + /* A task is enqueued in semaphore / mailbox waiting list. */ + p_task->p_rlnk->p_lnk = p_task->p_lnk; + if (p_task->p_lnk != NULL) { + p_task->p_lnk->p_rlnk = p_task->p_rlnk; + } + return; + } + + p_b = (P_TCB)&os_rdy; + while (p_b != NULL) { + /* Search the ready list for task "p_task" */ + if (p_b->p_lnk == p_task) { + p_b->p_lnk = p_task->p_lnk; + return; + } + p_b = p_b->p_lnk; + } +} + + +/*--------------------------- rt_rmv_dly ------------------------------------*/ + +void rt_rmv_dly (P_TCB p_task) { + /* Remove task identified with "p_task" from delay list if enqueued. */ + P_TCB p_b; + + p_b = p_task->p_blnk; + if (p_b != NULL) { + /* Task is really enqueued */ + p_b->p_dlnk = p_task->p_dlnk; + if (p_task->p_dlnk != NULL) { + /* 'p_task' is in the middle of list */ + p_b->delta_time += p_task->delta_time; + p_task->p_dlnk->p_blnk = p_b; + p_task->p_dlnk = NULL; + } + else { + /* 'p_task' is at the end of list */ + p_b->delta_time = 0; + } + p_task->p_blnk = NULL; + } +} + + +/*--------------------------- rt_psq_enq ------------------------------------*/ + +void rt_psq_enq (OS_ID entry, U32 arg) { + /* Insert post service request "entry" into ps-queue. */ + U32 idx; + + idx = rt_inc_qi (os_psq->size, &os_psq->count, &os_psq->first); + if (idx < os_psq->size) { + os_psq->q[idx].id = entry; + os_psq->q[idx].arg = arg; + } + else { + os_error (OS_ERR_FIFO_OVF); + } +} + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_List.h b/libraries/rtos/rtx_ca/rt_List.h new file mode 100644 index 0000000000..c9cfe295ad --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_List.h @@ -0,0 +1,67 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_LIST.H + * Purpose: Functions for the management of different lists + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Definitions */ + +/* Values for 'cb_type' */ +#define TCB 0 +#define MCB 1 +#define SCB 2 +#define MUCB 3 +#define HCB 4 + +/* Variables */ +extern struct OS_XCB os_rdy; +extern struct OS_XCB os_dly; + +/* Functions */ +extern void rt_put_prio (P_XCB p_CB, P_TCB p_task); +extern P_TCB rt_get_first (P_XCB p_CB); +extern void rt_put_rdy_first (P_TCB p_task); +extern P_TCB rt_get_same_rdy_prio (void); +extern void rt_resort_prio (P_TCB p_task); +extern void rt_put_dly (P_TCB p_task, U16 delay); +extern void rt_dec_dly (void); +extern void rt_rmv_list (P_TCB p_task); +extern void rt_rmv_dly (P_TCB p_task); +extern void rt_psq_enq (OS_ID entry, U32 arg); + +/* This is a fast macro generating in-line code */ +#define rt_rdy_prio(void) (os_rdy.p_lnk->prio) + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Mailbox.c b/libraries/rtos/rtx_ca/rt_Mailbox.c new file mode 100644 index 0000000000..80f5a4d0b5 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Mailbox.c @@ -0,0 +1,296 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MAILBOX.C + * Purpose: Implements waits and wake-ups for mailbox messages + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_System.h" +#include "rt_List.h" +#include "rt_Mailbox.h" +#include "rt_MemBox.h" +#include "rt_Task.h" +#ifdef __CORTEX_A9 +#include "rt_HAL_CA.h" +#else +#include "rt_HAL_CM.h" +#endif + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_mbx_init -----------------------------------*/ + +void rt_mbx_init (OS_ID mailbox, U16 mbx_size) { + /* Initialize a mailbox */ + P_MCB p_MCB = mailbox; + + p_MCB->cb_type = MCB; + p_MCB->state = 0; + p_MCB->isr_st = 0; + p_MCB->p_lnk = NULL; + p_MCB->first = 0; + p_MCB->last = 0; + p_MCB->count = 0; + p_MCB->size = (mbx_size + sizeof(void *) - sizeof(struct OS_MCB)) / + (U32)sizeof (void *); +} + + +/*--------------------------- rt_mbx_send -----------------------------------*/ + +OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) { + /* Send message to a mailbox */ + P_MCB p_MCB = mailbox; + P_TCB p_TCB; + + if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 1)) { + /* A task is waiting for message */ + p_TCB = rt_get_first ((P_XCB)p_MCB); +#ifdef __CMSIS_RTOS + rt_ret_val2(p_TCB, 0x10/*osEventMessage*/, (U32)p_msg); +#else + *p_TCB->msg = p_msg; + rt_ret_val (p_TCB, OS_R_MBX); +#endif + rt_rmv_dly (p_TCB); + rt_dispatch (p_TCB); + } + else { + /* Store message in mailbox queue */ + if (p_MCB->count == p_MCB->size) { + /* No free message entry, wait for one. If message queue is full, */ + /* then no task is waiting for message. The 'p_MCB->p_lnk' list */ + /* pointer can now be reused for send message waits task list. */ + if (timeout == 0) { + return (OS_R_TMO); + } + if (p_MCB->p_lnk != NULL) { + rt_put_prio ((P_XCB)p_MCB, os_tsk.run); + } + else { + p_MCB->p_lnk = os_tsk.run; + os_tsk.run->p_lnk = NULL; + os_tsk.run->p_rlnk = (P_TCB)p_MCB; + /* Task is waiting to send a message */ + p_MCB->state = 2; + } + os_tsk.run->msg = p_msg; + rt_block (timeout, WAIT_MBX); + return (OS_R_TMO); + } + /* Yes, there is a free entry in a mailbox. */ + p_MCB->msg[p_MCB->first] = p_msg; + rt_inc (&p_MCB->count); + if (++p_MCB->first == p_MCB->size) { + p_MCB->first = 0; + } + } + return (OS_R_OK); +} + + +/*--------------------------- rt_mbx_wait -----------------------------------*/ + +OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout) { + /* Receive a message; possibly wait for it */ + P_MCB p_MCB = mailbox; + P_TCB p_TCB; + + /* If a message is available in the fifo buffer */ + /* remove it from the fifo buffer and return. */ + if (p_MCB->count) { + *message = p_MCB->msg[p_MCB->last]; + if (++p_MCB->last == p_MCB->size) { + p_MCB->last = 0; + } + if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2)) { + /* A task is waiting to send message */ + p_TCB = rt_get_first ((P_XCB)p_MCB); +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 0/*osOK*/); +#else + rt_ret_val(p_TCB, OS_R_OK); +#endif + p_MCB->msg[p_MCB->first] = p_TCB->msg; + if (++p_MCB->first == p_MCB->size) { + p_MCB->first = 0; + } + rt_rmv_dly (p_TCB); + rt_dispatch (p_TCB); + } + else { + rt_dec (&p_MCB->count); + } + return (OS_R_OK); + } + /* No message available: wait for one */ + if (timeout == 0) { + return (OS_R_TMO); + } + if (p_MCB->p_lnk != NULL) { + rt_put_prio ((P_XCB)p_MCB, os_tsk.run); + } + else { + p_MCB->p_lnk = os_tsk.run; + os_tsk.run->p_lnk = NULL; + os_tsk.run->p_rlnk = (P_TCB)p_MCB; + /* Task is waiting to receive a message */ + p_MCB->state = 1; + } + rt_block(timeout, WAIT_MBX); +#ifndef __CMSIS_RTOS + os_tsk.run->msg = message; +#endif + return (OS_R_TMO); +} + + +/*--------------------------- rt_mbx_check ----------------------------------*/ + +OS_RESULT rt_mbx_check (OS_ID mailbox) { + /* Check for free space in a mailbox. Returns the number of messages */ + /* that can be stored to a mailbox. It returns 0 when mailbox is full. */ + P_MCB p_MCB = mailbox; + + return (p_MCB->size - p_MCB->count); +} + + +/*--------------------------- isr_mbx_send ----------------------------------*/ + +void isr_mbx_send (OS_ID mailbox, void *p_msg) { + /* Same function as "os_mbx_send", but to be called by ISRs. */ + P_MCB p_MCB = mailbox; + + rt_psq_enq (p_MCB, (U32)p_msg); + rt_psh_req (); +} + + +/*--------------------------- isr_mbx_receive -------------------------------*/ + +OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message) { + /* Receive a message in the interrupt function. The interrupt function */ + /* should not wait for a message since this would block the rtx os. */ + P_MCB p_MCB = mailbox; + + if (p_MCB->count) { + /* A message is available in the fifo buffer. */ + *message = p_MCB->msg[p_MCB->last]; + if (p_MCB->state == 2) { + /* A task is locked waiting to send message */ + rt_psq_enq (p_MCB, 0); + rt_psh_req (); + } + rt_dec (&p_MCB->count); + if (++p_MCB->last == p_MCB->size) { + p_MCB->last = 0; + } + return (OS_R_MBX); + } + return (OS_R_OK); +} + + +/*--------------------------- rt_mbx_psh ------------------------------------*/ + +void rt_mbx_psh (P_MCB p_CB, void *p_msg) { + /* Store the message to the mailbox queue or pass it to task directly. */ + P_TCB p_TCB; + void *mem; + + if (p_CB->p_lnk != NULL) switch (p_CB->state) { +#ifdef __CMSIS_RTOS + case 3: + /* Task is waiting to allocate memory, remove it from the waiting list */ + mem = rt_alloc_box(p_msg); + if (mem == NULL) break; + p_TCB = rt_get_first ((P_XCB)p_CB); + rt_ret_val(p_TCB, (U32)mem); + p_TCB->state = READY; + rt_rmv_dly (p_TCB); + rt_put_prio (&os_rdy, p_TCB); + break; +#endif + case 2: + /* Task is waiting to send a message, remove it from the waiting list */ + p_TCB = rt_get_first ((P_XCB)p_CB); +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 0/*osOK*/); +#else + rt_ret_val(p_TCB, OS_R_OK); +#endif + p_CB->msg[p_CB->first] = p_TCB->msg; + rt_inc (&p_CB->count); + if (++p_CB->first == p_CB->size) { + p_CB->first = 0; + } + p_TCB->state = READY; + rt_rmv_dly (p_TCB); + rt_put_prio (&os_rdy, p_TCB); + break; + case 1: + /* Task is waiting for a message, pass the message to the task directly */ + p_TCB = rt_get_first ((P_XCB)p_CB); +#ifdef __CMSIS_RTOS + rt_ret_val2(p_TCB, 0x10/*osEventMessage*/, (U32)p_msg); +#else + *p_TCB->msg = p_msg; + rt_ret_val (p_TCB, OS_R_MBX); +#endif + p_TCB->state = READY; + rt_rmv_dly (p_TCB); + rt_put_prio (&os_rdy, p_TCB); + break; + } else { + /* No task is waiting for a message, store it to the mailbox queue */ + if (p_CB->count < p_CB->size) { + p_CB->msg[p_CB->first] = p_msg; + rt_inc (&p_CB->count); + if (++p_CB->first == p_CB->size) { + p_CB->first = 0; + } + } + else { + os_error (OS_ERR_MBX_OVF); + } + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Mailbox.h b/libraries/rtos/rtx_ca/rt_Mailbox.h new file mode 100644 index 0000000000..06a20c0fca --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Mailbox.h @@ -0,0 +1,48 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MAILBOX.H + * Purpose: Implements waits and wake-ups for mailbox messages + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Functions */ +extern void rt_mbx_init (OS_ID mailbox, U16 mbx_size); +extern OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout); +extern OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout); +extern OS_RESULT rt_mbx_check (OS_ID mailbox); +extern void isr_mbx_send (OS_ID mailbox, void *p_msg); +extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message); +extern void rt_mbx_psh (P_MCB p_CB, void *p_msg); + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_MemBox.c b/libraries/rtos/rtx_ca/rt_MemBox.c new file mode 100644 index 0000000000..a34278379a --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_MemBox.c @@ -0,0 +1,170 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MEMBOX.C + * Purpose: Interface functions for fixed memory block management system + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_System.h" +#include "rt_MemBox.h" +#ifdef __CORTEX_A9 +#include "rt_HAL_CA.h" +#else +#include "rt_HAL_CM.h" +#endif + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- _init_box -------------------------------------*/ + +int _init_box (void *box_mem, U32 box_size, U32 blk_size) { + /* Initialize memory block system, returns 0 if OK, 1 if fails. */ + void *end; + void *blk; + void *next; + U32 sizeof_bm; + + /* Create memory structure. */ + if (blk_size & BOX_ALIGN_8) { + /* Memory blocks 8-byte aligned. */ + blk_size = ((blk_size & ~BOX_ALIGN_8) + 7) & ~7; + sizeof_bm = (sizeof (struct OS_BM) + 7) & ~7; + } + else { + /* Memory blocks 4-byte aligned. */ + blk_size = (blk_size + 3) & ~3; + sizeof_bm = sizeof (struct OS_BM); + } + if (blk_size == 0) { + return (1); + } + if ((blk_size + sizeof_bm) > box_size) { + return (1); + } + /* Create a Memory structure. */ + blk = ((U8 *) box_mem) + sizeof_bm; + ((P_BM) box_mem)->free = blk; + end = ((U8 *) box_mem) + box_size; + ((P_BM) box_mem)->end = end; + ((P_BM) box_mem)->blk_size = blk_size; + + /* Link all free blocks using offsets. */ + end = ((U8 *) end) - blk_size; + while (1) { + next = ((U8 *) blk) + blk_size; + if (next > end) break; + *((void **)blk) = next; + blk = next; + } + /* end marker */ + *((void **)blk) = 0; + return (0); +} + +/*--------------------------- rt_alloc_box ----------------------------------*/ + +void *rt_alloc_box (void *box_mem) { + /* Allocate a memory block and return start address. */ + void **free; +#ifndef __USE_EXCLUSIVE_ACCESS + int irq_dis; + + irq_dis = __disable_irq (); + free = ((P_BM) box_mem)->free; + if (free) { + ((P_BM) box_mem)->free = *free; + } + if (!irq_dis) __enable_irq (); +#else + do { + if ((free = (void **)__ldrex(&((P_BM) box_mem)->free)) == 0) { + __clrex(); + break; + } + } while (__strex((U32)*free, &((P_BM) box_mem)->free)); +#endif + return (free); +} + + +/*--------------------------- _calloc_box -----------------------------------*/ + +void *_calloc_box (void *box_mem) { + /* Allocate a 0-initialized memory block and return start address. */ + void *free; + U32 *p; + U32 i; + + free = _alloc_box (box_mem); + if (free) { + p = free; + for (i = ((P_BM) box_mem)->blk_size; i; i -= 4) { + *p = 0; + p++; + } + } + return (free); +} + + +/*--------------------------- rt_free_box -----------------------------------*/ + +int rt_free_box (void *box_mem, void *box) { + /* Free a memory block, returns 0 if OK, 1 if box does not belong to box_mem */ +#ifndef __USE_EXCLUSIVE_ACCESS + int irq_dis; +#endif + + if (box < box_mem || box >= ((P_BM) box_mem)->end) { + return (1); + } + +#ifndef __USE_EXCLUSIVE_ACCESS + irq_dis = __disable_irq (); + *((void **)box) = ((P_BM) box_mem)->free; + ((P_BM) box_mem)->free = box; + if (!irq_dis) __enable_irq (); +#else + do { + *((void **)box) = (void *)__ldrex(&((P_BM) box_mem)->free); + } while (__strex ((U32)box, &((P_BM) box_mem)->free)); +#endif + return (0); +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_MemBox.h b/libraries/rtos/rtx_ca/rt_MemBox.h new file mode 100644 index 0000000000..52f150f138 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_MemBox.h @@ -0,0 +1,46 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MEMBOX.H + * Purpose: Interface functions for fixed memory block management system + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Functions */ +#define rt_init_box _init_box +#define rt_calloc_box _calloc_box +extern int _init_box (void *box_mem, U32 box_size, U32 blk_size); +extern void *rt_alloc_box (void *box_mem); +extern void * _calloc_box (void *box_mem); +extern int rt_free_box (void *box_mem, void *box); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Memory.c b/libraries/rtos/rtx_ca/rt_Memory.c new file mode 100644 index 0000000000..69d85f33d4 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Memory.c @@ -0,0 +1,140 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MEMORY.C + * Purpose: Interface functions for Dynamic Memory Management System + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "rt_Memory.h" + + +/* Functions */ + +// Initialize Dynamic Memory pool +// Parameters: +// pool: Pointer to memory pool +// size: Size of memory pool in bytes +// Return: 0 - OK, 1 - Error + +int rt_init_mem (void *pool, U32 size) { + MEMP *ptr; + + if ((pool == NULL) || (size < sizeof(MEMP))) return (1); + + ptr = (MEMP *)pool; + ptr->next = (MEMP *)((U32)pool + size - sizeof(MEMP *)); + ptr->next->next = NULL; + ptr->len = 0; + + return (0); +} + +// Allocate Memory from Memory pool +// Parameters: +// pool: Pointer to memory pool +// size: Size of memory in bytes to allocate +// Return: Pointer to allocated memory + +void *rt_alloc_mem (void *pool, U32 size) { + MEMP *p, *p_search, *p_new; + U32 hole_size; + + if ((pool == NULL) || (size == 0)) return NULL; + + /* Add header offset to 'size' */ + size += sizeof(MEMP); + /* Make sure that block is 4-byte aligned */ + size = (size + 3) & ~3; + + p_search = (MEMP *)pool; + while (1) { + hole_size = (U32)p_search->next - (U32)p_search; + hole_size -= p_search->len; + /* Check if hole size is big enough */ + if (hole_size >= size) break; + p_search = p_search->next; + if (p_search->next == NULL) { + /* Failed, we are at the end of the list */ + return NULL; + } + } + + if (p_search->len == 0) { + /* No block is allocated, set the Length of the first element */ + p_search->len = size; + p = (MEMP *)(((U32)p_search) + sizeof(MEMP)); + } else { + /* Insert new list element into the memory list */ + p_new = (MEMP *)((U32)p_search + p_search->len); + p_new->next = p_search->next; + p_new->len = size; + p_search->next = p_new; + p = (MEMP *)(((U32)p_new) + sizeof(MEMP)); + } + + return (p); +} + +// Free Memory and return it to Memory pool +// Parameters: +// pool: Pointer to memory pool +// mem: Pointer to memory to free +// Return: 0 - OK, 1 - Error + +int rt_free_mem (void *pool, void *mem) { + MEMP *p_search, *p_prev, *p_return; + + if ((pool == NULL) || (mem == NULL)) return (1); + + p_return = (MEMP *)((U32)mem - sizeof(MEMP)); + + /* Set list header */ + p_prev = NULL; + p_search = (MEMP *)pool; + while (p_search != p_return) { + p_prev = p_search; + p_search = p_search->next; + if (p_search == NULL) { + /* Valid Memory block not found */ + return (1); + } + } + + if (p_prev == NULL) { + /* First block to be released, only set length to 0 */ + p_search->len = 0; + } else { + /* Discard block from chain list */ + p_prev->next = p_search->next; + } + + return (0); +} diff --git a/libraries/rtos/rtx_ca/rt_Memory.h b/libraries/rtos/rtx_ca/rt_Memory.h new file mode 100644 index 0000000000..337a36065e --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Memory.h @@ -0,0 +1,44 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MEMORY.H + * Purpose: Interface functions for Dynamic Memory Management System + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Types */ +typedef struct mem { /* << Memory Pool management struct >> */ + struct mem *next; /* Next Memory Block in the list */ + U32 len; /* Length of data block */ +} MEMP; + +/* Functions */ +extern int rt_init_mem (void *pool, U32 size); +extern void *rt_alloc_mem (void *pool, U32 size); +extern int rt_free_mem (void *pool, void *mem); diff --git a/libraries/rtos/rtx_ca/rt_Mutex.c b/libraries/rtos/rtx_ca/rt_Mutex.c new file mode 100644 index 0000000000..41aa134e78 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Mutex.c @@ -0,0 +1,204 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MUTEX.C + * Purpose: Implements mutex synchronization objects + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_List.h" +#include "rt_Task.h" +#include "rt_Mutex.h" +#ifdef __CORTEX_A9 +#include "rt_HAL_CA.h" +#else +#include "rt_HAL_CM.h" +#endif + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_mut_init -----------------------------------*/ + +void rt_mut_init (OS_ID mutex) { + /* Initialize a mutex object */ + P_MUCB p_MCB = mutex; + + p_MCB->cb_type = MUCB; + p_MCB->prio = 0; + p_MCB->level = 0; + p_MCB->p_lnk = NULL; + p_MCB->owner = NULL; +} + + +/*--------------------------- rt_mut_delete ---------------------------------*/ + +#ifdef __CMSIS_RTOS +OS_RESULT rt_mut_delete (OS_ID mutex) { + /* Delete a mutex object */ + P_MUCB p_MCB = mutex; + P_TCB p_TCB; + + __DMB(); + /* Restore owner task's priority. */ + if (p_MCB->level != 0) { + p_MCB->owner->prio = p_MCB->prio; + if (p_MCB->owner != os_tsk.run) { + rt_resort_prio (p_MCB->owner); + } + } + + while (p_MCB->p_lnk != NULL) { + /* A task is waiting for mutex. */ + p_TCB = rt_get_first ((P_XCB)p_MCB); + rt_ret_val(p_TCB, 0/*osOK*/); + rt_rmv_dly(p_TCB); + p_TCB->state = READY; + rt_put_prio (&os_rdy, p_TCB); + } + + if (os_rdy.p_lnk && (os_rdy.p_lnk->prio > os_tsk.run->prio)) { + /* preempt running task */ + rt_put_prio (&os_rdy, os_tsk.run); + os_tsk.run->state = READY; + rt_dispatch (NULL); + } + + p_MCB->cb_type = 0; + + return (OS_R_OK); +} +#endif + + +/*--------------------------- rt_mut_release --------------------------------*/ + +OS_RESULT rt_mut_release (OS_ID mutex) { + /* Release a mutex object */ + P_MUCB p_MCB = mutex; + P_TCB p_TCB; + + if (p_MCB->level == 0 || p_MCB->owner != os_tsk.run) { + /* Unbalanced mutex release or task is not the owner */ + return (OS_R_NOK); + } + __DMB(); + if (--p_MCB->level != 0) { + return (OS_R_OK); + } + /* Restore owner task's priority. */ + os_tsk.run->prio = p_MCB->prio; + if (p_MCB->p_lnk != NULL) { + /* A task is waiting for mutex. */ + p_TCB = rt_get_first ((P_XCB)p_MCB); +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 0/*osOK*/); +#else + rt_ret_val(p_TCB, OS_R_MUT); +#endif + rt_rmv_dly (p_TCB); + /* A waiting task becomes the owner of this mutex. */ + p_MCB->level = 1; + p_MCB->owner = p_TCB; + p_MCB->prio = p_TCB->prio; + /* Priority inversion, check which task continues. */ + if (os_tsk.run->prio >= rt_rdy_prio()) { + rt_dispatch (p_TCB); + } + else { + /* Ready task has higher priority than running task. */ + rt_put_prio (&os_rdy, os_tsk.run); + rt_put_prio (&os_rdy, p_TCB); + os_tsk.run->state = READY; + p_TCB->state = READY; + rt_dispatch (NULL); + } + } + else { + /* Check if own priority raised by priority inversion. */ + if (rt_rdy_prio() > os_tsk.run->prio) { + rt_put_prio (&os_rdy, os_tsk.run); + os_tsk.run->state = READY; + rt_dispatch (NULL); + } + } + return (OS_R_OK); +} + + +/*--------------------------- rt_mut_wait -----------------------------------*/ + +OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout) { + /* Wait for a mutex, continue when mutex is free. */ + P_MUCB p_MCB = mutex; + + if (p_MCB->level == 0) { + p_MCB->owner = os_tsk.run; + p_MCB->prio = os_tsk.run->prio; + goto inc; + } + if (p_MCB->owner == os_tsk.run) { + /* OK, running task is the owner of this mutex. */ +inc:p_MCB->level++; + __DMB(); + return (OS_R_OK); + } + /* Mutex owned by another task, wait until released. */ + if (timeout == 0) { + return (OS_R_TMO); + } + /* Raise the owner task priority if lower than current priority. */ + /* This priority inversion is called priority inheritance. */ + if (p_MCB->prio < os_tsk.run->prio) { + p_MCB->owner->prio = os_tsk.run->prio; + rt_resort_prio (p_MCB->owner); + } + if (p_MCB->p_lnk != NULL) { + rt_put_prio ((P_XCB)p_MCB, os_tsk.run); + } + else { + p_MCB->p_lnk = os_tsk.run; + os_tsk.run->p_lnk = NULL; + os_tsk.run->p_rlnk = (P_TCB)p_MCB; + } + rt_block(timeout, WAIT_MUT); + return (OS_R_TMO); +} + + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Mutex.h b/libraries/rtos/rtx_ca/rt_Mutex.h new file mode 100644 index 0000000000..4f6b0de8a0 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Mutex.h @@ -0,0 +1,44 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_MUTEX.H + * Purpose: Implements mutex synchronization objects + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Functions */ +extern void rt_mut_init (OS_ID mutex); +extern OS_RESULT rt_mut_delete (OS_ID mutex); +extern OS_RESULT rt_mut_release (OS_ID mutex); +extern OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Robin.c b/libraries/rtos/rtx_ca/rt_Robin.c new file mode 100644 index 0000000000..a8182ce618 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Robin.c @@ -0,0 +1,88 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_ROBIN.C + * Purpose: Round Robin Task switching + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_List.h" +#include "rt_Task.h" +#include "rt_Time.h" +#include "rt_Robin.h" +#ifdef __CORTEX_A9 +#include "rt_HAL_CA.h" +#else +#include "rt_HAL_CM.h" +#endif + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +struct OS_ROBIN os_robin; + + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- rt_init_robin ---------------------------------*/ + +__weak void rt_init_robin (void) { + /* Initialize Round Robin variables. */ + os_robin.task = NULL; + os_robin.tout = (U16)os_rrobin; +} + +/*--------------------------- rt_chk_robin ----------------------------------*/ + +__weak void rt_chk_robin (void) { + /* Check if Round Robin timeout expired and switch to the next ready task.*/ + P_TCB p_new; + + if (os_robin.task != os_rdy.p_lnk) { + /* New task was suspended, reset Round Robin timeout. */ + os_robin.task = os_rdy.p_lnk; + os_robin.time = (U16)os_time + os_robin.tout - 1; + } + if (os_robin.time == (U16)os_time) { + /* Round Robin timeout has expired, swap Robin tasks. */ + os_robin.task = NULL; + p_new = rt_get_first (&os_rdy); + rt_put_prio ((P_XCB)&os_rdy, p_new); + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Robin.h b/libraries/rtos/rtx_ca/rt_Robin.h new file mode 100644 index 0000000000..eb665ad6ef --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Robin.h @@ -0,0 +1,45 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_ROBIN.H + * Purpose: Round Robin Task switching definitions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Variables */ +extern struct OS_ROBIN os_robin; + +/* Functions */ +extern void rt_init_robin (void); +extern void rt_chk_robin (void); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Semaphore.c b/libraries/rtos/rtx_ca/rt_Semaphore.c new file mode 100644 index 0000000000..adf1b744bb --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Semaphore.c @@ -0,0 +1,191 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_SEMAPHORE.C + * Purpose: Implements binary and counting semaphores + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_System.h" +#include "rt_List.h" +#include "rt_Task.h" +#include "rt_Semaphore.h" +#ifdef __CORTEX_A9 +#include "rt_HAL_CA.h" +#else +#include "rt_HAL_CM.h" +#endif + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_sem_init -----------------------------------*/ + +void rt_sem_init (OS_ID semaphore, U16 token_count) { + /* Initialize a semaphore */ + P_SCB p_SCB = semaphore; + + p_SCB->cb_type = SCB; + p_SCB->p_lnk = NULL; + p_SCB->tokens = token_count; +} + + +/*--------------------------- rt_sem_delete ---------------------------------*/ + +#ifdef __CMSIS_RTOS +OS_RESULT rt_sem_delete (OS_ID semaphore) { + /* Delete semaphore */ + P_SCB p_SCB = semaphore; + P_TCB p_TCB; + + __DMB(); + while (p_SCB->p_lnk != NULL) { + /* A task is waiting for token */ + p_TCB = rt_get_first ((P_XCB)p_SCB); + rt_ret_val(p_TCB, 0); + rt_rmv_dly(p_TCB); + p_TCB->state = READY; + rt_put_prio (&os_rdy, p_TCB); + } + + if (os_rdy.p_lnk && (os_rdy.p_lnk->prio > os_tsk.run->prio)) { + /* preempt running task */ + rt_put_prio (&os_rdy, os_tsk.run); + os_tsk.run->state = READY; + rt_dispatch (NULL); + } + + p_SCB->cb_type = 0; + + return (OS_R_OK); +} +#endif + + +/*--------------------------- rt_sem_send -----------------------------------*/ + +OS_RESULT rt_sem_send (OS_ID semaphore) { + /* Return a token to semaphore */ + P_SCB p_SCB = semaphore; + P_TCB p_TCB; + + __DMB(); + if (p_SCB->p_lnk != NULL) { + /* A task is waiting for token */ + p_TCB = rt_get_first ((P_XCB)p_SCB); +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 1); +#else + rt_ret_val(p_TCB, OS_R_SEM); +#endif + rt_rmv_dly (p_TCB); + rt_dispatch (p_TCB); + } + else { + /* Store token. */ + p_SCB->tokens++; + } + return (OS_R_OK); +} + + +/*--------------------------- rt_sem_wait -----------------------------------*/ + +OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout) { + /* Obtain a token; possibly wait for it */ + P_SCB p_SCB = semaphore; + + if (p_SCB->tokens) { + p_SCB->tokens--; + __DMB(); + return (OS_R_OK); + } + /* No token available: wait for one */ + if (timeout == 0) { + return (OS_R_TMO); + } + if (p_SCB->p_lnk != NULL) { + rt_put_prio ((P_XCB)p_SCB, os_tsk.run); + } + else { + p_SCB->p_lnk = os_tsk.run; + os_tsk.run->p_lnk = NULL; + os_tsk.run->p_rlnk = (P_TCB)p_SCB; + } + rt_block(timeout, WAIT_SEM); + return (OS_R_TMO); +} + + +/*--------------------------- isr_sem_send ----------------------------------*/ + +void isr_sem_send (OS_ID semaphore) { + /* Same function as "os_sem"send", but to be called by ISRs */ + P_SCB p_SCB = semaphore; + + rt_psq_enq (p_SCB, 0); + rt_psh_req (); +} + + +/*--------------------------- rt_sem_psh ------------------------------------*/ + +void rt_sem_psh (P_SCB p_CB) { + /* Check if task has to be waken up */ + P_TCB p_TCB; + + __DMB(); + if (p_CB->p_lnk != NULL) { + /* A task is waiting for token */ + p_TCB = rt_get_first ((P_XCB)p_CB); + rt_rmv_dly (p_TCB); + p_TCB->state = READY; +#ifdef __CMSIS_RTOS + rt_ret_val(p_TCB, 1); +#else + rt_ret_val(p_TCB, OS_R_SEM); +#endif + rt_put_prio (&os_rdy, p_TCB); + } + else { + /* Store token */ + p_CB->tokens++; + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Semaphore.h b/libraries/rtos/rtx_ca/rt_Semaphore.h new file mode 100644 index 0000000000..5b04480282 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Semaphore.h @@ -0,0 +1,46 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_SEMAPHORE.H + * Purpose: Implements binary and counting semaphores + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Functions */ +extern void rt_sem_init (OS_ID semaphore, U16 token_count); +extern OS_RESULT rt_sem_delete(OS_ID semaphore); +extern OS_RESULT rt_sem_send (OS_ID semaphore); +extern OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout); +extern void isr_sem_send (OS_ID semaphore); +extern void rt_sem_psh (P_SCB p_CB); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_System.c b/libraries/rtos/rtx_ca/rt_System.c new file mode 100644 index 0000000000..a3942c3510 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_System.c @@ -0,0 +1,304 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_SYSTEM.C + * Purpose: System Task Manager + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_Task.h" +#include "rt_System.h" +#include "rt_Event.h" +#include "rt_List.h" +#include "rt_Mailbox.h" +#include "rt_Semaphore.h" +#include "rt_Time.h" +#include "rt_Timer.h" +#include "rt_Robin.h" +#ifdef __CORTEX_A9 +#include "rt_HAL_CA.h" +#else +#include "rt_HAL_CM.h" +#endif + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +int os_tick_irqn; + +/*---------------------------------------------------------------------------- + * Local Variables + *---------------------------------------------------------------------------*/ + +static volatile BIT os_lock; +static volatile BIT os_psh_flag; +#ifndef __CORTEX_A9 +static U8 pend_flags; +#endif +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +#if defined (__CC_ARM) +__asm void $$RTX$$version (void) { + /* Export a version number symbol for a version control. */ + + EXPORT __RL_RTX_VER + +__RL_RTX_VER EQU 0x450 +} +#endif + + +/*--------------------------- rt_suspend ------------------------------------*/ + +U32 rt_suspend (void) { + /* Suspend OS scheduler */ + U32 delta = 0xFFFF; + + rt_tsk_lock(); + + if (os_dly.p_dlnk) { + delta = os_dly.delta_time; + } +#ifndef __CMSIS_RTOS + if (os_tmr.next) { + if (os_tmr.tcnt < delta) delta = os_tmr.tcnt; + } +#endif + + return (delta); +} + + +/*--------------------------- rt_resume -------------------------------------*/ + +void rt_resume (U32 sleep_time) { + /* Resume OS scheduler after suspend */ + P_TCB next; + U32 delta; + + os_tsk.run->state = READY; + rt_put_rdy_first (os_tsk.run); + + os_robin.task = NULL; + + /* Update delays. */ + if (os_dly.p_dlnk) { + delta = sleep_time; + if (delta >= os_dly.delta_time) { + delta -= os_dly.delta_time; + os_time += os_dly.delta_time; + os_dly.delta_time = 1; + while (os_dly.p_dlnk) { + rt_dec_dly(); + if (delta == 0) break; + delta--; + os_time++; + } + } else { + os_time += delta; + os_dly.delta_time -= delta; + } + } else { + os_time += sleep_time; + } + +#ifndef __CMSIS_RTOS + /* Check the user timers. */ + if (os_tmr.next) { + delta = sleep_time; + if (delta >= os_tmr.tcnt) { + delta -= os_tmr.tcnt; + os_tmr.tcnt = 1; + while (os_tmr.next) { + rt_tmr_tick(); + if (delta == 0) break; + delta--; + } + } else { + os_tmr.tcnt -= delta; + } + } +#endif + + /* Switch back to highest ready task */ + next = rt_get_first (&os_rdy); + rt_switch_req (next); + + rt_tsk_unlock(); +} + + +/*--------------------------- rt_tsk_lock -----------------------------------*/ + +void rt_tsk_lock (void) { + /* Prevent task switching by locking out scheduler */ + if (os_tick_irqn < 0) { + OS_LOCK(); + os_lock = __TRUE; + OS_UNPEND (&pend_flags); + } else { + OS_X_LOCK(os_tick_irqn); + os_lock = __TRUE; + OS_X_UNPEND (&pend_flags); + } +} + + +/*--------------------------- rt_tsk_unlock ---------------------------------*/ + +void rt_tsk_unlock (void) { + /* Unlock scheduler and re-enable task switching */ + if (os_tick_irqn < 0) { + OS_UNLOCK(); + os_lock = __FALSE; + OS_PEND (pend_flags, os_psh_flag); + os_psh_flag = __FALSE; + } else { + OS_X_UNLOCK(os_tick_irqn); + os_lock = __FALSE; + OS_X_PEND (pend_flags, os_psh_flag); + os_psh_flag = __FALSE; + } +} + + +/*--------------------------- rt_psh_req ------------------------------------*/ + +void rt_psh_req (void) { + /* Initiate a post service handling request if required. */ + if (os_lock == __FALSE) { + OS_PEND_IRQ (); + } + else { + os_psh_flag = __TRUE; + } +} + + +/*--------------------------- rt_pop_req ------------------------------------*/ + +void rt_pop_req (void) { + /* Process an ISR post service requests. */ + struct OS_XCB *p_CB; + P_TCB next; + U32 idx; + + os_tsk.run->state = READY; + rt_put_rdy_first (os_tsk.run); + + idx = os_psq->last; + while (os_psq->count) { + p_CB = os_psq->q[idx].id; + if (p_CB->cb_type == TCB) { + /* Is of TCB type */ + rt_evt_psh ((P_TCB)p_CB, (U16)os_psq->q[idx].arg); + } + else if (p_CB->cb_type == MCB) { + /* Is of MCB type */ + rt_mbx_psh ((P_MCB)p_CB, (void *)os_psq->q[idx].arg); + } + else { + /* Must be of SCB type */ + rt_sem_psh ((P_SCB)p_CB); + } + if (++idx == os_psq->size) idx = 0; + rt_dec (&os_psq->count); + } + os_psq->last = idx; + + next = rt_get_first (&os_rdy); + rt_switch_req (next); +} + + +/*--------------------------- os_tick_init ----------------------------------*/ + +__weak int os_tick_init (void) { + /* Initialize SysTick timer as system tick timer. */ + rt_systick_init (); + return (-1); /* Return IRQ number of SysTick timer */ +} + + +/*--------------------------- os_tick_irqack --------------------------------*/ + +__weak void os_tick_irqack (void) { + /* Acknowledge timer interrupt. */ +} + + +/*--------------------------- rt_systick ------------------------------------*/ + +extern void sysTimerTick(void); + +void rt_systick (void) { + /* Check for system clock update, suspend running task. */ + P_TCB next; + + os_tsk.run->state = READY; + rt_put_rdy_first (os_tsk.run); + + /* Check Round Robin timeout. */ + rt_chk_robin (); + + /* Update delays. */ + os_time++; + rt_dec_dly (); + + /* Check the user timers. */ +#ifdef __CMSIS_RTOS + sysTimerTick(); +#else + rt_tmr_tick (); +#endif + + /* Switch back to highest ready task */ + next = rt_get_first (&os_rdy); + rt_switch_req (next); +} + +/*--------------------------- rt_stk_check ----------------------------------*/ + +__weak void rt_stk_check (void) { + /* Check for stack overflow. */ + if ((os_tsk.run->tsk_stack < (U32)os_tsk.run->stack) || + (os_tsk.run->stack[0] != MAGIC_WORD)) { + os_error (OS_ERR_STK_OVF); + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_System.h b/libraries/rtos/rtx_ca/rt_System.h new file mode 100644 index 0000000000..aff9aa662d --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_System.h @@ -0,0 +1,52 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_SYSTEM.H + * Purpose: System Task Manager definitions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Variables */ +#define os_psq ((P_PSQ)&os_fifo) +extern int os_tick_irqn; + +/* Functions */ +extern U32 rt_suspend (void); +extern void rt_resume (U32 sleep_time); +extern void rt_tsk_lock (void); +extern void rt_tsk_unlock (void); +extern void rt_psh_req (void); +extern void rt_pop_req (void); +extern void rt_systick (void); +extern void rt_stk_check (void); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Task.c b/libraries/rtos/rtx_ca/rt_Task.c new file mode 100644 index 0000000000..ae6e600752 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Task.c @@ -0,0 +1,372 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TASK.C + * Purpose: Task functions and system start up. + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_System.h" +#include "rt_Task.h" +#include "rt_List.h" +#include "rt_MemBox.h" +#include "rt_Robin.h" +#ifdef __CORTEX_A9 +#include "rt_HAL_CA.h" +#else +#include "rt_HAL_CM.h" +#endif + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +/* Running and next task info. */ +struct OS_TSK os_tsk; + +/* Task Control Blocks of idle demon */ +struct OS_TCB os_idle_TCB; + + +/*---------------------------------------------------------------------------- + * Local Functions + *---------------------------------------------------------------------------*/ + +static OS_TID rt_get_TID (void) { + U32 tid; + + for (tid = 1; tid <= os_maxtaskrun; tid++) { + if (os_active_TCB[tid-1] == NULL) { + return ((OS_TID)tid); + } + } + return (0); +} + + +/*--------------------------- rt_init_context -------------------------------*/ + +static void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body) { + /* Initialize general part of the Task Control Block. */ + p_TCB->cb_type = TCB; + p_TCB->state = READY; + p_TCB->prio = priority; + p_TCB->p_lnk = NULL; + p_TCB->p_rlnk = NULL; + p_TCB->p_dlnk = NULL; + p_TCB->p_blnk = NULL; + p_TCB->delta_time = 0; + p_TCB->interval_time = 0; + p_TCB->events = 0; + p_TCB->waits = 0; + p_TCB->stack_frame = 0; + + if (p_TCB->priv_stack == 0) { + /* Allocate the memory space for the stack. */ + p_TCB->stack = rt_alloc_box (mp_stk); + } + rt_init_stack (p_TCB, task_body); +} + + +/*--------------------------- rt_switch_req ---------------------------------*/ + +void rt_switch_req (P_TCB p_new) { + /* Switch to next task (identified by "p_new"). */ + os_tsk.new = p_new; + p_new->state = RUNNING; + DBG_TASK_SWITCH(p_new->task_id); +} + + +/*--------------------------- rt_dispatch -----------------------------------*/ + +void rt_dispatch (P_TCB next_TCB) { + /* Dispatch next task if any identified or dispatch highest ready task */ + /* "next_TCB" identifies a task to run or has value NULL (=no next task) */ + if (next_TCB == NULL) { + /* Running task was blocked: continue with highest ready task */ + next_TCB = rt_get_first (&os_rdy); + rt_switch_req (next_TCB); + } + else { + /* Check which task continues */ + if (next_TCB->prio > os_tsk.run->prio) { + /* preempt running task */ + rt_put_rdy_first (os_tsk.run); + os_tsk.run->state = READY; + rt_switch_req (next_TCB); + } + else { + /* put next task into ready list, no task switch takes place */ + next_TCB->state = READY; + rt_put_prio (&os_rdy, next_TCB); + } + } +} + + +/*--------------------------- rt_block --------------------------------------*/ + +void rt_block (U16 timeout, U8 block_state) { + /* Block running task and choose next ready task. */ + /* "timeout" sets a time-out value or is 0xffff (=no time-out). */ + /* "block_state" defines the appropriate task state */ + P_TCB next_TCB; + + if (timeout) { + if (timeout < 0xffff) { + rt_put_dly (os_tsk.run, timeout); + } + os_tsk.run->state = block_state; + next_TCB = rt_get_first (&os_rdy); + rt_switch_req (next_TCB); + } +} + + +/*--------------------------- rt_tsk_pass -----------------------------------*/ + +void rt_tsk_pass (void) { + /* Allow tasks of same priority level to run cooperatively.*/ + P_TCB p_new; + + p_new = rt_get_same_rdy_prio(); + if (p_new != NULL) { + rt_put_prio ((P_XCB)&os_rdy, os_tsk.run); + os_tsk.run->state = READY; + rt_switch_req (p_new); + } +} + + +/*--------------------------- rt_tsk_self -----------------------------------*/ + +OS_TID rt_tsk_self (void) { + /* Return own task identifier value. */ + if (os_tsk.run == NULL) { + return (0); + } + return (os_tsk.run->task_id); +} + + +/*--------------------------- rt_tsk_prio -----------------------------------*/ + +OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio) { + /* Change execution priority of a task to "new_prio". */ + P_TCB p_task; + + if (task_id == 0) { + /* Change execution priority of calling task. */ + os_tsk.run->prio = new_prio; +run:if (rt_rdy_prio() > new_prio) { + rt_put_prio (&os_rdy, os_tsk.run); + os_tsk.run->state = READY; + rt_dispatch (NULL); + } + return (OS_R_OK); + } + + /* Find the task in the "os_active_TCB" array. */ + if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) { + /* Task with "task_id" not found or not started. */ + return (OS_R_NOK); + } + p_task = os_active_TCB[task_id-1]; + p_task->prio = new_prio; + if (p_task == os_tsk.run) { + goto run; + } + rt_resort_prio (p_task); + if (p_task->state == READY) { + /* Task enqueued in a ready list. */ + p_task = rt_get_first (&os_rdy); + rt_dispatch (p_task); + } + return (OS_R_OK); +} + + +/*--------------------------- rt_tsk_create ---------------------------------*/ + +OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv) { + /* Start a new task declared with "task". */ + P_TCB task_context; + U32 i; + + /* Priority 0 is reserved for idle task! */ + if ((prio_stksz & 0xFF) == 0) { + prio_stksz += 1; + } + task_context = rt_alloc_box (mp_tcb); + if (task_context == NULL) { + return (0); + } + /* If "size != 0" use a private user provided stack. */ + task_context->stack = stk; + task_context->priv_stack = prio_stksz >> 8; + /* Pass parameter 'argv' to 'rt_init_context' */ + task_context->msg = argv; + /* For 'size == 0' system allocates the user stack from the memory pool. */ + rt_init_context (task_context, prio_stksz & 0xFF, task); + + /* Find a free entry in 'os_active_TCB' table. */ + i = rt_get_TID (); + os_active_TCB[i-1] = task_context; + task_context->task_id = i; + DBG_TASK_NOTIFY(task_context, __TRUE); + rt_dispatch (task_context); + return ((OS_TID)i); +} + + +/*--------------------------- rt_tsk_delete ---------------------------------*/ + +OS_RESULT rt_tsk_delete (OS_TID task_id) { + /* Terminate the task identified with "task_id". */ + P_TCB task_context; + + if (task_id == 0 || task_id == os_tsk.run->task_id) { + /* Terminate itself. */ + os_tsk.run->state = INACTIVE; + os_tsk.run->tsk_stack = rt_get_PSP (); + rt_stk_check (); + os_active_TCB[os_tsk.run->task_id-1] = NULL; + rt_free_box (mp_stk, os_tsk.run->stack); + os_tsk.run->stack = NULL; + DBG_TASK_NOTIFY(os_tsk.run, __FALSE); + rt_free_box (mp_tcb, os_tsk.run); + os_tsk.run = NULL; + rt_dispatch (NULL); + /* The program should never come to this point. */ + } + else { + /* Find the task in the "os_active_TCB" array. */ + if (task_id > os_maxtaskrun || os_active_TCB[task_id-1] == NULL) { + /* Task with "task_id" not found or not started. */ + return (OS_R_NOK); + } + task_context = os_active_TCB[task_id-1]; + rt_rmv_list (task_context); + rt_rmv_dly (task_context); + os_active_TCB[task_id-1] = NULL; + rt_free_box (mp_stk, task_context->stack); + task_context->stack = NULL; + DBG_TASK_NOTIFY(task_context, __FALSE); + rt_free_box (mp_tcb, task_context); + } + return (OS_R_OK); +} + + +/*--------------------------- rt_sys_init -----------------------------------*/ + +#ifdef __CMSIS_RTOS +void rt_sys_init (void) { +#else +void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk) { +#endif + /* Initialize system and start up task declared with "first_task". */ + U32 i; + + DBG_INIT(); + + /* Initialize dynamic memory and task TCB pointers to NULL. */ + for (i = 0; i < os_maxtaskrun; i++) { + os_active_TCB[i] = NULL; + } + rt_init_box (&mp_tcb, mp_tcb_size, sizeof(struct OS_TCB)); + rt_init_box (&mp_stk, mp_stk_size, BOX_ALIGN_8 | (U16)(os_stackinfo)); + rt_init_box ((U32 *)m_tmr, mp_tmr_size, sizeof(struct OS_TMR)); + + /* Set up TCB of idle demon */ + os_idle_TCB.task_id = 255; + os_idle_TCB.priv_stack = 0; + rt_init_context (&os_idle_TCB, 0, os_idle_demon); + + /* Set up ready list: initially empty */ + os_rdy.cb_type = HCB; + os_rdy.p_lnk = NULL; + /* Set up delay list: initially empty */ + os_dly.cb_type = HCB; + os_dly.p_dlnk = NULL; + os_dly.p_blnk = NULL; + os_dly.delta_time = 0; + + /* Fix SP and system variables to assume idle task is running */ + /* Transform main program into idle task by assuming idle TCB */ +#ifndef __CMSIS_RTOS + rt_set_PSP (os_idle_TCB.tsk_stack+32); +#endif + os_tsk.run = &os_idle_TCB; + os_tsk.run->state = RUNNING; + + /* Initialize ps queue */ + os_psq->first = 0; + os_psq->last = 0; + os_psq->size = os_fifo_size; + + rt_init_robin (); + + /* Initialize SVC and PendSV */ + rt_svc_init (); + +#ifndef __CMSIS_RTOS + /* Initialize and start system clock timer */ + os_tick_irqn = os_tick_init (); + if (os_tick_irqn >= 0) { + OS_X_INIT(os_tick_irqn); + } + + /* Start up first user task before entering the endless loop */ + rt_tsk_create (first_task, prio_stksz, stk, NULL); +#endif +} + + +/*--------------------------- rt_sys_start ----------------------------------*/ + +#ifdef __CMSIS_RTOS +void rt_sys_start (void) { + /* Start system */ + + /* Initialize and start system clock timer */ + os_tick_irqn = os_tick_init (); + if (os_tick_irqn >= 0) { + OS_X_INIT(os_tick_irqn); + } +} +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx_ca/rt_Task.h b/libraries/rtos/rtx_ca/rt_Task.h new file mode 100644 index 0000000000..58718f9352 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Task.h @@ -0,0 +1,87 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TASK.H + * Purpose: Task functions and system start up. + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Definitions */ + +/* Values for 'state' */ +#define INACTIVE 0 +#define READY 1 +#define RUNNING 2 +#define WAIT_DLY 3 +#define WAIT_ITV 4 +#define WAIT_OR 5 +#define WAIT_AND 6 +#define WAIT_SEM 7 +#define WAIT_MBX 8 +#define WAIT_MUT 9 + +/* Return codes */ +#define OS_R_TMO 0x01 +#define OS_R_EVT 0x02 +#define OS_R_SEM 0x03 +#define OS_R_MBX 0x04 +#define OS_R_MUT 0x05 + +#define OS_R_OK 0x00 +#define OS_R_NOK 0xff + +/* Variables */ +extern struct OS_TSK os_tsk; +extern struct OS_TCB os_idle_TCB; + +/* Functions */ +extern void rt_switch_req (P_TCB p_new); +extern void rt_dispatch (P_TCB next_TCB); +extern void rt_block (U16 timeout, U8 block_state); +extern void rt_tsk_pass (void); +extern OS_TID rt_tsk_self (void); +extern OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio); +extern OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv); +extern OS_RESULT rt_tsk_delete (OS_TID task_id); +#ifdef __CMSIS_RTOS +extern void rt_sys_init (void); +extern void rt_sys_start (void); +#else +extern void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk); +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + + + + + + diff --git a/libraries/rtos/rtx_ca/rt_Time.c b/libraries/rtos/rtx_ca/rt_Time.c new file mode 100644 index 0000000000..58769c675e --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Time.c @@ -0,0 +1,94 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TIME.C + * Purpose: Delay and interval wait functions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_Task.h" +#include "rt_Time.h" + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +/* Free running system tick counter */ +U32 os_time; + + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + + +/*--------------------------- rt_time_get -----------------------------------*/ + +U32 rt_time_get (void) { + /* Get system time tick */ + return (os_time); +} + + +/*--------------------------- rt_dly_wait -----------------------------------*/ + +void rt_dly_wait (U16 delay_time) { + /* Delay task by "delay_time" */ + rt_block (delay_time, WAIT_DLY); +} + + +/*--------------------------- rt_itv_set ------------------------------------*/ + +void rt_itv_set (U16 interval_time) { + /* Set interval length and define start of first interval */ + os_tsk.run->interval_time = interval_time; + os_tsk.run->delta_time = interval_time + (U16)os_time; +} + + +/*--------------------------- rt_itv_wait -----------------------------------*/ + +void rt_itv_wait (void) { + /* Wait for interval end and define start of next one */ + U16 delta; + + delta = os_tsk.run->delta_time - (U16)os_time; + os_tsk.run->delta_time += os_tsk.run->interval_time; + if ((delta & 0x8000) == 0) { + rt_block (delta, WAIT_ITV); + } +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Time.h b/libraries/rtos/rtx_ca/rt_Time.h new file mode 100644 index 0000000000..e6bae1a6e2 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Time.h @@ -0,0 +1,47 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TIME.H + * Purpose: Delay and interval wait functions definitions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Variables */ +extern U32 os_time; + +/* Functions */ +extern U32 rt_time_get (void); +extern void rt_dly_wait (U16 delay_time); +extern void rt_itv_set (U16 interval_time); +extern void rt_itv_wait (void); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_Timer.c b/libraries/rtos/rtx_ca/rt_Timer.c new file mode 100644 index 0000000000..03902f5d43 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Timer.c @@ -0,0 +1,129 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TIMER.C + * Purpose: User timer functions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "rt_TypeDef.h" +#include "RTX_Config.h" +#include "rt_Timer.h" +#include "rt_MemBox.h" + + +/*---------------------------------------------------------------------------- + * Global Variables + *---------------------------------------------------------------------------*/ + +/* User Timer list pointer */ +struct OS_XTMR os_tmr; + +/*---------------------------------------------------------------------------- + * Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- rt_tmr_tick -----------------------------------*/ + +void rt_tmr_tick (void) { + /* Decrement delta count of timer list head. Timers having the value of */ + /* zero are removed from the list and the callback function is called. */ + P_TMR p; + + if (os_tmr.next == NULL) { + return; + } + os_tmr.tcnt--; + while (os_tmr.tcnt == 0 && (p = os_tmr.next) != NULL) { + /* Call a user provided function to handle an elapsed timer */ + os_tmr_call (p->info); + os_tmr.tcnt = p->tcnt; + os_tmr.next = p->next; + rt_free_box ((U32 *)m_tmr, p); + } +} + +/*--------------------------- rt_tmr_create ---------------------------------*/ + +OS_ID rt_tmr_create (U16 tcnt, U16 info) { + /* Create an user timer and put it into the chained timer list using */ + /* a timeout count value of "tcnt". User parameter "info" is used as a */ + /* parameter for the user provided callback function "os_tmr_call ()". */ + P_TMR p_tmr, p; + U32 delta,itcnt = tcnt; + + if (tcnt == 0 || m_tmr == NULL) { + return (NULL); + } + p_tmr = rt_alloc_box ((U32 *)m_tmr); + if (!p_tmr) { + return (NULL); + } + p_tmr->info = info; + p = (P_TMR)&os_tmr; + delta = p->tcnt; + while (delta < itcnt && p->next != NULL) { + p = p->next; + delta += p->tcnt; + } + /* Right place found, insert timer into the list */ + p_tmr->next = p->next; + p_tmr->tcnt = (U16)(delta - itcnt); + p->next = p_tmr; + p->tcnt -= p_tmr->tcnt; + return (p_tmr); +} + +/*--------------------------- rt_tmr_kill -----------------------------------*/ + +OS_ID rt_tmr_kill (OS_ID timer) { + /* Remove user timer from the chained timer list. */ + P_TMR p, p_tmr; + + p_tmr = (P_TMR)timer; + p = (P_TMR)&os_tmr; + /* Search timer list for requested timer */ + while (p->next != p_tmr) { + if (p->next == NULL) { + /* Failed, "timer" is not in the timer list */ + return (p_tmr); + } + p = p->next; + } + /* Timer was found, remove it from the list */ + p->next = p_tmr->next; + p->tcnt += p_tmr->tcnt; + rt_free_box ((U32 *)m_tmr, p_tmr); + /* Timer killed */ + return (NULL); +} + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/libraries/rtos/rtx_ca/rt_Timer.h b/libraries/rtos/rtx_ca/rt_Timer.h new file mode 100644 index 0000000000..f0719eb612 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_Timer.h @@ -0,0 +1,46 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TIMER.H + * Purpose: User timer functions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Variables */ +extern struct OS_XTMR os_tmr; + +/* Functions */ +extern void rt_tmr_tick (void); +extern OS_ID rt_tmr_create (U16 tcnt, U16 info); +extern OS_ID rt_tmr_kill (OS_ID timer); + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/libraries/rtos/rtx_ca/rt_TypeDef.h b/libraries/rtos/rtx_ca/rt_TypeDef.h new file mode 100644 index 0000000000..5f59ea6006 --- /dev/null +++ b/libraries/rtos/rtx_ca/rt_TypeDef.h @@ -0,0 +1,167 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RT_TYPEDEF.H + * Purpose: Type Definitions + * Rev.: V4.60 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +/* Types */ +typedef char S8; +typedef unsigned char U8; +typedef short S16; +typedef unsigned short U16; +typedef int S32; +typedef unsigned int U32; +typedef long long S64; +typedef unsigned long long U64; +typedef unsigned char BIT; +typedef unsigned int BOOL; +typedef void (*FUNCP)(void); + +typedef U32 OS_TID; +typedef void *OS_ID; +typedef U32 OS_RESULT; + +typedef struct OS_TCB { + /* General part: identical for all implementations. */ + U8 cb_type; /* Control Block Type */ + U8 state; /* Task state */ + U8 prio; /* Execution priority */ + U8 task_id; /* Task ID value for optimized TCB access */ + struct OS_TCB *p_lnk; /* Link pointer for ready/sem. wait list */ + struct OS_TCB *p_rlnk; /* Link pointer for sem./mbx lst backwards */ + struct OS_TCB *p_dlnk; /* Link pointer for delay list */ + struct OS_TCB *p_blnk; /* Link pointer for delay list backwards */ + U16 delta_time; /* Time until time out */ + U16 interval_time; /* Time interval for periodic waits */ + U16 events; /* Event flags */ + U16 waits; /* Wait flags */ + void **msg; /* Direct message passing when task waits */ + + /* Hardware dependant part: specific for Cortex processor */ + U8 stack_frame; /* Stack frame: 0x1 Basic/Extended, 0x2 FP stacked/not stacked */ + U8 reserved; + U16 priv_stack; /* Private stack size, 0= system assigned */ + U32 tsk_stack; /* Current task Stack pointer (R13) */ + U32 *stack; /* Pointer to Task Stack memory block */ + + /* Task entry point used for uVision debugger */ + FUNCP ptask; /* Task entry address */ +} *P_TCB; +#define TCB_TID 3 /* 'task id' offset */ +#define TCB_STACKF 32 /* 'stack_frame' offset */ +#define TCB_TSTACK 36 /* 'tsk_stack' offset */ + +typedef struct OS_PSFE { /* Post Service Fifo Entry */ + void *id; /* Object Identification */ + U32 arg; /* Object Argument */ +} *P_PSFE; + +typedef struct OS_PSQ { /* Post Service Queue */ + U8 first; /* FIFO Head Index */ + U8 last; /* FIFO Tail Index */ + U8 count; /* Number of stored items in FIFO */ + U8 size; /* FIFO Size */ + struct OS_PSFE q[1]; /* FIFO Content */ +} *P_PSQ; + +typedef struct OS_TSK { + P_TCB run; /* Current running task */ + P_TCB new; /* Scheduled task to run */ +} *P_TSK; + +typedef struct OS_ROBIN { /* Round Robin Control */ + P_TCB task; /* Round Robin task */ + U16 time; /* Round Robin switch time */ + U16 tout; /* Round Robin timeout */ +} *P_ROBIN; + +typedef struct OS_XCB { + U8 cb_type; /* Control Block Type */ + struct OS_TCB *p_lnk; /* Link pointer for ready/sem. wait list */ + struct OS_TCB *p_rlnk; /* Link pointer for sem./mbx lst backwards */ + struct OS_TCB *p_dlnk; /* Link pointer for delay list */ + struct OS_TCB *p_blnk; /* Link pointer for delay list backwards */ + U16 delta_time; /* Time until time out */ +} *P_XCB; + +typedef struct OS_MCB { + U8 cb_type; /* Control Block Type */ + U8 state; /* State flag variable */ + U8 isr_st; /* State flag variable for isr functions */ + struct OS_TCB *p_lnk; /* Chain of tasks waiting for message */ + U16 first; /* Index of the message list begin */ + U16 last; /* Index of the message list end */ + U16 count; /* Actual number of stored messages */ + U16 size; /* Maximum number of stored messages */ + void *msg[1]; /* FIFO for Message pointers 1st element */ +} *P_MCB; + +typedef struct OS_SCB { + U8 cb_type; /* Control Block Type */ + U8 mask; /* Semaphore token mask */ + U16 tokens; /* Semaphore tokens */ + struct OS_TCB *p_lnk; /* Chain of tasks waiting for tokens */ +} *P_SCB; + +typedef struct OS_MUCB { + U8 cb_type; /* Control Block Type */ + U8 prio; /* Owner task default priority */ + U16 level; /* Call nesting level */ + struct OS_TCB *p_lnk; /* Chain of tasks waiting for mutex */ + struct OS_TCB *owner; /* Mutex owner task */ +} *P_MUCB; + +typedef struct OS_XTMR { + struct OS_TMR *next; + U16 tcnt; +} *P_XTMR; + +typedef struct OS_TMR { + struct OS_TMR *next; /* Link pointer to Next timer */ + U16 tcnt; /* Timer delay count */ + U16 info; /* User defined call info */ +} *P_TMR; + +typedef struct OS_BM { + void *free; /* Pointer to first free memory block */ + void *end; /* Pointer to memory block end */ + U32 blk_size; /* Memory block size */ +} *P_BM; + +/* Definitions */ +#define __TRUE 1 +#define __FALSE 0 +#define NULL ((void *) 0) + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ + diff --git a/workspace_tools/build.py b/workspace_tools/build.py index 44fff281c9..73984b4c2c 100755 --- a/workspace_tools/build.py +++ b/workspace_tools/build.py @@ -157,7 +157,10 @@ if __name__ == '__main__': # Additional Libraries if options.rtos: - libraries.extend(["rtx", "rtos"]) + if mcu == "RZ_A1H": + libraries.extend(["rtx_ca", "rtos_ca"]) + else: + libraries.extend(["rtx", "rtos"]) if options.eth: libraries.append("eth") if options.usb: diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 7088d16cb2..b7448ed5a2 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -72,6 +72,8 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('LPC11U68', ('uARM','GCC_ARM','GCC_CR')), ('OC_MBUINO', ('ARM', 'uARM', 'GCC_ARM')), + + ('RZ_A1H' , ('ARM')), ) diff --git a/workspace_tools/libraries.py b/workspace_tools/libraries.py index 5bb19913e0..6ec4d36165 100644 --- a/workspace_tools/libraries.py +++ b/workspace_tools/libraries.py @@ -33,6 +33,18 @@ LIBRARIES = [ "build_dir": RTOS_LIBRARIES, "dependencies": [MBED_LIBRARIES, MBED_RTX], }, + { + "id": "rtx_ca", + "source_dir": MBED_RTX_CA, + "build_dir": RTOS_LIBRARIES, + "dependencies": [MBED_LIBRARIES], + }, + { + "id": "rtos_ca", + "source_dir": RTOS_ABSTRACTION, + "build_dir": RTOS_LIBRARIES, + "dependencies": [MBED_LIBRARIES, MBED_RTX_CA], + }, # USB Device libraries { diff --git a/workspace_tools/paths.py b/workspace_tools/paths.py index 2b601e8170..4fed2995c7 100644 --- a/workspace_tools/paths.py +++ b/workspace_tools/paths.py @@ -49,6 +49,7 @@ MBED_RPC = join(LIB_DIR, "rpc") # mbed RTOS RTOS = join(LIB_DIR, "rtos") MBED_RTX = join(RTOS, "rtx") +MBED_RTX_CA = join(RTOS, "rtx_ca") RTOS_ABSTRACTION = join(RTOS, "rtos") RTOS_LIBRARIES = join(BUILD_DIR, "rtos") diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 4ad22aa9ef..be997b5cf4 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -21,7 +21,8 @@ CORE_LABELS = { "Cortex-M0+": "M0P", "Cortex-M3" : "M3", "Cortex-M4" : "M4", - "Cortex-M4F" : "M4" + "Cortex-M4F" : "M4", + "Cortex-A9" : "A9" } import os @@ -701,6 +702,14 @@ class ARM_MPS2(Target): self.supported_toolchains = ["ARM", "GCC_ARM"] self.default_toolchain = "ARM" +class RZ_A1H(Target): + def __init__(self): + Target.__init__(self) + self.core = "Cortex-A9" + self.extra_labels = ['RENESAS', 'MBRZA1H'] + self.supported_toolchains = ["ARM", "GCC_ARM"] + self.supported_form_factors = ["ARDUINO"] + self.default_toolchain = "ARM" class OC_MBUINO(LPC11U24): def __init__(self): @@ -783,6 +792,7 @@ TARGETS = [ LPCCAPPUCCINO(), HRM1017(), ARM_MPS2(), + RZ_A1H(), RBLAB_NRF51822(), RBLAB_BLENANO(), OC_MBUINO(), diff --git a/workspace_tools/tests.py b/workspace_tools/tests.py index 92d8888c09..33eb764339 100644 --- a/workspace_tools/tests.py +++ b/workspace_tools/tests.py @@ -208,7 +208,7 @@ TESTS = [ "id": "MBED_A20", "description": "I2C master/slave test", "source_dir": join(TEST_DIR, "mbed", "i2c_master_slave"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB,], - "mcu": ["LPC1768"], + "mcu": ["LPC1768", "RZ_A1H"], "peripherals": ["i2c_loop"] }, { @@ -583,7 +583,7 @@ TESTS = [ "duration": 15, "automated": True, "host_test": "wait_us_auto", - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z"], + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H"], }, { "id": "RTOS_2", "description": "Mutex resource lock", @@ -591,7 +591,7 @@ TESTS = [ "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "duration": 20, "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z"], + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H"], }, { "id": "RTOS_3", "description": "Semaphore resource lock", @@ -599,28 +599,28 @@ TESTS = [ "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "duration": 20, "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z"], + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H"], }, { "id": "RTOS_4", "description": "Signals messaging", "source_dir": join(TEST_DIR, "rtos", "mbed", "signals"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z"], + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H"], }, { "id": "RTOS_5", "description": "Queue messaging", "source_dir": join(TEST_DIR, "rtos", "mbed", "queue"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z"], + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H"], }, { "id": "RTOS_6", "description": "Mail messaging", "source_dir": join(TEST_DIR, "rtos", "mbed", "mail"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z"], + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H"], }, { "id": "RTOS_7", "description": "Timer", @@ -629,14 +629,14 @@ TESTS = [ "duration": 15, "automated": True, "host_test": "wait_us_auto", - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z"], + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H"], }, { "id": "RTOS_8", "description": "ISR (Queue)", "source_dir": join(TEST_DIR, "rtos", "mbed", "isr"), "dependencies": [MBED_LIBRARIES, RTOS_LIBRARIES, TEST_MBED_LIB], "automated": True, - "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z"], + "mcu": ["LPC1768", "LPC1549", "LPC11U24", "LPC812", "KL25Z", "KL05Z", "K64F", "KL46Z", "RZ_A1H"], }, { "id": "RTOS_9", "description": "SD File write-read", diff --git a/workspace_tools/toolchains/__init__.py b/workspace_tools/toolchains/__init__.py index df089d1ddc..6edd17e39d 100644 --- a/workspace_tools/toolchains/__init__.py +++ b/workspace_tools/toolchains/__init__.py @@ -198,6 +198,7 @@ class mbedToolchain: "Cortex-M0+": ["__CORTEX_M0PLUS", "ARM_MATH_CM0PLUS"], "Cortex-M4" : ["__CORTEX_M4", "ARM_MATH_CM4"], "Cortex-M4F" : ["__CORTEX_M4", "ARM_MATH_CM4", "__FPU_PRESENT=1"], + "Cortex-A9" : ["__CORTEX_A9", "ARM_MATH_CA9", "__FPU_PRESENT", "__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA9"], } GOANNA_FORMAT = "[Goanna] warning [%FILENAME%:%LINENO%] - [%CHECKNAME%(%SEVERITY%)] %MESSAGE%" @@ -311,7 +312,7 @@ class mbedToolchain: return False - def scan_resources(self, path): + def scan_resources(self, path, exclude=None): labels = self.get_labels() resources = Resources(path) self.has_config = False @@ -354,7 +355,8 @@ class mbedToolchain: resources.c_sources.append(file_path) elif ext == '.cpp': - resources.cpp_sources.append(file_path) + if file != exclude: + resources.cpp_sources.append(file_path) elif ext == '.h' or ext == '.hpp': if basename(file_path) == "mbed_config.h": diff --git a/workspace_tools/toolchains/gcc.py b/workspace_tools/toolchains/gcc.py index fda908dc30..ac705ada2f 100644 --- a/workspace_tools/toolchains/gcc.py +++ b/workspace_tools/toolchains/gcc.py @@ -48,6 +48,10 @@ class GCC(mbedToolchain): self.cpu.append("-mfpu=fpv4-sp-d16") self.cpu.append("-mfloat-abi=softfp") + if target.core == "Cortex-A9": + self.cpu.append("-mfpu=vfpv3-fp16") + self.cpu.append("-mfloat-abi=hard") + # Note: We are using "-O2" instead of "-Os" to avoid this known GCC bug: # http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46762 common_flags = ["-c", "-Wall", "-Wextra",