diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralPins.c
index c94ebdfe68..6ddd72e438 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralPins.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralPins.c
@@ -250,11 +250,6 @@ const PinMap PinMap_PWM[] = {
     {P7_0  , PWM_TIOC2A, 5},
     {P9_4  , PWM_TIOC2A, 5}, /* for 208QFP */
     {P2_6  , PWM_TIOC2A, 3},
-    {P6_7  , PWM_TIOC3A, 5},
-    {P2_5  , PWM_TIOC3A, 3},
-    {P3_11 , PWM_TIOC3A, 3},
-    {P6_9  , PWM_TIOC3C, 5},
-    {P3_12 , PWM_TIOC3C, 3},
     {P5_8  , PWM_TIOC4A, 3},
     {P2_4  , PWM_TIOC4A, 3},
     {P5_10 , PWM_TIOC4C, 3},
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c
index 89420e51f2..8dd0d07697 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c
@@ -192,5 +192,9 @@ uint32_t OS_Tick_GetOverflow (void)
   return (IRQ_GetPending(OSTM_IRQn));
 }
 
+// Get Cortex-A9 OS Timer interrupt number
+IRQn_ID_t mbed_get_a9_tick_irqn(){
+  return OSTMI0TINT_IRQn;
+}
 #endif
 
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h
index e20cb88383..d7279fc10e 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/mbed_drv_cfg.h
@@ -34,6 +34,8 @@
 
 #define RENESAS_RZ_A1_P0_CLK   CM1_RENESAS_RZ_A1_P0_CLK
 
+#define LP_TICKER_MTU2_CH      3
+
 /* flash (W25Q64JV) */
 #define FLASH_BASE                 (0x18000000UL) /**< Flash Base Address */
 #define FLASH_SIZE                 (0x00800000UL) /**< Available Flash Memory */
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c
index bfc94f513a..0af90e3778 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c
@@ -276,17 +276,13 @@ const PinMap PinMap_PWM[] = {
     {P4_4  , PWM_TIOC4A, 3},
     {P4_6  , PWM_TIOC4C, 3},
     {P5_0  , PWM_TIOC0A, 6},
-    {P5_3  , PWM_TIOC3C, 6},
     {P5_5  , PWM_TIOC0C, 6},
     {P7_2  , PWM_TIOC0C, 7},
     {P7_4  , PWM_TIOC1A, 7},
     {P7_6  , PWM_TIOC2A, 7},
-    {P7_10 , PWM_TIOC3C, 7},
     {P7_12 , PWM_TIOC4A, 7},
     {P7_14 , PWM_TIOC4C, 7},
     {P8_8  , PWM_TIOC1A, 5},
-    {P8_10 , PWM_TIOC3A, 4},
-    {P8_12 , PWM_TIOC3C, 4},
     {P8_14 , PWM_TIOC2A, 4},
     {P11_0 , PWM_TIOC4A, 2},
     {P11_2 , PWM_TIOC4C, 2},
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h
index 1033832fbd..b883ed84a8 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h
@@ -34,6 +34,8 @@
 
 #define RENESAS_RZ_A1_P0_CLK   CM0_RENESAS_RZ_A1_P0_CLK
 
+#define LP_TICKER_MTU2_CH      3
+
 /* flash (MX25L6433FM2I) */
 #define FLASH_BASE                 (0x18000000UL) /**< Flash Base Address */
 #define FLASH_SIZE                 (0x00800000UL) /**< Available Flash Memory */
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/lp_ticker.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/lp_ticker.c
new file mode 100644
index 0000000000..1edbf34d2b
--- /dev/null
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/lp_ticker.c
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#if DEVICE_LPTICKER
+#include "lp_ticker_api.h"
+#include "mtu2_iobitmask.h"
+#include "mbed_drv_cfg.h"
+#include "mtu2.h"
+
+#if (LP_TICKER_MTU2_CH == 2)
+ #define LP_TICKER_TIMER_IRQn (TGI2A_IRQn)
+ #define MTU2TCR              (MTU2TCR_2)
+ #define MTU2TCNT             (MTU2TCNT_2)
+ #define MTU2TIER             (MTU2TIER_2)
+ #define MTU2TGRA             (MTU2TGRA_2)
+ #define MTU2TSR              (MTU2TSR_2)
+ #define MTU2_TSTR_CST        MTU2_TSTR_CST2
+ #define MTU2_TCR_TPSC        (0x07)
+#elif (LP_TICKER_MTU2_CH == 3)
+ #define LP_TICKER_TIMER_IRQn (TGI3A_IRQn)
+ #define MTU2TCR              (MTU2TCR_3)
+ #define MTU2TCNT             (MTU2TCNT_3)
+ #define MTU2TIER             (MTU2TIER_3)
+ #define MTU2TGRA             (MTU2TGRA_3)
+ #define MTU2TSR              (MTU2TSR_3)
+ #define MTU2_TSTR_CST        MTU2_TSTR_CST3
+ #define MTU2_TCR_TPSC        (0x05)
+#elif (LP_TICKER_MTU2_CH == 4)
+ #define LP_TICKER_TIMER_IRQn (TGI4A_IRQn)
+ #define MTU2TCR              (MTU2TCR_4)
+ #define MTU2TCNT             (MTU2TCNT_4)
+ #define MTU2TIER             (MTU2TIER_4)
+ #define MTU2TGRA             (MTU2TGRA_4)
+ #define MTU2TSR              (MTU2TSR_4)
+ #define MTU2_TSTR_CST        MTU2_TSTR_CST4
+ #define MTU2_TCR_TPSC        (0x05)
+#else
+ #error "Invalid number : LP_TICKER_MTU2_CH (2-4)"
+#endif
+
+static int lp_ticker_inited = 0;
+
+void lp_ticker_init(void)
+{
+    GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
+    GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);
+
+    /* Power Control for Peripherals      */
+    mtu2_init();
+
+    if (lp_ticker_inited) return;
+    lp_ticker_inited = 1;
+
+    MTU2TCR   = MTU2_TCR_TPSC;
+    MTU2TSTR  |= MTU2_TSTR_CST;
+    MTU2TIER  |= MTU2_TIER_n_TGIEA;
+
+    // INTC settings
+    InterruptHandlerRegister(LP_TICKER_TIMER_IRQn, (void (*)(uint32_t))lp_ticker_irq_handler);
+    GIC_SetPriority(LP_TICKER_TIMER_IRQn, 5);
+    GIC_SetConfiguration(LP_TICKER_TIMER_IRQn, 3);
+}
+
+void lp_ticker_free(void)
+{
+    GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
+    GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);
+
+    MTU2TIER  &= ~MTU2_TIER_n_TGIEA;
+    lp_ticker_inited = 0;
+    mtu2_free();
+}
+
+uint32_t lp_ticker_read()
+{
+    return (uint32_t)MTU2TCNT;
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+    MTU2TSR = (MTU2TSR & 0xFE);
+    MTU2TGRA = (uint16_t)timestamp;
+    GIC_EnableIRQ(LP_TICKER_TIMER_IRQn);
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+    GIC_SetPendingIRQ(LP_TICKER_TIMER_IRQn);
+    GIC_EnableIRQ(LP_TICKER_TIMER_IRQn);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+    GIC_DisableIRQ(LP_TICKER_TIMER_IRQn);
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+    MTU2TSR = (MTU2TSR & 0xFE);
+    GIC_ClearPendingIRQ(LP_TICKER_TIMER_IRQn);
+}
+
+const ticker_info_t* lp_ticker_get_info()
+{
+    static const ticker_info_t info = {
+        (uint32_t)((float)RENESAS_RZ_A1_P0_CLK / 1024.0f + 0.5f),
+        16
+    };
+    return &info;
+}
+
+#endif // DEVICE_LPTICKER
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/mtu2.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/mtu2.c
new file mode 100644
index 0000000000..196cd11d9c
--- /dev/null
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/mtu2.c
@@ -0,0 +1,43 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "mbed_drv_cfg.h"
+
+#if (defined(FUMC_MTU2_PWM) || defined(DEVICE_LPTICKER))
+#include "mtu2.h"
+
+static int mtu2_used_cnt = 0;
+
+void mtu2_init(void)
+{
+    if (mtu2_used_cnt == 0) {
+        CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33);
+    }
+    if (mtu2_used_cnt < 256) {
+        mtu2_used_cnt++;
+    }
+}
+
+void mtu2_free(void)
+{
+    if (mtu2_used_cnt > 0) {
+        mtu2_used_cnt--;
+    }
+    if (mtu2_used_cnt == 0) {
+        CPGSTBCR3 |= (CPG_STBCR3_BIT_MSTP33);
+    }
+}
+#endif
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/mtu2.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/mtu2.h
new file mode 100644
index 0000000000..43cda3ef53
--- /dev/null
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/mtu2.h
@@ -0,0 +1,34 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MTU2_H
+#define MTU2_H
+
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void mtu2_init(void);
+void mtu2_free(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c
index 0bed1c4aa3..6ffae0a964 100644
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c
@@ -21,6 +21,7 @@
 #include "iodefine.h"
 #include "gpio_addrdefine.h"
 #include "mbed_drv_cfg.h"
+#include "mtu2.h"
 
 #define MTU2_PWM_OFFSET         0x20
 
@@ -208,7 +209,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
         int tmp_pwm;
         
         // power on
-        CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33);
+        mtu2_init();
         
         obj->pwm = pwm;
         tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
@@ -274,6 +275,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
 
 void pwmout_free(pwmout_t* obj) {
     pwmout_write(obj, 0);
+    mtu2_free();
 }
 
 void pwmout_write(pwmout_t* obj, float value) {
diff --git a/targets/targets.json b/targets/targets.json
index a27646f1c1..6982cbbab9 100755
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -2841,7 +2841,7 @@
         "inherits": ["RZ_A1XX"],
         "supported_form_factors": ["ARDUINO"],
         "extra_labels_add": ["RZA1H", "MBRZA1H", "RZ_A1_EMAC"],
-        "device_has_add": ["EMAC", "FLASH"],
+        "device_has_add": ["EMAC", "FLASH", "LPTICKER"],
         "release_versions": ["2", "5"],
         "device_name": "R7S72100",
         "bootloader_supported": true
@@ -2856,7 +2856,7 @@
         "inherits": ["RZ_A1XX"],
         "supported_form_factors": ["ARDUINO"],
         "extra_labels_add": ["RZA1UL", "MBRZA1LU"],
-        "device_has_add": ["TRNG", "FLASH"],
+        "device_has_add": ["TRNG", "FLASH", "LPTICKER"],
         "device_has_remove": ["ETHERNET"],
         "release_versions": ["2", "5"],
         "device_name": "R7S72103",