mirror of https://github.com/ARMmbed/mbed-os.git
Przemek Wirkus
commit
b746b28dbf
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@ -1,5 +1,8 @@
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---
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install: "sudo $TRAVIS_BUILD_DIR/travis/install_dependencies.sh > /dev/null"
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python:
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- "2.7"
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script: "python workspace_tools/build_travis.py"
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install:
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- "sudo $TRAVIS_BUILD_DIR/travis/install_dependencies.sh > /dev/null"
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- sudo pip install colorama
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- sudo pip install prettytable
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@ -33,6 +33,7 @@ NXP:
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* LPC810 (Cortex-M0+)
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* [LPC812](http://developer.mbed.org/platforms/NXP-LPC800-MAX/) (Cortex-M0+)
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* [EA LPC4088](http://developer.mbed.org/platforms/EA-LPC4088/) (Cortex-M4F)
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* [EA LPC4088 DM](http://developer.mbed.org/platforms/EA-LPC4088-Display-Module/) (Cortex-M4F)
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* LPC4330 (Cortex-M4F + Cortex-M0)
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* [LPC1347](http://developer.mbed.org/platforms/DipCortex-M3/) (Cortex-M3)
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* [LPC1114](http://developer.mbed.org/platforms/LPC1114FN28/) (Cortex-M0)
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@ -37,7 +37,7 @@ typedef enum {
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} EP_STATUS;
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/* Include configuration for specific target */
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#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088)
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#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
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#include "USBEndpoints_LPC17_LPC23.h"
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#elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549)
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#include "USBEndpoints_LPC11U.h"
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@ -16,7 +16,7 @@
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#if defined(TARGET_LPC4088)
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#if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
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#include "USBHAL.h"
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@ -58,15 +58,35 @@ public:
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*/
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void mode(PinMode pull);
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/** Binary mask of bus pins connected to actual pins (not NC pins)
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* If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
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*
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* @returns
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* Binary mask of connected pins
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*/
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int mask() {
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return _nc_mask;
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}
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#ifdef MBED_OPERATORS
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/** A shorthand for read()
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*/
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operator int();
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/** Access to particular bit in random-iterator fashion
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*/
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DigitalIn & operator[] (int index);
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#endif
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protected:
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DigitalIn* _pin[16];
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/** Mask of bus's NC pins
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* If bit[n] is set to 1 - pin is connected
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* if bit[n] is cleared - pin is not connected (NC)
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*/
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int _nc_mask;
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/* disallow copy constructor and assignment operators */
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private:
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BusIn(const BusIn&);
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@ -51,7 +51,6 @@ public:
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*/
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void write(int value);
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/** Read the value currently output on the bus
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*
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* @returns
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@ -73,12 +72,26 @@ public:
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*/
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void mode(PinMode pull);
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/** Binary mask of bus pins connected to actual pins (not NC pins)
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* If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
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*
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* @returns
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* Binary mask of connected pins
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*/
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int mask() {
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return _nc_mask;
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}
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#ifdef MBED_OPERATORS
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/** A shorthand for write()
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*/
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BusInOut& operator= (int v);
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BusInOut& operator= (BusInOut& rhs);
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/** Access to particular bit in random-iterator fashion
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*/
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DigitalInOut& operator[] (int index);
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/** A shorthand for read()
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*/
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operator int();
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@ -87,6 +100,12 @@ public:
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protected:
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DigitalInOut* _pin[16];
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/** Mask of bus's NC pins
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* If bit[n] is set to 1 - pin is connected
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* if bit[n] is cleared - pin is not connected (NC)
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*/
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int _nc_mask;
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/* disallow copy constructor and assignment operators */
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private:
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BusInOut(const BusInOut&);
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@ -56,12 +56,26 @@ public:
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*/
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int read();
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/** Binary mask of bus pins connected to actual pins (not NC pins)
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* If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
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*
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* @returns
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* Binary mask of connected pins
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*/
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int mask() {
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return _nc_mask;
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}
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#ifdef MBED_OPERATORS
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/** A shorthand for write()
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*/
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BusOut& operator= (int v);
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BusOut& operator= (BusOut& rhs);
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/** Access to particular bit in random-iterator fashion
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*/
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DigitalOut& operator[] (int index);
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/** A shorthand for read()
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*/
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operator int();
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@ -70,6 +84,12 @@ public:
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protected:
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DigitalOut* _pin[16];
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/** Mask of bus's NC pins
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* If bit[n] is set to 1 - pin is connected
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* if bit[n] is cleared - pin is not connected (NC)
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*/
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int _nc_mask;
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/* disallow copy constructor and assignment operators */
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private:
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BusOut(const BusOut&);
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@ -80,6 +80,16 @@ public:
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gpio_mode(&gpio, pull);
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}
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/** Return the output setting, represented as 0 or 1 (int)
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*
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* @returns
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* Non zero value if pin is connected to uc GPIO
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* 0 if gpio object was initialized with NC
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*/
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int is_connected() {
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return gpio_is_connected(&gpio);
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}
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#ifdef MBED_OPERATORS
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/** An operator shorthand for read()
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*/
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@ -85,6 +85,16 @@ public:
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gpio_mode(&gpio, pull);
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}
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/** Return the output setting, represented as 0 or 1 (int)
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*
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* @returns
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* Non zero value if pin is connected to uc GPIO
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* 0 if gpio object was initialized with NC
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*/
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int is_connected() {
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return gpio_is_connected(&gpio);
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}
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#ifdef MBED_OPERATORS
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/** A shorthand for write()
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*/
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@ -77,6 +77,16 @@ public:
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return gpio_read(&gpio);
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}
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/** Return the output setting, represented as 0 or 1 (int)
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*
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* @returns
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* Non zero value if pin is connected to uc GPIO
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* 0 if gpio object was initialized with NC
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*/
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int is_connected() {
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return gpio_is_connected(&gpio);
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}
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#ifdef MBED_OPERATORS
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/** A shorthand for write()
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*/
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@ -16,7 +16,7 @@
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#ifndef MBED_H
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#define MBED_H
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#define MBED_LIBRARY_VERSION 92
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#define MBED_LIBRARY_VERSION 94
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#include "platform.h"
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@ -14,20 +14,29 @@
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* limitations under the License.
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*/
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#include "BusIn.h"
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#include "mbed_assert.h"
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namespace mbed {
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BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
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PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
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_nc_mask = 0;
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for (int i=0; i<16; i++) {
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_pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
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if (pins[i] != NC) {
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_nc_mask |= (1 << i);
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}
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}
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}
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BusIn::BusIn(PinName pins[16]) {
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_nc_mask = 0;
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for (int i=0; i<16; i++) {
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_pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
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if (pins[i] != NC) {
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_nc_mask |= (1 << i);
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}
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}
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}
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@ -61,6 +70,13 @@ void BusIn::mode(PinMode pull) {
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BusIn::operator int() {
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return read();
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}
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DigitalIn& BusIn::operator[] (int index) {
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MBED_ASSERT(index >= 0 && index <= 16);
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MBED_ASSERT(_pin[index]);
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return *_pin[index];
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}
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#endif
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} // namespace mbed
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@ -14,20 +14,29 @@
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* limitations under the License.
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*/
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#include "BusInOut.h"
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#include "mbed_assert.h"
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namespace mbed {
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BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
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PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
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_nc_mask = 0;
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for (int i=0; i<16; i++) {
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_pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
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if (pins[i] != NC) {
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_nc_mask |= (1 << i);
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}
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}
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}
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BusInOut::BusInOut(PinName pins[16]) {
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_nc_mask = 0;
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for (int i=0; i<16; i++) {
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_pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
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if (pins[i] != NC) {
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_nc_mask |= (1 << i);
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}
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}
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}
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@ -92,6 +101,12 @@ BusInOut& BusInOut::operator= (BusInOut& rhs) {
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return *this;
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}
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DigitalInOut& BusInOut::operator[] (int index) {
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MBED_ASSERT(index >= 0 && index <= 16);
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MBED_ASSERT(_pin[index]);
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return *_pin[index];
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}
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BusInOut::operator int() {
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return read();
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}
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@ -14,20 +14,29 @@
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* limitations under the License.
|
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*/
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#include "BusOut.h"
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#include "mbed_assert.h"
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namespace mbed {
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BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
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PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
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_nc_mask = 0;
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for (int i=0; i<16; i++) {
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_pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
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if (pins[i] != NC) {
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_nc_mask |= (1 << i);
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}
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}
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}
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|
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BusOut::BusOut(PinName pins[16]) {
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_nc_mask = 0;
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for (int i=0; i<16; i++) {
|
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_pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
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if (pins[i] != NC) {
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_nc_mask |= (1 << i);
|
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}
|
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}
|
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}
|
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|
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@ -68,6 +77,12 @@ BusOut& BusOut::operator= (BusOut& rhs) {
|
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return *this;
|
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}
|
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|
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DigitalOut& BusOut::operator[] (int index) {
|
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MBED_ASSERT(index >= 0 && index <= 16);
|
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MBED_ASSERT(_pin[index]);
|
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return *_pin[index];
|
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}
|
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|
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BusOut::operator int() {
|
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return read();
|
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}
|
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|
|
|
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|
|
@ -1,46 +0,0 @@
|
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/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "semihost_api.h"
|
||||
#include "mbed_interface.h"
|
||||
#if DEVICE_STDIO_MESSAGES
|
||||
#include <stdio.h>
|
||||
#endif
|
||||
|
||||
#ifdef TOOLCHAIN_GCC_CW
|
||||
// TODO: Ideally, we would like to define directly "_ExitProcess"
|
||||
void mbed_exit(int return_code) {
|
||||
#elif defined TOOLCHAIN_GCC_ARM
|
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void _exit(int return_code) {
|
||||
#else
|
||||
void exit(int return_code) {
|
||||
#endif
|
||||
|
||||
#if DEVICE_STDIO_MESSAGES
|
||||
fflush(stdout);
|
||||
fflush(stderr);
|
||||
#endif
|
||||
|
||||
#if DEVICE_SEMIHOST
|
||||
if (mbed_interface_connected()) {
|
||||
semihost_exit();
|
||||
}
|
||||
#endif
|
||||
if (return_code) {
|
||||
mbed_die();
|
||||
}
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
|
|
@ -19,6 +19,11 @@
|
|||
#include "FilePath.h"
|
||||
#include "serial_api.h"
|
||||
#include "toolchain.h"
|
||||
#include "semihost_api.h"
|
||||
#include "mbed_interface.h"
|
||||
#if DEVICE_STDIO_MESSAGES
|
||||
#include <stdio.h>
|
||||
#endif
|
||||
#include <errno.h>
|
||||
|
||||
#if defined(__ARMCC_VERSION)
|
||||
|
|
@ -482,6 +487,38 @@ extern "C" caddr_t _sbrk(int incr) {
|
|||
#endif
|
||||
|
||||
|
||||
#ifdef TOOLCHAIN_GCC_CW
|
||||
// TODO: Ideally, we would like to define directly "_ExitProcess"
|
||||
extern "C" void mbed_exit(int return_code) {
|
||||
#elif defined TOOLCHAIN_GCC_ARM
|
||||
extern "C" void _exit(int return_code) {
|
||||
#else
|
||||
namespace std {
|
||||
extern "C" void exit(int return_code) {
|
||||
#endif
|
||||
|
||||
#if DEVICE_STDIO_MESSAGES
|
||||
fflush(stdout);
|
||||
fflush(stderr);
|
||||
#endif
|
||||
|
||||
#if DEVICE_SEMIHOST
|
||||
if (mbed_interface_connected()) {
|
||||
semihost_exit();
|
||||
}
|
||||
#endif
|
||||
if (return_code) {
|
||||
mbed_die();
|
||||
}
|
||||
|
||||
while (1);
|
||||
}
|
||||
|
||||
#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CW)
|
||||
} //namespace std
|
||||
#endif
|
||||
|
||||
|
||||
namespace mbed {
|
||||
|
||||
void mbed_set_unbuffered_stream(FILE *_file) {
|
||||
|
|
@ -524,11 +561,3 @@ char* mbed_gets(char*s, int size, FILE *_file){
|
|||
}
|
||||
|
||||
} // namespace mbed
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t
|
|||
ticker_event_t *prev = NULL, *p = head;
|
||||
while (p != NULL) {
|
||||
/* check if we come before p */
|
||||
if ((int64_t)(timestamp - p->timestamp) < 0) {
|
||||
if ((int)(timestamp - p->timestamp) < 0) {
|
||||
break;
|
||||
}
|
||||
/* go to the next element */
|
||||
|
|
|
|||
|
|
@ -28,6 +28,12 @@ extern "C" {
|
|||
**/
|
||||
uint32_t gpio_set(PinName pin);
|
||||
|
||||
/* Checks if gpio object is connected (pin was not initialized with NC)
|
||||
* @param pin The pin to be set as GPIO
|
||||
* @return 0 if port is initialized with NC
|
||||
**/
|
||||
int gpio_is_connected(const gpio_t *obj);
|
||||
|
||||
/* GPIO object */
|
||||
void gpio_init(gpio_t *obj, PinName pin);
|
||||
|
||||
|
|
|
|||
|
|
@ -46,6 +46,8 @@ void i2c_slave_mode (i2c_t *obj, int enable_slave);
|
|||
int i2c_slave_receive(i2c_t *obj);
|
||||
int i2c_slave_read (i2c_t *obj, char *data, int length);
|
||||
int i2c_slave_write (i2c_t *obj, const char *data, int length);
|
||||
int i2c_slave_byte_read(i2c_t *obj, int last);
|
||||
int i2c_slave_byte_write(i2c_t *obj, int data);
|
||||
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef uint64_t timestamp_t;
|
||||
typedef uint32_t timestamp_t;
|
||||
|
||||
uint32_t us_ticker_read(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@
|
|||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
|
||||
#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
#include "cmsis.h"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00016000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20002000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x900;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __code_start_soft_device__ = 0x0;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
keep { section .intvec };
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK,
|
||||
block HEAP };
|
||||
|
||||
/*This is used for mbed applications build inside the Embedded workbench
|
||||
Applications build with the python scritps use a hex merge so need to merge it
|
||||
inside the linker. The linker can only use binary files so the hex merge is not possible
|
||||
through the linker. That is why a binary is used instead of a hex image for the embedded project.
|
||||
*/
|
||||
if(isdefinedsymbol(SOFT_DEVICE_BIN))
|
||||
{
|
||||
place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
|
||||
}
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
|
||||
;; The information contained herein is confidential property of Nordic
|
||||
;; Semiconductor ASA.Terms and conditions of usage are described in detail
|
||||
;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
|
||||
;; Licensees are granted free, non-transferable use of the information. NO
|
||||
;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
|
||||
;; the file.
|
||||
|
||||
;; Description message
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Stack size default : 1024
|
||||
;; Heap size default : 2048
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
;__vector_table_0x1c
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
|
||||
DCD RADIO_IRQHandler ;RADIO
|
||||
DCD UART0_IRQHandler ;UART0
|
||||
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
|
||||
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
|
||||
DCD 0 ;Reserved
|
||||
DCD GPIOTE_IRQHandler ;GPIOTE
|
||||
DCD ADC_IRQHandler ;ADC
|
||||
DCD TIMER0_IRQHandler ;TIMER0
|
||||
DCD TIMER1_IRQHandler ;TIMER1
|
||||
DCD TIMER2_IRQHandler ;TIMER2
|
||||
DCD RTC0_IRQHandler ;RTC0
|
||||
DCD TEMP_IRQHandler ;TEMP
|
||||
DCD RNG_IRQHandler ;RNG
|
||||
DCD ECB_IRQHandler ;ECB
|
||||
DCD CCM_AAR_IRQHandler ;CCM_AAR
|
||||
DCD WDT_IRQHandler ;WDT
|
||||
DCD RTC1_IRQHandler ;RTC1
|
||||
DCD QDEC_IRQHandler ;QDEC
|
||||
DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
|
||||
DCD SWI0_IRQHandler ;SWI0
|
||||
DCD SWI1_IRQHandler ;SWI1
|
||||
DCD SWI2_IRQHandler ;SWI2
|
||||
DCD SWI3_IRQHandler ;SWI3
|
||||
DCD SWI4_IRQHandler ;SWI4
|
||||
DCD SWI5_IRQHandler ;SWI5
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
|
||||
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
LDR R0, =NRF_POWER_RAMON_ADDRESS
|
||||
LDR R2, [R0]
|
||||
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
|
||||
ORRS R2, R2, R1
|
||||
STR R2, [R0]
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
PUBWEAK UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART0_IRQHandler
|
||||
B .
|
||||
PUBWEAK SPI0_TWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI0_TWI0_IRQHandler
|
||||
B .
|
||||
PUBWEAK SPI1_TWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI1_TWI1_IRQHandler
|
||||
B .
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC_IRQHandler
|
||||
B .
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
PUBWEAK LPCOMP_COMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
LPCOMP_COMP_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI4_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI5_IRQHandler
|
||||
B .
|
||||
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x00016000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20002000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define symbol __code_start_soft_device__ = 0x0;
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
keep { section .intvec };
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK,
|
||||
block HEAP };
|
||||
|
||||
/*This is used for mbed applications build inside the Embedded workbench
|
||||
Applications build with the python scritps use a hex merge so need to merge it
|
||||
inside the linker. The linker can only use binary files so the hex merge is not possible
|
||||
through the linker. That is why a binary is used instead of a hex image for the embedded project.
|
||||
*/
|
||||
if(isdefinedsymbol(SOFT_DEVICE_BIN))
|
||||
{
|
||||
place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
|
||||
}
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
|
||||
;; The information contained herein is confidential property of Nordic
|
||||
;; Semiconductor ASA.Terms and conditions of usage are described in detail
|
||||
;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
|
||||
;; Licensees are granted free, non-transferable use of the information. NO
|
||||
;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
|
||||
;; the file.
|
||||
|
||||
;; Description message
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Stack size default : 1024
|
||||
;; Heap size default : 2048
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
DCD NMI_Handler
|
||||
DCD HardFault_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
;__vector_table_0x1c
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
|
||||
DCD RADIO_IRQHandler ;RADIO
|
||||
DCD UART0_IRQHandler ;UART0
|
||||
DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
|
||||
DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
|
||||
DCD 0 ;Reserved
|
||||
DCD GPIOTE_IRQHandler ;GPIOTE
|
||||
DCD ADC_IRQHandler ;ADC
|
||||
DCD TIMER0_IRQHandler ;TIMER0
|
||||
DCD TIMER1_IRQHandler ;TIMER1
|
||||
DCD TIMER2_IRQHandler ;TIMER2
|
||||
DCD RTC0_IRQHandler ;RTC0
|
||||
DCD TEMP_IRQHandler ;TEMP
|
||||
DCD RNG_IRQHandler ;RNG
|
||||
DCD ECB_IRQHandler ;ECB
|
||||
DCD CCM_AAR_IRQHandler ;CCM_AAR
|
||||
DCD WDT_IRQHandler ;WDT
|
||||
DCD RTC1_IRQHandler ;RTC1
|
||||
DCD QDEC_IRQHandler ;QDEC
|
||||
DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
|
||||
DCD SWI0_IRQHandler ;SWI0
|
||||
DCD SWI1_IRQHandler ;SWI1
|
||||
DCD SWI2_IRQHandler ;SWI2
|
||||
DCD SWI3_IRQHandler ;SWI3
|
||||
DCD SWI4_IRQHandler ;SWI4
|
||||
DCD SWI5_IRQHandler ;SWI5
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
|
||||
|
||||
__Vectors_End
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
|
||||
NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
|
||||
|
||||
; Default handlers.
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
LDR R0, =NRF_POWER_RAMON_ADDRESS
|
||||
LDR R2, [R0]
|
||||
MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
|
||||
ORRS R2, R2, R1
|
||||
STR R2, [R0]
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
; Dummy exception handlers
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B .
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B .
|
||||
|
||||
; Dummy interrupt handlers
|
||||
|
||||
PUBWEAK POWER_CLOCK_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
POWER_CLOCK_IRQHandler
|
||||
B .
|
||||
PUBWEAK RADIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RADIO_IRQHandler
|
||||
B .
|
||||
PUBWEAK UART0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART0_IRQHandler
|
||||
B .
|
||||
PUBWEAK SPI0_TWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI0_TWI0_IRQHandler
|
||||
B .
|
||||
PUBWEAK SPI1_TWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI1_TWI1_IRQHandler
|
||||
B .
|
||||
PUBWEAK GPIOTE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
GPIOTE_IRQHandler
|
||||
B .
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC_IRQHandler
|
||||
B .
|
||||
PUBWEAK TIMER0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER0_IRQHandler
|
||||
B .
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER1_IRQHandler
|
||||
B .
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIMER2_IRQHandler
|
||||
B .
|
||||
PUBWEAK RTC0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC0_IRQHandler
|
||||
B .
|
||||
PUBWEAK TEMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TEMP_IRQHandler
|
||||
B .
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RNG_IRQHandler
|
||||
B .
|
||||
PUBWEAK ECB_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ECB_IRQHandler
|
||||
B .
|
||||
PUBWEAK CCM_AAR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CCM_AAR_IRQHandler
|
||||
B .
|
||||
PUBWEAK WDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WDT_IRQHandler
|
||||
B .
|
||||
PUBWEAK RTC1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC1_IRQHandler
|
||||
B .
|
||||
PUBWEAK QDEC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
QDEC_IRQHandler
|
||||
B .
|
||||
PUBWEAK LPCOMP_COMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
LPCOMP_COMP_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI0_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI1_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI2_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI3_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI4_IRQHandler
|
||||
B .
|
||||
PUBWEAK SWI5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SWI5_IRQHandler
|
||||
B .
|
||||
|
||||
|
||||
END
|
||||
Binary file not shown.
|
|
@ -1,6 +1,6 @@
|
|||
/* mbed Microcontroller Library
|
||||
|
||||
* Copyright (c) 2013 Nordic Semiconductor.
|
||||
* Copyright (c) 2015 Nordic Semiconductor.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
|
|
@ -21,7 +21,6 @@
|
|||
#include "nrf51822.h"
|
||||
#include "system_nrf51822.h"
|
||||
|
||||
|
||||
#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
|
||||
|
||||
static bool is_manual_peripheral_setup_needed(void);
|
||||
|
|
@ -67,7 +66,7 @@ void SystemInit(void)
|
|||
|
||||
// Start the external 32khz crystal oscillator.
|
||||
|
||||
#ifdef TARGET_HRM1017
|
||||
#if defined(TARGET_DELTA_DFCM_NNN40) || defined(TARGET_HRM1017)
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos);
|
||||
#else
|
||||
NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,13 @@
|
|||
|
||||
LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
|
||||
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100
|
||||
; 32kB (0x8000) - 0x100 = 0x7F00
|
||||
RW_IRAM1 (0x10000000+0x100) (0x8000-0x100) {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file startup_LPC11U6x.s
|
||||
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
|
||||
; * NXP LPC11U6x Device Series
|
||||
; * @version V1.00
|
||||
; * @date 22. October 2013
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2013 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __initial_sp
|
||||
|
||||
__initial_sp EQU 0x10008000 ; Top of RAM from LPC1U68
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0
|
||||
DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1
|
||||
DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2
|
||||
DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3
|
||||
DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4
|
||||
DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5
|
||||
DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6
|
||||
DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7
|
||||
DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt
|
||||
DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt
|
||||
DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt
|
||||
DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts
|
||||
DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts
|
||||
DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts
|
||||
DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt
|
||||
DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt
|
||||
DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt
|
||||
DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt
|
||||
DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt
|
||||
DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt
|
||||
DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt
|
||||
DCD USART0_IRQHandler ; 16+21 USART0 interrupt
|
||||
DCD USB_IRQHandler ; 16+22 USB interrupt
|
||||
DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt
|
||||
DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts
|
||||
DCD RTC_IRQHandler ; 16+25 RTC interrupt
|
||||
DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt
|
||||
DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts
|
||||
DCD DMA_IRQHandler ; 16+28 DMA interrupt
|
||||
DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts
|
||||
DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt
|
||||
DCD 0 ; 16+31 Reserved
|
||||
|
||||
; <h> Code Read Protection
|
||||
; <o> Code Read Protection <0xFFFFFFFF=>CRP Disabled
|
||||
; <0x12345678=>CRP Level 1
|
||||
; <0x87654321=>CRP Level 2
|
||||
; <0x43218765=>CRP Level 3 (ARE YOU SURE?)
|
||||
; <0x4E697370=>NO ISP (ARE YOU SURE?)
|
||||
; </h>
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
Reserved_IRQHandler PROC
|
||||
EXPORT Reserved_IRQHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT PIN_INT0_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT1_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT2_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT3_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT4_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT5_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT6_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT USART1_4_IRQHandler [WEAK]
|
||||
EXPORT USART2_3_IRQHandler [WEAK]
|
||||
EXPORT SCT0_1_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT CT16B0_IRQHandler [WEAK]
|
||||
EXPORT CT16B1_IRQHandler [WEAK]
|
||||
EXPORT CT32B0_IRQHandler [WEAK]
|
||||
EXPORT CT32B1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT USB_FIQ_IRQHandler [WEAK]
|
||||
EXPORT ADC_A_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT BOD_WDT_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT ADC_B_IRQHandler [WEAK]
|
||||
EXPORT USBWAKEUP_IRQHandler [WEAK]
|
||||
|
||||
PIN_INT0_IRQHandler
|
||||
PIN_INT1_IRQHandler
|
||||
PIN_INT2_IRQHandler
|
||||
PIN_INT3_IRQHandler
|
||||
PIN_INT4_IRQHandler
|
||||
PIN_INT5_IRQHandler
|
||||
PIN_INT6_IRQHandler
|
||||
PIN_INT7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
USART1_4_IRQHandler
|
||||
USART2_3_IRQHandler
|
||||
SCT0_1_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
CT16B0_IRQHandler
|
||||
CT16B1_IRQHandler
|
||||
CT32B0_IRQHandler
|
||||
CT32B1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USB_IRQHandler
|
||||
USB_FIQ_IRQHandler
|
||||
ADC_A_IRQHandler
|
||||
RTC_IRQHandler
|
||||
BOD_WDT_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
DMA_IRQHandler
|
||||
ADC_B_IRQHandler
|
||||
USBWAKEUP_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
|
||||
LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
|
||||
ER_IROM1 0x00000000 0xC000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
||||
; 8KB - 0xC0 = 0x1F40
|
||||
RW_IRAM1 0x100000C0 0x1F40 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
|
||||
.ANY (USBRAM)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,325 @@
|
|||
;/*****************************************************************************
|
||||
; * @file: startup_LPC11xx.s
|
||||
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
|
||||
; * for the NXP LPC11xx Device Series
|
||||
; * @version: V1.0
|
||||
; * @date: 25. Nov. 2008
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; * Copyright (C) 2008 ARM Limited. All rights reserved.
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __initial_sp
|
||||
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
|
||||
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; for LPC11Uxx (With USB)
|
||||
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
|
||||
DCD FLEX_INT1_IRQHandler
|
||||
DCD FLEX_INT2_IRQHandler
|
||||
DCD FLEX_INT3_IRQHandler
|
||||
DCD FLEX_INT4_IRQHandler
|
||||
DCD FLEX_INT5_IRQHandler
|
||||
DCD FLEX_INT6_IRQHandler
|
||||
DCD FLEX_INT7_IRQHandler
|
||||
DCD GINT0_IRQHandler
|
||||
DCD GINT1_IRQHandler ; PIO0 (0:7)
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD Reserved_IRQHandler
|
||||
DCD Reserved_IRQHandler
|
||||
DCD Reserved_IRQHandler
|
||||
DCD SSP1_IRQHandler ; SSP1
|
||||
DCD I2C_IRQHandler ; I2C
|
||||
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
|
||||
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
|
||||
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
|
||||
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
|
||||
DCD SSP0_IRQHandler ; SSP0
|
||||
DCD UART_IRQHandler ; UART
|
||||
DCD USB_IRQHandler ; USB IRQ
|
||||
DCD USB_FIQHandler ; USB FIQ
|
||||
DCD ADC_IRQHandler ; A/D Converter
|
||||
DCD WDT_IRQHandler ; Watchdog timer
|
||||
DCD BOD_IRQHandler ; Brown Out Detect
|
||||
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD USBWakeup_IRQHandler ; USB wake up
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
|
||||
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
|
||||
; for particular peripheral.
|
||||
;NMI_Handler PROC
|
||||
; EXPORT NMI_Handler [WEAK]
|
||||
; B .
|
||||
; ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
Reserved_IRQHandler PROC
|
||||
EXPORT Reserved_IRQHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; for LPC11Uxx (With USB)
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
EXPORT FLEX_INT0_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT1_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT2_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT3_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT4_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT5_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT6_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_1_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT UART_IRQHandler [WEAK]
|
||||
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT USB_FIQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT USBWakeup_IRQHandler [WEAK]
|
||||
|
||||
NMI_Handler
|
||||
FLEX_INT0_IRQHandler
|
||||
FLEX_INT1_IRQHandler
|
||||
FLEX_INT2_IRQHandler
|
||||
FLEX_INT3_IRQHandler
|
||||
FLEX_INT4_IRQHandler
|
||||
FLEX_INT5_IRQHandler
|
||||
FLEX_INT6_IRQHandler
|
||||
FLEX_INT7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
I2C_IRQHandler
|
||||
TIMER16_0_IRQHandler
|
||||
TIMER16_1_IRQHandler
|
||||
TIMER32_0_IRQHandler
|
||||
TIMER32_1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
UART_IRQHandler
|
||||
USB_IRQHandler
|
||||
USB_FIQHandler
|
||||
ADC_IRQHandler
|
||||
WDT_IRQHandler
|
||||
BOD_IRQHandler
|
||||
FMC_IRQHandler
|
||||
USBWakeup_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
|
||||
LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
|
||||
ER_IROM1 0x00000000 0xC000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
||||
; 8KB - 0xC0 = 0x1F40
|
||||
RW_IRAM1 0x100000C0 0x1F40 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
|
||||
.ANY (USBRAM)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,325 @@
|
|||
;/*****************************************************************************
|
||||
; * @file: startup_LPC11xx.s
|
||||
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
|
||||
; * for the NXP LPC11xx Device Series
|
||||
; * @version: V1.0
|
||||
; * @date: 25. Nov. 2008
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; * Copyright (C) 2008 ARM Limited. All rights reserved.
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __initial_sp
|
||||
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
|
||||
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; for LPC11Uxx (With USB)
|
||||
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
|
||||
DCD FLEX_INT1_IRQHandler
|
||||
DCD FLEX_INT2_IRQHandler
|
||||
DCD FLEX_INT3_IRQHandler
|
||||
DCD FLEX_INT4_IRQHandler
|
||||
DCD FLEX_INT5_IRQHandler
|
||||
DCD FLEX_INT6_IRQHandler
|
||||
DCD FLEX_INT7_IRQHandler
|
||||
DCD GINT0_IRQHandler
|
||||
DCD GINT1_IRQHandler ; PIO0 (0:7)
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD Reserved_IRQHandler
|
||||
DCD Reserved_IRQHandler
|
||||
DCD Reserved_IRQHandler
|
||||
DCD SSP1_IRQHandler ; SSP1
|
||||
DCD I2C_IRQHandler ; I2C
|
||||
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
|
||||
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
|
||||
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
|
||||
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
|
||||
DCD SSP0_IRQHandler ; SSP0
|
||||
DCD UART_IRQHandler ; UART
|
||||
DCD USB_IRQHandler ; USB IRQ
|
||||
DCD USB_FIQHandler ; USB FIQ
|
||||
DCD ADC_IRQHandler ; A/D Converter
|
||||
DCD WDT_IRQHandler ; Watchdog timer
|
||||
DCD BOD_IRQHandler ; Brown Out Detect
|
||||
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD USBWakeup_IRQHandler ; USB wake up
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
|
||||
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
|
||||
; for particular peripheral.
|
||||
;NMI_Handler PROC
|
||||
; EXPORT NMI_Handler [WEAK]
|
||||
; B .
|
||||
; ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
Reserved_IRQHandler PROC
|
||||
EXPORT Reserved_IRQHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; for LPC11Uxx (With USB)
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
EXPORT FLEX_INT0_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT1_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT2_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT3_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT4_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT5_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT6_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_1_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT UART_IRQHandler [WEAK]
|
||||
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT USB_FIQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT USBWakeup_IRQHandler [WEAK]
|
||||
|
||||
NMI_Handler
|
||||
FLEX_INT0_IRQHandler
|
||||
FLEX_INT1_IRQHandler
|
||||
FLEX_INT2_IRQHandler
|
||||
FLEX_INT3_IRQHandler
|
||||
FLEX_INT4_IRQHandler
|
||||
FLEX_INT5_IRQHandler
|
||||
FLEX_INT6_IRQHandler
|
||||
FLEX_INT7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
I2C_IRQHandler
|
||||
TIMER16_0_IRQHandler
|
||||
TIMER16_1_IRQHandler
|
||||
TIMER32_0_IRQHandler
|
||||
TIMER32_1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
UART_IRQHandler
|
||||
USB_IRQHandler
|
||||
USB_FIQHandler
|
||||
ADC_IRQHandler
|
||||
WDT_IRQHandler
|
||||
BOD_IRQHandler
|
||||
FMC_IRQHandler
|
||||
USBWakeup_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
|
||||
LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
|
||||
ER_IROM1 0x00000000 0xC000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
||||
; 8KB - 0xC0 = 0x1F40
|
||||
RW_IRAM1 0x100000C0 0x1F40 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
|
||||
.ANY (USBRAM)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,308 @@
|
|||
;/*****************************************************************************
|
||||
; * @file: startup_LPC11xx.s
|
||||
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
|
||||
; * for the NXP LPC11xx Device Series
|
||||
; * @version: V1.0
|
||||
; * @date: 25. Nov. 2008
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; * Copyright (C) 2008 ARM Limited. All rights reserved.
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; for LPC11Uxx (With USB)
|
||||
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
|
||||
DCD FLEX_INT1_IRQHandler
|
||||
DCD FLEX_INT2_IRQHandler
|
||||
DCD FLEX_INT3_IRQHandler
|
||||
DCD FLEX_INT4_IRQHandler
|
||||
DCD FLEX_INT5_IRQHandler
|
||||
DCD FLEX_INT6_IRQHandler
|
||||
DCD FLEX_INT7_IRQHandler
|
||||
DCD GINT0_IRQHandler
|
||||
DCD GINT1_IRQHandler ; PIO0 (0:7)
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD Reserved_IRQHandler
|
||||
DCD Reserved_IRQHandler
|
||||
DCD Reserved_IRQHandler
|
||||
DCD SSP1_IRQHandler ; SSP1
|
||||
DCD I2C_IRQHandler ; I2C
|
||||
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
|
||||
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
|
||||
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
|
||||
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
|
||||
DCD SSP0_IRQHandler ; SSP0
|
||||
DCD UART_IRQHandler ; UART
|
||||
DCD USB_IRQHandler ; USB IRQ
|
||||
DCD USB_FIQHandler ; USB FIQ
|
||||
DCD ADC_IRQHandler ; A/D Converter
|
||||
DCD WDT_IRQHandler ; Watchdog timer
|
||||
DCD BOD_IRQHandler ; Brown Out Detect
|
||||
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD USBWakeup_IRQHandler ; USB wake up
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
|
||||
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
|
||||
; for particular peripheral.
|
||||
;NMI_Handler PROC
|
||||
; EXPORT NMI_Handler [WEAK]
|
||||
; B .
|
||||
; ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
Reserved_IRQHandler PROC
|
||||
EXPORT Reserved_IRQHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; for LPC11Uxx (With USB)
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
EXPORT FLEX_INT0_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT1_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT2_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT3_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT4_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT5_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT6_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_1_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT UART_IRQHandler [WEAK]
|
||||
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT USB_FIQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT USBWakeup_IRQHandler [WEAK]
|
||||
|
||||
NMI_Handler
|
||||
FLEX_INT0_IRQHandler
|
||||
FLEX_INT1_IRQHandler
|
||||
FLEX_INT2_IRQHandler
|
||||
FLEX_INT3_IRQHandler
|
||||
FLEX_INT4_IRQHandler
|
||||
FLEX_INT5_IRQHandler
|
||||
FLEX_INT6_IRQHandler
|
||||
FLEX_INT7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
I2C_IRQHandler
|
||||
TIMER16_0_IRQHandler
|
||||
TIMER16_1_IRQHandler
|
||||
TIMER32_0_IRQHandler
|
||||
TIMER32_1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
UART_IRQHandler
|
||||
USB_IRQHandler
|
||||
USB_FIQHandler
|
||||
ADC_IRQHandler
|
||||
WDT_IRQHandler
|
||||
BOD_IRQHandler
|
||||
FMC_IRQHandler
|
||||
USBWakeup_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
|
||||
LR_IROM1 0x00000000 0xC000 { ; load region size_region (48k)
|
||||
ER_IROM1 0x00000000 0xC000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
||||
; 8KB - 0xC0 = 0x1F40
|
||||
RW_IRAM1 0x100000C0 0x1F40 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
|
||||
.ANY (USBRAM)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,308 @@
|
|||
;/*****************************************************************************
|
||||
; * @file: startup_LPC11xx.s
|
||||
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
|
||||
; * for the NXP LPC11xx Device Series
|
||||
; * @version: V1.0
|
||||
; * @date: 25. Nov. 2008
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; * Copyright (C) 2008 ARM Limited. All rights reserved.
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
__initial_sp EQU 0x10002000 ; Top of RAM from LPC11U
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
; for LPC11Uxx (With USB)
|
||||
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
|
||||
DCD FLEX_INT1_IRQHandler
|
||||
DCD FLEX_INT2_IRQHandler
|
||||
DCD FLEX_INT3_IRQHandler
|
||||
DCD FLEX_INT4_IRQHandler
|
||||
DCD FLEX_INT5_IRQHandler
|
||||
DCD FLEX_INT6_IRQHandler
|
||||
DCD FLEX_INT7_IRQHandler
|
||||
DCD GINT0_IRQHandler
|
||||
DCD GINT1_IRQHandler ; PIO0 (0:7)
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD Reserved_IRQHandler
|
||||
DCD Reserved_IRQHandler
|
||||
DCD Reserved_IRQHandler
|
||||
DCD SSP1_IRQHandler ; SSP1
|
||||
DCD I2C_IRQHandler ; I2C
|
||||
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
|
||||
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
|
||||
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
|
||||
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
|
||||
DCD SSP0_IRQHandler ; SSP0
|
||||
DCD UART_IRQHandler ; UART
|
||||
DCD USB_IRQHandler ; USB IRQ
|
||||
DCD USB_FIQHandler ; USB FIQ
|
||||
DCD ADC_IRQHandler ; A/D Converter
|
||||
DCD WDT_IRQHandler ; Watchdog timer
|
||||
DCD BOD_IRQHandler ; Brown Out Detect
|
||||
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
DCD USBWakeup_IRQHandler ; USB wake up
|
||||
DCD Reserved_IRQHandler ; Reserved
|
||||
|
||||
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
DCD 0xFFFFFFFF ; Datafill
|
||||
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
AREA |.ARM.__at_0x02FC|, CODE, READONLY
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
ENDIF
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
|
||||
; for particular peripheral.
|
||||
;NMI_Handler PROC
|
||||
; EXPORT NMI_Handler [WEAK]
|
||||
; B .
|
||||
; ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
Reserved_IRQHandler PROC
|
||||
EXPORT Reserved_IRQHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; for LPC11Uxx (With USB)
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
EXPORT FLEX_INT0_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT1_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT2_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT3_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT4_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT5_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT6_IRQHandler [WEAK]
|
||||
EXPORT FLEX_INT7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT I2C_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_1_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_0_IRQHandler [WEAK]
|
||||
EXPORT TIMER32_1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT UART_IRQHandler [WEAK]
|
||||
|
||||
EXPORT USB_IRQHandler [WEAK]
|
||||
EXPORT USB_FIQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT WDT_IRQHandler [WEAK]
|
||||
EXPORT BOD_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT USBWakeup_IRQHandler [WEAK]
|
||||
|
||||
NMI_Handler
|
||||
FLEX_INT0_IRQHandler
|
||||
FLEX_INT1_IRQHandler
|
||||
FLEX_INT2_IRQHandler
|
||||
FLEX_INT3_IRQHandler
|
||||
FLEX_INT4_IRQHandler
|
||||
FLEX_INT5_IRQHandler
|
||||
FLEX_INT6_IRQHandler
|
||||
FLEX_INT7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
I2C_IRQHandler
|
||||
TIMER16_0_IRQHandler
|
||||
TIMER16_1_IRQHandler
|
||||
TIMER32_0_IRQHandler
|
||||
TIMER32_1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
UART_IRQHandler
|
||||
USB_IRQHandler
|
||||
USB_FIQHandler
|
||||
ADC_IRQHandler
|
||||
WDT_IRQHandler
|
||||
BOD_IRQHandler
|
||||
FMC_IRQHandler
|
||||
USBWakeup_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
/* Linker script to configure memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K
|
||||
RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
|
||||
USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text.Reset_Handler)
|
||||
|
||||
/* Only vectors and code running at reset are safe to be in first 512
|
||||
bytes since RAM can be mapped into this area for RAM based interrupt
|
||||
vectors. */
|
||||
. = 0x00000200;
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
/* Linker script to configure memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 48K
|
||||
RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
|
||||
USB_RAM (rwx): ORIGIN = 0x20004000, LENGTH = 0x800
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text.Reset_Handler)
|
||||
|
||||
/* Only vectors and code running at reset are safe to be in first 512
|
||||
bytes since RAM can be mapped into this area for RAM based interrupt
|
||||
vectors. */
|
||||
. = 0x00000200;
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
|
@ -118,8 +118,8 @@ __isr_vector:
|
|||
.long TIMER32_1_IRQHandler /* 35 19 CT32B1 32 bit timer 1 */
|
||||
.long SSP0_IRQHandler /* 36 20 SSP */
|
||||
.long UART_IRQHandler /* 37 21 UART */
|
||||
.long Default_Handler /* 38 22 */
|
||||
.long Default_Handler /* 39 23 */
|
||||
.long USB_IRQHandler /* 38 22 USB IRQ */
|
||||
.long USB_FIQHandler /* 39 23 USB FIQ */
|
||||
.long ADC_IRQHandler /* 40 24 ADC end of conversion */
|
||||
.long WDT_IRQHandler /* 41 25 Watchdog interrupt (WDINT) */
|
||||
.long BOD_IRQHandler /* 42 26 BOD Brown-out detect */
|
||||
|
|
@ -203,6 +203,8 @@ Reset_Handler:
|
|||
def_irq_default_handler TIMER32_1_IRQHandler
|
||||
def_irq_default_handler SSP0_IRQHandler
|
||||
def_irq_default_handler UART_IRQHandler
|
||||
def_irq_default_handler USB_IRQHandler
|
||||
def_irq_default_handler USB_FIQHandler
|
||||
def_irq_default_handler ADC_IRQHandler
|
||||
def_irq_default_handler WDT_IRQHandler
|
||||
def_irq_default_handler BOD_IRQHandler
|
||||
|
|
|
|||
|
|
@ -100,14 +100,18 @@
|
|||
// </h>
|
||||
// </e>
|
||||
*/
|
||||
|
||||
// 1 == IRC 12Mhz 2 == System Oscillator 12Mhz Xtal:
|
||||
#define CLOCK_SETUP 1
|
||||
//use PLL for IRC
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
|
||||
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
|
||||
#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 MSEL=1 => M=2; PSEL=2 => 2P=8; PLLCLKOUT = (12x2) = 24MHz
|
||||
//#define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
|
||||
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 DIV=1 => SYSTEMCORECLK = 24 / 1 = 24MHz
|
||||
//#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
|
||||
/*
|
||||
//-------- <<< end of configuration section >>> ------------------------------
|
||||
*/
|
||||
|
|
@ -235,9 +239,10 @@
|
|||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
//Replaced SystemCoreClock with MainClock
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
|
@ -268,46 +273,46 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
|||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
MainClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
MainClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
MainClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
MainClock = 0;
|
||||
break;
|
||||
case 3: /* CLKIN pin */
|
||||
SystemCoreClock = __CLKIN_CLK;
|
||||
MainClock = __CLKIN_CLK;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
MainClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
MainClock = 0;
|
||||
break;
|
||||
case 3: /* CLKIN pin */
|
||||
SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -102,20 +102,24 @@
|
|||
*/
|
||||
#define CLOCK_SETUP 1 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
|
||||
|
||||
//Fixed to use PLL
|
||||
#if (CLOCK_SETUP == 1)
|
||||
//use PLL for IRC
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
|
||||
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||
#define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
#define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
|
||||
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
|
||||
#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
|
||||
|
||||
#elif (CLOCK_SETUP == 2)
|
||||
//use PLL for XTAL
|
||||
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
|
||||
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
|
||||
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
|
||||
#define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
|
||||
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 Select XTAL
|
||||
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
|
||||
#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -245,9 +249,10 @@
|
|||
/*----------------------------------------------------------------------------
|
||||
Clock Variable definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
|
||||
//Replaced SystemCoreClock with MainClock
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock functions
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
|
@ -278,47 +283,46 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
|
|||
|
||||
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
MainClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* Input Clock to System PLL */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK;
|
||||
MainClock = __IRC_OSC_CLK;
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK;
|
||||
MainClock = __SYS_OSC_CLK;
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
MainClock = 0;
|
||||
break;
|
||||
case 3: /* CLKIN pin */
|
||||
SystemCoreClock = __CLKIN_CLK;
|
||||
MainClock = __CLKIN_CLK;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2: /* WDT Oscillator */
|
||||
SystemCoreClock = wdt_osc;
|
||||
MainClock = wdt_osc;
|
||||
break;
|
||||
case 3: /* System PLL Clock Out */
|
||||
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
|
||||
case 0: /* Internal RC oscillator */
|
||||
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
case 1: /* System oscillator */
|
||||
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
case 2: /* Reserved */
|
||||
SystemCoreClock = 0;
|
||||
MainClock = 0;
|
||||
break;
|
||||
case 3: /* CLKIN pin */
|
||||
SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
break;
|
||||
}
|
||||
|
||||
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
|
||||
|
||||
SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ extern "C" {
|
|||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t MainClock; /*!< Main Clock Frequency */
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@
|
|||
// <2=> Reserved
|
||||
// <3=> CLKIN. External clock input.
|
||||
// </h>
|
||||
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
|
||||
#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
|
||||
//
|
||||
// <h> Main Clock Source Select Register (MAINCLKSEL)
|
||||
// <o.0..1> SEL: Clock Source for Main Clock
|
||||
|
|
|
|||
|
|
@ -0,0 +1,445 @@
|
|||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f439xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.0
|
||||
;* Date : 19-June-2014
|
||||
;* Description : STM32F439x devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __initial_sp
|
||||
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp EQU 0x20030000 ; Top of RAM
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit EQU (__initial_sp - Stack_Size)
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD CRYP_IRQHandler ; CRYPTO
|
||||
DCD HASH_RNG_IRQHandler ; Hash and Rng
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD SAI1_IRQHandler ; SAI1
|
||||
DCD LTDC_IRQHandler ; LTDC
|
||||
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT DCMI_IRQHandler [WEAK]
|
||||
EXPORT CRYP_IRQHandler [WEAK]
|
||||
EXPORT HASH_RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT LTDC_IRQHandler [WEAK]
|
||||
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Stream0_IRQHandler
|
||||
DMA1_Stream1_IRQHandler
|
||||
DMA1_Stream2_IRQHandler
|
||||
DMA1_Stream3_IRQHandler
|
||||
DMA1_Stream4_IRQHandler
|
||||
DMA1_Stream5_IRQHandler
|
||||
DMA1_Stream6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
DMA1_Stream7_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Stream0_IRQHandler
|
||||
DMA2_Stream1_IRQHandler
|
||||
DMA2_Stream2_IRQHandler
|
||||
DMA2_Stream3_IRQHandler
|
||||
DMA2_Stream4_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SCE_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMA2_Stream5_IRQHandler
|
||||
DMA2_Stream6_IRQHandler
|
||||
DMA2_Stream7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
DCMI_IRQHandler
|
||||
CRYP_IRQHandler
|
||||
HASH_RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
LTDC_IRQHandler
|
||||
LTDC_ER_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
; Scatter-Loading Description File
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; Copyright (c) 2014, STMicroelectronics
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice,
|
||||
; this list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software
|
||||
; without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
; STM32F439ZI: 2048 KB FLASH (0x200000) + 256 KB SRAM (0x30000 + 0x10000)
|
||||
LR_IROM1 0x08000000 0x200000 { ; load region size_region
|
||||
|
||||
ER_IROM1 0x08000000 0x200000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; Total: 107 vectors = 428 bytes (0x1AC) to be used
|
||||
; should match ER_IROM1::RESET/4 and cmsis_nvic.h::NVIC_NUM_VECTORS
|
||||
RW_IRAM1 (0x20000000 + (107*4)) (0x30000 - (107*4)) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_IRAM2 (0x10000000) 0x10000 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1,4 +1,6 @@
|
|||
/* mbed Microcontroller Library
|
||||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
|
|
@ -24,48 +26,31 @@
|
|||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef MBED_GPIO_OBJECT_H
|
||||
#define MBED_GPIO_OBJECT_H
|
||||
|
||||
#include "mbed_assert.h"
|
||||
#include "cmsis.h"
|
||||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
PinName pin;
|
||||
uint32_t mask;
|
||||
__IO uint32_t *reg_in;
|
||||
__IO uint32_t *reg_set;
|
||||
__IO uint32_t *reg_clr;
|
||||
} gpio_t;
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static inline void gpio_write(gpio_t *obj, int value)
|
||||
{
|
||||
MBED_ASSERT(obj->pin != (PinName)NC);
|
||||
if (value) {
|
||||
*obj->reg_set = obj->mask;
|
||||
} else {
|
||||
*obj->reg_clr = obj->mask;
|
||||
}
|
||||
}
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
static inline int gpio_read(gpio_t *obj)
|
||||
{
|
||||
MBED_ASSERT(obj->pin != (PinName)NC);
|
||||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,467 @@
|
|||
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f439xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.0
|
||||
;* Date : 19-June-2014
|
||||
;* Description : STM32F439x devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;*******************************************************************************
|
||||
;
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;
|
||||
;*******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD CRYP_IRQHandler ; CRYPTO
|
||||
DCD HASH_RNG_IRQHandler ; Hash and Rng
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD SAI1_IRQHandler ; SAI1
|
||||
DCD LTDC_IRQHandler ; LTDC
|
||||
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SCE_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Stream7_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream0_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream4_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT ETH_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SCE_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Stream7_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT OTG_HS_IRQHandler [WEAK]
|
||||
EXPORT DCMI_IRQHandler [WEAK]
|
||||
EXPORT CRYP_IRQHandler [WEAK]
|
||||
EXPORT HASH_RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT SPI6_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT LTDC_IRQHandler [WEAK]
|
||||
EXPORT LTDC_ER_IRQHandler [WEAK]
|
||||
EXPORT DMA2D_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMP_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Stream0_IRQHandler
|
||||
DMA1_Stream1_IRQHandler
|
||||
DMA1_Stream2_IRQHandler
|
||||
DMA1_Stream3_IRQHandler
|
||||
DMA1_Stream4_IRQHandler
|
||||
DMA1_Stream5_IRQHandler
|
||||
DMA1_Stream6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SCE_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
DMA1_Stream7_IRQHandler
|
||||
FMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_DAC_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Stream0_IRQHandler
|
||||
DMA2_Stream1_IRQHandler
|
||||
DMA2_Stream2_IRQHandler
|
||||
DMA2_Stream3_IRQHandler
|
||||
DMA2_Stream4_IRQHandler
|
||||
ETH_IRQHandler
|
||||
ETH_WKUP_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SCE_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
DMA2_Stream5_IRQHandler
|
||||
DMA2_Stream6_IRQHandler
|
||||
DMA2_Stream7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
OTG_HS_IRQHandler
|
||||
DCMI_IRQHandler
|
||||
CRYP_IRQHandler
|
||||
HASH_RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
SPI6_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
LTDC_IRQHandler
|
||||
LTDC_ER_IRQHandler
|
||||
DMA2D_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
; Scatter-Loading Description File
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; Copyright (c) 2014, STMicroelectronics
|
||||
; All rights reserved.
|
||||
;
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
;
|
||||
; 1. Redistributions of source code must retain the above copyright notice,
|
||||
; this list of conditions and the following disclaimer.
|
||||
; 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
; this list of conditions and the following disclaimer in the documentation
|
||||
; and/or other materials provided with the distribution.
|
||||
; 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
; may be used to endorse or promote products derived from this software
|
||||
; without specific prior written permission.
|
||||
;
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
||||
; STM32F439ZI: 512 KB FLASH (0x80000) + 256 KB SRAM (0x30000 + 0x10000)
|
||||
LR_IROM1 0x08000000 0x80000 { ; load region size_region
|
||||
|
||||
ER_IROM1 0x08000000 0x80000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
|
||||
RW_IRAM1 (0x20000000+0x1AC) (0x30000-0x1AC) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
RW_IRAM1 (0x10000000) (0x10000) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1,4 +1,6 @@
|
|||
/* mbed Microcontroller Library
|
||||
/* mbed Microcontroller Library - stackheap
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
|
|
@ -24,48 +26,31 @@
|
|||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef MBED_GPIO_OBJECT_H
|
||||
#define MBED_GPIO_OBJECT_H
|
||||
|
||||
#include "mbed_assert.h"
|
||||
#include "cmsis.h"
|
||||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
PinName pin;
|
||||
uint32_t mask;
|
||||
__IO uint32_t *reg_in;
|
||||
__IO uint32_t *reg_set;
|
||||
__IO uint32_t *reg_clr;
|
||||
} gpio_t;
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
static inline void gpio_write(gpio_t *obj, int value)
|
||||
{
|
||||
MBED_ASSERT(obj->pin != (PinName)NC);
|
||||
if (value) {
|
||||
*obj->reg_set = obj->mask;
|
||||
} else {
|
||||
*obj->reg_clr = obj->mask;
|
||||
}
|
||||
}
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
static inline int gpio_read(gpio_t *obj)
|
||||
{
|
||||
MBED_ASSERT(obj->pin != (PinName)NC);
|
||||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
/* Linker script to configure memory regions. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM (rwx) : ORIGIN = 0x200001AC, LENGTH = 192k - 0x1AC
|
||||
RAM2 (rwx) : ORIGIN = 0x10000000, LENGTH = 64k
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* _estack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
_sidata = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
_sdata = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
_edata = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
_sbss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
_ebss = .;
|
||||
} > RAM
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
*(.stack*)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
_estack = __StackTop;
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
|
@ -0,0 +1,570 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f439xx.s
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief STM32F439xx Devices vector table for Atollic TrueSTUDIO toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr sp, =_estack /* set stack pointer */
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window WatchDog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||
.word FLASH_IRQHandler /* FLASH */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word CAN1_TX_IRQHandler /* CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDIO_IRQHandler /* SDIO */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word DCMI_IRQHandler /* DCMI */
|
||||
.word CRYP_IRQHandler /* CRYP crypto */
|
||||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word SAI1_IRQHandler /* SAI1 */
|
||||
.word LTDC_IRQHandler /* LTDC */
|
||||
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM9_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM10_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_SCE_IRQHandler
|
||||
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRYP_IRQHandler
|
||||
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_RNG_IRQHandler
|
||||
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_IRQHandler
|
||||
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_ER_IRQHandler
|
||||
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,698 @@
|
|||
;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32f439xx.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.1.0
|
||||
;* Date : 19-June-2014
|
||||
;* Description : STM32F439xx devices vector table for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
;* 1. Redistributions of source code must retain the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer.
|
||||
;* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
;* this list of conditions and the following disclaimer in the documentation
|
||||
;* and/or other materials provided with the distribution.
|
||||
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
;* may be used to endorse or promote products derived from this software
|
||||
;* without specific prior written permission.
|
||||
;*
|
||||
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
;*
|
||||
;*******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detection
|
||||
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
|
||||
DCD FLASH_IRQHandler ; FLASH
|
||||
DCD RCC_IRQHandler ; RCC
|
||||
DCD EXTI0_IRQHandler ; EXTI Line0
|
||||
DCD EXTI1_IRQHandler ; EXTI Line1
|
||||
DCD EXTI2_IRQHandler ; EXTI Line2
|
||||
DCD EXTI3_IRQHandler ; EXTI Line3
|
||||
DCD EXTI4_IRQHandler ; EXTI Line4
|
||||
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
|
||||
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
|
||||
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
|
||||
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
|
||||
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
|
||||
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
|
||||
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
|
||||
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
|
||||
DCD CAN1_TX_IRQHandler ; CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
|
||||
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
|
||||
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
|
||||
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
|
||||
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; TIM2
|
||||
DCD TIM3_IRQHandler ; TIM3
|
||||
DCD TIM4_IRQHandler ; TIM4
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EV_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_IRQHandler ; SPI2
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
|
||||
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
|
||||
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
|
||||
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
|
||||
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
|
||||
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
|
||||
DCD FMC_IRQHandler ; FMC
|
||||
DCD SDIO_IRQHandler ; SDIO
|
||||
DCD TIM5_IRQHandler ; TIM5
|
||||
DCD SPI3_IRQHandler ; SPI3
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
|
||||
DCD TIM7_IRQHandler ; TIM7
|
||||
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
|
||||
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
|
||||
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
|
||||
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
|
||||
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
|
||||
DCD ETH_IRQHandler ; Ethernet
|
||||
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
|
||||
DCD OTG_FS_IRQHandler ; USB OTG FS
|
||||
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
|
||||
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
|
||||
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 event
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 error
|
||||
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
|
||||
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
|
||||
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
|
||||
DCD OTG_HS_IRQHandler ; USB OTG HS
|
||||
DCD DCMI_IRQHandler ; DCMI
|
||||
DCD CRYP_IRQHandler ; CRYP crypto
|
||||
DCD HASH_RNG_IRQHandler ; Hash and Rng
|
||||
DCD FPU_IRQHandler ; FPU
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD SPI5_IRQHandler ; SPI5
|
||||
DCD SPI6_IRQHandler ; SPI6
|
||||
DCD SAI1_IRQHandler ; SAI1
|
||||
DCD LTDC_IRQHandler ; LTDC
|
||||
DCD LTDC_ER_IRQHandler ; LTDC error
|
||||
DCD DMA2D_IRQHandler ; DMA2D
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PVD_IRQHandler
|
||||
B PVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TAMP_STAMP_IRQHandler
|
||||
B TAMP_STAMP_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream0_IRQHandler
|
||||
B DMA1_Stream0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream1_IRQHandler
|
||||
B DMA1_Stream1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream2_IRQHandler
|
||||
B DMA1_Stream2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream3_IRQHandler
|
||||
B DMA1_Stream3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream4_IRQHandler
|
||||
B DMA1_Stream4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream5_IRQHandler
|
||||
B DMA1_Stream5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream6_IRQHandler
|
||||
B DMA1_Stream6_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_SCE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_SCE_IRQHandler
|
||||
B CAN1_SCE_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_TIM9_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM1_BRK_TIM9_IRQHandler
|
||||
B TIM1_BRK_TIM9_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM1_UP_TIM10_IRQHandler
|
||||
B TIM1_UP_TIM10_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM1_TRG_COM_TIM11_IRQHandler
|
||||
B TIM1_TRG_COM_TIM11_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM3_IRQHandler
|
||||
B TIM3_IRQHandler
|
||||
|
||||
PUBWEAK TIM4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM4_IRQHandler
|
||||
B TIM4_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
B OTG_FS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_BRK_TIM12_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM8_BRK_TIM12_IRQHandler
|
||||
B TIM8_BRK_TIM12_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_UP_TIM13_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM8_UP_TIM13_IRQHandler
|
||||
B TIM8_UP_TIM13_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM8_TRG_COM_TIM14_IRQHandler
|
||||
B TIM8_TRG_COM_TIM14_IRQHandler
|
||||
|
||||
PUBWEAK TIM8_CC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM8_CC_IRQHandler
|
||||
B TIM8_CC_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Stream7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Stream7_IRQHandler
|
||||
B DMA1_Stream7_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SDIO_IRQHandler
|
||||
B SDIO_IRQHandler
|
||||
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM5_IRQHandler
|
||||
B TIM5_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK TIM6_DAC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM6_DAC_IRQHandler
|
||||
B TIM6_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TIM7_IRQHandler
|
||||
B TIM7_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream0_IRQHandler
|
||||
B DMA2_Stream0_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream1_IRQHandler
|
||||
B DMA2_Stream1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream2_IRQHandler
|
||||
B DMA2_Stream2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream3_IRQHandler
|
||||
B DMA2_Stream3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream4_IRQHandler
|
||||
B DMA2_Stream4_IRQHandler
|
||||
|
||||
PUBWEAK ETH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ETH_IRQHandler
|
||||
B ETH_IRQHandler
|
||||
|
||||
PUBWEAK ETH_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ETH_WKUP_IRQHandler
|
||||
B ETH_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_TX_IRQHandler
|
||||
B CAN2_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_RX0_IRQHandler
|
||||
B CAN2_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_RX1_IRQHandler
|
||||
B CAN2_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_SCE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_SCE_IRQHandler
|
||||
B CAN2_SCE_IRQHandler
|
||||
|
||||
PUBWEAK OTG_FS_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_FS_IRQHandler
|
||||
B OTG_FS_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream5_IRQHandler
|
||||
B DMA2_Stream5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream6_IRQHandler
|
||||
B DMA2_Stream6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Stream7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Stream7_IRQHandler
|
||||
B DMA2_Stream7_IRQHandler
|
||||
|
||||
PUBWEAK USART6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART6_IRQHandler
|
||||
B USART6_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_EP1_OUT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_HS_EP1_OUT_IRQHandler
|
||||
B OTG_HS_EP1_OUT_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_EP1_IN_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_HS_EP1_IN_IRQHandler
|
||||
B OTG_HS_EP1_IN_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_HS_WKUP_IRQHandler
|
||||
B OTG_HS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK OTG_HS_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
OTG_HS_IRQHandler
|
||||
B OTG_HS_IRQHandler
|
||||
|
||||
PUBWEAK DCMI_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DCMI_IRQHandler
|
||||
B DCMI_IRQHandler
|
||||
|
||||
PUBWEAK CRYP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CRYP_IRQHandler
|
||||
B CRYP_IRQHandler
|
||||
|
||||
PUBWEAK HASH_RNG_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HASH_RNG_IRQHandler
|
||||
B HASH_RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK UART7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART7_IRQHandler
|
||||
B UART7_IRQHandler
|
||||
|
||||
PUBWEAK UART8_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART8_IRQHandler
|
||||
B UART8_IRQHandler
|
||||
|
||||
PUBWEAK SPI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI4_IRQHandler
|
||||
B SPI4_IRQHandler
|
||||
|
||||
PUBWEAK SPI5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI5_IRQHandler
|
||||
B SPI5_IRQHandler
|
||||
|
||||
PUBWEAK SPI6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI6_IRQHandler
|
||||
B SPI6_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SAI1_IRQHandler
|
||||
B SAI1_IRQHandler
|
||||
|
||||
PUBWEAK LTDC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
LTDC_IRQHandler
|
||||
B LTDC_IRQHandler
|
||||
|
||||
PUBWEAK LTDC_ER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
LTDC_ER_IRQHandler
|
||||
B LTDC_ER_IRQHandler
|
||||
|
||||
PUBWEAK DMA2D_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2D_IRQHandler
|
||||
B DMA2D_IRQHandler
|
||||
|
||||
|
||||
END
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
|
||||
define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
|
||||
define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -1,4 +1,6 @@
|
|||
/* mbed Microcontroller Library
|
||||
* A generic CMSIS include header
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
|
|
@ -24,14 +26,13 @@
|
|||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "cmsis.h"
|
||||
|
||||
// This function is called after RAM initialization and before main.
|
||||
void mbed_sdk_init()
|
||||
{
|
||||
// Update the SystemCoreClock variable.
|
||||
SystemCoreClockUpdate();
|
||||
// Need to restart HAL driver after the RAM is initialized
|
||||
HAL_Init();
|
||||
}
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||
uint32_t i;
|
||||
|
||||
// Copy and switch to dynamic vectors if the first time called
|
||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||
uint32_t *old_vectors = vectors;
|
||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
|
||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||
}
|
||||
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
}
|
||||
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
|
@ -1,4 +1,5 @@
|
|||
/* mbed Microcontroller Library
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2014, STMicroelectronics
|
||||
* All rights reserved.
|
||||
|
|
@ -26,34 +27,29 @@
|
|||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#include "sleep_api.h"
|
||||
*/
|
||||
|
||||
#if DEVICE_SLEEP
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
// STM32F439ZI
|
||||
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
|
||||
// MCU Peripherals: 91 vectors = 364 bytes from 0x40 to 0x1AB
|
||||
// Total: 107 vectors = 428 bytes (0x1AC) to be reserved in RAM
|
||||
#define NVIC_NUM_VECTORS 107
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
void sleep(void)
|
||||
{
|
||||
// Stop HAL systick
|
||||
HAL_SuspendTick();
|
||||
// Request to enter SLEEP mode
|
||||
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
|
||||
// Restart HAL systick
|
||||
HAL_ResumeTick();
|
||||
}
|
||||
|
||||
void deepsleep(void)
|
||||
{
|
||||
// Request to enter STOP mode with regulator in low power mode
|
||||
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
|
||||
|
||||
HAL_InitTick(TICK_INT_PRIORITY);
|
||||
|
||||
// After wake-up from STOP reconfigure the PLL
|
||||
SetSysClock();
|
||||
|
||||
HAL_InitTick(TICK_INT_PRIORITY);
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file hal_tick.c
|
||||
* @author MCD Application Team
|
||||
* @brief Initialization of HAL tick
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#include "hal_tick.h"
|
||||
|
||||
TIM_HandleTypeDef TimMasterHandle;
|
||||
uint32_t PreviousVal = 0;
|
||||
|
||||
void us_ticker_irq_handler(void);
|
||||
|
||||
void timer_irq_handler(void) {
|
||||
// Channel 1 for mbed timeout
|
||||
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
|
||||
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
|
||||
us_ticker_irq_handler();
|
||||
}
|
||||
|
||||
// Channel 2 for HAL tick
|
||||
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
|
||||
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
|
||||
uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
|
||||
if ((val - PreviousVal) >= HAL_TICK_DELAY) {
|
||||
// Increment HAL variable
|
||||
HAL_IncTick();
|
||||
// Prepare next interrupt
|
||||
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
|
||||
PreviousVal = val;
|
||||
#if 0 // For DEBUG only
|
||||
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Reconfigure the HAL tick using a standard timer instead of systick.
|
||||
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
|
||||
// Enable timer clock
|
||||
TIM_MST_RCC;
|
||||
|
||||
// Reset timer
|
||||
TIM_MST_RESET_ON;
|
||||
TIM_MST_RESET_OFF;
|
||||
|
||||
// Configure time base
|
||||
TimMasterHandle.Instance = TIM_MST;
|
||||
TimMasterHandle.Init.Period = 0xFFFFFFFF;
|
||||
if ( SystemCoreClock == 16000000 ) {
|
||||
TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 1000000) - 1; // 1 µs tick
|
||||
} else {
|
||||
TimMasterHandle.Init.Prescaler = (uint32_t)( SystemCoreClock / 2 / 1000000) - 1; // 1 µs tick
|
||||
}
|
||||
TimMasterHandle.Init.ClockDivision = 0;
|
||||
TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
TimMasterHandle.Init.RepetitionCounter = 0;
|
||||
HAL_TIM_OC_Init(&TimMasterHandle);
|
||||
|
||||
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
|
||||
NVIC_EnableIRQ(TIM_MST_IRQ);
|
||||
|
||||
// Channel 1 for mbed timeout
|
||||
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
|
||||
|
||||
// Channel 2 for HAL tick
|
||||
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
|
||||
PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
|
||||
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
|
||||
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
|
||||
|
||||
#if 0 // For DEBUG only
|
||||
__GPIOB_CLK_ENABLE();
|
||||
GPIO_InitTypeDef GPIO_InitStruct;
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_6;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
#endif
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file hal_tick.h
|
||||
* @author MCD Application Team
|
||||
* @brief Initialization of HAL tick
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __HAL_TICK_H
|
||||
#define __HAL_TICK_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define TIM_MST TIM5
|
||||
#define TIM_MST_IRQ TIM5_IRQn
|
||||
#define TIM_MST_RCC __TIM5_CLK_ENABLE()
|
||||
|
||||
#define TIM_MST_RESET_ON __TIM5_FORCE_RESET()
|
||||
#define TIM_MST_RESET_OFF __TIM5_RELEASE_RESET()
|
||||
|
||||
#define HAL_TICK_DELAY (1000) // 1 ms
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __HAL_TICK_H
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,222 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32F4xx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __STM32F4xx_H
|
||||
#define __STM32F4xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/
|
||||
|
||||
#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
|
||||
!defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
|
||||
!defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F411xE)
|
||||
/* #define STM32F405xx */ /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
|
||||
/* #define STM32F415xx */ /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
|
||||
/* #define STM32F407xx */ /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG and STM32F407IE Devices */
|
||||
/* #define STM32F417xx */ /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
|
||||
/* #define STM32F427xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
|
||||
/* #define STM32F437xx */ /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
|
||||
/* #define STM32F429xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG,
|
||||
STM32F439NI, STM32F429IG and STM32F429II Devices */
|
||||
#define STM32F439xx /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
|
||||
STM32F439NI, STM32F439IG and STM32F439II Devices */
|
||||
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
|
||||
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
|
||||
/* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
#define USE_HAL_DRIVER
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.1.0
|
||||
*/
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F4xx_CMSIS_DEVICE_VERSION ((__STM32F4xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|(__STM32F4xx_CMSIS_DEVICE_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F4xx_CMSIS_DEVICE_VERSION))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32F405xx)
|
||||
#include "stm32f405xx.h"
|
||||
#elif defined(STM32F415xx)
|
||||
#include "stm32f415xx.h"
|
||||
#elif defined(STM32F407xx)
|
||||
#include "stm32f407xx.h"
|
||||
#elif defined(STM32F417xx)
|
||||
#include "stm32f417xx.h"
|
||||
#elif defined(STM32F427xx)
|
||||
#include "stm32f427xx.h"
|
||||
#elif defined(STM32F437xx)
|
||||
#include "stm32f437xx.h"
|
||||
#elif defined(STM32F429xx)
|
||||
#include "stm32f429xx.h"
|
||||
#elif defined(STM32F439xx)
|
||||
#include "stm32f439xx.h"
|
||||
#elif defined(STM32F401xC)
|
||||
#include "stm32f401xc.h"
|
||||
#elif defined(STM32F401xE)
|
||||
#include "stm32f401xe.h"
|
||||
#elif defined(STM32F411xE)
|
||||
#include "stm32f411xe.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ERROR = 0,
|
||||
SUCCESS = !ERROR
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32f4xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F4xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,706 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f4xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------
|
||||
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
|
||||
* | (external 8 MHz clock) | (internal 16 MHz)
|
||||
* | 2- PLL_HSE_XTAL |
|
||||
* | (external 8 MHz xtal) |
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 100 | 100
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHBCLK (MHz) | 100 | 100
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1CLK (MHz) | 50 | 50
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2CLK (MHz) | 100 | 100
|
||||
*-----------------------------------------------------------------------------
|
||||
* USB capable (48 MHz precise clock) | NO | NO
|
||||
*-----------------------------------------------------------------------------
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
#include "hal_tick.h"
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
|
||||
on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
/* #define DATA_IN_ExtSRAM */
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
/* #define DATA_IN_ExtSDRAM */
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
|
||||
#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
|
||||
#error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
|
||||
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
|
||||
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
|
||||
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 16000000;
|
||||
__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif
|
||||
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the FPU setting, vector table location and External memory
|
||||
* configuration.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
/* Configure the Cube driver */
|
||||
SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
|
||||
HAL_Init();
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings */
|
||||
SetSysClock();
|
||||
|
||||
/* Reset the timer to avoid issues after the RAM initialization */
|
||||
TIM_MST_RESET_ON;
|
||||
TIM_MST_RESET_OFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
|
||||
* depends on the application requirements), user has to ensure that HSE_VALUE
|
||||
* is same as the real frequency of the crystal used. Otherwise, this function
|
||||
* may have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock source */
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
SYSCLK = PLL_VCO / PLL_P
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||
|
||||
if (pllsource != 0)
|
||||
{
|
||||
/* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
SystemCoreClock = pllvco/pllp;
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK frequency --------------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f4xx.s before jump to main.
|
||||
* This function configures the external memories (SRAM/SDRAM)
|
||||
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
#if defined (DATA_IN_ExtSDRAM)
|
||||
register uint32_t tmpreg = 0, timeout = 0xFFFF;
|
||||
register uint32_t index;
|
||||
|
||||
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
|
||||
clock */
|
||||
RCC->AHB1ENR |= 0x000001F8;
|
||||
|
||||
/* Connect PDx pins to FMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x000000CC;
|
||||
GPIOD->AFR[1] = 0xCC000CCC;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xA02A000A;
|
||||
/* Configure PDx pins speed to 50 MHz */
|
||||
GPIOD->OSPEEDR = 0xA02A000A;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xC00000CC;
|
||||
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xAAAA800A;
|
||||
/* Configure PEx pins speed to 50 MHz */
|
||||
GPIOE->OSPEEDR = 0xAAAA800A;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FMC Alternate function */
|
||||
GPIOF->AFR[0] = 0xCCCCCCCC;
|
||||
GPIOF->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xAA800AAA;
|
||||
/* Configure PFx pins speed to 50 MHz */
|
||||
GPIOF->OSPEEDR = 0xAA800AAA;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FMC Alternate function */
|
||||
GPIOG->AFR[0] = 0xCCCCCCCC;
|
||||
GPIOG->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0xAAAAAAAA;
|
||||
/* Configure PGx pins speed to 50 MHz */
|
||||
GPIOG->OSPEEDR = 0xAAAAAAAA;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PHx pins to FMC Alternate function */
|
||||
GPIOH->AFR[0] = 0x00C0CC00;
|
||||
GPIOH->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PHx pins in Alternate function mode */
|
||||
GPIOH->MODER = 0xAAAA08A0;
|
||||
/* Configure PHx pins speed to 50 MHz */
|
||||
GPIOH->OSPEEDR = 0xAAAA08A0;
|
||||
/* Configure PHx pins Output type to push-pull */
|
||||
GPIOH->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PHx pins */
|
||||
GPIOH->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PIx pins to FMC Alternate function */
|
||||
GPIOI->AFR[0] = 0xCCCCCCCC;
|
||||
GPIOI->AFR[1] = 0x00000CC0;
|
||||
/* Configure PIx pins in Alternate function mode */
|
||||
GPIOI->MODER = 0x0028AAAA;
|
||||
/* Configure PIx pins speed to 50 MHz */
|
||||
GPIOI->OSPEEDR = 0x0028AAAA;
|
||||
/* Configure PIx pins Output type to push-pull */
|
||||
GPIOI->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PIx pins */
|
||||
GPIOI->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FMC Configuration ------------------------------------------------------*/
|
||||
/* Enable the FMC interface clock */
|
||||
RCC->AHB3ENR |= 0x00000001;
|
||||
|
||||
/* Configure and enable SDRAM bank1 */
|
||||
FMC_Bank5_6->SDCR[0] = 0x000019E0;
|
||||
FMC_Bank5_6->SDTR[0] = 0x01115351;
|
||||
|
||||
/* SDRAM initialization sequence */
|
||||
/* Clock enable command */
|
||||
FMC_Bank5_6->SDCMR = 0x00000011;
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Delay */
|
||||
for (index = 0; index<1000; index++);
|
||||
|
||||
/* PALL command */
|
||||
FMC_Bank5_6->SDCMR = 0x00000012;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Auto refresh command */
|
||||
FMC_Bank5_6->SDCMR = 0x00000073;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* MRD register program */
|
||||
FMC_Bank5_6->SDCMR = 0x00046014;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Set refresh count */
|
||||
tmpreg = FMC_Bank5_6->SDRTR;
|
||||
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
|
||||
|
||||
/* Disable write protection */
|
||||
tmpreg = FMC_Bank5_6->SDCR[0];
|
||||
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
|
||||
#endif /* DATA_IN_ExtSDRAM */
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
#if defined(DATA_IN_ExtSRAM)
|
||||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||
RCC->AHB1ENR |= 0x00000078;
|
||||
|
||||
/* Connect PDx pins to FMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x00CCC0CC;
|
||||
GPIOD->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xAAAA0A8A;
|
||||
/* Configure PDx pins speed to 100 MHz */
|
||||
GPIOD->OSPEEDR = 0xFFFF0FCF;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xC00CC0CC;
|
||||
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xAAAA828A;
|
||||
/* Configure PEx pins speed to 100 MHz */
|
||||
GPIOE->OSPEEDR = 0xFFFFC3CF;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00CCCCCC;
|
||||
GPIOF->AFR[1] = 0xCCCC0000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xAA000AAA;
|
||||
/* Configure PFx pins speed to 100 MHz */
|
||||
GPIOF->OSPEEDR = 0xFF000FFF;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00CCCCCC;
|
||||
GPIOG->AFR[1] = 0x000000C0;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x00085AAA;
|
||||
/* Configure PGx pins speed to 100 MHz */
|
||||
GPIOG->OSPEEDR = 0x000CAFFF;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FMC/FSMC Configuration --------------------------------------------------*/
|
||||
/* Enable the FMC/FSMC interface clock */
|
||||
RCC->AHB3ENR |= 0x00000001;
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FMC_Bank1->BTCR[2] = 0x00001011;
|
||||
FMC_Bank1->BTCR[3] = 0x00000201;
|
||||
FMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FSMC_Bank1->BTCR[2] = 0x00001011;
|
||||
FSMC_Bank1->BTCR[3] = 0x00000201;
|
||||
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
|
||||
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SetSysClock(void)
|
||||
{
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
#if USE_PLL_HSE_EXTC != 0
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
#if USE_PLL_HSE_XTAL != 0
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 3- If fail start with HSI clock */
|
||||
if (SetSysClock_PLL_HSI() == 0)
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
// [TODO] Put something here to tell the user that a problem occured...
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Output clock on MCO2 pin(PC9) for debugging purpose */
|
||||
//HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
|
||||
}
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
|
||||
/* The voltage scaling allows optimizing the power consumption when the device is
|
||||
clocked below the maximum system frequency, to update the voltage scaling value
|
||||
regarding system frequency refer to product datasheet. */
|
||||
__PWR_CLK_ENABLE();
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
|
||||
|
||||
/* Enable HSE oscillator and activate PLL with HSE as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
if (bypass == 0)
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
|
||||
}
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
//RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
|
||||
//RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
|
||||
RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
|
||||
RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
/* Output clock on MCO1 pin(PA8) for debugging purpose */
|
||||
|
||||
//if (bypass == 0)
|
||||
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
|
||||
//else
|
||||
// HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct;
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct;
|
||||
|
||||
/* The voltage scaling allows optimizing the power consumption when the device is
|
||||
clocked below the maximum system frequency, to update the voltage scaling value
|
||||
regarding system frequency refer to product datasheet. */
|
||||
__PWR_CLK_ENABLE();
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
|
||||
|
||||
/* Enable HSI oscillator and activate PLL with HSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSICalibrationValue = 16;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
||||
//RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
|
||||
//RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
|
||||
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
|
||||
RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
/* Output clock on MCO1 pin(PA8) for debugging purpose */
|
||||
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-June-2014
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F4XX_H
|
||||
#define __SYSTEM_STM32F4XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
/* This variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
extern void SetSysClock(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F4XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
|
|||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
|
|||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ uint32_t gpio_set(PinName pin) {
|
|||
}
|
||||
|
||||
void gpio_init(gpio_t *obj, PinName pin) {
|
||||
obj->pinName = pin;
|
||||
obj->pin = pin;
|
||||
if (pin == (PinName)NC)
|
||||
return;
|
||||
|
||||
|
|
@ -42,14 +42,14 @@ void gpio_init(gpio_t *obj, PinName pin) {
|
|||
}
|
||||
|
||||
void gpio_mode(gpio_t *obj, PinMode mode) {
|
||||
pin_mode(obj->pinName, mode);
|
||||
pin_mode(obj->pin, mode);
|
||||
}
|
||||
|
||||
void gpio_dir(gpio_t *obj, PinDirection direction) {
|
||||
MBED_ASSERT(obj->pinName != (PinName)NC);
|
||||
uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
|
||||
MBED_ASSERT(obj->pin != (PinName)NC);
|
||||
uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
|
||||
uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
|
||||
uint32_t pin_num = obj->pinName & 0xFF;
|
||||
uint32_t pin_num = obj->pin & 0xFF;
|
||||
|
||||
switch (direction) {
|
||||
case PIN_INPUT:
|
||||
|
|
|
|||
|
|
@ -25,27 +25,31 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
typedef struct {
|
||||
PinName pinName;
|
||||
PinName pin;
|
||||
} gpio_t;
|
||||
|
||||
static inline void gpio_write(gpio_t *obj, int value) {
|
||||
MBED_ASSERT(obj->pinName != (PinName)NC);
|
||||
uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
|
||||
uint32_t pin = obj->pinName & 0xFF;
|
||||
MBED_ASSERT(obj->pin != (PinName)NC);
|
||||
uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
|
||||
uint32_t pin = obj->pin & 0xFF;
|
||||
uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
|
||||
|
||||
GPIO_HAL_WritePinOutput(gpio_addrs[port], pin, value);
|
||||
}
|
||||
|
||||
static inline int gpio_read(gpio_t *obj) {
|
||||
MBED_ASSERT(obj->pinName != (PinName)NC);
|
||||
uint32_t port = obj->pinName >> GPIO_PORT_SHIFT;
|
||||
uint32_t pin = obj->pinName & 0xFF;
|
||||
MBED_ASSERT(obj->pin != (PinName)NC);
|
||||
uint32_t port = obj->pin >> GPIO_PORT_SHIFT;
|
||||
uint32_t pin = obj->pin & 0xFF;
|
||||
uint32_t gpio_addrs[] = GPIO_BASE_ADDRS;
|
||||
|
||||
return (int)GPIO_HAL_ReadPinInput(gpio_addrs[port], pin);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,125 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2015 Nordic Semiconductor
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 3
|
||||
|
||||
typedef enum {
|
||||
NC = (int)0xFFFFFFFF,
|
||||
p0 = 0,
|
||||
p1 = 1,
|
||||
p2 = 2,
|
||||
p3 = 3,
|
||||
p4 = 4,
|
||||
p5 = 5,
|
||||
p6 = 6,
|
||||
p7 = 7,
|
||||
p8 = NC,
|
||||
p9 = NC,
|
||||
p10 = NC,
|
||||
p11 = NC,
|
||||
p12 = NC,
|
||||
p13 = 13,
|
||||
p14 = NC,
|
||||
p15 = NC,
|
||||
p16 = 16,
|
||||
p17 = 17,
|
||||
p18 = NC,
|
||||
p19 = 19,
|
||||
p20 = 20,
|
||||
p21 = 21,
|
||||
p22 = 22,
|
||||
p23 = 23,
|
||||
p24 = 24,
|
||||
p25 = 25,
|
||||
p26 = 26,
|
||||
p27 = 27,
|
||||
p28 = NC,
|
||||
p29 = 29,
|
||||
p30 = 30,
|
||||
p31 = 31,
|
||||
|
||||
LED1 = p7,
|
||||
LED2 = p13,
|
||||
|
||||
BUTTON0 = p16,
|
||||
BUTTON1 = p17,
|
||||
|
||||
RX_PIN_NUMBER = p23,
|
||||
TX_PIN_NUMBER = p25,
|
||||
|
||||
// mBed interface Pins
|
||||
USBTX = TX_PIN_NUMBER,
|
||||
USBRX = RX_PIN_NUMBER,
|
||||
|
||||
SPI_PSELMOSI0 = p24,
|
||||
SPI_PSELMISO0 = p29,
|
||||
SPI_PSELSS0 = p6,
|
||||
SPI_PSELSCK0 = p21,
|
||||
|
||||
SPIS_PSELMOSI = p24,
|
||||
SPIS_PSELMISO = p29,
|
||||
SPIS_PSELSS = p6,
|
||||
SPIS_PSELSCK = p21,
|
||||
|
||||
I2C_SDA0 = p22,
|
||||
I2C_SCL0 = p20,
|
||||
|
||||
A0 = p0,
|
||||
A1 = p1,
|
||||
A2 = p2,
|
||||
A3 = p3,
|
||||
A4 = p4,
|
||||
A5 = p5,
|
||||
|
||||
SWIO = p19,
|
||||
VERF0 = p0,
|
||||
// Not connected
|
||||
|
||||
CTS_PIN_NUMBER = NC,
|
||||
RTS_PIN_NUMBER = NC,
|
||||
SPI_PSELMOSI1 = NC,
|
||||
SPI_PSELMISO1 = NC,
|
||||
SPI_PSELSS1 = NC,
|
||||
SPI_PSELSCK1 = NC,
|
||||
LED3 = NC,
|
||||
LED4 = NC
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 1,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_PORTIN 1
|
||||
#define DEVICE_PORTOUT 1
|
||||
#define DEVICE_PORTINOUT 1
|
||||
|
||||
#define DEVICE_INTERRUPTIN 1
|
||||
|
||||
#define DEVICE_ANALOGIN 1
|
||||
#define DEVICE_ANALOGOUT 0
|
||||
|
||||
#define DEVICE_SERIAL 1
|
||||
|
||||
#define DEVICE_I2C 1
|
||||
#define DEVICE_I2CSLAVE 0
|
||||
|
||||
#define DEVICE_SPI 1
|
||||
#define DEVICE_SPISLAVE 1
|
||||
|
||||
#define DEVICE_CAN 0
|
||||
|
||||
#define DEVICE_RTC 0
|
||||
|
||||
#define DEVICE_ETHERNET 0
|
||||
|
||||
#define DEVICE_PWMOUT 1
|
||||
|
||||
#define DEVICE_SEMIHOST 0
|
||||
#define DEVICE_LOCALFILESYSTEM 0
|
||||
|
||||
#define DEVICE_SLEEP 1
|
||||
|
||||
#define DEVICE_DEBUG_AWARENESS 1
|
||||
|
||||
#define DEVICE_STDIO_MESSAGES 0
|
||||
|
||||
#define DEVICE_ERROR_PATTERN 1
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
void mbed_sdk_init()
|
||||
{
|
||||
// Default SWIO setting, pull SWIO(p19) to low for turning antenna switch to BLE radiated path
|
||||
NRF_GPIO->PIN_CNF[19] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
|
||||
| (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
|
||||
| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
|
||||
| (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
|
||||
| (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
|
||||
|
||||
NRF_GPIO->OUTCLR = (GPIO_OUTCLR_PIN19_Clear << GPIO_OUTCLR_PIN19_Pos);
|
||||
|
||||
// Config External Crystal to 32MHz
|
||||
NRF_CLOCK->XTALFREQ = 0x00;
|
||||
NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
|
||||
NRF_CLOCK->TASKS_HFCLKSTART = 1;
|
||||
while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0)
|
||||
{// Do nothing.
|
||||
}
|
||||
}
|
||||
|
|
@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
|
|||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
0
libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c
Executable file → Normal file
0
libraries/mbed/targets/hal/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c
Executable file → Normal file
|
|
@ -29,8 +29,7 @@ void us_ticker_init(void)
|
|||
return;
|
||||
}
|
||||
|
||||
APP_TIMER_INIT(0 /*CFG_TIMER_PRESCALER*/ , 1 /*CFG_TIMER_MAX_INSTANCE*/, 1 /*CFG_TIMER_OPERATION_QUEUE_SIZE*/, false /*CFG_SCHEDULER_ENABLE*/);
|
||||
|
||||
APP_TIMER_INIT(0 /*CFG_TIMER_PRESCALER*/ , 1 /*CFG_TIMER_MAX_INSTANCE*/, 1 /*CFG_TIMER_OPERATION_QUEUE_SIZE*/, false /*CFG_SCHEDULER_ENABLE*/);
|
||||
us_ticker_inited = true;
|
||||
}
|
||||
|
||||
|
|
@ -40,7 +39,7 @@ uint32_t us_ticker_read()
|
|||
us_ticker_init();
|
||||
}
|
||||
|
||||
timestamp_t value;
|
||||
uint64_t value;
|
||||
app_timer_cnt_get(&value); /* This returns the RTC counter (which is fed by the 32khz crystal clock source) */
|
||||
return ((value * 1000000) / (uint32_t)APP_TIMER_CLOCK_FREQ); /* Return a pseudo microsecond counter value.
|
||||
* This is only as precise as the 32khz low-freq
|
||||
|
|
@ -72,7 +71,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
|
|||
return;
|
||||
}
|
||||
|
||||
timestamp_t currentCounter64;
|
||||
uint64_t currentCounter64;
|
||||
app_timer_cnt_get(¤tCounter64);
|
||||
uint32_t currentCounter = currentCounter64 & MAX_RTC_COUNTER_VAL;
|
||||
uint32_t targetCounter = ((uint32_t)((timestamp * (uint64_t)APP_TIMER_CLOCK_FREQ) / 1000000) + 1) & MAX_RTC_COUNTER_VAL;
|
||||
|
|
@ -94,13 +93,17 @@ void us_ticker_set_interrupt(timestamp_t timestamp)
|
|||
void us_ticker_disable_interrupt(void)
|
||||
{
|
||||
if (us_ticker_appTimerRunning) {
|
||||
app_timer_stop(us_ticker_appTimerID);
|
||||
if (app_timer_stop(us_ticker_appTimerID) == NRF_SUCCESS) {
|
||||
us_ticker_appTimerRunning = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void us_ticker_clear_interrupt(void)
|
||||
{
|
||||
if (us_ticker_appTimerRunning) {
|
||||
app_timer_stop(us_ticker_appTimerID);
|
||||
if (app_timer_stop(us_ticker_appTimerID) == NRF_SUCCESS) {
|
||||
us_ticker_appTimerRunning = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
|
|||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,71 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
UART_0 = (int)LPC_USART_BASE
|
||||
} UARTName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = (int)LPC_I2C_BASE
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
ADC0_0 = 0,
|
||||
ADC0_1,
|
||||
ADC0_2,
|
||||
ADC0_3,
|
||||
ADC0_4,
|
||||
ADC0_5,
|
||||
ADC0_6,
|
||||
ADC0_7
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = (int)LPC_SSP0_BASE,
|
||||
SPI_1 = (int)LPC_SSP1_BASE
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
PWM_1 = 0,
|
||||
PWM_2,
|
||||
PWM_3,
|
||||
PWM_4,
|
||||
PWM_5,
|
||||
PWM_6,
|
||||
PWM_7,
|
||||
PWM_8,
|
||||
PWM_9,
|
||||
PWM_10,
|
||||
PWM_11
|
||||
} PWMName;
|
||||
|
||||
#define STDIO_UART_TX UART_TX
|
||||
#define STDIO_UART_RX UART_RX
|
||||
#define STDIO_UART UART_0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
/************ADC***************/
|
||||
const PinMap PinMap_ADC[] = {
|
||||
{P0_11, ADC0_0, 0x02},
|
||||
{P0_12, ADC0_1, 0x02},
|
||||
{P0_13, ADC0_2, 0x02},
|
||||
{P0_14, ADC0_3, 0x02},
|
||||
{P0_15, ADC0_4, 0x02},
|
||||
{P0_16, ADC0_5, 0x01},
|
||||
{P0_22, ADC0_6, 0x01},
|
||||
{P0_23, ADC0_7, 0x01},
|
||||
{NC , NC , 0 }
|
||||
};
|
||||
|
||||
/************I2C***************/
|
||||
const PinMap PinMap_I2C_SDA[] = {
|
||||
{P0_5, I2C_0, 1},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_I2C_SCL[] = {
|
||||
{P0_4, I2C_0, 1},
|
||||
{NC , NC, 0}
|
||||
};
|
||||
|
||||
/************UART***************/
|
||||
const PinMap PinMap_UART_TX[] = {
|
||||
{P0_19, UART_0, 1},
|
||||
{P1_13, UART_0, 3},
|
||||
{P1_27, UART_0, 2},
|
||||
{ NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
{P0_18, UART_0, 1},
|
||||
{P1_14, UART_0, 3},
|
||||
{P1_26, UART_0, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************SPI***************/
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
{P0_6 , SPI_0, 0x02},
|
||||
{P0_10, SPI_0, 0x02},
|
||||
{P1_29, SPI_0, 0x01},
|
||||
{P1_15, SPI_1, 0x03},
|
||||
{P1_20, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{P0_9 , SPI_0, 0x01},
|
||||
{P0_21, SPI_1, 0x02},
|
||||
{P1_22, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{P0_8 , SPI_0, 0x01},
|
||||
{P0_22, SPI_1, 0x03},
|
||||
{P1_21, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
{P0_2 , SPI_0, 0x01},
|
||||
{P1_19, SPI_1, 0x02},
|
||||
{P1_23, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************PWM***************/
|
||||
/* To have a PWM where we can change both the period and the duty cycle,
|
||||
* we need an entire timer. With the following conventions:
|
||||
* * MR3 is used for the PWM period
|
||||
* * MR0, MR1, MR2 are used for the duty cycle
|
||||
*/
|
||||
const PinMap PinMap_PWM[] = {
|
||||
/* CT16B0 */
|
||||
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
|
||||
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
|
||||
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
|
||||
|
||||
/* CT16B1 */
|
||||
{P0_21, PWM_4, 1}, /* MR0 */
|
||||
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
|
||||
|
||||
/* CT32B0 */
|
||||
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
|
||||
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
|
||||
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
|
||||
|
||||
/* CT32B1 */
|
||||
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
|
||||
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
|
||||
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
|
||||
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 5
|
||||
|
||||
typedef enum {
|
||||
// LPC11U Pin Names
|
||||
P0_0 = 0,
|
||||
P0_1 = 1,
|
||||
P0_2 = 2,
|
||||
P0_3 = 3,
|
||||
P0_4 = 4,
|
||||
P0_5 = 5,
|
||||
P0_6 = 6,
|
||||
P0_7 = 7,
|
||||
P0_8 = 8,
|
||||
P0_9 = 9,
|
||||
P0_10 = 10,
|
||||
P0_11 = 11,
|
||||
P0_12 = 12,
|
||||
P0_13 = 13,
|
||||
P0_14 = 14,
|
||||
P0_15 = 15,
|
||||
P0_16 = 16,
|
||||
P0_17 = 17,
|
||||
P0_18 = 18,
|
||||
P0_19 = 19,
|
||||
P0_20 = 20,
|
||||
P0_21 = 21,
|
||||
P0_22 = 22,
|
||||
P0_23 = 23,
|
||||
P0_24 = 24,
|
||||
P0_25 = 25,
|
||||
P0_26 = 26,
|
||||
P0_27 = 27,
|
||||
|
||||
P1_0 = 32,
|
||||
P1_1 = 33,
|
||||
P1_2 = 34,
|
||||
P1_3 = 35,
|
||||
P1_4 = 36,
|
||||
P1_5 = 37,
|
||||
P1_6 = 38,
|
||||
P1_7 = 39,
|
||||
P1_8 = 40,
|
||||
P1_9 = 41,
|
||||
P1_10 = 42,
|
||||
P1_11 = 43,
|
||||
P1_12 = 44,
|
||||
P1_13 = 45,
|
||||
P1_14 = 46,
|
||||
P1_15 = 47,
|
||||
P1_16 = 48,
|
||||
P1_17 = 49,
|
||||
P1_18 = 50,
|
||||
P1_19 = 51,
|
||||
P1_20 = 52,
|
||||
P1_21 = 53,
|
||||
P1_22 = 54,
|
||||
P1_23 = 55,
|
||||
P1_24 = 56,
|
||||
P1_25 = 57,
|
||||
P1_26 = 58,
|
||||
P1_27 = 59,
|
||||
P1_28 = 60,
|
||||
P1_29 = 61,
|
||||
|
||||
P1_31 = 63,
|
||||
|
||||
// MicroNFCBoard pin names
|
||||
M_RST = P0_0,
|
||||
M_BOOT = P0_1,
|
||||
M_RXD = P0_18,
|
||||
M_TXD = P0_19,
|
||||
M_SCL = P0_4,
|
||||
M_SDA = P0_5,
|
||||
M_D0 = P0_20,
|
||||
|
||||
M_A0 = P0_16,
|
||||
M_A1 = P0_15,
|
||||
M_A2 = P0_14,
|
||||
M_A3 = P0_13,
|
||||
M_SCK = P0_10,
|
||||
M_MOSI = P0_9,
|
||||
M_MISO = P0_8,
|
||||
M_NCS = P0_2,
|
||||
M_IRQ = P0_7,
|
||||
|
||||
// MicroNFCBoard pin numbers
|
||||
p4 = M_RST,
|
||||
p5 = M_BOOT,
|
||||
p6 = M_RXD,
|
||||
p7 = M_TXD,
|
||||
p8 = M_SCL,
|
||||
p9 = M_SDA,
|
||||
p10 = M_D0,
|
||||
|
||||
p11 = M_IRQ,
|
||||
p12 = M_NCS,
|
||||
p13 = M_MISO,
|
||||
p14 = M_MOSI,
|
||||
p15 = M_SCK,
|
||||
p16 = M_A3,
|
||||
p17 = M_A2,
|
||||
p18 = M_A1,
|
||||
p19 = M_A0,
|
||||
|
||||
// Other Pin Names
|
||||
LED1 = P0_11,
|
||||
LED2 = P0_12,
|
||||
|
||||
// Alias to have correct blue lights of death pattern
|
||||
LED3 = LED2,
|
||||
LED4 = LED1,
|
||||
|
||||
UART_TX = M_TXD,
|
||||
UART_RX = M_RXD,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF,
|
||||
|
||||
// Standard but not supported pins
|
||||
USBTX = NC,
|
||||
USBRX = NC,
|
||||
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
CHANNEL0 = FLEX_INT0_IRQn,
|
||||
CHANNEL1 = FLEX_INT1_IRQn,
|
||||
CHANNEL2 = FLEX_INT2_IRQn,
|
||||
CHANNEL3 = FLEX_INT3_IRQn,
|
||||
CHANNEL4 = FLEX_INT4_IRQn,
|
||||
CHANNEL5 = FLEX_INT5_IRQn,
|
||||
CHANNEL6 = FLEX_INT6_IRQn,
|
||||
CHANNEL7 = FLEX_INT7_IRQn
|
||||
} Channel;
|
||||
|
||||
typedef enum {
|
||||
PullUp = 2,
|
||||
PullDown = 1,
|
||||
PullNone = 0,
|
||||
Repeater = 3,
|
||||
OpenDrain = 4,
|
||||
PullDefault = PullDown
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_PORTIN 1
|
||||
#define DEVICE_PORTOUT 1
|
||||
#define DEVICE_PORTINOUT 1
|
||||
|
||||
#define DEVICE_INTERRUPTIN 1
|
||||
|
||||
#define DEVICE_ANALOGIN 1
|
||||
#define DEVICE_ANALOGOUT 0
|
||||
|
||||
#define DEVICE_SERIAL 1
|
||||
|
||||
#define DEVICE_I2C 1
|
||||
#define DEVICE_I2CSLAVE 1
|
||||
|
||||
#define DEVICE_SPI 1
|
||||
#define DEVICE_SPISLAVE 1
|
||||
|
||||
#define DEVICE_CAN 0
|
||||
|
||||
#define DEVICE_RTC 0
|
||||
|
||||
#define DEVICE_ETHERNET 0
|
||||
|
||||
#define DEVICE_PWMOUT 1
|
||||
|
||||
#define DEVICE_SEMIHOST 0
|
||||
#define DEVICE_LOCALFILESYSTEM 0
|
||||
#define DEVICE_ID_LENGTH 32
|
||||
#define DEVICE_MAC_OFFSET 20
|
||||
|
||||
#define DEVICE_SLEEP 1
|
||||
|
||||
#define DEVICE_DEBUG_AWARENESS 0
|
||||
|
||||
#define DEVICE_STDIO_MESSAGES 0
|
||||
|
||||
#define DEVICE_ERROR_PATTERN 1
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
UART_0 = (int)LPC_USART_BASE
|
||||
} UARTName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = (int)LPC_I2C_BASE
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
ADC0_0 = 0,
|
||||
ADC0_1,
|
||||
ADC0_2,
|
||||
ADC0_3,
|
||||
ADC0_4,
|
||||
ADC0_5,
|
||||
ADC0_6,
|
||||
ADC0_7
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = (int)LPC_SSP0_BASE,
|
||||
SPI_1 = (int)LPC_SSP1_BASE
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
PWM_1 = 0,
|
||||
PWM_2,
|
||||
PWM_3,
|
||||
PWM_4,
|
||||
PWM_5,
|
||||
PWM_6,
|
||||
PWM_7,
|
||||
PWM_8,
|
||||
PWM_9,
|
||||
PWM_10,
|
||||
PWM_11
|
||||
} PWMName;
|
||||
|
||||
#define STDIO_UART_TX UART_TX
|
||||
#define STDIO_UART_RX UART_RX
|
||||
#define STDIO_UART UART_0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
|
||||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
/************ADC***************/
|
||||
const PinMap PinMap_ADC[] = {
|
||||
{P0_11, ADC0_0, 0x02},
|
||||
{P0_12, ADC0_1, 0x02},
|
||||
{P0_13, ADC0_2, 0x02},
|
||||
{P0_14, ADC0_3, 0x02},
|
||||
{P0_15, ADC0_4, 0x02},
|
||||
{P0_16, ADC0_5, 0x01},
|
||||
{P0_22, ADC0_6, 0x01},
|
||||
{P0_23, ADC0_7, 0x01},
|
||||
{NC , NC , 0 }
|
||||
};
|
||||
|
||||
/************I2C***************/
|
||||
const PinMap PinMap_I2C_SDA[] = {
|
||||
{P0_5, I2C_0, 1},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_I2C_SCL[] = {
|
||||
{P0_4, I2C_0, 1},
|
||||
{NC , NC, 0}
|
||||
};
|
||||
|
||||
/************UART***************/
|
||||
const PinMap PinMap_UART_TX[] = {
|
||||
{P0_19, UART_0, 1},
|
||||
{P1_13, UART_0, 3},
|
||||
{P1_27, UART_0, 2},
|
||||
{ NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
{P0_18, UART_0, 1},
|
||||
{P1_14, UART_0, 3},
|
||||
{P1_26, UART_0, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************SPI***************/
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
{P0_6 , SPI_0, 0x02},
|
||||
{P0_10, SPI_0, 0x02},
|
||||
{P1_29, SPI_0, 0x01},
|
||||
{P1_15, SPI_1, 0x03},
|
||||
{P1_20, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{P0_9 , SPI_0, 0x01},
|
||||
{P0_21, SPI_1, 0x02},
|
||||
{P1_22, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{P0_8 , SPI_0, 0x01},
|
||||
{P0_22, SPI_1, 0x03},
|
||||
{P1_21, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
{P0_2 , SPI_0, 0x01},
|
||||
{P1_19, SPI_1, 0x02},
|
||||
{P1_23, SPI_1, 0x02},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************PWM***************/
|
||||
/* To have a PWM where we can change both the period and the duty cycle,
|
||||
* we need an entire timer. With the following conventions:
|
||||
* * MR3 is used for the PWM period
|
||||
* * MR0, MR1, MR2 are used for the duty cycle
|
||||
*/
|
||||
const PinMap PinMap_PWM[] = {
|
||||
/* CT16B0 */
|
||||
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
|
||||
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
|
||||
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
|
||||
|
||||
/* CT16B1 */
|
||||
{P0_21, PWM_4, 1}, /* MR0 */
|
||||
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
|
||||
|
||||
/* CT32B0 */
|
||||
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
|
||||
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
|
||||
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
|
||||
|
||||
/* CT32B1 */
|
||||
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
|
||||
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
|
||||
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
|
||||
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 5
|
||||
|
||||
typedef enum {
|
||||
// LPC11U Pin Names
|
||||
P0_0 = 0,
|
||||
P0_1 = 1,
|
||||
P0_2 = 2,
|
||||
P0_3 = 3,
|
||||
P0_4 = 4,
|
||||
P0_5 = 5,
|
||||
P0_6 = 6,
|
||||
P0_7 = 7,
|
||||
P0_8 = 8,
|
||||
P0_9 = 9,
|
||||
P0_10 = 10,
|
||||
P0_11 = 11,
|
||||
P0_12 = 12,
|
||||
P0_13 = 13,
|
||||
P0_14 = 14,
|
||||
P0_15 = 15,
|
||||
P0_16 = 16,
|
||||
P0_17 = 17,
|
||||
P0_18 = 18,
|
||||
P0_19 = 19,
|
||||
P0_20 = 20,
|
||||
P0_21 = 21,
|
||||
P0_22 = 22,
|
||||
P0_23 = 23,
|
||||
P0_24 = 24,
|
||||
P0_25 = 25,
|
||||
P0_26 = 26,
|
||||
P0_27 = 27,
|
||||
|
||||
P1_0 = 32,
|
||||
P1_1 = 33,
|
||||
P1_2 = 34,
|
||||
P1_3 = 35,
|
||||
P1_4 = 36,
|
||||
P1_5 = 37,
|
||||
P1_6 = 38,
|
||||
P1_7 = 39,
|
||||
P1_8 = 40,
|
||||
P1_9 = 41,
|
||||
P1_10 = 42,
|
||||
P1_11 = 43,
|
||||
P1_12 = 44,
|
||||
P1_13 = 45,
|
||||
P1_14 = 46,
|
||||
P1_15 = 47,
|
||||
P1_16 = 48,
|
||||
P1_17 = 49,
|
||||
P1_18 = 50,
|
||||
P1_19 = 51,
|
||||
P1_20 = 52,
|
||||
P1_21 = 53,
|
||||
P1_22 = 54,
|
||||
P1_23 = 55,
|
||||
P1_24 = 56,
|
||||
P1_25 = 57,
|
||||
P1_26 = 58,
|
||||
P1_27 = 59,
|
||||
P1_28 = 60,
|
||||
P1_29 = 61,
|
||||
|
||||
P1_31 = 63,
|
||||
|
||||
// Other mbed Pin Names
|
||||
LED1 = P0_7,
|
||||
LED2 = P0_7,
|
||||
LED3 = P0_7,
|
||||
LED4 = P0_7,
|
||||
|
||||
UART_TX = P0_19,
|
||||
UART_RX = P0_18,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF,
|
||||
|
||||
// Standard but not supported pins
|
||||
USBTX = NC,
|
||||
USBRX = NC,
|
||||
|
||||
} PinName;
|
||||
|
||||
typedef enum {
|
||||
CHANNEL0 = FLEX_INT0_IRQn,
|
||||
CHANNEL1 = FLEX_INT1_IRQn,
|
||||
CHANNEL2 = FLEX_INT2_IRQn,
|
||||
CHANNEL3 = FLEX_INT3_IRQn,
|
||||
CHANNEL4 = FLEX_INT4_IRQn,
|
||||
CHANNEL5 = FLEX_INT5_IRQn,
|
||||
CHANNEL6 = FLEX_INT6_IRQn,
|
||||
CHANNEL7 = FLEX_INT7_IRQn
|
||||
} Channel;
|
||||
|
||||
typedef enum {
|
||||
PullUp = 2,
|
||||
PullDown = 1,
|
||||
PullNone = 0,
|
||||
Repeater = 3,
|
||||
OpenDrain = 4,
|
||||
PullDefault = PullDown
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2015 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_PORTIN 1
|
||||
#define DEVICE_PORTOUT 1
|
||||
#define DEVICE_PORTINOUT 1
|
||||
|
||||
#define DEVICE_INTERRUPTIN 1
|
||||
|
||||
#define DEVICE_ANALOGIN 1
|
||||
#define DEVICE_ANALOGOUT 0
|
||||
|
||||
#define DEVICE_SERIAL 1
|
||||
|
||||
#define DEVICE_I2C 1
|
||||
#define DEVICE_I2CSLAVE 1
|
||||
|
||||
#define DEVICE_SPI 1
|
||||
#define DEVICE_SPISLAVE 1
|
||||
|
||||
#define DEVICE_CAN 0
|
||||
|
||||
#define DEVICE_RTC 0
|
||||
|
||||
#define DEVICE_ETHERNET 0
|
||||
|
||||
#define DEVICE_PWMOUT 1
|
||||
|
||||
#define DEVICE_SEMIHOST 0
|
||||
#define DEVICE_LOCALFILESYSTEM 0
|
||||
#define DEVICE_ID_LENGTH 32
|
||||
#define DEVICE_MAC_OFFSET 20
|
||||
|
||||
#define DEVICE_SLEEP 1
|
||||
|
||||
#define DEVICE_DEBUG_AWARENESS 0
|
||||
|
||||
#define DEVICE_STDIO_MESSAGES 0
|
||||
|
||||
#define DEVICE_ERROR_PATTERN 1
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
|
|||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -43,6 +43,10 @@ static inline int gpio_read(gpio_t *obj) {
|
|||
return ((*obj->reg_mask_read) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
|
|||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -46,6 +46,10 @@ static inline int gpio_read(gpio_t *obj) {
|
|||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
|
|||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@ static inline int gpio_read(gpio_t *obj) {
|
|||
return ((*obj->reg_in & obj->mask) ? 1 : 0);
|
||||
}
|
||||
|
||||
static inline int gpio_is_connected(const gpio_t *obj) {
|
||||
return obj->pin != (PinName)NC;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue