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Merge pull request #12810 from MarceloSalazar/platform_cleanup 

Remove unsupported targets

Note, commit 21e364e is just a styling fix, no target removal.
pull/12846/head
Martin Kojtal 2020-04-22 10:58:50 +02:00 committed by GitHub
parent 8de5c32d9e 1a345cec66
commit b622a25688
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
346 changed files with 4 additions and 101392 deletions
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16
TESTS/integration/COMMON/target_extended.json
View File

@ -197,13 +197,6 @@
"nanostack.configuration" : "thread_router",
"nanostack-hal.event_loop_thread_stack_size": 8192
},
"MTB_USI_WM_BN_BM_22": {
"target.components_add" : ["SPIF"],
"spif-driver.SPI_MOSI" : "PC_3",
"spif-driver.SPI_MISO" : "PC_2",
"spif-driver.SPI_CLK" : "PB_13",
"spif-driver.SPI_CS" : "PA_6"
},
"MTB_ADV_WISE_1570": {
"target.components_add" : ["SPIF"],
"spif-driver.SPI_FREQ" : 20000000,
@ -214,15 +207,6 @@
"platform.default-serial-baud-rate" : 115200,
"nsapi.dns-response-wait-time" : 30000
},
"MTB_ADV_WISE_1530": {
"target.components_add" : ["SPIF"],
"spif-driver.SPI_MOSI" : "PC_3",
"spif-driver.SPI_MISO" : "PC_2",
"spif-driver.SPI_CLK" : "PB_13",
"spif-driver.SPI_CS" : "PC_12",
"no_led" : "1",
"tests-fs-size" : "2*1024*1024"
},
"MCU_PSOC6": {
"tests-fs-size" : "8*1024*1024"
},

66
TESTS/lorawan/loraradio/template_mbed_app.txt
View File

@ -69,28 +69,6 @@
"lora-tcxo": "PA_12"
},
"MTB_MURATA_ABZ": {
"lora-radio": "SX1276",
"lora-spi-mosi": "PA_7",
"lora-spi-miso": "PA_6",
"lora-spi-sclk": "PB_3",
"lora-cs": "PA_15",
"lora-reset": "PC_0",
"lora-dio0": "PB_4",
"lora-dio1": "PB_1",
"lora-dio2": "PB_0",
"lora-dio3": "PC_13",
"lora-dio4": "NC",
"lora-dio5": "NC",
"lora-rf-switch-ctl1": "NC",
"lora-rf-switch-ctl2": "NC",
"lora-txctl": "PC_2",
"lora-rxctl": "PA_1",
"lora-ant-switch": "NC",
"lora-pwr-amp-ctl": "PC_1",
"lora-tcxo": "PA_12"
},
"XDOT_L151CC": {
"lora-radio": "SX1272",
"lora-spi-mosi": "LORA_MOSI",
@ -113,28 +91,6 @@
"lora-tcxo": "NC"
},
"MTB_MTS_XDOT": {
"lora-radio": "SX1272",
"lora-spi-mosi": "LORA_MOSI",
"lora-spi-miso": "LORA_MISO",
"lora-spi-sclk": "LORA_SCK",
"lora-cs": "LORA_NSS",
"lora-reset": "LORA_RESET",
"lora-dio0": "LORA_DIO0",
"lora-dio1": "LORA_DIO1",
"lora-dio2": "LORA_DIO2",
"lora-dio3": "LORA_DIO3",
"lora-dio4": "LORA_DIO4",
"lora-dio5": "NC",
"lora-rf-switch-ctl1": "NC",
"lora-rf-switch-ctl2": "NC",
"lora-txctl": "NC",
"lora-rxctl": "NC",
"lora-ant-switch": "NC",
"lora-pwr-amp-ctl": "NC",
"lora-tcxo": "NC"
},
"LTEK_FF1705": {
"lora-radio": "SX1272",
"lora-spi-mosi": "LORA_MOSI",
@ -199,28 +155,6 @@
"lora-ant-switch": "ANT_SWITCH",
"lora-pwr-amp-ctl": "NC",
"lora-tcxo": "NC"
},
"MTB_RAK811": {
"lora-radio": "SX1276",
"lora-spi-mosi": "SPI_RF_MOSI",
"lora-spi-miso": "SPI_RF_MISO",
"lora-spi-sclk": "SPI_RF_SCK",
"lora-cs": "SPI_RF_CS",
"lora-reset": "SPI_RF_RESET",
"lora-dio0": "DIO0",
"lora-dio1": "DIO1",
"lora-dio2": "DIO2",
"lora-dio3": "DIO3",
"lora-dio4": "DIO4",
"lora-dio5": "NC",
"lora-rf-switch-ctl1": "NC",
"lora-rf-switch-ctl2": "NC",
"lora-txctl": "ANT_CTX_PA",
"lora-rxctl": "ANT_CRX_RX",
"lora-ant-switch": "NC",
"lora-pwr-amp-ctl": "NC",
"lora-tcxo": "RF_TCXO_EN"
}
}
}

8
TESTS/network/emac/main.cpp
View File

@ -32,14 +32,6 @@
#error [NOT_SUPPORTED] Either wifi or ethernet testing need to be enabled
#else
#if (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI) && \
!defined(TARGET_MTB_ADV_WISE_1530) && \
!defined(TARGET_MTB_USI_WM_BN_BM_22) && \
!defined(TARGET_WIO_EMW3166)
#error [NOT_SUPPORTED] Wifi tests are not valid for the target
#else
#include "greentea-client/test_env.h"
#include "unity.h"

6
TESTS/network/emac/mbed_lib.json
View File

@ -7,12 +7,6 @@
"target_overrides": {
"WIO_EMW3166": {
"NO_SUPPORT_FOR_IPV4_MULTICAST_FILTER": true
},
"MTB_ADV_WISE_1530": {
"NO_SUPPORT_FOR_IPV4_MULTICAST_FILTER": true
},
"MTB_USI_WM_BN_BM_22": {
"NO_SUPPORT_FOR_IPV4_MULTICAST_FILTER": true
}
}
}

5
components/802.15.4_RF/stm-s2lp-rf-driver/mbed_lib.json
View File

@ -4,11 +4,6 @@
"provide-default": {
"help": "Provide default NanostackRfpy. [true/false]",
"value": false
},
"target_overrides": {
"MTB_STM_S2LP": {
"s2lp.provide-default": true
}
}
}
}

43
components/802.15.4_RF/stm-s2lp-rf-driver/stm-s2lp-rf-driver/NanostackRfPhys2lp.h
View File

@ -28,42 +28,6 @@
// Uncomment to use testing gpios attached to TX/RX processes
// #define TEST_GPIOS_ENABLED
#if defined(TARGET_MTB_STM_S2LP)
#if !defined(S2LP_SPI_SDI)
#define S2LP_SPI_SDI PA_7
#endif
#if !defined(S2LP_SPI_SDO)
#define S2LP_SPI_SDO PA_6
#endif
#if !defined(S2LP_SPI_SCLK)
#define S2LP_SPI_SCLK PA_5
#endif
#if !defined(S2LP_SPI_CS)
#define S2LP_SPI_CS PC_0
#endif
#if !defined(S2LP_SPI_SDN)
#define S2LP_SPI_SDN PF_13
#endif
#if !defined(S2LP_SPI_GPIO0)
#define S2LP_SPI_GPIO0 PA_3
#endif
#if !defined(S2LP_SPI_GPIO1)
#define S2LP_SPI_GPIO1 PC_3
#endif
#if !defined(S2LP_SPI_GPIO2)
#define S2LP_SPI_GPIO2 PF_3
#endif
#if !defined(S2LP_SPI_GPIO3)
#define S2LP_SPI_GPIO3 PF_10
#endif
#if !defined(S2LP_I2C_SDA)
#define S2LP_I2C_SDA PB_7
#endif
#if !defined(S2LP_I2C_SCL)
#define S2LP_I2C_SCL PB_6
#endif
#define AT24MAC
#else
#if !defined(S2LP_SPI_SDI)
#define S2LP_SPI_SDI D11
#endif
@ -106,7 +70,6 @@
#if !defined(S2LP_SPI_GPIO3)
#define S2LP_SPI_GPIO3 A5
#endif
#endif
#include "at24mac_s2lp.h"
@ -116,11 +79,11 @@ class TestPins_S2LP;
class NanostackRfPhys2lp : public NanostackRfPhy {
public:
NanostackRfPhys2lp(PinName spi_sdi, PinName spi_sdo, PinName spi_sclk, PinName spi_cs, PinName spi_sdn
,PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3
, PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3
#ifdef AT24MAC
,PinName i2c_sda, PinName i2c_scl
, PinName i2c_sda, PinName i2c_scl
#endif //AT24MAC
);
);
virtual ~NanostackRfPhys2lp();
virtual int8_t rf_register();
virtual void rf_unregister();

12
components/storage/blockdevice/COMPONENT_SD/mbed_lib.json
View File

@ -71,12 +71,6 @@
"SPI_CLK": "PTE2",
"SPI_CS": "PTE4"
},
"LPC11U37H_401": {
"SPI_MOSI": "SDMOSI",
"SPI_MISO": "SDMISO",
"SPI_CLK": "SDSCLK",
"SPI_CS": "SDSSEL"
},
"LPC2368": {
"SPI_MOSI": "p11",
"SPI_MISO": "p12",
@ -131,12 +125,6 @@
"SPI_CLK": "PTE2",
"SPI_CS": "PTE4"
},
"MTB_MTS_DRAGONFLY": {
"SPI_MOSI": "SPI2_MOSI",
"SPI_MISO": "SPI2_MISO",
"SPI_CLK": "SPI2_SCK",
"SPI_CS": "SPI_CS2"
},
"TB_SENSE_12": {
"SPI_MOSI": "PC6",
"SPI_MISO": "PC7",

12
components/storage/blockdevice/COMPONENT_SPIF/mbed_lib.json
View File

@ -37,24 +37,12 @@
"SPI_CLK": "PTD5",
"SPI_CS": "PTD4"
},
"MTB_ADV_WISE_1530": {
"SPI_MOSI": "PC_3",
"SPI_MISO": "PC_2",
"SPI_CLK": "PB_13",
"SPI_CS": "PC_12"
},
"WIO_EMW3166": {
"SPI_MOSI": "PB_15",
"SPI_MISO": "PB_14",
"SPI_CLK": "PB_13",
"SPI_CS": "PA_10"
},
"MTB_USI_WM_BN_BM_22": {
"SPI_MOSI": "PC_3",
"SPI_MISO": "PC_2",
"SPI_CLK": "PB_13",
"SPI_CS": "PA_6"
},
"MTB_ADV_WISE_1570": {
"SPI_MOSI": "PA_7",
"SPI_MISO": "PA_6",

8
features/cellular/framework/targets/QUECTEL/BG96/mbed_lib.json
View File

@ -37,13 +37,5 @@
"help": "Provide as default CellularDevice [true/false]",
"value": false
}
},
"target_overrides": {
"MTB_STM_L475": {
"tx": "SERIAL_TX",
"rx": "SERIAL_RX",
"pwr": "PE_15",
"rst": "PE_9"
}
}
}

60
features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F4/TARGET_OLIMEX_STM32E407_F407ZG/stm32f4_eth_conf.c
View File

@ -1,60 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "stm32f4xx_hal.h"
void _eth_config_mac(ETH_HandleTypeDef *heth)
{
ETH_MACInitTypeDef macconf = {
.Watchdog = ETH_WATCHDOG_ENABLE,
.Jabber = ETH_JABBER_ENABLE,
.InterFrameGap = ETH_INTERFRAMEGAP_96BIT,
.CarrierSense = ETH_CARRIERSENCE_ENABLE,
.ReceiveOwn = ETH_RECEIVEOWN_ENABLE,
.LoopbackMode = ETH_LOOPBACKMODE_DISABLE,
.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE,
.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE,
.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE,
.BackOffLimit = ETH_BACKOFFLIMIT_10,
.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE,
.ReceiveAll = ETH_RECEIVEAll_DISABLE,
.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE,
.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL,
.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE,
.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL,
.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE,
.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_NONE, // Disable multicast filter
.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT,
.HashTableHigh = 0x0U,
.HashTableLow = 0x0U,
.PauseTime = 0x0U,
.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE,
.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4,
.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE,
.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE,
.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE,
.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT,
.VLANTagIdentifier = 0x0U,
};
if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) {
macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
} else {
macconf.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
}
(void) HAL_ETH_ConfigMAC(heth, &macconf);
}

114
features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F4/TARGET_OLIMEX_STM32E407_F407ZG/stm32f4_eth_init.c
View File

@ -1,114 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
#include "stm32f4xx_hal.h"
/**
* Override HAL Eth Init function
*/
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStructure;
if (heth->Instance == ETH) {
/* Enable GPIOs clocks */
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
/** ETH GPIO Configuration
RMII_REF_CLK ----------------------> PA1
RMII_MDIO -------------------------> PA2
RMII_MDC --------------------------> PC1
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PG14
*/
/* Configure PA1, PA2 and PA7 */
GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
GPIO_InitStructure.Pull = GPIO_NOPULL;
GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
/* Configure PC1, PC4 and PC5 */
GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
/* Configure PG2, PG11 and PG13 */
GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
/* Enable the Ethernet global Interrupt */
HAL_NVIC_SetPriority(ETH_IRQn, 0x7, 0);
HAL_NVIC_EnableIRQ(ETH_IRQn);
/* Enable ETHERNET clock */
__HAL_RCC_ETH_CLK_ENABLE();
}
}
/**
* Override HAL Eth DeInit function
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */
__HAL_RCC_ETH_CLK_DISABLE();
/** ETH GPIO Configuration
RMII_REF_CLK ----------------------> PA1
RMII_MDIO -------------------------> PA2
RMII_MDC --------------------------> PC1
RMII_MII_CRS_DV -------------------> PA7
RMII_MII_RXD0 ---------------------> PC4
RMII_MII_RXD1 ---------------------> PC5
RMII_MII_RXER ---------------------> none
RMII_MII_TX_EN --------------------> PG11
RMII_MII_TXD0 ---------------------> PG13
RMII_MII_TXD1 ---------------------> PG14
*/
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7);
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14);
/* Disable the Ethernet global Interrupt */
NVIC_DisableIRQ(ETH_IRQn);
}
}
#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */

7
features/storage/TESTS/blockdevice/heap_block_device/main.cpp
View File

@ -23,11 +23,6 @@
using namespace utest::v1;
// TODO HACK, replace with available ram/heap property
#if defined(TARGET_MTB_MTS_XDOT)
#error [NOT_SUPPORTED] Insufficient heap for heap block device tests
#else
#define TEST_BLOCK_SIZE 128
#define TEST_BLOCK_DEVICE_SIZE 32*TEST_BLOCK_SIZE
#define TEST_BLOCK_COUNT 10
@ -186,5 +181,3 @@ int main()
{
return !Harness::run(specification);
}
#endif // defined(TARGET_MTB_MTS_XDOT)

7
features/storage/TESTS/blockdevice/mbr_block_device/main.cpp
View File

@ -24,11 +24,6 @@
using namespace utest::v1;
// TODO HACK, replace with available ram/heap property
#if defined(TARGET_MTB_MTS_XDOT)
#error [NOT_SUPPORTED] Insufficient heap for heap block device tests
#else
#define BLOCK_COUNT 16
#define BLOCK_SIZE 512
@ -250,5 +245,3 @@ int main()
{
return !Harness::run(specification);
}
#endif // defined(TARGET_MTB_MTS_XDOT)

7
features/storage/TESTS/blockdevice/util_block_device/main.cpp
View File

@ -26,11 +26,6 @@
using namespace utest::v1;
// TODO HACK, replace with available ram/heap property
#if defined(TARGET_MTB_MTS_XDOT)
#error [NOT_SUPPORTED] Insufficient heap for heap block device tests
#else
#define BLOCK_COUNT 16
#define BLOCK_SIZE 512
@ -308,5 +303,3 @@ int main()
{
return !Harness::run(specification);
}
#endif // defined(TARGET_MTB_MTS_XDOT)

86
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralNames.h
View File

@ -1,86 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)UART0_BASE,
UART_1 = (int)UART1_BASE,
UART_2 = (int)UART2_BASE
} UARTName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
typedef enum {
I2C_0 = (int)I2C0_BASE,
I2C_1 = (int)I2C1_BASE,
} I2CName;
#define TPM_SHIFT 8
typedef enum {
PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
} PWMName;
typedef enum {
ADC0_SE4b = 4,
ADC0_SE5b = 5,
ADC0_SE6b = 6,
ADC0_SE7b = 7,
ADC0_SE8 = 8,
ADC0_SE9 = 9,
ADC0_SE12 = 12,
ADC0_SE13 = 13,
ADC0_SE14 = 14,
ADC0_SE15 = 15,
ADC1_SE4b = 16,
ADC1_SE5b = 17,
ADC1_SE6b = 18,
ADC1_SE7b = 19,
} ADCName;
typedef enum {
DAC_0 = 0
} DACName;
typedef enum {
SPI_0 = (int)SPI0_BASE,
SPI_1 = (int)SPI0_BASE,
SPI_2 = (int)SPI0_BASE,
SPI_3 = (int)SPI0_BASE,
SPI_4 = (int)SPI0_BASE,
} SPIName;
#ifdef __cplusplus
}
#endif
#endif

137
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PeripheralPins.c
View File

@ -1,137 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PTC2, ADC0_SE4b, 0},
{PTD1, ADC0_SE5b, 0},
{PTD5, ADC0_SE6b, 0},
{PTD6, ADC0_SE7b, 0},
{PTB0, ADC0_SE8, 0},
{PTB1, ADC0_SE9, 0},
{PTB2, ADC0_SE12, 0},
{PTB3, ADC0_SE13, 0},
{PTC0, ADC0_SE14, 0},
{PTC1, ADC0_SE15, 0},
{PTC8, ADC1_SE4b, 0},
{PTC9, ADC1_SE5b, 0},
{PTC10,ADC1_SE6b, 0},
{PTC11,ADC1_SE7b, 0},
{NC, NC, 0}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{DAC0_OUT, DAC_0, 0},
{NC , NC , 0}
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{PTB1, I2C_0, 2},
{PTB3, I2C_0, 2},
{PTE0, I2C_1, 2},
{PTC11, I2C_1, 2},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PTB0, I2C_0, 2},
{PTB2, I2C_0, 2},
{PTE1, I2C_1, 2},
{PTC10, I2C_1, 2},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{PTB17, UART_0, 3},
{PTC4 , UART_1, 3},
{PTD3 , UART_2, 3},
{PTD7 , UART_0, 3},
{PTE0 , UART_1, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{PTB16, UART_0, 3},
{PTC3 , UART_1, 3},
{PTD2 , UART_2, 3},
{PTD6 , UART_0, 3},
{PTE1 , UART_1, 3},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = { // SCK
{PTC5, SPI_0, 2},
{PTD1, SPI_0, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = { // DOUT
{PTD2, SPI_0, 2},
{PTC6, SPI_0, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = { // DIN
{PTD3, SPI_0, 2},
{PTC7, SPI_0, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = { // CS
{PTD0, SPI_0, 2},
{PTC4, SPI_0, 2},
{PTD4, SPI_0, 2},
{PTC3, SPI_0, 2},
{PTC2, SPI_0, 2},
{PTD5, SPI_0, 2},
{PTD6, SPI_0, 2},
{PTC1, SPI_0, 2},
{PTC0, SPI_0, 2}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
// LEDs
{LED_RED , PWM_3 , 4}, // PTC3, FTM0 CH2
{LED_GREEN, PWM_5, 4}, // PTD4, FTM0 CH4
{LED_BLUE , PWM_8 , 3}, // PTA2, FTM0 CH7
{PTA0, PWM_6 , 3}, // PTA0, FTM0 CH5
{PTA1, PWM_7 , 3}, // PTA1, FTM0 CH6
{PTA3, PWM_1 , 3}, // PTA3, FTM0 CH0
{PTA4, PWM_2 , 3}, // PTA4, FTM0 CH1
{PTA5, PWM_3 , 3}, // PTA5, FTM0 CH2
{PTA12, PWM_9 , 3}, // PTA12, FTM1 CH0
{PTA13, PWM_10, 3}, // PTA13, FTM1 CH1
{PTB0, PWM_9 , 3}, // PTB0, FTM1 CH0
{PTB1, PWM_10, 3}, // PTB1, FTM1 CH1
{PTC1, PWM_1 , 4}, // PTC1, FTM0 CH0
{PTC2, PWM_2 , 4}, // PTC2, FTM0 CH1
{PTC3, PWM_3 , 4}, // PTC3, FTM0 CH2
{PTD4, PWM_4 , 4}, // PTD4, FTM0 CH3
{PTD5, PWM_6 , 4}, // PTD5, FTM0 CH6
{PTD6, PWM_7 , 4}, // PTD6, FTM0 CH6
{PTD7, PWM_8 , 4}, // PTD7, FTM0 CH7
{NC , NC , 0}
};

310
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h
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@ -1,310 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
/* PCR - 0x1000 */
#define PORT_SHIFT 12
typedef enum {
PTA0 = 0x0,
PTA1 = 0x4,
PTA2 = 0x8,
PTA3 = 0xc,
PTA4 = 0x10,
PTA5 = 0x14,
PTA6 = 0x18,
PTA7 = 0x1c,
PTA8 = 0x20,
PTA9 = 0x24,
PTA10 = 0x28,
PTA11 = 0x2c,
PTA12 = 0x30,
PTA13 = 0x34,
PTA14 = 0x38,
PTA15 = 0x3c,
PTA16 = 0x40,
PTA17 = 0x44,
PTA18 = 0x48,
PTA19 = 0x4c,
PTA20 = 0x50,
PTA21 = 0x54,
PTA22 = 0x58,
PTA23 = 0x5c,
PTA24 = 0x60,
PTA25 = 0x64,
PTA26 = 0x68,
PTA27 = 0x6c,
PTA28 = 0x70,
PTA29 = 0x74,
PTA30 = 0x78,
PTA31 = 0x7c,
PTB0 = 0x1000,
PTB1 = 0x1004,
PTB2 = 0x1008,
PTB3 = 0x100c,
PTB4 = 0x1010,
PTB5 = 0x1014,
PTB6 = 0x1018,
PTB7 = 0x101c,
PTB8 = 0x1020,
PTB9 = 0x1024,
PTB10 = 0x1028,
PTB11 = 0x102c,
PTB12 = 0x1030,
PTB13 = 0x1034,
PTB14 = 0x1038,
PTB15 = 0x103c,
PTB16 = 0x1040,
PTB17 = 0x1044,
PTB18 = 0x1048,
PTB19 = 0x104c,
PTB20 = 0x1050,
PTB21 = 0x1054,
PTB22 = 0x1058,
PTB23 = 0x105c,
PTB24 = 0x1060,
PTB25 = 0x1064,
PTB26 = 0x1068,
PTB27 = 0x106c,
PTB28 = 0x1070,
PTB29 = 0x1074,
PTB30 = 0x1078,
PTB31 = 0x107c,
PTC0 = 0x2000,
PTC1 = 0x2004,
PTC2 = 0x2008,
PTC3 = 0x200c,
PTC4 = 0x2010,
PTC5 = 0x2014,
PTC6 = 0x2018,
PTC7 = 0x201c,
PTC8 = 0x2020,
PTC9 = 0x2024,
PTC10 = 0x2028,
PTC11 = 0x202c,
PTC12 = 0x2030,
PTC13 = 0x2034,
PTC14 = 0x2038,
PTC15 = 0x203c,
PTC16 = 0x2040,
PTC17 = 0x2044,
PTC18 = 0x2048,
PTC19 = 0x204c,
PTC20 = 0x2050,
PTC21 = 0x2054,
PTC22 = 0x2058,
PTC23 = 0x205c,
PTC24 = 0x2060,
PTC25 = 0x2064,
PTC26 = 0x2068,
PTC27 = 0x206c,
PTC28 = 0x2070,
PTC29 = 0x2074,
PTC30 = 0x2078,
PTC31 = 0x207c,
PTD0 = 0x3000,
PTD1 = 0x3004,
PTD2 = 0x3008,
PTD3 = 0x300c,
PTD4 = 0x3010,
PTD5 = 0x3014,
PTD6 = 0x3018,
PTD7 = 0x301c,
PTD8 = 0x3020,
PTD9 = 0x3024,
PTD10 = 0x3028,
PTD11 = 0x302c,
PTD12 = 0x3030,
PTD13 = 0x3034,
PTD14 = 0x3038,
PTD15 = 0x303c,
PTD16 = 0x3040,
PTD17 = 0x3044,
PTD18 = 0x3048,
PTD19 = 0x304c,
PTD20 = 0x3050,
PTD21 = 0x3054,
PTD22 = 0x3058,
PTD23 = 0x305c,
PTD24 = 0x3060,
PTD25 = 0x3064,
PTD26 = 0x3068,
PTD27 = 0x306c,
PTD28 = 0x3070,
PTD29 = 0x3074,
PTD30 = 0x3078,
PTD31 = 0x307c,
PTE0 = 0x4000,
PTE1 = 0x4004,
PTE2 = 0x4008,
PTE3 = 0x400c,
PTE4 = 0x4010,
PTE5 = 0x4014,
PTE6 = 0x4018,
PTE7 = 0x401c,
PTE8 = 0x4020,
PTE9 = 0x4024,
PTE10 = 0x4028,
PTE11 = 0x402c,
PTE12 = 0x4030,
PTE13 = 0x4034,
PTE14 = 0x4038,
PTE15 = 0x403c,
PTE16 = 0x4040,
PTE17 = 0x4044,
PTE18 = 0x4048,
PTE19 = 0x404c,
PTE20 = 0x4050,
PTE21 = 0x4054,
PTE22 = 0x4058,
PTE23 = 0x405c,
PTE24 = 0x4060,
PTE25 = 0x4064,
PTE26 = 0x4068,
PTE27 = 0x406c,
PTE28 = 0x4070,
PTE29 = 0x4074,
PTE30 = 0x4078,
PTE31 = 0x407c,
LED_RED = PTC5, // set these to the only led on board
LED_GREEN = PTC5, //
LED_BLUE = PTC5, //
// mbed original LED naming
LED1 = LED_RED,
LED2 = LED_GREEN,
LED3 = LED_BLUE,
LED4 = LED_BLUE,
// USB Pins
USBTX = PTB17,
USBRX = PTB16,
// DAC Pins
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
// Teensy3.1 Headers
D0 = PTB16,
D1 = PTB17,
D2 = PTD0,
D3 = PTA12,
D4 = PTA13,
D5 = PTD7,
D6 = PTD4,
D7 = PTD2,
D8 = PTD3,
D9 = PTC3,
D10 = PTC4,
D11 = PTC6,
D12 = PTC7,
D13 = PTC5,
D14 = PTD1,
D15 = PTC0,
D16 = PTB0,
D17 = PTB1,
D18 = PTB3,
D19 = PTB2,
D20 = PTD5,
D21 = PTD6,
D22 = PTC1,
D23 = PTC2,
D24 = PTA5,
D25 = PTB19,
D26 = PTE1,
D27 = PTC9,
D28 = PTC8,
D29 = PTC10,
D30 = PTC11,
D31 = PTE0,
D32 = PTB18,
D33 = PTA4,
A0 = PTD1,
A1 = PTC0,
A2 = PTB0,
A3 = PTB1,
A4 = PTB3,
A5 = PTB2,
A6 = PTD5,
A7 = PTD6,
A8 = PTC1,
A9 = PTC2,
A15 = PTE1,
A16 = PTC9,
A17 = PTC8,
A18 = PTC10,
A19 = PTC11,
A20 = PTE0,
I2C_SCL = PTB2,
I2C_SDA = PTB3,
SPI_SCK = PTC5, // sclk
SPI_DOUT = PTC6, // mosi
SPI_DIN = PTC7, // miso
SPI_CS = PTC4, // ssel
SERIAL_TX = PTB17,
SERIAL_RX = PTB16,
PWM = PTA12,
PWM1 = PTA13,
PWM2 = PTD7,
PWM3 = PTD4,
PWM4 = PTC3,
PWM5 = PTC4,
PWM6 = PTD5,
PWM7 = PTD6,
PWM8 = PTC1,
PWM9 = PTC2,
PWM10 = PTB19,
PWM11 = PTB18,
DAC = DAC0_OUT,
TSI_ELEC0 = PTC1,
TSI_ELEC1 = PTC2,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 2,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

39
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device.h
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@ -1,39 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 24
#include "objects.h"
#endif

6034
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/MK20DX256.h
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File diff suppressed because it is too large Load Diff

26
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_ARM_STD/MK20DX256.sct
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@ -1,26 +0,0 @@
#! armcc -E
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(112 vect * 4 bytes) = 8_byte_aligned(0x1C0) = 0x1C0
; 0x10000 - 0x1C0 = 0xFE40
RW_IRAM1 0x1FFF81C0 0xFE40 {
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x1FFF8000+0x10000-Stack_Size-AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap region growing up
}
ARM_LIB_STACK 0x1FFF8000+0x10000 EMPTY -Stack_Size { ; Stack region growing down
}
}

558
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_ARM_STD/startup_MK20DX256.S
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;/*****************************************************************************
; * @file: startup_MK20DX256.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
; * MK20DX256
; * @version: 1.0
; * @date: 2011-12-15
; *
; * Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
;*
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; *****************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
DCD DMA4_IRQHandler ; DMA channel 4 transfer complete interrupt
DCD DMA5_IRQHandler ; DMA channel 5 transfer complete interrupt
DCD DMA6_IRQHandler ; DMA channel 6 transfer complete interrupt
DCD DMA7_IRQHandler ; DMA channel 7 transfer complete interrupt
DCD DMA8_IRQHandler ; DMA channel 8 transfer complete interrupt
DCD DMA9_IRQHandler ; DMA channel 9 transfer complete interrupt
DCD DMA10_IRQHandler ; DMA channel 10 transfer complete interrupt
DCD DMA11_IRQHandler ; DMA channel 11 transfer complete interrupt
DCD DMA12_IRQHandler ; DMA channel 12 transfer complete interrupt
DCD DMA13_IRQHandler ; DMA channel 13 transfer complete interrupt
DCD DMA14_IRQHandler ; DMA channel 14 transfer complete interrupt
DCD DMA15_IRQHandler ; DMA channel 15 transfer complete interrupt
DCD DMA_Error_IRQHandler ; DMA error interrupt
DCD Reserved33_IRQHandler ; Reserved interrupt 33
DCD FTFL_IRQHandler ; FTFL interrupt
DCD Read_Collision_IRQHandler ; Read collision interrupt
DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
DCD LLW_IRQHandler ; Low Leakage Wakeup
DCD Watchdog_IRQHandler ; WDOG interrupt
DCD Reserved39_IRQHandler ; Reserved interrupt 39
DCD I2C0_IRQHandler ; I2C0 interrupt
DCD I2C1_IRQHandler ; I2C1 interrupt
DCD SPI0_IRQHandler ; SPI0 interrupt
DCD SPI1_IRQHandler ; SPI1 interrupt
DCD Reserved44_IRQHandler ; Reserved interrupt 44
DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
DCD Reserved53_IRQHandler ; Reserved interrupt 53
DCD Reserved54_IRQHandler ; Reserved interrupt 54
DCD Reserved55_IRQHandler ; Reserved interrupt 55
DCD Reserved56_IRQHandler ; Reserved interrupt 56
DCD Reserved57_IRQHandler ; Reserved interrupt 57
DCD Reserved58_IRQHandler ; Reserved interrupt 58
DCD Reserved59_IRQHandler ; Reserved interrupt 59
DCD UART0_LON_IRQHandler ; UART0 LON interrupt
DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
DCD UART0_ERR_IRQHandler ; UART0 error interrupt
DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
DCD UART1_ERR_IRQHandler ; UART1 error interrupt
DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
DCD UART2_ERR_IRQHandler ; UART2 error interrupt
DCD Reserved67_IRQHandler ; Reserved interrupt 67
DCD Reserved68_IRQHandler ; Reserved interrupt 68
DCD Reserved69_IRQHandler ; Reserved interrupt 69
DCD Reserved70_IRQHandler ; Reserved interrupt 70
DCD Reserved71_IRQHandler ; Reserved interrupt 71
DCD Reserved72_IRQHandler ; Reserved interrupt 72
DCD ADC0_IRQHandler ; ADC0 interrupt
DCD ADC1_IRQHandler ; ADC1 interrupt
DCD CMP0_IRQHandler ; CMP0 interrupt
DCD CMP1_IRQHandler ; CMP1 interrupt
DCD CMP2_IRQHandler ; CMP2 interrupt
DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
DCD CMT_IRQHandler ; CMT interrupt
DCD RTC_IRQHandler ; RTC interrupt
DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
DCD PDB0_IRQHandler ; PDB0 interrupt
DCD USB0_IRQHandler ; USB0 interrupt
DCD USBDCD_IRQHandler ; USBDCD interrupt
DCD Reserved91_IRQHandler ; Reserved interrupt 91
DCD Reserved92_IRQHandler ; Reserved interrupt 92
DCD Reserved93_IRQHandler ; Reserved interrupt 93
DCD Reserved94_IRQHandler ; Reserved interrupt 94
DCD Reserved95_IRQHandler ; Reserved interrupt 95
DCD Reserved96_IRQHandler ; Reserved interrupt 96
DCD DAC0_IRQHandler ; DAC0 interrupt
DCD Reserved98_IRQHandler ; Reserved interrupt 98
DCD TSI0_IRQHandler ; TSI0 interrupt
DCD MCG_IRQHandler ; MCG interrupt
DCD LPTimer_IRQHandler ; LPTimer interrupt
DCD Reserved102_IRQHandler ; Reserved interrupt 102
DCD PORTA_IRQHandler ; Port A interrupt
DCD PORTB_IRQHandler ; Port B interrupt
DCD PORTC_IRQHandler ; Port C interrupt
DCD PORTD_IRQHandler ; Port D interrupt
DCD PORTE_IRQHandler ; Port E interrupt
DCD Reserved108_IRQHandler ; Reserved interrupt 108
DCD Reserved109_IRQHandler ; Reserved interrupt 109
DCD SWI_IRQHandler ; Software interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; <h> Flash Configuration
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
; <i> and security information that allows the MCU to restrict acces to the FTFL module.
; <h> Backdoor Comparison Key
; <o0> Backdoor Key 0 <0x0-0xFF:2>
; <o1> Backdoor Key 1 <0x0-0xFF:2>
; <o2> Backdoor Key 2 <0x0-0xFF:2>
; <o3> Backdoor Key 3 <0x0-0xFF:2>
; <o4> Backdoor Key 4 <0x0-0xFF:2>
; <o5> Backdoor Key 5 <0x0-0xFF:2>
; <o6> Backdoor Key 6 <0x0-0xFF:2>
; <o7> Backdoor Key 7 <0x0-0xFF:2>
BackDoorK0 EQU 0xFF
BackDoorK1 EQU 0xFF
BackDoorK2 EQU 0xFF
BackDoorK3 EQU 0xFF
BackDoorK4 EQU 0xFF
BackDoorK5 EQU 0xFF
BackDoorK6 EQU 0xFF
BackDoorK7 EQU 0xFF
; </h>
; <h> Program flash protection bytes (FPROT)
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
; <i> Each bit protects a 1/32 region of the program flash memory.
; <h> FPROT0
; <i> Program flash protection bytes
; <i> 1/32 - 8/32 region
; <o.0> FPROT0.0
; <o.1> FPROT0.1
; <o.2> FPROT0.2
; <o.3> FPROT0.3
; <o.4> FPROT0.4
; <o.5> FPROT0.5
; <o.6> FPROT0.6
; <o.7> FPROT0.7
nFPROT0 EQU 0x00
FPROT0 EQU nFPROT0:EOR:0xFF
; </h>
; <h> FPROT1
; <i> Program Flash Region Protect Register 1
; <i> 9/32 - 16/32 region
; <o.0> FPROT1.0
; <o.1> FPROT1.1
; <o.2> FPROT1.2
; <o.3> FPROT1.3
; <o.4> FPROT1.4
; <o.5> FPROT1.5
; <o.6> FPROT1.6
; <o.7> FPROT1.7
nFPROT1 EQU 0x00
FPROT1 EQU nFPROT1:EOR:0xFF
; </h>
; <h> FPROT2
; <i> Program Flash Region Protect Register 2
; <i> 17/32 - 24/32 region
; <o.0> FPROT2.0
; <o.1> FPROT2.1
; <o.2> FPROT2.2
; <o.3> FPROT2.3
; <o.4> FPROT2.4
; <o.5> FPROT2.5
; <o.6> FPROT2.6
; <o.7> FPROT2.7
nFPROT2 EQU 0x00
FPROT2 EQU nFPROT2:EOR:0xFF
; </h>
; <h> FPROT3
; <i> Program Flash Region Protect Register 3
; <i> 25/32 - 32/32 region
; <o.0> FPROT3.0
; <o.1> FPROT3.1
; <o.2> FPROT3.2
; <o.3> FPROT3.3
; <o.4> FPROT3.4
; <o.5> FPROT3.5
; <o.6> FPROT3.6
; <o.7> FPROT3.7
nFPROT3 EQU 0x00
FPROT3 EQU nFPROT3:EOR:0xFF
; </h>
; </h>
; <h> Data flash protection byte (FDPROT)
; <i> Each bit protects a 1/8 region of the data flash memory.
; <i> (Program flash only devices: Reserved)
; <o.0> FDPROT.0
; <o.1> FDPROT.1
; <o.2> FDPROT.2
; <o.3> FDPROT.3
; <o.4> FDPROT.4
; <o.5> FDPROT.5
; <o.6> FDPROT.6
; <o.7> FDPROT.7
nFDPROT EQU 0x00
FDPROT EQU nFDPROT:EOR:0xFF
; </h>
; <h> EEPROM protection byte (FEPROT)
; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
; <i> (Program flash only devices: Reserved)
; <o.0> FEPROT.0
; <o.1> FEPROT.1
; <o.2> FEPROT.2
; <o.3> FEPROT.3
; <o.4> FEPROT.4
; <o.5> FEPROT.5
; <o.6> FEPROT.6
; <o.7> FEPROT.7
nFEPROT EQU 0x00
FEPROT EQU nFEPROT:EOR:0xFF
; </h>
; <h> Flash nonvolatile option byte (FOPT)
; <i> Allows the user to customize the operation of the MCU at boot time.
; <o.0> LPBOOT
; <0=> Low-power boot
; <1=> normal boot
; <o.1> EZPORT_DIS
; <0=> EzPort operation is enabled
; <1=> EzPort operation is disabled
FOPT EQU 0xFF
; </h>
; <h> Flash security byte (FSEC)
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
; <o.0..1> SEC
; <2=> MCU security status is unsecure
; <3=> MCU security status is secure
; <i> Flash Security
; <i> This bits define the security state of the MCU.
; <o.2..3> FSLACC
; <2=> Freescale factory access denied
; <3=> Freescale factory access granted
; <i> Freescale Failure Analysis Access Code
; <i> This bits define the security state of the MCU.
; <o.4..5> MEEN
; <2=> Mass erase is disabled
; <3=> Mass erase is enabled
; <i> Mass Erase Enable Bits
; <i> Enables and disables mass erase capability of the FTFL module
; <o.6..7> KEYEN
; <2=> Backdoor key access enabled
; <3=> Backdoor key access disabled
; <i> Backdoor key Security Enable
; <i> These bits enable and disable backdoor key access to the FTFL module.
FSEC EQU 0xFE
; </h>
; </h>
IF :LNOT::DEF:RAM_TARGET
AREA |.ARM.__at_0x400|, CODE, READONLY
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
DCB FPROT0, FPROT1, FPROT2, FPROT3
DCB FSEC, FOPT, FEPROT, FDPROT
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DMA0_IRQHandler [WEAK]
EXPORT DMA1_IRQHandler [WEAK]
EXPORT DMA2_IRQHandler [WEAK]
EXPORT DMA3_IRQHandler [WEAK]
EXPORT DMA4_IRQHandler [WEAK]
EXPORT DMA5_IRQHandler [WEAK]
EXPORT DMA6_IRQHandler [WEAK]
EXPORT DMA7_IRQHandler [WEAK]
EXPORT DMA8_IRQHandler [WEAK]
EXPORT DMA9_IRQHandler [WEAK]
EXPORT DMA10_IRQHandler [WEAK]
EXPORT DMA11_IRQHandler [WEAK]
EXPORT DMA12_IRQHandler [WEAK]
EXPORT DMA13_IRQHandler [WEAK]
EXPORT DMA14_IRQHandler [WEAK]
EXPORT DMA15_IRQHandler [WEAK]
EXPORT DMA_Error_IRQHandler [WEAK]
EXPORT Reserved33_IRQHandler [WEAK]
EXPORT FTFL_IRQHandler [WEAK]
EXPORT Read_Collision_IRQHandler [WEAK]
EXPORT LVD_LVW_IRQHandler [WEAK]
EXPORT LLW_IRQHandler [WEAK]
EXPORT Watchdog_IRQHandler [WEAK]
EXPORT Reserved39_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT Reserved44_IRQHandler [WEAK]
EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
EXPORT CAN0_Error_IRQHandler [WEAK]
EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
EXPORT I2S0_Tx_IRQHandler [WEAK]
EXPORT I2S0_Rx_IRQHandler [WEAK]
EXPORT Reserved53_IRQHandler [WEAK]
EXPORT Reserved54_IRQHandler [WEAK]
EXPORT Reserved55_IRQHandler [WEAK]
EXPORT Reserved56_IRQHandler [WEAK]
EXPORT Reserved57_IRQHandler [WEAK]
EXPORT Reserved58_IRQHandler [WEAK]
EXPORT Reserved59_IRQHandler [WEAK]
EXPORT UART0_LON_IRQHandler [WEAK]
EXPORT UART0_RX_TX_IRQHandler [WEAK]
EXPORT UART0_ERR_IRQHandler [WEAK]
EXPORT UART1_RX_TX_IRQHandler [WEAK]
EXPORT UART1_ERR_IRQHandler [WEAK]
EXPORT UART2_RX_TX_IRQHandler [WEAK]
EXPORT UART2_ERR_IRQHandler [WEAK]
EXPORT Reserved67_IRQHandler [WEAK]
EXPORT Reserved68_IRQHandler [WEAK]
EXPORT Reserved69_IRQHandler [WEAK]
EXPORT Reserved70_IRQHandler [WEAK]
EXPORT Reserved71_IRQHandler [WEAK]
EXPORT Reserved72_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT CMP0_IRQHandler [WEAK]
EXPORT CMP1_IRQHandler [WEAK]
EXPORT CMP2_IRQHandler [WEAK]
EXPORT FTM0_IRQHandler [WEAK]
EXPORT FTM1_IRQHandler [WEAK]
EXPORT FTM2_IRQHandler [WEAK]
EXPORT CMT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT RTC_Seconds_IRQHandler [WEAK]
EXPORT PIT0_IRQHandler [WEAK]
EXPORT PIT1_IRQHandler [WEAK]
EXPORT PIT2_IRQHandler [WEAK]
EXPORT PIT3_IRQHandler [WEAK]
EXPORT PDB0_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USBDCD_IRQHandler [WEAK]
EXPORT Reserved91_IRQHandler [WEAK]
EXPORT Reserved92_IRQHandler [WEAK]
EXPORT Reserved93_IRQHandler [WEAK]
EXPORT Reserved94_IRQHandler [WEAK]
EXPORT Reserved95_IRQHandler [WEAK]
EXPORT Reserved96_IRQHandler [WEAK]
EXPORT DAC0_IRQHandler [WEAK]
EXPORT Reserved98_IRQHandler [WEAK]
EXPORT TSI0_IRQHandler [WEAK]
EXPORT MCG_IRQHandler [WEAK]
EXPORT LPTimer_IRQHandler [WEAK]
EXPORT Reserved102_IRQHandler [WEAK]
EXPORT PORTA_IRQHandler [WEAK]
EXPORT PORTB_IRQHandler [WEAK]
EXPORT PORTC_IRQHandler [WEAK]
EXPORT PORTD_IRQHandler [WEAK]
EXPORT PORTE_IRQHandler [WEAK]
EXPORT Reserved108_IRQHandler [WEAK]
EXPORT Reserved109_IRQHandler [WEAK]
EXPORT SWI_IRQHandler [WEAK]
EXPORT DefaultISR [WEAK]
DMA0_IRQHandler
DMA1_IRQHandler
DMA2_IRQHandler
DMA3_IRQHandler
DMA4_IRQHandler
DMA5_IRQHandler
DMA6_IRQHandler
DMA7_IRQHandler
DMA8_IRQHandler
DMA9_IRQHandler
DMA10_IRQHandler
DMA11_IRQHandler
DMA12_IRQHandler
DMA13_IRQHandler
DMA14_IRQHandler
DMA15_IRQHandler
DMA_Error_IRQHandler
Reserved33_IRQHandler
FTFL_IRQHandler
Read_Collision_IRQHandler
LVD_LVW_IRQHandler
LLW_IRQHandler
Watchdog_IRQHandler
Reserved39_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
Reserved44_IRQHandler
CAN0_ORed_Message_buffer_IRQHandler
CAN0_Bus_Off_IRQHandler
CAN0_Error_IRQHandler
CAN0_Tx_Warning_IRQHandler
CAN0_Rx_Warning_IRQHandler
CAN0_Wake_Up_IRQHandler
I2S0_Tx_IRQHandler
I2S0_Rx_IRQHandler
Reserved53_IRQHandler
Reserved54_IRQHandler
Reserved55_IRQHandler
Reserved56_IRQHandler
Reserved57_IRQHandler
Reserved58_IRQHandler
Reserved59_IRQHandler
UART0_LON_IRQHandler
UART0_RX_TX_IRQHandler
UART0_ERR_IRQHandler
UART1_RX_TX_IRQHandler
UART1_ERR_IRQHandler
UART2_RX_TX_IRQHandler
UART2_ERR_IRQHandler
Reserved67_IRQHandler
Reserved68_IRQHandler
Reserved69_IRQHandler
Reserved70_IRQHandler
Reserved71_IRQHandler
Reserved72_IRQHandler
ADC0_IRQHandler
ADC1_IRQHandler
CMP0_IRQHandler
CMP1_IRQHandler
CMP2_IRQHandler
FTM0_IRQHandler
FTM1_IRQHandler
FTM2_IRQHandler
CMT_IRQHandler
RTC_IRQHandler
RTC_Seconds_IRQHandler
PIT0_IRQHandler
PIT1_IRQHandler
PIT2_IRQHandler
PIT3_IRQHandler
PDB0_IRQHandler
USB0_IRQHandler
USBDCD_IRQHandler
Reserved91_IRQHandler
Reserved92_IRQHandler
Reserved93_IRQHandler
Reserved94_IRQHandler
Reserved95_IRQHandler
Reserved96_IRQHandler
DAC0_IRQHandler
Reserved98_IRQHandler
TSI0_IRQHandler
MCG_IRQHandler
LPTimer_IRQHandler
Reserved102_IRQHandler
PORTA_IRQHandler
PORTB_IRQHandler
PORTC_IRQHandler
PORTD_IRQHandler
PORTE_IRQHandler
Reserved108_IRQHandler
Reserved109_IRQHandler
SWI_IRQHandler
DefaultISR
B .
ENDP
ALIGN
END

171
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_GCC_ARM/MK20DX256.ld
View File

@ -1,171 +0,0 @@
/*
* K20DX256 ARM GCC linker script file
*/
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
MEMORY
{
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410
RAM (rwx) : ORIGIN = 0x1FFF81C0, LENGTH = 64K - 0x1C0
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* _reset_init : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.isr_vector :
{
. = 0;
__isr_vector = .;
KEEP(*(.isr_vector))
*(.text.Reset_Handler)
*(.text.SystemInit)
. = ALIGN(8);
} > VECTORS
.flash_protect :
{
KEEP(*(.kinetis_flash_config_field))
. = ALIGN(8);
} > FLASH_PROTECTION
.text :
{
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(8);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

366
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/TOOLCHAIN_GCC_ARM/startup_MK20DX256.S
View File

@ -1,366 +0,0 @@
/* File: startup_MK20DX256.s
* Purpose: startup file for Cortex-M4 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V1.3
* Date: 08 Feb 2012
*
* Copyright (c) 2015, ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the ARM Limited nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0xC00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long DMA0_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA1_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA2_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA3_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA4_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA5_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA6_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA7_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA8_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA9_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA10_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA11_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA12_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA13_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA14_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA15_IRQHandler // DMA channel 0 transfer complete interrupt
.long DMA_Error_IRQHandler // DMA error interrupt
.long Reserved33_IRQHandler // Reserved interrupt 33
.long FTFL_IRQHandler // FTFL interrupt
.long Read_Collision_IRQHandler // Read collision interrupt
.long LVD_LVW_IRQHandler // Low Voltage Detect, Low Voltage Warning
.long LLW_IRQHandler // Low Leakage Wakeup
.long Watchdog_IRQHandler // WDOG interrupt
.long Reserved39_IRQHandler // Reserved interrupt 39
.long I2C0_IRQHandler // I2C0 interrupt
.long I2C1_IRQHandler // I2C1 interrupt
.long SPI0_IRQHandler // SPI0 interrupt
.long SPI1_IRQHandler // SPI1 interrupt
.long Reserved44_IRQHandler // Reserved interrupt 44
.long CAN0_ORed_Message_buffer_IRQHandler // CAN0 OR'd message buffers interrupt
.long CAN0_Bus_Off_IRQHandler // CAN0 bus off interrupt
.long CAN0_Error_IRQHandler // CAN0 error interrupt
.long CAN0_Tx_Warning_IRQHandler // CAN0 Tx warning interrupt
.long CAN0_Rx_Warning_IRQHandler // CAN0 Rx warning interrupt
.long CAN0_Wake_Up_IRQHandler // CAN0 wake up interrupt
.long I2S0_Tx_IRQHandler // I2S0 transmit interrupt
.long I2S0_Rx_IRQHandler // I2S0 receive interrupt
.long Reserved53_IRQHandler // Reserved interrupt 53
.long Reserved54_IRQHandler // Reserved interrupt 54
.long Reserved55_IRQHandler // Reserved interrupt 55
.long Reserved56_IRQHandler // Reserved interrupt 56
.long Reserved57_IRQHandler // Reserved interrupt 57
.long Reserved58_IRQHandler // Reserved interrupt 58
.long Reserved59_IRQHandler // Reserved interrupt 59
.long UART0_LON_IRQHandler // UART0 LON interrupt
.long UART0_RX_TX_IRQHandler // UART0 receive/transmit interrupt
.long UART0_ERR_IRQHandler // UART0 error interrupt
.long UART1_RX_TX_IRQHandler // UART1 receive/transmit interrupt
.long UART1_ERR_IRQHandler // UART1 error interrupt
.long UART2_RX_TX_IRQHandler // UART2 receive/transmit interrupt
.long UART2_ERR_IRQHandler // UART2 error interrupt
.long Reserved67_IRQHandler // Reserved interrupt 67
.long Reserved68_IRQHandler // Reserved interrupt 68
.long Reserved69_IRQHandler // Reserved interrupt 69
.long Reserved70_IRQHandler // Reserved interrupt 70
.long Reserved71_IRQHandler // Reserved interrupt 71
.long Reserved72_IRQHandler // Reserved interrupt 72
.long ADC0_IRQHandler // ADC0 interrupt
.long ADC1_IRQHandler // ADC1 interrupt
.long CMP0_IRQHandler // CMP0 interrupt
.long CMP1_IRQHandler // CMP1 interrupt
.long CMP2_IRQHandler // CMP2 interrupt
.long FTM0_IRQHandler // FTM0 fault, overflow and channels interrupt
.long FTM1_IRQHandler // FTM1 fault, overflow and channels interrupt
.long FTM2_IRQHandler // FTM2 fault, overflow and channels interrupt
.long CMT_IRQHandler // CMT interrupt
.long RTC_IRQHandler // RTC interrupt
.long RTC_Seconds_IRQHandler // RTC seconds interrupt
.long PIT0_IRQHandler // PIT timer channel 0 interrupt
.long PIT1_IRQHandler // PIT timer channel 1 interrupt
.long PIT2_IRQHandler // PIT timer channel 2 interrupt
.long PIT3_IRQHandler // PIT timer channel 3 interrupt
.long PDB0_IRQHandler // PDB0 interrupt
.long USB0_IRQHandler // USB0 interrupt
.long USBDCD_IRQHandler // USBDCD interrupt
.long Reserved91_IRQHandler // Reserved interrupt 91
.long Reserved92_IRQHandler // Reserved interrupt 92
.long Reserved93_IRQHandler // Reserved interrupt 93
.long Reserved94_IRQHandler // Reserved interrupt 94
.long Reserved95_IRQHandler // Reserved interrupt 95
.long Reserved96_IRQHandler // Reserved interrupt 96
.long DAC0_IRQHandler // DAC0 interrupt
.long Reserved98_IRQHandler // Reserved interrupt 98
.long TSI0_IRQHandler // TSI0 interrupt
.long MCG_IRQHandler // MCG interrupt
.long LPTimer_IRQHandler // LPTimer interrupt
.long Reserved102_IRQHandler // Reserved interrupt 102
.long PORTA_IRQHandler // Port A interrupt
.long PORTB_IRQHandler // Port B interrupt
.long PORTC_IRQHandler // Port C interrupt
.long PORTD_IRQHandler // Port D interrupt
.long PORTE_IRQHandler // Port E interrupt
.long Reserved108_IRQHandler // Reserved interrupt 108
.long Reserved109_IRQHandler // Reserved interrupt 109
.long SWI_IRQHandler // Software interrupt
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/*
* Call SystemInit before loading the .data section to prevent the watchdog
* from resetting the board.
*/
ldr r0, =SystemInit
blx r0
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler DMA0_IRQHandler
def_irq_default_handler DMA1_IRQHandler
def_irq_default_handler DMA2_IRQHandler
def_irq_default_handler DMA3_IRQHandler
def_irq_default_handler DMA4_IRQHandler
def_irq_default_handler DMA5_IRQHandler
def_irq_default_handler DMA6_IRQHandler
def_irq_default_handler DMA7_IRQHandler
def_irq_default_handler DMA8_IRQHandler
def_irq_default_handler DMA9_IRQHandler
def_irq_default_handler DMA10_IRQHandler
def_irq_default_handler DMA11_IRQHandler
def_irq_default_handler DMA12_IRQHandler
def_irq_default_handler DMA13_IRQHandler
def_irq_default_handler DMA14_IRQHandler
def_irq_default_handler DMA15_IRQHandler
def_irq_default_handler DMA_Error_IRQHandler
def_irq_default_handler Reserved33_IRQHandler
def_irq_default_handler FTFL_IRQHandler
def_irq_default_handler Read_Collision_IRQHandler
def_irq_default_handler LVD_LVW_IRQHandler
def_irq_default_handler LLW_IRQHandler
def_irq_default_handler Watchdog_IRQHandler
def_irq_default_handler Reserved39_IRQHandler
def_irq_default_handler I2C0_IRQHandler
def_irq_default_handler I2C1_IRQHandler
def_irq_default_handler SPI0_IRQHandler
def_irq_default_handler SPI1_IRQHandler
def_irq_default_handler Reserved44_IRQHandler
def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler
def_irq_default_handler CAN0_Bus_Off_IRQHandler
def_irq_default_handler CAN0_Error_IRQHandler
def_irq_default_handler CAN0_Tx_Warning_IRQHandler
def_irq_default_handler CAN0_Rx_Warning_IRQHandler
def_irq_default_handler CAN0_Wake_Up_IRQHandler
def_irq_default_handler I2S0_Tx_IRQHandler
def_irq_default_handler I2S0_Rx_IRQHandler
def_irq_default_handler Reserved53_IRQHandler
def_irq_default_handler Reserved54_IRQHandler
def_irq_default_handler Reserved55_IRQHandler
def_irq_default_handler Reserved56_IRQHandler
def_irq_default_handler Reserved57_IRQHandler
def_irq_default_handler Reserved58_IRQHandler
def_irq_default_handler Reserved59_IRQHandler
def_irq_default_handler UART0_LON_IRQHandler
def_irq_default_handler UART0_RX_TX_IRQHandler
def_irq_default_handler UART0_ERR_IRQHandler
def_irq_default_handler UART1_RX_TX_IRQHandler
def_irq_default_handler UART1_ERR_IRQHandler
def_irq_default_handler UART2_RX_TX_IRQHandler
def_irq_default_handler UART2_ERR_IRQHandler
def_irq_default_handler Reserved67_IRQHandler
def_irq_default_handler Reserved68_IRQHandler
def_irq_default_handler Reserved69_IRQHandler
def_irq_default_handler Reserved70_IRQHandler
def_irq_default_handler Reserved71_IRQHandler
def_irq_default_handler Reserved72_IRQHandler
def_irq_default_handler ADC0_IRQHandler
def_irq_default_handler ADC1_IRQHandler
def_irq_default_handler CMP0_IRQHandler
def_irq_default_handler CMP1_IRQHandler
def_irq_default_handler CMP2_IRQHandler
def_irq_default_handler FTM0_IRQHandler
def_irq_default_handler FTM1_IRQHandler
def_irq_default_handler FTM2_IRQHandler
def_irq_default_handler CMT_IRQHandler
def_irq_default_handler RTC_IRQHandler
def_irq_default_handler RTC_Seconds_IRQHandler
def_irq_default_handler PIT0_IRQHandler
def_irq_default_handler PIT1_IRQHandler
def_irq_default_handler PIT2_IRQHandler
def_irq_default_handler PIT3_IRQHandler
def_irq_default_handler PDB0_IRQHandler
def_irq_default_handler USB0_IRQHandler
def_irq_default_handler USBDCD_IRQHandler
def_irq_default_handler Reserved91_IRQHandler
def_irq_default_handler Reserved92_IRQHandler
def_irq_default_handler Reserved93_IRQHandler
def_irq_default_handler Reserved94_IRQHandler
def_irq_default_handler Reserved95_IRQHandler
def_irq_default_handler Reserved96_IRQHandler
def_irq_default_handler DAC0_IRQHandler
def_irq_default_handler Reserved98_IRQHandler
def_irq_default_handler TSI0_IRQHandler
def_irq_default_handler MCG_IRQHandler
def_irq_default_handler LPTimer_IRQHandler
def_irq_default_handler Reserved102_IRQHandler
def_irq_default_handler PORTA_IRQHandler
def_irq_default_handler PORTB_IRQHandler
def_irq_default_handler PORTC_IRQHandler
def_irq_default_handler PORTD_IRQHandler
def_irq_default_handler PORTE_IRQHandler
def_irq_default_handler Reserved108_IRQHandler
def_irq_default_handler Reserved109_IRQHandler
def_irq_default_handler SWI_IRQHandler
def_irq_default_handler DefaultISR
/* Flash protection region, placed at 0x400 */
.text
.thumb
.align 2
.section .kinetis_flash_config_field,"a",%progbits
kinetis_flash_config:
.long 0xffffffff
.long 0xffffffff
.long 0xffffffff
.long 0xfffffffe
.end

13
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/cmsis.h
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2015 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC11U24 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "MK20DX256.h"
#include "cmsis_nvic.h"
#endif

37
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/cmsis_nvic.h
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 95) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x1FFF8000 // Vectors positioned at start of RAM
#endif

280
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/system_MK20DX256.c
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/*
** ###################################################################
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
**
**
** Version: rev. 1.0, 2011-12-15
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2011-12-15)
** Initial version
**
** ###################################################################
*/
/**
* @file MK20DX256
* @version 1.0
* @date 2011-12-15
* @brief Device specific configuration file for MK20DX256 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "MK20DX256.h"
#define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups
0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 41.94MHz, BusClock = 41.94MHz
Works on Teensy3.1 but no USB support
1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external crystal 16MHz
Core clock = 96MHz, BusClock = 48MHz
Default high speed Teensy3.1 96Mhz set up
2 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
Reference clock source for MCG module is an external crystal 16MHz
Core clock = 72MHz, BusClock = 36MHz
Alternative standard 'slower' Teensy3.1 72Mhz set up
*/
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 96000000u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 2) */
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
/* SystemInit MUST NOT use any variables from the .data section, as this section is not loaded yet! */
#if (DISABLE_WDOG)
/* Disable the WDOG module */
/* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
/* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
/* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
WDOG->STCTRLH = (uint16_t)0x01D2u;
#endif /* (DISABLE_WDOG) */
#if (CLOCK_SETUP == 0)
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
/* Switch to FEI Mode */
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
/* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
MCG->C2 = (uint8_t)0x00u;
/* MCG_C4: DMX32=0,DRST_DRS=1 */
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
/* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
MCG->C5 = (uint8_t)0x00u;
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00u;
while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */
while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */
#elif (CLOCK_SETUP == 1)
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV4=3 Set Prescalers 96MHz cpu, 48MHz bus, 24MHz flash*/
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3);
/* SIM->CLKDIV2: USBDIV=2, Divide 96MHz system clock for USB 48MHz */
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(1);
/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
/* Switch to FBE Mode */
/* MCG->C7: OSCSEL=0 */
MCG->C7 = (uint8_t)0x00u;
/* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
//MCG->C2 = (uint8_t)0x24u;
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
/* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
/* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
MCG->C5 = MCG_C5_PRDIV0(7);
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00u;
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
/* Switch to PBE Mode */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
MCG->C5 = MCG_C5_PRDIV0(3); // config PLL input for 16 MHz Crystal / 4 = 4 MHz
/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0);// config PLL for 96 MHz output
while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
/* Switch to PEE Mode */
/* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
#elif (CLOCK_SETUP == 2)
/* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 36MHz bus, 24MHz flash*/
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(2);
/* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */
SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK;
/* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
/* Switch to FBE Mode */
/* MCG->C7: OSCSEL=0 */
MCG->C7 = (uint8_t)0x00u;
/* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
//MCG->C2 = (uint8_t)0x24u;
/* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
/* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
/* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
MCG->C5 = MCG_C5_PRDIV0(7);
/* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
MCG->C6 = (uint8_t)0x00u;
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
/* Switch to PBE Mode */
/* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
MCG->C5 = MCG_C5_PRDIV0(5);
/* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
/* Switch to PEE Mode */
/* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
#endif /* (CLOCK_SETUP) */
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint8_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* Output of FLL or PLL is selected */
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
/* FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
} /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
} else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
MCGOUTClock *= 640u;
break;
case 0x20u:
MCGOUTClock *= 1280u;
break;
case 0x40u:
MCGOUTClock *= 1920u;
break;
case 0x60u:
MCGOUTClock *= 2560u;
break;
case 0x80u:
MCGOUTClock *= 732u;
break;
case 0xA0u:
MCGOUTClock *= 1464u;
break;
case 0xC0u:
MCGOUTClock *= 2197u;
break;
case 0xE0u:
MCGOUTClock *= 2929u;
break;
default:
break;
}
} else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
/* PLL is selected */
Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
MCGOUTClock *= Divider; /* Calculate the MCG output clock */
} /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
/* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
} /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */
if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
} /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
} else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
/* Reserved value */
return;
} /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
}

85
targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/device/system_MK20DX256.h
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/*
** ###################################################################
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
**
**
** Version: rev. 2.0, 2012-03-19
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2011-12-15)
** Initial version
** - rev. 2.0 (2012-03-19)
** PDB Peripheral register structure updated.
** DMA Registers and bits for unsupported DMA channels removed.
**
** ###################################################################
*/
/**
* @file MK20DX256
* @version 2.0
* @date 2012-03-19
* @brief Device specific configuration file for MK20DX256 (header file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef SYSTEM_MK20DX256_H_
#define SYSTEM_MK20DX256_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* #if !defined(SYSTEM_MK20DX256_H_) */

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targets/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/us_ticker.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#include "clk_freqs.h"
static int us_ticker_inited = 0;
void us_ticker_init(void) {
if (us_ticker_inited)
return;
us_ticker_inited = 1;
SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
PIT->MCR = 0; // Enable PIT
//Timer on PIT0+1, ticker on PIT 2+3
//Init timer
PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;
PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK | PIT_TCTRL_TEN_MASK; // Start timer 1, chained to timer 0
// Use channel 0 as a prescaler for channel 1
uint32_t ldval = (bus_frequency() + 500000) / 1000000 - 1;
PIT->CHANNEL[0].LDVAL = ldval;
PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer
//Init ticker
PIT->CHANNEL[2].LDVAL = ldval;
PIT->CHANNEL[2].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 2 as prescaler
NVIC_SetVector(PIT3_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(PIT3_IRQn);
}
/******************************************************************************
* Timer for us timing.
******************************************************************************/
uint32_t us_ticker_read() {
if (!us_ticker_inited)
us_ticker_init();
return ~(PIT->CHANNEL[1].CVAL);
}
/******************************************************************************
* Ticker Event
******************************************************************************/
void us_ticker_disable_interrupt(void) {
PIT->CHANNEL[3].TCTRL &= ~PIT_TCTRL_TIE_MASK;
}
void us_ticker_clear_interrupt(void) {
PIT->CHANNEL[3].TFLG = 1;
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
uint32_t delta = timestamp - us_ticker_read();
PIT->CHANNEL[3].TCTRL = 0;
PIT->CHANNEL[3].LDVAL = delta;
PIT->CHANNEL[3].TCTRL = PIT_TCTRL_TIE_MASK | PIT_TCTRL_TEN_MASK | PIT_TCTRL_CHN_MASK;
}
void us_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(PIT3_IRQn);
}
void us_ticker_free(void)
{
}

113
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
OSC32KCLK = 0,
} RTCName;
typedef enum {
LPUART_0 = 0,
LPUART_1 = 1,
LPUART_2 = 2,
LPUART_3 = 3,
LPUART_4 = 4,
} UARTName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART LPUART_0
/* LPTMR interrupt is defined differently in K82F */
#define LPTMR0_IRQn LPTMR0_LPTMR1_IRQn
typedef enum {
I2C_0 = 0,
I2C_1 = 1,
I2C_2 = 2,
I2C_3 = 3,
} I2CName;
#define TPM_SHIFT 8
typedef enum {
PWM_1 = (0 << TPM_SHIFT) | (0), // FTM0 CH0
PWM_2 = (0 << TPM_SHIFT) | (1), // FTM0 CH1
PWM_3 = (0 << TPM_SHIFT) | (2), // FTM0 CH2
PWM_4 = (0 << TPM_SHIFT) | (3), // FTM0 CH3
PWM_5 = (0 << TPM_SHIFT) | (4), // FTM0 CH4
PWM_6 = (0 << TPM_SHIFT) | (5), // FTM0 CH5
PWM_7 = (0 << TPM_SHIFT) | (6), // FTM0 CH6
PWM_8 = (0 << TPM_SHIFT) | (7), // FTM0 CH7
PWM_9 = (1 << TPM_SHIFT) | (0), // FTM1 CH0
PWM_10 = (1 << TPM_SHIFT) | (1), // FTM1 CH1
PWM_11 = (2 << TPM_SHIFT) | (0), // FTM2 CH0
PWM_12 = (2 << TPM_SHIFT) | (1), // FTM2 CH1
PWM_13 = (3 << TPM_SHIFT) | (0), // FTM3 CH0
PWM_14 = (3 << TPM_SHIFT) | (1), // FTM3 CH1
PWM_15 = (3 << TPM_SHIFT) | (2), // FTM3 CH2
PWM_16 = (3 << TPM_SHIFT) | (3), // FTM3 CH3
PWM_17 = (3 << TPM_SHIFT) | (4), // FTM3 CH4
PWM_18 = (3 << TPM_SHIFT) | (5), // FTM3 CH5
PWM_19 = (3 << TPM_SHIFT) | (6), // FTM3 CH6
PWM_20 = (3 << TPM_SHIFT) | (7), // FTM3 CH7
} PWMName;
#define ADC_INSTANCE_SHIFT 8
#define ADC_B_CHANNEL_SHIFT 5
typedef enum {
ADC0_SE4a = (0 << ADC_INSTANCE_SHIFT) | 4,
ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
ADC0_SE5a = (0 << ADC_INSTANCE_SHIFT) | 5,
ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
ADC0_SE6a = (0 << ADC_INSTANCE_SHIFT) | 6,
ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
ADC0_SE7a = (0 << ADC_INSTANCE_SHIFT) | 7,
ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
ADC0_SE10 = (0 << ADC_INSTANCE_SHIFT) | 10,
ADC0_SE11 = (0 << ADC_INSTANCE_SHIFT) | 11,
ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22,
ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23,
} ADCName;
typedef enum {
DAC_0 = 0
} DACName;
typedef enum {
SPI_0 = 0,
SPI_1 = 1,
SPI_2 = 2,
} SPIName;
#ifdef __cplusplus
}
#endif
#endif

267
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************RTC***************/
const PinMap PinMap_RTC[] = {
{NC, OSC32KCLK, 0},
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PTE16, ADC0_SE4a, 0},
{PTE17, ADC0_SE5a, 0},
{PTE18, ADC0_SE6a, 0},
{PTE19, ADC0_SE7a, 0},
{PTB0, ADC0_SE8, 0},
{PTB1, ADC0_SE9, 0},
{PTA7, ADC0_SE10, 0},
{PTA8, ADC0_SE11, 0},
{PTB2, ADC0_SE12, 0},
{PTB3, ADC0_SE13, 0},
{PTC0, ADC0_SE14, 0},
{PTC1, ADC0_SE15, 0},
{PTC2, ADC0_SE4b, 0},
{PTD1, ADC0_SE5b, 0},
{PTD5, ADC0_SE6b, 0},
{PTD6, ADC0_SE7b, 0},
{NC , NC , 0}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{DAC0_OUT, DAC_0, 0},
{NC , NC , 0}
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{PTE0, I2C_1, 6},
{PTE10, I2C_3, 2},
{PTE18, I2C_0, 4},
{PTA21, I2C_0, 2},
{PTA1, I2C_3, 4},
{PTA7, I2C_2, 2},
{PTA10, I2C_2, 2},
{PTB1, I2C_0, 2},
{PTB3, I2C_0, 2},
{PTB11, I2C_2, 4},
{PTC11, I2C_1, 2},
{PTD3, I2C_0, 7},
{PTD9, I2C_0, 2},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PTE1, I2C_1, 6},
{PTE11, I2C_3, 2},
{PTE19, I2C_0, 4},
{PTA20, I2C_0, 2},
{PTA2, I2C_3, 4},
{PTA6, I2C_2, 2},
{PTA11, I2C_2, 2},
{PTB0, I2C_0, 2},
{PTB2, I2C_0, 2},
{PTB10, I2C_2, 4},
{PTC10, I2C_1, 2},
{PTD2, I2C_0, 7},
{PTD8, I2C_0, 2},
{NC , NC , 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{PTE0, LPUART_1, 3},
{PTE4, LPUART_3, 3},
{PTE12, LPUART_2, 3},
{PTE16, LPUART_2, 3},
{PTA20, LPUART_4, 3},
{PTA2, LPUART_0, 2},
{PTA14, LPUART_0, 3},
{PTB11, LPUART_3, 3},
{PTB17, LPUART_0, 3},
{PTC4, LPUART_1, 3},
{PTC15, LPUART_4, 3},
{PTC17, LPUART_3, 3},
{PTD3, LPUART_2, 3},
{PTD7, LPUART_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{PTE1, LPUART_1, 3},
{PTE5, LPUART_3, 3},
{PTE13, LPUART_2, 3},
{PTE17, LPUART_2, 3},
{PTA21, LPUART_4, 3},
{PTA1, LPUART_0, 2},
{PTA15, LPUART_0, 3},
{PTB10, LPUART_3, 3},
{PTB16, LPUART_0, 3},
{PTC3, LPUART_1, 3},
{PTC14, LPUART_4, 3},
{PTC16, LPUART_3, 3},
{PTD2, LPUART_2, 3},
{PTD6, LPUART_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_CTS[] = {
{PTE2, LPUART_1, 3},
{PTE6, LPUART_3, 3},
{PTE18, LPUART_2, 3},
{PTA0, LPUART_0, 2},
{PTA16, LPUART_0, 3},
{PTB3, LPUART_0, 3},
{PTB9, LPUART_3, 3},
{PTC2, LPUART_1, 3},
{PTC13, LPUART_4, 3},
{PTC19, LPUART_3, 3},
{PTD1, LPUART_2, 3},
{PTD5, LPUART_0, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RTS[] = {
{PTE3, LPUART_1, 3},
{PTE7, LPUART_3, 3},
{PTE19, LPUART_2, 3},
{PTA3, LPUART_0, 2},
{PTA17, LPUART_0, 3},
{PTB2, LPUART_0, 3},
{PTB8, LPUART_3, 3},
{PTC1, LPUART_1, 3},
{PTC12, LPUART_4, 3},
{PTC18, LPUART_3, 3},
{PTD0, LPUART_2, 3},
{PTD4, LPUART_0, 3},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{PTE1, SPI_1, 2},
{PTE2, SPI_1, 7},
{PTE7, SPI_2, 2},
{PTE17, SPI_0, 2},
{PTA15, SPI_0, 2},
{PTB11, SPI_1, 2},
{PTB21, SPI_2, 2},
{PTC5, SPI_0, 2},
{PTD1, SPI_0, 2},
{PTD5, SPI_1, 7},
{PTD12, SPI_2, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{PTE2, SPI_1, 2},
{PTE3, SPI_1, 7},
{PTE8, SPI_2, 3},
{PTE18, SPI_0, 2},
{PTA16, SPI_0, 2},
{PTB16, SPI_1, 2},
{PTB16, SPI_1, 2},
{PTB22, SPI_2, 2},
{PTC6, SPI_0, 2},
{PTD2, SPI_0, 2},
{PTD6, SPI_1, 7},
{PTD13, SPI_2, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PTE1, SPI_1, 7},
{PTE4, SPI_1, 2},
{PTE10, SPI_2, 3},
{PTE19, SPI_0, 2},
{PTA17, SPI_0, 2},
{PTB17, SPI_1, 2},
{PTB23, SPI_2, 2},
{PTC7, SPI_0, 2},
{PTD3, SPI_0, 2},
{PTD7, SPI_1, 7},
{PTD14, SPI_2, 2},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PTE5, SPI_1, 2},
{PTE11, SPI_2, 3},
{PTE16, SPI_0, 2},
{PTA14, SPI_0, 2},
{PTB10, SPI_1, 2},
{PTB20, SPI_2, 2},
{PTC4, SPI_0, 2},
{PTD0, SPI_0, 2},
{PTD4, SPI_1, 7},
{PTD11, SPI_2, 2},
{NC , NC , 0}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
/* FTM 0 */
{PTA0, PWM_6, 3},
{PTA1, PWM_7, 3},
{PTA2, PWM_8, 3},
{PTA3, PWM_1, 3},
{PTA4, PWM_2, 3},
{PTA5, PWM_3, 3},
{PTA6, PWM_4, 3},
{PTA7, PWM_5, 3},
{PTC1, PWM_1, 4},
{PTC2, PWM_2, 4},
{PTC3, PWM_3, 4},
{PTC4, PWM_4, 4},
{PTC5, PWM_3, 7},
{PTD4, PWM_5, 4},
{PTD5, PWM_6, 4},
{PTD6, PWM_7, 4},
{PTD7, PWM_8, 4},
/* FTM 1 */
{PTA8, PWM_9, 3},
{PTA9, PWM_10, 3},
{PTA12, PWM_9, 3},
{PTA13, PWM_10, 3},
{PTB0, PWM_9, 3},
{PTB1, PWM_10, 3},
/* FTM 2 */
{PTA10, PWM_11, 3},
{PTA11, PWM_12, 3},
{PTB18, PWM_11, 3},
{PTB19, PWM_12, 3},
/* FTM 3 */
{PTE5, PWM_13, 6},
{PTE6, PWM_14, 6},
{PTE7, PWM_15, 6},
{PTE8, PWM_16, 6},
{PTE9, PWM_17, 6},
{PTE10, PWM_18, 6},
{PTE11, PWM_19, 6},
{PTE12, PWM_20, 6},
{PTC8, PWM_17, 3},
{PTC9, PWM_18, 3},
{PTC10, PWM_19, 3},
{PTC11, PWM_20, 3},
{PTD0, PWM_13, 4},
{PTD1, PWM_14, 4},
{PTD2, PWM_15, 4},
{PTD3, PWM_16, 4},
{NC , NC , 0}
};

180
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define GPIO_PORT_SHIFT 12
typedef enum {
PTA0 = (0 << GPIO_PORT_SHIFT | 0),
PTA1 = (0 << GPIO_PORT_SHIFT | 1),
PTA2 = (0 << GPIO_PORT_SHIFT | 2),
PTA3 = (0 << GPIO_PORT_SHIFT | 3),
PTA4 = (0 << GPIO_PORT_SHIFT | 4),
PTA5 = (0 << GPIO_PORT_SHIFT | 5),
PTA6 = (0 << GPIO_PORT_SHIFT | 6),
PTA7 = (0 << GPIO_PORT_SHIFT | 7),
PTA8 = (0 << GPIO_PORT_SHIFT | 8),
PTA9 = (0 << GPIO_PORT_SHIFT | 9),
PTA10 = (0 << GPIO_PORT_SHIFT | 10),
PTA11 = (0 << GPIO_PORT_SHIFT | 11),
PTA12 = (0 << GPIO_PORT_SHIFT | 12),
PTA13 = (0 << GPIO_PORT_SHIFT | 13),
PTA14 = (0 << GPIO_PORT_SHIFT | 14),
PTA15 = (0 << GPIO_PORT_SHIFT | 15),
PTA16 = (0 << GPIO_PORT_SHIFT | 16),
PTA17 = (0 << GPIO_PORT_SHIFT | 17),
PTA18 = (0 << GPIO_PORT_SHIFT | 18),
PTA19 = (0 << GPIO_PORT_SHIFT | 19),
PTA20 = (0 << GPIO_PORT_SHIFT | 20),
PTA21 = (0 << GPIO_PORT_SHIFT | 21),
PTB0 = (1 << GPIO_PORT_SHIFT | 0),
PTB1 = (1 << GPIO_PORT_SHIFT | 1),
PTB2 = (1 << GPIO_PORT_SHIFT | 2),
PTB3 = (1 << GPIO_PORT_SHIFT | 3),
PTB8 = (1 << GPIO_PORT_SHIFT | 8),
PTB9 = (1 << GPIO_PORT_SHIFT | 9),
PTB10 = (1 << GPIO_PORT_SHIFT | 10),
PTB11 = (1 << GPIO_PORT_SHIFT | 11),
PTB16 = (1 << GPIO_PORT_SHIFT | 16),
PTB17 = (1 << GPIO_PORT_SHIFT | 17),
PTB18 = (1 << GPIO_PORT_SHIFT | 18),
PTB19 = (1 << GPIO_PORT_SHIFT | 19),
PTB20 = (1 << GPIO_PORT_SHIFT | 20),
PTB21 = (1 << GPIO_PORT_SHIFT | 21),
PTB22 = (1 << GPIO_PORT_SHIFT | 22),
PTB23 = (1 << GPIO_PORT_SHIFT | 23),
PTC0 = (2 << GPIO_PORT_SHIFT | 0),
PTC1 = (2 << GPIO_PORT_SHIFT | 1),
PTC2 = (2 << GPIO_PORT_SHIFT | 2),
PTC3 = (2 << GPIO_PORT_SHIFT | 3),
PTC4 = (2 << GPIO_PORT_SHIFT | 4),
PTC5 = (2 << GPIO_PORT_SHIFT | 5),
PTC6 = (2 << GPIO_PORT_SHIFT | 6),
PTC7 = (2 << GPIO_PORT_SHIFT | 7),
PTC8 = (2 << GPIO_PORT_SHIFT | 8),
PTC9 = (2 << GPIO_PORT_SHIFT | 9),
PTC10 = (2 << GPIO_PORT_SHIFT | 10),
PTC11 = (2 << GPIO_PORT_SHIFT | 11),
PTC12 = (2 << GPIO_PORT_SHIFT | 12),
PTC13 = (2 << GPIO_PORT_SHIFT | 13),
PTC14 = (2 << GPIO_PORT_SHIFT | 14),
PTC15 = (2 << GPIO_PORT_SHIFT | 15),
PTC16 = (2 << GPIO_PORT_SHIFT | 16),
PTC17 = (2 << GPIO_PORT_SHIFT | 17),
PTC18 = (2 << GPIO_PORT_SHIFT | 18),
PTC19 = (2 << GPIO_PORT_SHIFT | 19),
PTD0 = (3 << GPIO_PORT_SHIFT | 0),
PTD1 = (3 << GPIO_PORT_SHIFT | 1),
PTD2 = (3 << GPIO_PORT_SHIFT | 2),
PTD3 = (3 << GPIO_PORT_SHIFT | 3),
PTD4 = (3 << GPIO_PORT_SHIFT | 4),
PTD5 = (3 << GPIO_PORT_SHIFT | 5),
PTD6 = (3 << GPIO_PORT_SHIFT | 6),
PTD7 = (3 << GPIO_PORT_SHIFT | 7),
PTD8 = (3 << GPIO_PORT_SHIFT | 8),
PTD9 = (3 << GPIO_PORT_SHIFT | 9),
PTD11 = (3 << GPIO_PORT_SHIFT | 11),
PTD12 = (3 << GPIO_PORT_SHIFT | 12),
PTD13 = (3 << GPIO_PORT_SHIFT | 13),
PTD14 = (3 << GPIO_PORT_SHIFT | 14),
PTE0 = (4 << GPIO_PORT_SHIFT | 0),
PTE1 = (4 << GPIO_PORT_SHIFT | 1),
PTE2 = (4 << GPIO_PORT_SHIFT | 2),
PTE3 = (4 << GPIO_PORT_SHIFT | 3),
PTE4 = (4 << GPIO_PORT_SHIFT | 4),
PTE5 = (4 << GPIO_PORT_SHIFT | 5),
PTE6 = (4 << GPIO_PORT_SHIFT | 6),
PTE7 = (4 << GPIO_PORT_SHIFT | 7),
PTE8 = (4 << GPIO_PORT_SHIFT | 8),
PTE9 = (4 << GPIO_PORT_SHIFT | 9),
PTE10 = (4 << GPIO_PORT_SHIFT | 10),
PTE11 = (4 << GPIO_PORT_SHIFT | 11),
PTE12 = (4 << GPIO_PORT_SHIFT | 12),
PTE13 = (4 << GPIO_PORT_SHIFT | 13),
PTE16 = (4 << GPIO_PORT_SHIFT | 16),
PTE17 = (4 << GPIO_PORT_SHIFT | 17),
PTE18 = (4 << GPIO_PORT_SHIFT | 18),
PTE19 = (4 << GPIO_PORT_SHIFT | 19),
LED_RED = PTD4,
LED_RGB = PTA14,
// mbed original LED naming
LED1 = LED_RED,
LED2 = LED_RED,
LED3 = LED_RED,
LED4 = LED_RED,
//Push buttons
SW0 = PTD0,
// Console Pins
USBTX = PTA2,
USBRX = PTA1,
// GSM modem Pins
GSM_UART_TX = PTC15,
GSM_UART_RX = PTC14,
GSM_UART_CMD_TX = PTC4,
GSM_UART_CMD_RX = PTC3,
GSM_POWER = PTD7,
GSM_STATUS = PTE6,
GSM_PWRKEY = PTE8,
GSM_RI = PTE9,
GSM_DCD = PTE10,
I2C_SCL = PTB10,
I2C_SDA = PTB11,
SDHC_D0 = PTE1,
SDHC_D1 = PTE0,
SDHC_D2 = PTE5,
SDHC_D3 = PTE4,
SDHC_DCLK = PTE2,
SDHC_CMD = PTE3,
SHDC_DETECT = PTE7,
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
// Not connected
NC = (int) 0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/device.h
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 24
#include "objects.h"
#endif

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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.c
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/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* How to setup clock using clock driver functions:
*
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
* and flash clock are in allowed range during clock mode switch.
*
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
*
* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
* internal reference clock(MCGIRCLK). Follow the steps to setup:
*
* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
*
* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
* explicitly to setup MCGIRCLK.
*
* 3). Don't need to configure FLL explicitly, because if target mode is FLL
* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
* if the target mode is not FLL mode, the FLL is disabled.
*
* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
*
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
*/
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
!!ClocksProfile
product: Clocks v1.0
processor: MK82FN256xxx15
package_id: MK82FN256VLL15
mcu_data: ksdk2_0
processor_version: 1.0.1
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
#include "fsl_smc.h"
#include "fsl_rtc.h"
#include "fsl_clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
#define RTC_OSC_CAP_LOAD_0PF 0x0U /*!< RTC oscillator capacity load: 0pF */
#define RTC_RTC32KCLK_PERIPHERALS_ENABLED 1U /*!< RTC32KCLK to other peripherals: enabled */
#define SIM_FLEXIO_CLK_SEL_CORE_SYSTEM_CLK 0U /*!< FLEXIO clock select: Core/system clock */
#define SIM_FLEXIO_CLK_SEL_MCGIRCLK_CLK 3U /*!< FLEXIO clock select: MCGIRCLK clock */
#define SIM_LPUART_CLK_SEL_MCGIRCLK_CLK 3U /*!< LPUART clock select: MCGIRCLK clock */
#define SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK 1U /*!< LPUART clock select: PLLFLLSEL output clock */
#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_CONFIG_SetRtcClock
* Description : This function is used to configuring RTC clock including
* enabling RTC oscillator.
* Param capLoad : RTC oscillator capacity load
* Param enableOutPeriph : Enable (1U)/Disable (0U) clock to peripherals
*
*END**************************************************************************/
static void CLOCK_CONFIG_SetRtcClock(uint32_t capLoad, uint8_t enableOutPeriph)
{
/* RTC clock gate enable */
CLOCK_EnableClock(kCLOCK_Rtc0);
if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the Rtc oscillator is not already enabled */
/* Set the specified capacitor configuration for the RTC oscillator */
RTC_SetOscCapLoad(RTC, capLoad);
/* Enable the RTC 32KHz oscillator */
RTC->CR |= RTC_CR_OSCE_MASK;
}
/* Output to other peripherals */
if (enableOutPeriph) {
RTC->CR &= ~RTC_CR_CLKO_MASK;
}
else {
RTC->CR |= RTC_CR_CLKO_MASK;
}
/* Set the XTAL32/RTC_CLKIN frequency based on board setting. */
CLOCK_SetXtal32Freq(BOARD_XTAL32K_CLK_HZ);
/* Set RTC_TSR if there is fault value in RTC */
if (RTC->SR & RTC_SR_TIF_MASK) {
RTC -> TSR = RTC -> TSR;
}
/* RTC clock gate disable */
CLOCK_DisableClock(kCLOCK_Rtc0);
}
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_CONFIG_SetFllExtRefDiv
* Description : Configure FLL external reference divider (FRDIV).
* Param frdiv : The value to set FRDIV.
*
*END**************************************************************************/
static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
{
MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
}
/*******************************************************************************
********************* Configuration BOARD_BootClockHSRUN **********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
!!Configuration
name: BOARD_BootClockHSRUN
outputs:
- {id: Bus_clock.outFreq, value: 75 MHz}
- {id: Core_clock.outFreq, value: 150 MHz}
- {id: ERCLK32K.outFreq, value: 32.768 kHz}
- {id: FLEXIOCLK.outFreq, value: 150 MHz}
- {id: Flash_clock.outFreq, value: 25 MHz}
- {id: FlexBus_clock.outFreq, value: 75 MHz}
- {id: IRC48MCLK.outFreq, value: 48 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: LPUARTCLK.outFreq, value: 75 MHz}
- {id: MCGFFCLK.outFreq, value: 1.5 MHz}
- {id: MCGIRCLK.outFreq, value: 2 MHz}
- {id: MCGPLLCLK.outFreq, value: 150 MHz}
- {id: MCGPLLCLK2X.outFreq, value: 300 MHz}
- {id: PLLFLLCLK.outFreq, value: 150 MHz}
- {id: System_clock.outFreq, value: 150 MHz}
settings:
- {id: MCGMode, value: PEE}
- {id: powerMode, value: HSRUN}
- {id: FLEXIOClkConfig, value: 'yes'}
- {id: LPUARTClkConfig, value: 'yes'}
- {id: MCG.FLL_mul.scale, value: '2929', locked: true}
- {id: MCG.FRDIV.scale, value: '32', locked: true}
- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
- {id: MCG.IREFS.sel, value: MCG.FRDIV}
- {id: MCG.OSCSEL.sel, value: SIM.IRC48MCLK}
- {id: MCG.OSCSEL_PLL.sel, value: SIM.IRC48MCLK}
- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
- {id: MCG.PRDIV.scale, value: '4', locked: true}
- {id: MCG.VDIV.scale, value: '25', locked: true}
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
- {id: MCG_C2_RANGE0_CFG, value: Very_high}
- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
- {id: MCG_C5_PLLCLKEN0_CFG, value: Enabled}
- {id: RTC_CR_OSCE_CFG, value: Enabled}
- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLDIV}
- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
- {id: SIM.OUTDIV2.scale, value: '2'}
- {id: SIM.OUTDIV4.scale, value: '6'}
- {id: SIM.PLLFLLDIV.scale, value: '2', locked: true}
- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
- {id: SIM.USBDIV.scale, value: '1', locked: true}
- {id: SIM.USBFRAC.scale, value: '1', locked: true}
sources:
- {id: IRC48M.IRC48M.outFreq, value: 48 MHz}
- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
/*******************************************************************************
* Variables for BOARD_BootClockHSRUN configuration
******************************************************************************/
const mcg_config_t mcgConfig_BOARD_BootClockHSRUN =
{
.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
.fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
.drs = kMCG_DrsHigh, /* High frequency range */
.dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
.oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */
.pll0Config =
{
.enableMode = kMCG_PllEnableIndependent,/* MCGPLLCLK enabled independent of MCG clock mode, MCGPLLCLK disabled in STOP mode */
.prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
.vdiv = 0x9U, /* VCO divider: multiplied by 25 */
},
};
const sim_clock_config_t simConfig_BOARD_BootClockHSRUN =
{
.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
.pllFllDiv = 1, /* PLLFLLSEL clock divider divisor: divided by 2 */
.pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
.clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
};
const osc_config_t oscConfig_BOARD_BootClockHSRUN =
{
.freq = 0U, /* Oscillator frequency: 0Hz */
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
.workMode = kOSC_ModeExt, /* Use external clock */
.oscerConfig =
{
.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
}
};
/*******************************************************************************
* Code for BOARD_BootClockHSRUN configuration
******************************************************************************/
void BOARD_BootClockHSRUN(void)
{
/* Set HSRUN power mode */
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
SMC_SetPowerModeHsrun(SMC);
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
{
}
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
/* Configure RTC clock including enabling RTC oscillator. */
CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED);
/* Configure the Internal Reference clock (MCGIRCLK). */
CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode,
mcgConfig_BOARD_BootClockHSRUN.ircs,
mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
/* Configure FLL external reference divider (FRDIV). */
CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
/* Set MCG to PEE mode. */
CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel,
kMCG_PllClkSelPll0,
&mcgConfig_BOARD_BootClockHSRUN.pll0Config);
/* Set the clock configuration in SIM module. */
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
/* Set LPUART clock source. */
CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK);
/* Set FLEXIO clock source. */
CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_CORE_SYSTEM_CLK);
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
!!Configuration
name: BOARD_BootClockRUN
outputs:
- {id: Bus_clock.outFreq, value: 60 MHz}
- {id: Core_clock.outFreq, value: 120 MHz}
- {id: ERCLK32K.outFreq, value: 32.768 kHz}
- {id: FLEXIOCLK.outFreq, value: 120 MHz}
- {id: Flash_clock.outFreq, value: 20 MHz}
- {id: FlexBus_clock.outFreq, value: 60 MHz}
- {id: IRC48MCLK.outFreq, value: 48 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: LPUARTCLK.outFreq, value: 60 MHz}
- {id: MCGFFCLK.outFreq, value: 1.5 MHz}
- {id: MCGIRCLK.outFreq, value: 2 MHz}
- {id: MCGPLLCLK.outFreq, value: 120 MHz}
- {id: MCGPLLCLK2X.outFreq, value: 240 MHz}
- {id: PLLFLLCLK.outFreq, value: 120 MHz}
- {id: System_clock.outFreq, value: 120 MHz}
settings:
- {id: MCGMode, value: PEE}
- {id: FLEXIOClkConfig, value: 'yes'}
- {id: LPUARTClkConfig, value: 'yes'}
- {id: MCG.FLL_mul.scale, value: '2929', locked: true}
- {id: MCG.FRDIV.scale, value: '32', locked: true}
- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
- {id: MCG.IREFS.sel, value: MCG.FRDIV}
- {id: MCG.OSCSEL.sel, value: SIM.IRC48MCLK}
- {id: MCG.OSCSEL_PLL.sel, value: SIM.IRC48MCLK}
- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
- {id: MCG.PRDIV.scale, value: '4', locked: true}
- {id: MCG.VDIV.scale, value: '20', locked: true}
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
- {id: MCG_C2_RANGE0_CFG, value: Very_high}
- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
- {id: MCG_C5_PLLCLKEN0_CFG, value: Enabled}
- {id: RTC_CR_OSCE_CFG, value: Enabled}
- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLDIV}
- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
- {id: SIM.OUTDIV2.scale, value: '2'}
- {id: SIM.OUTDIV4.scale, value: '6'}
- {id: SIM.PLLFLLDIV.scale, value: '2', locked: true}
- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
- {id: SIM.USBDIV.scale, value: '1', locked: true}
- {id: SIM.USBFRAC.scale, value: '1', locked: true}
sources:
- {id: IRC48M.IRC48M.outFreq, value: 48 MHz}
- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const mcg_config_t mcgConfig_BOARD_BootClockRUN =
{
.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
.fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
.drs = kMCG_DrsHigh, /* High frequency range */
.dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
.oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */
.pll0Config =
{
.enableMode = kMCG_PllEnableIndependent,/* MCGPLLCLK enabled independent of MCG clock mode, MCGPLLCLK disabled in STOP mode */
.prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
.vdiv = 0x4U, /* VCO divider: multiplied by 20 */
},
};
const sim_clock_config_t simConfig_BOARD_BootClockRUN =
{
.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
.pllFllDiv = 1, /* PLLFLLSEL clock divider divisor: divided by 2 */
.pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
.clkdiv1 = 0x1150000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
};
const osc_config_t oscConfig_BOARD_BootClockRUN =
{
.freq = 0U, /* Oscillator frequency: 0Hz */
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
.workMode = kOSC_ModeExt, /* Use external clock */
.oscerConfig =
{
.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
}
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
/* Configure RTC clock including enabling RTC oscillator. */
CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED);
/* Configure the Internal Reference clock (MCGIRCLK). */
CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
mcgConfig_BOARD_BootClockRUN.ircs,
mcgConfig_BOARD_BootClockRUN.fcrdiv);
/* Configure FLL external reference divider (FRDIV). */
CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
/* Set MCG to PEE mode. */
CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
kMCG_PllClkSelPll0,
&mcgConfig_BOARD_BootClockRUN.pll0Config);
/* Set the clock configuration in SIM module. */
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
/* Set LPUART clock source. */
CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK);
/* Set FLEXIO clock source. */
CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_CORE_SYSTEM_CLK);
}
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
!!Configuration
name: BOARD_BootClockVLPR
outputs:
- {id: Bus_clock.outFreq, value: 4 MHz}
- {id: Core_clock.outFreq, value: 4 MHz}
- {id: ERCLK32K.outFreq, value: 32.768 kHz}
- {id: FLEXIOCLK.outFreq, value: 4 MHz}
- {id: Flash_clock.outFreq, value: 800 kHz}
- {id: FlexBus_clock.outFreq, value: 4 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: LPUARTCLK.outFreq, value: 4 MHz}
- {id: MCGIRCLK.outFreq, value: 4 MHz}
- {id: System_clock.outFreq, value: 4 MHz}
settings:
- {id: MCGMode, value: BLPI}
- {id: powerMode, value: VLPR}
- {id: FLEXIOClkConfig, value: 'yes'}
- {id: LPUARTClkConfig, value: 'yes'}
- {id: MCG.CLKS.sel, value: MCG.IRCS}
- {id: MCG.FCRDIV.scale, value: '1'}
- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
- {id: RTC_CR_OSCE_CFG, value: Enabled}
- {id: SIM.FLEXIOSRCSEL.sel, value: MCG.MCGIRCLK}
- {id: SIM.LPUARTSRCSEL.sel, value: MCG.MCGIRCLK}
- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
- {id: SIM.OUTDIV3.scale, value: '1'}
- {id: SIM.OUTDIV4.scale, value: '5'}
sources:
- {id: RTC.RTC32kHz.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
/*******************************************************************************
* Variables for BOARD_BootClockVLPR configuration
******************************************************************************/
const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
{
.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
.drs = kMCG_DrsLow, /* Low frequency range */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
.pll0Config =
{
.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
.vdiv = 0x0U, /* VCO divider: multiplied by 16 */
},
};
const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
{
.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
.pllFllDiv = 0, /* PLLFLLSEL clock divider divisor: divided by 1 */
.pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
.clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
};
const osc_config_t oscConfig_BOARD_BootClockVLPR =
{
.freq = 0U, /* Oscillator frequency: 0Hz */
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
.workMode = kOSC_ModeExt, /* Use external clock */
.oscerConfig =
{
.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
}
};
/*******************************************************************************
* Code for BOARD_BootClockVLPR configuration
******************************************************************************/
void BOARD_BootClockVLPR(void)
{
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
/* Configure RTC clock including enabling RTC oscillator. */
CLOCK_CONFIG_SetRtcClock(RTC_OSC_CAP_LOAD_0PF, RTC_RTC32KCLK_PERIPHERALS_ENABLED);
/* Set MCG to BLPI mode. */
CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
mcgConfig_BOARD_BootClockVLPR.ircs,
mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
/* Set the clock configuration in SIM module. */
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
/* Set VLPR power mode. */
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
SMC_SetPowerModeVlpr(SMC, false);
#else
SMC_SetPowerModeVlpr(SMC);
#endif
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
{
}
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
/* Set LPUART clock source. */
CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_MCGIRCLK_CLK);
/* Set FLEXIO clock source. */
CLOCK_SetFlexio0Clock(SIM_FLEXIO_CLK_SEL_MCGIRCLK_CLK);
}

147
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/fsl_clock_config.h
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@ -1,147 +0,0 @@
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board RTC xtal frequency in Hz */
/*******************************************************************************
********************* Configuration BOARD_BootClockHSRUN **********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockHSRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKHSRUN_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
/*! @brief MCG set for BOARD_BootClockHSRUN configuration.
*/
extern const mcg_config_t mcgConfig_BOARD_BootClockHSRUN;
/*! @brief SIM module set for BOARD_BootClockHSRUN configuration.
*/
extern const sim_clock_config_t simConfig_BOARD_BootClockHSRUN;
/*! @brief OSC set for BOARD_BootClockHSRUN configuration.
*/
extern const osc_config_t oscConfig_BOARD_BootClockHSRUN;
/*******************************************************************************
* API for BOARD_BootClockHSRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockHSRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */
/*! @brief MCG set for BOARD_BootClockRUN configuration.
*/
extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
/*! @brief SIM module set for BOARD_BootClockRUN configuration.
*/
extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
/*! @brief OSC set for BOARD_BootClockRUN configuration.
*/
extern const osc_config_t oscConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************* Configuration BOARD_BootClockVLPR ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockVLPR configuration
******************************************************************************/
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 2000000U /*!< Core clock frequency: 2000000Hz */
/*! @brief MCG set for BOARD_BootClockVLPR configuration.
*/
extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
*/
extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
/*! @brief OSC set for BOARD_BootClockVLPR configuration.
*/
extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
/*******************************************************************************
* API for BOARD_BootClockVLPR configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockVLPR(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

85
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/TARGET_UBRIDGE/mbed_overrides.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <hal/gpio_api.h>
#include "fsl_smc.h"
#include "fsl_rcm.h"
#include "fsl_pmc.h"
#include "fsl_rtc.h"
#include "fsl_clock_config.h"
//!< this contains the wakeup source
rcm_reset_source_t kinetisResetSource;
// called before main
void mbed_sdk_init()
{
rtc_config_t rtc_basic_config;
uint32_t u32cTPR_counter = 0;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
// check the power mode source
kinetisResetSource = (rcm_reset_source_t) (RCM_GetPreviousResetSources(RCM));
// if waking up from VLLS, do some cleanup
if (kinetisResetSource & kRCM_SourceWakeup) {
PMC_ClearPeriphIOIsolationFlag(PMC);
NVIC_ClearPendingIRQ(LLWU_IRQn);
}
BOARD_BootClockRUN();
CLOCK_EnableClock(kCLOCK_Rtc0);
/* Check if the Rtc oscillator is enabled */
if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
/*Init the RTC with default configuration*/
RTC_GetDefaultConfig(&rtc_basic_config);
/* Setup the 32K RTC OSC */
RTC_Init(RTC, &rtc_basic_config);
/* Enable the RTC 32KHz oscillator */
RTC->CR |= RTC_CR_OSCE_MASK;
/* Start the RTC time counter */
RTC_StartTimer(RTC);
/* Verify TPR register reaches 4096 counts */
while (u32cTPR_counter < 4096) {
u32cTPR_counter = RTC->TPR;
}
/* 32kHz Oscillator is ready. */
RTC_Deinit(RTC);
}
CLOCK_DisableClock(kCLOCK_Rtc0);
}
// Change the NMI pin to an input. This allows NMI pin to
// be used as a low power mode wakeup. The application will
// need to change the pin back to NMI_b or wakeup only occurs once!
void NMI_Handler(void)
{
gpio_t gpio;
gpio_init_in(&gpio, PTA4);
}
// Set the UART clock source
void serial_clock_init(void)
{
CLOCK_SetLpuartClock(1U);
}

102
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
OSC32KCLK = 0,
} RTCName;
/* LPUART */
typedef enum {
LPUART_0 = 0,
LPUART_1 = 1,
LPUART_2 = 2,
} UARTName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART LPUART_0
typedef enum {
I2C_0 = 0,
I2C_1 = 1,
} I2CName;
#define TPM_SHIFT 8
typedef enum {
PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0
PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1
PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2
PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3
PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4
PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5
PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0
PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1
PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0
PWM_10 = (2 << TPM_SHIFT) | (1), // TPM2 CH1
} PWMName;
#define ADC_INSTANCE_SHIFT 8
#define ADC_B_CHANNEL_SHIFT 5
typedef enum {
ADC0_SE0 = (0 << ADC_INSTANCE_SHIFT) | 0,
ADC0_SE1 = (0 << ADC_INSTANCE_SHIFT) | 1,
ADC0_SE2 = (0 << ADC_INSTANCE_SHIFT) | 2,
ADC0_SE3 = (0 << ADC_INSTANCE_SHIFT) | 3,
ADC0_SE4a = (0 << ADC_INSTANCE_SHIFT) | 4,
ADC0_SE5a = (0 << ADC_INSTANCE_SHIFT) | 5,
ADC0_SE6a = (0 << ADC_INSTANCE_SHIFT) | 6,
ADC0_SE7a = (0 << ADC_INSTANCE_SHIFT) | 7,
ADC0_SE4b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 4,
ADC0_SE5b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 5,
ADC0_SE6b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 6,
ADC0_SE7b = (0 << ADC_INSTANCE_SHIFT) | (1 << ADC_B_CHANNEL_SHIFT) | 7,
ADC0_SE8 = (0 << ADC_INSTANCE_SHIFT) | 8,
ADC0_SE9 = (0 << ADC_INSTANCE_SHIFT) | 9,
ADC0_SE11 = (0 << ADC_INSTANCE_SHIFT) | 11,
ADC0_SE12 = (0 << ADC_INSTANCE_SHIFT) | 12,
ADC0_SE13 = (0 << ADC_INSTANCE_SHIFT) | 13,
ADC0_SE14 = (0 << ADC_INSTANCE_SHIFT) | 14,
ADC0_SE15 = (0 << ADC_INSTANCE_SHIFT) | 15,
ADC0_SE16 = (0 << ADC_INSTANCE_SHIFT) | 16,
ADC0_SE17 = (0 << ADC_INSTANCE_SHIFT) | 17,
ADC0_SE18 = (0 << ADC_INSTANCE_SHIFT) | 18,
ADC0_SE21 = (0 << ADC_INSTANCE_SHIFT) | 21,
ADC0_SE22 = (0 << ADC_INSTANCE_SHIFT) | 22,
ADC0_SE23 = (0 << ADC_INSTANCE_SHIFT) | 23,
} ADCName;
typedef enum {
SPI_0 = 0,
SPI_1 = 1,
} SPIName;
typedef enum {
DAC_0 = 0
} DACName;
#ifdef __cplusplus
}
#endif
#endif

159
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PeripheralPins.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************RTC***************/
const PinMap PinMap_RTC[] = {
{NC, OSC32KCLK, 0},
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PTB0, ADC0_SE8, 0},
{PTB1, ADC0_SE9, 0},
{PTB2, ADC0_SE12, 0},
{PTB3, ADC0_SE13, 0},
{PTC0, ADC0_SE14, 0},
{PTC1, ADC0_SE15, 0},
{PTC2, ADC0_SE4b, 0},
{PTD1, ADC0_SE5b, 0},
{PTD5, ADC0_SE6b, 0},
{PTD6, ADC0_SE7b, 0},
{NC , NC , 0}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{DAC0_OUT, DAC_0, 0},
{NC , NC , 0}
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{PTB1, I2C_0, 2},
{PTB3, I2C_0, 2},
{PTC11, I2C_1, 2},
{PTD3, I2C_0, 7},
{PTD9, I2C_0, 2},
{PTE0, I2C_1, 6},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PTB0, I2C_0, 2},
{PTB2, I2C_0, 2},
{PTC10, I2C_1, 2},
{PTD2, I2C_0, 7},
{PTD8, I2C_0, 2},
{PTE1, I2C_1, 6},
{NC , NC , 0}
};
/************LPUART***************/
const PinMap PinMap_UART_TX[] = {
{PTA2, LPUART_0, 2},
{PTA14, LPUART_0, 3},
{PTB17, LPUART_0, 3},
{PTC4, LPUART_1, 3},
{PTD3, LPUART_2, 3},
{PTD7, LPUART_0, 3},
{PTE0, LPUART_1, 3},
{NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{PTA1, LPUART_0, 2},
{PTA15, LPUART_0, 3},
{PTB16, LPUART_0, 3},
{PTC3, LPUART_1, 3},
{PTD2, LPUART_2, 3},
{PTD6, LPUART_0, 3},
{PTE1, LPUART_1, 3},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{PTE1, SPI_1, 2},
{PTE2, SPI_1, 7},
{PTA15, SPI_1, 2},
{PTB11, SPI_1, 2},
{PTC5, SPI_0, 2},
{PTD1, SPI_0, 2},
{PTD5, SPI_1, 7},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{PTE2, SPI_1, 2},
{PTE3, SPI_1, 7},
{PTA16, SPI_1, 2},
{PTB16, SPI_1, 2},
{PTC6, SPI_0, 2},
{PTD2, SPI_0, 2},
{PTD6, SPI_1, 7},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PTE1, SPI_1, 7},
{PTE4, SPI_1, 2},
{PTA17, SPI_1, 2},
{PTB17, SPI_1, 2},
{PTC7, SPI_0, 2},
{PTD3, SPI_0, 2},
{PTD7, SPI_1, 7},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PTE5, SPI_1, 2},
{PTA14, SPI_1, 2},
{PTB10, SPI_1, 2},
{PTC4, SPI_0, 2},
{PTD0, SPI_0, 2},
{PTD4, SPI_1, 7},
{NC , NC , 0}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PTA0, PWM_6, 3}, // PTA0 , TPM0 CH5
{PTA3, PWM_1, 3}, // PTA3 , TPM0 CH0
{PTA4, PWM_2 , 3}, // PTA4 , TPM0 CH1
{PTA5, PWM_3 , 3}, // PTA5 , TPM0 CH2
{PTA10, PWM_9, 3}, // PTA10, TPM2 CH0
{PTA11, PWM_10, 3}, // PTA11, TPM2 CH1
{PTA12, PWM_7 , 3}, // PTA12, TPM1 CH0
{PTA13, PWM_8 , 3}, // PTA13, TPM1 CH1
{PTB0, PWM_7, 3}, // PTB0 , TPM1 CH0
{PTB1, PWM_8, 3}, // PTB1 , TPM1 CH1
{PTB18, PWM_9, 3}, // PTB18, TPM2 CH0
{PTB19, PWM_10, 3}, // PTB18, TPM2 CH1
{PTC1, PWM_1, 4}, // PTC1 , TPM0 CH0
{PTC2, PWM_2, 4}, // PTC2 , TPM0 CH1
{PTC3, PWM_3, 4}, // PTC3 , TPM0 CH2
{PTC4, PWM_4, 4}, // PTC4 , TPM0 CH3
{PTC5, PWM_3, 7}, // PTC4 , TPM0 CH2
{PTD4, PWM_5 , 4}, // PTD4 , TPM0 CH4
{PTD5, PWM_6 , 4}, // PTD5 , TPM0 CH5
{NC , NC , 0}
};

147
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define GPIO_PORT_SHIFT 12
typedef enum {
PTA0 = (0 << GPIO_PORT_SHIFT | 0),
PTA1 = (0 << GPIO_PORT_SHIFT | 1),
PTA2 = (0 << GPIO_PORT_SHIFT | 2),
PTA3 = (0 << GPIO_PORT_SHIFT | 3),
PTA4 = (0 << GPIO_PORT_SHIFT | 4),
PTA5 = (0 << GPIO_PORT_SHIFT | 5),
PTA10 = (0 << GPIO_PORT_SHIFT | 10),
PTA11 = (0 << GPIO_PORT_SHIFT | 11),
PTA12 = (0 << GPIO_PORT_SHIFT | 12),
PTA13 = (0 << GPIO_PORT_SHIFT | 13),
PTA14 = (0 << GPIO_PORT_SHIFT | 14),
PTA15 = (0 << GPIO_PORT_SHIFT | 15),
PTA16 = (0 << GPIO_PORT_SHIFT | 16),
PTA17 = (0 << GPIO_PORT_SHIFT | 17),
PTA18 = (0 << GPIO_PORT_SHIFT | 18),
PTA19 = (0 << GPIO_PORT_SHIFT | 19),
PTB0 = (1 << GPIO_PORT_SHIFT | 0),
PTB1 = (1 << GPIO_PORT_SHIFT | 1),
PTB2 = (1 << GPIO_PORT_SHIFT | 2),
PTB3 = (1 << GPIO_PORT_SHIFT | 3),
PTB9 = (1 << GPIO_PORT_SHIFT | 9),
PTB10 = (1 << GPIO_PORT_SHIFT | 10),
PTB11 = (1 << GPIO_PORT_SHIFT | 11),
PTB16 = (1 << GPIO_PORT_SHIFT | 16),
PTB17 = (1 << GPIO_PORT_SHIFT | 17),
PTB18 = (1 << GPIO_PORT_SHIFT | 18),
PTB19 = (1 << GPIO_PORT_SHIFT | 19),
PTB20 = (1 << GPIO_PORT_SHIFT | 20),
PTB21 = (1 << GPIO_PORT_SHIFT | 21),
PTB22 = (1 << GPIO_PORT_SHIFT | 22),
PTB23 = (1 << GPIO_PORT_SHIFT | 23),
PTC0 = (2 << GPIO_PORT_SHIFT | 0),
PTC1 = (2 << GPIO_PORT_SHIFT | 1),
PTC2 = (2 << GPIO_PORT_SHIFT | 2),
PTC3 = (2 << GPIO_PORT_SHIFT | 3),
PTC4 = (2 << GPIO_PORT_SHIFT | 4),
PTC5 = (2 << GPIO_PORT_SHIFT | 5),
PTC6 = (2 << GPIO_PORT_SHIFT | 6),
PTC7 = (2 << GPIO_PORT_SHIFT | 7),
PTC8 = (2 << GPIO_PORT_SHIFT | 8),
PTC9 = (2 << GPIO_PORT_SHIFT | 9),
PTC10 = (2 << GPIO_PORT_SHIFT | 10),
PTC11 = (2 << GPIO_PORT_SHIFT | 11),
PTC12 = (2 << GPIO_PORT_SHIFT | 12),
PTC13 = (2 << GPIO_PORT_SHIFT | 13),
PTC14 = (2 << GPIO_PORT_SHIFT | 14),
PTC15 = (2 << GPIO_PORT_SHIFT | 15),
PTC17 = (2 << GPIO_PORT_SHIFT | 17),
PTD0 = (3 << GPIO_PORT_SHIFT | 0),
PTD1 = (3 << GPIO_PORT_SHIFT | 1),
PTD2 = (3 << GPIO_PORT_SHIFT | 2),
PTD3 = (3 << GPIO_PORT_SHIFT | 3),
PTD4 = (3 << GPIO_PORT_SHIFT | 4),
PTD5 = (3 << GPIO_PORT_SHIFT | 5),
PTD6 = (3 << GPIO_PORT_SHIFT | 6),
PTD7 = (3 << GPIO_PORT_SHIFT | 7),
PTD8 = (3 << GPIO_PORT_SHIFT | 8),
PTD9 = (3 << GPIO_PORT_SHIFT | 9),
PTE0 = (4 << GPIO_PORT_SHIFT | 0),
PTE1 = (4 << GPIO_PORT_SHIFT | 1),
PTE2 = (4 << GPIO_PORT_SHIFT | 2),
PTE3 = (4 << GPIO_PORT_SHIFT | 3),
PTE4 = (4 << GPIO_PORT_SHIFT | 4),
PTE5 = (4 << GPIO_PORT_SHIFT | 5),
PTE6 = (4 << GPIO_PORT_SHIFT | 6),
PTE7 = (4 << GPIO_PORT_SHIFT | 7),
PTE8 = (4 << GPIO_PORT_SHIFT | 9),
PTE9 = (4 << GPIO_PORT_SHIFT | 9),
PTE10 = (4 << GPIO_PORT_SHIFT | 10),
PTE11 = (4 << GPIO_PORT_SHIFT | 11),
LED_RED = PTE1,
// mbed original LED naming
LED1 = LED_RED,
LED2 = LED_RED,
LED3 = LED_RED,
LED4 = LED_RED,
//Push buttons
SW0 = PTE2,
USBRX = PTA1,
USBTX = PTA2,
UART_RTS = PTC1,
UART_CTS = PTC2,
UART_RX = PTC3,
UART_TX = PTC4,
I2C_SCL = PTC10,
I2C_SDA = PTC11,
DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */
// Not connected
NC = (int) 0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

39
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/device.h
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 24
#include "objects.h"
#endif

180
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.c
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/*
* How to setup clock using clock driver functions:
*
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
* and flash clock are in allowed range during clock mode switch.
*
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
*
* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
* internal reference clock(MCGIRCLK). Follow the steps to setup:
*
* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
*
* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
* explicitly to setup MCGIRCLK.
*
* 3). Don't need to configure FLL explicitly, because if target mode is FLL
* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
* if the target mode is not FLL mode, the FLL is disabled.
*
* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
*
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
*/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v3.0
processor: MKL82Z128xxx7
package_id: MKL82Z128VLL7
mcu_data: ksdk2_0
processor_version: 2.0.0
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "fsl_clock_config.h"
/*******************************************************************************
* Definitions
******************************************************************************/
#define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */
#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
#define SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK 1U /*!< LPUART clock select: PLLFLLSEL output clock */
#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
/*******************************************************************************
* Variables
******************************************************************************/
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/*******************************************************************************
* Code
******************************************************************************/
/*FUNCTION**********************************************************************
*
* Function Name : CLOCK_CONFIG_SetFllExtRefDiv
* Description : Configure FLL external reference divider (FRDIV).
* Param frdiv : The value to set FRDIV.
*
*END**************************************************************************/
static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
{
MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
}
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
void BOARD_InitBootClocks(void)
{
BOARD_BootClockRUN();
}
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: Bus_clock.outFreq, value: 16 MHz}
- {id: Core_clock.outFreq, value: 48 MHz}
- {id: Fast_bus_clock.outFreq, value: 48 MHz}
- {id: Flash_clock.outFreq, value: 16 MHz}
- {id: IRC48MCLK.outFreq, value: 48 MHz}
- {id: LPO_clock.outFreq, value: 1 kHz}
- {id: LPUARTCLK.outFreq, value: 48 MHz}
- {id: MCGPLLCLK.outFreq, value: 96 MHz}
- {id: MCGPLLCLK2X.outFreq, value: 192 MHz}
- {id: PLLFLLCLK.outFreq, value: 96 MHz}
- {id: System_clock.outFreq, value: 48 MHz}
settings:
- {id: MCGMode, value: PEE}
- {id: LPUARTClkConfig, value: 'yes'}
- {id: MCG.IREFS.sel, value: MCG.FRDIV}
- {id: MCG.OSCSEL.sel, value: SIM.IRC48MCLK}
- {id: MCG.OSCSEL_PLL.sel, value: SIM.IRC48MCLK}
- {id: MCG.PLLS.sel, value: MCG.PLL_DIV2}
- {id: MCG.PRDIV.scale, value: '4'}
- {id: RTC_CR_OSCE_CFG, value: Enabled}
- {id: SIM.FLEXIOSRCSEL.sel, value: SIM.PLLFLLDIV}
- {id: SIM.LPUARTSRCSEL.sel, value: SIM.PLLFLLDIV}
- {id: SIM.OUTDIV1.scale, value: '2'}
- {id: SIM.OUTDIV2.scale, value: '6'}
- {id: SIM.OUTDIV4.scale, value: '6'}
- {id: SIM.OUTDIV5.scale, value: '2'}
- {id: SIM.PLLFLLDIV.scale, value: '2'}
- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
sources:
- {id: IRC48M.IRC48M.outFreq, value: 48 MHz}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
const mcg_config_t mcgConfig_BOARD_BootClockRUN =
{
.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
.irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */
.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
.fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
.frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
.drs = kMCG_DrsLow, /* Low frequency range */
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
.oscsel = kMCG_OscselIrc, /* Selects 48 MHz IRC Oscillator */
.pll0Config =
{
.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
.prdiv = 0x3U, /* PLL Reference divider: divided by 4 */
.vdiv = 0x0U, /* VCO divider: multiplied by 16 */
},
};
const sim_clock_config_t simConfig_BOARD_BootClockRUN =
{
.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
.pllFllDiv = 1, /* PLLFLLSEL clock divider divisor: divided by 2 */
.pllFllFrac = 0, /* PLLFLLSEL clock divider fraction: multiplied by 1 */
.er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
.clkdiv1 = 0x15051000U, /* SIM_CLKDIV1 - OUTDIV1: /2, OUTDIV2: /6, OUTDIV4: /6, OUTDIV5: /2 */
};
const osc_config_t oscConfig_BOARD_BootClockRUN =
{
.freq = 0U, /* Oscillator frequency: 0Hz */
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
.workMode = kOSC_ModeExt, /* Use external clock */
.oscerConfig =
{
.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
.erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
}
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Set the system clock dividers in SIM to safe value. */
CLOCK_SetSimSafeDivs();
/* Configure FLL external reference divider (FRDIV). */
CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
/* Set MCG to PEE mode. */
CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
kMCG_PllClkSelPll0,
&mcgConfig_BOARD_BootClockRUN.pll0Config);
/* Set the clock configuration in SIM module. */
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
/* Set LPUART clock source. */
CLOCK_SetLpuartClock(SIM_LPUART_CLK_SEL_PLLFLLSEL_CLK);
}

64
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/fsl_clock_config.h
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#ifndef _CLOCK_CONFIG_H_
#define _CLOCK_CONFIG_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes default configuration of clocks.
*
*/
void BOARD_InitBootClocks(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
/*! @brief MCG set for BOARD_BootClockRUN configuration.
*/
extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
/*! @brief SIM module set for BOARD_BootClockRUN configuration.
*/
extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
/*! @brief OSC set for BOARD_BootClockRUN configuration.
*/
extern const osc_config_t oscConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus*/
/*!
* @brief This function executes configuration of clocks.
*
*/
void BOARD_BootClockRUN(void);
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
#endif /* _CLOCK_CONFIG_H_ */

84
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <hal/gpio_api.h>
#include "fsl_smc.h"
#include "fsl_rcm.h"
#include "fsl_pmc.h"
#include "fsl_rtc.h"
#include "fsl_clock_config.h"
//!< this contains the wakeup source
rcm_reset_source_t kinetisResetSource;
// called before main
void mbed_sdk_init()
{
rtc_config_t rtc_basic_config;
uint32_t u32cTPR_counter = 0;
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
// check the power mode source
kinetisResetSource = (rcm_reset_source_t) (RCM_GetPreviousResetSources(RCM));
// if waking up from VLLS, do some cleanup
if (kinetisResetSource & kRCM_SourceWakeup) {
PMC_ClearPeriphIOIsolationFlag(PMC);
NVIC_ClearPendingIRQ(LLWU_IRQn);
}
BOARD_BootClockRUN();
CLOCK_EnableClock(kCLOCK_Rtc0);
/* Check if the Rtc oscillator is enabled */
if ((RTC->CR & RTC_CR_OSCE_MASK) == 0u) {
/*Init the RTC with default configuration*/
RTC_GetDefaultConfig(&rtc_basic_config);
/* Setup the 32K RTC OSC */
RTC_Init(RTC, &rtc_basic_config);
/* Enable the RTC 32KHz oscillator */
RTC->CR |= RTC_CR_OSCE_MASK;
/* Start the RTC time counter */
RTC_StartTimer(RTC);
/* Verify TPR register reaches 4096 counts */
while (u32cTPR_counter < 4096) {
u32cTPR_counter = RTC->TPR;
}
/* 32kHz Oscillator is ready. */
RTC_Deinit(RTC);
}
CLOCK_DisableClock(kCLOCK_Rtc0);
}
// Change the NMI pin to an input. This allows NMI pin to
// be used as a low power mode wakeup. The application will
// need to change the pin back to NMI_b or wakeup only occurs once!
void NMI_Handler(void)
{
gpio_t gpio;
gpio_init_in(&gpio, PTA4);
}
// Set the UART clock source
void serial_clock_init(void)
{
CLOCK_SetLpuartClock(2U);
}

255
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_MTB_LAIRD_BL600/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
// Module pins. Refer datasheet for pin numbers.
SIO_1 = P0_1,
SIO_2 = P0_2,
SIO_3 = P0_3,
SIO_4 = P0_4,
SIO_5 = P0_5,
SIO_6 = P0_6,
SIO_7 = P0_7,
SIO_8 = P0_8,
SIO_9 = P0_9,
SIO_10 = P0_10,
SIO_11 = P0_11,
SIO_12 = P0_12,
SIO_13 = P0_13,
SIO_14 = P0_14,
SIO_15 = P0_15,
SIO_16 = P0_16,
SIO_17 = P0_17,
SIO_18 = P0_18,
SIO_19 = P0_19,
SIO_20 = P0_20,
SIO_21 = P0_21,
SIO_22 = P0_22,
SIO_23 = P0_23,
SIO_24 = P0_24,
SIO_25 = P0_25,
SIO_26 = P0_26,
SIO_27 = P0_27,
SIO_28 = P0_28,
SIO_29 = P0_29,
SIO_30 = P0_30,
SIO_0 = P0_0,
// Not connected
NC = (int)0xFFFFFFFF,
//Mbed MTB pin defines.
P_1 = NC,
P_2 = SIO_1,
P_3 = NC,
P_4 = SIO_2,
P_5 = SIO_3,
P_6 = SIO_4,
P_7 = SIO_5,
P_8 = SIO_6,
P_9 = SIO_7,
P_10 = NC,
P_11 = NC,
P_12 = SIO_8,
P_13 = SIO_9,
P_14 = SIO_10,
P_15 = SIO_11,
P_16 = SIO_12,
P_17 = NC,
P_18 = SIO_13,
P_19 = SIO_14,
P_20 = SIO_15,
P_21 = SIO_16,
P_22 = NC,
P_23 = NC,
P_24 = SIO_17,
P_25 = SIO_18,
P_26 = SIO_19,
P_27 = SIO_20,
P_28 = NC,
P_29 = NC,
P_30 = NC,
P_31 = NC,
P_32 = SIO_21,
P_33 = SIO_22,
P_34 = SIO_23,
P_35 = SIO_24,
P_36 = SIO_25,
P_37 = NC,
P_38 = SIO_26,
P_39 = SIO_27,
P_40 = SIO_28,
P_41 = SIO_29,
P_42 = SIO_30,
P_43 = NC,
P_44 = SIO_0,
//MTB aliases
GP0 = SIO_30,
GP1 = SIO_0,
AIN0 = SIO_1,
AIN1 = SIO_2,
AIN2 = SIO_3,
GP2 = SIO_7,
GP3 = SIO_13,
UART1_TX = SIO_17,
UART1_RX = SIO_18,
UART2_TX = SIO_25,
UART2_RX = SIO_26,
GP4 = SIO_14,
GP5 = SIO_15, //A0 for LCD on MTB
GP6 = SIO_16, //RESET for LCD on MTB
GP7 = SIO_19,
GP8 = SIO_20,
//LEDs
LED1 = SIO_4,
LED2 = SIO_5,
LED3 = SIO_6,
//Standardized button name
BUTTON1 = SIO_30,
//Nordic SDK pin names
RX_PIN_NUMBER = p22,
TX_PIN_NUMBER = p21,
CTS_PIN_NUMBER = p24,
RTS_PIN_NUMBER = p23,
// mBed interface Pins
USBTX = MBED_CONF_TARGET_USB_TX,
USBRX = MBED_CONF_TARGET_USB_RX,
SPI_MOSI0 = SIO_10,
SPI_MISO0 = SIO_11,
SPI_SS0 = SIO_19, //CS for LCD on MTB
SPI_SCK0 = SIO_12,
SPI_MOSI1 = SIO_27,
SPI_MISO1 = SIO_28,
SPI_SS1 = SIO_7, //CS for SD card on MTB
SPI_SCK1 = SIO_29,
//Default SPI
SPIS_PSELMOSI = SPI_MOSI0,
SPIS_PSELMISO = SPI_MISO0,
SPIS_PSELSS = SPI_SS0,
SPIS_PSELSCK = SPI_SCK0,
SPI_MOSI = SPI_MOSI0,
SPI_MISO = SPI_MISO0,
SPI_SS = SPI_SS0,
SPI_SCK = SPI_SCK0,
I2C_SDA0 = SIO_8,
I2C_SCL0 = SIO_9,
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

23
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_MTB_LAIRD_BL600/device.h
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// The 'provides' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'provides' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

214
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_OSHCHIP/PinNames.h
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/*
* Copyright (c) 2013 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
/*
┏━━━━━━━━━━┓
UART┬── TX D0 ╶┨ 1 ╒╕ 16 ┠╴ VCC
└── RX D1 ╶┨ 2 ╘╛ 15 ┠╴ D8 SCL ─┬I²C
D2 ╶┨ 3 14 ┠╴ D7 SDA ─┘
SPI┬ MOSI D3 ╶┨ 4 13 ┠╴ A0
│ MISO D4 ╶┨ 5 ┌──┐12 ┠╴ A1
│ SEL D5 ╶┨ 6 └──┘11 ┠╴ D9 AREF
└─ CLK D4 ╶┨ 7 10 ┠╴ A2
GND ╶┨ 8 :: 9 ┠╴ A3
┗━━━━━━━━━━┛
*/
OSHCHIP_PIN_1 = p20,
OSHCHIP_PIN_2 = p18,
OSHCHIP_PIN_3 = p16,
OSHCHIP_PIN_4 = p15,
OSHCHIP_PIN_5 = p12,
OSHCHIP_PIN_6 = p11,
OSHCHIP_PIN_7 = p9,
OSHCHIP_PIN_9 = p1,
OSHCHIP_PIN_10 = p2,
OSHCHIP_PIN_11 = p0,
OSHCHIP_PIN_12 = p27,
OSHCHIP_PIN_13 = p26,
OSHCHIP_PIN_14 = p24,
OSHCHIP_PIN_15 = p21,
LED1 = p8,
LED2 = p5,
LED3 = p3,
LED_RED = LED1,
LED_GREEN = LED2,
LED_BLUE = LED3,
RX_PIN_NUMBER = OSHCHIP_PIN_2,
TX_PIN_NUMBER = OSHCHIP_PIN_1,
CTS_PIN_NUMBER = (int)0xFFFFFFFF, //no connection
RTS_PIN_NUMBER = (int)0xFFFFFFFF, //no connection
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
SPI_PSELMOSI0 = OSHCHIP_PIN_4,
SPI_PSELMISO0 = OSHCHIP_PIN_5,
SPI_PSELSS0 = OSHCHIP_PIN_6,
SPI_PSELSCK0 = OSHCHIP_PIN_7,
SPI_PSELMOSI1 = OSHCHIP_PIN_4,
SPI_PSELMISO1 = OSHCHIP_PIN_5,
SPI_PSELSS1 = OSHCHIP_PIN_6,
SPI_PSELSCK1 = OSHCHIP_PIN_7,
SPIS_PSELMOSI = OSHCHIP_PIN_4,
SPIS_PSELMISO = OSHCHIP_PIN_5,
SPIS_PSELSS = OSHCHIP_PIN_6,
SPIS_PSELSCK = OSHCHIP_PIN_7,
I2C_SDA0 = OSHCHIP_PIN_14,
I2C_SCL0 = OSHCHIP_PIN_15,
D0 = OSHCHIP_PIN_1,
D1 = OSHCHIP_PIN_2,
D2 = OSHCHIP_PIN_3,
D3 = OSHCHIP_PIN_4,
D4 = OSHCHIP_PIN_5,
D5 = OSHCHIP_PIN_6,
D6 = OSHCHIP_PIN_7,
D7 = OSHCHIP_PIN_15,
D8 = OSHCHIP_PIN_14,
D9 = OSHCHIP_PIN_11,
A0 = OSHCHIP_PIN_13,
A1 = OSHCHIP_PIN_12,
A2 = OSHCHIP_PIN_10,
A3 = OSHCHIP_PIN_9,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

23
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_OSHCHIP/device.h
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@ -1,23 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

150
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/PinNames.h
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@ -1,150 +0,0 @@
/********************************************************************************
* \copyright
* \copyright
* Copyright 2018-2018, ARM Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
P0_31 = p31,
LED1 = p25,
LED2 = p26,
LED3 = p27,
AIN0 = p2,
AIN1 = p3,
AIN2 = p4,
GP0 = p19,
GP1 = p20,
GP2 = p28,
GP3 = p29,
GP4 = p30,
GP5 = p31, // LCD-A0
GP6 = p5, // LCD-RESET
GP7 = p6, // LCD-CS
GP8 = p7,
RX_PIN_NUMBER = p12,
TX_PIN_NUMBER = p11,
CTS_PIN_NUMBER = p9,
RTS_PIN_NUMBER = p8,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
STDIO_UART_CTS = CTS_PIN_NUMBER,
STDIO_UART_RTS = RTS_PIN_NUMBER,
SPI_MOSI = p16,
SPI_MISO = p17,
SPI_SCK = p18,
SPI_CS = p10,
USER_BUTTON = GP0,
I2C_SDA = p14,
I2C_SCL = p15,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

13
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_ACONNO_ACN52832/device.h
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@ -1,13 +0,0 @@
/********************************************************************************
* \copyright
* \copyright
* Copyright 2018-2018, ARM Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

245
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
P0_31 = p31,
// Module pins. Refer datasheet for pin numbers.
SIO_1 = P0_1,
SIO_2 = P0_2,
SIO_3 = P0_3,
SIO_4 = P0_4,
SIO_5 = P0_5,
SIO_6 = P0_6,
SIO_7 = P0_7,
SIO_8 = P0_8,
SIO_9 = P0_9, //NFC1
SIO_10 = P0_10, //NFC2
SIO_11 = P0_11,
SIO_12 = P0_12,
SIO_13 = P0_13,
SIO_14 = P0_14,
SIO_15 = P0_15,
SIO_16 = P0_16,
SIO_17 = P0_17,
SIO_18 = P0_18,
SIO_19 = P0_19,
SIO_20 = P0_20,
SIO_22 = P0_22,
SIO_23 = P0_23,
SIO_24 = P0_24,
SIO_25 = P0_25,
SIO_26 = P0_26,
SIO_27 = P0_27,
SIO_28 = P0_28,
SIO_29 = P0_29,
SIO_30 = P0_30,
SIO_31 = P0_31,
SIO_0 = P0_0,
// Not connected
NC = (int)0xFFFFFFFF,
//Mbed MTB pin defines.
P_1 = NC,
P_2 = SIO_24, //MISO
P_3 = SIO_23, //MOSI
P_4 = SIO_22,
// P_5 = SWDIO,
// P_6 = SWDCLK,
// P_7 = NRST,
P_8 = SIO_20,
P_9 = SIO_18,
P_10 = SIO_16,
P_11 = SIO_14,
P_12 = SIO_12,
P_13 = SIO_11,
P_14 = SIO_10,
P_15 = SIO_9,
P_16 = NC,
P_17 = SIO_8,
P_18 = SIO_7,
P_19 = SIO_6,
P_20 = SIO_5,
P_21 = SIO_4,
P_22 = SIO_3,
P_23 = SIO_2,
P_24 = SIO_1,
P_25 = SIO_0,
P_26 = NC,
P_27 = NC,
P_28 = SIO_13,
P_29 = SIO_15,
P_30 = SIO_17,
P_31 = SIO_19,
P_32 = SIO_31,
P_33 = SIO_30,
P_34 = SIO_29,
P_35 = SIO_28,
P_36 = SIO_27,
P_37 = SIO_26,
P_38 = SIO_25,
P_39 = NC,
//LEDs
LED1 = SIO_28,
LED2 = SIO_29,
LED3 = SIO_30,
LED_RED = LED1,
LED_GREEN = LED2,
LED_BLUE = LED3,
GP0 = SIO_11,
//Standardized button name
BUTTON1 = GP0,
//Nordic SDK pin names
RX_PIN_NUMBER = SIO_8,
TX_PIN_NUMBER = SIO_6,
CTS_PIN_NUMBER = SIO_7,
RTS_PIN_NUMBER = SIO_5,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
STDIO_UART_CTS = CTS_PIN_NUMBER,
STDIO_UART_RTS = RTS_PIN_NUMBER,
SPI_MOSI = SIO_23,
SPI_MISO = SIO_24,
SPI_SS0 = SIO_17, //CS for LCD on MTB
SPI_SS1 = SIO_10, //CS for SD card on MTB
SPI_SCK1 = SIO_25,
SPI_SCK2 = SIO_31,
//Default SPI
SPI_SCK = SPI_SCK1,
SPI_CS = SPI_SS1,
I2C_SDA = SIO_26,
I2C_SCL = SIO_27,
//MTB aliases
GP1 = SIO_13,
AIN0 = SIO_2,
AIN1 = SIO_3,
AIN2 = SIO_4,
GP2 = SIO_10,
GP3 = SIO_9,
GP4 = SIO_22,
GP5 = SIO_19, //A0 for LCD on MTB
GP6 = SIO_18, //RESET for LCD on MTB
GP7 = SIO_17,
GP8 = SIO_15,
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

23
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/device.h
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@ -1,23 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

198
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_MURATA_WSM_BL241/PinNames.h
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@ -1,198 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
// Module pins. Refer datasheet for pin numbers.
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
P0_31 = p31,
// Not connected
NC = (int)0xFFFFFFFF,
//Mbed MTB pin defines.
P_1 = P0_9,
P_2 = P0_6,
P_3 = P0_0,
P_4 = P0_1,
P_5 = NC,
P_6 = NC,
P_7 = NC,
P_8 = NC,
P_9 = P0_2,
P_10 = P0_5,
P_11 = P0_3,
P_12 = P0_4,
P_13 = P0_29,
P_14 = P0_7,
P_15 = P0_8,
P_17 = P0_21,
P_19 = NC,
P_20 = NC,
P_21 = NC,
P_22 = P0_18,
P_23 = P0_16,
P_24 = P0_15,
P_25 = P0_14,
P_26 = P0_10,
P_27 = P0_20,
P_28 = P0_17,
P_29 = P0_13,
P_30 = NC,
P_31 = NC,
P_32 = NC,
P_33 = NC,
P_34 = NC,
P_35 = NC,
P_36 = NC,
P_37 = NC,
//LEDs
LED1 = P_22,
LED_RED = LED1,
LED2 = NC,
LED3 = NC,
GP0 = P_23,
//Standardized button name
BUTTON1 = GP0,
//Nordic SDK pin names
RX_PIN_NUMBER = P_15,
TX_PIN_NUMBER = P_2,
CTS_PIN_NUMBER = P_14,
RTS_PIN_NUMBER = P_10,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
STDIO_UART_CTS = CTS_PIN_NUMBER,
STDIO_UART_RTS = RTS_PIN_NUMBER,
SPI_MOSI = P_9,
SPI_MISO = P_11,
SPI_NCS = P_22, //CS for SPIFlash on MTB
SPI_SCK = P_12,
I2C_SDA = P_25,
I2C_SCL = P_24,
//MTB aliases
AIN0 = P_13,
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

24
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_MURATA_WSM_BL241/device.h
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2018, Arm Limited and affiliates.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

157
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_UBLOX_NINA_B1/PinNames.h
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@ -1,157 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
// nRF52 pin names
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
NC = (int)0xFFFFFFFF, // Not connected
//NINA-B112 module pin names
P_1 = p8,
P_2 = p11,
P_3 = p12,
P_4 = p13,
P_5 = p14,
P_6 = NC,
P_7 = p16,
P_8 = p18,
P_9 = NC,
P_10 = NC,
P_11 = NC,
P_12 = NC,
P_13 = NC,
P_14 = NC,
P_15 = NC,
P_16 = p28,
P_17 = p29,
P_18 = p30,
P_19 = p21,
P_20 = p31,
P_21 = p7,
P_22 = p6,
P_23 = p5,
P_24 = p2,
P_25 = p3,
P_26 = NC,
P_27 = p4,
P_28 = p9,
P_29 = p10,
P_30 = NC,
// MTB aliases
GPIO18 = p30,
LED1 = p4, // Red LED
LED2 = p10, // Green LED
GPIO27 = LED1,
// GPIO29 = LED2,
GPIO7 = p16, //A0 for LCD
GPIO16 = p28, //RESET for LCD
SW1 = p29,
GPIO17 = SW1,
//Standardized button names
BUTTON1 = SW1,
// Nordic SDK pin names
RX_PIN_NUMBER = p5,
TX_PIN_NUMBER = p6,
CTS_PIN_NUMBER = p7,
RTS_PIN_NUMBER = p31,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
STDIO_UART_CTS = CTS_PIN_NUMBER,
STDIO_UART_RTS = RTS_PIN_NUMBER,
I2C_SDA = p2,
I2C_SCL = p3,
SPI0_MOSI = p13,
SPI0_MISO = p12,
SPI0_SCK = p14,
SPI0_CS = p11,
SPI1_CS = p8,
SPI_MOSI = SPI0_MOSI,
SPI_MISO = SPI0_MISO,
SPI_SCK = SPI0_SCK,
SPI_CS = SPI0_CS,
// DAPLink
USBRX = RX_PIN_NUMBER,
USBTX = TX_PIN_NUMBER,
NTRST = p21,
SWO = p18,
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

21
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

154
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/ONBOARD_RM1000_AT.cpp
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/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if MBED_CONF_NSAPI_PRESENT
#include "ONBOARD_RM1000_AT.h"
#include "drivers/BufferedSerial.h"
#include "mbed-trace/mbed_trace.h"
#ifndef TRACE_GROUP
#define TRACE_GROUP "RIOTMICRO"
#endif // TRACE_GROUP
#include "gpio_api.h"
#include "PinNames.h"
#include "hal/serial_api.h"
#include "platform/mbed_thread.h"
using namespace mbed;
ONBOARD_RM1000_AT::ONBOARD_RM1000_AT(FileHandle *fh) : RM1000_AT(fh)
{
}
nsapi_error_t ONBOARD_RM1000_AT::hard_power_on()
{
tr_debug("Calling ONBOARD_RM1000_AT::hard_power_on");
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_RM1000_AT::hard_power_off()
{
tr_debug("Calling ONBOARD_RM1000_AT::hard_power_off");
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_RM1000_AT::soft_power_on()
{
tr_debug("Calling ONBOARD_RM1000_AT::soft_power_on");
onboard_modem_init();
return NSAPI_ERROR_OK;
}
nsapi_error_t ONBOARD_RM1000_AT::soft_power_off()
{
tr_debug("Calling ONBOARD_RM1000_AT::soft_power_off");
onboard_modem_deinit();
return NSAPI_ERROR_OK;
}
void ONBOARD_RM1000_AT::onboard_modem_init()
{
char promptEnd;
tr_debug("onboard_modem_init");
gpio_t gpio;
gpio_init_out_ex(&gpio, MDMCHEN, 0);
gpio_init_out_ex(&gpio, MDMREMAP, 0);
// Take us out of reset
gpio_init_out_ex(&gpio, MDMRST, 0);
thread_sleep_for(100);
gpio_write(&gpio, 1);
/* Initialize UART1 pins to allow collecting logs from a PC */
gpio_init_in_ex(&gpio, MDM_UART1_TXD, PullNone);
gpio_init_in_ex(&gpio, MDM_UART1_RXD, PullNone);
serial_t bootrom_uart;
serial_init(&bootrom_uart, MDM_UART0_TXD, MDM_UART0_RXD);
serial_baud(&bootrom_uart, 115200);
tr_debug("%s: MODEM RESET", __func__);
serial_getc(&bootrom_uart);
tr_debug("%s: MODEM first activity after reset", __func__);
/* Wait for some dots */
for (int i = 0; i < 3; i++) {
do {
promptEnd = serial_getc(&bootrom_uart);
} while ('.' != promptEnd);
}
serial_putc(&bootrom_uart, ' ');
/* Wait for bootrom prompt */
for (int i = 0; i < 2; i++) {
do {
promptEnd = serial_getc(&bootrom_uart);
} while ('>' != promptEnd);
}
serial_putc(&bootrom_uart, '6');
serial_free(&bootrom_uart);
/* Wait for stack prompt */
tr_debug("%s: Wait for stack prompt", __func__);
thread_sleep_for(100);
serial_t cli_uart;
serial_init(&cli_uart, MDM_UART3_TXD, MDM_UART3_RXD);
serial_baud(&cli_uart, 230400); /* TODO make baud rate configurable */
do {
promptEnd = serial_getc(&cli_uart);
} while ('>' != promptEnd);
serial_free(&cli_uart);
tr_debug("%s: MODEM CLI prompt reached", __func__);
tr_debug("Reset RM1000 completed");
}
void ONBOARD_RM1000_AT::onboard_modem_deinit()
{
tr_debug("onboard_modem_deinit");
gpio_t gpio;
// Back into reset
gpio_init_out_ex(&gpio, MDMRST, 0);
}
CellularDevice *CellularDevice::get_target_default_instance()
{
tr_debug("Calling CellularDevice::get_target_default_instance from ONBOARD_RM1000_AT");
static BufferedSerial serial(MDM_UART3_TXD, MDM_UART3_RXD, 230400);
#if DEVICE_SERIAL_FC
if (MDM_UART3_RTS != NC && MDM_UART3_CTS != NC) {
tr_debug("Modem flow control: RTS %d CTS %d", MDM_UART3_RTS, MDM_UART3_CTS);
serial.set_flow_control(SerialBase::RTSCTS, MDM_UART3_RTS, MDM_UART3_CTS);
}
#endif
static ONBOARD_RM1000_AT device(&serial);
return &device;
}
#endif // MBED_CONF_NSAPI_PRESENT

43
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/ONBOARD_RM1000_AT.h
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@ -1,43 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef ONBOARD_RM1000_AT_
#define ONBOARD_RM1000_AT_
#include "RM1000_AT.h"
namespace mbed
{
class ONBOARD_RM1000_AT : public RM1000_AT
{
public:
ONBOARD_RM1000_AT(FileHandle *fh);
virtual nsapi_error_t hard_power_on();
virtual nsapi_error_t hard_power_off();
virtual nsapi_error_t soft_power_on();
virtual nsapi_error_t soft_power_off();
private:
void onboard_modem_init();
void onboard_modem_deinit();
};
} // namespace mbed
#endif // ONBOARD_RM1000_AT_

138
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_RIOT_MICRO_MODULE/TARGET_RM6100/PinNames.h
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#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
// nRF52 pin names
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
NC = (int)0xFFFFFFFF, // Not connected
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
P0_31 = p31,
MDMCHEN = p13,
MDMREMAP = p14,
MDMRST = p25,
MDM_UART0_TXD = p15,
MDM_UART0_RXD = p16,
MDM_UART1_TXD = p17,
MDM_UART1_RXD = p18,
MDM_UART3_TXD = p19,
MDM_UART3_RXD = p20,
MDM_UART3_RTS = NC,
MDM_UART3_CTS = NC,
LED1 = P0_10,
LED2 = P0_22,
RX_PIN_NUMBER = NC,
TX_PIN_NUMBER = NC,
CTS_PIN_NUMBER = NC,
RTS_PIN_NUMBER = NC,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
STDIO_UART_CTS = CTS_PIN_NUMBER,
STDIO_UART_RTS = RTS_PIN_NUMBER,
A0 = NC,
A1 = p4,
A2 = p28,
A3 = p29,
A4 = p30,
A5 = p31,
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
typedef enum {
// nRF52 pin names
p0 = 0,
p1 = 1,
p2 = 2,
p3 = 3,
p4 = 4,
p5 = 5,
p6 = 6,
p7 = 7,
p8 = 8,
p9 = 9,
p10 = 10,
p11 = 11,
p12 = 12,
p13 = 13,
p14 = 14,
p15 = 15,
p16 = 16,
p17 = 17,
p18 = 18,
p19 = 19,
p20 = 20,
p21 = 21,
p22 = 22,
p23 = 23,
p24 = 24,
p25 = 25,
p26 = 26,
p27 = 27,
p28 = 28,
p29 = 29,
p30 = 30,
p31 = 31,
NC = (int)0xFFFFFFFF, // Not connected
P0_0 = p0,
P0_1 = p1,
P0_2 = p2,
P0_3 = p3,
P0_4 = p4,
P0_5 = p5,
P0_6 = p6,
P0_7 = p7,
P0_8 = p8,
P0_9 = p9,
P0_10 = p10,
P0_11 = p11,
P0_12 = p12,
P0_13 = p13,
P0_14 = p14,
P0_15 = p15,
P0_16 = p16,
P0_17 = p17,
P0_18 = p18,
P0_19 = p19,
P0_20 = p20,
P0_21 = p21,
P0_22 = p22,
P0_23 = p23,
P0_24 = p24,
P0_25 = p25,
P0_26 = p26,
P0_27 = p27,
P0_28 = p28,
P0_29 = p29,
P0_30 = p30,
P0_31 = p31,
MDMCHEN = p13,
MDMREMAP = p14,
MDMRST = p25,
MDM_UART0_TXD = p15,
MDM_UART0_RXD = p16,
MDM_UART1_TXD = p17,
MDM_UART1_RXD = p18,
MDM_UART3_TXD = p19,
MDM_UART3_RXD = p20,
MDM_UART3_RTS = NC,
MDM_UART3_CTS = NC,
LED1 = P0_10,
LED2 = P0_22,
RX_PIN_NUMBER = NC,
TX_PIN_NUMBER = NC,
CTS_PIN_NUMBER = NC,
RTS_PIN_NUMBER = NC,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
STDIO_UART_CTS = CTS_PIN_NUMBER,
STDIO_UART_RTS = RTS_PIN_NUMBER,
I2C_SDA0 = p12,
I2C_SCL0 = p11,
A0 = p2,
A1 = p28,
A2 = p4,
A3 = p29,
A4 = p30,
A5 = p31,
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

23
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

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@ -1,252 +0,0 @@
/*
* Copyright (c) 2016 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "nrf_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
///> define macro producing for example Px_y = NRF_GPIO_PIN_MAP(x, y)
#define PinDef(port_num, pin_num) P##port_num##_##pin_num = NRF_GPIO_PIN_MAP(port_num, pin_num)
typedef enum {
PinDef(0 , 0), // P0_0 = 0...
PinDef(0 , 1),
PinDef(0 , 2),
PinDef(0 , 3),
PinDef(0 , 4),
PinDef(0 , 5),
PinDef(0 , 6),
PinDef(0 , 7),
PinDef(0 , 8),
PinDef(0 , 9),
PinDef(0 , 10),
PinDef(0 , 11),
PinDef(0 , 12),
PinDef(0 , 13),
PinDef(0 , 14),
PinDef(0 , 15),
PinDef(0 , 16),
PinDef(0 , 17),
PinDef(0 , 18),
PinDef(0 , 19),
PinDef(0 , 20),
PinDef(0 , 21),
PinDef(0 , 22),
PinDef(0 , 23),
PinDef(0 , 24),
PinDef(0 , 25),
PinDef(0 , 26),
PinDef(0 , 27),
PinDef(0 , 28),
PinDef(0 , 29),
PinDef(0 , 30),
PinDef(0 , 31),
PinDef(1 , 0), //P1_1 = 32...
PinDef(1 , 1),
PinDef(1 , 2),
PinDef(1 , 3),
PinDef(1 , 4),
PinDef(1 , 5),
PinDef(1 , 6),
PinDef(1 , 7),
PinDef(1 , 8),
PinDef(1 , 9),
PinDef(1 , 10),
PinDef(1 , 11),
PinDef(1 , 12),
PinDef(1 , 13),
PinDef(1 , 14),
PinDef(1 , 15),
// Port0
p0 = P0_0,
p1 = P0_1,
p2 = P0_2,
p3 = P0_3,
p4 = P0_4,
p5 = P0_5,
p6 = P0_6,
p7 = P0_7,
p8 = P0_8,
p9 = P0_9,
p10 = P0_10,
p11 = P0_11,
p12 = P0_12,
p13 = P0_13,
p14 = P0_14,
p15 = P0_15,
p16 = P0_16,
p17 = P0_17,
p18 = P0_18,
p19 = P0_19,
p20 = P0_20,
p21 = P0_21,
p22 = P0_22,
p23 = P0_23,
p24 = P0_24,
p25 = P0_25,
p26 = P0_26,
p27 = P0_27,
p28 = P0_28,
p29 = P0_29,
p30 = P0_30,
p31 = P0_31,
// Port1
p32 = P1_0,
p33 = P1_1,
p34 = P1_2,
p35 = P1_3,
p36 = P1_4,
p37 = P1_5,
p38 = P1_6,
p39 = P1_7,
p40 = P1_8,
p41 = P1_9,
p42 = P1_10,
p43 = P1_11,
p44 = P1_12,
p45 = P1_13,
p46 = P1_14,
p47 = P1_15,
LED_RED = p23,
LED_GREEN = p22,
LED_BLUE = p24,
LED1 = LED_RED,
LED2 = LED_GREEN,
LED3 = LED_BLUE,
BUTTON_USER = p32,
BUTTON_GROVE1 = p27, // on Base Dock Grove#1
BUTTON_GROVE2 = p29, // on Base Dock Grove#2
BUTTON_GROVE3 = p31, // on Base Dock Grove#3
BUTTON_GROVE4 = p3, // on Base Dock Grove#4
BUTTON1 = BUTTON_GROVE1, // on Base Dock Grove#1
BUTTON2 = BUTTON_GROVE2, // on Base Dock Grove#2
BUTTON3 = BUTTON_GROVE3, // on Base Dock Grove#3
BUTTON4 = BUTTON_GROVE4, // on Base Dock Grove#4
USR_BTN = BUTTON_USER, // on Board
RX_PIN_NUMBER = p19,
TX_PIN_NUMBER = p20,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
SPI_PSELMOSI0 = p15,
SPI_PSELMISO0 = p16,
SPI_PSELSS0 = p17,
SPI_PSELSCK0 = p21,
SPI_PSELMOSI1 = p12,
SPI_PSELMISO1 = p13,
SPI_PSELSS1 = p11,
SPI_PSELSCK1 = p14,
SPIS_PSELMOSI = p12,
SPIS_PSELMISO = p13,
SPIS_PSELSS = p11,
SPIS_PSELSCK = p14,
I2C_SDA0 = p26,
I2C_SCL0 = p27,
A0 = p2,
A1 = p3,
A4 = p28,
A5 = p29,
A6 = p30,
A7 = p31,
/**** QSPI pins ****/
QSPI1_IO0 = P1_5,
QSPI1_IO1 = P1_4,
QSPI1_IO2 = P1_2,
QSPI1_IO3 = P1_1,
QSPI1_SCK = P1_3,
QSPI1_CSN = P1_6,
/**** QSPI FLASH pins ****/
QSPI_FLASH1_IO0 = QSPI1_IO0,
QSPI_FLASH1_IO1 = QSPI1_IO1,
QSPI_FLASH1_IO2 = QSPI1_IO2,
QSPI_FLASH1_IO3 = QSPI1_IO3,
QSPI_FLASH1_SCK = QSPI1_SCK,
QSPI_FLASH1_CSN = QSPI1_CSN,
// Not connected
NC = (int)0xFFFFFFFF,
CTS_PIN_NUMBER = NC,
RTS_PIN_NUMBER = NC,
STDIO_UART_CTS = CTS_PIN_NUMBER,
STDIO_UART_RTS = RTS_PIN_NUMBER
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

38
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

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/*
* Copyright (c) 2016 Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
* integrated circuit in a product or a software update for such product, must reproduce
* the above copyright notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
* used to endorse or promote products derived from this software without specific prior
* written permission.
*
* 4. This software, with or without modification, must only be used with a
* Nordic Semiconductor ASA integrated circuit.
*
* 5. Any software provided in binary or object form under this license must not be reverse
* engineered, decompiled, modified and/or disassembled.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "nrf_gpio.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 3
///> define macro producing for example Px_y = NRF_GPIO_PIN_MAP(x, y)
#define PinDef(port_num, pin_num) P##port_num##_##pin_num = NRF_GPIO_PIN_MAP(port_num, pin_num)
typedef enum {
PinDef(0 , 0), // P0_0 = 0...
PinDef(0 , 1),
PinDef(0 , 2),
PinDef(0 , 3),
PinDef(0 , 4),
PinDef(0 , 5),
PinDef(0 , 6),
PinDef(0 , 7),
PinDef(0 , 8),
PinDef(0 , 9),
PinDef(0 , 10),
PinDef(0 , 11),
PinDef(0 , 12),
PinDef(0 , 13),
PinDef(0 , 14),
PinDef(0 , 15),
PinDef(0 , 16),
PinDef(0 , 17),
PinDef(0 , 18),
PinDef(0 , 19),
PinDef(0 , 20),
PinDef(0 , 21),
PinDef(0 , 22),
PinDef(0 , 23),
PinDef(0 , 24),
PinDef(0 , 25),
PinDef(0 , 26),
PinDef(0 , 27),
PinDef(0 , 28),
PinDef(0 , 29),
PinDef(0 , 30),
PinDef(0 , 31),
PinDef(1 , 0), //P1_1 = 32...
PinDef(1 , 1),
PinDef(1 , 2),
PinDef(1 , 3),
PinDef(1 , 4),
PinDef(1 , 5),
PinDef(1 , 6),
PinDef(1 , 7),
PinDef(1 , 8),
PinDef(1 , 9),
PinDef(1 , 10),
PinDef(1 , 11),
PinDef(1 , 12),
PinDef(1 , 13),
PinDef(1 , 14),
PinDef(1 , 15),
// Port0
p0 = P0_0,
p1 = P0_1,
p2 = P0_2,
p3 = P0_3,
p4 = P0_4,
p5 = P0_5,
p6 = P0_6,
p7 = P0_7,
p8 = P0_8,
p9 = P0_9,
p10 = P0_10,
p11 = P0_11,
p12 = P0_12,
p13 = P0_13,
p14 = P0_14,
p15 = P0_15,
p16 = P0_16,
p17 = P0_17,
p18 = P0_18,
p19 = P0_19,
p20 = P0_20,
p21 = P0_21,
p22 = P0_22,
p23 = P0_23,
p24 = P0_24,
p25 = P0_25,
p26 = P0_26,
p27 = P0_27,
p28 = P0_28,
p29 = P0_29,
p30 = P0_30,
p31 = P0_31,
// Port1
p32 = P1_0,
p33 = P1_1,
p34 = P1_2,
p35 = P1_3,
p36 = P1_4,
p37 = P1_5,
p38 = P1_6,
p39 = P1_7,
p40 = P1_8,
p41 = P1_9,
p42 = P1_10,
p43 = P1_11,
p44 = P1_12,
p45 = P1_13,
p46 = P1_14,
p47 = P1_15,
// Not connected
NC = (int)0xFFFFFFFF,
SIO_0 = P0_0,
SIO_1 = P0_1,
SIO_2 = P0_2,
SIO_3 = P0_3,
SIO_4 = P0_4,
SIO_5 = P0_5,
SIO_6 = P0_6,
SIO_7 = P0_7,
SIO_8 = P0_8,
SIO_9 = P0_9, //NFC1
SIO_10 = P0_10, //NFC2
SIO_11 = P0_11,
SIO_12 = P0_12,
SIO_13 = P0_13,
SIO_14 = P0_14,
SIO_15 = P0_15,
SIO_16 = P0_16,
SIO_17 = P0_17,
SIO_18 = NC,
SIO_19 = P0_19,
SIO_20 = P0_20,
SIO_21 = P0_21,
SIO_22 = P0_22,
SIO_23 = P0_23,
SIO_24 = P0_24,
SIO_25 = P0_25,
SIO_26 = P0_26,
SIO_27 = P0_27,
SIO_28 = P0_28,
SIO_29 = P0_29,
SIO_30 = P0_30,
SIO_31 = P0_31,
SIO_32 = P1_0,
SIO_33 = P1_1,
SIO_34 = P1_2,
SIO_35 = P1_3,
SIO_36 = P1_4,
SIO_37 = P1_5,
SIO_38 = P1_6,
SIO_39 = P1_7,
SIO_40 = P1_8,
SIO_41 = P1_9,
SIO_42 = P1_10,
SIO_43 = P1_11,
SIO_44 = P1_12,
SIO_45 = P1_13,
SIO_46 = P1_14,
SIO_47 = P1_15,
LED1 = SIO_38,
LED2 = SIO_39,
LED3 = SIO_37,
LED_RED = LED1,
LED_GREEN = LED3,
LED_BLUE = LED2,
BUTTON1 = SIO_33,
USER_BUTTON = BUTTON1,
//Nordic SDK pin names
RX_PIN_NUMBER = SIO_8,
TX_PIN_NUMBER = SIO_6,
CTS_PIN_NUMBER = SIO_7,
RTS_PIN_NUMBER = SIO_5,
// mBed interface Pins
USBTX = TX_PIN_NUMBER,
USBRX = RX_PIN_NUMBER,
STDIO_UART_TX = TX_PIN_NUMBER,
STDIO_UART_RX = RX_PIN_NUMBER,
STDIO_UART_CTS = CTS_PIN_NUMBER,
STDIO_UART_RTS = RTS_PIN_NUMBER,
SPI_PSELMOSI0 = SIO_45,
SPI_PSELMISO0 = SIO_46,
SPI_PSELSS0 = SIO_42, //CS for SD card on MTB
SPI_PSELSCK0 = SIO_47,
SPI_PSELMOSI1 = SIO_30,
SPI_PSELMISO1 = SIO_29,
SPI_PSELSS1 = SIO_41, //CS for LCD on MTB
SPI_PSELSCK1 = SIO_44,
//Default SPI
SPI_MOSI = SPI_PSELMOSI0,
SPI_MISO = SPI_PSELMISO0,
SPI_SCK = SPI_PSELSCK0,
SPI_CS = SPI_PSELSS0,
/*
SPIS_PSELMOSI = P1_2,
SPIS_PSELMISO = P1_3,
SPIS_PSELSS = P1_1,
SPIS_PSELSCK = P1_4,
*/
I2C_SDA0 = SIO_26,
I2C_SCL0 = SIO_27,
I2C_SDA1 = SIO_25,
I2C_SCL1 = SIO_28,
//Default I2C
I2C_SCL = I2C_SCL0,
I2C_SDA = I2C_SDA0,
UART_TX1 = SIO_16,
UART_RX1 = SIO_15,
UART_TX2 = SIO_21,
UART_RX2 = SIO_24,
//Default UART
UART_TX = UART_TX1,
UART_RX = UART_RX1,
/* QSPI */
QSPI1_IO0 = P0_20,
QSPI1_IO1 = P0_21,
QSPI1_IO2 = P0_22,
QSPI1_IO3 = P0_23,
QSPI1_SCK = P0_19,
QSPI1_CSN = P0_17,
/* QSPI FLASH */
QSPI_FLASH1_IO0 = QSPI1_IO0,
QSPI_FLASH1_IO1 = QSPI1_IO1,
QSPI_FLASH1_IO2 = QSPI1_IO2,
QSPI_FLASH1_IO3 = QSPI1_IO3,
QSPI_FLASH1_SCK = QSPI1_SCK,
QSPI_FLASH1_CSN = QSPI1_CSN,
//MTB aliases
GP0 = SIO_33,
GP1 = SIO_34,
AIN0 = SIO_2,
AIN1 = SIO_3,
AIN2 = SIO_4,
GP2 = SIO_42,
GP3 = SIO_43,
GP4 = SIO_19,
GP5 = SIO_17, //A0 for LCD on MTB
GP6 = SIO_40, //RESET for LCD on MTB
GP7 = SIO_41,
GP8 = SIO_12,
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 3,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

24
targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_MTB_LAIRD_BL654/device.h
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/PeripheralPins.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
/************ADC***************/
extern const PinMap PinMap_ADC[];
/************I2C***************/
extern const PinMap PinMap_I2C_SDA[];
extern const PinMap PinMap_I2C_SCL[];
/************UART***************/
extern const PinMap PinMap_UART_TX[];
extern const PinMap PinMap_UART_RX[];
/************SPI***************/
extern const PinMap PinMap_SPI_SCLK[];
extern const PinMap PinMap_SPI_MOSI[];
extern const PinMap PinMap_SPI_MISO[];
extern const PinMap PinMap_SPI_SSEL[];
/************PWM***************/
extern const PinMap PinMap_PWM[];
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/PortNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1
} PortName;
#ifdef __cplusplus
}
#endif
#endif

71
targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX UART_TX
#define STDIO_UART_RX UART_RX
#define STDIO_UART UART_0
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PeripheralPins.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P0_11, ADC0_0, 0x02},
{P0_12, ADC0_1, 0x02},
{P0_13, ADC0_2, 0x02},
{P0_14, ADC0_3, 0x02},
{P0_15, ADC0_4, 0x02},
{P0_16, ADC0_5, 0x01},
{P0_22, ADC0_6, 0x01},
{P0_23, ADC0_7, 0x01},
{NC , NC , 0 }
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P0_5, I2C_0, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P0_4, I2C_0, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_13, UART_0, 3},
{P1_27, UART_0, 2},
{ NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_14, UART_0, 3},
{P1_26, UART_0, 2},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P0_10, SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P1_15, SPI_1, 0x03},
{P1_20, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_19, SPI_1, 0x02},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
/************PWM***************/
/* To have a PWM where we can change both the period and the duty cycle,
* we need an entire timer. With the following conventions:
* * MR3 is used for the PWM period
* * MR0, MR1, MR2 are used for the duty cycle
*/
const PinMap PinMap_PWM[] = {
/* CT16B0 */
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
/* CT16B1 */
{P0_21, PWM_4, 1}, /* MR0 */
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
/* CT32B0 */
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
/* CT32B1 */
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
{NC, NC, 0}
};

178
targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// MicroNFCBoard pin names
M_RST = P0_0,
M_BOOT = P0_1,
M_RXD = P0_18,
M_TXD = P0_19,
M_SCL = P0_4,
M_SDA = P0_5,
M_D0 = P0_20,
M_A0 = P0_16,
M_A1 = P0_15,
M_A2 = P0_14,
M_A3 = P0_13,
M_SCK = P0_10,
M_MOSI = P0_9,
M_MISO = P0_8,
M_NCS = P0_2,
M_IRQ = P0_7,
// MicroNFCBoard pin numbers
p4 = M_RST,
p5 = M_BOOT,
p6 = M_RXD,
p7 = M_TXD,
p8 = M_SCL,
p9 = M_SDA,
p10 = M_D0,
p11 = M_IRQ,
p12 = M_NCS,
p13 = M_MISO,
p14 = M_MOSI,
p15 = M_SCK,
p16 = M_A3,
p17 = M_A2,
p18 = M_A1,
p19 = M_A0,
// Other Pin Names
LED1 = P0_11,
LED2 = P0_12,
// Alias to have correct blue lights of death pattern
LED3 = LED2,
LED4 = LED1,
UART_TX = M_TXD,
UART_RX = M_RXD,
// Not connected
NC = (int)0xFFFFFFFF,
// Standard but not supported pins
USBTX = NC,
USBRX = NC,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_APPNEARME_MICRONFCBOARD/device.h
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U24_301/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
// Default peripherals
#define MBED_SPI0 p5, p6, p7, p8
#define MBED_SPI1 p11, p12, p13, p14
#define MBED_UART0 p9, p10
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 p28, p27
#define MBED_ANALOGIN0 p15
#define MBED_ANALOGIN1 p16
#define MBED_ANALOGIN2 p17
#define MBED_ANALOGIN3 p18
#define MBED_ANALOGIN4 p19
#define MBED_ANALOGIN5 p20
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P0_11, ADC0_0, 0x02},
{P0_12, ADC0_1, 0x02},
{P0_13, ADC0_2, 0x02},
{P0_14, ADC0_3, 0x02},
{P0_15, ADC0_4, 0x02},
{P0_16, ADC0_5, 0x01},
{P0_22, ADC0_6, 0x01},
{P0_23, ADC0_7, 0x01},
{NC , NC , 0 }
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P0_5, I2C_0, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P0_4, I2C_0, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_13, UART_0, 3},
{P1_27, UART_0, 2},
{ NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_14, UART_0, 3},
{P1_26, UART_0, 2},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P0_10, SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P1_15, SPI_1, 0x03},
{P1_20, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_19, SPI_1, 0x02},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
/************PWM***************/
/* To have a PWM where we can change both the period and the duty cycle,
* we need an entire timer. With the following conventions:
* * MR3 is used for the PWM period
* * MR0, MR1, MR2 are used for the duty cycle
*/
const PinMap PinMap_PWM[] = {
/* CT16B0 */
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
/* CT16B1 */
{P0_21, PWM_4, 1}, /* MR0 */
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
/* CT32B0 */
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
/* CT32B1 */
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
{NC, NC, 0}
};

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// mbed DIP Pin Names
p5 = P0_9,
p6 = P0_8,
p7 = P1_29,
p8 = P0_2,
p9 = P1_27,
p10 = P1_26,
p11 = P1_22,
p12 = P1_21,
p13 = P1_20,
p14 = P1_23,
p15 = P0_11,
p16 = P0_12,
p17 = P0_13,
p18 = P0_14,
p19 = P0_16,
p20 = P0_22,
p21 = P0_7,
p22 = P0_17,
p23 = P1_17,
p24 = P1_18,
p25 = P1_24,
p26 = P1_25,
p27 = P0_4,
p28 = P0_5,
p29 = P1_5,
p30 = P1_2,
p33 = P0_3,
p34 = P1_15,
p35 = P0_20,
p36 = P0_21,
// Other mbed Pin Names
LED1 = P1_8,
LED2 = P1_9,
LED3 = P1_10,
LED4 = P1_11,
USBTX = P0_19,
USBRX = P0_18,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
// Default peripherals
#define MBED_SPI0 p5, p6, p7, p8
#define MBED_SPI1 p11, p12, p13, p14
#define MBED_UART0 p9, p10
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 p28, p27
#define MBED_ANALOGIN0 p15
#define MBED_ANALOGIN1 p16
#define MBED_ANALOGIN2 p17
#define MBED_ANALOGIN3 p18
#define MBED_ANALOGIN4 p19
#define MBED_ANALOGIN5 p20
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P0_11, ADC0_0, 0x02},
{P0_12, ADC0_1, 0x02},
{P0_13, ADC0_2, 0x02},
{P0_14, ADC0_3, 0x02},
{P0_15, ADC0_4, 0x02},
{P0_16, ADC0_5, 0x01},
{P0_22, ADC0_6, 0x01},
{P0_23, ADC0_7, 0x01},
{NC , NC , 0 }
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P0_5, I2C_0, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P0_4, I2C_0, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_13, UART_0, 3},
{P1_27, UART_0, 2},
{ NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_14, UART_0, 3},
{P1_26, UART_0, 2},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P0_10, SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P1_15, SPI_1, 0x03},
{P1_20, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_19, SPI_1, 0x02},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
/************PWM***************/
/* To have a PWM where we can change both the period and the duty cycle,
* we need an entire timer. With the following conventions:
* * MR3 is used for the PWM period
* * MR0, MR1, MR2 are used for the duty cycle
*/
const PinMap PinMap_PWM[] = {
/* CT16B0 */
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
/* CT16B1 */
{P0_21, PWM_4, 1}, /* MR0 */
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
/* CT32B0 */
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
/* CT32B1 */
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
{NC, NC, 0}
};

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// mbed DIP Pin Names
p5 = P0_9,
p6 = P0_8,
p7 = P1_29,
p8 = P0_2,
p9 = P1_27,
p10 = P1_26,
p11 = P1_22,
p12 = P1_21,
p13 = P1_20,
p14 = P1_23,
p15 = P0_11,
p16 = P0_12,
p17 = P0_13,
p18 = P0_14,
p19 = P0_16,
p20 = P0_22,
p21 = P0_7,
p22 = P0_17,
p23 = P1_17,
p24 = P1_18,
p25 = P1_24,
p26 = P1_25,
p27 = P0_4,
p28 = P0_5,
p29 = P1_5,
p30 = P1_2,
p33 = P0_3,
p34 = P1_15,
p35 = P0_20,
p36 = P0_21,
// Other mbed Pin Names
LED1 = P1_8,
LED2 = P1_9,
LED3 = P1_10,
LED4 = P1_11,
USBTX = P0_19,
USBRX = P0_18,
// for Arch V1.1
D0 = P0_18,
D1 = P0_19,
D2 = P0_17,
D3 = P1_17,
D4 = P1_18,
D5 = P1_24,
D6 = P1_25,
D7 = P1_5,
D8 = P1_26,
D9 = P1_27,
D10 = P0_2,
D11 = P0_9, // P1_29 for Arch V1.0
D12 = P0_8,
D13 = P1_29, // P0_9 for Arch V1.0
D14 = P0_5,
D15 = P0_4,
A0 = P0_11,
A1 = P0_12,
A2 = P0_13,
A3 = P0_14,
A4 = P0_16,
A5 = P0_22,
I2C_SCL = D15,
I2C_SDA = D14,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX UART_TX
#define STDIO_UART_RX UART_RX
#define STDIO_UART UART_0
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P0_11, ADC0_0, 0x02},
{P0_12, ADC0_1, 0x02},
{P0_13, ADC0_2, 0x02},
{P0_14, ADC0_3, 0x02},
{P0_15, ADC0_4, 0x02},
{P0_16, ADC0_5, 0x01},
{P0_22, ADC0_6, 0x01},
{P0_23, ADC0_7, 0x01},
{NC , NC , 0 }
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P0_5, I2C_0, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P0_4, I2C_0, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_13, UART_0, 3},
{P1_27, UART_0, 2},
{ NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_14, UART_0, 3},
{P1_26, UART_0, 2},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P0_10, SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P1_15, SPI_1, 0x03},
{P1_20, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_19, SPI_1, 0x02},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
/************PWM***************/
/* To have a PWM where we can change both the period and the duty cycle,
* we need an entire timer. With the following conventions:
* * MR3 is used for the PWM period
* * MR0, MR1, MR2 are used for the duty cycle
*/
const PinMap PinMap_PWM[] = {
/* CT16B0 */
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
/* CT16B1 */
{P0_21, PWM_4, 1}, /* MR0 */
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
/* CT32B0 */
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
/* CT32B1 */
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
{NC, NC, 0}
};

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@ -1,138 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// Other mbed Pin Names
LED1 = P0_7,
LED2 = P0_7,
LED3 = P0_7,
LED4 = P0_7,
UART_TX = P0_19,
UART_RX = P0_18,
// Not connected
NC = (int)0xFFFFFFFF,
// Standard but not supported pins
USBTX = NC,
USBRX = NC,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

40
targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U34_421/device.h
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@ -1,40 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PeripheralNames.h
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@ -1,71 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX UART_TX
#define STDIO_UART_RX UART_RX
#define STDIO_UART UART_0
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PeripheralPins.c
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@ -1,117 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P0_11, ADC0_0, 0x02},
{P0_12, ADC0_1, 0x02},
{P0_13, ADC0_2, 0x02},
{P0_14, ADC0_3, 0x02},
{P0_15, ADC0_4, 0x02},
{P0_16, ADC0_5, 0x01},
{P0_22, ADC0_6, 0x01},
{P0_23, ADC0_7, 0x01},
{NC , NC , 0 }
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P0_5, I2C_0, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P0_4, I2C_0, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_13, UART_0, 3},
{P1_27, UART_0, 2},
{ NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_14, UART_0, 3},
{P1_26, UART_0, 2},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P0_10, SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P1_15, SPI_1, 0x03},
{P1_20, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_19, SPI_1, 0x02},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
/************PWM***************/
/* To have a PWM where we can change both the period and the duty cycle,
* we need an entire timer. With the following conventions:
* * MR3 is used for the PWM period
* * MR0, MR1, MR2 are used for the duty cycle
*/
const PinMap PinMap_PWM[] = {
/* CT16B0 */
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
/* CT16B1 */
{P0_21, PWM_4, 1}, /* MR0 */
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
/* CT32B0 */
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
/* CT32B1 */
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
{NC, NC, 0}
};

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/PinNames.h
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@ -1,166 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// mbed DIP Pin Names
p3 = P0_7,
p4 = P0_8,
p5 = P0_9,
p6 = P0_10,
p7 = P0_22,
p8 = P0_11,
p9 = P0_12,
p10 = P0_13,
p11 = P0_14,
p12 = P0_15,
p13 = P0_16,
p14 = P0_23,
p15 = P1_15,
p16 = P0_17,
p17 = P0_18,
p18 = P0_19,
p19 = P0_1,
p20 = P1_19,
p21 = P0_0,
p22 = P0_20,
p23 = P0_2,
p24 = P0_3,
p25 = P0_4,
p26 = P0_5,
p27 = P0_21,
p28 = P0_6,
// Other mbed Pin Names
LED1 = P0_7,
LED2 = P0_7,
LED3 = P0_7,
LED4 = P0_7,
UART_TX = P0_19,
UART_RX = P0_18,
// Not connected
NC = (int)0xFFFFFFFF,
// Standard but not supported pins
USBTX = NC,
USBRX = NC,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U35_401/device.h
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@ -1,40 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralNames.h
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@ -1,71 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX UART_TX
#define STDIO_UART_RX UART_RX
#define STDIO_UART UART_0
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/PeripheralPins.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P0_11, ADC0_0, 0x02},
{P0_12, ADC0_1, 0x02},
{P0_13, ADC0_2, 0x02},
{P0_14, ADC0_3, 0x02},
{P0_15, ADC0_4, 0x02},
{P0_16, ADC0_5, 0x01},
{P0_22, ADC0_6, 0x01},
{P0_23, ADC0_7, 0x01},
{NC , NC , 0 }
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P0_5, I2C_0, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P0_4, I2C_0, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_13, UART_0, 3},
{P1_27, UART_0, 2},
{ NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_14, UART_0, 3},
{P1_26, UART_0, 2},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P0_10, SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P1_15, SPI_1, 0x03},
{P1_20, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_19, SPI_1, 0x02},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
/************PWM***************/
/* To have a PWM where we can change both the period and the duty cycle,
* we need an entire timer. With the following conventions:
* * MR3 is used for the PWM period
* * MR0, MR1, MR2 are used for the duty cycle
*/
const PinMap PinMap_PWM[] = {
/* CT16B0 */
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
/* CT16B1 */
{P0_21, PWM_4, 1}, /* MR0 */
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
/* CT32B0 */
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
/* CT32B1 */
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
{NC, NC, 0}
};

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// LED Names
LED1 = P1_24,
LED2 = P1_25,
LED3 = P1_26,
LED4 = P0_0,
LED5 = P1_3,
LED6 = P1_2,
LED7 = P1_1,
LED8 = P1_0,
// BTN Names
BTN1 = P0_16,
BTN2 = P0_1,
// Standardized button names
BUTTON1 = BTN1,
BUTTON2 = BTN2,
// UART
UART_TX = P0_19,
UART_RX = P0_18,
// Arduino Shield Receptacles Names
D0 = P0_18,
D1 = P0_19,
D2 = P1_17,
D3 = P1_24,
D4 = P1_5,
D5 = P0_1,
D6 = P1_27,
D7 = P0_7,
D8 = P0_2,
D9 = P1_25,
D10= P1_23,
D11= P0_21,
D12= P0_22,
D13= P1_15,
D14= P0_5,
D15= P0_4,
A0 = P0_11,
A1 = P0_12,
A2 = P0_13,
A3 = P0_16,
A4 = P0_5, // same port as SDA
A5 = P0_4, // same port as SCL
SDA= P0_5, // same port as A4
SCL= P0_4, // same port as A5
//SD Card pins
SDMOSI = P0_9,
SDMISO = P0_8,
SDSCLK = P1_29,
SDSSEL = P1_12,
// Not connected
NC = (int)0xFFFFFFFF,
// Standard but not supported pins
USBTX = NC,
USBRX = NC,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPC11U37H_401/device.h
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@ -1,40 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PeripheralNames.h
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@ -1,71 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX UART_TX
#define STDIO_UART_RX UART_RX
#define STDIO_UART UART_0
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P0_11, ADC0_0, 0x02},
{P0_12, ADC0_1, 0x02},
{P0_13, ADC0_2, 0x02},
{P0_14, ADC0_3, 0x02},
{P0_15, ADC0_4, 0x02},
{P0_16, ADC0_5, 0x01},
{P0_22, ADC0_6, 0x01},
{P0_23, ADC0_7, 0x01},
{NC , NC , 0 }
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P0_5, I2C_0, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P0_4, I2C_0, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_13, UART_0, 3},
{P1_27, UART_0, 2},
{ NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_14, UART_0, 3},
{P1_26, UART_0, 2},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P0_10, SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P1_15, SPI_1, 0x03},
{P1_20, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_19, SPI_1, 0x02},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
/************PWM***************/
/* To have a PWM where we can change both the period and the duty cycle,
* we need an entire timer. With the following conventions:
* * MR3 is used for the PWM period
* * MR0, MR1, MR2 are used for the duty cycle
*/
const PinMap PinMap_PWM[] = {
/* CT16B0 */
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
/* CT16B1 */
{P0_21, PWM_4, 1}, /* MR0 */
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
/* CT32B0 */
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
/* CT32B1 */
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
{NC, NC, 0}
};

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// Other mbed Pin Names
LED1 = P1_19,
LED2 = P1_19, // Negative On
LED3 = P1_19,
LED4 = P1_19,
UART_TX = P0_19,
UART_RX = P0_18,
// Not connected
NC = (int)0xFFFFFFFF,
// Standard but not supported pins
USBTX = NC,
USBRX = NC,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_LPCCAPPUCCINO/device.h
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@ -1,40 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

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targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/PeripheralNames.h
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@ -1,71 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)LPC_USART_BASE
} UARTName;
typedef enum {
I2C_0 = (int)LPC_I2C_BASE
} I2CName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2,
ADC0_3,
ADC0_4,
ADC0_5,
ADC0_6,
ADC0_7
} ADCName;
typedef enum {
SPI_0 = (int)LPC_SSP0_BASE,
SPI_1 = (int)LPC_SSP1_BASE
} SPIName;
typedef enum {
PWM_1 = 0,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
PWM_8,
PWM_9,
PWM_10,
PWM_11
} PWMName;
#define STDIO_UART_TX UART_TX
#define STDIO_UART_RX UART_RX
#define STDIO_UART UART_0
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P0_11, ADC0_0, 0x02},
{P0_12, ADC0_1, 0x02},
{P0_13, ADC0_2, 0x02},
{P0_14, ADC0_3, 0x02},
{P0_15, ADC0_4, 0x02},
{P0_16, ADC0_5, 0x01},
{P0_22, ADC0_6, 0x01},
{P0_23, ADC0_7, 0x01},
{NC , NC , 0 }
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P0_5, I2C_0, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P0_4, I2C_0, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P0_19, UART_0, 1},
{P1_13, UART_0, 3},
{P1_27, UART_0, 2},
{ NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P0_18, UART_0, 1},
{P1_14, UART_0, 3},
{P1_26, UART_0, 2},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P0_6 , SPI_0, 0x02},
{P0_10, SPI_0, 0x02},
{P1_29, SPI_0, 0x01},
{P1_15, SPI_1, 0x03},
{P1_20, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P0_9 , SPI_0, 0x01},
{P0_21, SPI_1, 0x02},
{P1_22, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_8 , SPI_0, 0x01},
{P0_22, SPI_1, 0x03},
{P1_21, SPI_1, 0x02},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_2 , SPI_0, 0x01},
{P1_19, SPI_1, 0x02},
{P1_23, SPI_1, 0x02},
{NC , NC , 0}
};
/************PWM***************/
/* To have a PWM where we can change both the period and the duty cycle,
* we need an entire timer. With the following conventions:
* * MR3 is used for the PWM period
* * MR0, MR1, MR2 are used for the duty cycle
*/
const PinMap PinMap_PWM[] = {
/* CT16B0 */
{P0_8 , PWM_1, 2}, {P1_13, PWM_1, 2}, /* MR0 */
{P0_9 , PWM_2, 2}, {P1_14, PWM_2, 2}, /* MR1 */
{P0_10, PWM_3, 3}, {P1_15, PWM_3, 2}, /* MR2 */
/* CT16B1 */
{P0_21, PWM_4, 1}, /* MR0 */
{P0_22, PWM_5, 2}, {P1_23, PWM_5, 1}, /* MR1 */
/* CT32B0 */
{P0_18, PWM_6, 2}, {P1_24, PWM_6, 1}, /* MR0 */
{P0_19, PWM_7, 2}, {P1_25, PWM_7, 1}, /* MR1 */
{P0_1 , PWM_8, 2}, {P1_26, PWM_8, 1}, /* MR2 */
/* CT32B1 */
{P0_13, PWM_9 , 3}, {P1_0, PWM_9 , 1}, /* MR0 */
{P0_14, PWM_10, 3}, {P1_1, PWM_10, 1}, /* MR1 */
{P0_15, PWM_11, 3}, {P1_2, PWM_11, 1}, /* MR2 */
{NC, NC, 0}
};

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@ -1,181 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// mbed DIP Pin Names
// CN1-1 (GND)
// CN1-2 (EXTPOWER)
// CN1-3 (NC)
p4 = P0_0, // CN1-4
p5 = P0_9, // CN1-5
p6 = P0_8, // CN1-6
p7 = P0_10, // CN1-7
p8 = P0_7, // CN1-8
p9 = P0_19, // CN1-9
p10 = P0_18, // CN1-10
p11 = P0_21, // CN1-11
p12 = P0_22, // CN1-12
p13 = P1_15, // CN1-13
p14 = P0_6, // CN1-14
p15 = P0_11, // CN1-15
p16 = P0_12, // CN1-16
p17 = P0_13, // CN1-17
p18 = P0_14, // CN1-18
p19 = P0_15, // CN1-19
p20 = P0_16, // CN1-20
p21 = P0_14, // CN2-20
p22 = P0_2, // CN2-19
p23 = P0_23, // CN2-18
p24 = P0_17, // CN2-17
p25 = P0_20, // CN2-16
p26 = P1_15, // CN2-15
p27 = P0_4, // CN2-14
p28 = P0_5, // CN2-13
p29 = P1_19, // CN2-12
p30 = P0_1, // CN2-11
// CN2-10 (D+USB)
// CN2-9 (D-USB)
p33 = P0_3, // CN2-8 (USB-VBUS)
// CN2-7 (NC)
// CN2-6 (NC)
// CN2-5 (NC)
// CN2-4 (NC)
// CN2-3 (NC)
// CN2-2 (VDD)
// CN2-1 (VDD)
// Other mbed Pin Names
LED1 = P0_20,
LED2 = P0_21,
LED3 = P0_20,
LED4 = P0_21,
UART_TX = P0_19,
UART_RX = P0_18,
// Not connected
NC = (int)0xFFFFFFFF,
// Standard but not supported pins
USBTX = NC,
USBRX = NC,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

40
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@ -1,40 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

184
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@ -1,184 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// mbed DIP Pin Names
// CN1-1 (GND)
// CN1-2 (EXTPOWER)
// CN1-3 (NC)
p4 = P0_0, // CN1-4
p5 = P0_9, // CN1-5
p6 = P0_8, // CN1-6
p7 = P0_10, // CN1-7
p8 = P0_7, // CN1-8
p9 = P0_19, // CN1-9
p10 = P0_18, // CN1-10
p11 = P0_21, // CN1-11
p12 = P0_22, // CN1-12
p13 = P1_15, // CN1-13
p14 = P0_6, // CN1-14
p15 = P0_11, // CN1-15
p16 = P0_12, // CN1-16
p17 = P0_13, // CN1-17
p18 = P0_14, // CN1-18
p19 = P0_15, // CN1-19
p20 = P0_16, // CN1-20
p21 = P0_14, // CN2-20
p22 = P0_2, // CN2-19
p23 = P0_23, // CN2-18
p24 = P0_17, // CN2-17
p25 = P0_20, // CN2-16
p26 = P1_15, // CN2-15
p27 = P0_4, // CN2-14
p28 = P0_5, // CN2-13
p29 = P1_19, // CN2-12
p30 = P0_1, // CN2-11
// CN2-10 (D+USB)
// CN2-9 (D-USB)
p33 = P0_3, // CN2-8 (USB-VBUS)
// CN2-7 (NC)
// CN2-6 (NC)
// CN2-5 (NC)
// CN2-4 (NC)
// CN2-3 (NC)
// CN2-2 (VDD)
// CN2-1 (VDD)
// Other mbed Pin Names
LED1 = P0_20, // GREEN LED
LED2 = P0_11, // RED LED
LED3 = P0_21, // BLUE LED
LED4 = P0_20, // repeat LED1
UART_TX = P0_19,
UART_RX = P0_18,
I2C_SCL = P0_4,
I2C_SDA = P0_5,
// Not connected
NC = (int)0xFFFFFFFF,
// Standard but not supported pins
USBTX = NC,
USBRX = NC,
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

40
targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_501_IBDAP/device.h
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@ -1,40 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

140
targets/TARGET_NXP/TARGET_LPC11UXX/TARGET_MCU_LPC11U35_501/TARGET_LPC11U35_Y5_MBUG/PinNames.h
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@ -1,140 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2014 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 5
typedef enum {
// LPC11U Pin Names
P0_0 = 0,
P0_1 = 1,
P0_2 = 2,
P0_3 = 3,
P0_4 = 4,
P0_5 = 5,
P0_6 = 6,
P0_7 = 7,
P0_8 = 8,
P0_9 = 9,
P0_10 = 10,
P0_11 = 11,
P0_12 = 12,
P0_13 = 13,
P0_14 = 14,
P0_15 = 15,
P0_16 = 16,
P0_17 = 17,
P0_18 = 18,
P0_19 = 19,
P0_20 = 20,
P0_21 = 21,
P0_22 = 22,
P0_23 = 23,
P0_24 = 24,
P0_25 = 25,
P0_26 = 26,
P0_27 = 27,
P1_0 = 32,
P1_1 = 33,
P1_2 = 34,
P1_3 = 35,
P1_4 = 36,
P1_5 = 37,
P1_6 = 38,
P1_7 = 39,
P1_8 = 40,
P1_9 = 41,
P1_10 = 42,
P1_11 = 43,
P1_12 = 44,
P1_13 = 45,
P1_14 = 46,
P1_15 = 47,
P1_16 = 48,
P1_17 = 49,
P1_18 = 50,
P1_19 = 51,
P1_20 = 52,
P1_21 = 53,
P1_22 = 54,
P1_23 = 55,
P1_24 = 56,
P1_25 = 57,
P1_26 = 58,
P1_27 = 59,
P1_28 = 60,
P1_29 = 61,
P1_31 = 63,
// Not connected
NC = (int)0xFFFFFFFF,
// Other mbed Pin Names
LED1 = P0_20, //Approved
LED2 = P0_9, //Approved
LED3 = P0_11, //Approved
LED4 = NC,
UART_TX = P0_19,
UART_RX = P0_18,
// Standard but not supported pins
USBTX = NC,
USBRX = NC
} PinName;
typedef enum {
CHANNEL0 = FLEX_INT0_IRQn,
CHANNEL1 = FLEX_INT1_IRQn,
CHANNEL2 = FLEX_INT2_IRQn,
CHANNEL3 = FLEX_INT3_IRQn,
CHANNEL4 = FLEX_INT4_IRQn,
CHANNEL5 = FLEX_INT5_IRQn,
CHANNEL6 = FLEX_INT6_IRQn,
CHANNEL7 = FLEX_INT7_IRQn
} Channel;
typedef enum {
PullUp = 2,
PullDown = 1,
PullNone = 0,
Repeater = 3,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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