diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/LPC11U68.sct b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/LPC11U68.sct new file mode 100644 index 0000000000..8a9325406a --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/LPC11U68.sct @@ -0,0 +1,13 @@ + +LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k) + ER_IROM1 0x00000000 0x40000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ; 8_byte_aligned(16+47 vect * 4 bytes) = 0x100 + ; 32kB (0x8000) - 0x100 = 0x7F00 + RW_IRAM1 (0x10000000+0x100) (0x8000-0x100) { + .ANY (+RW +ZI) + } +} diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.s b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.s new file mode 100644 index 0000000000..7a331f18c6 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.s @@ -0,0 +1,244 @@ +;/**************************************************************************//** +; * @file startup_LPC11U6x.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * NXP LPC11U6x Device Series +; * @version V1.00 +; * @date 22. October 2013 +; * +; * @note +; * Copyright (C) 2013 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +__initial_sp EQU 0x10008000 ; Top of RAM from LPC1U68 + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PIN_INT0_IRQHandler ; 16+ 0 GPIO pin interrupt 0 + DCD PIN_INT1_IRQHandler ; 16+ 1 GPIO pin interrupt 1 + DCD PIN_INT2_IRQHandler ; 16+ 2 GPIO pin interrupt 2 + DCD PIN_INT3_IRQHandler ; 16+ 3 GPIO pin interrupt 3 + DCD PIN_INT4_IRQHandler ; 16+ 4 GPIO pin interrupt 4 + DCD PIN_INT5_IRQHandler ; 16+ 5 GPIO pin interrupt 5 + DCD PIN_INT6_IRQHandler ; 16+ 6 GPIO pin interrupt 6 + DCD PIN_INT7_IRQHandler ; 16+ 7 GPIO pin interrupt 7 + DCD GINT0_IRQHandler ; 16+ 8 GPIO GROUP0 interrupt + DCD GINT1_IRQHandler ; 16+ 9 GPIO GROUP1 interrupt + DCD I2C1_IRQHandler ; 16+10 I2C1 interrupt + DCD USART1_4_IRQHandler ; 16+11 Combined USART1 and USART4 interrupts + DCD USART2_3_IRQHandler ; 16+12 Combined USART2 and USART3 interrupts + DCD SCT0_1_IRQHandler ; 16+13 Combined SCT0 and SCT1 interrupts + DCD SSP1_IRQHandler ; 16+14 SSP1 interrupt + DCD I2C0_IRQHandler ; 16+15 I2C0 interrupt + DCD CT16B0_IRQHandler ; 16+16 CT16B0 interrupt + DCD CT16B1_IRQHandler ; 16+17 CT16B1 interrupt + DCD CT32B0_IRQHandler ; 16+18 CT32B0 interrupt + DCD CT32B1_IRQHandler ; 16+19 CT32B1 interrupt + DCD SSP0_IRQHandler ; 16+20 SSP0 interrupt + DCD USART0_IRQHandler ; 16+21 USART0 interrupt + DCD USB_IRQHandler ; 16+22 USB interrupt + DCD USB_FIQ_IRQHandler ; 16+23 USB_FIQ interrupt + DCD ADC_A_IRQHandler ; 16+24 Combined ADC_A end-of-sequence A and threshold crossing interrupts + DCD RTC_IRQHandler ; 16+25 RTC interrupt + DCD BOD_WDT_IRQHandler ; 16+26 Combined BOD and WWDT interrupt + DCD FLASH_IRQHandler ; 16+27 Combined flash and EEPROM controller interrupts + DCD DMA_IRQHandler ; 16+28 DMA interrupt + DCD ADC_B_IRQHandler ; 16+29 Combined ADC_A end-of-sequence A and threshold crossing interrupts + DCD USBWAKEUP_IRQHandler ; 16+30 USB_WAKEUP interrupt + DCD 0 ; 16+31 Reserved + +; Code Read Protection +; Code Read Protection <0xFFFFFFFF=>CRP Disabled +; <0x12345678=>CRP Level 1 +; <0x87654321=>CRP Level 2 +; <0x43218765=>CRP Level 3 (ARE YOU SURE?) +; <0x4E697370=>NO ISP (ARE YOU SURE?) +; + IF :LNOT::DEF:NO_CRP + AREA |.ARM.__at_0x02FC|, CODE, READONLY + DCD 0xFFFFFFFF + ENDIF + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Reserved_IRQHandler PROC + EXPORT Reserved_IRQHandler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PIN_INT0_IRQHandler [WEAK] + EXPORT PIN_INT1_IRQHandler [WEAK] + EXPORT PIN_INT2_IRQHandler [WEAK] + EXPORT PIN_INT3_IRQHandler [WEAK] + EXPORT PIN_INT4_IRQHandler [WEAK] + EXPORT PIN_INT5_IRQHandler [WEAK] + EXPORT PIN_INT6_IRQHandler [WEAK] + EXPORT PIN_INT7_IRQHandler [WEAK] + EXPORT GINT0_IRQHandler [WEAK] + EXPORT GINT1_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT USART1_4_IRQHandler [WEAK] + EXPORT USART2_3_IRQHandler [WEAK] + EXPORT SCT0_1_IRQHandler [WEAK] + EXPORT SSP1_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT CT16B0_IRQHandler [WEAK] + EXPORT CT16B1_IRQHandler [WEAK] + EXPORT CT32B0_IRQHandler [WEAK] + EXPORT CT32B1_IRQHandler [WEAK] + EXPORT SSP0_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + EXPORT USB_FIQ_IRQHandler [WEAK] + EXPORT ADC_A_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT BOD_WDT_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT DMA_IRQHandler [WEAK] + EXPORT ADC_B_IRQHandler [WEAK] + EXPORT USBWAKEUP_IRQHandler [WEAK] + +PIN_INT0_IRQHandler +PIN_INT1_IRQHandler +PIN_INT2_IRQHandler +PIN_INT3_IRQHandler +PIN_INT4_IRQHandler +PIN_INT5_IRQHandler +PIN_INT6_IRQHandler +PIN_INT7_IRQHandler +GINT0_IRQHandler +GINT1_IRQHandler +I2C1_IRQHandler +USART1_4_IRQHandler +USART2_3_IRQHandler +SCT0_1_IRQHandler +SSP1_IRQHandler +I2C0_IRQHandler +CT16B0_IRQHandler +CT16B1_IRQHandler +CT32B0_IRQHandler +CT32B1_IRQHandler +SSP0_IRQHandler +USART0_IRQHandler +USB_IRQHandler +USB_FIQ_IRQHandler +ADC_A_IRQHandler +RTC_IRQHandler +BOD_WDT_IRQHandler +FLASH_IRQHandler +DMA_IRQHandler +ADC_B_IRQHandler +USBWAKEUP_IRQHandler + + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + END diff --git a/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/sys.cpp b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..2f1024ace8 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,31 @@ +/* mbed Microcontroller Library - stackheap + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +extern char Image$$RW_IRAM1$$ZI$$Limit[]; + +extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit; + uint32_t sp_limit = __current_sp(); + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/workspace_tools/build_release.py b/workspace_tools/build_release.py index 2c0a3c19c9..a9dd056c8a 100755 --- a/workspace_tools/build_release.py +++ b/workspace_tools/build_release.py @@ -83,7 +83,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = ( ('RBLAB_BLENANO', ('ARM', 'GCC_ARM')), ('WALLBOT_BLE', ('ARM', 'GCC_ARM')), - ('LPC11U68', ('uARM','GCC_ARM','GCC_CR', 'IAR')), + ('LPC11U68', ('ARM', 'uARM','GCC_ARM','GCC_CR', 'IAR')), ('OC_MBUINO', ('ARM', 'uARM', 'GCC_ARM', 'IAR')), ('RZ_A1H' , ('ARM',)), diff --git a/workspace_tools/export/uvision4.py b/workspace_tools/export/uvision4.py index 8c5f4b734e..7c62043ebe 100644 --- a/workspace_tools/export/uvision4.py +++ b/workspace_tools/export/uvision4.py @@ -54,6 +54,7 @@ class Uvision4(Exporter): 'NUCLEO_L152RE', 'UBLOX_C027', 'LPC1549', + 'LPC11U68', # Removed as uvision4_lpc11u35_501.uvproj.tmpl is missing. #'LPC11U35_501', 'NRF51822', @@ -90,6 +91,7 @@ class Uvision4(Exporter): 'NUCLEO_L053R8', 'NUCLEO_L152RE', 'LPC1549', + 'LPC11U68', 'LPC11U35_501', 'KL05Z', 'LPC11U37H_401', diff --git a/workspace_tools/export/uvision4_lpc11u68.uvopt.tmpl b/workspace_tools/export/uvision4_lpc11u68.uvopt.tmpl new file mode 100644 index 0000000000..b72496665f --- /dev/null +++ b/workspace_tools/export/uvision4_lpc11u68.uvopt.tmpl @@ -0,0 +1,181 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + mbed NXP LPC11U68 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + SARMCM3.DLL + + DARMP1.DLL + -pLPC11U14 + SARMCM3.DLL + + TARMP1.DLL + -pLPC11U14 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 14 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"MBED CMSIS-DAP" -UA000000001 -O206 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -FO15 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000 + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + src + 1 + 0 + 0 + + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 1 + 2 + 0 + main.cpp + main.cpp + + + + diff --git a/workspace_tools/export/uvision4_lpc11u68.uvproj.tmpl b/workspace_tools/export/uvision4_lpc11u68.uvproj.tmpl new file mode 100644 index 0000000000..45c58a1454 --- /dev/null +++ b/workspace_tools/export/uvision4_lpc11u68.uvproj.tmpl @@ -0,0 +1,419 @@ + + + + 1.1 + +
###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision
+ + + + mbed NXP LPC11U68 + 0x4 + ARM-ADS + + + LPC11U68 + NXP + IRAM(0x10000000-0x10001FFF) IRAM2(0x20004000-0x200047FF) IROM(0-0x1FFFF) CLOCK(12000000) CPUTYPE("Cortex-M0+") + + "STARTUP\NXP\LPC11Uxx\startup_LPC11Uxx.s" ("NXP LPC11Uxx Startup Code") + UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000) + 5738 + LPC11Uxx.h + + + + + + + + + + SFD\NXP\LPC11Uxx\LPC11Uxx.SFR + 0 + + + + NXP\LPC11Uxx\ + NXP\LPC11Uxx\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + {{name}} + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 1 + 1 + $K\ARM\BIN\ELFDWT.EXE "!L" + fromelf --bin -o {{name}}_LPC11U68.bin build\{{name}}.axf + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMP1.DLL + -pLPC11U14 + SARMCM3.DLL + + TARMP1.DLL + -pLPC11U68 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0+" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x2000 + + + 1 + 0x0 + 0x20000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x20000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x2000 + + + 0 + 0x20004000 + 0x800 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + {% for flag in flags %}{{flag}} {% endfor %} + {% for s in symbols %} {{s}}, {% endfor %} + + {% for path in include_paths %} {{path}}; {% endfor %} + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + {{scatter_file}} + + + + {% for file in object_files %} + {{file}} + {% endfor %} + + + + + + + + {% for group,files in source_files %} + + {{group}} + + {% for file in files %} + + {{file.name}} + {{file.type}} + {{file.path}} + {%if file.type == "1" %} + + + + + --c99 + + + + + {% endif %} + + {% endfor %} + + + {% endfor %} + + + + + diff --git a/workspace_tools/targets.py b/workspace_tools/targets.py index 93bb647971..2cd2cd64d7 100644 --- a/workspace_tools/targets.py +++ b/workspace_tools/targets.py @@ -187,7 +187,7 @@ class LPC11U68(LPCTarget): LPCTarget.__init__(self) self.core = "Cortex-M0+" self.extra_labels = ['NXP', 'LPC11U6X'] - self.supported_toolchains = ["uARM", "GCC_CR", "GCC_ARM", "IAR"] + self.supported_toolchains = ["ARM", "uARM", "GCC_CR", "GCC_ARM", "IAR"] self.default_toolchain = "uARM" self.supported_form_factors = ["ARDUINO"] self.detect_code = ["1168"]