diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c index 89448ceed8..81e69fd88d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.c @@ -147,8 +147,6 @@ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9} * @{ */ -void SetSysClock(void); - #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) uint8_t SetSysClock_PLL_HSE(uint8_t bypass); #endif @@ -223,15 +221,15 @@ void SystemInit (void) #endif /* DATA_IN_ExtSRAM */ #endif - /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); - #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); } /** @@ -609,3 +607,4 @@ uint8_t SetSysClock_PLL_HSI(void) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.h index 6c726a13ee..1746a61a02 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/system_stm32f10x.h @@ -93,6 +93,8 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc extern void SystemInit(void); extern void SystemCoreClockUpdate(void); +extern void SetSysClock(void); + /** * @} */ diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralNames.h b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralNames.h index 2a42e71288..48dcb1480f 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralNames.h +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/PeripheralNames.h @@ -37,13 +37,13 @@ extern "C" { #endif typedef enum { - ADC_1 = (int)ADC1_BASE, - ADC_2 = (int)ADC2_BASE + ADC_1 = (int)ADC1_BASE } ADCName; typedef enum { UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE } UARTName; #define STDIO_UART_TX PA_2 @@ -61,6 +61,7 @@ typedef enum { } I2CName; typedef enum { + PWM_1 = (int)TIM1_BASE, PWM_2 = (int)TIM2_BASE, PWM_3 = (int)TIM3_BASE, PWM_4 = (int)TIM4_BASE diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/analogin_api.c index 538a89fd24..50265be7df 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/analogin_api.c @@ -35,12 +35,22 @@ #include "error.h" static const PinMap PinMap_ADC[] = { - {PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, - {PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, + {PA_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN0 + {PA_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN1 + {PA_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN2 + {PA_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN3 + {PA_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN4 + {PA_5, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN5 + {PA_6, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN6 + {PA_7, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN7 + {PB_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN8 + {PB_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN9 + {PC_0, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN10 + {PC_1, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN11 + {PC_2, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN12 + {PC_3, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN13 + {PC_4, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN14 + {PC_5, ADC_1, STM_PIN_DATA(GPIO_Mode_AIN, 0)}, // ADC12_IN15 {NC, NC, 0} }; @@ -51,7 +61,7 @@ void analogin_init(analogin_t *obj, PinName pin) { ADC_TypeDef *adc; ADC_InitTypeDef ADC_InitStructure; - // Get the peripheral name (ADC_1, ADC_2...) from the pin and assign it to the object + // Get the peripheral name from the pin and assign it to the object obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); if (obj->adc == (ADCName)NC) { @@ -71,17 +81,18 @@ void analogin_init(analogin_t *obj, PinName pin) { // Get ADC registers structure address adc = (ADC_TypeDef *)(obj->adc); - // Enable ADC clock - RCC_ADCCLKConfig(RCC_PCLK2_Div4); + // Enable ADC clock (14 MHz maximum) + // PCLK2 = 64 MHz --> ADC clock = 64/6 = 10.666 MHz + RCC_ADCCLKConfig(RCC_PCLK2_Div6); RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); // Configure ADC - ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; - ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_InitStructure.ADC_ScanConvMode = DISABLE; ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; - ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; - ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStructure.ADC_NbrOfChannel = 1; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfChannel = 1; ADC_Init(adc, &ADC_InitStructure); // Enable ADC @@ -98,31 +109,64 @@ void analogin_init(analogin_t *obj, PinName pin) { static inline uint16_t adc_read(analogin_t *obj) { // Get ADC registers structure address ADC_TypeDef *adc = (ADC_TypeDef *)(obj->adc); + int channel = 0; // Configure ADC channel switch (obj->pin) { case PA_0: - ADC_RegularChannelConfig(adc, ADC_Channel_0, 1, ADC_SampleTime_7Cycles5); + channel = 0; break; case PA_1: - ADC_RegularChannelConfig(adc, ADC_Channel_1, 1, ADC_SampleTime_7Cycles5); + channel = 1; break; + case PA_2: + channel = 2; + break; + case PA_3: + channel = 3; + break; case PA_4: - ADC_RegularChannelConfig(adc, ADC_Channel_4, 1, ADC_SampleTime_7Cycles5); + channel = 4; break; + case PA_5: + channel = 5; + break; + case PA_6: + channel = 6; + break; + case PA_7: + channel = 7; + break; case PB_0: - ADC_RegularChannelConfig(adc, ADC_Channel_8, 1, ADC_SampleTime_7Cycles5); + channel = 8; + break; + case PB_1: + channel = 9; + break; + case PC_0: + channel = 10; break; case PC_1: - ADC_RegularChannelConfig(adc, ADC_Channel_11, 1, ADC_SampleTime_7Cycles5); + channel = 11; break; - case PC_0: - ADC_RegularChannelConfig(adc, ADC_Channel_10, 1, ADC_SampleTime_7Cycles5); + case PC_2: + channel = 12; break; + case PC_3: + channel = 13; + break; + case PC_4: + channel = 14; + break; + case PC_5: + channel = 15; + break; default: return 0; } + ADC_RegularChannelConfig(adc, channel, 1, ADC_SampleTime_7Cycles5); + ADC_SoftwareStartConvCmd(adc, ENABLE); // Start conversion while(ADC_GetFlagStatus(adc, ADC_FLAG_EOC) == RESET); // Wait end of conversion diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c index 9e12e30ce4..4d17b02b84 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/i2c_api.c @@ -42,12 +42,16 @@ #define LONG_TIMEOUT ((int)0x8000) static const PinMap PinMap_I2C_SDA[] = { - {PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 8)}, // GPIO_Remap_I2C1 + {PB_7, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 0)}, + {PB_9, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 2)}, // GPIO_Remap_I2C1 + {PB_11, I2C_2, STM_PIN_DATA(GPIO_Mode_AF_OD, 0)}, {NC, NC, 0} }; static const PinMap PinMap_I2C_SCL[] = { - {PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 8)}, // GPIO_Remap_I2C1 + {PB_6, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 0)}, + {PB_8, I2C_1, STM_PIN_DATA(GPIO_Mode_AF_OD, 2)}, // GPIO_Remap_I2C1 + {PB_10, I2C_2, STM_PIN_DATA(GPIO_Mode_AF_OD, 0)}, {NC, NC, 0} }; @@ -91,12 +95,12 @@ void i2c_frequency(i2c_t *obj, int hz) { I2C_DeInit(i2c); // I2C configuration - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = 0; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; + I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; + I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStructure.I2C_OwnAddress1 = 0; + I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = hz; + I2C_InitStructure.I2C_ClockSpeed = hz; I2C_Init(i2c, &I2C_InitStructure); I2C_Cmd(i2c, ENABLE); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/mbed_overrides.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/mbed_overrides.c index c0218bb69c..60d7941d83 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/mbed_overrides.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/mbed_overrides.c @@ -25,8 +25,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ - -extern void SystemCoreClockUpdate(void); +#include "cmsis.h" // This function is called after RAM initialization and before main. void mbed_sdk_init() { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c index 844157b482..83f2b38a93 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pinmap.c @@ -32,16 +32,18 @@ #include "error.h" // Alternate-function mapping -static const uint32_t AF_mapping[] = { - 0, // 0 = No AF - GPIO_Remap_SPI1, // 1 - GPIO_Remap_I2C1, // 2 - GPIO_Remap_USART1, // 3 - GPIO_Remap_USART2, // 4 - GPIO_FullRemap_TIM2, // 5 - GPIO_FullRemap_TIM3, // 6 - GPIO_PartialRemap_TIM3, // 7 - GPIO_Remap_I2C1 // 8 +#define AF_NUM (10) +static const uint32_t AF_mapping[AF_NUM] = { + 0, // 0 = No AF + GPIO_Remap_SPI1, // 1 + GPIO_Remap_I2C1, // 2 + GPIO_Remap_USART1, // 3 + GPIO_Remap_USART2, // 4 + GPIO_PartialRemap_USART3, // 5 + GPIO_PartialRemap_TIM1, // 6 + GPIO_PartialRemap_TIM3, // 7 + GPIO_FullRemap_TIM2, // 8 + GPIO_FullRemap_TIM3 // 9 }; // Enable GPIO clock and return GPIO base address @@ -93,7 +95,7 @@ void pin_function(PinName pin, int data) { // Configure Alternate Function // Warning: Must be done before the GPIO is initialized - if (afnum > 0) { + if ((afnum > 0) && (afnum < AF_NUM)) { GPIO_PinRemapConfig(AF_mapping[afnum], ENABLE); } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pwmout_api.c index c009314f60..8837f0a62d 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/pwmout_api.c @@ -33,13 +33,41 @@ #include "pinmap.h" #include "error.h" +// TIM4 cannot be used because already used by the us_ticker static const PinMap PinMap_PWM[] = { - // TIM2 full remap - {PB_3, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 5)}, // TIM2fr_CH2 - ARDUINO D3 - // TIM3 partial remap - {PB_4, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 7)}, // TIM3pr_CH1 - ARDUINO D5 - // TIM4 default - {PB_6, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH1 - ARDUINO D10 + {PA_1, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM2_CH2 - Default + {PA_2, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM2_CH3 - Default (warning: not connected on D1 per default) + {PA_3, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM2_CH4 - Default (warning: not connected on D0 per default) + {PA_6, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM3_CH1 - Default + {PA_7, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM3_CH2 - Default + //{PA_7, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 6)}, // TIM1_CH1N - GPIO_PartialRemap_TIM1 + {PA_8, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH1 - Default + {PA_9, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH2 - Default + {PA_10, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH3 - Default + {PA_11, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH4 - Default + {PA_15, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 8)}, // TIM2_CH1_ETR - GPIO_FullRemap_TIM2 + + {PB_0, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM3_CH3 - Default + //{PB_0, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 6)}, // TIM1_CH2N - GPIO_PartialRemap_TIM1 + {PB_1, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM3_CH4 - Default + //{PB_1, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 6)}, // TIM1_CH3N - GPIO_PartialRemap_TIM1 + {PB_3, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 8)}, // TIM2_CH2 - GPIO_FullRemap_TIM2 + {PB_4, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 7)}, // TIM3_CH1 - GPIO_PartialRemap_TIM3 + {PB_5, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 7)}, // TIM3_CH2 - GPIO_PartialRemap_TIM3 + //{PB_6, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH1 - Default (used by ticker) + //{PB_7, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH2 - Default (used by ticker) + //{PB_8, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH3 - Default (used by ticker) + //{PB_9, PWM_4, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM4_CH4 - Default (used by ticker) + {PB_10, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 8)}, // TIM2_CH3 - GPIO_FullRemap_TIM2 + {PB_11, PWM_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 8)}, // TIM2_CH4 - GPIO_FullRemap_TIM2 + {PB_13, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH1N - Default + {PB_14, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH2N - Default + {PB_15, PWM_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, // TIM1_CH3N - Default + + {PC_6, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 9)}, // TIM3_CH1 - GPIO_FullRemap_TIM3 + {PC_7, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 9)}, // TIM3_CH2 - GPIO_FullRemap_TIM3 + {PC_8, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 9)}, // TIM3_CH3 - GPIO_FullRemap_TIM3 + {PC_9, PWM_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 9)}, // TIM3_CH4 - GPIO_FullRemap_TIM3 {NC, NC, 0} }; @@ -52,6 +80,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) { } // Enable TIM clock + if (obj->pwm == PWM_1) RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE); if (obj->pwm == PWM_2) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); if (obj->pwm == PWM_3) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); if (obj->pwm == PWM_4) RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); @@ -83,22 +112,86 @@ void pwmout_write(pwmout_t* obj, float value) { obj->pulse = (uint32_t)((float)obj->period * value); - TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OCInitStructure.TIM_Pulse = obj->pulse; - TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; + TIM_OCInitStructure.TIM_Pulse = obj->pulse; + TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High; + TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset; - // Configure channel 1 - if ((obj->pin == PB_4) || (obj->pin == PB_6)) { - TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC1Init(tim, &TIM_OCInitStructure); - } - - // Configure channel 2 - if (obj->pin == PB_3) { - TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable); - TIM_OC2Init(tim, &TIM_OCInitStructure); + // Configure channels + switch (obj->pin) { + // Channels 1 + case PA_6: + case PA_8: + case PA_15: + case PB_4: + //case PB_6: + case PC_6: + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable); + TIM_OC1Init(tim, &TIM_OCInitStructure); + break; + // Channels 1N + //case PA_7: + case PB_13: + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; + TIM_OC1PreloadConfig(tim, TIM_OCPreload_Enable); + TIM_OC1Init(tim, &TIM_OCInitStructure); + break; + // Channels 2 + case PA_1: + case PA_7: + case PA_9: + case PB_3: + case PB_5: + //case PB_7: + case PC_7: + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable); + TIM_OC2Init(tim, &TIM_OCInitStructure); + break; + // Channels 2N + //case PB_0: + case PB_14: + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; + TIM_OC2PreloadConfig(tim, TIM_OCPreload_Enable); + TIM_OC2Init(tim, &TIM_OCInitStructure); + break; + // Channels 3 + case PA_2: + case PA_10: + case PB_0: + //case PB_8: + case PB_10: + case PC_8: + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OC3PreloadConfig(tim, TIM_OCPreload_Enable); + TIM_OC3Init(tim, &TIM_OCInitStructure); + break; + // Channels 3N + //case PB_1: + case PB_15: + TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable; + TIM_OC3PreloadConfig(tim, TIM_OCPreload_Enable); + TIM_OC3Init(tim, &TIM_OCInitStructure); + break; + // Channels 4 + case PA_3: + case PA_11: + case PB_1: + //case PB_9: + case PB_11: + case PC_9: + TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; + TIM_OC4PreloadConfig(tim, TIM_OCPreload_Enable); + TIM_OC4Init(tim, &TIM_OCInitStructure); + break; + default: + return; } + + TIM_CtrlPWMOutputs(tim, ENABLE); } float pwmout_read(pwmout_t* obj) { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c index 6d5eb9fbed..e152735238 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/serial_api.c @@ -34,20 +34,26 @@ #include static const PinMap PinMap_UART_TX[] = { - {PA_9, UART_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, {PA_2, UART_2, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, + {PA_9, UART_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, + {PB_6, UART_1, STM_PIN_DATA(GPIO_Mode_AF_PP, 3)}, // GPIO_Remap_USART1 + {PB_10, UART_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 0)}, + {PC_10, UART_3, STM_PIN_DATA(GPIO_Mode_AF_PP, 5)}, // GPIO_PartialRemap_USART3 {NC, NC, 0} }; static const PinMap PinMap_UART_RX[] = { - {PA_10, UART_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)}, {PA_3, UART_2, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)}, + {PA_10, UART_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)}, + {PB_7, UART_1, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 3)}, // GPIO_Remap_USART1 + {PB_11, UART_3, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 0)}, + {PC_11, UART_3, STM_PIN_DATA(GPIO_Mode_IN_FLOATING, 5)}, // GPIO_PartialRemap_USART3 {NC, NC, 0} }; -#define UART_NUM (2) +#define UART_NUM (3) -static uint32_t serial_irq_ids[UART_NUM] = {0}; +static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; static uart_irq_handler irq_handler; @@ -60,12 +66,12 @@ static void init_usart(serial_t *obj) { USART_Cmd(usart, DISABLE); - USART_InitStructure.USART_BaudRate = obj->baudrate; - USART_InitStructure.USART_WordLength = obj->databits; - USART_InitStructure.USART_StopBits = obj->stopbits; - USART_InitStructure.USART_Parity = obj->parity; + USART_InitStructure.USART_BaudRate = obj->baudrate; + USART_InitStructure.USART_WordLength = obj->databits; + USART_InitStructure.USART_StopBits = obj->stopbits; + USART_InitStructure.USART_Parity = obj->parity; USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_Init(usart, &USART_InitStructure); USART_Cmd(usart, ENABLE); @@ -90,7 +96,10 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { if (obj->uart == UART_2) { RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); } - + if (obj->uart == UART_3) { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); + } + // Configure the UART pins pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); @@ -106,6 +115,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) { // The index is used by irq if (obj->uart == UART_1) obj->index = 0; if (obj->uart == UART_2) obj->index = 1; + if (obj->uart == UART_3) obj->index = 2; // For stdio management if (obj->uart == STDIO_UART) { @@ -174,8 +184,15 @@ static void uart_irq(USART_TypeDef* usart, int id) { } } -static void uart1_irq(void) {uart_irq((USART_TypeDef*)UART_1, 0);} -static void uart2_irq(void) {uart_irq((USART_TypeDef*)UART_2, 1);} +static void uart1_irq(void) { + uart_irq((USART_TypeDef*)UART_1, 0); +} +static void uart2_irq(void) { + uart_irq((USART_TypeDef*)UART_2, 1); +} +static void uart3_irq(void) { + uart_irq((USART_TypeDef*)UART_3, 2); +} void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -196,6 +213,11 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { irq_n = USART2_IRQn; vector = (uint32_t)&uart2_irq; } + + if (obj->uart == UART_3) { + irq_n = USART3_IRQn; + vector = (uint32_t)&uart3_irq; + } if (enable) { diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c index 121cd6aaf9..4744d341f6 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_F103RB/us_ticker.c @@ -30,10 +30,9 @@ #include "PeripheralNames.h" // Timer selection: -#define TIM_MST TIM1 -#define TIM_MST_UP_IRQ TIM1_UP_IRQn -#define TIM_MST_OC_IRQ TIM1_CC_IRQn -#define TIM_MST_RCC RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE) +#define TIM_MST TIM4 +#define TIM_MST_IRQ TIM4_IRQn +#define TIM_MST_RCC RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE) static int us_ticker_inited = 0; static volatile uint32_t SlaveCounter = 0; @@ -47,35 +46,30 @@ void set_compare(uint16_t count) { TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE); } -// Used to increment the slave counter -static void tim_update_irq_handler(void) { +static void tim_irq_handler(void) { + uint16_t cval = TIM_MST->CNT; + if (TIM_GetITStatus(TIM_MST, TIM_IT_Update) == SET) { TIM_ClearITPendingBit(TIM_MST, TIM_IT_Update); SlaveCounter++; } -} -// Used by interrupt system -static void tim_oc_irq_handler(void) { - uint16_t cval = TIM_MST->CNT; - - // Clear interrupt flag if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) { TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); - } - - if (oc_rem_part > 0) { - set_compare(oc_rem_part); // Finish the remaining time left - oc_rem_part = 0; - } - else { - if (oc_int_part > 0) { - set_compare(0xFFFF); - oc_rem_part = cval; // To finish the counter loop the next time - oc_int_part--; + if (oc_rem_part > 0) { + set_compare(oc_rem_part); // Finish the remaining time left + oc_rem_part = 0; } else { - us_ticker_irq_handler(); + if (oc_int_part > 0) { + //set_compare(0); + //oc_rem_part = cval; // To finish the counter loop the next time + //if (oc_rem_part == 0) GPIOB->ODR ^= (1 << 6); // DEBUG + oc_int_part--; + } + else { + us_ticker_irq_handler(); + } } } } @@ -101,12 +95,9 @@ void us_ticker_init(void) { TIM_ITConfig(TIM_MST, TIM_IT_Update, ENABLE); // Update interrupt used for 32-bit counter - NVIC_SetVector(TIM_MST_UP_IRQ, (uint32_t)tim_update_irq_handler); - NVIC_EnableIRQ(TIM_MST_UP_IRQ); - // Output compare interrupt used for timeout feature - NVIC_SetVector(TIM_MST_OC_IRQ, (uint32_t)tim_oc_irq_handler); - NVIC_EnableIRQ(TIM_MST_OC_IRQ); + NVIC_SetVector(TIM_MST_IRQ, (uint32_t)tim_irq_handler); + NVIC_EnableIRQ(TIM_MST_IRQ); // Enable timer TIM_Cmd(TIM_MST, ENABLE); @@ -158,7 +149,5 @@ void us_ticker_disable_interrupt(void) { } void us_ticker_clear_interrupt(void) { - if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) { - TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); - } + TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1); }