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[RZ/A1H] updates iodefine.h

pull/594/head
AMANUMA Kazuhisa 2014-10-24 18:06:26 +09:00
parent 8087cf1600
commit b5cd75cd56
12 changed files with 23432 additions and 0 deletions
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357
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iobitmasks/bsc_iobitmask.h Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : bsc_iobitmask.h
* $Rev: 1115 $
* $Date:: 2014-07-09 15:35:02 +0900#$
* Description : BSC register define header
*******************************************************************************/
#ifndef BSC_IOBITMASK_H
#define BSC_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
#define BSC_CMNCR_HIZCNT (0x00000001uL)
#define BSC_CMNCR_HIZMEM (0x00000002uL)
#define BSC_CMNCR_DPRTY (0x00000600uL)
#define BSC_CMNCR_AL0 (0x01000000uL)
#define BSC_CMNCR_TL0 (0x10000000uL)
#define BSC_CS0BCR_BSZ (0x00000600uL)
#define BSC_CS0BCR_TYPE (0x00007000uL)
#define BSC_CS0BCR_IWRRS (0x00070000uL)
#define BSC_CS0BCR_IWRRD (0x00380000uL)
#define BSC_CS0BCR_IWRWS (0x01C00000uL)
#define BSC_CS0BCR_IWRWD (0x0E000000uL)
#define BSC_CS0BCR_IWW (0x70000000uL)
#define BSC_CS1BCR_BSZ (0x00000600uL)
#define BSC_CS1BCR_TYPE (0x00007000uL)
#define BSC_CS1BCR_IWRRS (0x00070000uL)
#define BSC_CS1BCR_IWRRD (0x00380000uL)
#define BSC_CS1BCR_IWRWS (0x01C00000uL)
#define BSC_CS1BCR_IWRWD (0x0E000000uL)
#define BSC_CS1BCR_IWW (0x70000000uL)
#define BSC_CS2BCR_BSZ (0x00000600uL)
#define BSC_CS2BCR_TYPE (0x00007000uL)
#define BSC_CS2BCR_IWRRS (0x00070000uL)
#define BSC_CS2BCR_IWRRD (0x00380000uL)
#define BSC_CS2BCR_IWRWS (0x01C00000uL)
#define BSC_CS2BCR_IWRWD (0x0E000000uL)
#define BSC_CS2BCR_IWW (0x70000000uL)
#define BSC_CS3BCR_BSZ (0x00000600uL)
#define BSC_CS3BCR_TYPE (0x00007000uL)
#define BSC_CS3BCR_IWRRS (0x00070000uL)
#define BSC_CS3BCR_IWRRD (0x00380000uL)
#define BSC_CS3BCR_IWRWS (0x01C00000uL)
#define BSC_CS3BCR_IWRWD (0x0E000000uL)
#define BSC_CS3BCR_IWW (0x70000000uL)
#define BSC_CS4BCR_BSZ (0x00000600uL)
#define BSC_CS4BCR_TYPE (0x00007000uL)
#define BSC_CS4BCR_IWRRS (0x00070000uL)
#define BSC_CS4BCR_IWRRD (0x00380000uL)
#define BSC_CS4BCR_IWRWS (0x01C00000uL)
#define BSC_CS4BCR_IWRWD (0x0E000000uL)
#define BSC_CS4BCR_IWW (0x70000000uL)
#define BSC_CS5BCR_BSZ (0x00000600uL)
#define BSC_CS5BCR_TYPE (0x00007000uL)
#define BSC_CS5BCR_IWRRS (0x00070000uL)
#define BSC_CS5BCR_IWRRD (0x00380000uL)
#define BSC_CS5BCR_IWRWS (0x01C00000uL)
#define BSC_CS5BCR_IWRWD (0x0E000000uL)
#define BSC_CS5BCR_IWW (0x70000000uL)
#define BSC_CS0WCR_NORMAL_HW (0x00000003uL)
#define BSC_CS0WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS0WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS0WCR_NORMAL_SW (0x00001800uL)
#define BSC_CS0WCR_NORMAL_BAS (0x00100000uL)
#define BSC_CS1WCR_NORMAL_HW (0x00000003uL)
#define BSC_CS1WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS1WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS1WCR_NORMAL_SW (0x00001800uL)
#define BSC_CS1WCR_NORMAL_WW (0x00070000uL)
#define BSC_CS1WCR_NORMAL_BAS (0x00100000uL)
#define BSC_CS2WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS2WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS2WCR_NORMAL_BAS (0x00100000uL)
#define BSC_CS3WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS3WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS3WCR_NORMAL_BAS (0x00100000uL)
#define BSC_CS4WCR_NORMAL_HW (0x00000003uL)
#define BSC_CS4WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS4WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS4WCR_NORMAL_SW (0x00001800uL)
#define BSC_CS4WCR_NORMAL_WW (0x00070000uL)
#define BSC_CS4WCR_NORMAL_BAS (0x00100000uL)
#define BSC_CS5WCR_NORMAL_HW (0x00000003uL)
#define BSC_CS5WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS5WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS5WCR_NORMAL_SW (0x00001800uL)
#define BSC_CS5WCR_NORMAL_WW (0x00070000uL)
#define BSC_CS5WCR_NORMAL_MPXWBAS (0x00100000uL)
#define BSC_CS5WCR_NORMAL_SZSEL (0x00200000uL)
#define BSC_CS0WCR_BROM_ASY_WM (0x00000040uL)
#define BSC_CS0WCR_BROM_ASY_W (0x00000780uL)
#define BSC_CS0WCR_BROM_ASY_BW (0x00030000uL)
#define BSC_CS0WCR_BROM_ASY_BST (0x00300000uL)
#define BSC_CS4WCR_BROM_ASY_HW (0x00000003uL)
#define BSC_CS4WCR_BROM_ASY_WM (0x00000040uL)
#define BSC_CS4WCR_BROM_ASY_W (0x00000780uL)
#define BSC_CS4WCR_BROM_ASY_SW (0x00001800uL)
#define BSC_CS4WCR_BROM_ASY_BW (0x00030000uL)
#define BSC_CS4WCR_BROM_ASY_BST (0x00300000uL)
#define BSC_CS2WCR_SDRAM_A2CL (0x00000180uL)
#define BSC_CS3WCR_SDRAM_WTRC (0x00000003uL)
#define BSC_CS3WCR_SDRAM_TRWL (0x00000018uL)
#define BSC_CS3WCR_SDRAM_A3CL (0x00000180uL)
#define BSC_CS3WCR_SDRAM_WTRCD (0x00000C00uL)
#define BSC_CS3WCR_SDRAM_WTRP (0x00006000uL)
#define BSC_CS0WCR_BROM_SY_WM (0x00000040uL)
#define BSC_CS0WCR_BROM_SY_W (0x00000780uL)
#define BSC_CS0WCR_BROM_SY_BW (0x00030000uL)
#define BSC_SDCR_A3COL (0x00000003uL)
#define BSC_SDCR_A3ROW (0x00000018uL)
#define BSC_SDCR_BACTV (0x00000100uL)
#define BSC_SDCR_PDOWN (0x00000200uL)
#define BSC_SDCR_RMODE (0x00000400uL)
#define BSC_SDCR_RFSH (0x00000800uL)
#define BSC_SDCR_DEEP (0x00002000uL)
#define BSC_SDCR_A2COL (0x00030000uL)
#define BSC_SDCR_A2ROW (0x00180000uL)
#define BSC_RTCSR_RRC (0x00000007uL)
#define BSC_RTCSR_CKS (0x00000038uL)
#define BSC_RTCSR_CMIE (0x00000040uL)
#define BSC_RTCSR_CMF (0x00000080uL)
#define BSC_RTCNT_D (0xFFFFFFFFuL)
#define BSC_RTCOR_D (0xFFFFFFFFuL)
#define BSC_TOSCOR0_D (0x0000FFFFuL)
#define BSC_TOSCOR1_D (0x0000FFFFuL)
#define BSC_TOSCOR2_D (0x0000FFFFuL)
#define BSC_TOSCOR3_D (0x0000FFFFuL)
#define BSC_TOSCOR4_D (0x0000FFFFuL)
#define BSC_TOSCOR5_D (0x0000FFFFuL)
#define BSC_TOSTR_CS0TOSTF (0x00000001uL)
#define BSC_TOSTR_CS1TOSTF (0x00000002uL)
#define BSC_TOSTR_CS2TOSTF (0x00000004uL)
#define BSC_TOSTR_CS3TOSTF (0x00000008uL)
#define BSC_TOSTR_CS4TOSTF (0x00000010uL)
#define BSC_TOSTR_CS5TOSTF (0x00000020uL)
#define BSC_TOENR_CS0TOEN (0x00000001uL)
#define BSC_TOENR_CS1TOEN (0x00000002uL)
#define BSC_TOENR_CS2TOEN (0x00000004uL)
#define BSC_TOENR_CS3TOEN (0x00000008uL)
#define BSC_TOENR_CS4TOEN (0x00000010uL)
#define BSC_TOENR_CS5TOEN (0x00000020uL)
/* ==== Shift values for IO registers ==== */
#define BSC_CMNCR_HIZCNT_SHIFT (0u)
#define BSC_CMNCR_HIZMEM_SHIFT (1u)
#define BSC_CMNCR_DPRTY_SHIFT (9u)
#define BSC_CMNCR_AL0_SHIFT (24u)
#define BSC_CMNCR_TL0_SHIFT (28u)
#define BSC_CS0BCR_BSZ_SHIFT (9u)
#define BSC_CS0BCR_TYPE_SHIFT (12u)
#define BSC_CS0BCR_IWRRS_SHIFT (16u)
#define BSC_CS0BCR_IWRRD_SHIFT (19u)
#define BSC_CS0BCR_IWRWS_SHIFT (22u)
#define BSC_CS0BCR_IWRWD_SHIFT (25u)
#define BSC_CS0BCR_IWW_SHIFT (28u)
#define BSC_CS1BCR_BSZ_SHIFT (9u)
#define BSC_CS1BCR_TYPE_SHIFT (12u)
#define BSC_CS1BCR_IWRRS_SHIFT (16u)
#define BSC_CS1BCR_IWRRD_SHIFT (19u)
#define BSC_CS1BCR_IWRWS_SHIFT (22u)
#define BSC_CS1BCR_IWRWD_SHIFT (25u)
#define BSC_CS1BCR_IWW_SHIFT (28u)
#define BSC_CS2BCR_BSZ_SHIFT (9u)
#define BSC_CS2BCR_TYPE_SHIFT (12u)
#define BSC_CS2BCR_IWRRS_SHIFT (16u)
#define BSC_CS2BCR_IWRRD_SHIFT (19u)
#define BSC_CS2BCR_IWRWS_SHIFT (22u)
#define BSC_CS2BCR_IWRWD_SHIFT (25u)
#define BSC_CS2BCR_IWW_SHIFT (28u)
#define BSC_CS3BCR_BSZ_SHIFT (9u)
#define BSC_CS3BCR_TYPE_SHIFT (12u)
#define BSC_CS3BCR_IWRRS_SHIFT (16u)
#define BSC_CS3BCR_IWRRD_SHIFT (19u)
#define BSC_CS3BCR_IWRWS_SHIFT (22u)
#define BSC_CS3BCR_IWRWD_SHIFT (25u)
#define BSC_CS3BCR_IWW_SHIFT (28u)
#define BSC_CS4BCR_BSZ_SHIFT (9u)
#define BSC_CS4BCR_TYPE_SHIFT (12u)
#define BSC_CS4BCR_IWRRS_SHIFT (16u)
#define BSC_CS4BCR_IWRRD_SHIFT (19u)
#define BSC_CS4BCR_IWRWS_SHIFT (22u)
#define BSC_CS4BCR_IWRWD_SHIFT (25u)
#define BSC_CS4BCR_IWW_SHIFT (28u)
#define BSC_CS5BCR_BSZ_SHIFT (9u)
#define BSC_CS5BCR_TYPE_SHIFT (12u)
#define BSC_CS5BCR_IWRRS_SHIFT (16u)
#define BSC_CS5BCR_IWRRD_SHIFT (19u)
#define BSC_CS5BCR_IWRWS_SHIFT (22u)
#define BSC_CS5BCR_IWRWD_SHIFT (25u)
#define BSC_CS5BCR_IWW_SHIFT (28u)
#define BSC_CS0WCR_NORMAL_HW_SHIFT (0u)
#define BSC_CS0WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS0WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS0WCR_NORMAL_SW_SHIFT (11u)
#define BSC_CS0WCR_NORMAL_BAS_SHIFT (20u)
#define BSC_CS1WCR_NORMAL_HW_SHIFT (0u)
#define BSC_CS1WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS1WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS1WCR_NORMAL_SW_SHIFT (11u)
#define BSC_CS1WCR_NORMAL_WW_SHIFT (16u)
#define BSC_CS1WCR_NORMAL_BAS_SHIFT (20u)
#define BSC_CS2WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS2WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS2WCR_NORMAL_BAS_SHIFT (20u)
#define BSC_CS3WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS3WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS3WCR_NORMAL_BAS_SHIFT (20u)
#define BSC_CS4WCR_NORMAL_HW_SHIFT (0u)
#define BSC_CS4WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS4WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS4WCR_NORMAL_SW_SHIFT (11u)
#define BSC_CS4WCR_NORMAL_WW_SHIFT (16u)
#define BSC_CS4WCR_NORMAL_BAS_SHIFT (20u)
#define BSC_CS5WCR_NORMAL_HW_SHIFT (0u)
#define BSC_CS5WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS5WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS5WCR_NORMAL_SW_SHIFT (11u)
#define BSC_CS5WCR_NORMAL_WW_SHIFT (16u)
#define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u)
#define BSC_CS5WCR_NORMAL_SZSEL_SHIFT (21u)
#define BSC_CS0WCR_BROM_ASY_WM_SHIFT (6u)
#define BSC_CS0WCR_BROM_ASY_W_SHIFT (7u)
#define BSC_CS0WCR_BROM_ASY_BW_SHIFT (16u)
#define BSC_CS0WCR_BROM_ASY_BST_SHIFT (20u)
#define BSC_CS4WCR_BROM_ASY_HW_SHIFT (0u)
#define BSC_CS4WCR_BROM_ASY_WM_SHIFT (6u)
#define BSC_CS4WCR_BROM_ASY_W_SHIFT (7u)
#define BSC_CS4WCR_BROM_ASY_SW_SHIFT (11u)
#define BSC_CS4WCR_BROM_ASY_BW_SHIFT (16u)
#define BSC_CS4WCR_BROM_ASY_BST_SHIFT (20u)
#define BSC_CS2WCR_SDRAM_A2CL_SHIFT (7u)
#define BSC_CS3WCR_SDRAM_WTRC_SHIFT (0u)
#define BSC_CS3WCR_SDRAM_TRWL_SHIFT (3u)
#define BSC_CS3WCR_SDRAM_A3CL_SHIFT (7u)
#define BSC_CS3WCR_SDRAM_WTRCD_SHIFT (10u)
#define BSC_CS3WCR_SDRAM_WTRP_SHIFT (13u)
#define BSC_CS0WCR_BROM_SY_WM_SHIFT (6u)
#define BSC_CS0WCR_BROM_SY_W_SHIFT (7u)
#define BSC_CS0WCR_BROM_SY_BW_SHIFT (16u)
#define BSC_SDCR_A3COL_SHIFT (0u)
#define BSC_SDCR_A3ROW_SHIFT (3u)
#define BSC_SDCR_BACTV_SHIFT (8u)
#define BSC_SDCR_PDOWN_SHIFT (9u)
#define BSC_SDCR_RMODE_SHIFT (10u)
#define BSC_SDCR_RFSH_SHIFT (11u)
#define BSC_SDCR_DEEP_SHIFT (13u)
#define BSC_SDCR_A2COL_SHIFT (16u)
#define BSC_SDCR_A2ROW_SHIFT (19u)
#define BSC_RTCSR_RRC_SHIFT (0u)
#define BSC_RTCSR_CKS_SHIFT (3u)
#define BSC_RTCSR_CMIE_SHIFT (6u)
#define BSC_RTCSR_CMF_SHIFT (7u)
#define BSC_RTCNT_D_SHIFT (0u)
#define BSC_RTCOR_D_SHIFT (0u)
#define BSC_TOSCOR0_D_SHIFT (0u)
#define BSC_TOSCOR1_D_SHIFT (0u)
#define BSC_TOSCOR2_D_SHIFT (0u)
#define BSC_TOSCOR3_D_SHIFT (0u)
#define BSC_TOSCOR4_D_SHIFT (0u)
#define BSC_TOSCOR5_D_SHIFT (0u)
#define BSC_TOSTR_CS0TOSTF_SHIFT (0u)
#define BSC_TOSTR_CS1TOSTF_SHIFT (1u)
#define BSC_TOSTR_CS2TOSTF_SHIFT (2u)
#define BSC_TOSTR_CS3TOSTF_SHIFT (3u)
#define BSC_TOSTR_CS4TOSTF_SHIFT (4u)
#define BSC_TOSTR_CS5TOSTF_SHIFT (5u)
#define BSC_TOENR_CS0TOEN_SHIFT (0u)
#define BSC_TOENR_CS1TOEN_SHIFT (1u)
#define BSC_TOENR_CS2TOEN_SHIFT (2u)
#define BSC_TOENR_CS3TOEN_SHIFT (3u)
#define BSC_TOENR_CS4TOEN_SHIFT (4u)
#define BSC_TOENR_CS5TOEN_SHIFT (5u)
#endif /* BSC_IOBITMASK_H */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : cpg_iobitmask.h
* $Rev: 1115 $
* $Date:: 2014-07-09 15:35:02 +0900#$
* Description : CPG register define header
*******************************************************************************/
#ifndef CPG_IOBITMASK_H
#define CPG_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
#define CPG_FRQCR_IFC (0x0300u)
#define CPG_FRQCR_CKOEN (0x3000u)
#define CPG_FRQCR_CKOEN2 (0x4000u)
#define CPG_FRQCR2_GFC (0x0003u)
#define CPG_CPUSTS_ISBUSY (0x10u)
#define CPG_STBCR1_DEEP (0x40u)
#define CPG_STBCR1_STBY (0x80u)
#define CPG_STBCR2_MSTP20 (0x01u)
#define CPG_STBCR2_HIZ (0x80u)
#define CPG_STBREQ1_STBRQ10 (0x01u)
#define CPG_STBREQ1_STBRQ12 (0x04u)
#define CPG_STBREQ1_STBRQ13 (0x08u)
#define CPG_STBREQ1_STBRQ15 (0x20u)
#define CPG_STBREQ2_STBRQ20 (0x01u)
#define CPG_STBREQ2_STBRQ21 (0x02u)
#define CPG_STBREQ2_STBRQ22 (0x04u)
#define CPG_STBREQ2_STBRQ23 (0x08u)
#define CPG_STBREQ2_STBRQ24 (0x10u)
#define CPG_STBREQ2_STBRQ25 (0x20u)
#define CPG_STBREQ2_STBRQ26 (0x40u)
#define CPG_STBREQ2_STBRQ27 (0x80u)
#define CPG_STBACK1_STBAK10 (0x01u)
#define CPG_STBACK1_STBAK12 (0x04u)
#define CPG_STBACK1_STBAK13 (0x08u)
#define CPG_STBACK1_STBAK15 (0x20u)
#define CPG_STBACK2_STBAK20 (0x01u)
#define CPG_STBACK2_STBAK21 (0x02u)
#define CPG_STBACK2_STBAK22 (0x04u)
#define CPG_STBACK2_STBAK23 (0x08u)
#define CPG_STBACK2_STBAK24 (0x10u)
#define CPG_STBACK2_STBAK25 (0x20u)
#define CPG_STBACK2_STBAK26 (0x40u)
#define CPG_STBACK2_STBAK27 (0x80u)
#define CPG_SYSCR1_VRAME0 (0x01u)
#define CPG_SYSCR1_VRAME1 (0x02u)
#define CPG_SYSCR1_VRAME2 (0x04u)
#define CPG_SYSCR1_VRAME3 (0x08u)
#define CPG_SYSCR1_VRAME4 (0x10u)
#define CPG_SYSCR2_VRAMWE0 (0x01u)
#define CPG_SYSCR2_VRAMWE1 (0x02u)
#define CPG_SYSCR2_VRAMWE2 (0x04u)
#define CPG_SYSCR2_VRAMWE3 (0x08u)
#define CPG_SYSCR2_VRAMWE4 (0x10u)
#define CPG_SYSCR3_RRAMWE0 (0x01u)
#define CPG_SYSCR3_RRAMWE1 (0x02u)
#define CPG_SYSCR3_RRAMWE2 (0x04u)
#define CPG_SYSCR3_RRAMWE3 (0x08u)
#define CPG_STBCR3_MSTP30 (0x01u)
#define CPG_STBCR3_MSTP31 (0x02u)
#define CPG_STBCR3_MSTP32 (0x04u)
#define CPG_STBCR3_MSTP33 (0x08u)
#define CPG_STBCR3_MSTP34 (0x10u)
#define CPG_STBCR3_MSTP35 (0x20u)
#define CPG_STBCR3_MSTP36 (0x40u)
#define CPG_STBCR3_MSTP37 (0x80u)
#define CPG_STBCR4_MSTP40 (0x01u)
#define CPG_STBCR4_MSTP41 (0x02u)
#define CPG_STBCR4_MSTP42 (0x04u)
#define CPG_STBCR4_MSTP43 (0x08u)
#define CPG_STBCR4_MSTP44 (0x10u)
#define CPG_STBCR4_MSTP45 (0x20u)
#define CPG_STBCR4_MSTP46 (0x40u)
#define CPG_STBCR4_MSTP47 (0x80u)
#define CPG_STBCR5_MSTP50 (0x01u)
#define CPG_STBCR5_MSTP51 (0x02u)
#define CPG_STBCR5_MSTP52 (0x04u)
#define CPG_STBCR5_MSTP53 (0x08u)
#define CPG_STBCR5_MSTP54 (0x10u)
#define CPG_STBCR5_MSTP55 (0x20u)
#define CPG_STBCR5_MSTP56 (0x40u)
#define CPG_STBCR5_MSTP57 (0x80u)
#define CPG_STBCR6_MSTP60 (0x01u)
#define CPG_STBCR6_MSTP61 (0x02u)
#define CPG_STBCR6_MSTP62 (0x04u)
#define CPG_STBCR6_MSTP63 (0x08u)
#define CPG_STBCR6_MSTP64 (0x10u)
#define CPG_STBCR6_MSTP65 (0x20u)
#define CPG_STBCR6_MSTP66 (0x40u)
#define CPG_STBCR6_MSTP67 (0x80u)
#define CPG_STBCR7_MSTP70 (0x01u)
#define CPG_STBCR7_MSTP71 (0x02u)
#define CPG_STBCR7_MSTP73 (0x08u)
#define CPG_STBCR7_MSTP74 (0x10u)
#define CPG_STBCR7_MSTP76 (0x40u)
#define CPG_STBCR7_MSTP77 (0x80u)
#define CPG_STBCR8_MSTP81 (0x02u)
#define CPG_STBCR8_MSTP82 (0x04u)
#define CPG_STBCR8_MSTP83 (0x08u)
#define CPG_STBCR8_MSTP84 (0x10u)
#define CPG_STBCR8_MSTP85 (0x20u)
#define CPG_STBCR8_MSTP86 (0x40u)
#define CPG_STBCR8_MSTP87 (0x80u)
#define CPG_STBCR9_MSTP90 (0x01u)
#define CPG_STBCR9_MSTP91 (0x02u)
#define CPG_STBCR9_MSTP92 (0x04u)
#define CPG_STBCR9_MSTP93 (0x08u)
#define CPG_STBCR9_MSTP94 (0x10u)
#define CPG_STBCR9_MSTP95 (0x20u)
#define CPG_STBCR9_MSTP96 (0x40u)
#define CPG_STBCR9_MSTP97 (0x80u)
#define CPG_STBCR10_MSTP100 (0x01u)
#define CPG_STBCR10_MSTP101 (0x02u)
#define CPG_STBCR10_MSTP102 (0x04u)
#define CPG_STBCR10_MSTP103 (0x08u)
#define CPG_STBCR10_MSTP104 (0x10u)
#define CPG_STBCR10_MSTP105 (0x20u)
#define CPG_STBCR10_MSTP106 (0x40u)
#define CPG_STBCR10_MSTP107 (0x80u)
#define CPG_STBCR11_MSTP110 (0x01u)
#define CPG_STBCR11_MSTP111 (0x02u)
#define CPG_STBCR11_MSTP112 (0x04u)
#define CPG_STBCR11_MSTP113 (0x08u)
#define CPG_STBCR11_MSTP114 (0x10u)
#define CPG_STBCR11_MSTP115 (0x20u)
#define CPG_STBCR12_MSTP120 (0x01u)
#define CPG_STBCR12_MSTP121 (0x02u)
#define CPG_STBCR12_MSTP122 (0x04u)
#define CPG_STBCR12_MSTP123 (0x08u)
#define CPG_STBCR13_MSTP131 (0x02u)
#define CPG_STBCR13_MSTP132 (0x04u)
#define CPG_SWRSTCR1_SRST11 (0x02u)
#define CPG_SWRSTCR1_SRST12 (0x04u)
#define CPG_SWRSTCR1_SRST13 (0x08u)
#define CPG_SWRSTCR1_SRST14 (0x10u)
#define CPG_SWRSTCR1_SRST15 (0x20u)
#define CPG_SWRSTCR1_SRST16 (0x40u)
#define CPG_SWRSTCR1_AXTALE (0x80u)
#define CPG_SWRSTCR2_SRST21 (0x02u)
#define CPG_SWRSTCR3_SRST32 (0x04u)
#define CPG_RRAMKP_RRAMKP0 (0x01u)
#define CPG_RRAMKP_RRAMKP1 (0x02u)
#define CPG_RRAMKP_RRAMKP2 (0x04u)
#define CPG_RRAMKP_RRAMKP3 (0x08u)
#define CPG_DSCTR_RAMBOOT (0x40u)
#define CPG_DSCTR_EBUSKEEPE (0x80u)
#define CPG_DSSSR_P8_2 (0x0001u)
#define CPG_DSSSR_P9_1 (0x0002u)
#define CPG_DSSSR_P2_15 (0x0004u)
#define CPG_DSSSR_P7_8 (0x0008u)
#define CPG_DSSSR_P5_9 (0x0010u)
#define CPG_DSSSR_P6_4 (0x0020u)
#define CPG_DSSSR_RTCAR (0x0040u)
#define CPG_DSSSR_NMI (0x0100u)
#define CPG_DSSSR_P3_3 (0x0200u)
#define CPG_DSSSR_P8_7 (0x0400u)
#define CPG_DSSSR_P2_12 (0x0800u)
#define CPG_DSSSR_P3_1 (0x1000u)
#define CPG_DSSSR_P3_9 (0x2000u)
#define CPG_DSSSR_P6_2 (0x4000u)
#define CPG_DSESR_P8_2E (0x0001u)
#define CPG_DSESR_P9_1E (0x0002u)
#define CPG_DSESR_P2_15E (0x0004u)
#define CPG_DSESR_P7_8E (0x0008u)
#define CPG_DSESR_P5_9E (0x0010u)
#define CPG_DSESR_P6_4E (0x0020u)
#define CPG_DSESR_NMIE (0x0100u)
#define CPG_DSESR_P3_3E (0x0200u)
#define CPG_DSESR_P8_7E (0x0400u)
#define CPG_DSESR_P2_12E (0x0800u)
#define CPG_DSESR_P3_1E (0x1000u)
#define CPG_DSESR_P3_9E (0x2000u)
#define CPG_DSESR_P6_2E (0x4000u)
#define CPG_DSFR_P8_2F (0x0001u)
#define CPG_DSFR_P9_1F (0x0002u)
#define CPG_DSFR_P2_15F (0x0004u)
#define CPG_DSFR_P7_8F (0x0008u)
#define CPG_DSFR_P5_9F (0x0010u)
#define CPG_DSFR_P6_4F (0x0020u)
#define CPG_DSFR_RTCARF (0x0040u)
#define CPG_DSFR_NMIF (0x0100u)
#define CPG_DSFR_P3_3F (0x0200u)
#define CPG_DSFR_P8_7F (0x0400u)
#define CPG_DSFR_P2_12F (0x0800u)
#define CPG_DSFR_P3_1F (0x1000u)
#define CPG_DSFR_P3_9F (0x2000u)
#define CPG_DSFR_P6_2F (0x4000u)
#define CPG_DSFR_IOKEEP (0x8000u)
#define CPG_XTALCTR_GAIN0 (0x01u)
#define CPG_XTALCTR_GAIN1 (0x02u)
/* ==== Shift values for IO registers ==== */
#define CPG_FRQCR_IFC_SHIFT (8u)
#define CPG_FRQCR_CKOEN_SHIFT (12u)
#define CPG_FRQCR_CKOEN2_SHIFT (14u)
#define CPG_FRQCR2_GFC_SHIFT (0u)
#define CPG_CPUSTS_ISBUSY_SHIFT (4u)
#define CPG_STBCR1_DEEP_SHIFT (6u)
#define CPG_STBCR1_STBY_SHIFT (7u)
#define CPG_STBCR2_MSTP20_SHIFT (0u)
#define CPG_STBCR2_HIZ_SHIFT (7u)
#define CPG_STBREQ1_STBRQ10_SHIFT (0u)
#define CPG_STBREQ1_STBRQ12_SHIFT (2u)
#define CPG_STBREQ1_STBRQ13_SHIFT (3u)
#define CPG_STBREQ1_STBRQ15_SHIFT (5u)
#define CPG_STBREQ2_STBRQ20_SHIFT (0u)
#define CPG_STBREQ2_STBRQ21_SHIFT (1u)
#define CPG_STBREQ2_STBRQ22_SHIFT (2u)
#define CPG_STBREQ2_STBRQ23_SHIFT (3u)
#define CPG_STBREQ2_STBRQ24_SHIFT (4u)
#define CPG_STBREQ2_STBRQ25_SHIFT (5u)
#define CPG_STBREQ2_STBRQ26_SHIFT (6u)
#define CPG_STBREQ2_STBRQ27_SHIFT (7u)
#define CPG_STBACK1_STBAK10_SHIFT (0u)
#define CPG_STBACK1_STBAK12_SHIFT (2u)
#define CPG_STBACK1_STBAK13_SHIFT (3u)
#define CPG_STBACK1_STBAK15_SHIFT (5u)
#define CPG_STBACK2_STBAK20_SHIFT (0u)
#define CPG_STBACK2_STBAK21_SHIFT (1u)
#define CPG_STBACK2_STBAK22_SHIFT (2u)
#define CPG_STBACK2_STBAK23_SHIFT (3u)
#define CPG_STBACK2_STBAK24_SHIFT (4u)
#define CPG_STBACK2_STBAK25_SHIFT (5u)
#define CPG_STBACK2_STBAK26_SHIFT (6u)
#define CPG_STBACK2_STBAK27_SHIFT (7u)
#define CPG_SYSCR1_VRAME0_SHIFT (0u)
#define CPG_SYSCR1_VRAME1_SHIFT (1u)
#define CPG_SYSCR1_VRAME2_SHIFT (2u)
#define CPG_SYSCR1_VRAME3_SHIFT (3u)
#define CPG_SYSCR1_VRAME4_SHIFT (4u)
#define CPG_SYSCR2_VRAMWE0_SHIFT (0u)
#define CPG_SYSCR2_VRAMWE1_SHIFT (1u)
#define CPG_SYSCR2_VRAMWE2_SHIFT (2u)
#define CPG_SYSCR2_VRAMWE3_SHIFT (3u)
#define CPG_SYSCR2_VRAMWE4_SHIFT (4u)
#define CPG_SYSCR3_RRAMWE0_SHIFT (0u)
#define CPG_SYSCR3_RRAMWE1_SHIFT (1u)
#define CPG_SYSCR3_RRAMWE2_SHIFT (2u)
#define CPG_SYSCR3_RRAMWE3_SHIFT (3u)
#define CPG_STBCR3_MSTP30_SHIFT (0u)
#define CPG_STBCR3_MSTP31_SHIFT (1u)
#define CPG_STBCR3_MSTP32_SHIFT (2u)
#define CPG_STBCR3_MSTP33_SHIFT (3u)
#define CPG_STBCR3_MSTP34_SHIFT (4u)
#define CPG_STBCR3_MSTP35_SHIFT (5u)
#define CPG_STBCR3_MSTP36_SHIFT (6u)
#define CPG_STBCR3_MSTP37_SHIFT (7u)
#define CPG_STBCR4_MSTP40_SHIFT (0u)
#define CPG_STBCR4_MSTP41_SHIFT (1u)
#define CPG_STBCR4_MSTP42_SHIFT (2u)
#define CPG_STBCR4_MSTP43_SHIFT (3u)
#define CPG_STBCR4_MSTP44_SHIFT (4u)
#define CPG_STBCR4_MSTP45_SHIFT (5u)
#define CPG_STBCR4_MSTP46_SHIFT (6u)
#define CPG_STBCR4_MSTP47_SHIFT (7u)
#define CPG_STBCR5_MSTP50_SHIFT (0u)
#define CPG_STBCR5_MSTP51_SHIFT (1u)
#define CPG_STBCR5_MSTP52_SHIFT (2u)
#define CPG_STBCR5_MSTP53_SHIFT (3u)
#define CPG_STBCR5_MSTP54_SHIFT (4u)
#define CPG_STBCR5_MSTP55_SHIFT (5u)
#define CPG_STBCR5_MSTP56_SHIFT (6u)
#define CPG_STBCR5_MSTP57_SHIFT (7u)
#define CPG_STBCR6_MSTP60_SHIFT (0u)
#define CPG_STBCR6_MSTP61_SHIFT (1u)
#define CPG_STBCR6_MSTP62_SHIFT (2u)
#define CPG_STBCR6_MSTP63_SHIFT (3u)
#define CPG_STBCR6_MSTP64_SHIFT (4u)
#define CPG_STBCR6_MSTP65_SHIFT (5u)
#define CPG_STBCR6_MSTP66_SHIFT (6u)
#define CPG_STBCR6_MSTP67_SHIFT (7u)
#define CPG_STBCR7_MSTP70_SHIFT (0u)
#define CPG_STBCR7_MSTP71_SHIFT (1u)
#define CPG_STBCR7_MSTP73_SHIFT (3u)
#define CPG_STBCR7_MSTP74_SHIFT (4u)
#define CPG_STBCR7_MSTP76_SHIFT (6u)
#define CPG_STBCR7_MSTP77_SHIFT (7u)
#define CPG_STBCR8_MSTP81_SHIFT (1u)
#define CPG_STBCR8_MSTP82_SHIFT (2u)
#define CPG_STBCR8_MSTP83_SHIFT (3u)
#define CPG_STBCR8_MSTP84_SHIFT (4u)
#define CPG_STBCR8_MSTP85_SHIFT (5u)
#define CPG_STBCR8_MSTP86_SHIFT (6u)
#define CPG_STBCR8_MSTP87_SHIFT (7u)
#define CPG_STBCR9_MSTP90_SHIFT (0u)
#define CPG_STBCR9_MSTP91_SHIFT (1u)
#define CPG_STBCR9_MSTP92_SHIFT (2u)
#define CPG_STBCR9_MSTP93_SHIFT (3u)
#define CPG_STBCR9_MSTP94_SHIFT (4u)
#define CPG_STBCR9_MSTP95_SHIFT (5u)
#define CPG_STBCR9_MSTP96_SHIFT (6u)
#define CPG_STBCR9_MSTP97_SHIFT (7u)
#define CPG_STBCR10_MSTP100_SHIFT (0u)
#define CPG_STBCR10_MSTP101_SHIFT (1u)
#define CPG_STBCR10_MSTP102_SHIFT (2u)
#define CPG_STBCR10_MSTP103_SHIFT (3u)
#define CPG_STBCR10_MSTP104_SHIFT (4u)
#define CPG_STBCR10_MSTP105_SHIFT (5u)
#define CPG_STBCR10_MSTP106_SHIFT (6u)
#define CPG_STBCR10_MSTP107_SHIFT (7u)
#define CPG_STBCR11_MSTP110_SHIFT (0u)
#define CPG_STBCR11_MSTP111_SHIFT (1u)
#define CPG_STBCR11_MSTP112_SHIFT (2u)
#define CPG_STBCR11_MSTP113_SHIFT (3u)
#define CPG_STBCR11_MSTP114_SHIFT (4u)
#define CPG_STBCR11_MSTP115_SHIFT (5u)
#define CPG_STBCR12_MSTP120_SHIFT (0u)
#define CPG_STBCR12_MSTP121_SHIFT (1u)
#define CPG_STBCR12_MSTP122_SHIFT (2u)
#define CPG_STBCR12_MSTP123_SHIFT (3u)
#define CPG_STBCR13_MSTP131_SHIFT (1u)
#define CPG_STBCR13_MSTP132_SHIFT (2u)
#define CPG_SWRSTCR1_SRST11_SHIFT (1u)
#define CPG_SWRSTCR1_SRST12_SHIFT (2u)
#define CPG_SWRSTCR1_SRST13_SHIFT (3u)
#define CPG_SWRSTCR1_SRST14_SHIFT (4u)
#define CPG_SWRSTCR1_SRST15_SHIFT (5u)
#define CPG_SWRSTCR1_SRST16_SHIFT (6u)
#define CPG_SWRSTCR1_AXTALE_SHIFT (7u)
#define CPG_SWRSTCR2_SRST21_SHIFT (1u)
#define CPG_SWRSTCR3_SRST32_SHIFT (2u)
#define CPG_RRAMKP_RRAMKP0_SHIFT (0u)
#define CPG_RRAMKP_RRAMKP1_SHIFT (1u)
#define CPG_RRAMKP_RRAMKP2_SHIFT (2u)
#define CPG_RRAMKP_RRAMKP3_SHIFT (3u)
#define CPG_DSCTR_RAMBOOT_SHIFT (6u)
#define CPG_DSCTR_EBUSKEEPE_SHIFT (7u)
#define CPG_DSSSR_P8_2_SHIFT (0u)
#define CPG_DSSSR_P9_1_SHIFT (1u)
#define CPG_DSSSR_P2_15_SHIFT (2u)
#define CPG_DSSSR_P7_8_SHIFT (3u)
#define CPG_DSSSR_P5_9_SHIFT (4u)
#define CPG_DSSSR_P6_4_SHIFT (5u)
#define CPG_DSSSR_RTCAR_SHIFT (6u)
#define CPG_DSSSR_NMI_SHIFT (8u)
#define CPG_DSSSR_P3_3_SHIFT (9u)
#define CPG_DSSSR_P8_7_SHIFT (10u)
#define CPG_DSSSR_P2_12_SHIFT (11u)
#define CPG_DSSSR_P3_1_SHIFT (12u)
#define CPG_DSSSR_P3_9_SHIFT (13u)
#define CPG_DSSSR_P6_2_SHIFT (14u)
#define CPG_DSESR_P8_2E_SHIFT (0u)
#define CPG_DSESR_P9_1E_SHIFT (1u)
#define CPG_DSESR_P2_15E_SHIFT (2u)
#define CPG_DSESR_P7_8E_SHIFT (3u)
#define CPG_DSESR_P5_9E_SHIFT (4u)
#define CPG_DSESR_P6_4E_SHIFT (5u)
#define CPG_DSESR_NMIE_SHIFT (8u)
#define CPG_DSESR_P3_3E_SHIFT (9u)
#define CPG_DSESR_P8_7E_SHIFT (10u)
#define CPG_DSESR_P2_12E_SHIFT (11u)
#define CPG_DSESR_P3_1E_SHIFT (12u)
#define CPG_DSESR_P3_9E_SHIFT (13u)
#define CPG_DSESR_P6_2E_SHIFT (14u)
#define CPG_DSFR_P8_2F_SHIFT (0u)
#define CPG_DSFR_P9_1F_SHIFT (1u)
#define CPG_DSFR_P2_15F_SHIFT (2u)
#define CPG_DSFR_P7_8F_SHIFT (3u)
#define CPG_DSFR_P5_9F_SHIFT (4u)
#define CPG_DSFR_P6_4F_SHIFT (5u)
#define CPG_DSFR_RTCARF_SHIFT (6u)
#define CPG_DSFR_NMIF_SHIFT (8u)
#define CPG_DSFR_P3_3F_SHIFT (9u)
#define CPG_DSFR_P8_7F_SHIFT (10u)
#define CPG_DSFR_P2_12F_SHIFT (11u)
#define CPG_DSFR_P3_1F_SHIFT (12u)
#define CPG_DSFR_P3_9F_SHIFT (13u)
#define CPG_DSFR_P6_2F_SHIFT (14u)
#define CPG_DSFR_IOKEEP_SHIFT (15u)
#define CPG_XTALCTR_GAIN0_SHIFT (0u)
#define CPG_XTALCTR_GAIN1_SHIFT (1u)
#endif /* CPG_IOBITMASK_H */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mtu2_iobitmask.h
* $Rev: 1138 $
* $Date:: 2014-08-08 11:03:56 +0900#$
* Description : MTU2 register define header
*******************************************************************************/
#ifndef MTU2_IOBITMASK_H
#define MTU2_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
#define MTU2_TCR_n_TPSC (0x07u)
#define MTU2_TCR_n_CKEG (0x18u)
#define MTU2_TCR_n_CCLR (0xE0u)
#define MTU2_TMDR_n_MD (0x0Fu)
#define MTU2_TIOR_2_IOA (0x0Fu)
#define MTU2_TIOR_2_IOB (0xF0u)
#define MTU2_TIER_n_TGIEA (0x01u)
#define MTU2_TIER_n_TGIEB (0x02u)
#define MTU2_TIER_n_TCIEV (0x10u)
#define MTU2_TIER_2_TCIEU (0x20u)
#define MTU2_TIER_n_TTGE (0x80u)
#define MTU2_TSR_n_TGFA (0x01u)
#define MTU2_TSR_n_TGFB (0x02u)
#define MTU2_TSR_n_TCFV (0x10u)
#define MTU2_TSR_2_TCFU (0x20u)
#define MTU2_TSR_2_TCFD (0x80u)
#define MTU2_TCNT_n_D (0xFFFFu)
#define MTU2_TGRA_n_D (0xFFFFu)
#define MTU2_TGRB_n_D (0xFFFFu)
#define MTU2_TMDR_3_BFA (0x10u)
#define MTU2_TMDR_3_BFB (0x20u)
#define MTU2_TMDR_4_BFA (0x10u)
#define MTU2_TMDR_4_BFB (0x20u)
#define MTU2_TIORH_3_IOA (0x0Fu)
#define MTU2_TIORH_3_IOB (0xF0u)
#define MTU2_TIORL_3_IOC (0x0Fu)
#define MTU2_TIORL_3_IOD (0xF0u)
#define MTU2_TIORH_4_IOA (0x0Fu)
#define MTU2_TIORH_4_IOB (0xF0u)
#define MTU2_TIORL_4_IOC (0x0Fu)
#define MTU2_TIORL_4_IOD (0xF0u)
#define MTU2_TIER_3_TGIEC (0x04u)
#define MTU2_TIER_3_TGIED (0x08u)
#define MTU2_TIER_4_TGIEC (0x04u)
#define MTU2_TIER_4_TGIED (0x08u)
#define MTU2_TIER_4_TTGE2 (0x40u)
#define MTU2_TOER_OE3B (0x01u)
#define MTU2_TOER_OE4A (0x02u)
#define MTU2_TOER_OE4B (0x04u)
#define MTU2_TOER_OE3D (0x08u)
#define MTU2_TOER_OE4C (0x10u)
#define MTU2_TOER_OE4D (0x20u)
#define MTU2_TGCR_UF (0x01u)
#define MTU2_TGCR_VF (0x02u)
#define MTU2_TGCR_WF (0x04u)
#define MTU2_TGCR_FB (0x08u)
#define MTU2_TGCR_P (0x10u)
#define MTU2_TGCR_N (0x20u)
#define MTU2_TGCR_BDC (0x40u)
#define MTU2_TOCR1_OLSP (0x01u)
#define MTU2_TOCR1_OLSN (0x02u)
#define MTU2_TOCR1_TOCS (0x04u)
#define MTU2_TOCR1_TOCL (0x08u)
#define MTU2_TOCR1_PSYE (0x40u)
#define MTU2_TOCR2_OLS1P (0x01u)
#define MTU2_TOCR2_OLS1N (0x02u)
#define MTU2_TOCR2_OLS2P (0x04u)
#define MTU2_TOCR2_OLS2N (0x08u)
#define MTU2_TOCR2_OLS3P (0x10u)
#define MTU2_TOCR2_OLS3N (0x20u)
#define MTU2_TOCR2_BF (0xC0u)
#define MTU2_TCDR_D (0xFFFFu)
#define MTU2_TDDR_D (0xFFFFu)
#define MTU2_TCNTS_D (0xFFFFu)
#define MTU2_TCBR_D (0xFFFFu)
#define MTU2_TGRC_3_D (0xFFFFu)
#define MTU2_TGRD_3_D (0xFFFFu)
#define MTU2_TGRC_4_D (0xFFFFu)
#define MTU2_TGRD_4_D (0xFFFFu)
#define MTU2_TSR_3_TGFC (0x04u)
#define MTU2_TSR_3_TGFD (0x08u)
#define MTU2_TSR_3_TCFD (0x80u)
#define MTU2_TSR_4_TGFC (0x04u)
#define MTU2_TSR_4_TGFD (0x08u)
#define MTU2_TSR_4_TCFD (0x80u)
#define MTU2_TITCR_4VCOR (0x07u)
#define MTU2_TITCR_T4VEN (0x08u)
#define MTU2_TITCR_3ACOR (0x70u)
#define MTU2_TITCR_T3AEN (0x80u)
#define MTU2_TITCNT_4VCNT (0x07u)
#define MTU2_TITCNT_3ACNT (0x70u)
#define MTU2_TBTER_BTE (0x03u)
#define MTU2_TDER_TDER (0x01u)
#define MTU2_TOLBR_OLS1P (0x01u)
#define MTU2_TOLBR_OLS1N (0x02u)
#define MTU2_TOLBR_OLS2P (0x04u)
#define MTU2_TOLBR_OLS2N (0x08u)
#define MTU2_TOLBR_OLS3P (0x10u)
#define MTU2_TOLBR_OLS3N (0x20u)
#define MTU2_TBTM_3_TTSA (0x01u)
#define MTU2_TBTM_3_TTSB (0x02u)
#define MTU2_TBTM_4_TTSA (0x01u)
#define MTU2_TBTM_4_TTSB (0x02u)
#define MTU2_TADCR_ITB4VE (0x0001u)
#define MTU2_TADCR_ITB3AE (0x0002u)
#define MTU2_TADCR_ITA4VE (0x0004u)
#define MTU2_TADCR_ITA3AE (0x0008u)
#define MTU2_TADCR_DT4BE (0x0010u)
#define MTU2_TADCR_UT4BE (0x0020u)
#define MTU2_TADCR_DT4AE (0x0040u)
#define MTU2_TADCR_UT4AE (0x0080u)
#define MTU2_TADCR_BF (0xC000u)
#define MTU2_TADCORA_4_D (0xFFFFu)
#define MTU2_TADCORB_4_D (0xFFFFu)
#define MTU2_TADCOBRA_4_D (0xFFFFu)
#define MTU2_TADCOBRB_4_D (0xFFFFu)
#define MTU2_TWCR_WRE (0x01u)
#define MTU2_TWCR_CCE (0x80u)
#define MTU2_TSTR_CST0 (0x01u)
#define MTU2_TSTR_CST1 (0x02u)
#define MTU2_TSTR_CST2 (0x04u)
#define MTU2_TSTR_CST3 (0x40u)
#define MTU2_TSTR_CST4 (0x80u)
#define MTU2_TSYR_SYNC0 (0x01u)
#define MTU2_TSYR_SYNC1 (0x02u)
#define MTU2_TSYR_SYNC2 (0x04u)
#define MTU2_TSYR_SYNC3 (0x40u)
#define MTU2_TSYR_SYNC4 (0x80u)
#define MTU2_TRWER_RWE (0x01u)
#define MTU2_TMDR_0_BFA (0x10u)
#define MTU2_TMDR_0_BFB (0x20u)
#define MTU2_TMDR_0_BFE (0x40u)
#define MTU2_TIORH_0_IOA (0x0Fu)
#define MTU2_TIORH_0_IOB (0xF0u)
#define MTU2_TIORL_0_IOC (0x0Fu)
#define MTU2_TIORL_0_IOD (0xF0u)
#define MTU2_TIER_0_TGIEC (0x04u)
#define MTU2_TIER_0_TGIED (0x08u)
#define MTU2_TSR_0_TGFC (0x04u)
#define MTU2_TSR_0_TGFD (0x08u)
#define MTU2_TGRC_0_D (0xFFFFu)
#define MTU2_TGRD_0_D (0xFFFFu)
#define MTU2_TGRE_0_D (0xFFFFu)
#define MTU2_TGRF_0_D (0xFFFFu)
#define MTU2_TIER2_0_TGIEE (0x01u)
#define MTU2_TIER2_0_TGIEF (0x02u)
#define MTU2_TSR2_0_TGFE (0x01u)
#define MTU2_TSR2_0_TGFF (0x02u)
#define MTU2_TBTM_0_TTSA (0x01u)
#define MTU2_TBTM_0_TTSB (0x02u)
#define MTU2_TBTM_0_TTSE (0x04u)
#define MTU2_TIOR_1_IOA (0x0Fu)
#define MTU2_TIOR_1_IOB (0xF0u)
#define MTU2_TIER_1_TCIEU (0x20u)
#define MTU2_TSR_1_TCFU (0x20u)
#define MTU2_TSR_1_TCFD (0x80u)
#define MTU2_TICCR_I1AE (0x01u)
#define MTU2_TICCR_I1BE (0x02u)
#define MTU2_TICCR_I2AE (0x04u)
#define MTU2_TICCR_I2BE (0x08u)
/* ==== Shift values for IO registers ==== */
#define MTU2_TCR_n_TPSC_SHIFT (0u)
#define MTU2_TCR_n_CKEG_SHIFT (3u)
#define MTU2_TCR_n_CCLR_SHIFT (5u)
#define MTU2_TMDR_n_MD_SHIFT (0u)
#define MTU2_TIOR_2_IOA_SHIFT (0u)
#define MTU2_TIOR_2_IOB_SHIFT (4u)
#define MTU2_TIER_n_TGIEA_SHIFT (0u)
#define MTU2_TIER_n_TGIEB_SHIFT (1u)
#define MTU2_TIER_n_TCIEV_SHIFT (4u)
#define MTU2_TIER_2_TCIEU_SHIFT (5u)
#define MTU2_TIER_n_TTGE_SHIFT (7u)
#define MTU2_TSR_n_TGFA_SHIFT (0u)
#define MTU2_TSR_n_TGFB_SHIFT (1u)
#define MTU2_TSR_n_TCFV_SHIFT (4u)
#define MTU2_TSR_2_TCFU_SHIFT (5u)
#define MTU2_TSR_2_TCFD_SHIFT (7u)
#define MTU2_TCNT_n_D_SHIFT (0u)
#define MTU2_TGRA_n_D_SHIFT (0u)
#define MTU2_TGRB_n_D_SHIFT (0u)
#define MTU2_TMDR_3_BFA_SHIFT (4u)
#define MTU2_TMDR_3_BFB_SHIFT (5u)
#define MTU2_TMDR_4_BFA_SHIFT (4u)
#define MTU2_TMDR_4_BFB_SHIFT (5u)
#define MTU2_TIORH_3_IOA_SHIFT (0u)
#define MTU2_TIORH_3_IOB_SHIFT (4u)
#define MTU2_TIORL_3_IOC_SHIFT (0u)
#define MTU2_TIORL_3_IOD_SHIFT (4u)
#define MTU2_TIORH_4_IOA_SHIFT (0u)
#define MTU2_TIORH_4_IOB_SHIFT (4u)
#define MTU2_TIORL_4_IOC_SHIFT (0u)
#define MTU2_TIORL_4_IOD_SHIFT (4u)
#define MTU2_TIER_3_TGIEC_SHIFT (2u)
#define MTU2_TIER_3_TGIED_SHIFT (3u)
#define MTU2_TIER_4_TGIEC_SHIFT (2u)
#define MTU2_TIER_4_TGIED_SHIFT (3u)
#define MTU2_TIER_4_TTGE2_SHIFT (6u)
#define MTU2_TOER_OE3B_SHIFT (0u)
#define MTU2_TOER_OE4A_SHIFT (1u)
#define MTU2_TOER_OE4B_SHIFT (2u)
#define MTU2_TOER_OE3D_SHIFT (3u)
#define MTU2_TOER_OE4C_SHIFT (4u)
#define MTU2_TOER_OE4D_SHIFT (5u)
#define MTU2_TGCR_UF_SHIFT (0u)
#define MTU2_TGCR_VF_SHIFT (1u)
#define MTU2_TGCR_WF_SHIFT (2u)
#define MTU2_TGCR_FB_SHIFT (3u)
#define MTU2_TGCR_P_SHIFT (4u)
#define MTU2_TGCR_N_SHIFT (5u)
#define MTU2_TGCR_BDC_SHIFT (6u)
#define MTU2_TOCR1_OLSP_SHIFT (0u)
#define MTU2_TOCR1_OLSN_SHIFT (1u)
#define MTU2_TOCR1_TOCS_SHIFT (2u)
#define MTU2_TOCR1_TOCL_SHIFT (3u)
#define MTU2_TOCR1_PSYE_SHIFT (6u)
#define MTU2_TOCR2_OLS1P_SHIFT (0u)
#define MTU2_TOCR2_OLS1N_SHIFT (1u)
#define MTU2_TOCR2_OLS2P_SHIFT (2u)
#define MTU2_TOCR2_OLS2N_SHIFT (3u)
#define MTU2_TOCR2_OLS3P_SHIFT (4u)
#define MTU2_TOCR2_OLS3N_SHIFT (5u)
#define MTU2_TOCR2_BF_SHIFT (6u)
#define MTU2_TCDR_D_SHIFT (0u)
#define MTU2_TDDR_D_SHIFT (0u)
#define MTU2_TCNTS_D_SHIFT (0u)
#define MTU2_TCBR_D_SHIFT (0u)
#define MTU2_TGRC_3_D_SHIFT (0u)
#define MTU2_TGRD_3_D_SHIFT (0u)
#define MTU2_TGRC_4_D_SHIFT (0u)
#define MTU2_TGRD_4_D_SHIFT (0u)
#define MTU2_TSR_3_TGFC_SHIFT (2u)
#define MTU2_TSR_3_TGFD_SHIFT (3u)
#define MTU2_TSR_3_TCFD_SHIFT (7u)
#define MTU2_TSR_4_TGFC_SHIFT (2u)
#define MTU2_TSR_4_TGFD_SHIFT (3u)
#define MTU2_TSR_4_TCFD_SHIFT (7u)
#define MTU2_TITCR_4VCOR_SHIFT (0u)
#define MTU2_TITCR_T4VEN_SHIFT (3u)
#define MTU2_TITCR_3ACOR_SHIFT (4u)
#define MTU2_TITCR_T3AEN_SHIFT (7u)
#define MTU2_TITCNT_4VCNT_SHIFT (0u)
#define MTU2_TITCNT_3ACNT_SHIFT (4u)
#define MTU2_TBTER_BTE_SHIFT (0u)
#define MTU2_TDER_TDER_SHIFT (0u)
#define MTU2_TOLBR_OLS1P_SHIFT (0u)
#define MTU2_TOLBR_OLS1N_SHIFT (1u)
#define MTU2_TOLBR_OLS2P_SHIFT (2u)
#define MTU2_TOLBR_OLS2N_SHIFT (3u)
#define MTU2_TOLBR_OLS3P_SHIFT (4u)
#define MTU2_TOLBR_OLS3N_SHIFT (5u)
#define MTU2_TBTM_3_TTSA_SHIFT (0u)
#define MTU2_TBTM_3_TTSB_SHIFT (1u)
#define MTU2_TBTM_4_TTSA_SHIFT (0u)
#define MTU2_TBTM_4_TTSB_SHIFT (1u)
#define MTU2_TADCR_ITB4VE_SHIFT (0u)
#define MTU2_TADCR_ITB3AE_SHIFT (1u)
#define MTU2_TADCR_ITA4VE_SHIFT (2u)
#define MTU2_TADCR_ITA3AE_SHIFT (3u)
#define MTU2_TADCR_DT4BE_SHIFT (4u)
#define MTU2_TADCR_UT4BE_SHIFT (5u)
#define MTU2_TADCR_DT4AE_SHIFT (6u)
#define MTU2_TADCR_UT4AE_SHIFT (7u)
#define MTU2_TADCR_BF_SHIFT (14u)
#define MTU2_TADCORA_4_D_SHIFT (0u)
#define MTU2_TADCORB_4_D_SHIFT (0u)
#define MTU2_TADCOBRA_4_D_SHIFT (0u)
#define MTU2_TADCOBRB_4_D_SHIFT (0u)
#define MTU2_TWCR_WRE_SHIFT (0u)
#define MTU2_TWCR_CCE_SHIFT (7u)
#define MTU2_TSTR_CST0_SHIFT (0u)
#define MTU2_TSTR_CST1_SHIFT (1u)
#define MTU2_TSTR_CST2_SHIFT (2u)
#define MTU2_TSTR_CST3_SHIFT (6u)
#define MTU2_TSTR_CST4_SHIFT (7u)
#define MTU2_TSYR_SYNC0_SHIFT (0u)
#define MTU2_TSYR_SYNC1_SHIFT (1u)
#define MTU2_TSYR_SYNC2_SHIFT (2u)
#define MTU2_TSYR_SYNC3_SHIFT (6u)
#define MTU2_TSYR_SYNC4_SHIFT (7u)
#define MTU2_TRWER_RWE_SHIFT (0u)
#define MTU2_TMDR_0_BFA_SHIFT (4u)
#define MTU2_TMDR_0_BFB_SHIFT (5u)
#define MTU2_TMDR_0_BFE_SHIFT (6u)
#define MTU2_TIORH_0_IOA_SHIFT (0u)
#define MTU2_TIORH_0_IOB_SHIFT (4u)
#define MTU2_TIORL_0_IOC_SHIFT (0u)
#define MTU2_TIORL_0_IOD_SHIFT (4u)
#define MTU2_TIER_0_TGIEC_SHIFT (2u)
#define MTU2_TIER_0_TGIED_SHIFT (3u)
#define MTU2_TSR_0_TGFC_SHIFT (2u)
#define MTU2_TSR_0_TGFD_SHIFT (3u)
#define MTU2_TGRC_0_D_SHIFT (0u)
#define MTU2_TGRD_0_D_SHIFT (0u)
#define MTU2_TGRE_0_D_SHIFT (0u)
#define MTU2_TGRF_0_D_SHIFT (0u)
#define MTU2_TIER2_0_TGIEE_SHIFT (0u)
#define MTU2_TIER2_0_TGIEF_SHIFT (1u)
#define MTU2_TSR2_0_TGFE_SHIFT (0u)
#define MTU2_TSR2_0_TGFF_SHIFT (1u)
#define MTU2_TBTM_0_TTSA_SHIFT (0u)
#define MTU2_TBTM_0_TTSB_SHIFT (1u)
#define MTU2_TBTM_0_TTSE_SHIFT (2u)
#define MTU2_TIOR_1_IOA_SHIFT (0u)
#define MTU2_TIOR_1_IOB_SHIFT (4u)
#define MTU2_TIER_1_TCIEU_SHIFT (5u)
#define MTU2_TSR_1_TCFU_SHIFT (5u)
#define MTU2_TSR_1_TCFD_SHIFT (7u)
#define MTU2_TICCR_I1AE_SHIFT (0u)
#define MTU2_TICCR_I1BE_SHIFT (1u)
#define MTU2_TICCR_I2AE_SHIFT (2u)
#define MTU2_TICCR_I2BE_SHIFT (3u)
#endif /* MTU2_IOBITMASK_H */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ostm_iobitmask.h
* $Rev: 1115 $
* $Date:: 2014-07-09 15:35:02 +0900#$
* Description : OSTM register define header
*******************************************************************************/
#ifndef OSTM_IOBITMASK_H
#define OSTM_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
/* ---- OSTM0 ---- */
#define OSTM0_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
#define OSTM0_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
#define OSTM0_OSTMnTE_OSTMnTE (0x01u)
#define OSTM0_OSTMnTS_OSTMnTS (0x01u)
#define OSTM0_OSTMnTT_OSTMnTT (0x01u)
#define OSTM0_OSTMnCTL_MD0 (0x00000001uL)
#define OSTM0_OSTMnCTL_MD1 (0x00000002uL)
/* ---- OSTM1 ---- */
#define OSTM1_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
#define OSTM1_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
#define OSTM1_OSTMnTE_OSTMnTE (0x01u)
#define OSTM1_OSTMnTS_OSTMnTS (0x01u)
#define OSTM1_OSTMnTT_OSTMnTT (0x01u)
#define OSTM1_OSTMnCTL_MD0 (0x00000001uL)
#define OSTM1_OSTMnCTL_MD1 (0x00000002uL)
/* ---- OSTMn ---- */
#define OSTMn_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
#define OSTMn_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
#define OSTMn_OSTMnTE_OSTMnTE (0x01u)
#define OSTMn_OSTMnTS_OSTMnTS (0x01u)
#define OSTMn_OSTMnTT_OSTMnTT (0x01u)
#define OSTMn_OSTMnCTL_MD0 (0x00000001uL)
#define OSTMn_OSTMnCTL_MD1 (0x00000002uL)
/* ==== Shift values for IO registers ==== */
/* ---- OSTM0 ---- */
#define OSTM0_OSTMnCMP_OSTMnCMP_SHIFT (0u)
#define OSTM0_OSTMnCNT_OSTMnCNT_SHIFT (0u)
#define OSTM0_OSTMnTE_OSTMnTE_SHIFT (0u)
#define OSTM0_OSTMnTS_OSTMnTS_SHIFT (0u)
#define OSTM0_OSTMnTT_OSTMnTT_SHIFT (0u)
#define OSTM0_OSTMnCTL_MD0_SHIFT (0u)
#define OSTM0_OSTMnCTL_MD1_SHIFT (1u)
/* ---- OSTM1 ---- */
#define OSTM1_OSTMnCMP_OSTMnCMP_SHIFT (0u)
#define OSTM1_OSTMnCNT_OSTMnCNT_SHIFT (0u)
#define OSTM1_OSTMnTE_OSTMnTE_SHIFT (0u)
#define OSTM1_OSTMnTS_OSTMnTS_SHIFT (0u)
#define OSTM1_OSTMnTT_OSTMnTT_SHIFT (0u)
#define OSTM1_OSTMnCTL_MD0_SHIFT (0u)
#define OSTM1_OSTMnCTL_MD1_SHIFT (1u)
/* ---- OSTMn ---- */
#define OSTMn_OSTMnCMP_OSTMnCMP_SHIFT (0u)
#define OSTMn_OSTMnCNT_OSTMnCNT_SHIFT (0u)
#define OSTMn_OSTMnTE_OSTMnTE_SHIFT (0u)
#define OSTMn_OSTMnTS_OSTMnTS_SHIFT (0u)
#define OSTMn_OSTMnTT_OSTMnTT_SHIFT (0u)
#define OSTMn_OSTMnCTL_MD0_SHIFT (0u)
#define OSTMn_OSTMnCTL_MD1_SHIFT (1u)
#endif /* OSTM_IOBITMASK_H */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : riic_iobitmask.h
* $Rev: 1114 $
* $Date:: 2014-07-09 14:56:39 +0900#$
* Description : RIIC register define header
*******************************************************************************/
#ifndef RIIC_IOBITMASK_H
#define RIIC_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
#define RIICn_RIICnCR1_SDAI (0x01u)
#define RIICn_RIICnCR1_SCLI (0x02u)
#define RIICn_RIICnCR1_SDAO (0x04u)
#define RIICn_RIICnCR1_SCLO (0x08u)
#define RIICn_RIICnCR1_SOWP (0x10u)
#define RIICn_RIICnCR1_CLO (0x20u)
#define RIICn_RIICnCR1_IICRST (0x40u)
#define RIICn_RIICnCR1_ICE (0x80u)
#define RIICn_RIICnCR2_ST (0x02u)
#define RIICn_RIICnCR2_RS (0x04u)
#define RIICn_RIICnCR2_SP (0x08u)
#define RIICn_RIICnCR2_TRS (0x20u)
#define RIICn_RIICnCR2_MST (0x40u)
#define RIICn_RIICnCR2_BBSY (0x80u)
#define RIICn_RIICnMR1_BC (0x07u)
#define RIICn_RIICnMR1_BCWP (0x08u)
#define RIICn_RIICnMR1_CKS (0x70u)
#define RIICn_RIICnMR1_MTWP (0x80u)
#define RIICn_RIICnMR2_TMOS (0x01u)
#define RIICn_RIICnMR2_TMOL (0x02u)
#define RIICn_RIICnMR2_TMOH (0x04u)
#define RIICn_RIICnMR2_SDDL (0x70u)
#define RIICn_RIICnMR2_DLCS (0x80u)
#define RIICn_RIICnMR3_NF (0x03u)
#define RIICn_RIICnMR3_ACKBR (0x04u)
#define RIICn_RIICnMR3_ACKBT (0x08u)
#define RIICn_RIICnMR3_ACKWP (0x10u)
#define RIICn_RIICnMR3_RDRFS (0x20u)
#define RIICn_RIICnMR3_WAIT (0x40u)
#define RIICn_RIICnMR3_SMBS (0x80u)
#define RIICn_RIICnFER_TMOE (0x01u)
#define RIICn_RIICnFER_MALE (0x02u)
#define RIICn_RIICnFER_NALE (0x04u)
#define RIICn_RIICnFER_SALE (0x08u)
#define RIICn_RIICnFER_NACKE (0x10u)
#define RIICn_RIICnFER_NFE (0x20u)
#define RIICn_RIICnFER_SCLE (0x40u)
#define RIICn_RIICnFER_FMPE (0x80u)
#define RIICn_RIICnSER_SAR0E (0x01u)
#define RIICn_RIICnSER_SAR1E (0x02u)
#define RIICn_RIICnSER_SAR2E (0x04u)
#define RIICn_RIICnSER_GCAE (0x08u)
#define RIICn_RIICnSER_DIDE (0x20u)
#define RIICn_RIICnSER_HOAE (0x80u)
#define RIICn_RIICnIER_TMOIE (0x01u)
#define RIICn_RIICnIER_ALIE (0x02u)
#define RIICn_RIICnIER_STIE (0x04u)
#define RIICn_RIICnIER_SPIE (0x08u)
#define RIICn_RIICnIER_NAKIE (0x10u)
#define RIICn_RIICnIER_RIE (0x20u)
#define RIICn_RIICnIER_TEIE (0x40u)
#define RIICn_RIICnIER_TIE (0x80u)
#define RIICn_RIICnSR1_AAS0 (0x01u)
#define RIICn_RIICnSR1_AAS1 (0x02u)
#define RIICn_RIICnSR1_AAS2 (0x04u)
#define RIICn_RIICnSR1_GCA (0x08u)
#define RIICn_RIICnSR1_DID (0x20u)
#define RIICn_RIICnSR1_HOA (0x80u)
#define RIICn_RIICnSR2_TMOF (0x01u)
#define RIICn_RIICnSR2_AL (0x02u)
#define RIICn_RIICnSR2_START (0x04u)
#define RIICn_RIICnSR2_STOP (0x08u)
#define RIICn_RIICnSR2_NACKF (0x10u)
#define RIICn_RIICnSR2_RDRF (0x20u)
#define RIICn_RIICnSR2_TEND (0x40u)
#define RIICn_RIICnSR2_TDRE (0x80u)
#define RIICn_RIICnSAR0_SVA0 (0x0001u)
#define RIICn_RIICnSAR0_SVA (0x03FEu)
#define RIICn_RIICnSAR0_FSy (0x8000u)
#define RIICn_RIICnSAR1_SVA0 (0x0001u)
#define RIICn_RIICnSAR1_SVA (0x03FEu)
#define RIICn_RIICnSAR1_FSy (0x8000u)
#define RIICn_RIICnSAR2_SVA0 (0x0001u)
#define RIICn_RIICnSAR2_SVA (0x03FEu)
#define RIICn_RIICnSAR2_FSy (0x8000u)
#define RIICn_RIICnBRL_BRL (0x1Fu)
#define RIICn_RIICnBRH_BRH (0x1Fu)
#define RIICn_RIICnDRT_DRT (0xFFu)
#define RIICn_RIICnDRR_DRR (0xFFu)
/* ==== Shift values for IO registers ==== */
#define RIICn_RIICnCR1_SDAI_SHIFT (0u)
#define RIICn_RIICnCR1_SCLI_SHIFT (1u)
#define RIICn_RIICnCR1_SDAO_SHIFT (2u)
#define RIICn_RIICnCR1_SCLO_SHIFT (3u)
#define RIICn_RIICnCR1_SOWP_SHIFT (4u)
#define RIICn_RIICnCR1_CLO_SHIFT (5u)
#define RIICn_RIICnCR1_IICRST_SHIFT (6u)
#define RIICn_RIICnCR1_ICE_SHIFT (7u)
#define RIICn_RIICnCR2_ST_SHIFT (1u)
#define RIICn_RIICnCR2_RS_SHIFT (2u)
#define RIICn_RIICnCR2_SP_SHIFT (3u)
#define RIICn_RIICnCR2_TRS_SHIFT (5u)
#define RIICn_RIICnCR2_MST_SHIFT (6u)
#define RIICn_RIICnCR2_BBSY_SHIFT (7u)
#define RIICn_RIICnMR1_BC_SHIFT (0u)
#define RIICn_RIICnMR1_BCWP_SHIFT (3u)
#define RIICn_RIICnMR1_CKS_SHIFT (4u)
#define RIICn_RIICnMR1_MTWP_SHIFT (7u)
#define RIICn_RIICnMR2_TMOS_SHIFT (0u)
#define RIICn_RIICnMR2_TMOL_SHIFT (1u)
#define RIICn_RIICnMR2_TMOH_SHIFT (2u)
#define RIICn_RIICnMR2_SDDL_SHIFT (4u)
#define RIICn_RIICnMR2_DLCS_SHIFT (7u)
#define RIICn_RIICnMR3_NF_SHIFT (0u)
#define RIICn_RIICnMR3_ACKBR_SHIFT (2u)
#define RIICn_RIICnMR3_ACKBT_SHIFT (3u)
#define RIICn_RIICnMR3_ACKWP_SHIFT (4u)
#define RIICn_RIICnMR3_RDRFS_SHIFT (5u)
#define RIICn_RIICnMR3_WAIT_SHIFT (6u)
#define RIICn_RIICnMR3_SMBS_SHIFT (7u)
#define RIICn_RIICnFER_TMOE_SHIFT (0u)
#define RIICn_RIICnFER_MALE_SHIFT (1u)
#define RIICn_RIICnFER_NALE_SHIFT (2u)
#define RIICn_RIICnFER_SALE_SHIFT (3u)
#define RIICn_RIICnFER_NACKE_SHIFT (4u)
#define RIICn_RIICnFER_NFE_SHIFT (5u)
#define RIICn_RIICnFER_SCLE_SHIFT (6u)
#define RIICn_RIICnFER_FMPE_SHIFT (7u)
#define RIICn_RIICnSER_SAR0E_SHIFT (0u)
#define RIICn_RIICnSER_SAR1E_SHIFT (1u)
#define RIICn_RIICnSER_SAR2E_SHIFT (2u)
#define RIICn_RIICnSER_GCAE_SHIFT (3u)
#define RIICn_RIICnSER_DIDE_SHIFT (5u)
#define RIICn_RIICnSER_HOAE_SHIFT (7u)
#define RIICn_RIICnIER_TMOIE_SHIFT (0u)
#define RIICn_RIICnIER_ALIE_SHIFT (1u)
#define RIICn_RIICnIER_STIE_SHIFT (2u)
#define RIICn_RIICnIER_SPIE_SHIFT (3u)
#define RIICn_RIICnIER_NAKIE_SHIFT (4u)
#define RIICn_RIICnIER_RIE_SHIFT (5u)
#define RIICn_RIICnIER_TEIE_SHIFT (6u)
#define RIICn_RIICnIER_TIE_SHIFT (7u)
#define RIICn_RIICnSR1_AAS0_SHIFT (0u)
#define RIICn_RIICnSR1_AAS1_SHIFT (1u)
#define RIICn_RIICnSR1_AAS2_SHIFT (2u)
#define RIICn_RIICnSR1_GCA_SHIFT (3u)
#define RIICn_RIICnSR1_DID_SHIFT (5u)
#define RIICn_RIICnSR1_HOA_SHIFT (7u)
#define RIICn_RIICnSR2_TMOF_SHIFT (0u)
#define RIICn_RIICnSR2_AL_SHIFT (1u)
#define RIICn_RIICnSR2_START_SHIFT (2u)
#define RIICn_RIICnSR2_STOP_SHIFT (3u)
#define RIICn_RIICnSR2_NACKF_SHIFT (4u)
#define RIICn_RIICnSR2_RDRF_SHIFT (5u)
#define RIICn_RIICnSR2_TEND_SHIFT (6u)
#define RIICn_RIICnSR2_TDRE_SHIFT (7u)
#define RIICn_RIICnSAR0_SVA0_SHIFT (0u)
#define RIICn_RIICnSAR0_SVA_SHIFT (1u)
#define RIICn_RIICnSAR0_FSy_SHIFT (15u)
#define RIICn_RIICnSAR1_SVA0_SHIFT (0u)
#define RIICn_RIICnSAR1_SVA_SHIFT (1u)
#define RIICn_RIICnSAR1_FSy_SHIFT (15u)
#define RIICn_RIICnSAR2_SVA0_SHIFT (0u)
#define RIICn_RIICnSAR2_SVA_SHIFT (1u)
#define RIICn_RIICnSAR2_FSy_SHIFT (15u)
#define RIICn_RIICnBRL_BRL_SHIFT (0u)
#define RIICn_RIICnBRH_BRH_SHIFT (0u)
#define RIICn_RIICnDRT_DRT_SHIFT (0u)
#define RIICn_RIICnDRR_DRR_SHIFT (0u)
#endif /* RIIC_IOBITMASK_H */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : rspi_iobitmask.h
* $Rev: 1114 $
* $Date:: 2014-07-09 14:56:39 +0900#$
* Description : Renesas Serial Peripheral Interface register define header
*******************************************************************************/
#ifndef RSPI_IOBITMASK_H
#define RSPI_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
#define RSPIn_SPCR_MODFEN (0x04u)
#define RSPIn_SPCR_MSTR (0x08u)
#define RSPIn_SPCR_SPEIE (0x10u)
#define RSPIn_SPCR_SPTIE (0x20u)
#define RSPIn_SPCR_SPE (0x40u)
#define RSPIn_SPCR_SPRIE (0x80u)
#define RSPIn_SSLP_SSL0P (0x01u)
#define RSPIn_SPPCR_SPLP (0x01u)
#define RSPIn_SPPCR_MOIFV (0x10u)
#define RSPIn_SPPCR_MOIFE (0x20u)
#define RSPIn_SPSR_OVRF (0x01u)
#define RSPIn_SPSR_MODF (0x04u)
#define RSPIn_SPSR_SPTEF (0x20u)
#define RSPIn_SPSR_TEND (0x40u)
#define RSPIn_SPSR_SPRF (0x80u)
#define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL)
#define RSPIn_SPDR_UINT16 (0xFFFFu)
#define RSPIn_SPDR_UINT8 (0xFFu)
#define RSPIn_SPSCR_SPSLN (0x03u)
#define RSPIn_SPSSR_SPCP (0x03u)
#define RSPIn_SPBR_SPR (0xFFu)
#define RSPIn_SPDCR_SPLW (0x60u)
#define RSPIn_SPDCR_TXDMY (0x80u)
#define RSPIn_SPCKD_SCKDL (0x07u)
#define RSPIn_SSLND_SLNDL (0x07u)
#define RSPIn_SPND_SPNDL (0x07u)
#define RSPIn_SPCMD0_CPHA (0x0001u)
#define RSPIn_SPCMD0_CPOL (0x0002u)
#define RSPIn_SPCMD0_BRDV (0x000Cu)
#define RSPIn_SPCMD0_SSLKP (0x0080u)
#define RSPIn_SPCMD0_SPB (0x0F00u)
#define RSPIn_SPCMD0_LSBF (0x1000u)
#define RSPIn_SPCMD0_SPNDEN (0x2000u)
#define RSPIn_SPCMD0_SLNDEN (0x4000u)
#define RSPIn_SPCMD0_SCKDEN (0x8000u)
#define RSPIn_SPCMD1_CPHA (0x0001u)
#define RSPIn_SPCMD1_CPOL (0x0002u)
#define RSPIn_SPCMD1_BRDV (0x000Cu)
#define RSPIn_SPCMD1_SSLKP (0x0080u)
#define RSPIn_SPCMD1_SPB (0x0F00u)
#define RSPIn_SPCMD1_LSBF (0x1000u)
#define RSPIn_SPCMD1_SPNDEN (0x2000u)
#define RSPIn_SPCMD1_SLNDEN (0x4000u)
#define RSPIn_SPCMD1_SCKDEN (0x8000u)
#define RSPIn_SPCMD2_CPHA (0x0001u)
#define RSPIn_SPCMD2_CPOL (0x0002u)
#define RSPIn_SPCMD2_BRDV (0x000Cu)
#define RSPIn_SPCMD2_SSLKP (0x0080u)
#define RSPIn_SPCMD2_SPB (0x0F00u)
#define RSPIn_SPCMD2_LSBF (0x1000u)
#define RSPIn_SPCMD2_SPNDEN (0x2000u)
#define RSPIn_SPCMD2_SLNDEN (0x4000u)
#define RSPIn_SPCMD2_SCKDEN (0x8000u)
#define RSPIn_SPCMD3_CPHA (0x0001u)
#define RSPIn_SPCMD3_CPOL (0x0002u)
#define RSPIn_SPCMD3_BRDV (0x000Cu)
#define RSPIn_SPCMD3_SSLKP (0x0080u)
#define RSPIn_SPCMD3_SPB (0x0F00u)
#define RSPIn_SPCMD3_LSBF (0x1000u)
#define RSPIn_SPCMD3_SPNDEN (0x2000u)
#define RSPIn_SPCMD3_SLNDEN (0x4000u)
#define RSPIn_SPCMD3_SCKDEN (0x8000u)
#define RSPIn_SPBFCR_RXTRG (0x07u)
#define RSPIn_SPBFCR_TXTRG (0x30u)
#define RSPIn_SPBFCR_RXRST (0x40u)
#define RSPIn_SPBFCR_TXRST (0x80u)
#define RSPIn_SPBFDR_R (0x003Fu)
#define RSPIn_SPBFDR_T (0x0F00u)
/* ==== Shift values for IO registers ==== */
#define RSPIn_SPCR_MODFEN_SHIFT (2u)
#define RSPIn_SPCR_MSTR_SHIFT (3u)
#define RSPIn_SPCR_SPEIE_SHIFT (4u)
#define RSPIn_SPCR_SPTIE_SHIFT (5u)
#define RSPIn_SPCR_SPE_SHIFT (6u)
#define RSPIn_SPCR_SPRIE_SHIFT (7u)
#define RSPIn_SSLP_SSL0P_SHIFT (0u)
#define RSPIn_SPPCR_SPLP_SHIFT (0u)
#define RSPIn_SPPCR_MOIFV_SHIFT (4u)
#define RSPIn_SPPCR_MOIFE_SHIFT (5u)
#define RSPIn_SPSR_OVRF_SHIFT (0u)
#define RSPIn_SPSR_MODF_SHIFT (2u)
#define RSPIn_SPSR_SPTEF_SHIFT (5u)
#define RSPIn_SPSR_TEND_SHIFT (6u)
#define RSPIn_SPSR_SPRF_SHIFT (7u)
#define RSPIn_SPDR_UINT32_SHIFT (0u)
#define RSPIn_SPDR_UINT16_SHIFT (0u)
#define RSPIn_SPDR_UINT8_SHIFT (0u)
#define RSPIn_SPSCR_SPSLN_SHIFT (0u)
#define RSPIn_SPSSR_SPCP_SHIFT (0u)
#define RSPIn_SPBR_SPR_SHIFT (0u)
#define RSPIn_SPDCR_SPLW_SHIFT (5u)
#define RSPIn_SPDCR_TXDMY_SHIFT (7u)
#define RSPIn_SPCKD_SCKDL_SHIFT (0u)
#define RSPIn_SSLND_SLNDL_SHIFT (0u)
#define RSPIn_SPND_SPNDL_SHIFT (0u)
#define RSPIn_SPCMD0_CPHA_SHIFT (0u)
#define RSPIn_SPCMD0_CPOL_SHIFT (1u)
#define RSPIn_SPCMD0_BRDV_SHIFT (2u)
#define RSPIn_SPCMD0_SSLKP_SHIFT (7u)
#define RSPIn_SPCMD0_SPB_SHIFT (8u)
#define RSPIn_SPCMD0_LSBF_SHIFT (12u)
#define RSPIn_SPCMD0_SPNDEN_SHIFT (13u)
#define RSPIn_SPCMD0_SLNDEN_SHIFT (14u)
#define RSPIn_SPCMD0_SCKDEN_SHIFT (15u)
#define RSPIn_SPCMD1_CPHA_SHIFT (0u)
#define RSPIn_SPCMD1_CPOL_SHIFT (1u)
#define RSPIn_SPCMD1_BRDV_SHIFT (2u)
#define RSPIn_SPCMD1_SSLKP_SHIFT (7u)
#define RSPIn_SPCMD1_SPB_SHIFT (8u)
#define RSPIn_SPCMD1_LSBF_SHIFT (12u)
#define RSPIn_SPCMD1_SPNDEN_SHIFT (13u)
#define RSPIn_SPCMD1_SLNDEN_SHIFT (14u)
#define RSPIn_SPCMD1_SCKDEN_SHIFT (15u)
#define RSPIn_SPCMD2_CPHA_SHIFT (0u)
#define RSPIn_SPCMD2_CPOL_SHIFT (1u)
#define RSPIn_SPCMD2_BRDV_SHIFT (2u)
#define RSPIn_SPCMD2_SSLKP_SHIFT (7u)
#define RSPIn_SPCMD2_SPB_SHIFT (8u)
#define RSPIn_SPCMD2_LSBF_SHIFT (12u)
#define RSPIn_SPCMD2_SPNDEN_SHIFT (13u)
#define RSPIn_SPCMD2_SLNDEN_SHIFT (14u)
#define RSPIn_SPCMD2_SCKDEN_SHIFT (15u)
#define RSPIn_SPCMD3_CPHA_SHIFT (0u)
#define RSPIn_SPCMD3_CPOL_SHIFT (1u)
#define RSPIn_SPCMD3_BRDV_SHIFT (2u)
#define RSPIn_SPCMD3_SSLKP_SHIFT (7u)
#define RSPIn_SPCMD3_SPB_SHIFT (8u)
#define RSPIn_SPCMD3_LSBF_SHIFT (12u)
#define RSPIn_SPCMD3_SPNDEN_SHIFT (13u)
#define RSPIn_SPCMD3_SLNDEN_SHIFT (14u)
#define RSPIn_SPCMD3_SCKDEN_SHIFT (15u)
#define RSPIn_SPBFCR_RXTRG_SHIFT (0u)
#define RSPIn_SPBFCR_TXTRG_SHIFT (4u)
#define RSPIn_SPBFCR_RXRST_SHIFT (6u)
#define RSPIn_SPBFCR_TXRST_SHIFT (7u)
#define RSPIn_SPBFDR_R_SHIFT (0u)
#define RSPIn_SPBFDR_T_SHIFT (8u)
#endif /* RSPI_IOBITMASK_H */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : usb_iobitmask.h
* $Rev: 1116 $
* $Date:: 2014-07-09 16:29:19 +0900#$
* Description : USB register define header
*******************************************************************************/
#ifndef USB_IOBITMASK_H
#define USB_IOBITMASK_H
/*==============================================*/
/* SYSCFG */
/*==============================================*/
#define USB_SYSCFG_USBE (0x0001u)
#define USB_SYSCFG_UPLLE (0x0002u)
#define USB_SYSCFG_UCKSEL (0x0004u)
/* #define USB_SYSCFG_RESERVED1 (0x0008u) */
#define USB_SYSCFG_DPRPU (0x0010u)
#define USB_SYSCFG_DRPD (0x0020u)
#define USB_SYSCFG_DCFM (0x0040u)
#define USB_SYSCFG_HSE (0x0080u)
/* #define USB_SYSCFG_RESERVED2 (0xFF00u) */
#define USB_SYSCFG_USBE_SHIFT (0)
#define USB_SYSCFG_UPLLE_SHIFT (1)
#define USB_SYSCFG_UCKSEL_SHIFT (2)
/* #define USB_SYSCFG_RESERVED1_SHIFT (3) */
#define USB_SYSCFG_DPRPU_SHIFT (4)
#define USB_SYSCFG_DRPD_SHIFT (5)
#define USB_SYSCFG_DCFM_SHIFT (6)
#define USB_SYSCFG_HSE_SHIFT (7)
/* #define USB_SYSCFG_RESERVED2_SHIFT (8) */
/*==============================================*/
/* BUSWAIT */
/*==============================================*/
#define USB_BUSWAIT_BWAIT (0x003Fu)
#define USB_BUSWAIT_BWAIT_SHIFT (0)
/*==============================================*/
/* SYSSTS0 */
/*==============================================*/
#define USB_SYSSTS0_LNST (0x0003u)
#define USB_SYSSTS0_SOFEA (0x0020u)
#define USB_SYSSTS0_HTACT (0x0040u)
#define USB_SYSSTS0_LNST_SHIFT (0)
#define USB_SYSSTS0_SOFEA_SHIFT (5)
#define USB_SYSSTS0_HTACT_SHIFT (6)
/*==============================================*/
/* DVSTCTR0 */
/*==============================================*/
#define USB_DVSTCTR0_RHST (0x0007u)
/* #define USB_DVSTCTR0_RESERVED (0x0008u) */
#define USB_DVSTCTR0_UACT (0x0010u)
#define USB_DVSTCTR0_RESUME (0x0020u)
#define USB_DVSTCTR0_USBRST (0x0040u)
#define USB_DVSTCTR0_RWUPE (0x0080u)
#define USB_DVSTCTR0_WKUP (0x0100u)
#define USB_DVSTCTR0_RHST_SHIFT (0)
/* #define USB_DVSTCTR0_RESERVED_SHIFT (3) */
#define USB_DVSTCTR0_UACT_SHIFT (4)
#define USB_DVSTCTR0_RESUME_SHIFT (5)
#define USB_DVSTCTR0_USBRST_SHIFT (6)
#define USB_DVSTCTR0_RWUPE_SHIFT (7)
#define USB_DVSTCTR0_WKUP_SHIFT (8)
/*==============================================*/
/* TESTMODE */
/*==============================================*/
#define USB_TESTMODE_UTST (0x000Fu)
/* #define USB_TESTMODE_RESERVED (0xFFF0u) */
#define USB_TESTMODE_UTST_SHIFT (0)
/* #define USB_TESTMODE_RESERVED_SHIFT (4) */
/*==============================================*/
/* DnFBCFG */
/*==============================================*/
/* #define USB_DnFBCFG_RESERVED1 (0x000Fu) */
#define USB_DnFBCFG_TENDE (0x0010u)
/* #define USB_DnFBCFG_RESERVED2 (0x0FE0u) */
#define USB_DnFBCFG_DFACC (0x3000u)
/* #define USB_DnFBCFG_RESERVED3 (0xC000u) */
/* #define USB_DnFBCFG_RESERVED1_SHIFT (0) */
#define USB_DnFBCFG_TENDE_SHIFT (4)
/* #define USB_DnFBCFG_RESERVED2_SHIFT (5) */
#define USB_DnFBCFG_DFACC_SHIFT (12)
/* #define USB_DnFBCFG_RESERVED3_SHIFT (14) */
/*==============================================*/
/* CFIFO */
/*==============================================*/
#define USB_CFIFO_FIFOPORT (0xFFFFFFFFuL)
#define USB_CFIFO_FIFOPORT_SHIFT (0)
/*==============================================*/
/* DnFIFO */
/*==============================================*/
#define USB_DnFIFO_FIFOPORT (0xFFFFFFFFuL)
#define USB_DnFIFO_FIFOPORT_SHIFT (0)
/*==============================================*/
/* CFIFOSEL */
/*==============================================*/
#define USB_CFIFOSEL_CURPIPE (0x000Fu)
/* #define USB_CFIFOSEL_RESERVED1 (0x0010u) */
#define USB_CFIFOSEL_ISEL_ (0x0020u)
/* #define USB_CFIFOSEL_RESERVED2 (0x00C0u) */
#define USB_CFIFOSEL_BIGEND (0x0100u)
/* #define USB_CFIFOSEL_RESERVED3 (0x0200u) */
#define USB_CFIFOSEL_MBW (0x0C00u)
/* #define USB_CFIFOSEL_RESERVED4 (0x3000u) */
#define USB_CFIFOSEL_REW (0x4000u)
#define USB_CFIFOSEL_RCNT (0x8000u)
#define USB_CFIFOSEL_CURPIPE_SHIFT (0)
/* #define USB_CFIFOSEL_RESERVED1_SHIFT (4) */
#define USB_CFIFOSEL_ISEL_SHIFT_ (5)
/* #define USB_CFIFOSEL_RESERVED2_SHIFT (6) */
#define USB_CFIFOSEL_BIGEND_SHIFT (8)
/* #define USB_CFIFOSEL_RESERVED3_SHIFT (9) */
#define USB_CFIFOSEL_MBW_SHIFT (10)
/* #define USB_CFIFOSEL_RESERVED4_SHIFT (12) */
#define USB_CFIFOSEL_REW_SHIFT (14)
#define USB_CFIFOSEL_RCNT_SHIFT (15)
/*==============================================*/
/* DnFIFOSEL */
/*==============================================*/
#define USB_DnFIFOSEL_CURPIPE (0x000Fu)
/* #define USB_DnFIFOSEL_RESERVED1 (0x00F0u) */
#define USB_DnFIFOSEL_BIGEND (0x0100u)
/* #define USB_DnFIFOSEL_RESERVED2 (0x0200u) */
#define USB_DnFIFOSEL_MBW (0x0C00u)
#define USB_DnFIFOSEL_DREQE (0x1000u)
#define USB_DnFIFOSEL_DCLRM (0x2000u)
#define USB_DnFIFOSEL_REW (0x4000u)
#define USB_DnFIFOSEL_RCNT (0x8000u)
#define USB_DnFIFOSEL_CURPIPE_SHIFT (0)
/* #define USB_DnFIFOSEL_RESERVED1_SHIFT (4) */
#define USB_DnFIFOSEL_BIGEND_SHIFT (8)
/* #define USB_DnFIFOSEL_RESERVED2_SHIFT (9) */
#define USB_DnFIFOSEL_MBW_SHIFT (10)
#define USB_DnFIFOSEL_DREQE_SHIFT (12)
#define USB_DnFIFOSEL_DCLRM_SHIFT (13)
#define USB_DnFIFOSEL_REW_SHIFT (14)
#define USB_DnFIFOSEL_RCNT_SHIFT (15)
/*==============================================*/
/* CFIFOCTR */
/*==============================================*/
#define USB_CFIFOCTR_DTLN (0x0FFFu)
/* #define USB_CFIFOCTR_RESERVED (0x1000u) */
#define USB_CFIFOCTR_FRDY (0x2000u)
#define USB_CFIFOCTR_BCLR (0x4000u)
#define USB_CFIFOCTR_BVAL (0x8000u)
#define USB_CFIFOCTR_DTLN_SHIFT (0)
/* #define USB_CFIFOCTR_RESERVED_SHIFT (12) */
#define USB_CFIFOCTR_FRDY_SHIFT (13)
#define USB_CFIFOCTR_BCLR_SHIFT (14)
#define USB_CFIFOCTR_BVAL_SHIFT (15)
/*==============================================*/
/* DnFIFOCTR */
/*==============================================*/
#define USB_DnFIFOCTR_DTLN (0x0FFFu)
/* #define USB_DnFIFOCTR_RESERVED (0x1000u) */
#define USB_DnFIFOCTR_FRDY (0x2000u)
#define USB_DnFIFOCTR_BCLR (0x4000u)
#define USB_DnFIFOCTR_BVAL (0x8000u)
#define USB_DnFIFOCTR_DTLN_SHIFT (0)
/* #define USB_DnFIFOCTR_RESERVED_SHIFT (12) */
#define USB_DnFIFOCTR_FRDY_SHIFT (13)
#define USB_DnFIFOCTR_BCLR_SHIFT (14)
#define USB_DnFIFOCTR_BVAL_SHIFT (15)
/*==============================================*/
/* INTENB0 */
/*==============================================*/
/* #define USB_INTENB0_RESERVED (0x00FFu) */
#define USB_INTENB0_BRDYE (0x0100u)
#define USB_INTENB0_NRDYE (0x0200u)
#define USB_INTENB0_BEMPE (0x0400u)
#define USB_INTENB0_CTRE (0x0800u)
#define USB_INTENB0_DVSE (0x1000u)
#define USB_INTENB0_SOFE (0x2000u)
#define USB_INTENB0_RSME (0x4000u)
#define USB_INTENB0_VBSE (0x8000u)
/* #define USB_INTENB0_RESERVED_SHIFT (0) */
#define USB_INTENB0_BRDYE_SHIFT (8)
#define USB_INTENB0_NRDYE_SHIFT (9)
#define USB_INTENB0_BEMPE_SHIFT (10)
#define USB_INTENB0_CTRE_SHIFT (11)
#define USB_INTENB0_DVSE_SHIFT (12)
#define USB_INTENB0_SOFE_SHIFT (13)
#define USB_INTENB0_RSME_SHIFT (14)
#define USB_INTENB0_VBSE_SHIFT (15)
/*==============================================*/
/* INTENB1 */
/*==============================================*/
/* #define USB_INTENB1_RESERVED1 (0x000Fu) */
#define USB_INTENB1_SACKE (0x0010u)
#define USB_INTENB1_SIGNE (0x0020u)
#define USB_INTENB1_EOFERRE (0x0040u)
/* #define USB_INTENB1_RESERVED2 (0x0780u) */
#define USB_INTENB1_ATTCHE (0x0800u)
#define USB_INTENB1_DTCHE (0x1000u)
/* #define USB_INTENB1_RESERVED3 (0x2000u) */
#define USB_INTENB1_BCHGE (0x4000u)
/* #define USB_INTENB1_RESERVED4 (0x8000u) */
/* #define USB_INTENB1_RESERVED1_SHIFT (0) */
#define USB_INTENB1_SACKE_SHIFT (4)
#define USB_INTENB1_SIGNE_SHIFT (5)
#define USB_INTENB1_EOFERRE_SHIFT (6)
/* #define USB_INTENB1_RESERVED2_SHIFT (7) */
#define USB_INTENB1_ATTCHE_SHIFT (11)
#define USB_INTENB1_DTCHE_SHIFT (12)
/* #define USB_INTENB1_RESERVED3_SHIFT (13) */
#define USB_INTENB1_BCHGE_SHIFT (14)
/* #define USB_INTENB1_RESERVED4_SHIFT (15) */
/*==============================================*/
/* BRDYENB */
/*==============================================*/
#define USB_BRDYENB (0xFFFFu)
#define USB_BRDYENB_SHIFT (0)
/*==============================================*/
/* NRDYENB */
/*==============================================*/
#define USB_NRDYENB (0xFFFFu)
#define USB_NRDYENB_SHIFT (0)
/*==============================================*/
/* BEMPENB */
/*==============================================*/
#define USB_BEMPENB (0xFFFFu)
#define USB_BEMPENB_SHIFT (0)
/*==============================================*/
/* SOFCFG */
/*==============================================*/
/* #define USB_SOFCFG_RESERVED1 (0x003Fu) */
#define USB_SOFCFG_BRDYM (0x0040u)
/* #define USB_SOFCFG_RESERVED2 (0x0080u) */
#define USB_SOFCFG_TRNENSEL (0x0100u)
/* #define USB_SOFCFG_RESERVED3 (0xFE00u) */
/* #define USB_SOFCFG_RESERVED1_SHIFT (0) */
#define USB_SOFCFG_BRDYM_SHIFT (6)
/* #define USB_SOFCFG_RESERVED2_SHIFT (7) */
#define USB_SOFCFG_TRNENSEL_SHIFT (8)
/* #define USB_SOFCFG_RESERVED3_SHIFT (9) */
/*==============================================*/
/* INTSTS0 */
/*==============================================*/
#define USB_INTSTS0_CTSQ (0x0007u)
#define USB_INTSTS0_VALID (0x0008u)
#define USB_INTSTS0_DVSQ (0x0070u)
#define USB_INTSTS0_VBSTS (0x0080u)
#define USB_INTSTS0_BRDY (0x0100u)
#define USB_INTSTS0_NRDY (0x0200u)
#define USB_INTSTS0_BEMP (0x0400u)
#define USB_INTSTS0_CTRT (0x0800u)
#define USB_INTSTS0_DVST (0x1000u)
#define USB_INTSTS0_SOFR (0x2000u)
#define USB_INTSTS0_RESM (0x4000u)
#define USB_INTSTS0_VBINT (0x8000u)
#define USB_INTSTS0_CTSQ_SHIFT (0)
#define USB_INTSTS0_VALID_SHIFT (3)
#define USB_INTSTS0_DVSQ_SHIFT (4)
#define USB_INTSTS0_VBSTS_SHIFT (7)
#define USB_INTSTS0_BRDY_SHIFT (8)
#define USB_INTSTS0_NRDY_SHIFT (9)
#define USB_INTSTS0_BEMP_SHIFT (10)
#define USB_INTSTS0_CTRT_SHIFT (11)
#define USB_INTSTS0_DVST_SHIFT (12)
#define USB_INTSTS0_SOFR_SHIFT (13)
#define USB_INTSTS0_RESM_SHIFT (14)
#define USB_INTSTS0_VBINT_SHIFT (15)
/*==============================================*/
/* INTSTS1 */
/*==============================================*/
/* #define USB_INTSTS1_RESERVED1 (0x000Fu) */
#define USB_INTSTS1_SACK (0x0010u)
#define USB_INTSTS1_SIGN (0x0020u)
#define USB_INTSTS1_EOFERR (0x0040u)
/* #define USB_INTSTS1_RESERVED2 (0x0780u) */
#define USB_INTSTS1_ATTCH (0x0800u)
#define USB_INTSTS1_DTCH (0x1000u)
/* #define USB_INTSTS1_RESERVED3 (0x2000u) */
#define USB_INTSTS1_BCHG (0x4000u)
/* #define USB_INTSTS1_RESERVED4 (0x8000u) */
/* #define USB_INTSTS1_RESERVED1_SHIFT (0) */
#define USB_INTSTS1_SACK_SHIFT (4)
#define USB_INTSTS1_SIGN_SHIFT (5)
#define USB_INTSTS1_EOFERR_SHIFT (6)
/* #define USB_INTSTS1_RESERVED2_SHIFT (7) */
#define USB_INTSTS1_ATTCH_SHIFT (11)
#define USB_INTSTS1_DTCH_SHIFT (12)
/* #define USB_INTSTS1_RESERVED3_SHIFT (13) */
#define USB_INTSTS1_BCHG_SHIFT (14)
/* #define USB_INTSTS1_RESERVED4_SHIFT (15) */
/*==============================================*/
/* BRDYSTS */
/*==============================================*/
#define USB_BRDYSTS (0xFFFFu)
#define USB_BRDYSTS_SHIFT (0)
/*==============================================*/
/* NRDYSTS */
/*==============================================*/
#define USB_NRDYSTS (0xFFFFu)
#define USB_NRDYSTS_SHIFT (0)
/*==============================================*/
/* BEMPSTS */
/*==============================================*/
#define USB_BEMPSTS (0xFFFFu)
#define USB_BEMPSTS_SHIFT (0)
/*==============================================*/
/* FRMNUM */
/*==============================================*/
#define USB_FRMNUM_FRNM (0x07FFu)
/* #define USB_FRMNUM_RESERVED (0x3800u) */
#define USB_FRMNUM_CRCE (0x4000u)
#define USB_FRMNUM_OVRN (0x8000u)
#define USB_FRMNUM_FRNM_SHIFT (0)
/* #define USB_FRMNUM_RESERVED_SHIFT (11) */
#define USB_FRMNUM_CRCE_SHIFT (14)
#define USB_FRMNUM_OVRN_SHIFT (15)
/*==============================================*/
/* UFRMNUM */
/*==============================================*/
#define USB_UFRMNUM_UFRNM (0x0007u)
/* #define USB_UFRMNUM_RESERVED (0xFFF8u) */
#define USB_UFRMNUM_UFRNM_SHIFT (0)
/* #define USB_UFRMNUM_RESERVED_SHIFT (3) */
/*==============================================*/
/* USBADDR */
/*==============================================*/
#define USB_USBADDR_USBADDR (0x007Fu)
/* #define USB_USBADDR_RESERVED (0xFF80u) */
#define USB_USBADDR_USBADDR_SHIFT (0)
/* #define USB_USBADDR_RESERVED_SHIFT (7) */
/*==============================================*/
/* USBREQ */
/*==============================================*/
#define USB_USBREQ_BMREQUESTTYPE (0x00FFu)
#define USB_USBREQ_BREQUEST (0xFF00u)
#define USB_USBREQ_BMREQUESTTYPE_SHIFT (0)
#define USB_USBREQ_BREQUEST_SHIFT (8)
/*==============================================*/
/* USBVAL */
/*==============================================*/
#define USB_USBVAL (0xFFFFu)
#define USB_USBVAL_SHIFT (0)
/*==============================================*/
/* USBINDX */
/*==============================================*/
#define USB_USBINDX (0xFFFFu)
#define USB_USBINDX_SHIFT (0)
/*==============================================*/
/* USBLENG */
/*==============================================*/
#define USB_USBLENG (0xFFFFu)
#define USB_USBLENG_SHIFT (0)
/*==============================================*/
/* DCPCFG */
/*==============================================*/
/* #define USB_DCPCFG_RESERVED1 (0x000Fu) */
#define USB_DCPCFG_DIR (0x0010u)
/* #define USB_DCPCFG_RESERVED2 (0x0060u) */
#define USB_DCPCFG_SHTNAK (0x0080u)
#define USB_DCPCFG_CNTMD (0x0100u)
/* #define USB_DCPCFG_RESERVED3 (0xFE00u) */
/* #define USB_DCPCFG_RESERVED1_SHIFT (0) */
#define USB_DCPCFG_DIR_SHIFT (4)
/* #define USB_DCPCFG_RESERVED2_SHIFT (5) */
#define USB_DCPCFG_SHTNK_SHIFT (7)
#define USB_DCPCFG_CNTMD_SHIFT (8)
/* #define USB_DCPCFG_RESERVED3 (9) */
/*==============================================*/
/* DCPMAXP */
/*==============================================*/
#define USB_DCPMAXP_MXPS (0x007Fu)
/* #define USB_DCPMAXP_RESERVED (0x0F80u) */
#define USB_DCPMAXP_DEVSEL (0xF000u)
#define USB_DCPMAXP_MXPS_SHIFT (0)
/* #define USB_DCPMAXP_RESERVED_SHIFT (7) */
#define USB_DCPMAXP_DEVSEL_SHIFT (12)
/*==============================================*/
/* DCPCTR */
/*==============================================*/
#define USB_DCPCTR_PID (0x0003u)
#define USB_DCPCTR_CCPL (0x0004u)
/* #define USB_DCPCTR_RESERVED1 (0x0008u) */
#define USB_DCPCTR_PINGE (0x0010u)
#define USB_DCPCTR_PBUSY (0x0020u)
#define USB_DCPCTR_SQMON (0x0040u)
#define USB_DCPCTR_SQSET (0x0080u)
#define USB_DCPCTR_SQCLR (0x0100u)
/* #define USB_DCPCTR_RESERVED2 (0x0600u) */
#define USB_DCPCTR_SUREQCLR (0x0800u)
#define USB_DCPCTR_CSSTS (0x1000u)
#define USB_DCPCTR_CSCLR (0x2000u)
#define USB_DCPCTR_SUREQ (0x4000u)
#define USB_DCPCTR_BSTS (0x8000u)
#define USB_DCPCTR_PID_SHIFT (0)
#define USB_DCPCTR_CCPL_SHIFT (2)
/* #define USB_DCPCTR_RESERVED1_SHIFT (3) */
#define USB_DCPCTR_PINGE_SHIFT (4)
#define USB_DCPCTR_PBUSY_SHIFT (5)
#define USB_DCPCTR_SQMON_SHIFT (6)
#define USB_DCPCTR_SQSET_SHIFT (7)
#define USB_DCPCTR_SQCLR_SHIFT (8)
/* #define USB_DCPCTR_RESERVED2_SHIFT (9) */
#define USB_DCPCTR_SUREQCLR_SHIFT (11)
#define USB_DCPCTR_CSSTS_SHIFT (12)
#define USB_DCPCTR_CSCLR_SHIFT (13)
#define USB_DCPCTR_SUREQ_SHIFT (14)
#define USB_DCPCTR_BSTS_SHIFT (15)
/*==============================================*/
/* PIPESEL */
/*==============================================*/
#define USB_PIPESEL_PIPESEL (0x000Fu)
/* #define USB_PIPESEL_RESERVED (0xFFF0u) */
#define USB_PIPESEL_PIPESEL_SHIFT (0)
/* #define USB_PIPESEL_RESERVED_SHIFT (4) */
/*==============================================*/
/* PIPECFG */
/*==============================================*/
#define USB_PIPECFG_EPNUM (0x000Fu)
#define USB_PIPECFG_DIR (0x0010u)
/* #define USB_PIPECFG_RESERVED1 (0x0060u) */
#define USB_PIPECFG_SHTNAK (0x0080u)
#define USB_PIPECFG_CNTMD (0x0100u)
#define USB_PIPECFG_DBLB (0x0200u)
#define USB_PIPECFG_BFRE (0x0400u)
/* #define USB_PIPECFG_RESERVED2 (0x3800u) */
#define USB_PIPECFG_TYPE (0xC000u)
#define USB_PIPECFG_EPNUM_SHIFT (0)
#define USB_PIPECFG_DIR_SHIFT (4)
/* #define USB_PIPECFG_RESERVED1_SHIFT (5) */
#define USB_PIPECFG_SHTNAK_SHIFT (7)
#define USB_PIPECFG_CNTMD_SHIFT (8)
#define USB_PIPECFG_DBLB_SHIFT (9)
#define USB_PIPECFG_BFRE_SHIFT (10)
/* #define USB_PIPECFG_RESERVED2_SHIFT (11) */
#define USB_PIPECFG_TYPE_SHIFT (14)
/*==============================================*/
/* PIPEBUF */
/*==============================================*/
#define USB_PIPEBUF_BUFNMB (0x00FFu)
/* #define USB_PIPEBUF_RESERVED1 (0x0300u) */
#define USB_PIPEBUF_BUFSIZE (0x7C00u)
/* #define USB_PIPEBUF_RESERVED2 (0x8000u) */
#define USB_PIPEBUF_BUFNMB_SHIFT (0)
/* #define USB_PIPEBUF_RESERVED1_SHIFT (8) */
#define USB_PIPEBUF_BUFSIZE_SHIFT (10)
/* #define USB_PIPEBUF_RESERVED2_SHIFT (15) */
/*==============================================*/
/* PIPEMAXP */
/*==============================================*/
#define USB_PIPEMAXP_MXPS (0x07FFu)
/* #define USB_PIPEMAXP_RESERVED (0x0800u) */
#define USB_PIPEMAXP_DEVSEL (0xF000u)
#define USB_PIPEMAXP_MXPS_SHIFT (0)
/* #define USB_PIPEMAXP_RESERVED_SHIFT (11) */
#define USB_PIPEMAXP_DEVSEL_SHIFT (12)
/*==============================================*/
/* PIPEPERI */
/*==============================================*/
#define USB_PIPEPERI_IITV (0x0007u)
/* #define USB_PIPEPERI_RESERVED1 (0x0FF8u) */
#define USB_PIPEPERI_IFIS (0x1000u)
/* #define USB_PIPEPERI_RESERVED2 (0xE000u) */
#define USB_PIPEPERI_IITV_SHIFT (0)
/* #define USB_PIPEPERI_RESERVED1_SHIFT (3) */
#define USB_PIPEPERI_IFIS_SHIFT (12)
/* #define USB_PIPEPERI_RESERVED2_SHIFT (13) */
/*==============================================*/
/* PIPEnCTR_1_5 */
/*==============================================*/
#define USB_PIPEnCTR_1_5_PID (0x0003u)
/* #define USB_PIPEnCTR_1_5_RESERVED1 (0x001Cu) */
#define USB_PIPEnCTR_1_5_PBUSY (0x0020u)
#define USB_PIPEnCTR_1_5_SQMON (0x0040u)
#define USB_PIPEnCTR_1_5_SQSET (0x0080u)
#define USB_PIPEnCTR_1_5_SQCLR (0x0100u)
#define USB_PIPEnCTR_1_5_ACLRM (0x0200u)
#define USB_PIPEnCTR_1_5_ATREPM (0x0400u)
/* #define USB_PIPEnCTR_1_5_RESERVED2 (0x0800u) */
#define USB_PIPEnCTR_1_5_CSSTS (0x1000u)
#define USB_PIPEnCTR_1_5_CSCLR (0x2000u)
#define USB_PIPEnCTR_1_5_INBUFM (0x4000u)
#define USB_PIPEnCTR_1_5_BSTS (0x8000u)
#define USB_PIPEnCTR_1_5_PID_SHIFT (0)
/* #define USB_PIPEnCTR_1_5_RESERVED1_SHIFT (2) */
#define USB_PIPEnCTR_1_5_PBUSY_SHIFT (5)
#define USB_PIPEnCTR_1_5_SQMON_SHIFT (6)
#define USB_PIPEnCTR_1_5_SQSET_SHIFT (7)
#define USB_PIPEnCTR_1_5_SQCLR_SHIFT (8)
#define USB_PIPEnCTR_1_5_ACLRM_SHIFT (9)
#define USB_PIPEnCTR_1_5_ATREPM_SHIFT (10)
/* #define USB_PIPEnCTR_1_5_RESERVED2_SHIFT (11) */
#define USB_PIPEnCTR_1_5_CSSTS_SHIFT (12)
#define USB_PIPEnCTR_1_5_CSCLR_SHIFT (13)
#define USB_PIPEnCTR_1_5_INBUFM_SHIFT (14)
#define USB_PIPEnCTR_1_5_BSTS_SHIFT (15)
/*==============================================*/
/* PIPEnCTR_6_8 */
/*==============================================*/
#define USB_PIPEnCTR_6_8_PID (0x0003u)
/* #define USB_PIPEnCTR_6_8_RESERVED1 (0x001Cu) */
#define USB_PIPEnCTR_6_8_PBUSY (0x0020u)
#define USB_PIPEnCTR_6_8_SQMON (0x0040u)
#define USB_PIPEnCTR_6_8_SQSET (0x0080u)
#define USB_PIPEnCTR_6_8_SQCLR (0x0100u)
#define USB_PIPEnCTR_6_8_ACLRM (0x0200u)
/* #define USB_PIPEnCTR_6_8_RESERVED2 (0x0C00u) */
#define USB_PIPEnCTR_6_8_CSSTS (0x1000u)
#define USB_PIPEnCTR_6_8_CSCLR (0x2000u)
/* #define USB_PIPEnCTR_6_8_RESERVED3 (0x4000u) */
#define USB_PIPEnCTR_6_8_BSTS (0x8000u)
#define USB_PIPEnCTR_6_8_PID_SHIFT (0)
/* #define USB_PIPEnCTR_6_8_RESERVED1_SHIFT (2) */
#define USB_PIPEnCTR_6_8_PBUSY_SHIFT (5)
#define USB_PIPEnCTR_6_8_SQMON_SHIFT (6)
#define USB_PIPEnCTR_6_8_SQSET_SHIFT (7)
#define USB_PIPEnCTR_6_8_SQCLR_SHIFT (8)
#define USB_PIPEnCTR_6_8_ACLRM_SHIFT (9)
/* #define USB_PIPEnCTR_6_8_RESERVED2_SHIFT (10) */
#define USB_PIPEnCTR_6_8_CSSTS_SHIFT (12)
#define USB_PIPEnCTR_6_8_CSCLR_SHIFT (13)
/* #define USB_PIPEnCTR_6_8_RESERVED3_SHIFT (14) */
#define USB_PIPEnCTR_6_8_BSTS_SHIFT (15)
/*==============================================*/
/* PIPEnCTR_9 */
/*==============================================*/
#define USB_PIPEnCTR_9_PID (0x0003u)
/* #define USB_PIPEnCTR_9_RESERVED1 (0x001Cu) */
#define USB_PIPEnCTR_9_PBUSY (0x0020u)
#define USB_PIPEnCTR_9_SQMON (0x0040u)
#define USB_PIPEnCTR_9_SQSET (0x0080u)
#define USB_PIPEnCTR_9_SQCLR (0x0100u)
#define USB_PIPEnCTR_9_ACLRM (0x0200u)
#define USB_PIPEnCTR_9_ATREPM (0x0400u)
/* #define USB_PIPEnCTR_9_RESERVED2 (0x0800u) */
#define USB_PIPEnCTR_9_CSSTS (0x1000u)
#define USB_PIPEnCTR_9_CSCLR (0x2000u)
#define USB_PIPEnCTR_9_INBUFM (0x4000u)
#define USB_PIPEnCTR_9_BSTS (0x8000u)
#define USB_PIPEnCTR_9_PID_SHIFT (0)
/* #define USB_PIPEnCTR_9_RESERVED1_SHIFT (2) */
#define USB_PIPEnCTR_9_PBUSY_SHIFT (5)
#define USB_PIPEnCTR_9_SQMON_SHIFT (6)
#define USB_PIPEnCTR_9_SQSET_SHIFT (7)
#define USB_PIPEnCTR_9_SQCLR_SHIFT (8)
#define USB_PIPEnCTR_9_ACLRM_SHIFT (9)
#define USB_PIPEnCTR_9_ATREPM_SHIFT (10)
/* #define USB_PIPEnCTR_9_RESERVED2_SHIFT (11) */
#define USB_PIPEnCTR_9_CSSTS_SHIFT (12)
#define USB_PIPEnCTR_9_CSCLR_SHIFT (13)
#define USB_PIPEnCTR_9_INBUFM_SHIFT (14)
#define USB_PIPEnCTR_9_BSTS_SHIFT (15)
/*==============================================*/
/* PIPEnCTR_A_F */
/*==============================================*/
#define USB_PIPEnCTR_A_F_PID (0x0003u)
/* #define USB_PIPEnCTR_A_F_RESERVED1 (0x001Cu) */
#define USB_PIPEnCTR_A_F_PBUSY (0x0020u)
#define USB_PIPEnCTR_A_F_SQMON (0x0040u)
#define USB_PIPEnCTR_A_F_SQSET (0x0080u)
#define USB_PIPEnCTR_A_F_SQCLR (0x0100u)
#define USB_PIPEnCTR_A_F_ACLRM (0x0200u)
#define USB_PIPEnCTR_A_F_ATREPM (0x0400u)
/* #define USB_PIPEnCTR_A_F_RESERVED2 (0x3800u) */
#define USB_PIPEnCTR_A_F_INBUFM (0x4000u)
#define USB_PIPEnCTR_A_F_BSTS (0x8000u)
#define USB_PIPEnCTR_A_F_PID_SHIFT (0)
/* #define USB_PIPEnCTR_A_F_RESERVED1_SHIFT (2) */
#define USB_PIPEnCTR_A_F_PBUSY_SHIFT (5)
#define USB_PIPEnCTR_A_F_SQMON_SHIFT (6)
#define USB_PIPEnCTR_A_F_SQSET_SHIFT (7)
#define USB_PIPEnCTR_A_F_SQCLR_SHIFT (8)
#define USB_PIPEnCTR_A_F_ACLRM_SHIFT (9)
#define USB_PIPEnCTR_A_F_ATREPM_SHIFT (10)
/* #define USB_PIPEnCTR_A_F_RESERVED2_SHIFT (11) */
#define USB_PIPEnCTR_A_F_INBUFM_SHIFT (14)
#define USB_PIPEnCTR_A_F_BSTS_SHIFT (15)
/*==============================================*/
/* PIPEnTRE */
/*==============================================*/
/* #define USB_PIPEnTRE_RESERVED1 (0x00FFu) */
#define USB_PIPEnTRE_TRCLR (0x0100u)
#define USB_PIPEnTRE_TRENB (0x0200u)
/* #define USB_PIPEnTRE_RESERVED2 (0xFC00u) */
/* #define USB_PIPEnTRE_RESERVED1_SHIFT (0) */
#define USB_PIPEnTRE_TRCLR_SHIFT (8)
#define USB_PIPEnTRE_TRENB_SHIFT (9)
/* #define USB_PIPEnTRE_RESERVED2_SHIFT (10) */
/*==============================================*/
/* PIPEnTRN */
/*==============================================*/
#define USB_PIPEnTRN (0xFFFFu)
#define USB_PIPEnTRN_SHIFT (0)
/*==============================================*/
/* DEVADDn */
/*==============================================*/
/* #define USB_DEVADDn_RESERVED1 (0x003Fu) */
#define USB_DEVADDn_USBSPD (0x00C0u)
#define USB_DEVADDn_HUBPORT (0x0700u)
#define USB_DEVADDn_UPPHUB (0x7800u)
/* #define USB_DEVADDn_RESERVED2 (0x8000u) */
/* #define USB_DEVADDn_RESERVED1_SHIFT (0) */
#define USB_DEVADDn_USBSPD_SHIFT (6)
#define USB_DEVADDn_HUBPORT_SHIFT (8)
#define USB_DEVADDn_UPPHUB_SHIFT (11)
/* #define USB_DEVADDn_RESERVED2_SHIFT (15) */
/*==============================================*/
/* SUSPMODE */
/*==============================================*/
/* #define USB_SUSPMODE_RESERVED1 (0x3FFFu) */
#define USB_SUSPMODE_SUSPM (0x4000u)
/* #define USB_SUSPMODE_RESERVED2 (0x8000u) */
/* #define USB_SUSPMODE_RESERVED1_SHIFT (0) */
#define USB_SUSPMODE_SUSPM_SHIFT (14)
/* #define USB_SUSPMODE_RESERVED2_SHIFT (15) */
/*==============================================*/
/* DnFIFOBm */
/*==============================================*/
#define USB_DnFIFOBm (0xFFFFu)
#define USB_DnFIFOBm_SHIFT (0)
#endif /* USB_IOBITMASK_H */
/* End of File */

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libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/rza_io_regrw.h Normal file
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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : rza_io_regrw.h
* $Rev: 1135 $
* $Date:: 2014-08-08 10:11:30 +0900#$
* Description : Low level register read/write header
*******************************************************************************/
#ifndef RZA_IO_REGRW_H
#define RZA_IO_REGRW_H
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
/* ==== includes each bit mask header ==== */
#include "iobitmasks/cpg_iobitmask.h"
#include "iobitmasks/intc_iobitmask.h"
#include "iobitmasks/bsc_iobitmask.h"
#include "iobitmasks/dmac_iobitmask.h"
#include "iobitmasks/mtu2_iobitmask.h"
#include "iobitmasks/ostm_iobitmask.h"
#include "iobitmasks/scif_iobitmask.h"
#include "iobitmasks/rspi_iobitmask.h"
#include "iobitmasks/riic_iobitmask.h"
#include "iobitmasks/usb_iobitmask.h"
#include "iobitmasks/gpio_iobitmask.h"
#ifdef __cplusplus
extern "C" {
#endif
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
/******************************************************************************
Variable Externs
******************************************************************************/
/******************************************************************************
Functions Prototypes
******************************************************************************/
void RZA_IO_RegWrite_8 (volatile uint8_t * ioreg, uint8_t write_value, uint8_t shift, uint8_t mask);
void RZA_IO_RegWrite_16(volatile uint16_t * ioreg, uint16_t write_value, uint16_t shift, uint16_t mask);
void RZA_IO_RegWrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask);
uint8_t RZA_IO_RegRead_8 (volatile uint8_t * ioreg, uint8_t shift, uint8_t mask);
uint16_t RZA_IO_RegRead_16 (volatile uint16_t * ioreg, uint16_t shift, uint16_t mask);
uint32_t RZA_IO_RegRead_32 (volatile uint32_t * ioreg, uint32_t shift, uint32_t mask);
#ifdef __cplusplus
}
#endif
#endif /* RZA_IO_REGRW_H */
/* End of File */