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Merge pull request #14718 from Meano/develop 

Feature: Make changes for Cortex-A5 support
pull/14850/head
Jaeden Amero 2021-07-01 10:23:41 +01:00 committed by GitHub
parent 43116a2822 2d2d1cf956
commit b5c2f7079e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
37 changed files with 37 additions and 41 deletions
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4
cmsis/device/rtos/source/mbed_boot.c
View File

@ -128,7 +128,7 @@ static void mbed_cpy_nvic(void)
VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is
responsible for correctly handling the vectors.
*/
#if !defined(__CORTEX_M0) && !defined(__CORTEX_A9)
#if !defined(__CORTEX_M0) && !defined(__CORTEX_A)
#ifdef NVIC_RAM_VECTOR_ADDRESS
uint32_t *old_vectors = (uint32_t *)SCB->VTOR;
uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
@ -137,5 +137,5 @@ static void mbed_cpy_nvic(void)
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
#endif /* NVIC_RAM_VECTOR_ADDRESS */
#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A9) */
#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A) */
}

2
hal/source/mbed_critical_section_api.c
View File

@ -26,7 +26,7 @@ static bool state_saved = false;
static bool are_interrupts_enabled(void)
{
#if defined(__CORTEX_A9)
#if defined(__CORTEX_A)
return ((__get_CPSR() & 0x80) == 0);
#else
return ((__get_PRIMASK() & 0x1) == 0);

2
hal/tests/TESTS/mbed_hal/critical_section/main.cpp
View File

@ -29,7 +29,7 @@ using utest::v1::Case;
bool test_are_interrupts_enabled(void)
{
#if defined(__CORTEX_A9)
#if defined(__CORTEX_A)
return ((__get_CPSR() & 0x80) == 0);
#else
return ((__get_PRIMASK() & 0x1) == 0);

2
platform/include/platform/mbed_application.h
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@ -21,7 +21,7 @@
#include<stdint.h>
#if defined(__CORTEX_M0PLUS) || defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7)\
|| defined(__CORTEX_M23) || defined(__CORTEX_A9) || defined(__CORTEX_M33)
|| defined(__CORTEX_M23) || defined(__CORTEX_A9) || defined(__CORTEX_A5) || defined(__CORTEX_M33)
#define MBED_APPLICATION_SUPPORT 1
#else
#define MBED_APPLICATION_SUPPORT 0

2
platform/source/mbed_application.c
View File

@ -23,7 +23,7 @@
#if MBED_APPLICATION_SUPPORT
#if defined(__CORTEX_A9)
#if defined(__CORTEX_A9) || defined(__CORTEX_A5)
static void powerdown_gic(void);

4
platform/source/mbed_critical.c
View File

@ -27,7 +27,7 @@ static uint32_t critical_section_reentrancy_counter = 0;
bool core_util_are_interrupts_enabled(void)
{
#if defined(__CORTEX_A9)
#if defined(__CORTEX_A)
return ((__get_CPSR() & 0x80) == 0);
#else
return ((__get_PRIMASK() & 0x1) == 0);
@ -36,7 +36,7 @@ bool core_util_are_interrupts_enabled(void)
bool core_util_is_isr_active(void)
{
#if defined(__CORTEX_A9)
#if defined(__CORTEX_A)
switch (__get_CPSR() & 0x1FU) {
case CPSR_M_USR:
case CPSR_M_SYS:

4
platform/source/mbed_sdk_boot.c
View File

@ -63,7 +63,7 @@ void mbed_copy_nvic(void)
VTOR register and for A9 for which CMSIS doesn't define NVIC_SetVector; in both cases target code is
responsible for correctly handling the vectors.
*/
#if !defined(__CORTEX_M0) && !defined(__CORTEX_A9)
#if !defined(__CORTEX_M0) && !defined(__CORTEX_A)
#ifdef NVIC_RAM_VECTOR_ADDRESS
uint32_t *old_vectors = (uint32_t *)SCB->VTOR;
uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
@ -72,7 +72,7 @@ void mbed_copy_nvic(void)
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
#endif /* NVIC_RAM_VECTOR_ADDRESS */
#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A9) */
#endif /* !defined(__CORTEX_M0) && !defined(__CORTEX_A) */
}
void mbed_init(void)

2
platform/source/mbed_wait_api_no_rtos.c
View File

@ -91,7 +91,7 @@ void wait_us(int us)
#define LOOP_SCALER 2000
#endif
#elif defined __CORTEX_A
#if __CORTEX_A == 9
#if __CORTEX_A == 9 || __CORTEX_A == 5
// Cortex-A9 can dual issue for 3 cycles per iteration (SUB,NOP) = 1, (NOP,BCS) = 2
#define LOOP_SCALER 3000
#endif

2
platform/tests/TESTS/mbed_platform/stats_cpu/main.cpp
View File

@ -33,7 +33,7 @@ DigitalOut led1(LED1);
#endif
// Targets with these cores have their RAM enough size to create threads with bigger stacks
#if defined(__CORTEX_A9) || defined(__CORTEX_M23) || defined(__CORTEX_M33) || defined(__CORTEX_M7)
#if defined(__CORTEX_A9) || defined(__CORTEX_A5) || defined(__CORTEX_M23) || defined(__CORTEX_M33) || defined(__CORTEX_M7)
#define MAX_THREAD_STACK 512
#else
#define MAX_THREAD_STACK 384

2
rtos/tests/TESTS/mbed_rtos/malloc/main.cpp
View File

@ -32,7 +32,7 @@ volatile bool thread_should_continue = true;
#define NUM_THREADS 4
#define THREAD_MALLOC_SIZE 100
#if defined(__CORTEX_A9)
#if defined(__CORTEX_A9) || defined(__CORTEX_A5)
#define THREAD_STACK_SIZE 512
#elif defined(__CORTEX_M23) || defined(__CORTEX_M33)
#define THREAD_STACK_SIZE 512

2
rtos/tests/TESTS/mbed_rtos/threads/main.cpp
View File

@ -32,7 +32,7 @@
#include <type_traits>
#define THREAD_STACK_SIZE 512
#if defined(__CORTEX_A9) || defined(__CORTEX_M23) || defined(__CORTEX_M33) || defined(TARGET_ARM_FM) || defined(TARGET_CY8CKIT_062_WIFI_BT_PSA)
#if defined(__CORTEX_A9) || defined(__CORTEX_A5) || defined(__CORTEX_M23) || defined(__CORTEX_M33) || defined(TARGET_ARM_FM) || defined(TARGET_CY8CKIT_062_WIFI_BT_PSA)
#define PARALLEL_THREAD_STACK_SIZE 512
#define CHILD_THREAD_STACK_SIZE 512
#else

9
tools/cmake/cores/Cortex-A9.cmake → tools/cmake/cores/Cortex-A.cmake
View File

@ -8,24 +8,23 @@ if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
"-mfpu=vfpv3"
"-mfloat-abi=softfp"
"-mno-unaligned-access"
"-mcpu=cortex-a9"
"-mcpu=${CMAKE_SYSTEM_PROCESSOR}"
)
elseif(${MBED_TOOLCHAIN} STREQUAL "ARM")
list(APPEND common_options
"-mfpu=vfpv3"
"-mfloat-abi=hard"
"-mcpu=cortex-a9"
"-mcpu=${CMAKE_SYSTEM_PROCESSOR}"
)
endif()
function(mbed_set_cpu_core_definitions target)
target_compile_definitions(${target}
INTERFACE
__CORTEX_A9
ARM_MATH_CA9
__CORTEX_${MBED_CPU_CORE_CODE}
ARM_MATH_C${MBED_CPU_CORE_CODE}
__FPU_PRESENT
__CMSIS_RTOS
__EVAL
__MBED_CMSIS_RTOS_CA9
)
endfunction()

1
tools/cmake/cores/Cortex-M0+.cmake
View File

@ -19,6 +19,5 @@ function(mbed_set_cpu_core_definitions target)
__CORTEX_M0PLUS
ARM_MATH_CM0PLUS
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M0.cmake
View File

@ -19,6 +19,5 @@ function(mbed_set_cpu_core_definitions target)
__CORTEX_M0
ARM_MATH_CM0
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M1.cmake
View File

@ -19,6 +19,5 @@ function(mbed_set_cpu_core_definitions target)
__CORTEX_M3
ARM_MATH_CM1
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M23-NS.cmake
View File

@ -21,6 +21,5 @@ function(mbed_set_cpu_core_definitions target)
ARM_MATH_ARMV8MBL
DOMAIN_NS=1
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M23.cmake
View File

@ -20,6 +20,5 @@ function(mbed_set_cpu_core_definitions target)
__CORTEX_M23
ARM_MATH_ARMV8MBL
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M3.cmake
View File

@ -19,6 +19,5 @@ function(mbed_set_cpu_core_definitions target)
__CORTEX_M3
ARM_MATH_CM3
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M33-NS.cmake
View File

@ -28,6 +28,5 @@ function(mbed_set_cpu_core_definitions target)
ARM_MATH_ARMV8MML
DOMAIN_NS=1
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M33.cmake
View File

@ -27,6 +27,5 @@ function(mbed_set_cpu_core_definitions target)
__CORTEX_M33
ARM_MATH_ARMV8MML
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M33F-NS.cmake
View File

@ -26,6 +26,5 @@ function(mbed_set_cpu_core_definitions target)
DOMAIN_NS=1
__FPU_PRESENT=1U
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M33F.cmake
View File

@ -24,6 +24,5 @@ function(mbed_set_cpu_core_definitions target)
ARM_MATH_ARMV8MML
__FPU_PRESENT=1U
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M33FE-NS.cmake
View File

@ -25,7 +25,6 @@ function(mbed_set_cpu_core_definitions target)
DOMAIN_NS=1
__FPU_PRESENT=1U
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
__DSP_PRESENT=1U
)
endfunction()

1
tools/cmake/cores/Cortex-M33FE.cmake
View File

@ -24,7 +24,6 @@ function(mbed_set_cpu_core_definitions target)
ARM_MATH_ARMV8MML
__FPU_PRESENT=1U
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
__DSP_PRESENT=1U
)
endfunction()

1
tools/cmake/cores/Cortex-M4.cmake
View File

@ -25,6 +25,5 @@ function(mbed_set_cpu_core_definitions target)
__CORTEX_M4
ARM_MATH_CM4
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M4F.cmake
View File

@ -24,6 +24,5 @@ function(mbed_set_cpu_core_definitions target)
ARM_MATH_CM4
__FPU_PRESENT=1
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M55.cmake
View File

@ -24,6 +24,5 @@ function(mbed_set_cpu_core_definitions target)
__CORTEX_M55
__FPU_PRESENT=1
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M7.cmake
View File

@ -20,6 +20,5 @@ function(mbed_set_cpu_core_definitions target)
__CORTEX_M7
ARM_MATH_CM7
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M7F.cmake
View File

@ -25,6 +25,5 @@ function(mbed_set_cpu_core_definitions target)
ARM_MATH_CM7
__FPU_PRESENT=1
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

1
tools/cmake/cores/Cortex-M7FD.cmake
View File

@ -24,6 +24,5 @@ function(mbed_set_cpu_core_definitions target)
ARM_MATH_CM7
__FPU_PRESENT=1
__CMSIS_RTOS
__MBED_CMSIS_RTOS_CM
)
endfunction()

11
tools/cmake/mbed_toolchain.cmake
View File

@ -25,6 +25,8 @@ endfunction()
# Set the system processor depending on the CPU core type
if (MBED_CPU_CORE STREQUAL Cortex-A9)
set(CMAKE_SYSTEM_PROCESSOR cortex-a9)
elseif (MBED_CPU_CORE STREQUAL Cortex-A5)
set(CMAKE_SYSTEM_PROCESSOR cortex-a5)
elseif (MBED_CPU_CORE STREQUAL Cortex-M0+)
set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus)
elseif (MBED_CPU_CORE STREQUAL Cortex-M0)
@ -102,7 +104,14 @@ set(c_cxx_compile_options "") # compile options only for C/CXX
set(asm_compile_options "") # compile options only for ASM
include(toolchains/${MBED_TOOLCHAIN})
include(cores/${MBED_CPU_CORE})
set(MBED_CPU_CORE_TAG ${MBED_CPU_CORE})
if (MBED_CPU_CORE MATCHES "Cortex-A[0-9]+$")
set(MBED_CPU_CORE_TAG "Cortex-A")
string(REPLACE "Cortex-" "" MBED_CPU_CORE_CODE "${MBED_CPU_CORE}")
endif()
include(cores/${MBED_CPU_CORE_TAG})
#converts a list into a string with each of its elements seperated by a space
macro(list_to_space_separated OUTPUT_VAR)# 2nd arg: LIST...

1
tools/export/gnuarmeclipse/__init__.py
View File

@ -428,6 +428,7 @@ class GNUARMEclipse(Exporter):
'Cortex-M7': {'mcpu': 'cortex-m7', 'fpu_unit': None},
'Cortex-M7F': {'mcpu': 'cortex-m7', 'fpu_unit': 'fpv4spd16'},
'Cortex-M7FD': {'mcpu': 'cortex-m7', 'fpu_unit': 'fpv5d16'},
'Cortex-A5': {'mcpu': 'cortex-a5', 'fpu_unit': 'vfpv3'},
'Cortex-A9': {'mcpu': 'cortex-a9', 'fpu_unit': 'vfpv3'}
}

1
tools/export/mcuxpresso/__init__.py
View File

@ -353,6 +353,7 @@ class MCUXpresso(GNUARMEclipse):
'Cortex-M7': {'mcpu': 'cortex-m7', 'fpu_unit': None},
'Cortex-M7F': {'mcpu': 'cortex-m7', 'fpu_unit': 'fpv4spd16'},
'Cortex-M7FD': {'mcpu': 'cortex-m7', 'fpu_unit': 'fpv5d16'},
'Cortex-A5': {'mcpu': 'cortex-a5', 'fpu_unit': 'vfpv3'},
'Cortex-A9': {'mcpu': 'cortex-a9', 'fpu_unit': 'vfpv3'}
}

2
tools/targets/__init__.py
View File

@ -49,6 +49,7 @@ CORE_LABELS = {
"Cortex-M7F": ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7", "CORTEX"],
"Cortex-M7FD": ["M7", "CORTEX_M", "RTOS_M4_M7", "LIKE_CORTEX_M7",
"CORTEX"],
"Cortex-A5": ["A5", "CORTEX_A", "LIKE_CORTEX_A5", "CORTEX"],
"Cortex-A9": ["A9", "CORTEX_A", "LIKE_CORTEX_A9", "CORTEX"],
"Cortex-M23": ["M23", "CORTEX_M", "LIKE_CORTEX_M23", "CORTEX"],
"Cortex-M23-NS": ["M23", "M23_NS", "CORTEX_M", "LIKE_CORTEX_M23",
@ -74,6 +75,7 @@ CORE_ARCH = {
"Cortex-M7": 7,
"Cortex-M7F": 7,
"Cortex-M7FD": 7,
"Cortex-A5": 7,
"Cortex-A9": 7,
"Cortex-M23": 8,
"Cortex-M23-NS": 8,

4
tools/toolchains/arm.py
View File

@ -57,7 +57,7 @@ class ARM(mbedToolchain):
SHEBANG = "#! armcc -E"
SUPPORTED_CORES = [
"Cortex-M0", "Cortex-M0+", "Cortex-M3", "Cortex-M4", "Cortex-M4F",
"Cortex-M7", "Cortex-M7F", "Cortex-M7FD", "Cortex-A9"
"Cortex-M7", "Cortex-M7F", "Cortex-M7FD", "Cortex-A5", "Cortex-A9"
]
ARMCC_RANGE = (LooseVersion("5.06"), LooseVersion("5.07"))
ARMCC_PRODUCT_RE = re.compile(b"Product: (.*)")
@ -544,7 +544,7 @@ class ARMC6(ARM_STD):
"Cortex-M4F", "Cortex-M7", "Cortex-M7F", "Cortex-M7FD",
"Cortex-M23", "Cortex-M23-NS", "Cortex-M33", "Cortex-M33F",
"Cortex-M33-NS", "Cortex-M33F-NS", "Cortex-M33FE-NS", "Cortex-M33FE",
"Cortex-A9"
"Cortex-A5", "Cortex-A9"
]
ARMCC_RANGE = (LooseVersion("6.10"), LooseVersion("7.0"))
LD_DIAGNOSTIC_PATTERN = re.compile(

2
tools/toolchains/gcc.py
View File

@ -131,7 +131,7 @@ class GCC(mbedToolchain):
self.cpu.append("-mfpu=fpv5-d16")
self.cpu.append("-mfloat-abi=softfp")
if target.core == "Cortex-A9":
if target.core == "Cortex-A9" or target.core == "Cortex-A5":
self.cpu.append("-mthumb-interwork")
self.cpu.append("-marm")
self.cpu.append("-march=armv7-a")

2
tools/toolchains/mbed_toolchain.py
View File

@ -86,6 +86,8 @@ CORTEX_SYMBOLS = {
"__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
"Cortex-M7FD": ["__CORTEX_M7", "ARM_MATH_CM7", "__FPU_PRESENT=1",
"__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"],
"Cortex-A5": ["__CORTEX_A5", "ARM_MATH_CA5", "__FPU_PRESENT",
"__CMSIS_RTOS", "__EVAL"],
"Cortex-A9": ["__CORTEX_A9", "ARM_MATH_CA9", "__FPU_PRESENT",
"__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA9"],
"Cortex-M23-NS": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "DOMAIN_NS=1",