mirror of https://github.com/ARMmbed/mbed-os.git
Merge branch 'doc_updates' of ssh://github.com/deepikabhavnani/mbed-os into deepikabhavnani-doc_updates
commit
b480a892b0
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@ -84,11 +84,14 @@ public:
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* @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
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* @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
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* @param sclk QSPI Clock pin
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* @param sclk QSPI Clock pin
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* @param ssel QSPI chip select pin
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* @param ssel QSPI chip select pin
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* @param mode Mode specifies the SPI mode(Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
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* @param mode Clock polarity and phase mode (0 - 3) of SPI
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* default value = 0
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* (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
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*
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*
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*/
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*/
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QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
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QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
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virtual ~QSPI()
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{
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}
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/** Configure the data transmission format
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/** Configure the data transmission format
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*
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*
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@ -96,7 +99,7 @@ public:
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* @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
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* @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
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* @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
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* @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
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* @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
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* @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
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* @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
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* @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32)
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* @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
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* @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
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* @param dummy_cycles Number of dummy clock cycles to be used after alt phase
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* @param dummy_cycles Number of dummy clock cycles to be used after alt phase
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*
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*
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@ -179,6 +182,7 @@ public:
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*/
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*/
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qspi_status_t command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
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qspi_status_t command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
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#if !defined(DOXYGEN_ONLY)
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protected:
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protected:
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/** Acquire exclusive access to this SPI bus
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/** Acquire exclusive access to this SPI bus
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*/
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*/
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@ -188,12 +192,6 @@ protected:
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*/
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*/
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virtual void unlock(void);
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virtual void unlock(void);
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public:
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virtual ~QSPI()
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{
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}
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protected:
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qspi_t _qspi;
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qspi_t _qspi;
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bool acquire(void);
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bool acquire(void);
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@ -223,6 +221,7 @@ private:
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* This function builds the qspi command struct to be send to Hal
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* This function builds the qspi command struct to be send to Hal
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*/
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*/
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inline void _build_qspi_command(int instruction, int address, int alt);
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inline void _build_qspi_command(int instruction, int address, int alt);
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#endif
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};
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};
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} // namespace mbed
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} // namespace mbed
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1
mbed.h
1
mbed.h
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@ -73,6 +73,7 @@
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#include "drivers/UARTSerial.h"
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#include "drivers/UARTSerial.h"
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#include "drivers/FlashIAP.h"
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#include "drivers/FlashIAP.h"
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#include "drivers/MbedCRC.h"
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#include "drivers/MbedCRC.h"
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#include "drivers/QSPI.h"
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// mbed Internal components
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// mbed Internal components
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#include "drivers/Timer.h"
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#include "drivers/Timer.h"
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