Merge branch 'master' of https://github.com/mbedmicro/mbed into DEV_DISCOF429ZI

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct

@@ -0,0 +1,29 @@
+;
+SAML21J18A
+;
+256KB FLASH (0x40000) @ 0x000000000
+;
+2KB RAM (0x8000) @ 0x20000000
+
+
+;
+SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+LR_IROM1 0x00000000 0x40000  {    ;
+    load region size_region
+    ER_IROM1 0x00000000 0x40000  {  ;
+                                    load address = execution address
+                                            *.o (RESET, +First)
+                                            *(InRoot$$Sections)
+                                            .ANY (+RO)
+                                 }
+
+    ;
+    [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
+            RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4)
+    {
+        ;
+        RW data
+        .ANY (+RW +ZI)
+    }
+
+}

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_MICRO/startup_SAML21.s

@@ -0,0 +1,194 @@
+;/**************************************************************************//**
+; * @file     startup_SAML21.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File for
+; *           Atmel SAML21 Device Series
+; * @version  V1.00
+; * @date     10. February 2015
+; *
+; * @note
+; * Copyright (C) 2015 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+__initial_sp        EQU     0x20008000  ;Top of RAM
+
+				PRESERVE8
+				THUMB
+
+
+;Vector Table Mapped to Address 0 at Reset
+
+				AREA    RESET, DATA, READONLY
+				EXPORT  __Vectors
+				EXPORT  __Vectors_End
+				EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ;Top of Stack
+				DCD     Reset_Handler             ;Reset Handler
+				DCD     NMI_Handler               ;NMI Handler
+				DCD     HardFault_Handler         ;Hard Fault Handler
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     SVC_Handler               ;SVCall Handler
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     PendSV_Handler            ;PendSV Handler
+				DCD     SysTick_Handler           ;SysTick Handler
+
+				;External Interrupts
+				DCD     SYSTEM_Handler            ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator
+				DCD     WDT_Handler               ;1 Watchdog Timer
+				DCD     RTC_Handler               ;2 Real-Time Counter
+				DCD     EIC_Handler               ;3 External Interrupt Controller
+				DCD     NVMCTRL_Handler           ;4 Non-Volatile Memory Controller
+				DCD     DMAC_Handler              ;5 Direct Memory Access Controller
+				DCD     USB_Handler               ;6 Universal Serial Bus
+				DCD     EVSYS_Handler             ;7 Event System Interface
+				DCD     SERCOM0_Handler           ;8 Serial Communication Interface 0
+				DCD     SERCOM1_Handler           ;9 Serial Communication Interface 1
+				DCD     SERCOM2_Handler           ;10 Serial Communication Interface 2
+				DCD     SERCOM3_Handler           ;11 Serial Communication Interface 3
+				DCD     SERCOM4_Handler           ;12 Serial Communication Interface 4
+				DCD     SERCOM5_Handler           ;13 Serial Communication Interface 5
+				DCD     TCC0_Handler              ;14 Timer Counter Control 0
+				DCD     TCC1_Handler              ;15 Timer Counter Control 1
+				DCD     TCC2_Handler              ;16 Timer Counter Control 2
+				DCD     TC0_Handler               ;17 Basic Timer Counter 0
+				DCD     TC1_Handler               ;18 Basic Timer Counter 1
+				DCD     TC2_Handler               ;19 Basic Timer Counter 2
+				DCD     TC3_Handler               ;20 Basic Timer Counter 3
+				DCD     TC4_Handler               ;21 Basic Timer Counter 4
+				DCD     ADC_Handler               ;22 Analog Digital Converter
+				DCD     AC_Handler                ;23 Analog Comparators
+				DCD     DAC_Handler               ;24 Digital-to-Analog Converter
+				DCD     PTC_Handler               ;25 Peripheral Touch Controller
+				DCD     AES_Handler               ;26 Advanced Encryption Standard
+				DCD     TRNG_Handler              ;27 True Random Generator
+				DCD     PICOP_Handler             ;28 PicoProcessor
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+				AREA    |.text|, CODE, READONLY
+
+
+;Reset Handler
+
+Reset_Handler   PROC
+				EXPORT  Reset_Handler             [WEAK]
+				IMPORT  SystemInit
+				IMPORT  __main
+				LDR     R0, =SystemInit
+				BLX     R0
+				LDR     R0, =__main
+				BX      R0
+				ENDP
+
+
+;Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+				EXPORT  NMI_Handler               [WEAK]
+				B       .
+				ENDP
+HardFault_Handler\
+				PROC
+				EXPORT  HardFault_Handler         [WEAK]
+				B       .
+				ENDP
+SVC_Handler     PROC
+				EXPORT  SVC_Handler               [WEAK]
+				B       .
+				ENDP
+PendSV_Handler  PROC
+				EXPORT  PendSV_Handler            [WEAK]
+				B       .
+				ENDP
+SysTick_Handler PROC
+				EXPORT  SysTick_Handler           [WEAK]
+				B       .
+				ENDP
+
+Default_Handler PROC
+				EXPORT  SYSTEM_Handler            [WEAK]
+				EXPORT  WDT_Handler               [WEAK]
+				EXPORT  RTC_Handler               [WEAK]
+				EXPORT  EIC_Handler               [WEAK]
+				EXPORT  NVMCTRL_Handler           [WEAK]
+				EXPORT  DMAC_Handler              [WEAK]
+				EXPORT  USB_Handler               [WEAK]
+				EXPORT  EVSYS_Handler             [WEAK]
+				EXPORT  SERCOM0_Handler           [WEAK]
+				EXPORT  SERCOM1_Handler           [WEAK]
+				EXPORT  SERCOM2_Handler           [WEAK]
+				EXPORT  SERCOM3_Handler           [WEAK]
+				EXPORT  SERCOM4_Handler           [WEAK]
+				EXPORT  SERCOM5_Handler           [WEAK]
+				EXPORT  TCC0_Handler              [WEAK]
+				EXPORT  TCC1_Handler              [WEAK]
+				EXPORT  TCC2_Handler              [WEAK]
+				EXPORT  TC0_Handler               [WEAK]
+				EXPORT  TC1_Handler               [WEAK]
+				EXPORT  TC2_Handler               [WEAK]
+				EXPORT  TC3_Handler               [WEAK]
+				EXPORT  TC4_Handler               [WEAK]
+				EXPORT  ADC_Handler               [WEAK]
+				EXPORT  AC_Handler                [WEAK]
+				EXPORT  DAC_Handler               [WEAK]
+				EXPORT  PTC_Handler               [WEAK]
+				EXPORT  AES_Handler               [WEAK]
+				EXPORT  TRNG_Handler              [WEAK]
+				EXPORT  PICOP_Handler             [WEAK]
+
+SYSTEM_Handler
+WDT_Handler
+RTC_Handler
+EIC_Handler
+NVMCTRL_Handler
+DMAC_Handler
+USB_Handler
+EVSYS_Handler
+SERCOM0_Handler
+SERCOM1_Handler
+SERCOM2_Handler
+SERCOM3_Handler
+SERCOM4_Handler
+SERCOM5_Handler
+TCC0_Handler
+TCC1_Handler
+TCC2_Handler
+TC0_Handler
+TC1_Handler
+TC2_Handler
+TC3_Handler
+TC4_Handler
+ADC_Handler
+AC_Handler
+DAC_Handler
+PTC_Handler
+AES_Handler
+TRNG_Handler
+PICOP_Handler
+				B       .
+				ENDP
+
+
+
+				ALIGN
+				END

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/SAML21J18A.sct

@@ -0,0 +1,29 @@
+;
+SAML21J18A
+;
+256KB FLASH (0x40000) @ 0x000000000
+;
+2KB RAM (0x8000) @ 0x20000000
+
+
+;
+SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
+LR_IROM1 0x00000000 0x40000  {    ;
+    load region size_region
+    ER_IROM1 0x00000000 0x40000  {  ;
+                                    load address = execution address
+                                            *.o (RESET, +First)
+                                            *(InRoot$$Sections)
+                                            .ANY (+RO)
+                                 }
+
+    ;
+    [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4) - alignment
+            RW_IRAM1 (0x20000000+0xB4) (0x8000-0xB4)
+    {
+        ;
+        RW data
+        .ANY (+RW +ZI)
+    }
+
+}

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_ARM_STD/startup_SAML21.s

@@ -0,0 +1,194 @@
+;/**************************************************************************//**
+; * @file     startup_SAML21.s
+; * @brief    CMSIS Cortex-M4 Core Device Startup File for
+; *           Atmel SAML21 Device Series
+; * @version  V1.00
+; * @date     10. February 2015
+; *
+; * @note
+; * Copyright (C) 2015 ARM Limited. All rights reserved.
+; *
+; * @par
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M
+; * processor based microcontrollers.  This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * @par
+; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; ******************************************************************************/
+__initial_sp        EQU     0x20008000  ;Top of RAM
+
+				PRESERVE8
+				THUMB
+
+
+;Vector Table Mapped to Address 0 at Reset
+
+				AREA    RESET, DATA, READONLY
+				EXPORT  __Vectors
+				EXPORT  __Vectors_End
+				EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ;Top of Stack
+				DCD     Reset_Handler             ;Reset Handler
+				DCD     NMI_Handler               ;NMI Handler
+				DCD     HardFault_Handler         ;Hard Fault Handler
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     SVC_Handler               ;SVCall Handler
+				DCD     0                         ;Reserved
+				DCD     0                         ;Reserved
+				DCD     PendSV_Handler            ;PendSV Handler
+				DCD     SysTick_Handler           ;SysTick Handler
+
+				;External Interrupts
+				DCD     SYSTEM_Handler            ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator
+				DCD     WDT_Handler               ;1 Watchdog Timer
+				DCD     RTC_Handler               ;2 Real-Time Counter
+				DCD     EIC_Handler               ;3 External Interrupt Controller
+				DCD     NVMCTRL_Handler           ;4 Non-Volatile Memory Controller
+				DCD     DMAC_Handler              ;5 Direct Memory Access Controller
+				DCD     USB_Handler               ;6 Universal Serial Bus
+				DCD     EVSYS_Handler             ;7 Event System Interface
+				DCD     SERCOM0_Handler           ;8 Serial Communication Interface 0
+				DCD     SERCOM1_Handler           ;9 Serial Communication Interface 1
+				DCD     SERCOM2_Handler           ;10 Serial Communication Interface 2
+				DCD     SERCOM3_Handler           ;11 Serial Communication Interface 3
+				DCD     SERCOM4_Handler           ;12 Serial Communication Interface 4
+				DCD     SERCOM5_Handler           ;13 Serial Communication Interface 5
+				DCD     TCC0_Handler              ;14 Timer Counter Control 0
+				DCD     TCC1_Handler              ;15 Timer Counter Control 1
+				DCD     TCC2_Handler              ;16 Timer Counter Control 2
+				DCD     TC0_Handler               ;17 Basic Timer Counter 0
+				DCD     TC1_Handler               ;18 Basic Timer Counter 1
+				DCD     TC2_Handler               ;19 Basic Timer Counter 2
+				DCD     TC3_Handler               ;20 Basic Timer Counter 3
+				DCD     TC4_Handler               ;21 Basic Timer Counter 4
+				DCD     ADC_Handler               ;22 Analog Digital Converter
+				DCD     AC_Handler                ;23 Analog Comparators
+				DCD     DAC_Handler               ;24 Digital-to-Analog Converter
+				DCD     PTC_Handler               ;25 Peripheral Touch Controller
+				DCD     AES_Handler               ;26 Advanced Encryption Standard
+				DCD     TRNG_Handler              ;27 True Random Generator
+				DCD     PICOP_Handler             ;28 PicoProcessor
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+				AREA    |.text|, CODE, READONLY
+
+
+;Reset Handler
+
+Reset_Handler   PROC
+				EXPORT  Reset_Handler             [WEAK]
+				IMPORT  SystemInit
+				IMPORT  __main
+				LDR     R0, =SystemInit
+				BLX     R0
+				LDR     R0, =__main
+				BX      R0
+				ENDP
+
+
+;Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+				EXPORT  NMI_Handler               [WEAK]
+				B       .
+				ENDP
+HardFault_Handler\
+				PROC
+				EXPORT  HardFault_Handler         [WEAK]
+				B       .
+				ENDP
+SVC_Handler     PROC
+				EXPORT  SVC_Handler               [WEAK]
+				B       .
+				ENDP
+PendSV_Handler  PROC
+				EXPORT  PendSV_Handler            [WEAK]
+				B       .
+				ENDP
+SysTick_Handler PROC
+				EXPORT  SysTick_Handler           [WEAK]
+				B       .
+				ENDP
+
+Default_Handler PROC
+				EXPORT  SYSTEM_Handler            [WEAK]
+				EXPORT  WDT_Handler               [WEAK]
+				EXPORT  RTC_Handler               [WEAK]
+				EXPORT  EIC_Handler               [WEAK]
+				EXPORT  NVMCTRL_Handler           [WEAK]
+				EXPORT  DMAC_Handler              [WEAK]
+				EXPORT  USB_Handler               [WEAK]
+				EXPORT  EVSYS_Handler             [WEAK]
+				EXPORT  SERCOM0_Handler           [WEAK]
+				EXPORT  SERCOM1_Handler           [WEAK]
+				EXPORT  SERCOM2_Handler           [WEAK]
+				EXPORT  SERCOM3_Handler           [WEAK]
+				EXPORT  SERCOM4_Handler           [WEAK]
+				EXPORT  SERCOM5_Handler           [WEAK]
+				EXPORT  TCC0_Handler              [WEAK]
+				EXPORT  TCC1_Handler              [WEAK]
+				EXPORT  TCC2_Handler              [WEAK]
+				EXPORT  TC0_Handler               [WEAK]
+				EXPORT  TC1_Handler               [WEAK]
+				EXPORT  TC2_Handler               [WEAK]
+				EXPORT  TC3_Handler               [WEAK]
+				EXPORT  TC4_Handler               [WEAK]
+				EXPORT  ADC_Handler               [WEAK]
+				EXPORT  AC_Handler                [WEAK]
+				EXPORT  DAC_Handler               [WEAK]
+				EXPORT  PTC_Handler               [WEAK]
+				EXPORT  AES_Handler               [WEAK]
+				EXPORT  TRNG_Handler              [WEAK]
+				EXPORT  PICOP_Handler             [WEAK]
+
+SYSTEM_Handler
+WDT_Handler
+RTC_Handler
+EIC_Handler
+NVMCTRL_Handler
+DMAC_Handler
+USB_Handler
+EVSYS_Handler
+SERCOM0_Handler
+SERCOM1_Handler
+SERCOM2_Handler
+SERCOM3_Handler
+SERCOM4_Handler
+SERCOM5_Handler
+TCC0_Handler
+TCC1_Handler
+TCC2_Handler
+TC0_Handler
+TC1_Handler
+TC2_Handler
+TC3_Handler
+TC4_Handler
+ADC_Handler
+AC_Handler
+DAC_Handler
+PTC_Handler
+AES_Handler
+TRNG_Handler
+PICOP_Handler
+				B       .
+				ENDP
+
+
+
+				ALIGN
+				END

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_GCC_ARM/saml21j18a.ld

@@ -0,0 +1,118 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+SEARCH_DIR(.)
+
+/* Memory Spaces Definitions */
+MEMORY {
+    rom (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00040000
+        ram (rwx) : ORIGIN = 0x20000000 + 0xB4, LENGTH = 0x00008000 - 0xB4
+    }
+
+    /* The stack size used by the application. NOTE: you need to adjust according to your application. */
+    STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
+
+    /* Section Definitions */
+    SECTIONS {
+.text :
+    {
+        . = ALIGN(4);
+        _sfixed = .;
+        KEEP(*(.vectors .vectors.*))
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.glue_7t) *(.glue_7)
+        *(.rodata .rodata* .gnu.linkonce.r.*)
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+
+        /* Support C constructors, and C destructors in both user code
+           and the C library. This also provides support for C++ code. */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+
+        . = ALIGN(4);
+        _efixed = .;            /* End of text section */
+    } > rom
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    PROVIDE_HIDDEN (__exidx_start = .);
+.ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > rom
+    PROVIDE_HIDDEN (__exidx_end = .);
+
+    . = ALIGN(4);
+    _etext = .;
+
+.relocate :
+    AT (_etext)
+    {
+        . = ALIGN(4);
+        _srelocate = .;
+        *(.ramfunc .ramfunc.*);
+        *(.data .data.*);
+        . = ALIGN(4);
+        _erelocate = .;
+    } > ram
+
+    /* .bss section which is used for uninitialized data */
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        _sbss = . ;
+        _szero = .;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+        _ezero = .;
+    } > ram
+
+    .heap (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __end__ = . ;
+        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+    } > ram
+
+    /* stack section */
+    .stack (NOLOAD):
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + STACK_SIZE;
+        . = ALIGN(8);
+        _estack = .;
+    } > ram
+
+    . = ALIGN(4);
+}

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_GCC_ARM/startup_saml21.c

@@ -0,0 +1,281 @@
+/**
+ * \file
+ *
+ * \brief gcc starttup file for SAML21
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "saml21.h"
+
+/* Initialize segments */
+extern uint32_t _sfixed;
+extern uint32_t _efixed;
+extern uint32_t _etext;
+extern uint32_t _srelocate;
+extern uint32_t _erelocate;
+extern uint32_t _szero;
+extern uint32_t _ezero;
+extern uint32_t _sstack;
+extern uint32_t _estack;
+
+/** \cond DOXYGEN_SHOULD_SKIP_THIS */
+int main(void);
+/** \endcond */
+
+void __libc_init_array(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+void NMI_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void HardFault_Handler       ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SVC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void PendSV_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SysTick_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+
+/* Peripherals handlers */
+void SYSTEM_Handler          ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */
+void WDT_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void RTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void EIC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void NVMCTRL_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void DMAC_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_USB
+void USB_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void EVSYS_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM0_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM1_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM2_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void SERCOM3_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_SERCOM4
+void SERCOM4_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_SERCOM5
+void SERCOM5_Handler         ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TCC0_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC1_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TCC2_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC0_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+void TC1_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_TC2
+void TC2_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TC3
+void TC3_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+void TC4_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#ifdef ID_ADC
+void ADC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AC
+void AC_Handler              ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_DAC
+void DAC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PTC
+void PTC_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_AES
+void AES_Handler             ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_TRNG
+void TRNG_Handler            ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+#ifdef ID_PICOP
+void PICOP_Handler           ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
+#endif
+
+/* Exception Table */
+__attribute__ ((section(".vectors")))
+const DeviceVectors exception_table = {
+
+    /* Configure Initial Stack Pointer, using linker-generated symbols */
+    (void*) (&_estack),
+
+    (void*) Reset_Handler,
+    (void*) NMI_Handler,
+    (void*) HardFault_Handler,
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) SVC_Handler,
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) PendSV_Handler,
+    (void*) SysTick_Handler,
+
+    /* Configurable interrupts */
+    (void*) SYSTEM_Handler,         /*  0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
+    (void*) WDT_Handler,            /*  1 Watchdog Timer */
+    (void*) RTC_Handler,            /*  2 Real-Time Counter */
+    (void*) EIC_Handler,            /*  3 External Interrupt Controller */
+    (void*) NVMCTRL_Handler,        /*  4 Non-Volatile Memory Controller */
+    (void*) DMAC_Handler,           /*  5 Direct Memory Access Controller */
+#ifdef ID_USB
+    (void*) USB_Handler,            /*  6 Universal Serial Bus */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+    (void*) EVSYS_Handler,          /*  7 Event System Interface */
+    (void*) SERCOM0_Handler,        /*  8 Serial Communication Interface 0 */
+    (void*) SERCOM1_Handler,        /*  9 Serial Communication Interface 1 */
+    (void*) SERCOM2_Handler,        /* 10 Serial Communication Interface 2 */
+    (void*) SERCOM3_Handler,        /* 11 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+    (void*) SERCOM4_Handler,        /* 12 Serial Communication Interface 4 */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_SERCOM5
+    (void*) SERCOM5_Handler,        /* 13 Serial Communication Interface 5 */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+    (void*) TCC0_Handler,           /* 14 Timer Counter Control 0 */
+    (void*) TCC1_Handler,           /* 15 Timer Counter Control 1 */
+    (void*) TCC2_Handler,           /* 16 Timer Counter Control 2 */
+    (void*) TC0_Handler,            /* 17 Basic Timer Counter 0 */
+    (void*) TC1_Handler,            /* 18 Basic Timer Counter 1 */
+#ifdef ID_TC2
+    (void*) TC2_Handler,            /* 19 Basic Timer Counter 2 */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_TC3
+    (void*) TC3_Handler,            /* 20 Basic Timer Counter 3 */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+    (void*) TC4_Handler,            /* 21 Basic Timer Counter 4 */
+#ifdef ID_ADC
+    (void*) ADC_Handler,            /* 22 Analog Digital Converter */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_AC
+    (void*) AC_Handler,             /* 23 Analog Comparators */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_DAC
+    (void*) DAC_Handler,            /* 24 Digital-to-Analog Converter */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_PTC
+    (void*) PTC_Handler,            /* 25 Peripheral Touch Controller */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_AES
+    (void*) AES_Handler,            /* 26 Advanced Encryption Standard */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_TRNG
+    (void*) TRNG_Handler,           /* 27 True Random Generator */
+#else
+    (void*) (0UL), /* Reserved */
+#endif
+#ifdef ID_PICOP
+    (void*) PICOP_Handler           /* 28 PicoProcessor */
+#else
+    (void*) (0UL)  /* Reserved */
+#endif
+};
+
+/**
+ * \brief This is the code that gets called on processor reset.
+ * To initialize the device, and call the main() routine.
+ */
+void Reset_Handler(void)
+{
+    uint32_t *pSrc, *pDest;
+
+    /* Initialize the relocate segment */
+    pSrc = &_etext;
+    pDest = &_srelocate;
+
+    if (pSrc != pDest) {
+        for (; pDest < &_erelocate;) {
+            *pDest++ = *pSrc++;
+        }
+    }
+
+    /* Clear the zero segment */
+    for (pDest = &_szero; pDest < &_ezero;) {
+        *pDest++ = 0;
+    }
+
+    /* Set the vector table base address */
+    pSrc = (uint32_t *) & _sfixed;
+    SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+    /* Initialize the C library */
+    __libc_init_array();
+
+    /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+    NVMCTRL->CTRLB.bit.MANW = 1;
+
+    /* Branch to main function */
+    main();
+
+    /* Infinite loop */
+    while (1);
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+    while (1) {
+    }
+}

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/TARGET_SAML21J18A/TOOLCHAIN_IAR/startup_saml21.c

@@ -0,0 +1,261 @@
+/**
+ * \file
+ *
+ * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * 3. The name of Atmel may not be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * 4. This software may only be redistributed and used in connection with an
+ *    Atmel microcontroller product.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \asf_license_stop
+ *
+ */
+/*
+ * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
+ */
+
+#include "saml21.h"
+
+typedef void (*intfunc) (void);
+typedef union {
+    intfunc __fun;
+    void * __ptr;
+} intvec_elem;
+
+void __iar_program_start(void);
+int __low_level_init(void);
+
+/* Default empty handler */
+void Dummy_Handler(void);
+
+/* Cortex-M0+ core handlers */
+#pragma weak NMI_Handler              = Dummy_Handler
+#pragma weak HardFault_Handler        = Dummy_Handler
+#pragma weak SVC_Handler              = Dummy_Handler
+#pragma weak PendSV_Handler           = Dummy_Handler
+#pragma weak SysTick_Handler          = Dummy_Handler
+
+/* Peripherals handlers */
+#pragma weak SYSTEM_Handler           = Dummy_Handler /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */
+#pragma weak WDT_Handler              = Dummy_Handler
+#pragma weak RTC_Handler              = Dummy_Handler
+#pragma weak EIC_Handler              = Dummy_Handler
+#pragma weak NVMCTRL_Handler          = Dummy_Handler
+#pragma weak DMAC_Handler             = Dummy_Handler
+#ifdef       ID_USB
+#pragma weak USB_Handler              = Dummy_Handler
+#endif
+#pragma weak EVSYS_Handler            = Dummy_Handler
+#pragma weak SERCOM0_Handler          = Dummy_Handler
+#pragma weak SERCOM1_Handler          = Dummy_Handler
+#pragma weak SERCOM2_Handler          = Dummy_Handler
+#pragma weak SERCOM3_Handler          = Dummy_Handler
+#ifdef       ID_SERCOM4
+#pragma weak SERCOM4_Handler          = Dummy_Handler
+#endif
+#ifdef       ID_SERCOM5
+#pragma weak SERCOM5_Handler          = Dummy_Handler
+#endif
+#pragma weak TCC0_Handler             = Dummy_Handler
+#pragma weak TCC1_Handler             = Dummy_Handler
+#pragma weak TCC2_Handler             = Dummy_Handler
+#pragma weak TC0_Handler              = Dummy_Handler
+#pragma weak TC1_Handler              = Dummy_Handler
+#ifdef       ID_TC2
+#pragma weak TC2_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_TC3
+#pragma weak TC3_Handler              = Dummy_Handler
+#endif
+#pragma weak TC4_Handler              = Dummy_Handler
+#ifdef       ID_ADC
+#pragma weak ADC_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_AC
+#pragma weak AC_Handler               = Dummy_Handler
+#endif
+#ifdef       ID_DAC
+#pragma weak DAC_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_PTC
+#pragma weak PTC_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_AES
+#pragma weak AES_Handler              = Dummy_Handler
+#endif
+#ifdef       ID_TRNG
+#pragma weak TRNG_Handler             = Dummy_Handler
+#endif
+#ifdef       ID_PICOP
+#pragma weak PICOP_Handler            = Dummy_Handler
+#endif
+
+/* Exception Table */
+#pragma language = extended
+#pragma segment  = "CSTACK"
+
+/* The name "__vector_table" has special meaning for C-SPY: */
+/* it is where the SP start value is found, and the NVIC vector */
+/* table register (VTOR) is initialized to this address if != 0 */
+
+#pragma section  = ".intvec"
+#pragma location = ".intvec"
+const DeviceVectors __vector_table[] = {
+    __sfe("CSTACK"),
+    (void*) __iar_program_start,
+    (void*) NMI_Handler,
+    (void*) HardFault_Handler,
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) SVC_Handler,
+    (void*) (0UL), /* Reserved */
+    (void*) (0UL), /* Reserved */
+    (void*) PendSV_Handler,
+    (void*) SysTick_Handler,
+
+    /* Configurable interrupts */
+    (void*) SYSTEM_Handler,         /*  0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
+    (void*) WDT_Handler,            /*  1 Watchdog Timer */
+    (void*) RTC_Handler,            /*  2 Real-Time Counter */
+    (void*) EIC_Handler,            /*  3 External Interrupt Controller */
+    (void*) NVMCTRL_Handler,        /*  4 Non-Volatile Memory Controller */
+    (void*) DMAC_Handler,           /*  5 Direct Memory Access Controller */
+#ifdef ID_USB
+    (void*) USB_Handler,            /*  6 Universal Serial Bus */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+    (void*) EVSYS_Handler,          /*  7 Event System Interface */
+    (void*) SERCOM0_Handler,        /*  8 Serial Communication Interface 0 */
+    (void*) SERCOM1_Handler,        /*  9 Serial Communication Interface 1 */
+    (void*) SERCOM2_Handler,        /* 10 Serial Communication Interface 2 */
+    (void*) SERCOM3_Handler,        /* 11 Serial Communication Interface 3 */
+#ifdef ID_SERCOM4
+    (void*) SERCOM4_Handler,        /* 12 Serial Communication Interface 4 */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_SERCOM5
+    (void*) SERCOM5_Handler,        /* 13 Serial Communication Interface 5 */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+    (void*) TCC0_Handler,           /* 14 Timer Counter Control 0 */
+    (void*) TCC1_Handler,           /* 15 Timer Counter Control 1 */
+    (void*) TCC2_Handler,           /* 16 Timer Counter Control 2 */
+    (void*) TC0_Handler,            /* 17 Basic Timer Counter 0 */
+    (void*) TC1_Handler,            /* 18 Basic Timer Counter 1 */
+#ifdef ID_TC2
+    (void*) TC2_Handler,            /* 19 Basic Timer Counter 2 */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_TC3
+    (void*) TC3_Handler,            /* 20 Basic Timer Counter 3 */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+    (void*) TC4_Handler,            /* 21 Basic Timer Counter 4 */
+#ifdef ID_ADC
+    (void*) ADC_Handler,            /* 22 Analog Digital Converter */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_AC
+    (void*) AC_Handler,             /* 23 Analog Comparators */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_DAC
+    (void*) DAC_Handler,            /* 24 Digital-to-Analog Converter */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_PTC
+    (void*) PTC_Handler,            /* 25 Peripheral Touch Controller */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_AES
+    (void*) AES_Handler,            /* 26 Advanced Encryption Standard */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_TRNG
+    (void*) TRNG_Handler,           /* 27 True Random Generator */
+#else
+    (void*) (0UL), /* Reserved*/
+#endif
+#ifdef ID_PICOP
+    (void*) PICOP_Handler           /* 28 PicoProcessor */
+#else
+    (void*) (0UL)  /* Reserved*/
+#endif
+};
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+int __low_level_init(void)
+{
+    uint32_t *pSrc = __section_begin(".intvec");
+
+    SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
+
+    return 1; /* if return 0, the data sections will not be initialized */
+}
+
+/**------------------------------------------------------------------------------
+ * This is the code that gets called on processor reset. To initialize the
+ * device.
+ *------------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+    /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
+    NVMCTRL->CTRLB.bit.MANW = 1;
+
+    __iar_program_start();
+}
+
+/**
+ * \brief Default interrupt handler for unused IRQs.
+ */
+void Dummy_Handler(void)
+{
+    while (1) {
+    }
+}

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis.h

@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in samr21j18a specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "saml21.h"
+#include "cmsis_nvic.h"
+
+#endif

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/cmsis_nvic.h

@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS      (16 +29)   // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_MICRO/sys.cpp

@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/sys.cpp

@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
+{
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif

libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/cmsis_nvic.c

@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x20000000)  // Vectors positioned at start of RAM
+//extern uint32_t _sdvectors;
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + 16];
+}