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Merge pull request #12464 from jeromecoutant/PR_ETHERNET 

STM32 EMAC : add configuration choice and connection check
pull/12619/head
Martin Kojtal 2020-03-03 16:04:18 +00:00 committed by GitHub
parent 32e8b2f7d4 b15dffaef2
commit b3583f04cf
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
10 changed files with 201 additions and 186 deletions
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2
features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F2/stm32xx_emac_config.h
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@ -19,6 +19,4 @@
#define ETH_IP_VERSION_V1 #define ETH_IP_VERSION_V1
#define THREAD_STACKSIZE 512
#endif // #define STM32XX_EMAC_CONFIG_H__ #endif // #define STM32XX_EMAC_CONFIG_H__

2
features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F4/stm32xx_emac_config.h
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@ -19,6 +19,4 @@
#define ETH_IP_VERSION_V1 #define ETH_IP_VERSION_V1
#define THREAD_STACKSIZE 512
#endif // #define STM32XX_EMAC_CONFIG_H__ #endif // #define STM32XX_EMAC_CONFIG_H__

2
features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32F7/stm32xx_emac_config.h
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@ -19,6 +19,4 @@
#define ETH_IP_VERSION_V1 #define ETH_IP_VERSION_V1
#define THREAD_STACKSIZE 512
#endif // #define STM32XX_EMAC_CONFIG_H__ #endif // #define STM32XX_EMAC_CONFIG_H__

2
features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32H7/stm32xx_emac_config.h
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@ -19,6 +19,4 @@
#define ETH_IP_VERSION_V2 #define ETH_IP_VERSION_V2
#define THREAD_STACKSIZE 512
#endif // #define STM32XX_EMAC_CONFIG_H__ #endif // #define STM32XX_EMAC_CONFIG_H__

36
features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json
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@ -3,9 +3,41 @@
"config": { "config": {
"eth-rxbufnb": 4, "eth-rxbufnb": 4,
"eth-txbufnb": 4, "eth-txbufnb": 4,
"eth-phyaddr": { "thread-stacksize": {
"help": "Stack size for stm32_emac_thread",
"value": 512
},
"eth-phy-address": {
"help" : "Configures actual PHY address according to pullup/down status of PHYAD pin(s)", "help" : "Configures actual PHY address according to pullup/down status of PHYAD pin(s)",
"value" : 0 "value" : 0
},
"eth-phy-AutoNegotiation": {
"help" : "Selects AutoNegotiation mode : ETH_AUTONEGOTIATION_ENABLE / ETH_AUTONEGOTIATION_DISABLE",
"value" : "ETH_AUTONEGOTIATION_ENABLE"
},
"eth-phy-DuplexMode": {
"help" : "Selects DuplexMode mode : ETH_MODE_FULLDUPLEX / ETH_MODE_HALFDUPLEX",
"value" : "ETH_MODE_FULLDUPLEX"
},
"eth-phy-Speed": {
"help" : "Selects Speed mode : ETH_SPEED_100M / ETH_SPEED_10M",
"value" : "ETH_SPEED_100M"
},
"eth-phy-reset-delay": {
"help" : "Reset process time - Default value: 0.5s as specified in LAN8742A datasheet",
"value" : "500"
},
"eth-phy-status-register": {
"help" : "PHY register Offset with auto-negotiation result - Default value is LAN8742A PHY Special Control/Status Register",
"value" : "31"
},
"eth-phy-speed-status": {
"help" : "Speed mask information in eth-phy-status-register",
"value" : "0x0004"
},
"eth-phy-duplex-status": {
"help" : "Duplex mask information in eth-phy-status-register",
"value" : "0x0010"
} }
}, },
"target_overrides": { "target_overrides": {
@ -14,7 +46,7 @@
"eth-txbufnb": 4 "eth-txbufnb": 4
}, },
"ARCH_MAX": { "ARCH_MAX": {
"eth-phyaddr": 1 "eth-phy-address": 1
} }
} }
} }

100
features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp Executable file → Normal file
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@ -30,6 +30,22 @@
#include "stm32xx_emac_config.h" #include "stm32xx_emac_config.h"
#include "stm32xx_emac.h" #include "stm32xx_emac.h"
#include "mbed-trace/mbed_trace.h"
#if defined(ETH_IP_VERSION_V2)
#define TRACE_GROUP "STE2"
#else
#define TRACE_GROUP "STE1"
#endif
/* mbed trace feature is supported */
/* ex in mbed_app.json */
/* "mbed-trace.enable": "1" */
/* mbed_trace: debug traces (tr_debug) can be disabled here with no change in mbed_app.json */
// #undef TRACE_LEVEL_DEBUG
// #define TRACE_LEVEL_DEBUG 0
#if defined(ETH_IP_VERSION_V2) #if defined(ETH_IP_VERSION_V2)
#include "lan8742/lan8742.h" #include "lan8742/lan8742.h"
#include "lwip/memp.h" #include "lwip/memp.h"
@ -43,7 +59,6 @@
#define THREAD_PRIORITY (osPriorityHigh) #define THREAD_PRIORITY (osPriorityHigh)
#define PHY_TASK_PERIOD_MS 200 #define PHY_TASK_PERIOD_MS 200
#define ETH_PHY_ADDRESS MBED_CONF_STM32_EMAC_ETH_PHYADDR
#define STM_HWADDR_SIZE (6) #define STM_HWADDR_SIZE (6)
#define STM_ETH_MTU_SIZE 1500 #define STM_ETH_MTU_SIZE 1500
@ -276,13 +291,15 @@ static osThreadId_t create_new_thread(const char *threadName, void (*thread)(voi
bool STM32_EMAC::low_level_init_successful() bool STM32_EMAC::low_level_init_successful()
#ifndef ETH_IP_VERSION_V2 #ifndef ETH_IP_VERSION_V2
{ {
uint32_t PHY_ID;
/* Init ETH */ /* Init ETH */
uint8_t MACAddr[6]; uint8_t MACAddr[6];
EthHandle.Instance = ETH; EthHandle.Instance = ETH;
EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE; EthHandle.Init.AutoNegotiation = MBED_CONF_STM32_EMAC_ETH_PHY_AUTONEGOTIATION;
EthHandle.Init.Speed = ETH_SPEED_100M; EthHandle.Init.Speed = MBED_CONF_STM32_EMAC_ETH_PHY_SPEED;
EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX; EthHandle.Init.DuplexMode = MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEXMODE;
EthHandle.Init.PhyAddress = ETH_PHY_ADDRESS; EthHandle.Init.PhyAddress = MBED_CONF_STM32_EMAC_ETH_PHY_ADDRESS;
#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE) #if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
MACAddr[0] = MBED_MAC_ADDR_0; MACAddr[0] = MBED_MAC_ADDR_0;
MACAddr[1] = MBED_MAC_ADDR_1; MACAddr[1] = MBED_MAC_ADDR_1;
@ -297,20 +314,48 @@ bool STM32_EMAC::low_level_init_successful()
EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE; EthHandle.Init.RxMode = ETH_RXINTERRUPT_MODE;
EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE; EthHandle.Init.ChecksumMode = ETH_CHECKSUM_BY_SOFTWARE;
EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII; EthHandle.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
HAL_ETH_Init(&EthHandle); tr_info("PHY Addr %u AutoNegotiation %u", EthHandle.Init.PhyAddress, EthHandle.Init.AutoNegotiation);
tr_debug("MAC Addr %02x:%02x:%02x:%02x:%02x:%02x", MACAddr[0], MACAddr[1], MACAddr[2], MACAddr[3], MACAddr[4], MACAddr[5]);
tr_info("ETH buffers : %u Rx %u Tx", ETH_RXBUFNB, ETH_TXBUFNB);
if (HAL_ETH_Init(&EthHandle) != HAL_OK) {
tr_error("HAL_ETH_Init issue");
return false;
}
uint32_t TempRegisterValue;
if (HAL_ETH_ReadPHYRegister(&EthHandle, 2, &TempRegisterValue) != HAL_OK) {
tr_error("HAL_ETH_ReadPHYRegister 2 issue");
}
PHY_ID = (TempRegisterValue << 16);
if (HAL_ETH_ReadPHYRegister(&EthHandle, 3, &TempRegisterValue) != HAL_OK) {
tr_error("HAL_ETH_ReadPHYRegister 3 issue");
}
PHY_ID |= (TempRegisterValue & 0XFFF0);
tr_info("PHY ID %#X", PHY_ID);
/* Initialize Tx Descriptors list: Chain Mode */ /* Initialize Tx Descriptors list: Chain Mode */
HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); if (HAL_ETH_DMATxDescListInit(&EthHandle, DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB) != HAL_OK) {
tr_error("HAL_ETH_DMATxDescListInit issue");
return false;
}
/* Initialize Rx Descriptors list: Chain Mode */ /* Initialize Rx Descriptors list: Chain Mode */
HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); if (HAL_ETH_DMARxDescListInit(&EthHandle, DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB) != HAL_OK) {
tr_error("HAL_ETH_DMARxDescListInit issue");
return false;
}
/* Configure MAC */ /* Configure MAC */
_eth_config_mac(&EthHandle); _eth_config_mac(&EthHandle);
/* Enable MAC and DMA transmission and reception */ /* Enable MAC and DMA transmission and reception */
HAL_ETH_Start(&EthHandle); if (HAL_ETH_Start(&EthHandle) != HAL_OK) {
tr_error("HAL_ETH_Start issue");
return false;
}
tr_info("low_level_init_successful");
return true; return true;
} }
#else // ETH_IP_VERSION_V2 #else // ETH_IP_VERSION_V2
@ -338,6 +383,9 @@ bool STM32_EMAC::low_level_init_successful()
EthHandle.Init.TxDesc = DMATxDscrTab; EthHandle.Init.TxDesc = DMATxDscrTab;
EthHandle.Init.RxBuffLen = 1524; EthHandle.Init.RxBuffLen = 1524;
tr_debug("MAC Addr %02x:%02x:%02x:%02x:%02x:%02x", MACAddr[0], MACAddr[1], MACAddr[2], MACAddr[3], MACAddr[4], MACAddr[5]);
tr_info("ETH buffers : %u Rx %u Tx", ETH_RX_DESC_CNT, ETH_TX_DESC_CNT);
if (HAL_ETH_Init(&EthHandle) != HAL_OK) { if (HAL_ETH_Init(&EthHandle) != HAL_OK) {
return false; return false;
} }
@ -351,6 +399,7 @@ bool STM32_EMAC::low_level_init_successful()
HAL_ETH_DescAssignMemory(&EthHandle, idx, Rx_Buff[idx], NULL); HAL_ETH_DescAssignMemory(&EthHandle, idx, Rx_Buff[idx], NULL);
} }
tr_info("low_level_init_successful");
return _phy_init(); return _phy_init();
} }
#endif // ETH_IP_VERSION_V2 #endif // ETH_IP_VERSION_V2
@ -371,7 +420,7 @@ bool STM32_EMAC::low_level_init_successful()
bool STM32_EMAC::link_out(emac_mem_buf_t *buf) bool STM32_EMAC::link_out(emac_mem_buf_t *buf)
#ifndef ETH_IP_VERSION_V2 #ifndef ETH_IP_VERSION_V2
{ {
bool success; bool success = true;
emac_mem_buf_t *q; emac_mem_buf_t *q;
uint8_t *buffer = reinterpret_cast<uint8_t *>(EthHandle.TxDesc->Buffer1Addr); uint8_t *buffer = reinterpret_cast<uint8_t *>(EthHandle.TxDesc->Buffer1Addr);
__IO ETH_DMADescTypeDef *DmaTxDesc; __IO ETH_DMADescTypeDef *DmaTxDesc;
@ -425,9 +474,10 @@ bool STM32_EMAC::link_out(emac_mem_buf_t *buf)
} }
/* Prepare transmit descriptors to give to DMA */ /* Prepare transmit descriptors to give to DMA */
HAL_ETH_TransmitFrame(&EthHandle, framelength); if (HAL_ETH_TransmitFrame(&EthHandle, framelength) != HAL_OK) {
tr_error("HAL_ETH_TransmitFrame issue");
success = true; success = false;
}
error: error:
@ -465,7 +515,7 @@ error:
/* copy frame from pbufs to driver buffers */ /* copy frame from pbufs to driver buffers */
for (q = p; q != NULL; q = q->next) { for (q = p; q != NULL; q = q->next) {
if (i >= ETH_TX_DESC_CNT) { if (i >= ETH_TX_DESC_CNT) {
printf("Error : ETH_TX_DESC_CNT not sufficient\n"); tr_error("Error : ETH_TX_DESC_CNT not sufficient");
goto error; goto error;
} }
@ -491,7 +541,7 @@ error:
if (status == HAL_OK) { if (status == HAL_OK) {
success = 1; success = 1;
} else { } else {
printf("Error returned by HAL_ETH_Transmit (%d)\n", status); tr_error("Error returned by HAL_ETH_Transmit (%d)", status);
success = 0; success = 0;
} }
@ -530,6 +580,7 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf)
/* get received frame */ /* get received frame */
if (HAL_ETH_GetReceivedFrame_IT(&EthHandle) != HAL_OK) { if (HAL_ETH_GetReceivedFrame_IT(&EthHandle) != HAL_OK) {
tr_debug("low_level_input no frame");
return -1; return -1;
} }
@ -541,6 +592,7 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf)
dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc; dmarxdesc = EthHandle.RxFrameInfos.FSRxDesc;
if (len > 0 && len <= ETH_RX_BUF_SIZE) { if (len > 0 && len <= ETH_RX_BUF_SIZE) {
tr_debug("low_level_input len %u", len);
/* Allocate a memory buffer chain from buffer pool */ /* Allocate a memory buffer chain from buffer pool */
*buf = memory_manager->alloc_pool(len, 0); *buf = memory_manager->alloc_pool(len, 0);
} }
@ -599,7 +651,7 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf)
if (HAL_ETH_GetRxDataBuffer(&EthHandle, &RxBuff) == HAL_OK) { if (HAL_ETH_GetRxDataBuffer(&EthHandle, &RxBuff) == HAL_OK) {
if (HAL_ETH_GetRxDataLength(&EthHandle, &frameLength) != HAL_OK) { if (HAL_ETH_GetRxDataLength(&EthHandle, &frameLength) != HAL_OK) {
printf("Error: returned by HAL_ETH_GetRxDataLength\n"); tr_error("Error: returned by HAL_ETH_GetRxDataLength");
return -1; return -1;
} }
@ -669,14 +721,18 @@ void STM32_EMAC::phy_task()
uint32_t status; uint32_t status;
if (HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BSR, &status) == HAL_OK) { if (HAL_ETH_ReadPHYRegister(&EthHandle, PHY_BSR, &status) == HAL_OK) {
if (emac_link_state_cb) { if ((emac_link_state_cb) && (status != 0xFFFF)) {
if ((status & PHY_LINKED_STATUS) && !(phy_status & PHY_LINKED_STATUS)) { if ((status & PHY_LINKED_STATUS) && !(phy_status & PHY_LINKED_STATUS)) {
tr_info("emac_link_state_cb set to true");
emac_link_state_cb(true); emac_link_state_cb(true);
} else if (!(status & PHY_LINKED_STATUS) && (phy_status & PHY_LINKED_STATUS)) { } else if (!(status & PHY_LINKED_STATUS) && (phy_status & PHY_LINKED_STATUS)) {
tr_info("emac_link_state_cb set to false");
emac_link_state_cb(false); emac_link_state_cb(false);
} }
} }
phy_status = status; phy_status = status;
} else {
tr_error("HAL_ETH_ReadPHYRegister issue");
} }
} }
@ -713,8 +769,10 @@ void STM32_EMAC::phy_task()
if (emac_link_state_cb) { if (emac_link_state_cb) {
if (is_up && !was_up) { if (is_up && !was_up) {
emac_link_state_cb(true); emac_link_state_cb(true);
tr_info("emac_link_state_cb set to true");
} else if (!is_up && was_up) { } else if (!is_up && was_up) {
emac_link_state_cb(false); emac_link_state_cb(false);
tr_info("emac_link_state_cb set to false");
} }
} }
@ -821,6 +879,8 @@ void mbed_default_mac_address(char *mac)
bool STM32_EMAC::power_up() bool STM32_EMAC::power_up()
{ {
tr_info("power_up");
sleep_manager_lock_deep_sleep(); sleep_manager_lock_deep_sleep();
/* Initialize the hardware */ /* Initialize the hardware */
@ -829,13 +889,13 @@ bool STM32_EMAC::power_up()
} }
/* Worker thread */ /* Worker thread */
thread = create_new_thread("stm32_emac_thread", &STM32_EMAC::thread_function, this, THREAD_STACKSIZE, THREAD_PRIORITY, &thread_cb); thread = create_new_thread("stm32_emac_thread", &STM32_EMAC::thread_function, this, MBED_CONF_STM32_EMAC_THREAD_STACKSIZE, THREAD_PRIORITY, &thread_cb);
phy_task_handle = mbed::mbed_event_queue()->call_every(PHY_TASK_PERIOD_MS, mbed::callback(this, &STM32_EMAC::phy_task)); phy_task_handle = mbed::mbed_event_queue()->call_every(PHY_TASK_PERIOD_MS, mbed::callback(this, &STM32_EMAC::phy_task));
#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\ #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx)\
|| defined (STM32F779xx) || defined (STM32F779xx)
rmii_watchdog_thread = create_new_thread("stm32_rmii_watchdog", &STM32_EMAC::rmii_watchdog_thread_function, this, THREAD_STACKSIZE, THREAD_PRIORITY, &rmii_watchdog_thread_cb); rmii_watchdog_thread = create_new_thread("stm32_rmii_watchdog", &STM32_EMAC::rmii_watchdog_thread_function, this, 128, THREAD_PRIORITY, &rmii_watchdog_thread_cb);
#endif #endif
/* Allow the PHY task to detect the initial link state and set up the proper flags */ /* Allow the PHY task to detect the initial link state and set up the proper flags */
@ -904,6 +964,8 @@ void STM32_EMAC::set_all_multicast(bool all)
void STM32_EMAC::power_down() void STM32_EMAC::power_down()
{ {
tr_info("power_down");
/* No-op at this stage */ /* No-op at this stage */
sleep_manager_unlock_deep_sleep(); sleep_manager_unlock_deep_sleep();
} }

4
features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.h
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@ -1,4 +1,6 @@
/* Copyright (c) 2017 ARM Limited /* Copyright (c) 2017 ARM Limited
* Copyright (c) 2017 STMicroelectronics
* SPDX-License-Identifier: Apache-2.0
* *
* Licensed under the Apache License, Version 2.0 (the "License"); * Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License. * you may not use this file except in compliance with the License.
@ -176,4 +178,4 @@ private:
int phy_task_handle; /**< Handle for phy task event */ int phy_task_handle; /**< Handle for phy task event */
}; };
#endif /* K64F_EMAC_H_ */ #endif /* STM32_EMAC_H_ */

85
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_conf.h
View File

@ -162,75 +162,52 @@
/* ################## Ethernet peripheral configuration ##################### */ /* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */ /* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB #ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB
#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */ /* default value in features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json */
#endif #define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB #else
#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */ /* ex: bare metal profile */
#define ETH_RXBUFNB 0 /* Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 0 /* Tx buffers of size ETH_TX_BUF_SIZE */
#endif #endif
/* Section 2: PHY configuration section */ /* Section 2: PHY configuration section */
/* DP83848 PHY Address*/ /* PHY delay */
#define DP83848_PHY_ADDRESS 0x01U #ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
#define PHY_RESET_DELAY 0x000000FFU #else
/* PHY Configuration delay */ #define PHY_RESET_DELAY 0
#endif
#define PHY_CONFIG_DELAY 0x00000FFFU #define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO 0x0000FFFFU #define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO 0x0000FFFFU #define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */ /* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ #define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ #define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */ /* Section 4: Extended PHY Registers */
#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ #define PHY_SR MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ #define PHY_SPEED_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS /*!< PHY Speed mask */
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ #define PHY_DUPLEX_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS /*!< PHY Duplex mask */
#else
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SR 0
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ #define PHY_SPEED_STATUS 0
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ #define PHY_DUPLEX_STATUS 0
#endif
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */ /* ################## SPI peripheral configuration ########################## */

83
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@ -170,75 +170,52 @@
/* ################## Ethernet peripheral configuration ##################### */ /* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */ /* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB #ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB
#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */ /* default value in features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json */
#endif #define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB #else
#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */ /* ex: bare metal profile */
#define ETH_RXBUFNB 0 /* Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 0 /* Tx buffers of size ETH_TX_BUF_SIZE */
#endif #endif
/* Section 2: PHY configuration section */ /* Section 2: PHY configuration section */
/* DP83848 PHY Address*/ /* PHY delay */
#define DP83848_PHY_ADDRESS 0x01U #ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
#define PHY_RESET_DELAY 0x000000FFU #else
/* PHY Configuration delay */ #define PHY_RESET_DELAY 0
#endif
#define PHY_CONFIG_DELAY 0x00000FFFU #define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO 0x0000FFFFU #define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO 0x0000FFFFU #define PHY_WRITE_TO 0x0000FFFFU
/* Section 3: Common PHY Registers */ /* Section 3: Common PHY Registers */
#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ #define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ #define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ #define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ #define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ #define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */ /* Section 4: Extended PHY Registers */
#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER
#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ #define PHY_SR MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ #define PHY_SPEED_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS /*!< PHY Speed mask */
#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ #define PHY_DUPLEX_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS /*!< PHY Duplex mask */
#else
#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ #define PHY_SR 0
#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ #define PHY_SPEED_STATUS 0
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ #define PHY_DUPLEX_STATUS 0
#endif
#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */ /* ################## SPI peripheral configuration ########################## */

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@ -196,41 +196,29 @@
/* ################## Ethernet peripheral configuration ##################### */ /* ################## Ethernet peripheral configuration ##################### */
/* Section 1 : Ethernet peripheral configuration */ /* Definition of the Ethernet driver buffers size and count */
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
#define MAC_ADDR0 2U
#define MAC_ADDR1 0U
#define MAC_ADDR2 0U
#define MAC_ADDR3 0U
#define MAC_ADDR4 0U
#define MAC_ADDR5 0U
/* Definition of the Ethernet driver buffers size and count */
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB #ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB
#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */ /* default value in features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json */
#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
#else #else
#define ETH_RXBUFNB 4 /* Rx buffers of size ETH_RX_BUF_SIZE */ /* ex: bare metal profile */
#endif #define ETH_RXBUFNB 0 /* Rx buffers of size ETH_RX_BUF_SIZE */
#define ETH_TXBUFNB 0 /* Tx buffers of size ETH_TX_BUF_SIZE */
#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB
#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
#else
#define ETH_TXBUFNB 4 /* Rx buffers of size ETH_TX_BUF_SIZE */
#endif #endif
/* Section 2: PHY configuration section */ /* Section 2: PHY configuration section */
/* DP83848 PHY Address*/ /* PHY delay */
#define DP83848_PHY_ADDRESS 0x01U #ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
#define PHY_RESET_DELAY 0x000000FFU #else
/* PHY Configuration delay */ #define PHY_RESET_DELAY 0
#endif
#define PHY_CONFIG_DELAY 0x00000FFFU #define PHY_CONFIG_DELAY 0x00000FFFU
#define PHY_READ_TO 0x0000FFFFU #define PHY_READ_TO 0x0000FFFFU
#define PHY_WRITE_TO 0x0000FFFFU #define PHY_WRITE_TO 0x0000FFFFU
@ -240,35 +228,20 @@
#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ #define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ #define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ #define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ #define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
/* Section 4: Extended PHY Registers */ /* Section 4: Extended PHY Registers */
#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ #define PHY_SR MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER /*!< PHY status register Offset */
#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ #define PHY_SPEED_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS /*!< PHY Speed mask */
#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ #define PHY_DUPLEX_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS /*!< PHY Duplex mask */
#else
#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ #define PHY_SR 0
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ #define PHY_SPEED_STATUS 0
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ #define PHY_DUPLEX_STATUS 0
#endif
#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */
#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */
/* ################## SPI peripheral configuration ########################## */ /* ################## SPI peripheral configuration ########################## */