Merge pull request #12317 from NXPmicro/MXRT_FlashSupport

MXRT1050 Flash support

components/storage/blockdevice/COMPONENT_FLASHIAP/mbed_lib.json

@@ -22,6 +22,10 @@
         "S5JS100": {
             "base-address": "0x40EF5000",
             "size": "0x80000"
+        },
+        "MIMXRT1050_EVK": {
+            "base-address": "0x60400000",
+            "size": "0x3C00000"
         }
     }
 }

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/flash_api.c

@@ -0,0 +1,374 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2019 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "mbed_toolchain.h"
+#include "mbed_critical.h"
+
+#if DEVICE_FLASH
+
+#include "fsl_flexspi.h"
+#include "fsl_cache.h"
+#include "flash_defines.h"
+
+AT_QUICKACCESS_SECTION_CODE(void flexspi_update_lut_ram(void));
+AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_write_enable_ram(uint32_t baseAddr));
+AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_wait_bus_busy_ram(void));
+AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_erase_sector_ram(uint32_t address));
+AT_QUICKACCESS_SECTION_CODE(static void flexspi_lower_clock_ram(void));
+AT_QUICKACCESS_SECTION_CODE(static void flexspi_clock_update_ram(void));
+AT_QUICKACCESS_SECTION_CODE(status_t flexspi_nor_flash_page_program_ram(uint32_t address,
+                                                                        const uint32_t *src,
+                                                                        uint32_t size));
+AT_QUICKACCESS_SECTION_CODE(void flexspi_nor_flash_read_data_ram(uint32_t addr,
+                                                                 uint32_t *buffer,
+                                                                 uint32_t size));
+
+void flexspi_update_lut_ram(void)
+{
+    flexspi_config_t config;
+
+    memset(&config, 0, sizeof(config));
+
+    /*Get FLEXSPI default settings and configure the flexspi. */
+    FLEXSPI_GetDefaultConfig(&config);
+
+    /*Set AHB buffer size for reading data through AHB bus. */
+    config.ahbConfig.enableAHBPrefetch = true;
+    /*Allow AHB read start address do not follow the alignment requirement. */
+    config.ahbConfig.enableReadAddressOpt = true;
+    config.ahbConfig.enableAHBBufferable  = true;
+    config.ahbConfig.enableAHBCachable    = true;
+    /* enable diff clock and DQS */
+    config.enableSckBDiffOpt = true;
+    config.rxSampleClock     = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
+    config.enableCombination = true;
+    FLEXSPI_Init(FLEXSPI, &config);
+
+    /* Configure flash settings according to serial flash feature. */
+    FLEXSPI_SetFlashConfig(FLEXSPI, &deviceconfig, kFLEXSPI_PortA1);
+
+    /* Update LUT table. */
+    FLEXSPI_UpdateLUT(FLEXSPI, 0, customLUT, CUSTOM_LUT_LENGTH);
+
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    /* Wait for bus idle. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+}
+
+status_t flexspi_nor_write_enable_ram(uint32_t baseAddr)
+{
+    flexspi_transfer_t flashXfer;
+    status_t status = kStatus_Success;
+
+    memset(&flashXfer, 0, sizeof(flashXfer));
+
+    /* Write enable */
+    flashXfer.deviceAddress = baseAddr;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 2;
+    flashXfer.seqIndex      = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE;
+
+    status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+    return status;
+}
+
+status_t flexspi_nor_wait_bus_busy_ram(void)
+{
+    /* Wait status ready. */
+    bool isBusy = false;
+    uint32_t readValue = 0;
+    status_t status = kStatus_Success;
+    flexspi_transfer_t flashXfer;
+
+    memset(&flashXfer, 0, sizeof(flashXfer));
+
+    flashXfer.deviceAddress = 0;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Read;
+    flashXfer.SeqNumber     = 2;
+    flashXfer.seqIndex      = HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS;
+    flashXfer.data          = &readValue;
+    flashXfer.dataSize      = 2;
+
+    do {
+        status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        if (readValue & 0x8000) {
+            isBusy = false;
+        } else {
+            isBusy = true;
+        }
+
+        if (readValue & 0x3200) {
+            status = kStatus_Fail;
+            break;
+        }
+
+    } while (isBusy);
+
+    return status;
+
+}
+
+status_t flexspi_nor_flash_erase_sector_ram(uint32_t address)
+{
+    status_t status = kStatus_Success;
+    flexspi_transfer_t flashXfer;
+
+    memset(&flashXfer, 0, sizeof(flashXfer));
+
+    /* Write enable */
+    status = flexspi_nor_write_enable_ram(address);
+    if (status != kStatus_Success) {
+        return status;
+    }
+
+    flashXfer.deviceAddress = address;
+    flashXfer.port          = kFLEXSPI_PortA1;
+    flashXfer.cmdType       = kFLEXSPI_Command;
+    flashXfer.SeqNumber     = 4;
+    flashXfer.seqIndex      = HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR;
+
+    status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+    if (status != kStatus_Success) {
+        return status;
+    }
+
+    status = flexspi_nor_wait_bus_busy_ram();
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    return status;
+}
+
+static void flexspi_lower_clock_ram(void)
+{
+    unsigned int reg = 0;
+
+    /* Wait for bus idle. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+
+    FLEXSPI_Enable(FLEXSPI, false);
+
+    /* Disable FlexSPI clock */
+    CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
+
+    /* flexspi clock 66M, DDR mode, internal clock 33M. */
+    reg = CCM->CSCMR1;
+    reg &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK;
+    reg |= CCM_CSCMR1_FLEXSPI_PODF(3);
+    CCM->CSCMR1 = reg;
+
+    /* Enable FlexSPI clock */
+    CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
+
+    FLEXSPI_Enable(FLEXSPI, true);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    /* Wait for bus idle. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+}
+
+static void flexspi_clock_update_ram(void)
+{
+    /* Program finished, speed the clock to 133M. */
+    /* Wait for bus idle before change flash configuration. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+    FLEXSPI_Enable(FLEXSPI, false);
+    /* Disable FlexSPI clock */
+    CCM->CCGR6 &= ~CCM_CCGR6_CG5_MASK;
+
+    /* flexspi clock 260M, DDR mode, internal clock 130M. */
+    CCM->CSCMR1 &= ~CCM_CSCMR1_FLEXSPI_PODF_MASK;
+
+    /* Enable FlexSPI clock */
+    CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
+
+    FLEXSPI_Enable(FLEXSPI, true);
+
+    /* Do software reset. */
+    FLEXSPI_SoftwareReset(FLEXSPI);
+
+    /* Wait for bus idle. */
+    while (!FLEXSPI_GetBusIdleStatus(FLEXSPI)) {
+    }
+}
+
+status_t flexspi_nor_flash_page_program_ram(uint32_t address, const uint32_t *src, uint32_t size)
+{
+    status_t status = kStatus_Success;
+    flexspi_transfer_t flashXfer;
+    uint32_t offset = 0;
+
+    memset(&flashXfer, 0, sizeof(flashXfer));
+
+    flexspi_lower_clock_ram();
+
+    while (size > 0) {
+        /* Write enable */
+        status = flexspi_nor_write_enable_ram(address + offset);
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        /* Prepare page program command */
+        flashXfer.deviceAddress = address + offset;
+        flashXfer.port          = kFLEXSPI_PortA1;
+        flashXfer.cmdType       = kFLEXSPI_Write;
+        flashXfer.SeqNumber     = 2;
+        flashXfer.seqIndex      = HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM;
+        flashXfer.data          = (uint32_t *)(src + offset);
+        flashXfer.dataSize      = BOARD_FLASH_PAGE_SIZE;
+
+        status = FLEXSPI_TransferBlocking(FLEXSPI, &flashXfer);
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        status = flexspi_nor_wait_bus_busy_ram();
+
+        if (status != kStatus_Success) {
+            return status;
+        }
+
+        size -= BOARD_FLASH_PAGE_SIZE;
+        offset += BOARD_FLASH_PAGE_SIZE;
+    }
+
+    flexspi_clock_update_ram();
+
+    return status;
+}
+
+void flexspi_nor_flash_read_data_ram(uint32_t addr, uint32_t *buffer, uint32_t size)
+{
+    memcpy(buffer, (void *)addr, size);
+}
+
+int32_t flash_init(flash_t *obj)
+{
+    flexspi_update_lut_ram();
+
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    status_t status = kStatus_Success;
+    int32_t ret = 0;
+
+    core_util_critical_section_enter();
+
+    status = flexspi_nor_flash_erase_sector_ram(address - FlexSPI_AMBA_BASE);
+
+    if (status != kStatus_Success) {
+        ret = -1;
+    } else {
+        DCACHE_InvalidateByRange(address, BOARD_FLASH_SECTOR_SIZE);
+    }
+
+    core_util_critical_section_exit();
+
+    return ret;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+    status_t status = kStatus_Success;
+    int32_t ret = 0;
+
+    core_util_critical_section_enter();
+
+    status = flexspi_nor_flash_page_program_ram(address - FlexSPI_AMBA_BASE, (uint32_t *)data, size);
+
+    if (status != kStatus_Success) {
+        ret = -1;
+    } else {
+        DCACHE_InvalidateByRange(address, size);
+    }
+
+    core_util_critical_section_exit();
+
+    return ret;
+}
+
+int32_t flash_read(flash_t *obj, uint32_t address, uint8_t *data, uint32_t size)
+{
+    flexspi_nor_flash_read_data_ram(address, (uint32_t *)data, size);
+
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    uint32_t sectorsize = MBED_FLASH_INVALID_SIZE;
+    uint32_t devicesize = BOARD_FLASH_SIZE;
+    uint32_t startaddr = BOARD_FLASH_START_ADDR;
+
+    if ((address >= startaddr) && (address < (startaddr + devicesize))) {
+        sectorsize = BOARD_FLASH_SECTOR_SIZE;
+    }
+
+    return sectorsize;
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return BOARD_FLASH_PAGE_SIZE;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    return BOARD_FLASH_START_ADDR;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+    return BOARD_FLASH_SIZE;
+}
+
+uint8_t flash_get_erase_value(const flash_t *obj)
+{
+    (void)obj;
+
+    return 0xFF;
+}
+
+#endif //DEVICE_FLASH
+

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/objects.h

@@ -66,6 +66,12 @@ struct trng_s {
     uint8_t dummy;
 };
 
+#if DEVICE_FLASH
+struct flash_s {
+    uint8_t dummy;
+};
+#endif
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h

@@ -19,7 +19,13 @@
 #define MBED_DEVICE_H
 
 #define DEVICE_ID_LENGTH       24
-#define BOARD_FLASH_SIZE       (0x4000000U)
+/* 4MB reserved for mbed-os */
+#define BOARD_FLASH_SIZE             (0x3C00000U)
+#define BOARD_FLASH_START_ADDR       (0x60400000U)
+
+#define BOARD_FLASH_PAGE_SIZE        (512)
+#define BOARD_FLASH_SECTOR_SIZE      (262144)
+
 #define BOARD_ENET_PHY_ADDR    (2)
 
 #include "objects.h"

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/flash_defines.h

@@ -0,0 +1,180 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2019 ARM Limited
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef _NXP_FLASH_DEFINES_H_
+#define _NXP_FLASH_DEFINES_H_
+
+#include "fsl_common.h"
+
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA 0
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA 1
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS 2
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE 4
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR 6
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM 10
+#define HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP 12
+#define CUSTOM_LUT_LENGTH 64
+
+static uint32_t customLUT[CUSTOM_LUT_LENGTH] = {
+    /* Read Data */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04),
+
+    /* Write Data */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x02),
+    /* Read Status */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 2] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 3] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x70), // DATA 0x70
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 4] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 5] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x0B),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_READSTATUS + 6] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR, kFLEXSPI_8PAD, 0x04, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
+
+    /* Write Enable */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 2] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 3] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // DATA 0xAA
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 4] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 5] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 6] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEENABLE + 7] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+
+    /* Erase Sector  */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 2] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 3] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80), // DATA 0x80
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 4] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 5] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 6] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 7] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 8] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 9] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 10] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 11] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 12] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 13] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASESECTOR + 14] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x30, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x00),
+
+    /* program page */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA), // ADDR 0x555
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 2] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 3] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0), // DATA 0xA0
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 4] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 5] = FLEXSPI_LUT_SEQ(
+        kFLEXSPI_Command_CADDR_DDR, kFLEXSPI_8PAD, 0x10, kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x80),
+
+    /* Erase chip */
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 1] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 2] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 3] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x80),
+    // 1
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 4] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 5] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 6] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 7] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+    // 2
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 8] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 9] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 10] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x02),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 11] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x55),
+    // 3
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 12] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 13] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xAA),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 14] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x05),
+    [4 * HYPERFLASH_CMD_LUT_SEQ_IDX_ERASECHIP + 15] =
+        FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x00, kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0x10),
+};
+
+flexspi_device_config_t deviceconfig = {
+    .flexspiRootClk       = 42000000, /* 42MHZ SPI serial clock */
+    .isSck2Enabled        = false,
+    .flashSize            = BOARD_FLASH_SIZE,
+    .CSIntervalUnit       = kFLEXSPI_CsIntervalUnit1SckCycle,
+    .CSInterval           = 2,
+    .CSHoldTime           = 0,
+    .CSSetupTime          = 3,
+    .dataValidTime        = 1,
+    .columnspace          = 3,
+    .enableWordAddress    = true,
+    .AWRSeqIndex          = HYPERFLASH_CMD_LUT_SEQ_IDX_WRITEDATA,
+    .AWRSeqNumber         = 1,
+    .ARDSeqIndex          = HYPERFLASH_CMD_LUT_SEQ_IDX_READDATA,
+    .ARDSeqNumber         = 1,
+    .AHBWriteWaitUnit     = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
+    .AHBWriteWaitInterval = 20,
+};
+
+#endif /* _NXP_FLASH_DEFINES_H_ */

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_ARM_STD/MIMXRT1052xxxxx.sct

@@ -44,7 +44,7 @@
 #define m_interrupts_size              0x00000400
 
 #define m_text_start                   0x60002400
-#define m_text_size                    0x03FFDC00
+#define m_text_size                    0x003FDC00
 
 #define m_text2_start                  0x00000000
 #define m_text2_size                   0x00020000

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_GCC_ARM/MIMXRT1052xxxxx.ld

@@ -45,7 +45,7 @@ MEMORY
   m_flash_config        (RX)  : ORIGIN = 0x60000000, LENGTH = 0x00001000
   m_ivt                 (RX)  : ORIGIN = 0x60001000, LENGTH = 0x00001000
   m_interrupts          (RX)  : ORIGIN = 0x60002000, LENGTH = 0x00000400
-  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x03FFDC00
+  m_text                (RX)  : ORIGIN = 0x60002400, LENGTH = 0x003FDC00
   m_text2               (RX)  : ORIGIN = 0x00000000, LENGTH = 0x00020000
   m_data                (RW)  : ORIGIN = 0x80000000, LENGTH = 0x01E00000
   m_ncache              (RW)  : ORIGIN = 0x81E00000, LENGTH = 0x00200000

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/device/TOOLCHAIN_IAR/MIMXRT1052xxxxx.icf

@@ -42,7 +42,7 @@ define symbol m_interrupts_start       = 0x60002000;
 define symbol m_interrupts_end         = 0x600023FF;
 
 define symbol m_text_start             = 0x60002400;
-define symbol m_text_end               = 0x63FFFFFF;
+define symbol m_text_end               = 0x603FFFFF;
 
 define symbol m_text2_start            = 0x00000000;
 define symbol m_text2_end              = 0x0001FFFF;

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.c

@@ -78,7 +78,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base);
  * @param base FLEXSPI base pointer.
  * @param config Flash configuration parameters.
  */
-static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config);
+AT_QUICKACCESS_SECTION_CODE(static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t *config));
 
 /*!
  * @brief Check and clear IP command execution errors.
@@ -86,7 +86,7 @@ static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t
  * @param base FLEXSPI base pointer.
  * @param status interrupt status.
  */
-status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status);
+AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status));
 
 /*******************************************************************************
  * Variables
@@ -164,7 +164,7 @@ static uint32_t FLEXSPI_ConfigureDll(FLEXSPI_Type *base, flexspi_device_config_t
             }
             break;
         default:
-            assert(false);
+            //assert(false);
             break;
     }
 
@@ -216,7 +216,7 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
         }
         else
         {
-            assert(false);
+            //assert(false);
         }
 
         /* Clear the flags. */
@@ -246,7 +246,9 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the flexspi clock */
-    CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]);
+    //CLOCK_EnableClock(s_flexspiClock[FLEXSPI_GetInstance(base)]);
+    /* Access the register directly to avoid warnings accessing non ran functions */
+    CCM->CCGR6 |= CCM_CCGR6_CG5_MASK;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(FSL_FEATURE_FLEXSPI_HAS_RESET) && FSL_FEATURE_FLEXSPI_HAS_RESET
@@ -497,7 +499,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
  */
 void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)
 {
-    assert(index < 64U);
+    //assert(index < 64U);
 
     uint8_t i = 0;
     volatile uint32_t *lutBase;

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexspi.h

@@ -346,14 +346,14 @@ extern "C" {
  * @param base FLEXSPI peripheral base address.
  * @param config FLEXSPI configure structure.
  */
-void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config);
+AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config));
 
 /*!
  * @brief Gets default settings for FLEXSPI.
  *
  * @param config FLEXSPI configuration structure.
  */
-void FLEXSPI_GetDefaultConfig(flexspi_config_t *config);
+AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_GetDefaultConfig(flexspi_config_t *config));
 
 /*!
  * @brief Deinitializes the FLEXSPI module.
@@ -374,7 +374,9 @@ void FLEXSPI_Deinit(FLEXSPI_Type *base);
  * @param config Flash configuration parameters.
  * @param port FLEXSPI Operation port.
  */
-void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port);
+AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base,
+                                                        flexspi_device_config_t *config,
+                                                        flexspi_port_t port));
 
 /*!
  * @brief Software reset for the FLEXSPI logic.
@@ -384,7 +386,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
  *
  * @param base FLEXSPI peripheral base address.
  */
-static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
+AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base))
 {
     base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
     while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK))
@@ -398,7 +400,7 @@ static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @param enable True means enable FLEXSPI, false means disable.
  */
-static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
+AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable))
 {
     if (enable)
     {
@@ -568,7 +570,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
  * @param base FLEXSPI peripheral base address.
  * @param interrupt status flag.
  */
-static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
+AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask))
 {
     base->INTR |= mask;
 }
@@ -637,7 +639,7 @@ static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Ty
  * @retval true Bus is idle.
  * @retval false Bus is busy.
  */
-static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
+AT_QUICKACCESS_SECTION_CODE(static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base))
 {
     return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
 }
@@ -698,7 +700,8 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable
  * @param cmd Command sequence array.
  * @param count Number of sequences.
  */
-void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count);
+AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index,
+                                                   const uint32_t *cmd, uint32_t count));
 
 /*!
  * @brief Writes data into FIFO.
@@ -735,7 +738,8 @@ static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex)
  * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
  * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
  */
-status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
+AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base,
+                                                           uint32_t *buffer, size_t size));
 
 /*!
  * @brief Receives a buffer of data bytes using a blocking method.
@@ -748,7 +752,8 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size
  * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected
  * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
  */
-status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size);
+AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base,
+                                                          uint32_t *buffer, size_t size));
 
 /*!
  * @brief Execute command to transfer a buffer data bytes using a blocking method.
@@ -759,7 +764,8 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)
  * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected
  * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected
  */
-status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer);
+AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base,
+                                                              flexspi_transfer_t *xfer));
 /*! @} */
 
 /*!

targets/targets.json

@@ -2824,6 +2824,9 @@
             "MBED_MPU_CUSTOM",
             "MBED_TICKLESS"
         ],
+        "components_add": [
+            "FLASHIAP"
+        ],
         "inherits": [
             "Target"
         ],
@@ -2850,7 +2853,8 @@
             "SPISLAVE",
             "STDIO_MESSAGES",
             "TRNG",
-            "WATCHDOG"
+            "WATCHDOG",
+            "FLASH"
         ],
         "release_versions": [
             "2",