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Refactor ARM MSP2 target scatter files for bare metal support

pull/14300/head
Harrison Mutai 2021-02-18 14:44:46 +00:00
parent 0f233735af
commit b31ce7a9c7
5 changed files with 10 additions and 15 deletions
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5
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -58,13 +58,13 @@
# endif # endif
#endif #endif
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
#define VECTOR_SIZE 0x100 #define VECTOR_SIZE 0x100
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE) #define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE) #define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE) #define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@ -73,7 +73,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
*(+RO) *(+RO)
} }
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data
*(+RW +ZI) *(+RW +ZI)
} }

5
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -58,13 +58,13 @@
# endif # endif
#endif #endif
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
#define VECTOR_SIZE 0x100 #define VECTOR_SIZE 0x100
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE) #define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE) #define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE) #define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@ -73,7 +73,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
*(+RO) *(+RO)
} }
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data
*(+RW +ZI) *(+RW +ZI)
} }

5
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -59,13 +59,13 @@
# endif # endif
#endif #endif
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
#define VECTOR_SIZE 0x100 #define VECTOR_SIZE 0x100
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE) #define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE) #define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE) #define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@ -74,7 +74,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
*(+RO) *(+RO)
} }
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data
*(+RW +ZI) *(+RW +ZI)
} }

5
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -59,13 +59,13 @@
# endif # endif
#endif #endif
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
#define VECTOR_SIZE 0x100 #define VECTOR_SIZE 0x100
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE) #define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE) #define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE) #define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@ -74,7 +74,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
*(+RO) *(+RO)
} }
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data
*(+RW +ZI) *(+RW +ZI)
} }

5
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -60,13 +60,13 @@
# endif # endif
#endif #endif
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 ; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
#define VECTOR_SIZE 0x100 #define VECTOR_SIZE 0x100
#define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE) #define RAM_FIXED_SIZE (MBED_CONF_TARGET_BOOT_STACK_SIZE + VECTOR_SIZE)
#define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE) #define MBED_RAM1_START (MBED_RAM_START + VECTOR_SIZE)
#define MBED_RAM1_SIZE (MBED_RAM_SIZE - VECTOR_SIZE) #define MBED_RAM1_SIZE (MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@ -75,7 +75,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
*(+RO) *(+RO)
} }
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data RW_IRAM1 MBED_RAM1_START MBED_RAM1_SIZE { ; RW data
*(+RW +ZI) *(+RW +ZI)
} }