mirror of https://github.com/ARMmbed/mbed-os.git
SPI fpga test: use get_capabilities() function to skip test cases for unsupported features
parent
4b1b4f72af
commit
b24afed5ae
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@ -44,6 +44,10 @@ typedef enum {
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#define FREQ_500_KHZ 500000
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#define FREQ_500_KHZ 500000
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#define FREQ_1_MHZ 1000000
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#define FREQ_1_MHZ 1000000
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#define FREQ_2_MHZ 2000000
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#define FREQ_2_MHZ 2000000
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#define FREQ_MIN ((uint32_t)0)
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#define FREQ_MAX ((uint32_t)-1)
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#define TEST_CAPABILITY_BIT(MASK, CAP) ((1 << CAP) & (MASK))
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const int TRANSFER_COUNT = 300;
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const int TRANSFER_COUNT = 300;
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SPIMasterTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins());
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SPIMasterTester tester(DefaultFormFactor::pins(), DefaultFormFactor::restricted_pins());
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@ -62,6 +66,36 @@ void spi_async_handler()
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}
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}
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#endif
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#endif
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/* Auxiliary function to check platform capabilities against test case. */
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static bool check_capabilities(const spi_capabilities_t *capabilities, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency)
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{
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// Symbol size
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if (!TEST_CAPABILITY_BIT(capabilities->word_length, (sym_size - 1))) {
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utest_printf("\n<Specified symbol size is not supported on this platform> skipped ");
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return false;
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}
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// SPI clock mode
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if (!TEST_CAPABILITY_BIT(capabilities->clk_modes, spi_mode)) {
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utest_printf("\n<Specified spi clock mode is not supported on this platform> skipped");
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return false;
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}
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// Frequency
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if (frequency != FREQ_MAX && frequency != FREQ_MIN && frequency < capabilities->minimum_frequency && frequency > capabilities->maximum_frequency) {
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utest_printf("\n<Specified frequency is not supported on this platform> skipped ");
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return false;
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}
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// Async mode
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if (transfer_type == TRANSFER_SPI_MASTER_TRANSFER_ASYNC && capabilities->async_mode == false) {
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utest_printf("\n<Async mode is not supported on this platform> skipped ");
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return false;
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}
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return true;
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}
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void fpga_spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel)
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void fpga_spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName ssel)
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{
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{
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spi_init(&spi, mosi, miso, sclk, ssel);
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spi_init(&spi, mosi, miso, sclk, ssel);
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@ -72,6 +106,15 @@ void fpga_spi_test_init_free(PinName mosi, PinName miso, PinName sclk, PinName s
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void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency)
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void fpga_spi_test_common(PinName mosi, PinName miso, PinName sclk, PinName ssel, SPITester::SpiMode spi_mode, uint32_t sym_size, transfer_type_t transfer_type, uint32_t frequency)
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{
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{
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spi_capabilities_t capabilities;
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spi_get_capabilities(ssel, false, &capabilities);
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if (check_capabilities(&capabilities, spi_mode, sym_size, transfer_type, frequency) == false) {
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return;
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}
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uint32_t sym_mask = ((1 << sym_size) - 1);
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uint32_t sym_mask = ((1 << sym_size) - 1);
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// Remap pins for test
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// Remap pins for test
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@ -178,14 +221,10 @@ Case cases[] = {
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Case("SPI - mode testing (MODE_1)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode1, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - mode testing (MODE_1)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode1, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - mode testing (MODE_2)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode2, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - mode testing (MODE_2)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode2, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - mode testing (MODE_3)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode3, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - mode testing (MODE_3)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode3, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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#if !defined(TARGET_NRF52840_DK)
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Case("SPI - symbol size testing (16)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 16, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - symbol size testing (16)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 16, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_1_MHZ> >),
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#endif
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Case("SPI - frequency testing (500 kHz)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_500_KHZ> >),
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Case("SPI - frequency testing (500 kHz)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_500_KHZ> >),
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Case("SPI - frequency testing (2 MHz)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_2_MHZ> >),
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Case("SPI - frequency testing (2 MHz)", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_WRITE_SYNC, FREQ_2_MHZ> >),
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Case("SPI - block write", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ> >),
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Case("SPI - block write", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_BLOCK_WRITE_SYNC, FREQ_1_MHZ> >),
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#if DEVICE_SPI_ASYNCH
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#if DEVICE_SPI_ASYNCH
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Case("SPI - async mode", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_1_MHZ> >)
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Case("SPI - async mode", one_peripheral<SPIPort, DefaultFormFactor, fpga_spi_test_common<SPITester::Mode0, 8, TRANSFER_SPI_MASTER_TRANSFER_ASYNC, FREQ_1_MHZ> >)
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#endif
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#endif
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@ -128,6 +128,51 @@ static void spi_configure_driver_instance(spi_t *obj)
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}
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}
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}
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}
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void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap)
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{
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if (slave) {
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cap->minimum_frequency = 200000; // 200 kHz
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cap->maximum_frequency = 2000000; // 2 MHz
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cap->word_length = 0x00000080; // 8 bit symbols
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cap->support_slave_mode = false; // to be determined later based on ssel
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cap->hw_cs_handle = false; // irrelevant in slave mode
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cap->slave_delay_between_symbols_ns = 2500; // 2.5 us
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cap->clk_modes = 0x0f; // all clock modes
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#if DEVICE_SPI_ASYNCH
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cap->async_mode = true;
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#else
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cap->async_mode = false;
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#endif
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} else {
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cap->minimum_frequency = 200000; // 200 kHz
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cap->maximum_frequency = 2000000; // 2 MHz
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cap->word_length = 0x00000080; // 8 bit symbols
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cap->support_slave_mode = false; // to be determined later based on ssel
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cap->hw_cs_handle = false; // to be determined later based on ssel
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cap->slave_delay_between_symbols_ns = 0; // irrelevant in master mode
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cap->clk_modes = 0x0f; // all clock modes
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#if DEVICE_SPI_ASYNCH
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cap->async_mode = true;
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#else
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cap->async_mode = false;
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#endif
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}
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// check if given ssel pin is in the cs pinmap
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const PinMap *cs_pins = spi_master_cs_pinmap();
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PinName pin = NC;
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while (cs_pins->pin != NC) {
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if (cs_pins->pin == ssel) {
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#if DEVICE_SPISLAVE
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cap->support_slave_mode = true;
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#endif
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cap->hw_cs_handle = true;
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break;
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}
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cs_pins++;
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}
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}
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/** Initialize the SPI peripheral
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/** Initialize the SPI peripheral
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*
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*
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* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
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* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
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@ -247,13 +292,13 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
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nrf_spi_mode_t new_mode = NRF_SPI_MODE_0;
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nrf_spi_mode_t new_mode = NRF_SPI_MODE_0;
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/* Convert Mbed HAL mode to Nordic mode. */
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/* Convert Mbed HAL mode to Nordic mode. */
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if(mode == 0) {
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if (mode == 0) {
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new_mode = NRF_SPI_MODE_0;
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new_mode = NRF_SPI_MODE_0;
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} else if(mode == 1) {
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} else if (mode == 1) {
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new_mode = NRF_SPI_MODE_1;
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new_mode = NRF_SPI_MODE_1;
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} else if(mode == 2) {
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} else if (mode == 2) {
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new_mode = NRF_SPI_MODE_2;
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new_mode = NRF_SPI_MODE_2;
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} else if(mode == 3) {
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} else if (mode == 3) {
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new_mode = NRF_SPI_MODE_3;
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new_mode = NRF_SPI_MODE_3;
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}
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}
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@ -351,8 +396,9 @@ int spi_master_write(spi_t *obj, int value)
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desc.rx_length = 1;
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desc.rx_length = 1;
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ret = nrfx_spi_xfer(&nordic_nrf5_spi_instance[instance], &desc, 0);
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ret = nrfx_spi_xfer(&nordic_nrf5_spi_instance[instance], &desc, 0);
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if (ret != NRFX_SUCCESS)
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if (ret != NRFX_SUCCESS) {
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DEBUG_PRINTF("%d error returned from nrf_spi_xfer\n\r");
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DEBUG_PRINTF("%d error returned from nrf_spi_xfer\n\r");
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}
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/* Manually set chip select pin if defined. */
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/* Manually set chip select pin if defined. */
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if (spi_inst->cs != NC) {
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if (spi_inst->cs != NC) {
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@ -421,7 +467,7 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, cha
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int tx_actual_length = (tx_length > 255) ? 255 : tx_length;
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int tx_actual_length = (tx_length > 255) ? 255 : tx_length;
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/* Set tx buffer pointer. Set to NULL if no data is going to be transmitted. */
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/* Set tx buffer pointer. Set to NULL if no data is going to be transmitted. */
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const uint8_t * tx_actual_buffer = (tx_actual_length > 0) ?
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const uint8_t *tx_actual_buffer = (tx_actual_length > 0) ?
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(const uint8_t *)(tx_buffer + tx_offset) :
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(const uint8_t *)(tx_buffer + tx_offset) :
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NULL;
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NULL;
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@ -429,7 +475,7 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, cha
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int rx_actual_length = (rx_length > 255) ? 255 : rx_length;
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int rx_actual_length = (rx_length > 255) ? 255 : rx_length;
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/* Set rx buffer pointer. Set to NULL if no data is going to be received. */
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/* Set rx buffer pointer. Set to NULL if no data is going to be received. */
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uint8_t * rx_actual_buffer = (rx_actual_length > 0) ?
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uint8_t *rx_actual_buffer = (rx_actual_length > 0) ?
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(uint8_t *)(rx_buffer + rx_offset) :
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(uint8_t *)(rx_buffer + rx_offset) :
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NULL;
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NULL;
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@ -721,7 +767,7 @@ void spi_master_transfer(spi_t *obj,
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struct buffer_s *buffer_pointer;
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struct buffer_s *buffer_pointer;
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buffer_pointer = &obj->tx_buff;
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buffer_pointer = &obj->tx_buff;
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buffer_pointer->buffer = (void*) tx;
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buffer_pointer->buffer = (void *) tx;
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buffer_pointer->length = tx_length;
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buffer_pointer->length = tx_length;
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buffer_pointer->pos = 0;
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buffer_pointer->pos = 0;
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buffer_pointer->width = 8;
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buffer_pointer->width = 8;
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