mirror of https://github.com/ARMmbed/mbed-os.git
Merge remote-tracking branch 'upstream/master'
Takayuki Kurosawa
commit
b161a143c5
|
|
@ -63,3 +63,7 @@ debug.log
|
|||
|
||||
# Orig diff files
|
||||
*.orig
|
||||
|
||||
# PyCharm
|
||||
*.idea
|
||||
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ NXP:
|
|||
Freescale:
|
||||
* [FRDM-KL05Z](https://developer.mbed.org/platforms/FRDM-KL05Z/) (Cortex-M0+)
|
||||
* [FRDM-KL25Z](http://developer.mbed.org/platforms/KL25Z/) (Cortex-M0+)
|
||||
* FRDM-KL43Z (Cortex-M0+)
|
||||
* [FRDM-KL46Z](https://developer.mbed.org/platforms/FRDM-KL46Z/) (Cortex-M0+)
|
||||
* [FRDM-K20D50M](https://developer.mbed.org/platforms/FRDM-K20D50M/) (Cortex-M4)
|
||||
* [FRDM-K22F](https://developer.mbed.org/platforms/FRDM-K22F/) (Cortex-M4F)
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ typedef enum {
|
|||
#include "USBEndpoints_LPC17_LPC23.h"
|
||||
#elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549)
|
||||
#include "USBEndpoints_LPC11U.h"
|
||||
#elif defined(TARGET_KL25Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F)
|
||||
#elif defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F)
|
||||
#include "USBEndpoints_KL25Z.h"
|
||||
#elif defined (TARGET_STM32F4)
|
||||
#include "USBEndpoints_STM32F4.h"
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#if defined(TARGET_KL25Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F)
|
||||
#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F)
|
||||
|
||||
#include "USBHAL.h"
|
||||
|
||||
|
|
@ -121,12 +121,25 @@ USBHAL::USBHAL(void) {
|
|||
epCallback[28] = &USBHAL::EP15_OUT_callback;
|
||||
epCallback[29] = &USBHAL::EP15_IN_callback;
|
||||
|
||||
#if defined(TARGET_KL43Z)
|
||||
// enable USBFS clock
|
||||
SIM->SCGC4 |= SIM_SCGC4_USBFS_MASK;
|
||||
|
||||
// enable the IRC48M clock
|
||||
USB0->CLK_RECOVER_IRC_EN |= USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK;
|
||||
|
||||
// enable the USB clock recovery tuning
|
||||
USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
|
||||
|
||||
// choose usb src clock
|
||||
SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK;
|
||||
#else
|
||||
// choose usb src as PLL
|
||||
SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
|
||||
|
||||
// enable OTG clock
|
||||
SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
|
||||
#endif
|
||||
|
||||
// Attach IRQ
|
||||
instance = this;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,14 @@
|
|||
|
||||
LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
|
||||
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
|
||||
; 0x8000 - 0xC0 = 0x7F40
|
||||
RW_IRAM1 0x1FFFE0C0 0x7F40 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,362 @@
|
|||
; * ---------------------------------------------------------------------------------------
|
||||
; * @file: startup_MKL43Z4.s
|
||||
; * @purpose: CMSIS Cortex-M0P Core Device Startup File
|
||||
; * MKL43Z4
|
||||
; * @version: 1.3
|
||||
; * @date: 2014-8-21
|
||||
; * @build: b140821
|
||||
; * ---------------------------------------------------------------------------------------
|
||||
; *
|
||||
; * Copyright (c) 1997 - 2014 , Freescale Semiconductor, Inc.
|
||||
; * All rights reserved.
|
||||
; *
|
||||
; * Redistribution and use in source and binary forms, with or without modification,
|
||||
; * are permitted provided that the following conditions are met:
|
||||
; *
|
||||
; * o Redistributions of source code must retain the above copyright notice, this list
|
||||
; * of conditions and the following disclaimer.
|
||||
; *
|
||||
; * o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
; * list of conditions and the following disclaimer in the documentation and/or
|
||||
; * other materials provided with the distribution.
|
||||
; *
|
||||
; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
; * contributors may be used to endorse or promote products derived from this
|
||||
; * software without specific prior written permission.
|
||||
; *
|
||||
; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
; *
|
||||
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
; *
|
||||
; *****************************************************************************/
|
||||
|
||||
|
||||
__initial_sp EQU 0x20006000 ; Top of RAM
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ;NMI Handler
|
||||
DCD HardFault_Handler ;Hard Fault Handler
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD SVC_Handler ;SVCall Handler
|
||||
DCD 0 ;Reserved
|
||||
DCD 0 ;Reserved
|
||||
DCD PendSV_Handler ;PendSV Handler
|
||||
DCD SysTick_Handler ;SysTick Handler
|
||||
|
||||
;External Interrupts
|
||||
DCD DMA0_IRQHandler ;DMA channel 0 transfer complete
|
||||
DCD DMA1_IRQHandler ;DMA channel 1 transfer complete
|
||||
DCD DMA2_IRQHandler ;DMA channel 2 transfer complete
|
||||
DCD DMA3_IRQHandler ;DMA channel 3 transfer complete
|
||||
DCD Reserved20_IRQHandler ;Reserved interrupt
|
||||
DCD FTFA_IRQHandler ;Command complete and read collision
|
||||
DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning
|
||||
DCD LLWU_IRQHandler ;Low leakage wakeup
|
||||
DCD I2C0_IRQHandler ;I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ;I2C1 interrupt
|
||||
DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources
|
||||
DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources
|
||||
DCD LPUART0_IRQHandler ;LPUART0 status and error
|
||||
DCD LPUART1_IRQHandler ;LPUART1 status and error
|
||||
DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO
|
||||
DCD ADC0_IRQHandler ;ADC0 interrupt
|
||||
DCD CMP0_IRQHandler ;CMP0 interrupt
|
||||
DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources
|
||||
DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
|
||||
DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
|
||||
DCD RTC_IRQHandler ;RTC alarm
|
||||
DCD RTC_Seconds_IRQHandler ;RTC seconds
|
||||
DCD PIT_IRQHandler ;PIT interrupt
|
||||
DCD I2S0_IRQHandler ;I2S0 interrupt
|
||||
DCD USB0_IRQHandler ;USB0 interrupt
|
||||
DCD DAC0_IRQHandler ;DAC0 interrupt
|
||||
DCD Reserved42_IRQHandler ;Reserved interrupt
|
||||
DCD Reserved43_IRQHandler ;Reserved interrupt
|
||||
DCD LPTMR0_IRQHandler ;LPTMR0 interrupt
|
||||
DCD LCD_IRQHandler ;LCD interrupt
|
||||
DCD PORTA_IRQHandler ;PORTA Pin detect
|
||||
DCD PORTCD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
; <h> Flash Configuration
|
||||
; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
|
||||
; <i> and security information that allows the MCU to restrict access to the FTFL module.
|
||||
; <h> Backdoor Comparison Key
|
||||
; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
|
||||
; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
|
||||
; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
|
||||
; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
|
||||
; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
|
||||
; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
|
||||
; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
|
||||
; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
|
||||
BackDoorK0 EQU 0xFF
|
||||
BackDoorK1 EQU 0xFF
|
||||
BackDoorK2 EQU 0xFF
|
||||
BackDoorK3 EQU 0xFF
|
||||
BackDoorK4 EQU 0xFF
|
||||
BackDoorK5 EQU 0xFF
|
||||
BackDoorK6 EQU 0xFF
|
||||
BackDoorK7 EQU 0xFF
|
||||
; </h>
|
||||
; <h> Program flash protection bytes (FPROT)
|
||||
; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
|
||||
; <i> Each bit protects a 1/32 region of the program flash memory.
|
||||
; <h> FPROT0
|
||||
; <i> Program Flash Region Protect Register 0
|
||||
; <i> 1/32 - 8/32 region
|
||||
; <o.0> FPROT0.0
|
||||
; <o.1> FPROT0.1
|
||||
; <o.2> FPROT0.2
|
||||
; <o.3> FPROT0.3
|
||||
; <o.4> FPROT0.4
|
||||
; <o.5> FPROT0.5
|
||||
; <o.6> FPROT0.6
|
||||
; <o.7> FPROT0.7
|
||||
nFPROT0 EQU 0x00
|
||||
FPROT0 EQU nFPROT0:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT1
|
||||
; <i> Program Flash Region Protect Register 1
|
||||
; <i> 9/32 - 16/32 region
|
||||
; <o.0> FPROT1.0
|
||||
; <o.1> FPROT1.1
|
||||
; <o.2> FPROT1.2
|
||||
; <o.3> FPROT1.3
|
||||
; <o.4> FPROT1.4
|
||||
; <o.5> FPROT1.5
|
||||
; <o.6> FPROT1.6
|
||||
; <o.7> FPROT1.7
|
||||
nFPROT1 EQU 0x00
|
||||
FPROT1 EQU nFPROT1:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT2
|
||||
; <i> Program Flash Region Protect Register 2
|
||||
; <i> 17/32 - 24/32 region
|
||||
; <o.0> FPROT2.0
|
||||
; <o.1> FPROT2.1
|
||||
; <o.2> FPROT2.2
|
||||
; <o.3> FPROT2.3
|
||||
; <o.4> FPROT2.4
|
||||
; <o.5> FPROT2.5
|
||||
; <o.6> FPROT2.6
|
||||
; <o.7> FPROT2.7
|
||||
nFPROT2 EQU 0x00
|
||||
FPROT2 EQU nFPROT2:EOR:0xFF
|
||||
; </h>
|
||||
; <h> FPROT3
|
||||
; <i> Program Flash Region Protect Register 3
|
||||
; <i> 25/32 - 32/32 region
|
||||
; <o.0> FPROT3.0
|
||||
; <o.1> FPROT3.1
|
||||
; <o.2> FPROT3.2
|
||||
; <o.3> FPROT3.3
|
||||
; <o.4> FPROT3.4
|
||||
; <o.5> FPROT3.5
|
||||
; <o.6> FPROT3.6
|
||||
; <o.7> FPROT3.7
|
||||
nFPROT3 EQU 0x00
|
||||
FPROT3 EQU nFPROT3:EOR:0xFF
|
||||
; </h>
|
||||
; </h>
|
||||
; <h> Flash nonvolatile option byte (FOPT)
|
||||
; <i> Allows the user to customize the operation of the MCU at boot time.
|
||||
; <o.0> LPBOOT0
|
||||
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
|
||||
; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
|
||||
; <o.1> BOOTPIN_OPT
|
||||
; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
|
||||
; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
|
||||
; <o.2> NMI_DIS
|
||||
; <0=> NMI interrupts are always blocked
|
||||
; <1=> NMI_b pin/interrupts reset default to enabled
|
||||
; <o.3> RESET_PIN_CFG
|
||||
; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function
|
||||
; <1=> RESET_b pin is dedicated
|
||||
; <o.4> LPBOOT1
|
||||
; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
|
||||
; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
|
||||
; <o.5> FAST_INIT
|
||||
; <0=> Slower initialization
|
||||
; <1=> Fast Initialization
|
||||
; <o.6..7> BOOTSRC_SEL
|
||||
; <0=> Boot from Flash
|
||||
; <2=> Boot from ROM
|
||||
; <3=> Boot from ROM
|
||||
; <i> Boot source selection
|
||||
FOPT EQU 0x3F
|
||||
; </h>
|
||||
; <h> Flash security byte (FSEC)
|
||||
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
||||
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
||||
; <o.0..1> SEC
|
||||
; <2=> MCU security status is unsecure
|
||||
; <3=> MCU security status is secure
|
||||
; <i> Flash Security
|
||||
; <o.2..3> FSLACC
|
||||
; <2=> Freescale factory access denied
|
||||
; <3=> Freescale factory access granted
|
||||
; <i> Freescale Failure Analysis Access Code
|
||||
; <o.4..5> MEEN
|
||||
; <2=> Mass erase is disabled
|
||||
; <3=> Mass erase is enabled
|
||||
; <o.6..7> KEYEN
|
||||
; <2=> Backdoor key access enabled
|
||||
; <3=> Backdoor key access disabled
|
||||
; <i> Backdoor Key Security Enable
|
||||
FSEC EQU 0xFE
|
||||
; </h>
|
||||
; </h>
|
||||
IF :LNOT::DEF:RAM_TARGET
|
||||
AREA |.ARM.__at_0x400|, DATA, READONLY
|
||||
__FlashConfig
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
|
||||
DCB FSEC , FOPT , 0xFF , 0xFF
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
Default_Handler\
|
||||
PROC
|
||||
EXPORT DMA0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_IRQHandler [WEAK]
|
||||
EXPORT DMA3_IRQHandler [WEAK]
|
||||
EXPORT Reserved20_IRQHandler [WEAK]
|
||||
EXPORT FTFA_IRQHandler [WEAK]
|
||||
EXPORT PMC_IRQHandler [WEAK]
|
||||
EXPORT LLWU_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT LPUART0_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_FLEXIO_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT CMP0_IRQHandler [WEAK]
|
||||
EXPORT TPM0_IRQHandler [WEAK]
|
||||
EXPORT TPM1_IRQHandler [WEAK]
|
||||
EXPORT TPM2_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT RTC_Seconds_IRQHandler [WEAK]
|
||||
EXPORT PIT_IRQHandler [WEAK]
|
||||
EXPORT I2S0_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT DAC0_IRQHandler [WEAK]
|
||||
EXPORT Reserved42_IRQHandler [WEAK]
|
||||
EXPORT Reserved43_IRQHandler [WEAK]
|
||||
EXPORT LPTMR0_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT PORTA_IRQHandler [WEAK]
|
||||
EXPORT PORTCD_IRQHandler [WEAK]
|
||||
EXPORT DefaultISR [WEAK]
|
||||
DMA0_IRQHandler
|
||||
DMA1_IRQHandler
|
||||
DMA2_IRQHandler
|
||||
DMA3_IRQHandler
|
||||
Reserved20_IRQHandler
|
||||
FTFA_IRQHandler
|
||||
PMC_IRQHandler
|
||||
LLWU_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
LPUART0_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
UART2_FLEXIO_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
CMP0_IRQHandler
|
||||
TPM0_IRQHandler
|
||||
TPM1_IRQHandler
|
||||
TPM2_IRQHandler
|
||||
RTC_IRQHandler
|
||||
RTC_Seconds_IRQHandler
|
||||
PIT_IRQHandler
|
||||
I2S0_IRQHandler
|
||||
USB0_IRQHandler
|
||||
DAC0_IRQHandler
|
||||
Reserved42_IRQHandler
|
||||
Reserved43_IRQHandler
|
||||
LPTMR0_IRQHandler
|
||||
LCD_IRQHandler
|
||||
PORTA_IRQHandler
|
||||
PORTCD_IRQHandler
|
||||
DefaultISR
|
||||
B .
|
||||
ENDP
|
||||
ALIGN
|
||||
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <rt_misc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
extern char Image$$RW_IRAM1$$ZI$$Limit[];
|
||||
|
||||
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
|
||||
uint32_t sp_limit = __current_sp();
|
||||
|
||||
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
|
||||
|
||||
struct __initial_stackheap r;
|
||||
r.heap_base = zi_limit;
|
||||
r.heap_limit = sp_limit;
|
||||
return r;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* KL43Z ARM GCC linker script file
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
|
||||
FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
|
||||
FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410
|
||||
RAM (rwx) : ORIGIN = 0x1FFFE0C0, LENGTH = 32K - 0xC0
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* _reset_init : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.isr_vector :
|
||||
{
|
||||
__vector_table = .;
|
||||
KEEP(*(.vector_table))
|
||||
*(.text.Reset_Handler)
|
||||
*(.text.System_Init)
|
||||
. = ALIGN(4);
|
||||
} > VECTORS
|
||||
|
||||
.flash_protect :
|
||||
{
|
||||
KEEP(*(.kinetis_flash_config_field))
|
||||
. = ALIGN(4);
|
||||
} > FLASH_PROTECTION
|
||||
|
||||
.text :
|
||||
{
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap :
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy :
|
||||
{
|
||||
*(.stack)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
/* KL43Z startup ARM GCC
|
||||
* Purpose: startup file for Cortex-M0 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V1.3
|
||||
* Date: 10 Nov 2014
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
* Neither the name of the ARM Limited nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
.syntax unified
|
||||
.arch armv6-m
|
||||
|
||||
/* Memory Model
|
||||
The HEAP starts at the end of the DATA section and grows upward.
|
||||
|
||||
The STACK starts at the end of the RAM and grows downward.
|
||||
|
||||
The HEAP and stack STACK are only checked at compile time:
|
||||
(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
|
||||
|
||||
This is just a check for the bare minimum for the Heap+Stack area before
|
||||
aborting compilation, it is not the run time limit:
|
||||
Heap_Size + Stack_Size = 0x200 + 0x400 = 0x600
|
||||
*/
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x400
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x200
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.space Heap_Size
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vector_table,"a",%progbits
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
|
||||
.long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
|
||||
.long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
|
||||
.long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
|
||||
.long Default_Handler /* Reserved interrupt 20 */
|
||||
.long FTFA_IRQHandler /* FTFA interrupt */
|
||||
.long PMC_IRQHandler /* Low-voltage detect, low-voltage warning*/
|
||||
.long LLWU_IRQHandler /* Low leakage wakeup*/
|
||||
.long I2C0_IRQHandler /* I2C0 interrupt*/
|
||||
.long I2C1_IRQHandler /* I2C1 interrupt*/
|
||||
.long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/
|
||||
.long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/
|
||||
.long LPUART0_IRQHandler /* LPUART0 status and error*/
|
||||
.long LPUART1_IRQHandler /* LPUART1 status and error*/
|
||||
.long UART2_FLEXIO_IRQHandler /* UART2 or FLEXIO*/
|
||||
.long ADC0_IRQHandler /* ADC0 interrupt*/
|
||||
.long CMP0_IRQHandler /* CMP0 interrupt*/
|
||||
.long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/
|
||||
.long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
|
||||
.long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
|
||||
.long RTC_IRQHandler /* RTC alarm*/
|
||||
.long RTC_Seconds_IRQHandler /* RTC seconds*/
|
||||
.long PIT_IRQHandler /* PIT interrupt*/
|
||||
.long I2S0_IRQHandler /* I2S0 interrupt*/
|
||||
.long USB0_IRQHandler /* USB0 interrupt*/
|
||||
.long DAC0_IRQHandler /* DAC0 interrupt*/
|
||||
.long Reserved42_IRQHandler /* Reserved interrupt*/
|
||||
.long Reserved43_IRQHandler /* Reserved interrupt*/
|
||||
.long LPTMR0_IRQHandler /* LPTMR0 interrupt*/
|
||||
.long LCD_IRQHandler /* LCD interrupt*/
|
||||
.long PORTA_IRQHandler /* PORTA Pin detect*/
|
||||
.long PORTCD_IRQHandler /* Single interrupt vector for PORTC; PORTD Pin detect*/
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
/* Reset Handler */
|
||||
.section .text.Reset_Handler
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Loop to copy data from read only memory to RAM. The ranges
|
||||
* of copy from/to are specified by following symbols evaluated in
|
||||
* linker script.
|
||||
* __etext: End of code section, i.e., begin of data sections to copy from.
|
||||
* __data_start__/__data_end__: RAM address range that data should be
|
||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
subs r3, r2
|
||||
ble .Lflash_to_ram_loop_end
|
||||
|
||||
movs r4, 0
|
||||
.Lflash_to_ram_loop:
|
||||
ldr r0, [r1,r4]
|
||||
str r0, [r2,r4]
|
||||
adds r4, 4
|
||||
cmp r4, r3
|
||||
blt .Lflash_to_ram_loop
|
||||
.Lflash_to_ram_loop_end:
|
||||
|
||||
ldr r0, =SystemInit
|
||||
blx r0
|
||||
ldr r0, =_start
|
||||
bx r0
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
|
||||
.text
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_default_handler handler_name
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak \handler_name
|
||||
.type \handler_name, %function
|
||||
\handler_name :
|
||||
b .
|
||||
.size \handler_name, . - \handler_name
|
||||
.endm
|
||||
|
||||
def_default_handler NMI_Handler
|
||||
def_default_handler HardFault_Handler
|
||||
def_default_handler SVC_Handler
|
||||
def_default_handler PendSV_Handler
|
||||
def_default_handler SysTick_Handler
|
||||
def_default_handler Default_Handler
|
||||
|
||||
.macro def_irq_default_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_default_handler DMA0_IRQHandler
|
||||
def_irq_default_handler DMA1_IRQHandler
|
||||
def_irq_default_handler DMA2_IRQHandler
|
||||
def_irq_default_handler DMA3_IRQHandler
|
||||
def_irq_default_handler Reserved20_IRQHandler
|
||||
def_irq_default_handler FTFA_IRQHandler
|
||||
def_irq_default_handler PMC_IRQHandler
|
||||
def_irq_default_handler LLWU_IRQHandler
|
||||
def_irq_default_handler I2C0_IRQHandler
|
||||
def_irq_default_handler I2C1_IRQHandler
|
||||
def_irq_default_handler SPI0_IRQHandler
|
||||
def_irq_default_handler SPI1_IRQHandler
|
||||
def_irq_default_handler LPUART0_IRQHandler
|
||||
def_irq_default_handler LPUART1_IRQHandler
|
||||
def_irq_default_handler UART2_FLEXIO_IRQHandler
|
||||
def_irq_default_handler ADC0_IRQHandler
|
||||
def_irq_default_handler CMP0_IRQHandler
|
||||
def_irq_default_handler TPM0_IRQHandler
|
||||
def_irq_default_handler TPM1_IRQHandler
|
||||
def_irq_default_handler TPM2_IRQHandler
|
||||
def_irq_default_handler RTC_IRQHandler
|
||||
def_irq_default_handler RTC_Seconds_IRQHandler
|
||||
def_irq_default_handler PIT_IRQHandler
|
||||
def_irq_default_handler I2S0_IRQHandler
|
||||
def_irq_default_handler USB0_IRQHandler
|
||||
def_irq_default_handler DAC0_IRQHandler
|
||||
def_irq_default_handler Reserved42_IRQHandler
|
||||
def_irq_default_handler Reserved43_IRQHandler
|
||||
def_irq_default_handler LPTMR0_IRQHandler
|
||||
def_irq_default_handler LCD_IRQHandler
|
||||
def_irq_default_handler PORTA_IRQHandler
|
||||
def_irq_default_handler PORTCD_IRQHandler
|
||||
def_irq_default_handler DefaultISR
|
||||
|
||||
/* Flash protection region, placed at 0x400 */
|
||||
.text
|
||||
.thumb
|
||||
.align 2
|
||||
.section .kinetis_flash_config_field,"a",%progbits
|
||||
kinetis_flash_config:
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFFFFFF
|
||||
.long 0xFFFF3FFE
|
||||
|
||||
.end
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/* mbed Microcontroller Library - stackheap
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* Setup a fixed single stack/heap memory model,
|
||||
* between the top of the RW/ZI region and the stackpointer
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <errno.h>
|
||||
|
||||
extern void exit(int return_code);
|
||||
|
||||
int _kill(int pid, int sig) {
|
||||
errno = EINVAL;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _exit(int status) {
|
||||
exit(status);
|
||||
}
|
||||
|
||||
int _getpid(void) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/* mbed Microcontroller Library - CMSIS
|
||||
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* A generic CMSIS include header, pulling in LPC11U24 specifics
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "MKL43Z4.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
|
||||
* Copyright (c) 2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*/
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
uint32_t i;
|
||||
|
||||
// Copy and switch to dynamic vectors if the first time called
|
||||
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
|
||||
uint32_t *old_vectors = vectors;
|
||||
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
|
||||
for (i=0; i<NVIC_NUM_VECTORS; i++) {
|
||||
vectors[i] = old_vectors[i];
|
||||
}
|
||||
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
|
||||
}
|
||||
vectors[IRQn + 16] = vector;
|
||||
}
|
||||
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
|
||||
uint32_t *vectors = (uint32_t*)SCB->VTOR;
|
||||
return vectors[IRQn + 16];
|
||||
}
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* mbed Microcontroller Library - cmsis_nvic
|
||||
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
|
||||
*
|
||||
* CMSIS-style functionality to support dynamic vectors
|
||||
*/
|
||||
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MKL43Z256VLH4
|
||||
** MKL43Z128VLH4
|
||||
** MKL43Z64VLH4
|
||||
** MKL43Z256VMP4
|
||||
** MKL43Z128VMP4
|
||||
** MKL43Z64VMP4
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** GNU C Compiler - CodeSourcery Sourcery G++
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
|
||||
** Version: rev. 1.4, 2014-09-01
|
||||
** Build: b140904
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2014-03-27)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2014-05-26)
|
||||
** I2S registers TCR2/RCR2 and others were changed.
|
||||
** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
|
||||
** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
|
||||
** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
|
||||
** Clock configuration for high range external oscillator has been added.
|
||||
** RFSYS module access has been added.
|
||||
** - rev. 1.2 (2014-07-10)
|
||||
** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
|
||||
** UART0 - UART0 module renamed to UART2.
|
||||
** I2S - removed MDR register.
|
||||
** - rev. 1.3 (2014-08-21)
|
||||
** UART2 - Removed ED register.
|
||||
** UART2 - Removed MODEM register.
|
||||
** UART2 - Removed IR register.
|
||||
** UART2 - Removed PFIFO register.
|
||||
** UART2 - Removed CFIFO register.
|
||||
** UART2 - Removed SFIFO register.
|
||||
** UART2 - Removed TWFIFO register.
|
||||
** UART2 - Removed TCFIFO register.
|
||||
** UART2 - Removed RWFIFO register.
|
||||
** UART2 - Removed RCFIFO register.
|
||||
** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
|
||||
** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
|
||||
** SIM - Removed bitfield DIEID in SDID register.
|
||||
** - rev. 1.4 (2014-09-01)
|
||||
** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
|
||||
** USB - USB0_CTL1 was renamed to USB0_CTL register.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MKL43Z4
|
||||
* @version 1.4
|
||||
* @date 2014-09-01
|
||||
* @brief Device specific configuration file for MKL43Z4 (implementation file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "MKL43Z4.h"
|
||||
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- Core clock
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemInit()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemInit (void) {
|
||||
|
||||
#if (ACK_ISOLATION)
|
||||
if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) {
|
||||
PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (DISABLE_WDOG)
|
||||
/* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
|
||||
SIM->COPC = (uint32_t)0x00u;
|
||||
#endif /* (DISABLE_WDOG) */
|
||||
|
||||
/* Power mode protection initialization */
|
||||
#ifdef SMC_PMPROT_VALUE
|
||||
SMC->PMPROT = SMC_PMPROT_VALUE;
|
||||
#endif
|
||||
|
||||
/* System clock initialization */
|
||||
|
||||
/* Set system prescalers and clock sources */
|
||||
SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
|
||||
SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
|
||||
#define SOPT2_WRITE_MASK ((SIM_SOPT2_USBSRC_MASK) | (SIM_SOPT2_TPMSRC_MASK) | (SIM_SOPT2_LPUART0SRC_MASK) | (SIM_SOPT2_LPUART1SRC_MASK)) /* define mask of written bits. */
|
||||
SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~SOPT2_WRITE_MASK)) | ((SYSTEM_SIM_SOPT2_VALUE) & SOPT2_WRITE_MASK); /* Selects the clock source for the TPM counter clock. */
|
||||
#if (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M || MCG_MODE == MCG_MODE_HIRC)
|
||||
/* Set MCG and OSC0 */
|
||||
#if (((OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U)
|
||||
/* SIM_SCGC5: PORTA=1 */
|
||||
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
|
||||
/* PORTA_PCR3: ISF=0,MUX=0 */
|
||||
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
|
||||
if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
|
||||
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
|
||||
}
|
||||
#endif
|
||||
MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */
|
||||
MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */
|
||||
MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */
|
||||
MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */
|
||||
OSC0->CR = OSC0_CR_VALUE; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
|
||||
|
||||
#else /* MCG_MODE */
|
||||
/* Set MCG and OSC0 */
|
||||
/* SIM_SCGC5: PORTA=1 */
|
||||
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
|
||||
/* PORTA_PCR3: ISF=0,MUX=0 */
|
||||
PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
|
||||
if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
|
||||
PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
|
||||
}
|
||||
MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */
|
||||
MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */
|
||||
OSC0->CR = OSC0_CR_VALUE; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
|
||||
MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */
|
||||
MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */
|
||||
if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0U) {
|
||||
while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
|
||||
}
|
||||
}
|
||||
#endif /* MCG_MODE */
|
||||
|
||||
/* Common for all MCG modes */
|
||||
|
||||
#if (MCG_MODE == MCG_MODE_HIRC)
|
||||
while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until high internal reference clock is selected as MCG_Lite output */
|
||||
}
|
||||
#elif (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M)
|
||||
while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until low internal reference clock is selected as MCG_Lite output */
|
||||
}
|
||||
#elif (MCG_MODE == MCG_MODE_EXT)
|
||||
while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG_Lite output */
|
||||
}
|
||||
#endif
|
||||
if (((SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == SMC_PMCTRL_RUNM(0x02U)) {
|
||||
SMC->PMCTRL = (uint8_t)((SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
|
||||
while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SystemCoreClockUpdate()
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
void SystemCoreClockUpdate (void) {
|
||||
|
||||
uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
|
||||
uint16_t Divider;
|
||||
|
||||
if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
|
||||
/* High internal reference clock is selected */
|
||||
MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
|
||||
} else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
|
||||
/* Internal reference clock is selected */
|
||||
Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
|
||||
MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */
|
||||
} else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
|
||||
/* External reference clock is selected */
|
||||
MCGOUTClock = CPU_XTAL_CLK_HZ;
|
||||
} else {
|
||||
/* Reserved value */
|
||||
return;
|
||||
} /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
|
||||
SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,335 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Processors: MKL43Z256VLH4
|
||||
** MKL43Z128VLH4
|
||||
** MKL43Z64VLH4
|
||||
** MKL43Z256VMP4
|
||||
** MKL43Z128VMP4
|
||||
** MKL43Z64VMP4
|
||||
**
|
||||
** Compilers: Keil ARM C/C++ Compiler
|
||||
** Freescale C/C++ for Embedded ARM
|
||||
** GNU C Compiler
|
||||
** GNU C Compiler - CodeSourcery Sourcery G++
|
||||
** IAR ANSI C/C++ Compiler for ARM
|
||||
**
|
||||
** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
|
||||
** Version: rev. 1.4, 2014-09-01
|
||||
** Build: b140904
|
||||
**
|
||||
** Abstract:
|
||||
** Provides a system configuration function and a global variable that
|
||||
** contains the system frequency. It configures the device and initializes
|
||||
** the oscillator (PLL) that is part of the microcontroller device.
|
||||
**
|
||||
** Copyright (c) 2014 Freescale Semiconductor, Inc.
|
||||
** All rights reserved.
|
||||
**
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.freescale.com
|
||||
** mail: support@freescale.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2014-03-27)
|
||||
** Initial version.
|
||||
** - rev. 1.1 (2014-05-26)
|
||||
** I2S registers TCR2/RCR2 and others were changed.
|
||||
** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
|
||||
** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
|
||||
** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
|
||||
** Clock configuration for high range external oscillator has been added.
|
||||
** RFSYS module access has been added.
|
||||
** - rev. 1.2 (2014-07-10)
|
||||
** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
|
||||
** UART0 - UART0 module renamed to UART2.
|
||||
** I2S - removed MDR register.
|
||||
** - rev. 1.3 (2014-08-21)
|
||||
** UART2 - Removed ED register.
|
||||
** UART2 - Removed MODEM register.
|
||||
** UART2 - Removed IR register.
|
||||
** UART2 - Removed PFIFO register.
|
||||
** UART2 - Removed CFIFO register.
|
||||
** UART2 - Removed SFIFO register.
|
||||
** UART2 - Removed TWFIFO register.
|
||||
** UART2 - Removed TCFIFO register.
|
||||
** UART2 - Removed RWFIFO register.
|
||||
** UART2 - Removed RCFIFO register.
|
||||
** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
|
||||
** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
|
||||
** SIM - Removed bitfield DIEID in SDID register.
|
||||
** - rev. 1.4 (2014-09-01)
|
||||
** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
|
||||
** USB - USB0_CTL1 was renamed to USB0_CTL register.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @file MKL43Z4
|
||||
* @version 1.4
|
||||
* @date 2014-09-01
|
||||
* @brief Device specific configuration file for MKL43Z4 (header file)
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_MKL43Z4_H_
|
||||
#define SYSTEM_MKL43Z4_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#ifndef DISABLE_WDOG
|
||||
#define DISABLE_WDOG 1
|
||||
#endif
|
||||
|
||||
#define ACK_ISOLATION 1
|
||||
|
||||
#ifndef CLOCK_SETUP
|
||||
#define CLOCK_SETUP 1
|
||||
#endif
|
||||
|
||||
/* MCG_Lite mode constants */
|
||||
|
||||
#define MCG_MODE_LIRC_8M 0U
|
||||
#define MCG_MODE_HIRC 1U
|
||||
#define MCG_MODE_LIRC_2M 2U
|
||||
#define MCG_MODE_EXT 3U
|
||||
|
||||
/* Predefined clock setups
|
||||
0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
|
||||
Default part configuration.
|
||||
Core clock/Bus clock derived from the internal clock source 8 MHz
|
||||
Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
|
||||
1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
|
||||
Maximum achievable clock frequency configuration using internal clock.
|
||||
Core clock/Bus clock derived from the internal clock source 48MHz
|
||||
Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
|
||||
2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
|
||||
Core clock/Bus clock derived directly from the external crystal 32.768kHz
|
||||
The clock settings is ready for Very Low Power Run mode.
|
||||
Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
|
||||
3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
|
||||
Core clock/Bus clock derived from the internal clock source 2 MHz
|
||||
The clock settings is ready for Very Low Power Run mode.
|
||||
Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
|
||||
4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
|
||||
USB clock setup - for USB to receive internal 48MHz clock derived from HIRC.
|
||||
Core clock/Bus clock derived from the internal clock source 48MHz
|
||||
Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK)
|
||||
5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
|
||||
Core clock/Bus clock derived directly from the external crystal 8 MHz
|
||||
Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
|
||||
*/
|
||||
|
||||
/* Define clock source values */
|
||||
|
||||
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
|
||||
#define CPU_INT_FAST_CLK_HZ 48000000u /* Value of the fast internal oscillator clock frequency in Hz */
|
||||
#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
|
||||
|
||||
/* Low power mode enable */
|
||||
/* SMC_PMPROT: AVLP=1,AVLLS=1 */
|
||||
#define SMC_PMPROT_VALUE 0x22u /* SMC_PMPROT */
|
||||
|
||||
#if (CLOCK_SETUP == 0)
|
||||
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
|
||||
#define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define MCG_MODE MCG_MODE_LIRC_8M /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define MCG_C1_VALUE 0x42u /* MCG_C1 */
|
||||
/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
|
||||
#define MCG_C2_VALUE 0x01u /* MCG_C2 */
|
||||
/* MCG_SC: FCRDIV=0 */
|
||||
#define MCG_SC_VALUE 0x00u /* MCG_SC */
|
||||
/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
|
||||
#define MCG_MC_VALUE 0x00u /* MCG_MC */
|
||||
/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define OSC0_CR_VALUE 0x00u /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
|
||||
#elif (CLOCK_SETUP == 1)
|
||||
#define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
|
||||
#define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define MCG_MODE MCG_MODE_HIRC /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
|
||||
#define MCG_C1_VALUE 0x00u /* MCG_C1 */
|
||||
/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
|
||||
#define MCG_C2_VALUE 0x01u /* MCG_C2 */
|
||||
/* MCG_SC: FCRDIV=0 */
|
||||
#define MCG_SC_VALUE 0x00u /* MCG_SC */
|
||||
/* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
|
||||
#define MCG_MC_VALUE 0x80u /* MCG_MC */
|
||||
/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define OSC0_CR_VALUE 0x00u /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x03000000U /* SIM_SOPT2 */
|
||||
#elif (CLOCK_SETUP == 2)
|
||||
#define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
|
||||
#define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define MCG_MODE MCG_MODE_EXT /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define MCG_C1_VALUE 0x82u /* MCG_C1 */
|
||||
/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
|
||||
#define MCG_C2_VALUE 0x05u /* MCG_C2 */
|
||||
/* MCG_SC: FCRDIV=0 */
|
||||
#define MCG_SC_VALUE 0x00u /* MCG_SC */
|
||||
/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
|
||||
#define MCG_MC_VALUE 0x00u /* MCG_MC */
|
||||
/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define OSC0_CR_VALUE 0x80u /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x00u /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x02000000u /* SIM_SOPT2 */
|
||||
#elif (CLOCK_SETUP == 3)
|
||||
#define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
|
||||
#define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define MCG_C1_VALUE 0x42u /* MCG_C1 */
|
||||
/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
|
||||
#define MCG_C2_VALUE 0x00u /* MCG_C2 */
|
||||
/* MCG_SC: FCRDIV=0 */
|
||||
#define MCG_SC_VALUE 0x00u /* MCG_SC */
|
||||
/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
|
||||
#define MCG_MC_VALUE 0x00u /* MCG_MC */
|
||||
/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define OSC0_CR_VALUE 0x00u /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
|
||||
#elif (CLOCK_SETUP == 4)
|
||||
#define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
|
||||
#define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
|
||||
#define MCG_C1_VALUE 0x02u /* MCG_C1 */
|
||||
/* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
|
||||
#define MCG_C2_VALUE 0x01u /* MCG_C2 */
|
||||
/* MCG_SC: FCRDIV=0 */
|
||||
#define MCG_SC_VALUE 0x00u /* MCG_SC */
|
||||
/* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
|
||||
#define MCG_MC_VALUE 0x80u /* MCG_MC */
|
||||
/* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define OSC0_CR_VALUE 0x00u /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x03040000u /* SIM_SOPT2 */
|
||||
#elif (CLOCK_SETUP == 5)
|
||||
#define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
|
||||
#define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
|
||||
#define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
|
||||
/* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */
|
||||
#define MCG_C1_VALUE 0x80u /* MCG_C1 */
|
||||
/* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
|
||||
#define MCG_C2_VALUE 0x15u /* MCG_C2 */
|
||||
/* MCG_SC: FCRDIV=0 */
|
||||
#define MCG_SC_VALUE 0x00u /* MCG_SC */
|
||||
/* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
|
||||
#define MCG_MC_VALUE 0x00u /* MCG_MC */
|
||||
/* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
|
||||
#define OSC0_CR_VALUE 0x80u /* OSC0_CR */
|
||||
/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
|
||||
#define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
|
||||
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
|
||||
#define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
|
||||
/* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
|
||||
#define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
|
||||
/* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
|
||||
#define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
|
||||
#else
|
||||
#error The selected clock setup is not supported.
|
||||
#endif /* (CLOCK_SETUP == 5) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* #if !defined(SYSTEM_MKL43Z4_H_) */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* [ROM = 512kb = 0x80000] */
|
||||
define symbol __intvec_start__ = 0x08000000;
|
||||
define symbol __region_ROM_start__ = 0x08000000;
|
||||
define symbol __region_ROM_end__ = 0x0807FFFF;
|
||||
|
||||
/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
|
||||
define symbol __NVIC_start__ = 0x20000000;
|
||||
define symbol __NVIC_end__ = 0x20000197; /* Aligned on 8 bytes */
|
||||
define symbol __region_RAM_start__ = 0x20000198;
|
||||
define symbol __region_RAM_end__ = 0x2001FFFF;
|
||||
|
||||
/* Memory regions */
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
|
||||
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
|
||||
|
||||
/* Stack and Heap */
|
||||
define symbol __size_cstack__ = 0x400;
|
||||
define symbol __size_heap__ = 0x400;
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
|
||||
|
||||
initialize by copy with packing = zeros { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, block STACKHEAP };
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x200;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,295 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "serial_api.h"
|
||||
|
||||
// math.h required for floating point operations for baud rate calculation
|
||||
#include <math.h>
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "clk_freqs.h"
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
//Devices either user UART0 or UARTLP
|
||||
#ifndef UARTLP_BASES
|
||||
#define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
|
||||
#define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
|
||||
#define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
|
||||
#define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
|
||||
#define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
|
||||
#define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
|
||||
#define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
|
||||
#define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
|
||||
#define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
|
||||
#define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
|
||||
#endif
|
||||
|
||||
#ifdef UART2
|
||||
#define UART_NUM 3
|
||||
#else
|
||||
#define UART_NUM 1
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
* INITIALIZATION
|
||||
******************************************************************************/
|
||||
|
||||
static uint32_t serial_irq_ids[UART_NUM] = {0};
|
||||
static uart_irq_handler irq_handler;
|
||||
|
||||
int stdio_uart_inited = 0;
|
||||
serial_t stdio_uart;
|
||||
|
||||
void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
||||
// determine the UART to use
|
||||
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
|
||||
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
|
||||
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
|
||||
MBED_ASSERT((int)uart != NC);
|
||||
|
||||
obj->uart = (UARTLP_Type *)uart;
|
||||
// enable clk
|
||||
switch (uart) {
|
||||
case UART_0: if (mcgpllfll_frequency() != 0) //PLL/FLL is selected
|
||||
SIM->SOPT2 |= (1<<SIM_SOPT2_UART0SRC_SHIFT);
|
||||
else
|
||||
SIM->SOPT2 |= (2<<SIM_SOPT2_UART0SRC_SHIFT);
|
||||
SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break;
|
||||
#if UART_NUM > 1
|
||||
case UART_1: SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break;
|
||||
case UART_2: SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break;
|
||||
#endif
|
||||
}
|
||||
// Disable UART before changing registers
|
||||
obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
|
||||
|
||||
switch (uart) {
|
||||
case UART_0: obj->index = 0; break;
|
||||
#if UART_NUM > 1
|
||||
case UART_1: obj->index = 1; break;
|
||||
case UART_2: obj->index = 2; break;
|
||||
#endif
|
||||
}
|
||||
|
||||
// set default baud rate and format
|
||||
serial_baud (obj, 9600);
|
||||
serial_format(obj, 8, ParityNone, 1);
|
||||
|
||||
// pinout the chosen uart
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
pinmap_pinout(rx, PinMap_UART_RX);
|
||||
|
||||
// set rx/tx pins in PullUp mode
|
||||
if (tx != NC) {
|
||||
pin_mode(tx, PullUp);
|
||||
}
|
||||
if (rx != NC) {
|
||||
pin_mode(rx, PullUp);
|
||||
}
|
||||
|
||||
obj->uart->C2 |= (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
|
||||
|
||||
if (uart == STDIO_UART) {
|
||||
stdio_uart_inited = 1;
|
||||
memcpy(&stdio_uart, obj, sizeof(serial_t));
|
||||
}
|
||||
}
|
||||
|
||||
void serial_free(serial_t *obj) {
|
||||
serial_irq_ids[obj->index] = 0;
|
||||
}
|
||||
|
||||
// serial_baud
|
||||
//
|
||||
// set the baud rate, taking in to account the current SystemFrequency
|
||||
void serial_baud(serial_t *obj, int baudrate) {
|
||||
|
||||
// save C2 state
|
||||
uint8_t c2_state = (obj->uart->C2 & (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK));
|
||||
|
||||
// Disable UART before changing registers
|
||||
obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
|
||||
|
||||
uint32_t PCLK;
|
||||
if (obj->uart == UART0) {
|
||||
if (mcgpllfll_frequency() != 0)
|
||||
PCLK = mcgpllfll_frequency();
|
||||
else
|
||||
PCLK = extosc_frequency();
|
||||
} else
|
||||
PCLK = bus_frequency();
|
||||
|
||||
// First we check to see if the basic divide with no DivAddVal/MulVal
|
||||
// ratio gives us an integer result. If it does, we set DivAddVal = 0,
|
||||
// MulVal = 1. Otherwise, we search the valid ratio value range to find
|
||||
// the closest match. This could be more elegant, using search methods
|
||||
// and/or lookup tables, but the brute force method is not that much
|
||||
// slower, and is more maintainable.
|
||||
uint16_t DL = PCLK / (16 * baudrate);
|
||||
|
||||
// set BDH and BDL
|
||||
obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f);
|
||||
obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff);
|
||||
|
||||
// restore C2 state
|
||||
obj->uart->C2 |= c2_state;
|
||||
}
|
||||
|
||||
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
|
||||
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
|
||||
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
|
||||
MBED_ASSERT(data_bits == 8); // TODO: Support other number of data bits (also in the write method!)
|
||||
|
||||
// save C2 state
|
||||
uint8_t c2_state = (obj->uart->C2 & (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK));
|
||||
|
||||
// Disable UART before changing registers
|
||||
obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
|
||||
|
||||
|
||||
uint8_t parity_enable, parity_select;
|
||||
switch (parity) {
|
||||
case ParityNone: parity_enable = 0; parity_select = 0; break;
|
||||
case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break;
|
||||
case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
stop_bits -= 1;
|
||||
|
||||
// data bits, parity and parity mode
|
||||
obj->uart->C1 = ((parity_enable << 1)
|
||||
| (parity_select << 0));
|
||||
|
||||
// stop bits
|
||||
obj->uart->BDH &= ~UARTLP_BDH_SBNS_MASK;
|
||||
obj->uart->BDH |= (stop_bits << UARTLP_BDH_SBNS_SHIFT);
|
||||
|
||||
// restore C2 state
|
||||
obj->uart->C2 |= c2_state;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* INTERRUPTS HANDLING
|
||||
******************************************************************************/
|
||||
static inline void uart_irq(uint8_t status, uint32_t index) {
|
||||
if (serial_irq_ids[index] != 0) {
|
||||
if (status & UARTLP_S1_TDRE_MASK)
|
||||
irq_handler(serial_irq_ids[index], TxIrq);
|
||||
|
||||
if (status & UARTLP_S1_RDRF_MASK)
|
||||
irq_handler(serial_irq_ids[index], RxIrq);
|
||||
}
|
||||
}
|
||||
|
||||
void uart0_irq() {
|
||||
uart_irq(UART0->S1, 0);
|
||||
if (UART0->S1 & UARTLP_S1_OR_MASK)
|
||||
UART0->S1 |= UARTLP_S1_OR_MASK;
|
||||
}
|
||||
#if UART_NUM > 1
|
||||
void uart1_irq() {uart_irq(UART1->S1, 1);}
|
||||
void uart2_irq() {uart_irq(UART2->S1, 2);}
|
||||
#endif
|
||||
|
||||
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
|
||||
irq_handler = handler;
|
||||
serial_irq_ids[obj->index] = id;
|
||||
}
|
||||
|
||||
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
||||
IRQn_Type irq_n = (IRQn_Type)0;
|
||||
uint32_t vector = 0;
|
||||
switch ((int)obj->uart) {
|
||||
case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
|
||||
#if UART_NUM > 1
|
||||
case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
|
||||
case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
switch (irq) {
|
||||
case RxIrq: obj->uart->C2 |= (UARTLP_C2_RIE_MASK); break;
|
||||
case TxIrq: obj->uart->C2 |= (UARTLP_C2_TIE_MASK); break;
|
||||
}
|
||||
NVIC_SetVector(irq_n, vector);
|
||||
NVIC_EnableIRQ(irq_n);
|
||||
|
||||
} else { // disable
|
||||
int all_disabled = 0;
|
||||
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
|
||||
switch (irq) {
|
||||
case RxIrq: obj->uart->C2 &= ~(UARTLP_C2_RIE_MASK); break;
|
||||
case TxIrq: obj->uart->C2 &= ~(UARTLP_C2_TIE_MASK); break;
|
||||
}
|
||||
switch (other_irq) {
|
||||
case RxIrq: all_disabled = (obj->uart->C2 & (UARTLP_C2_RIE_MASK)) == 0; break;
|
||||
case TxIrq: all_disabled = (obj->uart->C2 & (UARTLP_C2_TIE_MASK)) == 0; break;
|
||||
}
|
||||
if (all_disabled)
|
||||
NVIC_DisableIRQ(irq_n);
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* READ/WRITE
|
||||
******************************************************************************/
|
||||
int serial_getc(serial_t *obj) {
|
||||
while (!serial_readable(obj));
|
||||
return obj->uart->D;
|
||||
}
|
||||
|
||||
void serial_putc(serial_t *obj, int c) {
|
||||
while (!serial_writable(obj));
|
||||
obj->uart->D = c;
|
||||
}
|
||||
|
||||
int serial_readable(serial_t *obj) {
|
||||
// check overrun
|
||||
if (obj->uart->S1 & UARTLP_S1_OR_MASK) {
|
||||
obj->uart->S1 |= UARTLP_S1_OR_MASK;
|
||||
}
|
||||
return (obj->uart->S1 & UARTLP_S1_RDRF_MASK);
|
||||
}
|
||||
|
||||
int serial_writable(serial_t *obj) {
|
||||
// check overrun
|
||||
if (obj->uart->S1 & UARTLP_S1_OR_MASK) {
|
||||
obj->uart->S1 |= UARTLP_S1_OR_MASK;
|
||||
}
|
||||
return (obj->uart->S1 & UARTLP_S1_TDRE_MASK);
|
||||
}
|
||||
|
||||
void serial_clear(serial_t *obj) {
|
||||
}
|
||||
|
||||
void serial_pinout_tx(PinName tx) {
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
}
|
||||
|
||||
void serial_break_set(serial_t *obj) {
|
||||
obj->uart->C2 |= UARTLP_C2_SBK_MASK;
|
||||
}
|
||||
|
||||
void serial_break_clear(serial_t *obj) {
|
||||
obj->uart->C2 &= ~UARTLP_C2_SBK_MASK;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
OSC32KCLK = 0,
|
||||
RTC_CLKIN = 2
|
||||
} RTCName;
|
||||
|
||||
typedef enum {
|
||||
UART_0 = (int)LPUART0_BASE,
|
||||
UART_1 = (int)LPUART1_BASE,
|
||||
UART_2 = (int)UART2_BASE
|
||||
} UARTName;
|
||||
#define STDIO_UART_TX USBTX
|
||||
#define STDIO_UART_RX USBRX
|
||||
#define STDIO_UART UART_0
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = (int)I2C0_BASE,
|
||||
I2C_1 = (int)I2C1_BASE,
|
||||
} I2CName;
|
||||
|
||||
#define TPM_SHIFT 8
|
||||
typedef enum {
|
||||
PWM_1 = (0 << TPM_SHIFT) | (0), // TPM0 CH0
|
||||
PWM_2 = (0 << TPM_SHIFT) | (1), // TPM0 CH1
|
||||
PWM_3 = (0 << TPM_SHIFT) | (2), // TPM0 CH2
|
||||
PWM_4 = (0 << TPM_SHIFT) | (3), // TPM0 CH3
|
||||
PWM_5 = (0 << TPM_SHIFT) | (4), // TPM0 CH4
|
||||
PWM_6 = (0 << TPM_SHIFT) | (5), // TPM0 CH5
|
||||
|
||||
PWM_7 = (1 << TPM_SHIFT) | (0), // TPM1 CH0
|
||||
PWM_8 = (1 << TPM_SHIFT) | (1), // TPM1 CH1
|
||||
|
||||
PWM_9 = (2 << TPM_SHIFT) | (0), // TPM2 CH0
|
||||
PWM_10 = (2 << TPM_SHIFT) | (1) // TPM2 CH1
|
||||
} PWMName;
|
||||
|
||||
#define CHANNELS_A_SHIFT 5
|
||||
typedef enum {
|
||||
ADC0_SE0 = 0,
|
||||
ADC0_SE3 = 3,
|
||||
ADC0_SE4a = (1 << CHANNELS_A_SHIFT) | (4),
|
||||
ADC0_SE4b = 4,
|
||||
ADC0_SE5b = 5,
|
||||
ADC0_SE6b = 6,
|
||||
ADC0_SE7a = (1 << CHANNELS_A_SHIFT) | (7),
|
||||
ADC0_SE7b = 7,
|
||||
ADC0_SE8 = 8,
|
||||
ADC0_SE9 = 9,
|
||||
ADC0_SE11 = 11,
|
||||
ADC0_SE12 = 12,
|
||||
ADC0_SE13 = 13,
|
||||
ADC0_SE14 = 14,
|
||||
ADC0_SE15 = 15,
|
||||
ADC0_SE23 = 23
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
DAC_0 = 0
|
||||
} DACName;
|
||||
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = (int)SPI0_BASE,
|
||||
SPI_1 = (int)SPI1_BASE,
|
||||
} SPIName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
/************RTC***************/
|
||||
const PinMap PinMap_RTC[] = {
|
||||
{PTC1, RTC_CLKIN, 1},
|
||||
};
|
||||
|
||||
/************ADC***************/
|
||||
const PinMap PinMap_ADC[] = {
|
||||
{PTE20, ADC0_SE0, 0},
|
||||
{PTE22, ADC0_SE3, 0},
|
||||
{PTE21, ADC0_SE4a, 0},
|
||||
{PTE29, ADC0_SE4b, 0},
|
||||
{PTE30, ADC0_SE23, 0},
|
||||
{PTE23, ADC0_SE7a, 0},
|
||||
{PTB0, ADC0_SE8, 0},
|
||||
{PTB1, ADC0_SE9, 0},
|
||||
{PTB2, ADC0_SE12, 0},
|
||||
{PTB3, ADC0_SE13, 0},
|
||||
{PTC0, ADC0_SE14, 0},
|
||||
{PTC1, ADC0_SE15, 0},
|
||||
{PTC2, ADC0_SE11, 0},
|
||||
{PTD1, ADC0_SE5b, 0},
|
||||
{PTD5, ADC0_SE6b, 0},
|
||||
{PTD6, ADC0_SE7b, 0},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
/************DAC***************/
|
||||
const PinMap PinMap_DAC[] = {
|
||||
{PTE30, DAC_0, 0},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************I2C***************/
|
||||
const PinMap PinMap_I2C_SDA[] = {
|
||||
{PTA4, I2C_0, 2},
|
||||
{PTB1, I2C_0, 2},
|
||||
{PTB3, I2C_0, 2},
|
||||
{PTC2, I2C_1, 2},
|
||||
{PTE0, I2C_1, 6},
|
||||
{PTE25, I2C_0, 5},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_I2C_SCL[] = {
|
||||
{PTA3, I2C_0, 2},
|
||||
{PTB0, I2C_0, 2},
|
||||
{PTB2, I2C_0, 2},
|
||||
{PTC1, I2C_1, 2},
|
||||
{PTE1, I2C_1, 6},
|
||||
{PTE24, I2C_0, 5},
|
||||
{NC , NC, 0}
|
||||
};
|
||||
|
||||
/************UART***************/
|
||||
const PinMap PinMap_UART_TX[] = {
|
||||
{PTA2, UART_0, 2},
|
||||
{PTA19, UART_1, 3},
|
||||
{PTB17, UART_0, 3},
|
||||
{PTD3, UART_2, 3},
|
||||
{PTD5, UART_2, 3},
|
||||
{PTD7, UART_0, 3},
|
||||
{PTE0, UART_1, 3},
|
||||
{PTE20, UART_0, 4},
|
||||
{PTE22, UART_2, 4},
|
||||
{PTE30, UART_1, 5},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
{PTA1, UART_0, 2},
|
||||
{PTA18, UART_1, 3},
|
||||
{PTB16, UART_0, 3},
|
||||
{PTC3, UART_1, 3},
|
||||
{PTD2, UART_2, 3},
|
||||
{PTD4, UART_2, 3},
|
||||
{PTD6, UART_0, 3},
|
||||
{PTE1, UART_1, 3},
|
||||
{PTE21, UART_0, 4},
|
||||
{PTE23, UART_2, 4},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************SPI***************/
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
{PTC3, SPI_1, 2},
|
||||
{PTC5, SPI_0, 2},
|
||||
{PTD1, SPI_0, 2},
|
||||
{PTD5, SPI_1, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PTB16, SPI_1, 2},
|
||||
{PTB17, SPI_1, 5},
|
||||
{PTC6, SPI_0, 2},
|
||||
{PTC7, SPI_0, 5},
|
||||
{PTD2, SPI_0, 2},
|
||||
{PTD3, SPI_0, 5},
|
||||
{PTD6, SPI_1, 2},
|
||||
{PTD7, SPI_1, 5},
|
||||
{PTE1, SPI_1, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{PTB16, SPI_1, 5},
|
||||
{PTB17, SPI_1, 2},
|
||||
{PTC6, SPI_0, 5},
|
||||
{PTC7, SPI_0, 2},
|
||||
{PTD2, SPI_0, 5},
|
||||
{PTD3, SPI_0, 2},
|
||||
{PTD6, SPI_1, 5},
|
||||
{PTD7, SPI_1, 2},
|
||||
{PTE0, SPI_1, 2},
|
||||
{PTE1, SPI_1, 5},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
{PTC4, SPI_0, 2},
|
||||
{PTD0, SPI_0, 2},
|
||||
{PTD4, SPI_1, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
/************PWM***************/
|
||||
const PinMap PinMap_PWM[] = {
|
||||
{PTA0, PWM_6, 3}, // PTA0 , TPM0 CH5
|
||||
{PTA1, PWM_9 , 3}, // PTA1 , TPM2 CH0
|
||||
{PTA2, PWM_10, 3}, // PTA2 , TPM2 CH1
|
||||
{PTA3, PWM_1, 3}, // PTA3 , TPM0 CH0
|
||||
{PTA4, PWM_2 , 3}, // PTA4 , TPM0 CH1
|
||||
{PTA5, PWM_3 , 3}, // PTA5 , TPM0 CH2
|
||||
{PTA12, PWM_7 , 3}, // PTA12, TPM1 CH0
|
||||
{PTA13, PWM_8 , 3}, // PTA13, TPM1 CH1
|
||||
|
||||
{PTB0, PWM_7, 3}, // PTB0 , TPM1 CH0
|
||||
{PTB1, PWM_8, 3}, // PTB1 , TPM1 CH1
|
||||
{PTB2, PWM_9, 3}, // PTB2 , TPM2 CH0
|
||||
{PTB3, PWM_10, 3}, // PTB3 , TPM2 CH1
|
||||
{PTB18, PWM_9, 3}, // PTB18, TPM2 CH0
|
||||
{PTB19, PWM_10, 3}, // PTB18, TPM2 CH1
|
||||
|
||||
{PTC1, PWM_1, 4}, // PTC1 , TPM0 CH0
|
||||
{PTC2, PWM_2, 4}, // PTC2 , TPM0 CH1
|
||||
{PTC3, PWM_3, 4}, // PTC3 , TPM0 CH2
|
||||
{PTC4, PWM_4, 4}, // PTC4 , TPM0 CH3
|
||||
|
||||
{PTD0, PWM_1 , 4}, // PTD0 , TPM0 CH0
|
||||
{PTD1, PWM_2 , 4}, // PTD0 , TPM0 CH1
|
||||
{PTD2, PWM_3 , 4}, // PTD2 , TPM0 CH2
|
||||
{PTD3, PWM_4 , 4}, // PTD3 , TPM0 CH3
|
||||
{PTD4, PWM_5 , 4}, // PTD4 , TPM0 CH4
|
||||
{PTD5, PWM_6 , 4}, // PTD5 , TPM0 CH5
|
||||
|
||||
{PTE20, PWM_7, 3}, // PTE20, TPM1 CH0
|
||||
{PTE21, PWM_8, 3}, // PTE21, TPM1 CH1
|
||||
{PTE22, PWM_9, 3}, // PTE22, TPM2 CH0
|
||||
{PTE23, PWM_10, 3}, // PTE23, TPM2 CH1
|
||||
{PTE24, PWM_1, 3}, // PTE24, TPM0 CH0
|
||||
{PTE25, PWM_2, 3}, // PTE25, TPM0 CH1
|
||||
{PTE29, PWM_3, 3}, // PTE29, TPM0 CH2
|
||||
{PTE30, PWM_4, 3}, // PTE30, TPM0 CH3
|
||||
{PTE31, PWM_5, 3}, // PTE31, TPM0 CH4
|
||||
{NC , NC, 0}
|
||||
};
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PIN_INPUT,
|
||||
PIN_OUTPUT
|
||||
} PinDirection;
|
||||
|
||||
#define PORT_SHIFT 12
|
||||
|
||||
typedef enum {
|
||||
PTA0 = 0x0,
|
||||
PTA1 = 0x4,
|
||||
PTA2 = 0x8,
|
||||
PTA3 = 0xc,
|
||||
PTA4 = 0x10,
|
||||
PTA5 = 0x14,
|
||||
PTA6 = 0x18,
|
||||
PTA7 = 0x1c,
|
||||
PTA8 = 0x20,
|
||||
PTA9 = 0x24,
|
||||
PTA10 = 0x28,
|
||||
PTA11 = 0x2c,
|
||||
PTA12 = 0x30,
|
||||
PTA13 = 0x34,
|
||||
PTA14 = 0x38,
|
||||
PTA15 = 0x3c,
|
||||
PTA16 = 0x40,
|
||||
PTA17 = 0x44,
|
||||
PTA18 = 0x48,
|
||||
PTA19 = 0x4c,
|
||||
PTA20 = 0x50,
|
||||
PTA21 = 0x54,
|
||||
PTA22 = 0x58,
|
||||
PTA23 = 0x5c,
|
||||
PTA24 = 0x60,
|
||||
PTA25 = 0x64,
|
||||
PTA26 = 0x68,
|
||||
PTA27 = 0x6c,
|
||||
PTA28 = 0x70,
|
||||
PTA29 = 0x74,
|
||||
PTA30 = 0x78,
|
||||
PTA31 = 0x7c,
|
||||
PTB0 = 0x1000,
|
||||
PTB1 = 0x1004,
|
||||
PTB2 = 0x1008,
|
||||
PTB3 = 0x100c,
|
||||
PTB4 = 0x1010,
|
||||
PTB5 = 0x1014,
|
||||
PTB6 = 0x1018,
|
||||
PTB7 = 0x101c,
|
||||
PTB8 = 0x1020,
|
||||
PTB9 = 0x1024,
|
||||
PTB10 = 0x1028,
|
||||
PTB11 = 0x102c,
|
||||
PTB12 = 0x1030,
|
||||
PTB13 = 0x1034,
|
||||
PTB14 = 0x1038,
|
||||
PTB15 = 0x103c,
|
||||
PTB16 = 0x1040,
|
||||
PTB17 = 0x1044,
|
||||
PTB18 = 0x1048,
|
||||
PTB19 = 0x104c,
|
||||
PTB20 = 0x1050,
|
||||
PTB21 = 0x1054,
|
||||
PTB22 = 0x1058,
|
||||
PTB23 = 0x105c,
|
||||
PTB24 = 0x1060,
|
||||
PTB25 = 0x1064,
|
||||
PTB26 = 0x1068,
|
||||
PTB27 = 0x106c,
|
||||
PTB28 = 0x1070,
|
||||
PTB29 = 0x1074,
|
||||
PTB30 = 0x1078,
|
||||
PTB31 = 0x107c,
|
||||
PTC0 = 0x2000,
|
||||
PTC1 = 0x2004,
|
||||
PTC2 = 0x2008,
|
||||
PTC3 = 0x200c,
|
||||
PTC4 = 0x2010,
|
||||
PTC5 = 0x2014,
|
||||
PTC6 = 0x2018,
|
||||
PTC7 = 0x201c,
|
||||
PTC8 = 0x2020,
|
||||
PTC9 = 0x2024,
|
||||
PTC10 = 0x2028,
|
||||
PTC11 = 0x202c,
|
||||
PTC12 = 0x2030,
|
||||
PTC13 = 0x2034,
|
||||
PTC14 = 0x2038,
|
||||
PTC15 = 0x203c,
|
||||
PTC16 = 0x2040,
|
||||
PTC17 = 0x2044,
|
||||
PTC18 = 0x2048,
|
||||
PTC19 = 0x204c,
|
||||
PTC20 = 0x2050,
|
||||
PTC21 = 0x2054,
|
||||
PTC22 = 0x2058,
|
||||
PTC23 = 0x205c,
|
||||
PTC24 = 0x2060,
|
||||
PTC25 = 0x2064,
|
||||
PTC26 = 0x2068,
|
||||
PTC27 = 0x206c,
|
||||
PTC28 = 0x2070,
|
||||
PTC29 = 0x2074,
|
||||
PTC30 = 0x2078,
|
||||
PTC31 = 0x207c,
|
||||
PTD0 = 0x3000,
|
||||
PTD1 = 0x3004,
|
||||
PTD2 = 0x3008,
|
||||
PTD3 = 0x300c,
|
||||
PTD4 = 0x3010,
|
||||
PTD5 = 0x3014,
|
||||
PTD6 = 0x3018,
|
||||
PTD7 = 0x301c,
|
||||
PTD8 = 0x3020,
|
||||
PTD9 = 0x3024,
|
||||
PTD10 = 0x3028,
|
||||
PTD11 = 0x302c,
|
||||
PTD12 = 0x3030,
|
||||
PTD13 = 0x3034,
|
||||
PTD14 = 0x3038,
|
||||
PTD15 = 0x303c,
|
||||
PTD16 = 0x3040,
|
||||
PTD17 = 0x3044,
|
||||
PTD18 = 0x3048,
|
||||
PTD19 = 0x304c,
|
||||
PTD20 = 0x3050,
|
||||
PTD21 = 0x3054,
|
||||
PTD22 = 0x3058,
|
||||
PTD23 = 0x305c,
|
||||
PTD24 = 0x3060,
|
||||
PTD25 = 0x3064,
|
||||
PTD26 = 0x3068,
|
||||
PTD27 = 0x306c,
|
||||
PTD28 = 0x3070,
|
||||
PTD29 = 0x3074,
|
||||
PTD30 = 0x3078,
|
||||
PTD31 = 0x307c,
|
||||
PTE0 = 0x4000,
|
||||
PTE1 = 0x4004,
|
||||
PTE2 = 0x4008,
|
||||
PTE3 = 0x400c,
|
||||
PTE4 = 0x4010,
|
||||
PTE5 = 0x4014,
|
||||
PTE6 = 0x4018,
|
||||
PTE7 = 0x401c,
|
||||
PTE8 = 0x4020,
|
||||
PTE9 = 0x4024,
|
||||
PTE10 = 0x4028,
|
||||
PTE11 = 0x402c,
|
||||
PTE12 = 0x4030,
|
||||
PTE13 = 0x4034,
|
||||
PTE14 = 0x4038,
|
||||
PTE15 = 0x403c,
|
||||
PTE16 = 0x4040,
|
||||
PTE17 = 0x4044,
|
||||
PTE18 = 0x4048,
|
||||
PTE19 = 0x404c,
|
||||
PTE20 = 0x4050,
|
||||
PTE21 = 0x4054,
|
||||
PTE22 = 0x4058,
|
||||
PTE23 = 0x405c,
|
||||
PTE24 = 0x4060,
|
||||
PTE25 = 0x4064,
|
||||
PTE26 = 0x4068,
|
||||
PTE27 = 0x406c,
|
||||
PTE28 = 0x4070,
|
||||
PTE29 = 0x4074,
|
||||
PTE30 = 0x4078,
|
||||
PTE31 = 0x407c,
|
||||
|
||||
LED_RED = PTE31,
|
||||
LED_GREEN = PTD5,
|
||||
|
||||
// mbed original LED naming
|
||||
LED1 = LED_GREEN,
|
||||
LED2 = LED_RED,
|
||||
LED3 = LED_GREEN,
|
||||
LED4 = LED_RED,
|
||||
|
||||
//Push buttons
|
||||
SW1 = PTA4,
|
||||
SW3 = PTC3,
|
||||
|
||||
// USB Pins
|
||||
USBTX = PTA2,
|
||||
USBRX = PTA1,
|
||||
|
||||
// Arduino Headers
|
||||
D0 = PTA1,
|
||||
D1 = PTA2,
|
||||
D2 = PTD3,
|
||||
D3 = PTA12,
|
||||
D4 = PTA4,
|
||||
D5 = PTA5,
|
||||
D6 = PTC8,
|
||||
D7 = PTC9,
|
||||
D8 = PTA13,
|
||||
D9 = PTD2,
|
||||
D10 = PTD4,
|
||||
D11 = PTD6,
|
||||
D12 = PTD7,
|
||||
D13 = PTD5,
|
||||
D14 = PTE0,
|
||||
D15 = PTE1,
|
||||
|
||||
A0 = PTB0,
|
||||
A1 = PTB1,
|
||||
A2 = PTB2,
|
||||
A3 = PTB3,
|
||||
A4 = PTC2,
|
||||
A5 = PTC1,
|
||||
|
||||
I2C_SCL = D15,
|
||||
I2C_SDA = D14,
|
||||
|
||||
TSI_ELEC0 = PTB16,
|
||||
TSI_ELEC1 = PTB17,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
/* Pull modes for input pins */
|
||||
typedef enum {
|
||||
PullNone = 0,
|
||||
PullDown = 2,
|
||||
PullUp = 3,
|
||||
PullDefault = PullUp
|
||||
} PinMode;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_PORTIN 1
|
||||
#define DEVICE_PORTOUT 1
|
||||
#define DEVICE_PORTINOUT 1
|
||||
|
||||
#define DEVICE_INTERRUPTIN 1
|
||||
|
||||
#define DEVICE_ANALOGIN 1
|
||||
#define DEVICE_ANALOGOUT 1
|
||||
|
||||
#define DEVICE_SERIAL 1
|
||||
|
||||
#define DEVICE_I2C 1
|
||||
#define DEVICE_I2CSLAVE 1
|
||||
|
||||
#define DEVICE_SPI 1
|
||||
#define DEVICE_SPISLAVE 1
|
||||
|
||||
#define DEVICE_CAN 0
|
||||
|
||||
#define DEVICE_RTC 1
|
||||
|
||||
#define DEVICE_ETHERNET 0
|
||||
|
||||
#define DEVICE_PWMOUT 1
|
||||
|
||||
#define DEVICE_SEMIHOST 1
|
||||
#define DEVICE_LOCALFILESYSTEM 0
|
||||
#define DEVICE_ID_LENGTH 24
|
||||
|
||||
#define DEVICE_SLEEP 1
|
||||
|
||||
#define DEVICE_DEBUG_AWARENESS 0
|
||||
|
||||
#define DEVICE_STDIO_MESSAGES 1
|
||||
|
||||
#define DEVICE_ERROR_RED 1
|
||||
|
||||
#include "objects.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <stddef.h>
|
||||
#include "cmsis.h"
|
||||
|
||||
#include "gpio_irq_api.h"
|
||||
#include "gpio_api.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
#define CHANNEL_NUM 96
|
||||
|
||||
static uint32_t channel_ids[CHANNEL_NUM] = {0};
|
||||
static gpio_irq_handler irq_handler;
|
||||
|
||||
#define IRQ_DISABLED (0)
|
||||
#define IRQ_RAISING_EDGE PORT_PCR_IRQC(9)
|
||||
#define IRQ_FALLING_EDGE PORT_PCR_IRQC(10)
|
||||
#define IRQ_EITHER_EDGE PORT_PCR_IRQC(11)
|
||||
|
||||
const uint32_t search_bits[] = {0x0000FFFF, 0x000000FF, 0x0000000F, 0x00000003, 0x00000001};
|
||||
|
||||
static void handle_interrupt_in(PORT_Type *port, int ch_base) {
|
||||
uint32_t isfr;
|
||||
uint8_t location;
|
||||
|
||||
while((isfr = port->ISFR) != 0) {
|
||||
location = 0;
|
||||
for (int i = 0; i < 5; i++) {
|
||||
if (!(isfr & (search_bits[i] << location)))
|
||||
location += 1 << (4 - i);
|
||||
}
|
||||
|
||||
uint32_t id = channel_ids[ch_base + location];
|
||||
if (id == 0) {
|
||||
continue;
|
||||
}
|
||||
|
||||
GPIO_Type *gpio;
|
||||
gpio_irq_event event = IRQ_NONE;
|
||||
switch (port->PCR[location] & PORT_PCR_IRQC_MASK) {
|
||||
case IRQ_RAISING_EDGE:
|
||||
event = IRQ_RISE;
|
||||
break;
|
||||
|
||||
case IRQ_FALLING_EDGE:
|
||||
event = IRQ_FALL;
|
||||
break;
|
||||
|
||||
case IRQ_EITHER_EDGE:
|
||||
if (port == PORTA) {
|
||||
gpio = GPIOA;
|
||||
} else if (port == PORTC) {
|
||||
gpio = GPIOC;
|
||||
} else {
|
||||
gpio = GPIOD;
|
||||
}
|
||||
event = (gpio->PDIR & (1<<location)) ? (IRQ_RISE) : (IRQ_FALL);
|
||||
break;
|
||||
}
|
||||
if (event != IRQ_NONE) {
|
||||
irq_handler(id, event);
|
||||
}
|
||||
port->ISFR = 1 << location;
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_irqA(void) {
|
||||
handle_interrupt_in(PORTA, 0);
|
||||
}
|
||||
|
||||
/* PORTC and PORTD share same vector */
|
||||
void gpio_irqCD(void) {
|
||||
if ((SIM->SCGC5 & SIM_SCGC5_PORTC_MASK) && (PORTC->ISFR)) {
|
||||
handle_interrupt_in(PORTC, 32);
|
||||
} else if ((SIM->SCGC5 & SIM_SCGC5_PORTD_MASK) && (PORTD->ISFR)) {
|
||||
handle_interrupt_in(PORTD, 64);
|
||||
}
|
||||
}
|
||||
|
||||
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
|
||||
if (pin == NC)
|
||||
return -1;
|
||||
|
||||
irq_handler = handler;
|
||||
|
||||
obj->port = pin >> PORT_SHIFT;
|
||||
obj->pin = (pin & 0x7F) >> 2;
|
||||
|
||||
uint32_t ch_base, vector;
|
||||
IRQn_Type irq_n;
|
||||
switch (obj->port) {
|
||||
case PortA:
|
||||
ch_base = 0; irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA;
|
||||
break;
|
||||
|
||||
case PortC:
|
||||
ch_base = 32; irq_n = PORTCD_IRQn; vector = (uint32_t)gpio_irqCD;
|
||||
break;
|
||||
|
||||
case PortD:
|
||||
ch_base = 64; irq_n = PORTCD_IRQn; vector = (uint32_t)gpio_irqCD;
|
||||
break;
|
||||
|
||||
default:
|
||||
error("gpio_irq only supported on port A,C and D");
|
||||
break;
|
||||
}
|
||||
NVIC_SetVector(irq_n, vector);
|
||||
NVIC_EnableIRQ(irq_n);
|
||||
|
||||
obj->ch = ch_base + obj->pin;
|
||||
channel_ids[obj->ch] = id;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void gpio_irq_free(gpio_irq_t *obj) {
|
||||
channel_ids[obj->ch] = 0;
|
||||
}
|
||||
|
||||
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
|
||||
PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port);
|
||||
|
||||
uint32_t irq_settings = IRQ_DISABLED;
|
||||
|
||||
switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
|
||||
case IRQ_DISABLED:
|
||||
if (enable) {
|
||||
irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
|
||||
}
|
||||
break;
|
||||
|
||||
case IRQ_RAISING_EDGE:
|
||||
if (enable) {
|
||||
irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE);
|
||||
} else {
|
||||
if (event == IRQ_FALL)
|
||||
irq_settings = IRQ_RAISING_EDGE;
|
||||
}
|
||||
break;
|
||||
|
||||
case IRQ_FALLING_EDGE:
|
||||
if (enable) {
|
||||
irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE);
|
||||
} else {
|
||||
if (event == IRQ_RISE)
|
||||
irq_settings = IRQ_FALLING_EDGE;
|
||||
}
|
||||
break;
|
||||
|
||||
case IRQ_EITHER_EDGE:
|
||||
if (enable) {
|
||||
irq_settings = IRQ_EITHER_EDGE;
|
||||
} else {
|
||||
irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
// Interrupt configuration and clear interrupt
|
||||
port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK;
|
||||
}
|
||||
|
||||
void gpio_irq_enable(gpio_irq_t *obj) {
|
||||
if (obj->port == PortA) {
|
||||
NVIC_EnableIRQ(PORTA_IRQn);
|
||||
} else {
|
||||
NVIC_EnableIRQ(PORTCD_IRQn);
|
||||
}
|
||||
}
|
||||
|
||||
void gpio_irq_disable(gpio_irq_t *obj) {
|
||||
if (obj->port == PortA) {
|
||||
NVIC_DisableIRQ(PORTA_IRQn);
|
||||
} else {
|
||||
NVIC_DisableIRQ(PORTCD_IRQn);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "gpio_api.h"
|
||||
|
||||
// called before main - implement here if board needs it ortherwise, let
|
||||
// the application override this if necessary
|
||||
//void mbed_sdk_init()
|
||||
//{
|
||||
//
|
||||
//}
|
||||
|
||||
// Change the NMI pin to an input. This allows NMI pin to
|
||||
// be used as a low power mode wakeup. The application will
|
||||
// need to change the pin back to NMI_b or wakeup only occurs once!
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
gpio_t gpio;
|
||||
gpio_init_in(&gpio, PTA4);
|
||||
}
|
||||
|
|
@ -0,0 +1,298 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "serial_api.h"
|
||||
|
||||
// math.h required for floating point operations for baud rate calculation
|
||||
#include <math.h>
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "clk_freqs.h"
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
#define UART_NUM 2
|
||||
|
||||
/******************************************************************************
|
||||
* INITIALIZATION
|
||||
******************************************************************************/
|
||||
|
||||
static uint32_t serial_irq_ids[UART_NUM] = {0};
|
||||
static uart_irq_handler irq_handler;
|
||||
|
||||
int stdio_uart_inited = 0;
|
||||
serial_t stdio_uart;
|
||||
|
||||
void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
||||
// determine the UART to use
|
||||
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
|
||||
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
|
||||
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
|
||||
MBED_ASSERT((int)uart != NC);
|
||||
|
||||
obj->uart = (LPUART_Type *)uart;
|
||||
|
||||
// enable clk
|
||||
switch (uart) {
|
||||
case UART_0:
|
||||
SIM->SOPT2 |= SIM_SOPT2_LPUART0SRC(1);
|
||||
SIM->SCGC5 |= SIM_SCGC5_LPUART0_MASK;
|
||||
break;
|
||||
case UART_1:
|
||||
SIM->SOPT2 |= SIM_SOPT2_LPUART1SRC(1);
|
||||
SIM->SCGC5 |= SIM_SCGC5_LPUART1_MASK;
|
||||
break;
|
||||
case UART_2: /* TODO: add UART2 support */ break;
|
||||
}
|
||||
|
||||
// reset UART registers
|
||||
obj->uart->BAUD = 0x0F000004;
|
||||
obj->uart->STAT = 0xC01FC000;
|
||||
obj->uart->CTRL = 0x00000000;
|
||||
obj->uart->MATCH = 0x00000000;
|
||||
|
||||
switch (uart) {
|
||||
case UART_0: obj->index = 0; break;
|
||||
case UART_1: obj->index = 1; break;
|
||||
case UART_2: /* TODO: add UART2 support */ break;
|
||||
}
|
||||
|
||||
// set default baud rate and format
|
||||
serial_baud (obj, 9600);
|
||||
serial_format(obj, 8, ParityNone, 1);
|
||||
|
||||
// pinout the chosen uart
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
pinmap_pinout(rx, PinMap_UART_RX);
|
||||
|
||||
// set rx/tx pins in PullUp mode
|
||||
if (tx != NC) pin_mode(tx, PullUp);
|
||||
if (rx != NC) pin_mode(rx, PullUp);
|
||||
|
||||
obj->uart->CTRL |= (LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK);
|
||||
|
||||
if (uart == STDIO_UART) {
|
||||
stdio_uart_inited = 1;
|
||||
memcpy(&stdio_uart, obj, sizeof(serial_t));
|
||||
}
|
||||
}
|
||||
|
||||
void serial_free(serial_t *obj) {
|
||||
serial_irq_ids[obj->index] = 0;
|
||||
}
|
||||
|
||||
// serial_baud
|
||||
//
|
||||
// set the baud rate, taking in to account the current SystemFrequency
|
||||
void serial_baud(serial_t *obj, int baudrate) {
|
||||
int calcBaudrate;
|
||||
uint16_t sbr, sbrTemp, i;
|
||||
uint32_t osr, temp, baudDiff;
|
||||
|
||||
/* Use Fast IRC Clock 48Mhz */
|
||||
uint32_t PCLK = CPU_INT_FAST_CLK_HZ;
|
||||
|
||||
/* This lpuart instantiation uses a slightly different baud rate calculation
|
||||
* The idea is to use the best OSR (over-sampling rate) possible
|
||||
* Note, osr is typically hard-set to 16 in other lpuart instantiations
|
||||
* First calculate the baud rate using the minimum OSR possible (4) */
|
||||
osr = 4;
|
||||
sbr = PCLK / (baudrate * osr);
|
||||
calcBaudrate = PCLK / (osr * sbr);
|
||||
|
||||
if (calcBaudrate > baudrate) {
|
||||
baudDiff = calcBaudrate - baudrate;
|
||||
} else {
|
||||
baudDiff = baudrate - calcBaudrate;
|
||||
}
|
||||
|
||||
/* loop to find the best osr value possible, one that generates minimum baudDiff
|
||||
* iterate through the rest of the supported values of osr */
|
||||
for (i = 5; i <= 32; i++) {
|
||||
/* calculate the temporary sbr value */
|
||||
sbrTemp = PCLK / (baudrate * i);
|
||||
|
||||
/* calculate the baud rate based on the temporary osr and sbr values */
|
||||
calcBaudrate = PCLK / (i * sbrTemp);
|
||||
|
||||
if (calcBaudrate > baudrate) {
|
||||
temp = calcBaudrate - baudrate;
|
||||
} else {
|
||||
temp = baudrate - calcBaudrate;
|
||||
}
|
||||
|
||||
if (temp <= baudDiff) {
|
||||
baudDiff = temp;
|
||||
osr = i; /* update and store the best osr value calculated */
|
||||
sbr = sbrTemp; /* update store the best sbr value calculated */
|
||||
}
|
||||
}
|
||||
|
||||
/* save C2 state */
|
||||
temp = obj->uart->CTRL & (LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK);
|
||||
|
||||
/* disable UART before changing registers */
|
||||
obj->uart->CTRL &= ~(LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK);
|
||||
|
||||
/* reset old baudrate settings */
|
||||
obj->uart->BAUD &= ~(LPUART_BAUD_SBR_MASK | LPUART_BAUD_OSR_MASK | LPUART_BAUD_BOTHEDGE_MASK);
|
||||
|
||||
/* write the new osr and sbr values to the BAUD register */
|
||||
obj->uart->BAUD |= LPUART_BAUD_SBR(sbr) | LPUART_BAUD_OSR(osr-1);
|
||||
|
||||
/* Check if osr is between 4x and 7x oversampling.
|
||||
* If so, then "BOTHEDGE" sampling must be turned on */
|
||||
if ((osr > 3) && (osr < 8)) {
|
||||
obj->uart->BAUD |= LPUART_BAUD_BOTHEDGE_MASK;
|
||||
}
|
||||
|
||||
/* restore C2 state */
|
||||
obj->uart->CTRL |= temp;
|
||||
}
|
||||
|
||||
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
|
||||
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
|
||||
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
|
||||
MBED_ASSERT(data_bits == 8); // TODO: Support other number of data bits (also in the write method!)
|
||||
|
||||
// save C2 state
|
||||
uint32_t c2_state = obj->uart->CTRL & (LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK);
|
||||
|
||||
// disable UART before changing registers
|
||||
obj->uart->CTRL &= ~(LPUART_CTRL_RE_MASK | LPUART_CTRL_TE_MASK);
|
||||
|
||||
|
||||
uint8_t parity_enable = 0, parity_select = 0;
|
||||
switch (parity) {
|
||||
case ParityNone: parity_enable = 0; parity_select = 0; break;
|
||||
case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break;
|
||||
case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
stop_bits -= 1;
|
||||
|
||||
// data bits, parity and parity mode
|
||||
obj->uart->CTRL = ((parity_enable << 1) | (parity_select << 0));
|
||||
|
||||
// stop bits
|
||||
obj->uart->BAUD &= ~LPUART_BAUD_SBNS_MASK;
|
||||
obj->uart->BAUD |= (stop_bits << LPUART_BAUD_SBNS_SHIFT);
|
||||
|
||||
// restore C2 state
|
||||
obj->uart->CTRL |= c2_state;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* INTERRUPTS HANDLING
|
||||
******************************************************************************/
|
||||
static inline void uart_irq(uint32_t status, uint32_t index) {
|
||||
if (serial_irq_ids[index] != 0) {
|
||||
if (status & LPUART_STAT_TDRE_MASK)
|
||||
irq_handler(serial_irq_ids[index], TxIrq);
|
||||
|
||||
if (status & LPUART_STAT_RDRF_MASK)
|
||||
irq_handler(serial_irq_ids[index], RxIrq);
|
||||
}
|
||||
}
|
||||
|
||||
void uart0_irq() {uart_irq(LPUART0->STAT, 0);}
|
||||
void uart1_irq() {uart_irq(LPUART1->STAT, 1);}
|
||||
|
||||
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
|
||||
irq_handler = handler;
|
||||
serial_irq_ids[obj->index] = id;
|
||||
}
|
||||
|
||||
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
||||
IRQn_Type irq_n = (IRQn_Type)0;
|
||||
uint32_t vector = 0;
|
||||
switch ((int)obj->uart) {
|
||||
case UART_0: irq_n=LPUART0_IRQn; vector = (uint32_t)&uart0_irq; break;
|
||||
case UART_1: irq_n=LPUART1_IRQn; vector = (uint32_t)&uart1_irq; break;
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
switch (irq) {
|
||||
case RxIrq: obj->uart->CTRL |= LPUART_CTRL_RIE_MASK; break;
|
||||
case TxIrq: obj->uart->CTRL |= LPUART_CTRL_TIE_MASK; break;
|
||||
}
|
||||
NVIC_SetVector(irq_n, vector);
|
||||
NVIC_EnableIRQ(irq_n);
|
||||
|
||||
} else { // disable
|
||||
int all_disabled = 0;
|
||||
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
|
||||
switch (irq) {
|
||||
case RxIrq: obj->uart->CTRL &= ~(LPUART_CTRL_RIE_MASK); break;
|
||||
case TxIrq: obj->uart->CTRL &= ~(LPUART_CTRL_TIE_MASK); break;
|
||||
}
|
||||
switch (other_irq) {
|
||||
case RxIrq: all_disabled = (obj->uart->CTRL & LPUART_CTRL_RIE_MASK) == 0; break;
|
||||
case TxIrq: all_disabled = (obj->uart->CTRL & LPUART_CTRL_TIE_MASK) == 0; break;
|
||||
}
|
||||
if (all_disabled)
|
||||
NVIC_DisableIRQ(irq_n);
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* READ/WRITE
|
||||
******************************************************************************/
|
||||
int serial_getc(serial_t *obj) {
|
||||
while (!serial_readable(obj));
|
||||
return (obj->uart->DATA & 0xFFu);
|
||||
}
|
||||
|
||||
void serial_putc(serial_t *obj, int c) {
|
||||
while (!serial_writable(obj));
|
||||
obj->uart->DATA = c;
|
||||
}
|
||||
|
||||
int serial_readable(serial_t *obj) {
|
||||
// check overrun
|
||||
if (obj->uart->STAT & LPUART_STAT_OR_MASK) {
|
||||
obj->uart->STAT |= LPUART_STAT_OR_MASK;
|
||||
}
|
||||
return (obj->uart->STAT & LPUART_STAT_RDRF_MASK);
|
||||
}
|
||||
|
||||
int serial_writable(serial_t *obj) {
|
||||
// check overrun
|
||||
if (obj->uart->STAT & LPUART_STAT_OR_MASK) {
|
||||
obj->uart->STAT |= LPUART_STAT_OR_MASK;
|
||||
}
|
||||
return (obj->uart->STAT & LPUART_STAT_TDRE_MASK);
|
||||
}
|
||||
|
||||
void serial_clear(serial_t *obj) {
|
||||
}
|
||||
|
||||
void serial_pinout_tx(PinName tx) {
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
}
|
||||
|
||||
void serial_break_set(serial_t *obj) {
|
||||
obj->uart->CTRL |= LPUART_CTRL_SBK_MASK;
|
||||
}
|
||||
|
||||
void serial_break_clear(serial_t *obj) {
|
||||
obj->uart->CTRL &= ~LPUART_CTRL_SBK_MASK;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "spi_api.h"
|
||||
|
||||
#include <math.h>
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
|
||||
static const PinMap PinMap_SPI_SCLK[] = {
|
||||
{PTC3, SPI_1, 2},
|
||||
{PTC5, SPI_0, 2},
|
||||
{PTD1, SPI_0, 2},
|
||||
{PTD5, SPI_1, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_MOSI[] = {
|
||||
{PTB16, SPI_1, 2},
|
||||
{PTB17, SPI_1, 5},
|
||||
{PTC6, SPI_0, 2},
|
||||
{PTC7, SPI_0, 5},
|
||||
{PTD2, SPI_0, 2},
|
||||
{PTD3, SPI_0, 5},
|
||||
{PTD6, SPI_1, 2},
|
||||
{PTD7, SPI_1, 5},
|
||||
{PTE1, SPI_1, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_MISO[] = {
|
||||
{PTB16, SPI_1, 5},
|
||||
{PTB17, SPI_1, 2},
|
||||
{PTC6, SPI_0, 5},
|
||||
{PTC7, SPI_0, 2},
|
||||
{PTD2, SPI_0, 5},
|
||||
{PTD3, SPI_0, 2},
|
||||
{PTD6, SPI_1, 5},
|
||||
{PTD7, SPI_1, 2},
|
||||
{PTE0, SPI_1, 2},
|
||||
{PTE1, SPI_1, 5},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
static const PinMap PinMap_SPI_SSEL[] = {
|
||||
{PTC4, SPI_0, 2},
|
||||
{PTD0, SPI_0, 2},
|
||||
{PTD4, SPI_1, 2},
|
||||
{NC , NC , 0}
|
||||
};
|
||||
|
||||
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
|
||||
// determine the SPI to use
|
||||
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
|
||||
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
|
||||
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
|
||||
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
|
||||
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
|
||||
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
|
||||
|
||||
obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
|
||||
MBED_ASSERT((int)obj->spi != NC);
|
||||
|
||||
// enable power and clocking
|
||||
switch ((int)obj->spi) {
|
||||
case SPI_0: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 22; break;
|
||||
case SPI_1: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 23; break;
|
||||
}
|
||||
|
||||
// set default format and frequency
|
||||
if (ssel == NC) {
|
||||
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
|
||||
} else {
|
||||
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
|
||||
}
|
||||
spi_frequency(obj, 1000000);
|
||||
|
||||
// enable SPI
|
||||
obj->spi->C1 |= SPI_C1_SPE_MASK;
|
||||
obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK; //8bit
|
||||
|
||||
// pin out the spi pins
|
||||
pinmap_pinout(mosi, PinMap_SPI_MOSI);
|
||||
pinmap_pinout(miso, PinMap_SPI_MISO);
|
||||
pinmap_pinout(sclk, PinMap_SPI_SCLK);
|
||||
if (ssel != NC) {
|
||||
pinmap_pinout(ssel, PinMap_SPI_SSEL);
|
||||
}
|
||||
}
|
||||
|
||||
void spi_free(spi_t *obj) {
|
||||
// [TODO]
|
||||
}
|
||||
|
||||
void spi_format(spi_t *obj, int bits, int mode, int slave) {
|
||||
MBED_ASSERT((bits == 8) || (bits == 16));
|
||||
MBED_ASSERT((mode >= 0) && (mode <= 3));
|
||||
|
||||
uint8_t polarity = (mode & 0x2) ? 1 : 0;
|
||||
uint8_t phase = (mode & 0x1) ? 1 : 0;
|
||||
uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2);
|
||||
|
||||
// clear MSTR, CPOL and CPHA bits
|
||||
obj->spi->C1 &= ~(0x7 << 2);
|
||||
|
||||
// write new value
|
||||
obj->spi->C1 |= c1_data;
|
||||
if (bits == 8) {
|
||||
obj->spi->C2 &= ~SPI_C2_SPIMODE_MASK;
|
||||
} else {
|
||||
obj->spi->C2 |= SPI_C2_SPIMODE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
void spi_frequency(spi_t *obj, int hz) {
|
||||
uint32_t error = 0;
|
||||
uint32_t p_error = 0xffffffff;
|
||||
uint32_t ref = 0;
|
||||
uint8_t spr = 0;
|
||||
uint8_t ref_spr = 0;
|
||||
uint8_t ref_prescaler = 0;
|
||||
|
||||
// bus clk
|
||||
uint32_t PCLK = SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
|
||||
uint8_t prescaler = 1;
|
||||
uint8_t divisor = 2;
|
||||
|
||||
for (prescaler = 1; prescaler <= 8; prescaler++) {
|
||||
divisor = 2;
|
||||
for (spr = 0; spr <= 8; spr++, divisor *= 2) {
|
||||
ref = PCLK / (prescaler*divisor);
|
||||
if (ref > (uint32_t)hz)
|
||||
continue;
|
||||
error = hz - ref;
|
||||
if (error < p_error) {
|
||||
ref_spr = spr;
|
||||
ref_prescaler = prescaler - 1;
|
||||
p_error = error;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// set SPPR and SPR
|
||||
obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf);
|
||||
}
|
||||
|
||||
static inline int spi_writeable(spi_t * obj) {
|
||||
return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0;
|
||||
}
|
||||
|
||||
static inline int spi_readable(spi_t * obj) {
|
||||
return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0;
|
||||
}
|
||||
|
||||
int spi_master_write(spi_t *obj, int value) {
|
||||
int ret;
|
||||
if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
|
||||
// 16bit
|
||||
while(!spi_writeable(obj));
|
||||
obj->spi->DL = (value & 0xff);
|
||||
obj->spi->DH = ((value >> 8) & 0xff);
|
||||
|
||||
// wait rx buffer full
|
||||
while (!spi_readable(obj));
|
||||
ret = obj->spi->DH;
|
||||
ret = (ret << 8) | obj->spi->DL;
|
||||
} else {
|
||||
//8bit
|
||||
while(!spi_writeable(obj));
|
||||
obj->spi->DL = (value & 0xff);
|
||||
|
||||
// wait rx buffer full
|
||||
while (!spi_readable(obj));
|
||||
ret = (obj->spi->DL & 0xff);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int spi_slave_receive(spi_t *obj) {
|
||||
return spi_readable(obj);
|
||||
}
|
||||
|
||||
int spi_slave_read(spi_t *obj) {
|
||||
int ret;
|
||||
if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
|
||||
ret = obj->spi->DH;
|
||||
ret = ((ret << 8) | obj->spi->DL);
|
||||
} else {
|
||||
ret = obj->spi->DL;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
void spi_slave_write(spi_t *obj, int value) {
|
||||
while (!spi_writeable(obj));
|
||||
if (obj->spi->C2 & SPI_C2_SPIMODE_MASK) {
|
||||
obj->spi->DL = (value & 0xff);
|
||||
obj->spi->DH = ((value >> 8) & 0xff);
|
||||
} else {
|
||||
obj->spi->DL = value;
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,295 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "mbed_assert.h"
|
||||
#include "serial_api.h"
|
||||
|
||||
// math.h required for floating point operations for baud rate calculation
|
||||
#include <math.h>
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "clk_freqs.h"
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
//Devices either user UART0 or UARTLP
|
||||
#ifndef UARTLP_BASES
|
||||
#define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
|
||||
#define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
|
||||
#define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
|
||||
#define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
|
||||
#define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
|
||||
#define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
|
||||
#define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
|
||||
#define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
|
||||
#define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
|
||||
#define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
|
||||
#endif
|
||||
|
||||
#ifdef UART2
|
||||
#define UART_NUM 3
|
||||
#else
|
||||
#define UART_NUM 1
|
||||
#endif
|
||||
|
||||
/******************************************************************************
|
||||
* INITIALIZATION
|
||||
******************************************************************************/
|
||||
|
||||
static uint32_t serial_irq_ids[UART_NUM] = {0};
|
||||
static uart_irq_handler irq_handler;
|
||||
|
||||
int stdio_uart_inited = 0;
|
||||
serial_t stdio_uart;
|
||||
|
||||
void serial_init(serial_t *obj, PinName tx, PinName rx) {
|
||||
// determine the UART to use
|
||||
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
|
||||
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
|
||||
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
|
||||
MBED_ASSERT((int)uart != NC);
|
||||
|
||||
obj->uart = (UARTLP_Type *)uart;
|
||||
// enable clk
|
||||
switch (uart) {
|
||||
case UART_0: if (mcgpllfll_frequency() != 0) //PLL/FLL is selected
|
||||
SIM->SOPT2 |= (1<<SIM_SOPT2_UART0SRC_SHIFT);
|
||||
else
|
||||
SIM->SOPT2 |= (2<<SIM_SOPT2_UART0SRC_SHIFT);
|
||||
SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break;
|
||||
#if UART_NUM > 1
|
||||
case UART_1: SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break;
|
||||
case UART_2: SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break;
|
||||
#endif
|
||||
}
|
||||
// Disable UART before changing registers
|
||||
obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
|
||||
|
||||
switch (uart) {
|
||||
case UART_0: obj->index = 0; break;
|
||||
#if UART_NUM > 1
|
||||
case UART_1: obj->index = 1; break;
|
||||
case UART_2: obj->index = 2; break;
|
||||
#endif
|
||||
}
|
||||
|
||||
// set default baud rate and format
|
||||
serial_baud (obj, 9600);
|
||||
serial_format(obj, 8, ParityNone, 1);
|
||||
|
||||
// pinout the chosen uart
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
pinmap_pinout(rx, PinMap_UART_RX);
|
||||
|
||||
// set rx/tx pins in PullUp mode
|
||||
if (tx != NC) {
|
||||
pin_mode(tx, PullUp);
|
||||
}
|
||||
if (rx != NC) {
|
||||
pin_mode(rx, PullUp);
|
||||
}
|
||||
|
||||
obj->uart->C2 |= (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
|
||||
|
||||
if (uart == STDIO_UART) {
|
||||
stdio_uart_inited = 1;
|
||||
memcpy(&stdio_uart, obj, sizeof(serial_t));
|
||||
}
|
||||
}
|
||||
|
||||
void serial_free(serial_t *obj) {
|
||||
serial_irq_ids[obj->index] = 0;
|
||||
}
|
||||
|
||||
// serial_baud
|
||||
//
|
||||
// set the baud rate, taking in to account the current SystemFrequency
|
||||
void serial_baud(serial_t *obj, int baudrate) {
|
||||
|
||||
// save C2 state
|
||||
uint8_t c2_state = (obj->uart->C2 & (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK));
|
||||
|
||||
// Disable UART before changing registers
|
||||
obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
|
||||
|
||||
uint32_t PCLK;
|
||||
if (obj->uart == UART0) {
|
||||
if (mcgpllfll_frequency() != 0)
|
||||
PCLK = mcgpllfll_frequency();
|
||||
else
|
||||
PCLK = extosc_frequency();
|
||||
} else
|
||||
PCLK = bus_frequency();
|
||||
|
||||
// First we check to see if the basic divide with no DivAddVal/MulVal
|
||||
// ratio gives us an integer result. If it does, we set DivAddVal = 0,
|
||||
// MulVal = 1. Otherwise, we search the valid ratio value range to find
|
||||
// the closest match. This could be more elegant, using search methods
|
||||
// and/or lookup tables, but the brute force method is not that much
|
||||
// slower, and is more maintainable.
|
||||
uint16_t DL = PCLK / (16 * baudrate);
|
||||
|
||||
// set BDH and BDL
|
||||
obj->uart->BDH = (obj->uart->BDH & ~(0x1f)) | ((DL >> 8) & 0x1f);
|
||||
obj->uart->BDL = (obj->uart->BDL & ~(0xff)) | ((DL >> 0) & 0xff);
|
||||
|
||||
// restore C2 state
|
||||
obj->uart->C2 |= c2_state;
|
||||
}
|
||||
|
||||
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
|
||||
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
|
||||
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
|
||||
MBED_ASSERT(data_bits == 8); // TODO: Support other number of data bits (also in the write method!)
|
||||
|
||||
// save C2 state
|
||||
uint8_t c2_state = (obj->uart->C2 & (UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK));
|
||||
|
||||
// Disable UART before changing registers
|
||||
obj->uart->C2 &= ~(UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK);
|
||||
|
||||
|
||||
uint8_t parity_enable, parity_select;
|
||||
switch (parity) {
|
||||
case ParityNone: parity_enable = 0; parity_select = 0; break;
|
||||
case ParityOdd : parity_enable = 1; parity_select = 1; data_bits++; break;
|
||||
case ParityEven: parity_enable = 1; parity_select = 0; data_bits++; break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
stop_bits -= 1;
|
||||
|
||||
// data bits, parity and parity mode
|
||||
obj->uart->C1 = ((parity_enable << 1)
|
||||
| (parity_select << 0));
|
||||
|
||||
// stop bits
|
||||
obj->uart->BDH &= ~UARTLP_BDH_SBNS_MASK;
|
||||
obj->uart->BDH |= (stop_bits << UARTLP_BDH_SBNS_SHIFT);
|
||||
|
||||
// restore C2 state
|
||||
obj->uart->C2 |= c2_state;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* INTERRUPTS HANDLING
|
||||
******************************************************************************/
|
||||
static inline void uart_irq(uint8_t status, uint32_t index) {
|
||||
if (serial_irq_ids[index] != 0) {
|
||||
if (status & UARTLP_S1_TDRE_MASK)
|
||||
irq_handler(serial_irq_ids[index], TxIrq);
|
||||
|
||||
if (status & UARTLP_S1_RDRF_MASK)
|
||||
irq_handler(serial_irq_ids[index], RxIrq);
|
||||
}
|
||||
}
|
||||
|
||||
void uart0_irq() {
|
||||
uart_irq(UART0->S1, 0);
|
||||
if (UART0->S1 & UARTLP_S1_OR_MASK)
|
||||
UART0->S1 |= UARTLP_S1_OR_MASK;
|
||||
}
|
||||
#if UART_NUM > 1
|
||||
void uart1_irq() {uart_irq(UART1->S1, 1);}
|
||||
void uart2_irq() {uart_irq(UART2->S1, 2);}
|
||||
#endif
|
||||
|
||||
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
|
||||
irq_handler = handler;
|
||||
serial_irq_ids[obj->index] = id;
|
||||
}
|
||||
|
||||
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
|
||||
IRQn_Type irq_n = (IRQn_Type)0;
|
||||
uint32_t vector = 0;
|
||||
switch ((int)obj->uart) {
|
||||
case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
|
||||
#if UART_NUM > 1
|
||||
case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
|
||||
case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (enable) {
|
||||
switch (irq) {
|
||||
case RxIrq: obj->uart->C2 |= (UARTLP_C2_RIE_MASK); break;
|
||||
case TxIrq: obj->uart->C2 |= (UARTLP_C2_TIE_MASK); break;
|
||||
}
|
||||
NVIC_SetVector(irq_n, vector);
|
||||
NVIC_EnableIRQ(irq_n);
|
||||
|
||||
} else { // disable
|
||||
int all_disabled = 0;
|
||||
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
|
||||
switch (irq) {
|
||||
case RxIrq: obj->uart->C2 &= ~(UARTLP_C2_RIE_MASK); break;
|
||||
case TxIrq: obj->uart->C2 &= ~(UARTLP_C2_TIE_MASK); break;
|
||||
}
|
||||
switch (other_irq) {
|
||||
case RxIrq: all_disabled = (obj->uart->C2 & (UARTLP_C2_RIE_MASK)) == 0; break;
|
||||
case TxIrq: all_disabled = (obj->uart->C2 & (UARTLP_C2_TIE_MASK)) == 0; break;
|
||||
}
|
||||
if (all_disabled)
|
||||
NVIC_DisableIRQ(irq_n);
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* READ/WRITE
|
||||
******************************************************************************/
|
||||
int serial_getc(serial_t *obj) {
|
||||
while (!serial_readable(obj));
|
||||
return obj->uart->D;
|
||||
}
|
||||
|
||||
void serial_putc(serial_t *obj, int c) {
|
||||
while (!serial_writable(obj));
|
||||
obj->uart->D = c;
|
||||
}
|
||||
|
||||
int serial_readable(serial_t *obj) {
|
||||
// check overrun
|
||||
if (obj->uart->S1 & UARTLP_S1_OR_MASK) {
|
||||
obj->uart->S1 |= UARTLP_S1_OR_MASK;
|
||||
}
|
||||
return (obj->uart->S1 & UARTLP_S1_RDRF_MASK);
|
||||
}
|
||||
|
||||
int serial_writable(serial_t *obj) {
|
||||
// check overrun
|
||||
if (obj->uart->S1 & UARTLP_S1_OR_MASK) {
|
||||
obj->uart->S1 |= UARTLP_S1_OR_MASK;
|
||||
}
|
||||
return (obj->uart->S1 & UARTLP_S1_TDRE_MASK);
|
||||
}
|
||||
|
||||
void serial_clear(serial_t *obj) {
|
||||
}
|
||||
|
||||
void serial_pinout_tx(PinName tx) {
|
||||
pinmap_pinout(tx, PinMap_UART_TX);
|
||||
}
|
||||
|
||||
void serial_break_set(serial_t *obj) {
|
||||
obj->uart->C2 |= UARTLP_C2_SBK_MASK;
|
||||
}
|
||||
|
||||
void serial_break_clear(serial_t *obj) {
|
||||
obj->uart->C2 &= ~UARTLP_C2_SBK_MASK;
|
||||
}
|
||||
|
||||
|
|
@ -24,9 +24,29 @@ extern "C" {
|
|||
|
||||
//Get the peripheral bus clock frequency
|
||||
static inline uint32_t bus_frequency(void) {
|
||||
return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
|
||||
return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1));
|
||||
}
|
||||
|
||||
#if defined(TARGET_KL43Z)
|
||||
|
||||
static inline uint32_t extosc_frequency(void) {
|
||||
return CPU_XTAL_CLK_HZ;
|
||||
}
|
||||
|
||||
static inline uint32_t mcgirc_frequency(void) {
|
||||
uint32_t mcgirc_clock = 0;
|
||||
|
||||
if (MCG->C1 & MCG_C1_IREFSTEN_MASK) {
|
||||
mcgirc_clock = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u;
|
||||
mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT);
|
||||
mcgirc_clock /= 1u + (MCG->MC & MCG_MC_LIRC_DIV2_MASK);
|
||||
}
|
||||
|
||||
return mcgirc_clock;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
//Get external oscillator (crystal) frequency
|
||||
static uint32_t extosc_frequency(void) {
|
||||
uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
|
||||
|
|
@ -35,7 +55,7 @@ static uint32_t extosc_frequency(void) {
|
|||
return MCGClock;
|
||||
|
||||
uint32_t divider, multiplier;
|
||||
#ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
|
||||
#ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
|
||||
if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
|
||||
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
|
||||
#endif
|
||||
|
|
@ -111,6 +131,8 @@ static uint32_t mcgpllfll_frequency(void) {
|
|||
//for the peripherals, this is however an unlikely setup
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -32,7 +32,11 @@ void gpio_init(gpio_t *obj, PinName pin) {
|
|||
|
||||
unsigned int port = (unsigned int)pin >> PORT_SHIFT;
|
||||
|
||||
#if defined(TARGET_KL43Z)
|
||||
GPIO_Type *reg = (GPIO_Type *)(GPIOA_BASE + port * 0x40);
|
||||
#else
|
||||
FGPIO_Type *reg = (FGPIO_Type *)(FPTA_BASE + port * 0x40);
|
||||
#endif
|
||||
obj->reg_set = ®->PSOR;
|
||||
obj->reg_clr = ®->PCOR;
|
||||
obj->reg_in = ®->PDIR;
|
||||
|
|
|
|||
|
|
@ -25,8 +25,10 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef TARGET_KL46Z
|
||||
#if defined(TARGET_KL46Z)
|
||||
#define UARTLP_Type UART0_Type
|
||||
#elif defined(TARGET_KL43Z)
|
||||
#define UARTLP_Type LPUART_Type
|
||||
#endif
|
||||
|
||||
struct gpio_irq_s {
|
||||
|
|
|
|||
|
|
@ -24,9 +24,11 @@ PinName port_pin(PortName port, int pin_n) {
|
|||
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
|
||||
obj->port = port;
|
||||
obj->mask = mask;
|
||||
|
||||
#if defined(TARGET_KL43Z)
|
||||
GPIO_Type *reg = (GPIO_Type *)(GPIOA_BASE + port * 0x40);
|
||||
#else
|
||||
FGPIO_Type *reg = (FGPIO_Type *)(FPTA_BASE + port * 0x40);
|
||||
|
||||
#endif
|
||||
obj->reg_out = ®->PDOR;
|
||||
obj->reg_in = ®->PDIR;
|
||||
obj->reg_dir = ®->PDDR;
|
||||
|
|
|
|||
|
|
@ -30,6 +30,16 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
|
|||
|
||||
uint32_t clkdiv = 0;
|
||||
float clkval;
|
||||
|
||||
#if defined(TARGET_KL43Z)
|
||||
if (mcgirc_frequency()) {
|
||||
SIM->SOPT2 |= SIM_SOPT2_TPMSRC(3); // Clock source: MCGIRCLK
|
||||
clkval = mcgirc_frequency() / 1000000.0f;
|
||||
} else {
|
||||
SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: IRC48M
|
||||
clkval = CPU_INT_IRC_CLK_HZ / 1000000.0f;
|
||||
}
|
||||
#else
|
||||
if (mcgpllfll_frequency()) {
|
||||
SIM->SOPT2 |= SIM_SOPT2_TPMSRC(1); // Clock source: MCGFLLCLK or MCGPLLCLK
|
||||
clkval = mcgpllfll_frequency() / 1000000.0f;
|
||||
|
|
@ -37,7 +47,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
|
|||
SIM->SOPT2 |= SIM_SOPT2_TPMSRC(2); // Clock source: ExtOsc
|
||||
clkval = extosc_frequency() / 1000000.0f;
|
||||
}
|
||||
|
||||
#endif
|
||||
while (clkval > 1) {
|
||||
clkdiv++;
|
||||
clkval /= 2.0;
|
||||
|
|
@ -46,9 +56,9 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
|
|||
}
|
||||
|
||||
pwm_clock = clkval;
|
||||
unsigned int port = (unsigned int)pin >> PORT_SHIFT;
|
||||
unsigned int port = (unsigned int)pin >> PORT_SHIFT;
|
||||
unsigned int tpm_n = (pwm >> TPM_SHIFT);
|
||||
unsigned int ch_n = (pwm & 0xFF);
|
||||
unsigned int ch_n = (pwm & 0xFF);
|
||||
|
||||
SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
|
||||
SIM->SCGC6 |= 1 << (SIM_SCGC6_TPM0_SHIFT + tpm_n);
|
||||
|
|
|
|||
|
|
@ -30,9 +30,11 @@ void sleep(void)
|
|||
//Very low-power stop mode
|
||||
void deepsleep(void)
|
||||
{
|
||||
#if ! defined(TARGET_KL43Z)
|
||||
//Check if PLL/FLL is enabled:
|
||||
uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
|
||||
|
||||
#endif
|
||||
|
||||
SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
|
||||
SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
|
||||
|
||||
|
|
@ -41,6 +43,7 @@ void deepsleep(void)
|
|||
|
||||
__WFI();
|
||||
|
||||
#if ! defined(TARGET_KL43Z)
|
||||
//Switch back to PLL as clock source if needed
|
||||
//The interrupt that woke up the device will run at reduced speed
|
||||
if (PLL_FLL_en) {
|
||||
|
|
@ -50,5 +53,5 @@ void deepsleep(void)
|
|||
#endif
|
||||
MCG->C1 &= ~MCG_C1_CLKS_MASK;
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -66,20 +66,31 @@ uint32_t us_ticker_read() {
|
|||
static void lptmr_isr(void);
|
||||
|
||||
static void lptmr_init(void) {
|
||||
uint32_t extosc;
|
||||
|
||||
/* Clock the timer */
|
||||
SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
|
||||
|
||||
/* Reset */
|
||||
LPTMR0->CSR = 0;
|
||||
|
||||
|
||||
#if defined(TARGET_KL43Z)
|
||||
/* Set interrupt handler */
|
||||
NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr);
|
||||
NVIC_EnableIRQ(LPTMR0_IRQn);
|
||||
|
||||
|
||||
MCG->C1 |= MCG_C1_IRCLKEN_MASK;
|
||||
extosc = mcgirc_frequency();
|
||||
#else
|
||||
/* Set interrupt handler */
|
||||
NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
|
||||
NVIC_EnableIRQ(LPTimer_IRQn);
|
||||
|
||||
|
||||
/* Clock at (1)MHz -> (1)tick/us */
|
||||
/* Check if the external oscillator can be divided to 1MHz */
|
||||
uint32_t extosc = extosc_frequency();
|
||||
|
||||
extosc = extosc_frequency();
|
||||
#endif
|
||||
if (extosc != 0) { //If external oscillator found
|
||||
if (extosc % 1000000u == 0) { //If it is a multiple if 1MHz
|
||||
extosc /= 1000000;
|
||||
|
|
@ -102,6 +113,12 @@ static void lptmr_init(void) {
|
|||
}
|
||||
}
|
||||
}
|
||||
#if defined(TARGET_KL43Z)
|
||||
//No suitable actual IRC oscillator clock -> Set it to (8MHz / divider)
|
||||
MCG->SC &= ~MCG_SC_FCRDIV_MASK;
|
||||
MCG->MC &= ~MCG->MC & MCG_MC_LIRC_DIV2_MASK;
|
||||
LPTMR0->PSR = LPTMR_PSR_PCS(0) | LPTMR_PSR_PRESCALE(2);
|
||||
#else
|
||||
//No suitable external oscillator clock -> Use fast internal oscillator (4MHz / divider)
|
||||
MCG->C1 |= MCG_C1_IRCLKEN_MASK;
|
||||
MCG->C2 |= MCG_C2_IRCS_MASK;
|
||||
|
|
@ -118,7 +135,7 @@ static void lptmr_init(void) {
|
|||
MCG->SC |= MCG_SC_FCRDIV(2);
|
||||
LPTMR0->PSR |= LPTMR_PSR_PBYP_MASK;
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
void us_ticker_disable_interrupt(void) {
|
||||
|
|
|
|||
|
|
@ -226,6 +226,9 @@ osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 0, NULL}
|
|||
#elif defined(TARGET_KL46Z)
|
||||
#define INITIAL_SP (0x20006000UL)
|
||||
|
||||
#elif defined(TARGET_KL43Z)
|
||||
#define INITIAL_SP (0x20006000UL)
|
||||
|
||||
#elif defined(TARGET_KL05Z)
|
||||
#define INITIAL_SP (0x20000C00UL)
|
||||
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
// <i> Default: 6
|
||||
#ifndef OS_TASKCNT
|
||||
# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE)
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE)
|
||||
# define OS_TASKCNT 14
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
|
||||
|| defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \
|
||||
|
|
@ -64,7 +64,7 @@
|
|||
// <o>Scheduler (+ interrupts) stack size [bytes] <64-4096:8><#/4>
|
||||
#ifndef OS_SCHEDULERSTKSIZE
|
||||
# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4337) || defined(TARGET_LPC1347) || defined(TARGET_K64F) || defined(TARGET_STM32F401RE)\
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE)
|
||||
|| defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F407) || defined(TARGET_F407VG) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549) || defined(TARGET_LPC11U68) || defined(TARGET_NRF51822) || defined(TARGET_STM32F411RE)
|
||||
# define OS_SCHEDULERSTKSIZE 256
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) \
|
||||
|| defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \
|
||||
|
|
@ -117,7 +117,7 @@
|
|||
# elif defined(TARGET_LPC1347) || defined(TARGET_STM32F303VC) || defined(TARGET_LPC1549)
|
||||
# define OS_CLOCK 72000000
|
||||
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68)
|
||||
# elif defined(TARGET_LPC11U24) || defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501) || defined(TARGET_LPCCAPPUCCINO) || defined(TARGET_LPC1114) || defined(TARGET_KL25Z) || defined(TARGET_KL05Z) || defined(TARGET_KL46Z) || defined(TARGET_KL43Z) || defined(TARGET_STM32F051R8) || defined(TARGET_LPC11U68)
|
||||
# define OS_CLOCK 48000000
|
||||
|
||||
# elif defined(TARGET_LPC812)
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
|
|||
|
||||
('KL05Z', ('ARM', 'uARM', 'GCC_ARM')),
|
||||
('KL25Z', ('ARM', 'GCC_ARM')),
|
||||
('KL43Z', ('ARM', 'GCC_ARM')),
|
||||
('KL46Z', ('ARM', 'GCC_ARM')),
|
||||
('K64F', ('ARM', 'GCC_ARM')),
|
||||
('K22F', ('ARM', 'GCC_ARM')),
|
||||
|
|
@ -63,7 +64,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
|
|||
('NUCLEO_L053R8', ('ARM', 'uARM')),
|
||||
('NUCLEO_L152RE', ('ARM', 'uARM')),
|
||||
|
||||
('ARCH_MAX', ('ARM', 'GCC_ARM')),
|
||||
('ARCH_MAX', ('ARM', 'GCC_ARM')),
|
||||
|
||||
('NRF51822', ('ARM', 'GCC_ARM')),
|
||||
('HRM1017', ('ARM', 'GCC_ARM')),
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ build_list = (
|
|||
|
||||
{ "target": "KL05Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
|
||||
{ "target": "KL25Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
|
||||
{ "target": "KL43Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
|
||||
{ "target": "KL46Z", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
|
||||
{ "target": "K20D50M", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
|
||||
{ "target": "K64F", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
# This file was automagically generated by mbed.org. For more information,
|
||||
# see http://mbed.org/handbook/Exporting-to-GCC-ARM-Embedded
|
||||
|
||||
GCC_BIN =
|
||||
PROJECT = {{name}}
|
||||
OBJECTS = {% for f in to_be_compiled %}{{f}} {% endfor %}
|
||||
SYS_OBJECTS = {% for f in object_files %}{{f}} {% endfor %}
|
||||
INCLUDE_PATHS = {% for p in include_paths %}-I{{p}} {% endfor %}
|
||||
LIBRARY_PATHS = {% for p in library_paths %}-L{{p}} {% endfor %}
|
||||
LIBRARIES = {% for lib in libraries %}-l{{lib}} {% endfor %}
|
||||
LINKER_SCRIPT = {{linker_script}}
|
||||
|
||||
###############################################################################
|
||||
AS = $(GCC_BIN)arm-none-eabi-as
|
||||
CC = $(GCC_BIN)arm-none-eabi-gcc
|
||||
CPP = $(GCC_BIN)arm-none-eabi-g++
|
||||
LD = $(GCC_BIN)arm-none-eabi-gcc
|
||||
OBJCOPY = $(GCC_BIN)arm-none-eabi-objcopy
|
||||
|
||||
CPU = -mcpu=cortex-m0plus -mthumb
|
||||
CC_FLAGS = $(CPU) -c -g -fno-common -fmessage-length=0 -Wall -fno-exceptions -ffunction-sections -fdata-sections -fomit-frame-pointer
|
||||
CC_SYMBOLS = {% for s in symbols %}-D{{s}} {% endfor %}
|
||||
|
||||
LD_FLAGS = -mcpu=cortex-m0plus -mthumb -Wl,--gc-sections --specs=nano.specs -u _printf_float -u _scanf_float
|
||||
LD_SYS_LIBS = -lstdc++ -lsupc++ -lm -lc -lgcc -lnosys
|
||||
|
||||
ifeq ($(DEBUG), 1)
|
||||
CC_FLAGS += -DDEBUG -O0
|
||||
else
|
||||
CC_FLAGS += -DNDEBUG -Os
|
||||
endif
|
||||
|
||||
all: $(PROJECT).bin
|
||||
|
||||
clean:
|
||||
rm -f $(PROJECT).bin $(PROJECT).elf $(OBJECTS)
|
||||
|
||||
.s.o:
|
||||
$(AS) $(CPU) -o $@ $<
|
||||
|
||||
.c.o:
|
||||
$(CC) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu99 $(INCLUDE_PATHS) -o $@ $<
|
||||
|
||||
.cpp.o:
|
||||
$(CPP) $(CC_FLAGS) $(CC_SYMBOLS) -std=gnu++98 $(INCLUDE_PATHS) -o $@ $<
|
||||
|
||||
|
||||
$(PROJECT).elf: $(OBJECTS) $(SYS_OBJECTS)
|
||||
$(LD) $(LD_FLAGS) -T$(LINKER_SCRIPT) $(LIBRARY_PATHS) -o $@ $^ $(LIBRARIES) $(LD_SYS_LIBS) $(LIBRARIES) $(LD_SYS_LIBS)
|
||||
|
||||
$(PROJECT).bin: $(PROJECT).elf
|
||||
$(OBJCOPY) -O binary $< $@
|
||||
|
|
@ -27,6 +27,7 @@ class GccArm(Exporter):
|
|||
'LPC1549',
|
||||
'KL05Z',
|
||||
'KL25Z',
|
||||
'KL43Z',
|
||||
'KL46Z',
|
||||
'K64F',
|
||||
'K22F',
|
||||
|
|
|
|||
|
|
@ -29,8 +29,8 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>Variant</name>
|
||||
<version>20</version>
|
||||
<state>40</state>
|
||||
<version>21</version>
|
||||
<state>38</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GEndianMode</name>
|
||||
|
|
@ -61,7 +61,7 @@
|
|||
<option>
|
||||
<name>FPU</name>
|
||||
<version>2</version>
|
||||
<state>5</state>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OGCoreOrChip</name>
|
||||
|
|
@ -87,7 +87,7 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>OGLastSavedByProductVersion</name>
|
||||
<state>7.20.1.7306</state>
|
||||
<state>7.30.1.7765</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GeneralEnableMisra</name>
|
||||
|
|
@ -137,17 +137,17 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>GFPUCoreSlave</name>
|
||||
<version>20</version>
|
||||
<state>40</state>
|
||||
<version>21</version>
|
||||
<state>38</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GBECoreSlave</name>
|
||||
<version>20</version>
|
||||
<state>40</state>
|
||||
<version>21</version>
|
||||
<state>38</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OGUseCmsis</name>
|
||||
<state>1</state>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>OGUseCmsisDspLib</name>
|
||||
|
|
@ -172,7 +172,9 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>CCDefines</name>
|
||||
<state></state>
|
||||
{% for s in symbols %}
|
||||
<state>{{s}}</state>
|
||||
{% endfor %}
|
||||
</option>
|
||||
<option>
|
||||
<name>CCPreprocFile</name>
|
||||
|
|
@ -977,7 +979,7 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>Variant</name>
|
||||
<version>20</version>
|
||||
<version>21</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
|
|
@ -1085,12 +1087,12 @@
|
|||
</option>
|
||||
<option>
|
||||
<name>GFPUCoreSlave</name>
|
||||
<version>20</version>
|
||||
<version>21</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
<name>GBECoreSlave</name>
|
||||
<version>20</version>
|
||||
<version>21</version>
|
||||
<state>0</state>
|
||||
</option>
|
||||
<option>
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ class Uvision4(Exporter):
|
|||
'LPC11U24',
|
||||
'KL05Z',
|
||||
'KL25Z',
|
||||
'KL43Z',
|
||||
'KL46Z',
|
||||
'K64F',
|
||||
'K22F',
|
||||
|
|
|
|||
|
|
@ -0,0 +1,204 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Extensions>
|
||||
<cExt>*.c</cExt>
|
||||
<aExt>*.s*; *.src; *.a*</aExt>
|
||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
|
||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>mbed FRDM-KL43Z</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>8000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>1</RunSim>
|
||||
<RunTarget>0</RunTarget>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>14</CpuCode>
|
||||
<Books>
|
||||
<Book>
|
||||
<Number>0</Number>
|
||||
<Title>Data Sheet</Title>
|
||||
<Path>DATASHTS\Freescale\K40PB.pdf</Path>
|
||||
</Book>
|
||||
<Book>
|
||||
<Number>1</Number>
|
||||
<Title>Technical Reference Manual</Title>
|
||||
<Path>datashts\arm\cortex_m0p\r0p0\DDI0484B_CORTEX_M0P_R0P0_TRM.PDF</Path>
|
||||
</Book>
|
||||
<Book>
|
||||
<Number>2</Number>
|
||||
<Title>Generic User Guide</Title>
|
||||
<Path>datashts\arm\cortex_m0p\r0p0\DUI0662A_CORTEX_M0P_R0P0_DGUG.PDF</Path>
|
||||
</Book>
|
||||
</Books>
|
||||
<DllOpt>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
|
||||
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
|
||||
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||
</DllOpt>
|
||||
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>14</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\CMSIS_AGDI.dll</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>ULP2CM3</Key>
|
||||
<Name>-O2510 -S0 -C0 -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000)</Name>
|
||||
</SetRegEntry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>CMSIS_AGDI</Key>
|
||||
<Name>-X"MBED CMSIS-DAP" -UA000000001 -O462 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(0BC11477) -L00(0) -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>0</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>src</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>8</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<ColumnNumber>0</ColumnNumber>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<TopLine>1</TopLine>
|
||||
<CurrentLine>2</CurrentLine>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>main.cpp</PathWithFileName>
|
||||
<FilenameWithoutPath>main.cpp</FilenameWithoutPath>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
|
|
@ -0,0 +1,423 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
|
||||
|
||||
<SchemaVersion>1.1</SchemaVersion>
|
||||
|
||||
<Header>###This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Uvision </Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>mbed FRDM-KL43Z</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>MKL43Z256xxx4</Device>
|
||||
<Vendor>Freescale Semiconductor</Vendor>
|
||||
<Cpu>IRAM(0x1FFFE000-0x1FFFFFFF) IRAM2(0x20000000-0x20005FFF) IROM(0x0-0x3FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0+") ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile>"STARTUP\Freescale\Kinetis\startup_MKL43Z4.s" ("Freescale MKL43Zxxxxxx4 Startup Code")</StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-O2510 -S0 -C0 -FO15 -FD20000000 -FC800 -FN1 -FF0MK_P256_48MHZ -FS00 -FL040000)</FlashDriverDll>
|
||||
<DeviceId>6834</DeviceId>
|
||||
<RegisterFile>MKL43Z4.H</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>SFD\Freescale\Kinetis\MKL43Z4.sfr</SFDFile>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath>Freescale\Kinetis\</RegisterFilePath>
|
||||
<DBRegisterFilePath>Freescale\Kinetis\</DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\build\</OutputDirectory>
|
||||
<OutputName>{{name}}</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\build\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>1</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name>fromelf --bin -o build\{{name}}_KL25Z.bin build\{{name}}.axf</UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments></SimDllArguments>
|
||||
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments></TargetDllArguments>
|
||||
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>14</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver>BIN\CMSIS_AGDI.dll</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4105</DriverSelection>
|
||||
</Flash1>
|
||||
<Flash2>BIN\CMSIS_AGDI.dll</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M0+"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>0</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>1</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>0</RvdsVP>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>8</StupSel>
|
||||
<useUlib>0</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<RoSelD>3</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>0</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>1</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1ffff000</StartAddress>
|
||||
<Size>0x1000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x20000</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x40000</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x1fffe000</StartAddress>
|
||||
<Size>0x2000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x6000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>1</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>0</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<VariousControls>
|
||||
<MiscControls>{% for flag in flags %}{{flag}} {% endfor %}</MiscControls>
|
||||
<Define>{% for s in symbols %} {{s}}, {% endfor %}</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath> {% for path in include_paths %} {{path}}; {% endfor %} </IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>0</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x10000000</DataAddressRange>
|
||||
<ScatterFile>{{scatter_file}}</ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc>
|
||||
{% for file in object_files %}
|
||||
{{file}}
|
||||
{% endfor %}
|
||||
</Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
{% for group,files in source_files %}
|
||||
<Group>
|
||||
<GroupName>{{group}}</GroupName>
|
||||
<Files>
|
||||
{% for file in files %}
|
||||
<File>
|
||||
<FileName>{{file.name}}</FileName>
|
||||
<FileType>{{file.type}}</FileType>
|
||||
<FilePath>{{file.path}}</FilePath>
|
||||
{%if file.type == "1" %}
|
||||
<FileOption>
|
||||
<FileArmAds>
|
||||
<Cads>
|
||||
<VariousControls>
|
||||
<MiscControls>--c99</MiscControls>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
</FileArmAds>
|
||||
</FileOption>
|
||||
{% endif %}
|
||||
</File>
|
||||
{% endfor %}
|
||||
</Files>
|
||||
</Group>
|
||||
{% endfor %}
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
</Project>
|
||||
|
|
@ -132,6 +132,16 @@ class KL25Z(Target):
|
|||
self.detect_code = "0200"
|
||||
|
||||
|
||||
class KL43Z(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
self.core = "Cortex-M0+"
|
||||
self.extra_labels = ['Freescale', 'KLXX']
|
||||
self.supported_toolchains = ["GCC_ARM", "ARM"]
|
||||
self.supported_form_factors = ["ARDUINO"]
|
||||
self.is_disk_virtual = True
|
||||
|
||||
|
||||
class KL46Z(Target):
|
||||
def __init__(self):
|
||||
Target.__init__(self)
|
||||
|
|
@ -737,6 +747,7 @@ TARGETS = [
|
|||
LPC11U24_301(),
|
||||
KL05Z(),
|
||||
KL25Z(),
|
||||
KL43Z(),
|
||||
KL46Z(),
|
||||
K20D50M(),
|
||||
K64F(),
|
||||
|
|
|
|||
|
|
@ -369,6 +369,8 @@ class mbedToolchain:
|
|||
resources.lib_dirs.add(root)
|
||||
|
||||
elif ext == self.LINKER_EXT:
|
||||
if resources.linker_script is not None:
|
||||
self.info("Warning: Multiple linker scripts detected: %s -> %s" % (resources.linker_script, file_path))
|
||||
resources.linker_script = file_path
|
||||
|
||||
elif ext == '.lib':
|
||||
|
|
|
|||
Loading…
Reference in New Issue