diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c
index 74c28aba2c..cb430a4164 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c
@@ -26,9 +26,9 @@
void init_cycfg_all(void)
{
+ init_cycfg_system();
init_cycfg_clocks();
+ init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
- init_cycfg_platform();
- init_cycfg_routing();
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h
index ac6033d2bd..9abc7f0f4a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h
@@ -30,11 +30,11 @@ extern "C" {
#endif
#include "cycfg_notices.h"
+#include "cycfg_system.h"
#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
-#include "cycfg_platform.h"
-#include "cycfg_routing.h"
void init_cycfg_all(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c
index 9a6a4e3cf9..8494d2bc11 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c
@@ -32,14 +32,10 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
- Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
- Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-
- Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
- Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 0U);
- Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h
index ce944e4bd0..34da2e34d9 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h
@@ -32,14 +32,15 @@
extern "C" {
#endif
-#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_0_NUM 0U
-#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_1_NUM 1U
-#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_2_NUM 2U
-#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_3_NUM 3U
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_CLK_DIV_NUM 0U
+#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
+#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
void init_cycfg_clocks(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c
index 211f24a113..d8a12803e7 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c
@@ -28,7 +28,7 @@ cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
-const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
+const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
.slaveAddress1 = 8U,
@@ -36,16 +36,16 @@ const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
-const cy_stc_scb_uart_config_t KITPROG_UART_config =
+const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
- .oversample = 12,
+ .oversample = 8,
.enableMsbFirst = false,
- .dataWidth = 9UL,
+ .dataWidth = 8UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
@@ -64,14 +64,14 @@ const cy_stc_scb_uart_config_t KITPROG_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
-const cy_stc_smif_config_t QSPI_config =
+const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
- .deselectDelay = QSPI_DESELECT_DELAY,
+ .deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
-const cy_stc_mcwdt_config_t MCWDT0_config =
+const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
.c1Match = 32768U,
@@ -84,7 +84,7 @@ const cy_stc_mcwdt_config_t MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
-const cy_stc_rtc_config_t RTC_config =
+const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
.min = 0U,
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h
index 230df68ef5..7ae726a324 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h
@@ -38,6 +38,7 @@
extern "C" {
#endif
+#define CYBSP_BLE_ENABLED 1U
#define CY_BLE_CORE_CORTEX_M4 4U
#define CY_BLE_CORE_CORTEX_M0P 0U
#define CY_BLE_CORE_DUAL 255U
@@ -45,9 +46,10 @@ extern "C" {
#define CY_BLE_CORE 4U
#endif
#define CY_BLE_IRQ bless_interrupt_IRQn
+#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
-#define CY_CAPSENSE_PERI_CLK 50000000u
+#define CY_CAPSENSE_PERI_CLK 100000000u
#define CY_CAPSENSE_VDDA_MV 3300u
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
#define CY_CAPSENSE_PERI_DIV_INDEX 0u
@@ -78,45 +80,50 @@ extern "C" {
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
-#define CapSense_HW CSD0
-#define CapSense_IRQ csd_interrupt_IRQn
-#define CSD_COMM_HW SCB3
-#define CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define KITPROG_UART_HW SCB5
-#define KITPROG_UART_IRQ scb_5_interrupt_IRQn
-#define QSPI_HW SMIF0
-#define QSPI_IRQ smif_interrupt_IRQn
-#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
-#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
-#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
-#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
-#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
-#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
-#define QSPI_DATALINES0_1 (1UL)
-#define QSPI_DATALINES2_3 (1UL)
-#define QSPI_DATALINES4_5 (0UL)
-#define QSPI_DATALINES6_7 (0UL)
-#define QSPI_SS0 (1UL)
-#define QSPI_SS1 (0UL)
-#define QSPI_SS2 (0UL)
-#define QSPI_SS3 (0UL)
-#define QSPI_DESELECT_DELAY 7
-#define MCWDT0_HW MCWDT_STRUCT0
-#define RTC_10_MONTH_OFFSET (28U)
-#define RTC_MONTH_OFFSET (24U)
-#define RTC_10_DAY_OFFSET (20U)
-#define RTC_DAY_OFFSET (16U)
-#define RTC_1000_YEAR_OFFSET (12U)
-#define RTC_100_YEAR_OFFSET (8U)
-#define RTC_10_YEAR_OFFSET (4U)
-#define RTC_YEAR_OFFSET (0U)
+#define CYBSP_CSD_HW CSD0
+#define CYBSP_CSD_IRQ csd_interrupt_IRQn
+#define CYBSP_CSD_COMM_ENABLED 1U
+#define CYBSP_CSD_COMM_HW SCB3
+#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
+#define CYBSP_DEBUG_UART_ENABLED 1U
+#define CYBSP_DEBUG_UART_HW SCB5
+#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
+#define CYBSP_QSPI_ENABLED 1U
+#define CYBSP_QSPI_HW SMIF0
+#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
+#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
+#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
+#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
+#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
+#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
+#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
+#define CYBSP_QSPI_DATALINES0_1 (1UL)
+#define CYBSP_QSPI_DATALINES2_3 (1UL)
+#define CYBSP_QSPI_DATALINES4_5 (0UL)
+#define CYBSP_QSPI_DATALINES6_7 (0UL)
+#define CYBSP_QSPI_SS0 (1UL)
+#define CYBSP_QSPI_SS1 (0UL)
+#define CYBSP_QSPI_SS2 (0UL)
+#define CYBSP_QSPI_SS3 (0UL)
+#define CYBSP_QSPI_DESELECT_DELAY 7
+#define CYBSP_MCWDT0_ENABLED 1U
+#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
+#define CYBSP_RTC_ENABLED 1U
+#define CYBSP_RTC_10_MONTH_OFFSET (28U)
+#define CYBSP_RTC_MONTH_OFFSET (24U)
+#define CYBSP_RTC_10_DAY_OFFSET (20U)
+#define CYBSP_RTC_DAY_OFFSET (16U)
+#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
+#define CYBSP_RTC_100_YEAR_OFFSET (8U)
+#define CYBSP_RTC_10_YEAR_OFFSET (4U)
+#define CYBSP_RTC_YEAR_OFFSET (0U)
extern cy_stc_csd_context_t cy_csd_0_context;
-extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
-extern const cy_stc_smif_config_t QSPI_config;
-extern const cy_stc_mcwdt_config_t MCWDT0_config;
-extern const cy_stc_rtc_config_t RTC_config;
+extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
+extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
+extern const cy_stc_rtc_config_t CYBSP_RTC_config;
void init_cycfg_peripherals(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c
index 9f927f5c86..a24b492674 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.c
@@ -24,512 +24,512 @@
#include "cycfg_pins.h"
-const cy_stc_gpio_pin_config_t WCO_IN_config =
+const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = WCO_IN_HSIOM,
+ .hsiom = CYBSP_WCO_IN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t WCO_OUT_config =
+const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = WCO_OUT_HSIOM,
+ .hsiom = CYBSP_WCO_OUT_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_RED_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_RED_HSIOM,
+ .hsiom = CYBSP_LED_RED_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SW2_config =
+const cy_stc_gpio_pin_config_t CYBSP_BTN2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
- .hsiom = SW2_HSIOM,
+ .hsiom = CYBSP_BTN2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_BLUE_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_BLUE_HSIOM,
+ .hsiom = CYBSP_LED_BLUE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_SS0_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = QSPI_SS0_HSIOM,
+ .hsiom = CYBSP_QSPI_SS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA3_HSIOM,
+ .hsiom = CYBSP_QSPI_D3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA2_HSIOM,
+ .hsiom = CYBSP_QSPI_D2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA1_HSIOM,
+ .hsiom = CYBSP_QSPI_D1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA0_HSIOM,
+ .hsiom = CYBSP_QSPI_D0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = QSPI_SPI_CLOCK_HSIOM,
+ .hsiom = CYBSP_QSPI_SCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED9_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED9_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED9_HSIOM,
+ .hsiom = CYBSP_LED9_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_TX_HSIOM,
+ .hsiom = CYBSP_CSD_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_GREEN_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_GREEN_HSIOM,
+ .hsiom = CYBSP_LED_GREEN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ioss_0_port_1_pin_4_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED8_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = ioss_0_port_1_pin_4_HSIOM,
+ .hsiom = CYBSP_LED8_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED8_config =
+const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED8_HSIOM,
+ .hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t UART_TX_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = UART_TX_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t EZI2C_SCL_config =
+const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
- .hsiom = EZI2C_SCL_HSIOM,
+ .hsiom = CYBSP_EZI2C_SCL_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t EZI2C_SDA_config =
+const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
- .hsiom = EZI2C_SDA_HSIOM,
+ .hsiom = CYBSP_EZI2C_SDA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWO_config =
+const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = SWO_HSIOM,
+ .hsiom = CYBSP_SWO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWDIO_config =
+const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
- .hsiom = SWDIO_HSIOM,
+ .hsiom = CYBSP_SWDIO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWDCK_config =
+const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
- .hsiom = SWDCK_HSIOM,
+ .hsiom = CYBSP_SWDCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CINA_config =
+const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CINA_HSIOM,
+ .hsiom = CYBSP_CINA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CINB_config =
+const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CINB_HSIOM,
+ .hsiom = CYBSP_CINB_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CMOD_config =
+const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CMOD_HSIOM,
+ .hsiom = CYBSP_CMOD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_BTN0_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_BTN0_HSIOM,
+ .hsiom = CYBSP_CSD_BTN0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_BTN1_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_BTN1_HSIOM,
+ .hsiom = CYBSP_CSD_BTN1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD0_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD0_HSIOM,
+ .hsiom = CYBSP_CSD_SLD0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD1_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD1_HSIOM,
+ .hsiom = CYBSP_CSD_SLD1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD2_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD2_HSIOM,
+ .hsiom = CYBSP_CSD_SLD2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD3_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD3_HSIOM,
+ .hsiom = CYBSP_CSD_SLD3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD4_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD4_HSIOM,
+ .hsiom = CYBSP_CSD_SLD4_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
@@ -540,48 +540,48 @@ const cy_stc_gpio_pin_config_t CSD_SLD4_config =
void init_cycfg_pins(void)
{
- Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config);
+ Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
- Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config);
+ Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
- Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
- Cy_GPIO_Pin_Init(SW2_PORT, SW2_PIN, &SW2_config);
+ Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
- Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
- Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
- Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
- Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
- Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
- Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
- Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
- Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
- Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
- Cy_GPIO_Pin_Init(ioss_0_port_1_pin_4_PORT, ioss_0_port_1_pin_4_PIN, &ioss_0_port_1_pin_4_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
- Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config);
+ Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
- Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config);
+ Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
- Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config);
+ Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
- Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config);
+ Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
- Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config);
+ Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
- Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config);
+ Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
- Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config);
+ Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h
index 874eac99dc..af4127be86 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_pins.h
@@ -33,358 +33,391 @@
extern "C" {
#endif
-#define WCO_IN_PORT GPIO_PRT0
-#define WCO_IN_PIN 0U
-#define WCO_IN_NUM 0U
-#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define WCO_IN_INIT_DRIVESTATE 1
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_0_HSIOM
#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define WCO_OUT_PORT GPIO_PRT0
-#define WCO_OUT_PIN 1U
-#define WCO_OUT_NUM 1U
-#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define WCO_OUT_INIT_DRIVESTATE 1
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_1_HSIOM
#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define LED_RED_PORT GPIO_PRT0
-#define LED_RED_PIN 3U
-#define LED_RED_NUM 3U
-#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_RED_INIT_DRIVESTATE 1
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_LED_RED_ENABLED 1U
+#define CYBSP_LED_RED_PORT GPIO_PRT0
+#define CYBSP_LED_RED_PIN 3U
+#define CYBSP_LED_RED_NUM 3U
+#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED_RED_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_3_HSIOM
#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
-#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
-#define SW2_PORT GPIO_PRT0
-#define SW2_PIN 4U
-#define SW2_NUM 4U
-#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define SW2_INIT_DRIVESTATE 1
+#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
+#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_BTN2_ENABLED 1U
+#define CYBSP_BTN2_PORT GPIO_PRT0
+#define CYBSP_BTN2_PIN 4U
+#define CYBSP_BTN2_NUM 4U
+#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_BTN2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define SW2_IRQ ioss_interrupts_gpio_0_IRQn
-#define LED_BLUE_PORT GPIO_PRT11
-#define LED_BLUE_PIN 1U
-#define LED_BLUE_NUM 1U
-#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_BLUE_INIT_DRIVESTATE 1
+#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
+#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_LED_BLUE_ENABLED 1U
+#define CYBSP_LED_BLUE_PORT GPIO_PRT11
+#define CYBSP_LED_BLUE_PIN 1U
+#define CYBSP_LED_BLUE_NUM 1U
+#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_1_HSIOM
#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_SS0_PORT GPIO_PRT11
-#define QSPI_SS0_PIN 2U
-#define QSPI_SS0_NUM 2U
-#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define QSPI_SS0_INIT_DRIVESTATE 1
+#define CYBSP_LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
+#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_SS_ENABLED 1U
+#define CYBSP_QSPI_SS_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS_PIN 2U
+#define CYBSP_QSPI_SS_NUM 2U
+#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_2_HSIOM
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA3_PORT GPIO_PRT11
-#define QSPI_DATA3_PIN 3U
-#define QSPI_DATA3_NUM 3U
-#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA3_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D3_ENABLED 1U
+#define CYBSP_QSPI_D3_PORT GPIO_PRT11
+#define CYBSP_QSPI_D3_PIN 3U
+#define CYBSP_QSPI_D3_NUM 3U
+#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_3_HSIOM
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA2_PORT GPIO_PRT11
-#define QSPI_DATA2_PIN 4U
-#define QSPI_DATA2_NUM 4U
-#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA2_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D2_ENABLED 1U
+#define CYBSP_QSPI_D2_PORT GPIO_PRT11
+#define CYBSP_QSPI_D2_PIN 4U
+#define CYBSP_QSPI_D2_NUM 4U
+#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_4_HSIOM
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA1_PORT GPIO_PRT11
-#define QSPI_DATA1_PIN 5U
-#define QSPI_DATA1_NUM 5U
-#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA1_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D1_ENABLED 1U
+#define CYBSP_QSPI_D1_PORT GPIO_PRT11
+#define CYBSP_QSPI_D1_PIN 5U
+#define CYBSP_QSPI_D1_NUM 5U
+#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_5_HSIOM
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA0_PORT GPIO_PRT11
-#define QSPI_DATA0_PIN 6U
-#define QSPI_DATA0_NUM 6U
-#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA0_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D0_ENABLED 1U
+#define CYBSP_QSPI_D0_PORT GPIO_PRT11
+#define CYBSP_QSPI_D0_PIN 6U
+#define CYBSP_QSPI_D0_NUM 6U
+#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_6_HSIOM
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_SPI_CLOCK_PORT GPIO_PRT11
-#define QSPI_SPI_CLOCK_PIN 7U
-#define QSPI_SPI_CLOCK_NUM 7U
-#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_SCK_ENABLED 1U
+#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SCK_PIN 7U
+#define CYBSP_QSPI_SCK_NUM 7U
+#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_7_HSIOM
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define LED9_PORT GPIO_PRT13
-#define LED9_PIN 7U
-#define LED9_NUM 7U
-#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED9_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_LED9_ENABLED 1U
+#define CYBSP_LED9_PORT GPIO_PRT13
+#define CYBSP_LED9_PIN 7U
+#define CYBSP_LED9_NUM 7U
+#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED9_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_7_HSIOM
#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define LED9_IRQ ioss_interrupts_gpio_13_IRQn
-#define CSD_TX_PORT GPIO_PRT1
-#define CSD_TX_PIN 0U
-#define CSD_TX_NUM 0U
-#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_TX_INIT_DRIVESTATE 1
+#define CYBSP_LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
+#define CYBSP_LED9_IRQ ioss_interrupts_gpio_13_IRQn
+#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_0_HSIOM
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define LED_GREEN_PORT GPIO_PRT1
-#define LED_GREEN_PIN 1U
-#define LED_GREEN_NUM 1U
-#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_GREEN_INIT_DRIVESTATE 1
+#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_LED_GREEN_ENABLED 1U
+#define CYBSP_LED_GREEN_PORT GPIO_PRT1
+#define CYBSP_LED_GREEN_PIN 1U
+#define CYBSP_LED_GREEN_NUM 1U
+#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_1_HSIOM
#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
-#define ioss_0_port_1_pin_4_PORT GPIO_PRT1
-#define ioss_0_port_1_pin_4_PIN 4U
-#define ioss_0_port_1_pin_4_NUM 4U
-#define ioss_0_port_1_pin_4_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define ioss_0_port_1_pin_4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_4_HSIOM
- #define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define ioss_0_port_1_pin_4_IRQ ioss_interrupts_gpio_1_IRQn
-#define LED8_PORT GPIO_PRT1
-#define LED8_PIN 5U
-#define LED8_NUM 5U
-#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED8_INIT_DRIVESTATE 1
+#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
+#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_LED8_ENABLED 1U
+#define CYBSP_LED8_PORT GPIO_PRT1
+#define CYBSP_LED8_PIN 5U
+#define CYBSP_LED8_NUM 5U
+#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED8_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_5_HSIOM
#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define LED8_IRQ ioss_interrupts_gpio_1_IRQn
-#define UART_TX_PORT GPIO_PRT5
-#define UART_TX_PIN 1U
-#define UART_TX_NUM 1U
-#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define UART_TX_INIT_DRIVESTATE 1
+#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
+#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_DEBUG_UART_RX_ENABLED 1U
+#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
+#define CYBSP_DEBUG_UART_RX_PIN 0U
+#define CYBSP_DEBUG_UART_RX_NUM 0U
+#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_5_pin_0_HSIOM
+ #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
+#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
+#define CYBSP_DEBUG_UART_TX_ENABLED 1U
+#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
+#define CYBSP_DEBUG_UART_TX_PIN 1U
+#define CYBSP_DEBUG_UART_TX_NUM 1U
+#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_1_HSIOM
#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#define EZI2C_SCL_PORT GPIO_PRT6
-#define EZI2C_SCL_PIN 0U
-#define EZI2C_SCL_NUM 0U
-#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define EZI2C_SCL_INIT_DRIVESTATE 1
+#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
+#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_0_HSIOM
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define EZI2C_SDA_PORT GPIO_PRT6
-#define EZI2C_SDA_PIN 1U
-#define EZI2C_SDA_NUM 1U
-#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define EZI2C_SDA_INIT_DRIVESTATE 1
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_1_HSIOM
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWO_PORT GPIO_PRT6
-#define SWO_PIN 4U
-#define SWO_NUM 4U
-#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define SWO_INIT_DRIVESTATE 1
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWDIO_PORT GPIO_PRT6
-#define SWDIO_PIN 6U
-#define SWDIO_NUM 6U
-#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define SWDIO_INIT_DRIVESTATE 1
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_6_HSIOM
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWDCK_PORT GPIO_PRT6
-#define SWDCK_PIN 7U
-#define SWDCK_NUM 7U
-#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define SWDCK_INIT_DRIVESTATE 1
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CINA_PORT GPIO_PRT7
-#define CINA_PIN 1U
-#define CINA_NUM 1U
-#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CINA_INIT_DRIVESTATE 1
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_1_HSIOM
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CINB_PORT GPIO_PRT7
-#define CINB_PIN 2U
-#define CINB_NUM 2U
-#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CINB_INIT_DRIVESTATE 1
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_2_HSIOM
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CMOD_PORT GPIO_PRT7
-#define CMOD_PIN 7U
-#define CMOD_NUM 7U
-#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CMOD_INIT_DRIVESTATE 1
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_7_HSIOM
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CSD_BTN0_PORT GPIO_PRT8
-#define CSD_BTN0_PIN 1U
-#define CSD_BTN0_NUM 1U
-#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_BTN0_INIT_DRIVESTATE 1
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_1_HSIOM
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_BTN1_PORT GPIO_PRT8
-#define CSD_BTN1_PIN 2U
-#define CSD_BTN1_NUM 2U
-#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_BTN1_INIT_DRIVESTATE 1
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_2_HSIOM
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD0_PORT GPIO_PRT8
-#define CSD_SLD0_PIN 3U
-#define CSD_SLD0_NUM 3U
-#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD0_INIT_DRIVESTATE 1
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_3_HSIOM
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD1_PORT GPIO_PRT8
-#define CSD_SLD1_PIN 4U
-#define CSD_SLD1_NUM 4U
-#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD1_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_4_HSIOM
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD2_PORT GPIO_PRT8
-#define CSD_SLD2_PIN 5U
-#define CSD_SLD2_NUM 5U
-#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD2_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_5_HSIOM
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD3_PORT GPIO_PRT8
-#define CSD_SLD3_PIN 6U
-#define CSD_SLD3_NUM 6U
-#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD3_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_6_HSIOM
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD4_PORT GPIO_PRT8
-#define CSD_SLD4_PIN 7U
-#define CSD_SLD4_NUM 7U
-#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD4_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_7_HSIOM
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-extern const cy_stc_gpio_pin_config_t WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t LED_RED_config;
-extern const cy_stc_gpio_pin_config_t SW2_config;
-extern const cy_stc_gpio_pin_config_t LED_BLUE_config;
-extern const cy_stc_gpio_pin_config_t QSPI_SS0_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config;
-extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config;
-extern const cy_stc_gpio_pin_config_t LED9_config;
-extern const cy_stc_gpio_pin_config_t CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t LED_GREEN_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_1_pin_4_config;
-extern const cy_stc_gpio_pin_config_t LED8_config;
-extern const cy_stc_gpio_pin_config_t UART_TX_config;
-extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t SWO_config;
-extern const cy_stc_gpio_pin_config_t SWDIO_config;
-extern const cy_stc_gpio_pin_config_t SWDCK_config;
-extern const cy_stc_gpio_pin_config_t CINA_config;
-extern const cy_stc_gpio_pin_config_t CINB_config;
-extern const cy_stc_gpio_pin_config_t CMOD_config;
-extern const cy_stc_gpio_pin_config_t CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD4_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
void init_cycfg_pins(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h
deleted file mode 100644
index 391f01a0be..0000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_platform.h
-*
-* Description:
-* Platform configuration
-* This file was automatically generated and should not be modified.
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PLATFORM_H)
-#define CYCFG_PLATFORM_H
-
-#include "cycfg_notices.h"
-#include "cy_sysclk.h"
-#include "cy_ble_clk.h"
-#include "cy_gpio.h"
-#include "cy_syspm.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
-#define CY_CFG_PWR_VDDA_MV 3300
-#define CY_CFG_PWR_VDDD_MV 3300
-#define CY_CFG_PWR_VBACKUP_MV 3300
-#define CY_CFG_PWR_VDD_NS_MV 3300
-#define CY_CFG_PWR_VDDIO0_MV 3300
-#define CY_CFG_PWR_VDDIO1_MV 3300
-
-void init_cycfg_platform(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PLATFORM_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.c
new file mode 100644
index 0000000000..12487034d7
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.c
@@ -0,0 +1,264 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0xEBU,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_QUAD,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0x01U,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_QUAD,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 4U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x06U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x04U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0xD8U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x60U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x38U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_QUAD,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x35U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x05U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x01U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+{
+ /* Specifies the number of address bytes used by the memory slave device. */
+ .numOfAddrBytes = 0x03U,
+ /* The size of the memory. */
+ .memSize = 0x04000000U,
+ /* Specifies the Read command. */
+ .readCmd = &S25FL512S_SlaveSlot_0_readCmd,
+ /* Specifies the Write Enable command. */
+ .writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
+ /* Specifies the Write Disable command. */
+ .writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
+ /* Specifies the Erase command. */
+ .eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
+ /* Specifies the sector size of each erase. */
+ .eraseSize = 0x00040000U,
+ /* Specifies the Chip Erase command. */
+ .chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
+ /* Specifies the Program command. */
+ .programCmd = &S25FL512S_SlaveSlot_0_programCmd,
+ /* Specifies the page size for programming. */
+ .programSize = 0x00000200U,
+ /* Specifies the command to read the QE-containing status register. */
+ .readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+ /* Specifies the command to read the WIP-containing status register. */
+ .readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+ /* Specifies the command to write into the QE-containing status register. */
+ .writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+ /* The mask for the status register. */
+ .stsRegBusyMask = 0x01U,
+ /* The mask for the status register. */
+ .stsRegQuadEnableMask = 0x02U,
+ /* The max time for the erase type-1 cycle-time in ms. */
+ .eraseTime = 520U,
+ /* The max time for the chip-erase cycle-time in ms. */
+ .chipEraseTime = 134000U,
+ /* The max time for the page-program cycle-time in us. */
+ .programTime = 340U
+};
+
+const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+{
+ /* Determines the slot number where the memory device is placed. */
+ .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+ /* Flags. */
+ .flags = CY_SMIF_FLAG_WR_EN,
+ /* The data-line selection options for a slave device. */
+ .dataSelect = CY_SMIF_DATA_SEL0,
+ /* The base address the memory slave is mapped to in the PSoC memory map.
+ Valid when the memory-mapped mode is enabled. */
+ .baseAddress = 0x18000000U,
+ /* The size allocated in the PSoC memory map, for the memory slave device.
+ The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+ .memMappedSize = 0x10000U,
+ /* If this memory device is one of the devices in the dual quad SPI configuration.
+ Valid when the memory mapped mode is enabled. */
+ .dualQuadSlots = 0,
+ /* The configuration of the device. */
+ .deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
+ &S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_block_config_t smifBlockConfig =
+{
+ /* The number of SMIF memories defined. */
+ .memCount = CY_SMIF_DEVICE_NUM,
+ /* The pointer to the array of memory config structures of size memCount. */
+ .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+ /* The version of the SMIF driver. */
+ .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+ /* The version of the SMIF driver. */
+ .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+};
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.h
new file mode 100644
index 0000000000..1f4fb5dfca
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_qspi_memslot.h
@@ -0,0 +1,49 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+
+extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CY_SMIF_MEMCONFIG_H*/
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h
index 92fbc92d25..8c2b9d4076 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_routing.h
@@ -32,6 +32,8 @@ extern "C" {
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
+#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
+#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
@@ -39,6 +41,7 @@ void init_cycfg_routing(void);
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
@@ -50,8 +53,8 @@ void init_cycfg_routing(void);
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.c
similarity index 75%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.c
index f0edc010bc..f736a83142 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.c
@@ -1,8 +1,8 @@
/*******************************************************************************
-* File Name: cycfg_platform.c
+* File Name: cycfg_system.c
*
* Description:
-* Platform configuration
+* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
@@ -22,26 +22,29 @@
* limitations under the License.
********************************************************************************/
-#include "cycfg_platform.h"
+#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
#define CY_CFG_SYSCLK_PLL_ERROR 3
#define CY_CFG_SYSCLK_FLL_ERROR 4
#define CY_CFG_SYSCLK_WCO_ERROR 5
-#define CY_CFG_SYSCLK_PLL1_AVAILABLE 1
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
#define CY_CFG_SYSCLK_FLL_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 48UL
+#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_ILO_ENABLED 1
#define CY_CFG_SYSCLK_IMO_ENABLED 1
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
@@ -56,13 +59,15 @@
#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_PLL0_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
+#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
-#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_USING_PMIC 0
-#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD
-#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
@@ -78,12 +83,24 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
+{
+ .feedbackDiv = 30,
+ .referenceDiv = 1,
+ .outputDiv = 5,
+ .lfMode = false,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
while(1);
}
+__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
+{
+ Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
+}
__STATIC_INLINE void Cy_SysClk_ClkBakInit()
{
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
@@ -108,17 +125,23 @@ __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
}
+__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
+{
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
+}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
- Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
- Cy_SysClk_ClkHfEnable(2U);
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
-__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
+__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
- Cy_SysClk_ClkHfSetSource(4U, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(4U, CY_SYSCLK_CLKHF_NO_DIVIDE);
- Cy_SysClk_ClkHfEnable(4U);
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
@@ -153,12 +176,30 @@ __STATIC_INLINE void Cy_SysClk_ClkPath4Init()
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
- Cy_SysClk_ClkPeriSetDivider(1U);
+ Cy_SysClk_ClkPeriSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_Pll0Init()
+{
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
}
__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
{
Cy_SysClk_ClkSlowSetDivider(0U);
}
+__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
+{
+ Cy_SysClk_ClkTimerDisable();
+ Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
+ Cy_SysClk_ClkTimerSetDivider(0U);
+ Cy_SysClk_ClkTimerEnable();
+}
__STATIC_INLINE void Cy_SysClk_WcoInit()
{
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
@@ -168,37 +209,58 @@ __STATIC_INLINE void Cy_SysClk_WcoInit()
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
+__STATIC_INLINE void init_cycfg_power(void)
+{
+ /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
+ #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+ if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+ {
+ Cy_SysLib_ResetBackupDomain();
+ Cy_SysClk_IloDisable();
+ Cy_SysClk_IloInit();
+ }
+ #else /* Dedicated Supply */
+ Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
+ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+ /* Configure core regulator */
+ #if CY_CFG_PWR_USING_LDO
+ Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+ Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
+ #else
+ Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
+ #endif /* CY_CFG_PWR_USING_LDO */
+ /* Configure PMIC */
+ Cy_SysPm_UnlockPmic();
+ #if CY_CFG_PWR_USING_PMIC
+ Cy_SysPm_PmicEnableOutput();
+ #else
+ Cy_SysPm_PmicDisableOutput();
+ #endif /* CY_CFG_PWR_USING_PMIC */
+}
-void init_cycfg_platform(void)
+void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
- #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD)
- if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */){ Cy_SysLib_ResetBackupDomain(); }
- #endif
#ifdef CY_CFG_PWR_ENABLED
- /* Configure power mode */
- #if CY_CFG_PWR_USING_LDO
- Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
- #else
- Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE);
- #endif
- /* Configure PMIC */
- Cy_SysPm_UnlockPmic();
- #if CY_CFG_PWR_USING_PMIC
- Cy_SysPm_PmicEnableOutput();
- #else
- Cy_SysPm_PmicDisableOutput();
- #endif
- #endif
+ #ifdef CY_CFG_PWR_INIT
+ init_cycfg_power();
+ #else
+ #warning Power system will not be configured. Update power personality to v1.20 or later.
+ #endif /* CY_CFG_PWR_INIT */
+ #endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
- Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+ {
+ (void)Cy_SysClk_PllDisable(pll);
+ }
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
@@ -210,62 +272,10 @@ void init_cycfg_platform(void)
Cy_SysClk_FllDisable();
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
-
- #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
+ #ifdef CY_IP_MXBLESS
+ (void)Cy_BLE_EcoReset();
#endif
- #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15);
- #endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
@@ -498,6 +508,14 @@ void init_cycfg_platform(void)
#error the IMO must be enabled for proper chip operation
#endif
+ #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+ Cy_SysClk_MfoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+ Cy_SysClk_ClkMfInit();
+ #endif
+
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.h
new file mode 100644
index 0000000000..eb91736fba
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_system.h
@@ -0,0 +1,91 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_ble_clk.h"
+#include "cy_systick.h"
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define srss_0_clock_0_hfclk_1_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF1 1UL
+#define srss_0_clock_0_hfclk_2_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF2 2UL
+#define srss_0_clock_0_hfclk_3_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF3 3UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_timerclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/qspi_config.cfg
new file mode 100644
index 0000000000..a561643dcf
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/qspi_config.cfg
@@ -0,0 +1,2 @@
+set SMIF_BANKS {
+}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/design.modus
new file mode 100644
index 0000000000..0e5a069a96
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/design.modus
@@ -0,0 +1,710 @@
+
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diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c
index 74c28aba2c..cb430a4164 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.c
@@ -26,9 +26,9 @@
void init_cycfg_all(void)
{
+ init_cycfg_system();
init_cycfg_clocks();
+ init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
- init_cycfg_platform();
- init_cycfg_routing();
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h
index 1709481df2..3585cf91ba 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg.h
@@ -30,12 +30,12 @@ extern "C" {
#endif
#include "cycfg_notices.h"
+#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_dmas.h"
+#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
-#include "cycfg_platform.h"
-#include "cycfg_routing.h"
void init_cycfg_all(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c
index 5249f7d3a0..b9306818f3 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.c
@@ -44,10 +44,6 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
- Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 1U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
-
- Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
- Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U);
- Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h
index 0da97983ce..c2703466b2 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_clocks.h
@@ -32,18 +32,21 @@
extern "C" {
#endif
-#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT
-#define peri_0_div_16_0_NUM 0U
-#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_0_NUM 0U
-#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_1_NUM 1U
-#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_2_NUM 2U
-#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_3_NUM 3U
-#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_4_NUM 4U
+#define CYBSP_USB_CLK_DIV_ENABLED 1U
+#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_USB_CLK_DIV_NUM 0U
+#define CYBSP_SDIO_DIV_ENABLED 1U
+#define CYBSP_SDIO_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_SDIO_DIV_NUM 0U
+#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
+#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_CLK_DIV_NUM 3U
void init_cycfg_clocks(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h
index c68d4b9ec8..69a805e959 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_dmas.h
@@ -32,15 +32,19 @@
extern "C" {
#endif
+#define cpuss_0_dw0_0_chan_0_ENABLED 1U
#define cpuss_0_dw0_0_chan_0_HW DW0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0
#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
+#define cpuss_0_dw0_0_chan_1_ENABLED 1U
#define cpuss_0_dw0_0_chan_1_HW DW0
#define cpuss_0_dw0_0_chan_1_CHANNEL 1
#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
+#define cpuss_0_dw1_0_chan_1_ENABLED 1U
#define cpuss_0_dw1_0_chan_1_HW DW1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1
#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
+#define cpuss_0_dw1_0_chan_3_ENABLED 1U
#define cpuss_0_dw1_0_chan_3_HW DW1
#define cpuss_0_dw1_0_chan_3_CHANNEL 3
#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c
index 67b745f805..73f7af2d87 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.c
@@ -24,14 +24,13 @@
#include "cycfg_peripherals.h"
-#define PWM_INPUT_DISABLED 0x7U
-#define USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \
+#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
- CY_USBFS_DEV_DRV_SET_EP1_LVL(0x2U) | \
- CY_USBFS_DEV_DRV_SET_EP2_LVL(0x2U) | \
+ CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
+ CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
@@ -43,7 +42,7 @@ cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
-const cy_stc_scb_uart_config_t BT_UART_config =
+const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@@ -71,7 +70,7 @@ const cy_stc_scb_uart_config_t BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
-const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
+const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
.slaveAddress1 = 8U,
@@ -79,7 +78,7 @@ const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
-const cy_stc_scb_uart_config_t KITPROG_UART_config =
+const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@@ -107,14 +106,14 @@ const cy_stc_scb_uart_config_t KITPROG_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
-const cy_stc_smif_config_t QSPI_config =
+const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
- .deselectDelay = QSPI_DESELECT_DELAY,
+ .deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
-const cy_stc_mcwdt_config_t MCWDT0_config =
+const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
.c1Match = 32768U,
@@ -127,7 +126,7 @@ const cy_stc_mcwdt_config_t MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
-const cy_stc_rtc_config_t RTC_config =
+const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
.min = 0U,
@@ -139,35 +138,7 @@ const cy_stc_rtc_config_t RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
-const cy_stc_tcpwm_pwm_config_t PWM_config =
-{
- .pwmMode = CY_TCPWM_PWM_MODE_PWM,
- .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
- .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
- .deadTimeClocks = 0,
- .runMode = CY_TCPWM_PWM_CONTINUOUS,
- .period0 = 32000,
- .period1 = 32768,
- .enablePeriodSwap = false,
- .compare0 = 16384,
- .compare1 = 16384,
- .enableCompareSwap = false,
- .interruptSources = CY_TCPWM_INT_NONE,
- .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE,
- .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE,
- .killMode = CY_TCPWM_PWM_STOP_ON_KILL,
- .swapInputMode = PWM_INPUT_DISABLED & 0x3U,
- .swapInput = CY_TCPWM_INPUT_0,
- .reloadInputMode = PWM_INPUT_DISABLED & 0x3U,
- .reloadInput = CY_TCPWM_INPUT_0,
- .startInputMode = PWM_INPUT_DISABLED & 0x3U,
- .startInput = CY_TCPWM_INPUT_0,
- .killInputMode = PWM_INPUT_DISABLED & 0x3U,
- .killInput = CY_TCPWM_INPUT_0,
- .countInputMode = PWM_INPUT_DISABLED & 0x3U,
- .countInput = CY_TCPWM_INPUT_1,
-};
-const cy_stc_usbfs_dev_drv_config_t USBUART_config =
+const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
@@ -182,13 +153,13 @@ const cy_stc_usbfs_dev_drv_config_t USBUART_config =
.dmaConfig[6] = NULL,
.dmaConfig[7] = NULL,
.enableLpm = false,
- .intrLevelSel = USBUART_INTR_LVL_SEL,
+ .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
};
void init_cycfg_peripherals(void)
{
- Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
+ Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
@@ -196,8 +167,6 @@ void init_cycfg_peripherals(void)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
- Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM1_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U);
-
Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h
index beadadac39..8f73217044 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_peripherals.h
@@ -33,20 +33,19 @@
#include "cy_smif.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
-#include "cy_tcpwm_pwm.h"
-#include "cycfg_routing.h"
#include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus)
extern "C" {
#endif
+#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 100000000u
#define CY_CAPSENSE_VDDA_MV 3300u
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
-#define CY_CAPSENSE_PERI_DIV_INDEX 4u
+#define CY_CAPSENSE_PERI_DIV_INDEX 3u
#define Cmod_PORT GPIO_PRT7
#define CintA_PORT GPIO_PRT7
#define CintB_PORT GPIO_PRT7
@@ -74,61 +73,65 @@ extern "C" {
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
-#define CapSense_HW CSD0
-#define CapSense_IRQ csd_interrupt_IRQn
-#define BT_UART_HW SCB2
-#define BT_UART_IRQ scb_2_interrupt_IRQn
-#define CSD_COMM_HW SCB3
-#define CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define KITPROG_UART_HW SCB5
-#define KITPROG_UART_IRQ scb_5_interrupt_IRQn
-#define QSPI_HW SMIF0
-#define QSPI_IRQ smif_interrupt_IRQn
-#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
-#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
-#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
-#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
-#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
-#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
-#define QSPI_DATALINES0_1 (1UL)
-#define QSPI_DATALINES2_3 (1UL)
-#define QSPI_DATALINES4_5 (0UL)
-#define QSPI_DATALINES6_7 (0UL)
-#define QSPI_SS0 (1UL)
-#define QSPI_SS1 (0UL)
-#define QSPI_SS2 (0UL)
-#define QSPI_SS3 (0UL)
-#define QSPI_DESELECT_DELAY 7
-#define MCWDT0_HW MCWDT_STRUCT0
-#define RTC_10_MONTH_OFFSET (28U)
-#define RTC_MONTH_OFFSET (24U)
-#define RTC_10_DAY_OFFSET (20U)
-#define RTC_DAY_OFFSET (16U)
-#define RTC_1000_YEAR_OFFSET (12U)
-#define RTC_100_YEAR_OFFSET (8U)
-#define RTC_10_YEAR_OFFSET (4U)
-#define RTC_YEAR_OFFSET (0U)
-#define PWM_HW TCPWM1
-#define PWM_NUM 1UL
-#define PWM_MASK (1UL << 1)
-#define USBUART_ACTIVE_ENDPOINTS_MASK 7U
-#define USBUART_ENDPOINTS_BUFFER_SIZE 140U
-#define USBUART_ENDPOINTS_ACCESS_TYPE 0U
-#define USBUART_USB_CORE 4U
-#define USBUART_HW USBFS0
-#define USBUART_HI_IRQ usb_interrupt_hi_IRQn
-#define USBUART_MED_IRQ usb_interrupt_med_IRQn
-#define USBUART_LO_IRQ usb_interrupt_lo_IRQn
+#define CYBSP_CSD_HW CSD0
+#define CYBSP_CSD_IRQ csd_interrupt_IRQn
+#define CYBSP_BT_UART_ENABLED 1U
+#define CYBSP_BT_UART_HW SCB2
+#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
+#define CYBSP_CSD_COMM_ENABLED 1U
+#define CYBSP_CSD_COMM_HW SCB3
+#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
+#define CYBSP_DEBUG_UART_ENABLED 1U
+#define CYBSP_DEBUG_UART_HW SCB5
+#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
+#define CYBSP_QSPI_ENABLED 1U
+#define CYBSP_QSPI_HW SMIF0
+#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
+#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
+#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
+#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
+#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
+#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
+#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
+#define CYBSP_QSPI_DATALINES0_1 (1UL)
+#define CYBSP_QSPI_DATALINES2_3 (1UL)
+#define CYBSP_QSPI_DATALINES4_5 (0UL)
+#define CYBSP_QSPI_DATALINES6_7 (0UL)
+#define CYBSP_QSPI_SS0 (1UL)
+#define CYBSP_QSPI_SS1 (0UL)
+#define CYBSP_QSPI_SS2 (0UL)
+#define CYBSP_QSPI_SS3 (0UL)
+#define CYBSP_QSPI_DESELECT_DELAY 7
+#define CYBSP_MCWDT0_ENABLED 1U
+#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
+#define CYBSP_RTC_ENABLED 1U
+#define CYBSP_RTC_10_MONTH_OFFSET (28U)
+#define CYBSP_RTC_MONTH_OFFSET (24U)
+#define CYBSP_RTC_10_DAY_OFFSET (20U)
+#define CYBSP_RTC_DAY_OFFSET (16U)
+#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
+#define CYBSP_RTC_100_YEAR_OFFSET (8U)
+#define CYBSP_RTC_10_YEAR_OFFSET (4U)
+#define CYBSP_RTC_YEAR_OFFSET (0U)
+#define CYBSP_SDIO_ENABLED 1U
+#define CYBSP_USBUART_ENABLED 1U
+#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
+#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
+#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
+#define CYBSP_USBUART_USB_CORE 4U
+#define CYBSP_USBUART_HW USBFS0
+#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
+#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
+#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
extern cy_stc_csd_context_t cy_csd_0_context;
-extern const cy_stc_scb_uart_config_t BT_UART_config;
-extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
-extern const cy_stc_smif_config_t QSPI_config;
-extern const cy_stc_mcwdt_config_t MCWDT0_config;
-extern const cy_stc_rtc_config_t RTC_config;
-extern const cy_stc_tcpwm_pwm_config_t PWM_config;
-extern const cy_stc_usbfs_dev_drv_config_t USBUART_config;
+extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
+extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
+extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
+extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
void init_cycfg_peripherals(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c
index 8fed53e210..69bf22b3b4 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.c
@@ -24,192 +24,192 @@
#include "cycfg_pins.h"
-const cy_stc_gpio_pin_config_t WCO_IN_config =
+const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = WCO_IN_HSIOM,
+ .hsiom = CYBSP_WCO_IN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t WCO_OUT_config =
+const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = WCO_OUT_HSIOM,
+ .hsiom = CYBSP_WCO_OUT_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_RED_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_RED_HSIOM,
+ .hsiom = CYBSP_LED_RED_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SW2_config =
+const cy_stc_gpio_pin_config_t CYBSP_BTN2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
- .hsiom = SW2_HSIOM,
+ .hsiom = CYBSP_BTN2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_BLUE_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_BLUE_HSIOM,
+ .hsiom = CYBSP_LED_BLUE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_SS0_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = QSPI_SS0_HSIOM,
+ .hsiom = CYBSP_QSPI_SS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA3_HSIOM,
+ .hsiom = CYBSP_QSPI_D3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA2_HSIOM,
+ .hsiom = CYBSP_QSPI_D2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA1_HSIOM,
+ .hsiom = CYBSP_QSPI_D1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA0_HSIOM,
+ .hsiom = CYBSP_QSPI_D0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = QSPI_SPI_CLOCK_HSIOM,
+ .hsiom = CYBSP_QSPI_SCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED9_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED9_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED9_HSIOM,
+ .hsiom = CYBSP_LED9_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
@@ -225,7 +225,7 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config =
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
@@ -241,551 +241,567 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config =
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_TX_HSIOM,
+ .hsiom = CYBSP_CSD_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_GREEN_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_GREEN_HSIOM,
+ .hsiom = CYBSP_LED_GREEN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED8_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED8_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED8_HSIOM,
+ .hsiom = CYBSP_LED8_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT0_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT0_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_D0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT1_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT1_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_D1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT2_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT2_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_D2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT3_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT3_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_D3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_CMD_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_CMD_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_CLK_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = SDHC0_CLK_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ENABLE_WIFI_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = ENABLE_WIFI_HSIOM,
+ .hsiom = CYBSP_WIFI_WL_REG_ON_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_UART_RX_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
+{
+ .outVal = 0,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
- .hsiom = BT_UART_RX_HSIOM,
+ .hsiom = CYBSP_BT_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_UART_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = BT_UART_TX_HSIOM,
+ .hsiom = CYBSP_BT_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_UART_RTS_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = BT_UART_RTS_HSIOM,
+ .hsiom = CYBSP_BT_UART_RTS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_UART_CTS_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
- .hsiom = BT_UART_CTS_HSIOM,
+ .hsiom = CYBSP_BT_UART_CTS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_POWER_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF,
- .hsiom = BT_POWER_HSIOM,
+ .hsiom = CYBSP_BT_POWER_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = BT_HOST_WAKE_HSIOM,
+ .hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = BT_DEVICE_WAKE_HSIOM,
+ .hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t UART_RX_config =
+const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
- .hsiom = UART_RX_HSIOM,
+ .hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t UART_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = UART_TX_HSIOM,
+ .hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t EZI2C_SCL_config =
+const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
- .hsiom = EZI2C_SCL_HSIOM,
+ .hsiom = CYBSP_EZI2C_SCL_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t EZI2C_SDA_config =
+const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
- .hsiom = EZI2C_SDA_HSIOM,
+ .hsiom = CYBSP_EZI2C_SDA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWO_config =
+const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = SWO_HSIOM,
+ .hsiom = CYBSP_SWO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWDIO_config =
+const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
- .hsiom = SWDIO_HSIOM,
+ .hsiom = CYBSP_SWDIO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWDCK_config =
+const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
- .hsiom = SWDCK_HSIOM,
+ .hsiom = CYBSP_SWDCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CINA_config =
+const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CINA_HSIOM,
+ .hsiom = CYBSP_CINA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CINB_config =
+const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CINB_HSIOM,
+ .hsiom = CYBSP_CINB_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CMOD_config =
+const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CMOD_HSIOM,
+ .hsiom = CYBSP_CMOD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_BTN0_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_BTN0_HSIOM,
+ .hsiom = CYBSP_CSD_BTN0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_BTN1_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_BTN1_HSIOM,
+ .hsiom = CYBSP_CSD_BTN1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD0_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD0_HSIOM,
+ .hsiom = CYBSP_CSD_SLD0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD1_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD1_HSIOM,
+ .hsiom = CYBSP_CSD_SLD1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD2_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD2_HSIOM,
+ .hsiom = CYBSP_CSD_SLD2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD3_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD3_HSIOM,
+ .hsiom = CYBSP_CSD_SLD3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD4_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD4_HSIOM,
+ .hsiom = CYBSP_CSD_SLD4_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
@@ -796,80 +812,82 @@ const cy_stc_gpio_pin_config_t CSD_SLD4_config =
void init_cycfg_pins(void)
{
- Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config);
+ Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
- Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config);
+ Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
- Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
- Cy_GPIO_Pin_Init(SW2_PORT, SW2_PIN, &SW2_config);
+ Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
- Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
- Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
- Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
- Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
- Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
- Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
- Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
- Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config);
Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config);
- Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
- Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT0_PORT, SDHC0_DAT0_PIN, &SDHC0_DAT0_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D0_PORT, CYBSP_WIFI_SDIO_D0_PIN, &CYBSP_WIFI_SDIO_D0_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT1_PORT, SDHC0_DAT1_PIN, &SDHC0_DAT1_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D1_PORT, CYBSP_WIFI_SDIO_D1_PIN, &CYBSP_WIFI_SDIO_D1_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT2_PORT, SDHC0_DAT2_PIN, &SDHC0_DAT2_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D2_PORT, CYBSP_WIFI_SDIO_D2_PIN, &CYBSP_WIFI_SDIO_D2_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT3_PORT, SDHC0_DAT3_PIN, &SDHC0_DAT3_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D3_PORT, CYBSP_WIFI_SDIO_D3_PIN, &CYBSP_WIFI_SDIO_D3_config);
- Cy_GPIO_Pin_Init(SDHC0_CMD_PORT, SDHC0_CMD_PIN, &SDHC0_CMD_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config);
- Cy_GPIO_Pin_Init(SDHC0_CLK_PORT, SDHC0_CLK_PIN, &SDHC0_CLK_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
- Cy_GPIO_Pin_Init(ENABLE_WIFI_PORT, ENABLE_WIFI_PIN, &ENABLE_WIFI_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_WL_REG_ON_PORT, CYBSP_WIFI_WL_REG_ON_PIN, &CYBSP_WIFI_WL_REG_ON_config);
- Cy_GPIO_Pin_Init(BT_UART_RX_PORT, BT_UART_RX_PIN, &BT_UART_RX_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
- Cy_GPIO_Pin_Init(BT_UART_TX_PORT, BT_UART_TX_PIN, &BT_UART_TX_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
- Cy_GPIO_Pin_Init(BT_UART_RTS_PORT, BT_UART_RTS_PIN, &BT_UART_RTS_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
- Cy_GPIO_Pin_Init(BT_UART_CTS_PORT, BT_UART_CTS_PIN, &BT_UART_CTS_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
- Cy_GPIO_Pin_Init(BT_POWER_PORT, BT_POWER_PIN, &BT_POWER_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
- Cy_GPIO_Pin_Init(BT_HOST_WAKE_PORT, BT_HOST_WAKE_PIN, &BT_HOST_WAKE_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
- Cy_GPIO_Pin_Init(BT_DEVICE_WAKE_PORT, BT_DEVICE_WAKE_PIN, &BT_DEVICE_WAKE_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
- Cy_GPIO_Pin_Init(UART_RX_PORT, UART_RX_PIN, &UART_RX_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
- Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config);
+ Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
- Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config);
+ Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
- Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config);
+ Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
- Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config);
+ Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
- Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config);
+ Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
- Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config);
+ Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h
index 7496d6069e..a2b112783e 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_pins.h
@@ -33,126 +33,139 @@
extern "C" {
#endif
-#define WCO_IN_PORT GPIO_PRT0
-#define WCO_IN_PIN 0U
-#define WCO_IN_NUM 0U
-#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define WCO_IN_INIT_DRIVESTATE 1
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_0_HSIOM
#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define WCO_OUT_PORT GPIO_PRT0
-#define WCO_OUT_PIN 1U
-#define WCO_OUT_NUM 1U
-#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define WCO_OUT_INIT_DRIVESTATE 1
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_1_HSIOM
#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define LED_RED_PORT GPIO_PRT0
-#define LED_RED_PIN 3U
-#define LED_RED_NUM 3U
-#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_RED_INIT_DRIVESTATE 1
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_LED_RED_ENABLED 1U
+#define CYBSP_LED_RED_PORT GPIO_PRT0
+#define CYBSP_LED_RED_PIN 3U
+#define CYBSP_LED_RED_NUM 3U
+#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED_RED_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_3_HSIOM
#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
-#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
-#define SW2_PORT GPIO_PRT0
-#define SW2_PIN 4U
-#define SW2_NUM 4U
-#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define SW2_INIT_DRIVESTATE 1
+#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
+#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_BTN2_ENABLED 1U
+#define CYBSP_BTN2_PORT GPIO_PRT0
+#define CYBSP_BTN2_PIN 4U
+#define CYBSP_BTN2_NUM 4U
+#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_BTN2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define SW2_IRQ ioss_interrupts_gpio_0_IRQn
-#define LED_BLUE_PORT GPIO_PRT11
-#define LED_BLUE_PIN 1U
-#define LED_BLUE_NUM 1U
-#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_BLUE_INIT_DRIVESTATE 1
+#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
+#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_LED_BLUE_ENABLED 1U
+#define CYBSP_LED_BLUE_PORT GPIO_PRT11
+#define CYBSP_LED_BLUE_PIN 1U
+#define CYBSP_LED_BLUE_NUM 1U
+#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_1_HSIOM
#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_SS0_PORT GPIO_PRT11
-#define QSPI_SS0_PIN 2U
-#define QSPI_SS0_NUM 2U
-#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define QSPI_SS0_INIT_DRIVESTATE 1
+#define CYBSP_LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
+#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_SS_ENABLED 1U
+#define CYBSP_QSPI_SS_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS_PIN 2U
+#define CYBSP_QSPI_SS_NUM 2U
+#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_2_HSIOM
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA3_PORT GPIO_PRT11
-#define QSPI_DATA3_PIN 3U
-#define QSPI_DATA3_NUM 3U
-#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA3_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D3_ENABLED 1U
+#define CYBSP_QSPI_D3_PORT GPIO_PRT11
+#define CYBSP_QSPI_D3_PIN 3U
+#define CYBSP_QSPI_D3_NUM 3U
+#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_3_HSIOM
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA2_PORT GPIO_PRT11
-#define QSPI_DATA2_PIN 4U
-#define QSPI_DATA2_NUM 4U
-#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA2_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D2_ENABLED 1U
+#define CYBSP_QSPI_D2_PORT GPIO_PRT11
+#define CYBSP_QSPI_D2_PIN 4U
+#define CYBSP_QSPI_D2_NUM 4U
+#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_4_HSIOM
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA1_PORT GPIO_PRT11
-#define QSPI_DATA1_PIN 5U
-#define QSPI_DATA1_NUM 5U
-#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA1_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D1_ENABLED 1U
+#define CYBSP_QSPI_D1_PORT GPIO_PRT11
+#define CYBSP_QSPI_D1_PIN 5U
+#define CYBSP_QSPI_D1_NUM 5U
+#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_5_HSIOM
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA0_PORT GPIO_PRT11
-#define QSPI_DATA0_PIN 6U
-#define QSPI_DATA0_NUM 6U
-#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA0_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D0_ENABLED 1U
+#define CYBSP_QSPI_D0_PORT GPIO_PRT11
+#define CYBSP_QSPI_D0_PIN 6U
+#define CYBSP_QSPI_D0_NUM 6U
+#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_6_HSIOM
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_SPI_CLOCK_PORT GPIO_PRT11
-#define QSPI_SPI_CLOCK_PIN 7U
-#define QSPI_SPI_CLOCK_NUM 7U
-#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_SCK_ENABLED 1U
+#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SCK_PIN 7U
+#define CYBSP_QSPI_SCK_NUM 7U
+#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_7_HSIOM
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define LED9_PORT GPIO_PRT13
-#define LED9_PIN 7U
-#define LED9_NUM 7U
-#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED9_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_LED9_ENABLED 1U
+#define CYBSP_LED9_PORT GPIO_PRT13
+#define CYBSP_LED9_PIN 7U
+#define CYBSP_LED9_NUM 7U
+#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED9_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_7_HSIOM
#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define LED9_IRQ ioss_interrupts_gpio_13_IRQn
+#define CYBSP_LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
+#define CYBSP_LED9_IRQ ioss_interrupts_gpio_13_IRQn
+#define ioss_0_port_14_pin_0_ENABLED 1U
#define ioss_0_port_14_pin_0_PORT GPIO_PRT14
#define ioss_0_port_14_pin_0_PIN 0U
#define ioss_0_port_14_pin_0_NUM 0U
@@ -162,6 +175,7 @@ extern "C" {
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn
+#define ioss_0_port_14_pin_1_ENABLED 1U
#define ioss_0_port_14_pin_1_PORT GPIO_PRT14
#define ioss_0_port_14_pin_1_PIN 1U
#define ioss_0_port_14_pin_1_NUM 1U
@@ -171,395 +185,441 @@ extern "C" {
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn
-#define CSD_TX_PORT GPIO_PRT1
-#define CSD_TX_PIN 0U
-#define CSD_TX_NUM 0U
-#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_TX_INIT_DRIVESTATE 1
+#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_0_HSIOM
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define LED_GREEN_PORT GPIO_PRT1
-#define LED_GREEN_PIN 1U
-#define LED_GREEN_NUM 1U
-#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_GREEN_INIT_DRIVESTATE 1
+#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_LED_GREEN_ENABLED 1U
+#define CYBSP_LED_GREEN_PORT GPIO_PRT1
+#define CYBSP_LED_GREEN_PIN 1U
+#define CYBSP_LED_GREEN_NUM 1U
+#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_1_HSIOM
#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
-#define LED8_PORT GPIO_PRT1
-#define LED8_PIN 5U
-#define LED8_NUM 5U
-#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED8_INIT_DRIVESTATE 1
+#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
+#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_LED8_ENABLED 1U
+#define CYBSP_LED8_PORT GPIO_PRT1
+#define CYBSP_LED8_PIN 5U
+#define CYBSP_LED8_NUM 5U
+#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED8_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_5_HSIOM
#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define LED8_IRQ ioss_interrupts_gpio_1_IRQn
-#define SDHC0_DAT0_PORT GPIO_PRT2
-#define SDHC0_DAT0_PIN 0U
-#define SDHC0_DAT0_NUM 0U
-#define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT0_INIT_DRIVESTATE 1
+#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
+#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_WIFI_SDIO_D0_ENABLED 1U
+#define CYBSP_WIFI_SDIO_D0_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_D0_PIN 0U
+#define CYBSP_WIFI_SDIO_D0_NUM 0U
+#define CYBSP_WIFI_SDIO_D0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_0_HSIOM
#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
-#define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_DAT1_PORT GPIO_PRT2
-#define SDHC0_DAT1_PIN 1U
-#define SDHC0_DAT1_NUM 1U
-#define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT1_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_D0_HSIOM ioss_0_port_2_pin_0_HSIOM
+#define CYBSP_WIFI_SDIO_D0_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_D1_ENABLED 1U
+#define CYBSP_WIFI_SDIO_D1_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_D1_PIN 1U
+#define CYBSP_WIFI_SDIO_D1_NUM 1U
+#define CYBSP_WIFI_SDIO_D1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_1_HSIOM
#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
-#define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_DAT2_PORT GPIO_PRT2
-#define SDHC0_DAT2_PIN 2U
-#define SDHC0_DAT2_NUM 2U
-#define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT2_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_D1_HSIOM ioss_0_port_2_pin_1_HSIOM
+#define CYBSP_WIFI_SDIO_D1_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_D2_ENABLED 1U
+#define CYBSP_WIFI_SDIO_D2_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_D2_PIN 2U
+#define CYBSP_WIFI_SDIO_D2_NUM 2U
+#define CYBSP_WIFI_SDIO_D2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_2_HSIOM
#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
-#define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_DAT3_PORT GPIO_PRT2
-#define SDHC0_DAT3_PIN 3U
-#define SDHC0_DAT3_NUM 3U
-#define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT3_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_D2_HSIOM ioss_0_port_2_pin_2_HSIOM
+#define CYBSP_WIFI_SDIO_D2_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_D3_ENABLED 1U
+#define CYBSP_WIFI_SDIO_D3_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_D3_PIN 3U
+#define CYBSP_WIFI_SDIO_D3_NUM 3U
+#define CYBSP_WIFI_SDIO_D3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_3_HSIOM
#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
-#define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_CMD_PORT GPIO_PRT2
-#define SDHC0_CMD_PIN 4U
-#define SDHC0_CMD_NUM 4U
-#define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_CMD_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_D3_HSIOM ioss_0_port_2_pin_3_HSIOM
+#define CYBSP_WIFI_SDIO_D3_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
+#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_CMD_PIN 4U
+#define CYBSP_WIFI_SDIO_CMD_NUM 4U
+#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_4_HSIOM
#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
-#define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_CLK_PORT GPIO_PRT2
-#define SDHC0_CLK_PIN 5U
-#define SDHC0_CLK_NUM 5U
-#define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define SDHC0_CLK_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
+#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
+#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_CLK_PIN 5U
+#define CYBSP_WIFI_SDIO_CLK_NUM 5U
+#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_5_HSIOM
#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
-#define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn
-#define ENABLE_WIFI_PORT GPIO_PRT2
-#define ENABLE_WIFI_PIN 6U
-#define ENABLE_WIFI_NUM 6U
-#define ENABLE_WIFI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define ENABLE_WIFI_INIT_DRIVESTATE 0
+#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
+#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_WL_REG_ON_ENABLED 1U
+#define CYBSP_WIFI_WL_REG_ON_PORT GPIO_PRT2
+#define CYBSP_WIFI_WL_REG_ON_PIN 6U
+#define CYBSP_WIFI_WL_REG_ON_NUM 6U
+#define CYBSP_WIFI_WL_REG_ON_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WIFI_WL_REG_ON_INIT_DRIVESTATE 0
#ifndef ioss_0_port_2_pin_6_HSIOM
#define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define ENABLE_WIFI_HSIOM ioss_0_port_2_pin_6_HSIOM
-#define ENABLE_WIFI_IRQ ioss_interrupts_gpio_2_IRQn
-#define BT_UART_RX_PORT GPIO_PRT3
-#define BT_UART_RX_PIN 0U
-#define BT_UART_RX_NUM 0U
-#define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define BT_UART_RX_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_WL_REG_ON_HSIOM ioss_0_port_2_pin_6_HSIOM
+#define CYBSP_WIFI_WL_REG_ON_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
+#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
+#define CYBSP_WIFI_HOST_WAKE_PIN 7U
+#define CYBSP_WIFI_HOST_WAKE_NUM 7U
+#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_2_pin_7_HSIOM
+ #define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
+#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_BT_UART_RX_ENABLED 1U
+#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RX_PIN 0U
+#define CYBSP_BT_UART_RX_NUM 0U
+#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_0_HSIOM
#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
-#define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_UART_TX_PORT GPIO_PRT3
-#define BT_UART_TX_PIN 1U
-#define BT_UART_TX_NUM 1U
-#define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define BT_UART_TX_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_UART_TX_ENABLED 1U
+#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_TX_PIN 1U
+#define CYBSP_BT_UART_TX_NUM 1U
+#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_1_HSIOM
#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
-#define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_UART_RTS_PORT GPIO_PRT3
-#define BT_UART_RTS_PIN 2U
-#define BT_UART_RTS_NUM 2U
-#define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define BT_UART_RTS_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
+#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_UART_RTS_ENABLED 1U
+#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RTS_PIN 2U
+#define CYBSP_BT_UART_RTS_NUM 2U
+#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_2_HSIOM
#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
-#define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_UART_CTS_PORT GPIO_PRT3
-#define BT_UART_CTS_PIN 3U
-#define BT_UART_CTS_NUM 3U
-#define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define BT_UART_CTS_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
+#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_UART_CTS_ENABLED 1U
+#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_CTS_PIN 3U
+#define CYBSP_BT_UART_CTS_NUM 3U
+#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_3_HSIOM
#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
-#define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_POWER_PORT GPIO_PRT3
-#define BT_POWER_PIN 4U
-#define BT_POWER_NUM 4U
-#define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
-#define BT_POWER_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
+#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_POWER_ENABLED 1U
+#define CYBSP_BT_POWER_PORT GPIO_PRT3
+#define CYBSP_BT_POWER_PIN 4U
+#define CYBSP_BT_POWER_NUM 4U
+#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
+#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_4_HSIOM
#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
-#define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_HOST_WAKE_PORT GPIO_PRT3
-#define BT_HOST_WAKE_PIN 5U
-#define BT_HOST_WAKE_NUM 5U
-#define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define BT_HOST_WAKE_INIT_DRIVESTATE 0
+#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
+#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_HOST_WAKE_ENABLED 1U
+#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
+#define CYBSP_BT_HOST_WAKE_PIN 5U
+#define CYBSP_BT_HOST_WAKE_NUM 5U
+#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_3_pin_5_HSIOM
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
-#define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_DEVICE_WAKE_PORT GPIO_PRT4
-#define BT_DEVICE_WAKE_PIN 0U
-#define BT_DEVICE_WAKE_NUM 0U
-#define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
+#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
+#define CYBSP_BT_DEVICE_WAKE_PIN 0U
+#define CYBSP_BT_DEVICE_WAKE_NUM 0U
+#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_4_pin_0_HSIOM
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
-#define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
-#define UART_RX_PORT GPIO_PRT5
-#define UART_RX_PIN 0U
-#define UART_RX_NUM 0U
-#define UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define UART_RX_INIT_DRIVESTATE 1
+#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
+#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#define CYBSP_DEBUG_UART_RX_ENABLED 1U
+#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
+#define CYBSP_DEBUG_UART_RX_PIN 0U
+#define CYBSP_DEBUG_UART_RX_NUM 0U
+#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_0_HSIOM
#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
-#define UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
-#define UART_TX_PORT GPIO_PRT5
-#define UART_TX_PIN 1U
-#define UART_TX_NUM 1U
-#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define UART_TX_INIT_DRIVESTATE 1
+#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
+#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
+#define CYBSP_DEBUG_UART_TX_ENABLED 1U
+#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
+#define CYBSP_DEBUG_UART_TX_PIN 1U
+#define CYBSP_DEBUG_UART_TX_NUM 1U
+#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_1_HSIOM
#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#define EZI2C_SCL_PORT GPIO_PRT6
-#define EZI2C_SCL_PIN 0U
-#define EZI2C_SCL_NUM 0U
-#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define EZI2C_SCL_INIT_DRIVESTATE 1
+#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
+#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_0_HSIOM
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define EZI2C_SDA_PORT GPIO_PRT6
-#define EZI2C_SDA_PIN 1U
-#define EZI2C_SDA_NUM 1U
-#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define EZI2C_SDA_INIT_DRIVESTATE 1
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_1_HSIOM
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWO_PORT GPIO_PRT6
-#define SWO_PIN 4U
-#define SWO_NUM 4U
-#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define SWO_INIT_DRIVESTATE 1
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWDIO_PORT GPIO_PRT6
-#define SWDIO_PIN 6U
-#define SWDIO_NUM 6U
-#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define SWDIO_INIT_DRIVESTATE 1
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_6_HSIOM
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWDCK_PORT GPIO_PRT6
-#define SWDCK_PIN 7U
-#define SWDCK_NUM 7U
-#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define SWDCK_INIT_DRIVESTATE 1
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CINA_PORT GPIO_PRT7
-#define CINA_PIN 1U
-#define CINA_NUM 1U
-#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CINA_INIT_DRIVESTATE 1
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_1_HSIOM
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CINB_PORT GPIO_PRT7
-#define CINB_PIN 2U
-#define CINB_NUM 2U
-#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CINB_INIT_DRIVESTATE 1
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_2_HSIOM
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CMOD_PORT GPIO_PRT7
-#define CMOD_PIN 7U
-#define CMOD_NUM 7U
-#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CMOD_INIT_DRIVESTATE 1
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_7_HSIOM
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CSD_BTN0_PORT GPIO_PRT8
-#define CSD_BTN0_PIN 1U
-#define CSD_BTN0_NUM 1U
-#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_BTN0_INIT_DRIVESTATE 1
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_1_HSIOM
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_BTN1_PORT GPIO_PRT8
-#define CSD_BTN1_PIN 2U
-#define CSD_BTN1_NUM 2U
-#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_BTN1_INIT_DRIVESTATE 1
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_2_HSIOM
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD0_PORT GPIO_PRT8
-#define CSD_SLD0_PIN 3U
-#define CSD_SLD0_NUM 3U
-#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD0_INIT_DRIVESTATE 1
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_3_HSIOM
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD1_PORT GPIO_PRT8
-#define CSD_SLD1_PIN 4U
-#define CSD_SLD1_NUM 4U
-#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD1_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_4_HSIOM
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD2_PORT GPIO_PRT8
-#define CSD_SLD2_PIN 5U
-#define CSD_SLD2_NUM 5U
-#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD2_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_5_HSIOM
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD3_PORT GPIO_PRT8
-#define CSD_SLD3_PIN 6U
-#define CSD_SLD3_NUM 6U
-#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD3_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_6_HSIOM
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD4_PORT GPIO_PRT8
-#define CSD_SLD4_PIN 7U
-#define CSD_SLD4_NUM 7U
-#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD4_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_7_HSIOM
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-extern const cy_stc_gpio_pin_config_t WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t LED_RED_config;
-extern const cy_stc_gpio_pin_config_t SW2_config;
-extern const cy_stc_gpio_pin_config_t LED_BLUE_config;
-extern const cy_stc_gpio_pin_config_t QSPI_SS0_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config;
-extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config;
-extern const cy_stc_gpio_pin_config_t LED9_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config;
extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config;
-extern const cy_stc_gpio_pin_config_t CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t LED_GREEN_config;
-extern const cy_stc_gpio_pin_config_t LED8_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config;
-extern const cy_stc_gpio_pin_config_t ENABLE_WIFI_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t BT_POWER_config;
-extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config;
-extern const cy_stc_gpio_pin_config_t UART_RX_config;
-extern const cy_stc_gpio_pin_config_t UART_TX_config;
-extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t SWO_config;
-extern const cy_stc_gpio_pin_config_t SWDIO_config;
-extern const cy_stc_gpio_pin_config_t SWDCK_config;
-extern const cy_stc_gpio_pin_config_t CINA_config;
-extern const cy_stc_gpio_pin_config_t CINB_config;
-extern const cy_stc_gpio_pin_config_t CMOD_config;
-extern const cy_stc_gpio_pin_config_t CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD4_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
void init_cycfg_pins(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h
deleted file mode 100644
index 76dfbef7bc..0000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_platform.h
-*
-* Description:
-* Platform configuration
-* This file was automatically generated and should not be modified.
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PLATFORM_H)
-#define CYCFG_PLATFORM_H
-
-#include "cycfg_notices.h"
-#include "cy_sysclk.h"
-#include "cy_systick.h"
-#include "cy_gpio.h"
-#include "cy_syspm.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
-#define CY_CFG_PWR_VDDA_MV 3300
-#define CY_CFG_PWR_VDDD_MV 3300
-#define CY_CFG_PWR_VBACKUP_MV 3300
-#define CY_CFG_PWR_VDD_NS_MV 3300
-#define CY_CFG_PWR_VDDIO0_MV 3300
-#define CY_CFG_PWR_VDDIO1_MV 3300
-
-void init_cycfg_platform(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PLATFORM_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.c
new file mode 100644
index 0000000000..12487034d7
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.c
@@ -0,0 +1,264 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0xEBU,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_QUAD,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0x01U,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_QUAD,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 4U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x06U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x04U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0xD8U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x60U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x38U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_QUAD,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x35U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x05U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x01U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+{
+ /* Specifies the number of address bytes used by the memory slave device. */
+ .numOfAddrBytes = 0x03U,
+ /* The size of the memory. */
+ .memSize = 0x04000000U,
+ /* Specifies the Read command. */
+ .readCmd = &S25FL512S_SlaveSlot_0_readCmd,
+ /* Specifies the Write Enable command. */
+ .writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
+ /* Specifies the Write Disable command. */
+ .writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
+ /* Specifies the Erase command. */
+ .eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
+ /* Specifies the sector size of each erase. */
+ .eraseSize = 0x00040000U,
+ /* Specifies the Chip Erase command. */
+ .chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
+ /* Specifies the Program command. */
+ .programCmd = &S25FL512S_SlaveSlot_0_programCmd,
+ /* Specifies the page size for programming. */
+ .programSize = 0x00000200U,
+ /* Specifies the command to read the QE-containing status register. */
+ .readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+ /* Specifies the command to read the WIP-containing status register. */
+ .readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+ /* Specifies the command to write into the QE-containing status register. */
+ .writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+ /* The mask for the status register. */
+ .stsRegBusyMask = 0x01U,
+ /* The mask for the status register. */
+ .stsRegQuadEnableMask = 0x02U,
+ /* The max time for the erase type-1 cycle-time in ms. */
+ .eraseTime = 520U,
+ /* The max time for the chip-erase cycle-time in ms. */
+ .chipEraseTime = 134000U,
+ /* The max time for the page-program cycle-time in us. */
+ .programTime = 340U
+};
+
+const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+{
+ /* Determines the slot number where the memory device is placed. */
+ .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+ /* Flags. */
+ .flags = CY_SMIF_FLAG_WR_EN,
+ /* The data-line selection options for a slave device. */
+ .dataSelect = CY_SMIF_DATA_SEL0,
+ /* The base address the memory slave is mapped to in the PSoC memory map.
+ Valid when the memory-mapped mode is enabled. */
+ .baseAddress = 0x18000000U,
+ /* The size allocated in the PSoC memory map, for the memory slave device.
+ The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+ .memMappedSize = 0x10000U,
+ /* If this memory device is one of the devices in the dual quad SPI configuration.
+ Valid when the memory mapped mode is enabled. */
+ .dualQuadSlots = 0,
+ /* The configuration of the device. */
+ .deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
+ &S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_block_config_t smifBlockConfig =
+{
+ /* The number of SMIF memories defined. */
+ .memCount = CY_SMIF_DEVICE_NUM,
+ /* The pointer to the array of memory config structures of size memCount. */
+ .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+ /* The version of the SMIF driver. */
+ .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+ /* The version of the SMIF driver. */
+ .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+};
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.h
new file mode 100644
index 0000000000..1f4fb5dfca
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_qspi_memslot.h
@@ -0,0 +1,49 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+
+extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CY_SMIF_MEMCONFIG_H*/
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c
index 8a1e655157..31a3774214 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.c
@@ -34,12 +34,12 @@ void init_cycfg_routing(void)
{
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
- Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT44, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
- Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
- Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
- Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT1, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT44, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT1, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h
index 9d9b019eae..16be9931a1 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_routing.h
@@ -32,14 +32,17 @@ extern "C" {
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
-#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM1_LINE_COMPL1
+#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
+#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
+#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI
#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI
#define ioss_0_port_2_pin_2_HSIOM P2_2_DSI_DSI
@@ -60,26 +63,26 @@ void init_cycfg_routing(void);
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
+#define CYBSP_SDIO_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
+#define CYBSP_SDIO_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
+#define CYBSP_SDIO_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT4
+#define CYBSP_SDIO_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
+#define CYBSP_SDIO_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
+#define CYBSP_SDIO_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
+#define CYBSP_SDIO_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
+#define CYBSP_SDIO_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT1
#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0
#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1
#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
-#define udb_0_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
-#define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT1
-#define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT4
-#define udb_0_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
-#define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
-#define udb_0_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
-#define udb_0_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
-#define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
#if defined(__cplusplus)
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.c
similarity index 82%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.c
index 306a16a389..9f12369c1a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_platform.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.c
@@ -1,8 +1,8 @@
/*******************************************************************************
-* File Name: cycfg_platform.c
+* File Name: cycfg_system.c
*
* Description:
-* Platform configuration
+* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
@@ -22,7 +22,7 @@
* limitations under the License.
********************************************************************************/
-#include "cycfg_platform.h"
+#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
@@ -64,10 +64,10 @@
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
-#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_USING_PMIC 0
-#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD
-#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
@@ -127,21 +127,21 @@ __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
}
__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
{
- Cy_SysClk_ClkHfSetSource(1U, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(1U, CY_SYSCLK_CLKHF_NO_DIVIDE);
- Cy_SysClk_ClkHfEnable(1U);
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
- Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
- Cy_SysClk_ClkHfEnable(2U);
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
- Cy_SysClk_ClkHfSetSource(3U, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(3U, CY_SYSCLK_CLKHF_NO_DIVIDE);
- Cy_SysClk_ClkHfEnable(3U);
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
@@ -209,42 +209,58 @@ __STATIC_INLINE void Cy_SysClk_WcoInit()
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
+__STATIC_INLINE void init_cycfg_power(void)
+{
+ /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
+ #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+ if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+ {
+ Cy_SysLib_ResetBackupDomain();
+ Cy_SysClk_IloDisable();
+ Cy_SysClk_IloInit();
+ }
+ #else /* Dedicated Supply */
+ Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
+ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+ /* Configure core regulator */
+ #if CY_CFG_PWR_USING_LDO
+ Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+ Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
+ #else
+ Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
+ #endif /* CY_CFG_PWR_USING_LDO */
+ /* Configure PMIC */
+ Cy_SysPm_UnlockPmic();
+ #if CY_CFG_PWR_USING_PMIC
+ Cy_SysPm_PmicEnableOutput();
+ #else
+ Cy_SysPm_PmicDisableOutput();
+ #endif /* CY_CFG_PWR_USING_PMIC */
+}
-void init_cycfg_platform(void)
+void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
- #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD)
- if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
- {
- Cy_SysLib_ResetBackupDomain();
- Cy_SysClk_IloDisable();
- Cy_SysClk_IloInit();
- }
- #endif
#ifdef CY_CFG_PWR_ENABLED
- /* Configure power mode */
- #if CY_CFG_PWR_USING_LDO
- Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
- #else
- Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE);
- #endif
- /* Configure PMIC */
- Cy_SysPm_UnlockPmic();
- #if CY_CFG_PWR_USING_PMIC
- Cy_SysPm_PmicEnableOutput();
- #else
- Cy_SysPm_PmicDisableOutput();
- #endif
- #endif
+ #ifdef CY_CFG_PWR_INIT
+ init_cycfg_power();
+ #else
+ #warning Power system will not be configured. Update power personality to v1.20 or later.
+ #endif /* CY_CFG_PWR_INIT */
+ #endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
- Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+ {
+ (void)Cy_SysClk_PllDisable(pll);
+ }
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
@@ -260,61 +276,6 @@ void init_cycfg_platform(void)
(void)Cy_BLE_EcoReset();
#endif
- #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15);
- #endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
@@ -547,6 +508,14 @@ void init_cycfg_platform(void)
#error the IMO must be enabled for proper chip operation
#endif
+ #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+ Cy_SysClk_MfoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+ Cy_SysClk_ClkMfInit();
+ #endif
+
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.h
new file mode 100644
index 0000000000..644e36fccc
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/cycfg_system.h
@@ -0,0 +1,90 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_systick.h"
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define srss_0_clock_0_hfclk_1_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF1 1UL
+#define srss_0_clock_0_hfclk_2_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF2 2UL
+#define srss_0_clock_0_hfclk_3_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF3 3UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_timerclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/qspi_config.cfg
new file mode 100644
index 0000000000..a561643dcf
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/GeneratedSource/qspi_config.cfg
@@ -0,0 +1,2 @@
+set SMIF_BANKS {
+}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/design.modus
new file mode 100644
index 0000000000..bf3e7a0e77
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/design.modus
@@ -0,0 +1,1183 @@
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diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c
index 74c28aba2c..cb430a4164 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.c
@@ -26,9 +26,9 @@
void init_cycfg_all(void)
{
+ init_cycfg_system();
init_cycfg_clocks();
+ init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
- init_cycfg_platform();
- init_cycfg_routing();
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h
index ac6033d2bd..9abc7f0f4a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg.h
@@ -30,11 +30,11 @@ extern "C" {
#endif
#include "cycfg_notices.h"
+#include "cycfg_system.h"
#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
-#include "cycfg_platform.h"
-#include "cycfg_routing.h"
void init_cycfg_all(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c
index 9a6a4e3cf9..42e905fca4 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.c
@@ -38,8 +38,4 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
-
- Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
- Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 0U);
- Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h
index ce944e4bd0..34da2e34d9 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_clocks.h
@@ -32,14 +32,15 @@
extern "C" {
#endif
-#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_0_NUM 0U
-#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_1_NUM 1U
-#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_2_NUM 2U
-#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_3_NUM 3U
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_CLK_DIV_NUM 0U
+#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
+#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
void init_cycfg_clocks(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c
index 72e28490f0..2c05696e1c 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.c
@@ -24,13 +24,11 @@
#include "cycfg_peripherals.h"
-#define PWM_INPUT_DISABLED 0x7U
-
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
-const cy_stc_scb_uart_config_t BT_UART_config =
+const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@@ -58,7 +56,7 @@ const cy_stc_scb_uart_config_t BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
-const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
+const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
.slaveAddress1 = 8U,
@@ -66,7 +64,7 @@ const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
-const cy_stc_scb_uart_config_t KITPROG_UART_config =
+const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@@ -94,31 +92,31 @@ const cy_stc_scb_uart_config_t KITPROG_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
-cy_en_sd_host_card_capacity_t RADIO_cardCapacity = CY_SD_HOST_SDSC;
-cy_en_sd_host_card_type_t RADIO_cardType = CY_SD_HOST_NOT_EMMC;
-uint32_t RADIO_rca = 0u;
-const cy_stc_sd_host_init_config_t RADIO_config =
+cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
+cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
+uint32_t CYBSP_RADIO_rca = 0u;
+const cy_stc_sd_host_init_config_t CYBSP_RADIO_config =
{
.emmc = false,
.dmaType = CY_SD_HOST_DMA_SDMA,
.enableLedControl = false,
};
-cy_stc_sd_host_sd_card_config_t RADIO_card_cfg =
+cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg =
{
.lowVoltageSignaling = false,
.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
- .cardType = &RADIO_cardType,
- .rca = &RADIO_rca,
- .cardCapacity = &RADIO_cardCapacity,
+ .cardType = &CYBSP_RADIO_cardType,
+ .rca = &CYBSP_RADIO_rca,
+ .cardCapacity = &CYBSP_RADIO_cardCapacity,
};
-const cy_stc_smif_config_t QSPI_config =
+const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
- .deselectDelay = QSPI_DESELECT_DELAY,
+ .deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
-const cy_stc_mcwdt_config_t MCWDT0_config =
+const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
.c1Match = 32768U,
@@ -131,7 +129,7 @@ const cy_stc_mcwdt_config_t MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
-const cy_stc_rtc_config_t RTC_config =
+const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
.min = 0U,
@@ -143,34 +141,6 @@ const cy_stc_rtc_config_t RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
-const cy_stc_tcpwm_pwm_config_t PWM_config =
-{
- .pwmMode = CY_TCPWM_PWM_MODE_PWM,
- .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
- .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
- .deadTimeClocks = 0,
- .runMode = CY_TCPWM_PWM_CONTINUOUS,
- .period0 = 32000,
- .period1 = 32768,
- .enablePeriodSwap = false,
- .compare0 = 16384,
- .compare1 = 16384,
- .enableCompareSwap = false,
- .interruptSources = CY_TCPWM_INT_NONE,
- .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE,
- .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE,
- .killMode = CY_TCPWM_PWM_STOP_ON_KILL,
- .swapInputMode = PWM_INPUT_DISABLED & 0x3U,
- .swapInput = CY_TCPWM_INPUT_0,
- .reloadInputMode = PWM_INPUT_DISABLED & 0x3U,
- .reloadInput = CY_TCPWM_INPUT_0,
- .startInputMode = PWM_INPUT_DISABLED & 0x3U,
- .startInput = CY_TCPWM_INPUT_0,
- .killInputMode = PWM_INPUT_DISABLED & 0x3U,
- .killInput = CY_TCPWM_INPUT_0,
- .countInputMode = PWM_INPUT_DISABLED & 0x3U,
- .countInput = CY_TCPWM_INPUT_1,
-};
void init_cycfg_peripherals(void)
@@ -182,6 +152,4 @@ void init_cycfg_peripherals(void)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
-
- Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U);
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h
index 2a1bfa380e..24a66b86c5 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_peripherals.h
@@ -34,13 +34,12 @@
#include "cy_smif.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
-#include "cy_tcpwm_pwm.h"
-#include "cycfg_routing.h"
#if defined(__cplusplus)
extern "C" {
#endif
+#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 50000000u
@@ -74,59 +73,62 @@ extern "C" {
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
-#define CapSense_HW CSD0
-#define CapSense_IRQ csd_interrupt_IRQn
-#define BT_UART_HW SCB2
-#define BT_UART_IRQ scb_2_interrupt_IRQn
-#define CSD_COMM_HW SCB3
-#define CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define KITPROG_UART_HW SCB5
-#define KITPROG_UART_IRQ scb_5_interrupt_IRQn
-#define RADIO_HW SDHC0
-#define RADIO_IRQ sdhc_0_interrupt_general_IRQn
-#define QSPI_HW SMIF0
-#define QSPI_IRQ smif_interrupt_IRQn
-#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
-#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
-#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
-#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
-#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
-#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
-#define QSPI_DATALINES0_1 (1UL)
-#define QSPI_DATALINES2_3 (1UL)
-#define QSPI_DATALINES4_5 (0UL)
-#define QSPI_DATALINES6_7 (0UL)
-#define QSPI_SS0 (1UL)
-#define QSPI_SS1 (0UL)
-#define QSPI_SS2 (0UL)
-#define QSPI_SS3 (0UL)
-#define QSPI_DESELECT_DELAY 7
-#define MCWDT0_HW MCWDT_STRUCT0
-#define RTC_10_MONTH_OFFSET (28U)
-#define RTC_MONTH_OFFSET (24U)
-#define RTC_10_DAY_OFFSET (20U)
-#define RTC_DAY_OFFSET (16U)
-#define RTC_1000_YEAR_OFFSET (12U)
-#define RTC_100_YEAR_OFFSET (8U)
-#define RTC_10_YEAR_OFFSET (4U)
-#define RTC_YEAR_OFFSET (0U)
-#define PWM_HW TCPWM0
-#define PWM_NUM 1UL
-#define PWM_MASK (1UL << 1)
+#define CYBSP_CSD_HW CSD0
+#define CYBSP_CSD_IRQ csd_interrupt_IRQn
+#define CYBSP_BT_UART_ENABLED 1U
+#define CYBSP_BT_UART_HW SCB2
+#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
+#define CYBSP_CSD_COMM_ENABLED 1U
+#define CYBSP_CSD_COMM_HW SCB3
+#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
+#define CYBSP_DEBUG_UART_ENABLED 1U
+#define CYBSP_DEBUG_UART_HW SCB5
+#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
+#define CYBSP_RADIO_ENABLED 1U
+#define CYBSP_RADIO_HW SDHC0
+#define CYBSP_RADIO_IRQ sdhc_0_interrupt_general_IRQn
+#define CYBSP_QSPI_ENABLED 1U
+#define CYBSP_QSPI_HW SMIF0
+#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
+#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
+#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
+#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
+#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
+#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
+#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
+#define CYBSP_QSPI_DATALINES0_1 (1UL)
+#define CYBSP_QSPI_DATALINES2_3 (1UL)
+#define CYBSP_QSPI_DATALINES4_5 (0UL)
+#define CYBSP_QSPI_DATALINES6_7 (0UL)
+#define CYBSP_QSPI_SS0 (1UL)
+#define CYBSP_QSPI_SS1 (0UL)
+#define CYBSP_QSPI_SS2 (0UL)
+#define CYBSP_QSPI_SS3 (0UL)
+#define CYBSP_QSPI_DESELECT_DELAY 7
+#define CYBSP_MCWDT0_ENABLED 1U
+#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
+#define CYBSP_RTC_ENABLED 1U
+#define CYBSP_RTC_10_MONTH_OFFSET (28U)
+#define CYBSP_RTC_MONTH_OFFSET (24U)
+#define CYBSP_RTC_10_DAY_OFFSET (20U)
+#define CYBSP_RTC_DAY_OFFSET (16U)
+#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
+#define CYBSP_RTC_100_YEAR_OFFSET (8U)
+#define CYBSP_RTC_10_YEAR_OFFSET (4U)
+#define CYBSP_RTC_YEAR_OFFSET (0U)
extern cy_stc_csd_context_t cy_csd_0_context;
-extern const cy_stc_scb_uart_config_t BT_UART_config;
-extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
-extern cy_en_sd_host_card_capacity_t RADIO_cardCapacity;
-extern cy_en_sd_host_card_type_t RADIO_cardType;
-extern uint32_t RADIO_rca;
-extern const cy_stc_sd_host_init_config_t RADIO_config;
-extern cy_stc_sd_host_sd_card_config_t RADIO_card_cfg;
-extern const cy_stc_smif_config_t QSPI_config;
-extern const cy_stc_mcwdt_config_t MCWDT0_config;
-extern const cy_stc_rtc_config_t RTC_config;
-extern const cy_stc_tcpwm_pwm_config_t PWM_config;
+extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
+extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
+extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+extern cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity;
+extern cy_en_sd_host_card_type_t CYBSP_RADIO_cardType;
+extern uint32_t CYBSP_RADIO_rca;
+extern const cy_stc_sd_host_init_config_t CYBSP_RADIO_config;
+extern cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg;
+extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
+extern const cy_stc_rtc_config_t CYBSP_RTC_config;
void init_cycfg_peripherals(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c
index 7f16b5f459..43b7426f58 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.c
@@ -24,704 +24,656 @@
#include "cycfg_pins.h"
-const cy_stc_gpio_pin_config_t WCO_IN_config =
+const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = WCO_IN_HSIOM,
+ .hsiom = CYBSP_WCO_IN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t WCO_OUT_config =
+const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = WCO_OUT_HSIOM,
+ .hsiom = CYBSP_WCO_OUT_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_RED_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_RED_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t SW2_config =
+const cy_stc_gpio_pin_config_t CYBSP_BTN2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
- .hsiom = SW2_HSIOM,
+ .hsiom = CYBSP_BTN2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_BLUE_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_BLUE_HSIOM,
+ .hsiom = CYBSP_QSPI_SS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_SS0_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_QSPI_DATA3_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_QSPI_DATA2_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_QSPI_DATA1_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_QSPI_DATA0_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = QSPI_SS0_HSIOM,
+ .hsiom = CYBSP_QSPI_SCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA3_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA2_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA1_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA0_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = QSPI_SPI_CLOCK_HSIOM,
+ .hsiom = CYBSP_LED_RED_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED9_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED9_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t CSD_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_TX_HSIOM,
+ .hsiom = CYBSP_CSD_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_GREEN_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_GREEN_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t LED8_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED8_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t SDHC0_DAT0_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT0_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_DAT0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT1_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT1_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_DAT1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT2_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT2_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_DAT2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT3_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT3_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_DAT3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_CMD_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_CMD_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_CLK_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_CLK_HSIOM,
+ .hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_UART_RX_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
- .hsiom = BT_UART_RX_HSIOM,
+ .hsiom = CYBSP_BT_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_UART_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = BT_UART_TX_HSIOM,
+ .hsiom = CYBSP_BT_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_UART_RTS_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = BT_UART_RTS_HSIOM,
+ .hsiom = CYBSP_BT_UART_RTS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_UART_CTS_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
- .hsiom = BT_UART_CTS_HSIOM,
+ .hsiom = CYBSP_BT_UART_CTS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_POWER_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF,
- .hsiom = BT_POWER_HSIOM,
+ .hsiom = CYBSP_BT_POWER_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = BT_HOST_WAKE_HSIOM,
+ .hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = BT_DEVICE_WAKE_HSIOM,
+ .hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t UART_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = UART_TX_HSIOM,
+ .hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t EZI2C_SCL_config =
+const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
- .hsiom = EZI2C_SCL_HSIOM,
+ .hsiom = CYBSP_EZI2C_SCL_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t EZI2C_SDA_config =
+const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESLOW,
- .hsiom = EZI2C_SDA_HSIOM,
+ .hsiom = CYBSP_EZI2C_SDA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWO_config =
+const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = SWO_HSIOM,
+ .hsiom = CYBSP_SWO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWDIO_config =
+const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
- .hsiom = SWDIO_HSIOM,
+ .hsiom = CYBSP_SWDIO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWDCK_config =
+const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
- .hsiom = SWDCK_HSIOM,
+ .hsiom = CYBSP_SWDCK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CINA_config =
+const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CINA_HSIOM,
+ .hsiom = CYBSP_CINA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CINB_config =
+const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CINB_HSIOM,
+ .hsiom = CYBSP_CINB_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CMOD_config =
+const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CMOD_HSIOM,
+ .hsiom = CYBSP_CMOD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_BTN0_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_BTN0_HSIOM,
+ .hsiom = CYBSP_CSD_BTN0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_BTN1_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_BTN1_HSIOM,
+ .hsiom = CYBSP_CSD_BTN1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD0_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD0_HSIOM,
+ .hsiom = CYBSP_CSD_SLD0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD1_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD1_HSIOM,
+ .hsiom = CYBSP_CSD_SLD1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD2_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD2_HSIOM,
+ .hsiom = CYBSP_CSD_SLD2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD3_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD3_HSIOM,
+ .hsiom = CYBSP_CSD_SLD3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD4_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD4_HSIOM,
+ .hsiom = CYBSP_CSD_SLD4_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
@@ -732,72 +684,66 @@ const cy_stc_gpio_pin_config_t CSD_SLD4_config =
void init_cycfg_pins(void)
{
- Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config);
+ Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
- Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config);
+ Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
- Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config);
+ Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
- Cy_GPIO_Pin_Init(SW2_PORT, SW2_PIN, &SW2_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
- Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
- Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
- Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
- Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
- Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
- Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config);
-
- Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config);
-
- Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
- Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT0_PORT, CYBSP_WIFI_SDIO_DAT0_PIN, &CYBSP_WIFI_SDIO_DAT0_config);
- Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT1_PORT, CYBSP_WIFI_SDIO_DAT1_PIN, &CYBSP_WIFI_SDIO_DAT1_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT0_PORT, SDHC0_DAT0_PIN, &SDHC0_DAT0_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT2_PORT, CYBSP_WIFI_SDIO_DAT2_PIN, &CYBSP_WIFI_SDIO_DAT2_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT1_PORT, SDHC0_DAT1_PIN, &SDHC0_DAT1_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT3_PORT, CYBSP_WIFI_SDIO_DAT3_PIN, &CYBSP_WIFI_SDIO_DAT3_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT2_PORT, SDHC0_DAT2_PIN, &SDHC0_DAT2_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT3_PORT, SDHC0_DAT3_PIN, &SDHC0_DAT3_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
- Cy_GPIO_Pin_Init(SDHC0_CMD_PORT, SDHC0_CMD_PIN, &SDHC0_CMD_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
- Cy_GPIO_Pin_Init(SDHC0_CLK_PORT, SDHC0_CLK_PIN, &SDHC0_CLK_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
- Cy_GPIO_Pin_Init(BT_UART_RX_PORT, BT_UART_RX_PIN, &BT_UART_RX_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
- Cy_GPIO_Pin_Init(BT_UART_TX_PORT, BT_UART_TX_PIN, &BT_UART_TX_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
- Cy_GPIO_Pin_Init(BT_UART_RTS_PORT, BT_UART_RTS_PIN, &BT_UART_RTS_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
- Cy_GPIO_Pin_Init(BT_UART_CTS_PORT, BT_UART_CTS_PIN, &BT_UART_CTS_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
- Cy_GPIO_Pin_Init(BT_POWER_PORT, BT_POWER_PIN, &BT_POWER_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
- Cy_GPIO_Pin_Init(BT_HOST_WAKE_PORT, BT_HOST_WAKE_PIN, &BT_HOST_WAKE_config);
+ Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
- Cy_GPIO_Pin_Init(BT_DEVICE_WAKE_PORT, BT_DEVICE_WAKE_PIN, &BT_DEVICE_WAKE_config);
+ Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
- Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config);
+ Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
- Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config);
+ Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
- Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config);
+ Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
- Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config);
+ Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
- Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config);
-
- Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config);
+ Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h
index d0709a2adc..c6a2238ed6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_pins.h
@@ -33,491 +33,499 @@
extern "C" {
#endif
-#define WCO_IN_PORT GPIO_PRT0
-#define WCO_IN_PIN 0U
-#define WCO_IN_NUM 0U
-#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define WCO_IN_INIT_DRIVESTATE 1
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_0_HSIOM
#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define WCO_OUT_PORT GPIO_PRT0
-#define WCO_OUT_PIN 1U
-#define WCO_OUT_NUM 1U
-#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define WCO_OUT_INIT_DRIVESTATE 1
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_1_HSIOM
#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define LED_RED_PORT GPIO_PRT0
-#define LED_RED_PIN 3U
-#define LED_RED_NUM 3U
-#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_RED_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_3_HSIOM
- #define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
-#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
-#define SW2_PORT GPIO_PRT0
-#define SW2_PIN 4U
-#define SW2_NUM 4U
-#define SW2_DRIVEMODE CY_GPIO_DM_PULLUP
-#define SW2_INIT_DRIVESTATE 1
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_BTN2_ENABLED 1U
+#define CYBSP_BTN2_PORT GPIO_PRT0
+#define CYBSP_BTN2_PIN 4U
+#define CYBSP_BTN2_NUM 4U
+#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_BTN2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define SW2_IRQ ioss_interrupts_gpio_0_IRQn
-#define LED_BLUE_PORT GPIO_PRT11
-#define LED_BLUE_PIN 1U
-#define LED_BLUE_NUM 1U
-#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_BLUE_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_11_pin_1_HSIOM
- #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_SS0_PORT GPIO_PRT11
-#define QSPI_SS0_PIN 2U
-#define QSPI_SS0_NUM 2U
-#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define QSPI_SS0_INIT_DRIVESTATE 1
+#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
+#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_QSPI_SS_ENABLED 1U
+#define CYBSP_QSPI_SS_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS_PIN 2U
+#define CYBSP_QSPI_SS_NUM 2U
+#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_2_HSIOM
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA3_PORT GPIO_PRT11
-#define QSPI_DATA3_PIN 3U
-#define QSPI_DATA3_NUM 3U
-#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA3_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_DATA3_ENABLED 1U
+#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA3_PIN 3U
+#define CYBSP_QSPI_DATA3_NUM 3U
+#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_3_HSIOM
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA2_PORT GPIO_PRT11
-#define QSPI_DATA2_PIN 4U
-#define QSPI_DATA2_NUM 4U
-#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA2_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_DATA2_ENABLED 1U
+#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA2_PIN 4U
+#define CYBSP_QSPI_DATA2_NUM 4U
+#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_4_HSIOM
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA1_PORT GPIO_PRT11
-#define QSPI_DATA1_PIN 5U
-#define QSPI_DATA1_NUM 5U
-#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA1_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_DATA1_ENABLED 1U
+#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA1_PIN 5U
+#define CYBSP_QSPI_DATA1_NUM 5U
+#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_5_HSIOM
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA0_PORT GPIO_PRT11
-#define QSPI_DATA0_PIN 6U
-#define QSPI_DATA0_NUM 6U
-#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA0_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_DATA0_ENABLED 1U
+#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
+#define CYBSP_QSPI_DATA0_PIN 6U
+#define CYBSP_QSPI_DATA0_NUM 6U
+#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_DATA0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_6_HSIOM
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_SPI_CLOCK_PORT GPIO_PRT11
-#define QSPI_SPI_CLOCK_PIN 7U
-#define QSPI_SPI_CLOCK_NUM 7U
-#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_SCK_ENABLED 1U
+#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SCK_PIN 7U
+#define CYBSP_QSPI_SCK_NUM 7U
+#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_7_HSIOM
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define LED9_PORT GPIO_PRT13
-#define LED9_PIN 7U
-#define LED9_NUM 7U
-#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED9_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_LED_RED_ENABLED 1U
+#define CYBSP_LED_RED_PORT GPIO_PRT13
+#define CYBSP_LED_RED_PIN 7U
+#define CYBSP_LED_RED_NUM 7U
+#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED_RED_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_7_HSIOM
#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define LED9_IRQ ioss_interrupts_gpio_13_IRQn
-#define CSD_TX_PORT GPIO_PRT1
-#define CSD_TX_PIN 0U
-#define CSD_TX_NUM 0U
-#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_TX_INIT_DRIVESTATE 1
+#define CYBSP_LED_RED_HSIOM ioss_0_port_13_pin_7_HSIOM
+#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_13_IRQn
+#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_0_HSIOM
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define LED_GREEN_PORT GPIO_PRT1
-#define LED_GREEN_PIN 1U
-#define LED_GREEN_NUM 1U
-#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_GREEN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_1_HSIOM
- #define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
-#define LED8_PORT GPIO_PRT1
-#define LED8_PIN 5U
-#define LED8_NUM 5U
-#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED8_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_5_HSIOM
- #define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define LED8_IRQ ioss_interrupts_gpio_1_IRQn
-#define SDHC0_DAT0_PORT GPIO_PRT2
-#define SDHC0_DAT0_PIN 0U
-#define SDHC0_DAT0_NUM 0U
-#define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT0_INIT_DRIVESTATE 1
+#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_WIFI_SDIO_DAT0_ENABLED 1U
+#define CYBSP_WIFI_SDIO_DAT0_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_DAT0_PIN 0U
+#define CYBSP_WIFI_SDIO_DAT0_NUM 0U
+#define CYBSP_WIFI_SDIO_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_DAT0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_0_HSIOM
#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
-#define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_DAT1_PORT GPIO_PRT2
-#define SDHC0_DAT1_PIN 1U
-#define SDHC0_DAT1_NUM 1U
-#define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT1_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
+#define CYBSP_WIFI_SDIO_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_DAT1_ENABLED 1U
+#define CYBSP_WIFI_SDIO_DAT1_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_DAT1_PIN 1U
+#define CYBSP_WIFI_SDIO_DAT1_NUM 1U
+#define CYBSP_WIFI_SDIO_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_DAT1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_1_HSIOM
#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
-#define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_DAT2_PORT GPIO_PRT2
-#define SDHC0_DAT2_PIN 2U
-#define SDHC0_DAT2_NUM 2U
-#define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT2_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
+#define CYBSP_WIFI_SDIO_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_DAT2_ENABLED 1U
+#define CYBSP_WIFI_SDIO_DAT2_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_DAT2_PIN 2U
+#define CYBSP_WIFI_SDIO_DAT2_NUM 2U
+#define CYBSP_WIFI_SDIO_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_DAT2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_2_HSIOM
#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
-#define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_DAT3_PORT GPIO_PRT2
-#define SDHC0_DAT3_PIN 3U
-#define SDHC0_DAT3_NUM 3U
-#define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT3_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
+#define CYBSP_WIFI_SDIO_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_DAT3_ENABLED 1U
+#define CYBSP_WIFI_SDIO_DAT3_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_DAT3_PIN 3U
+#define CYBSP_WIFI_SDIO_DAT3_NUM 3U
+#define CYBSP_WIFI_SDIO_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_DAT3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_3_HSIOM
#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
-#define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_CMD_PORT GPIO_PRT2
-#define SDHC0_CMD_PIN 4U
-#define SDHC0_CMD_NUM 4U
-#define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_CMD_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
+#define CYBSP_WIFI_SDIO_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
+#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_CMD_PIN 4U
+#define CYBSP_WIFI_SDIO_CMD_NUM 4U
+#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_4_HSIOM
#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
-#define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_CLK_PORT GPIO_PRT2
-#define SDHC0_CLK_PIN 5U
-#define SDHC0_CLK_NUM 5U
-#define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_CLK_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
+#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
+#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_CLK_PIN 5U
+#define CYBSP_WIFI_SDIO_CLK_NUM 5U
+#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_5_HSIOM
#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
-#define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn
-#define BT_UART_RX_PORT GPIO_PRT3
-#define BT_UART_RX_PIN 0U
-#define BT_UART_RX_NUM 0U
-#define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define BT_UART_RX_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
+#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_BT_UART_RX_ENABLED 1U
+#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RX_PIN 0U
+#define CYBSP_BT_UART_RX_NUM 0U
+#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_0_HSIOM
#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
-#define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_UART_TX_PORT GPIO_PRT3
-#define BT_UART_TX_PIN 1U
-#define BT_UART_TX_NUM 1U
-#define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define BT_UART_TX_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_UART_TX_ENABLED 1U
+#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_TX_PIN 1U
+#define CYBSP_BT_UART_TX_NUM 1U
+#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_1_HSIOM
#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
-#define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_UART_RTS_PORT GPIO_PRT3
-#define BT_UART_RTS_PIN 2U
-#define BT_UART_RTS_NUM 2U
-#define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define BT_UART_RTS_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
+#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_UART_RTS_ENABLED 1U
+#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RTS_PIN 2U
+#define CYBSP_BT_UART_RTS_NUM 2U
+#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_2_HSIOM
#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
-#define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_UART_CTS_PORT GPIO_PRT3
-#define BT_UART_CTS_PIN 3U
-#define BT_UART_CTS_NUM 3U
-#define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define BT_UART_CTS_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
+#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_UART_CTS_ENABLED 1U
+#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_CTS_PIN 3U
+#define CYBSP_BT_UART_CTS_NUM 3U
+#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_3_HSIOM
#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
-#define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_POWER_PORT GPIO_PRT3
-#define BT_POWER_PIN 4U
-#define BT_POWER_NUM 4U
-#define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
-#define BT_POWER_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
+#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_POWER_ENABLED 1U
+#define CYBSP_BT_POWER_PORT GPIO_PRT3
+#define CYBSP_BT_POWER_PIN 4U
+#define CYBSP_BT_POWER_NUM 4U
+#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
+#define CYBSP_BT_POWER_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_4_HSIOM
#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
-#define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_HOST_WAKE_PORT GPIO_PRT3
-#define BT_HOST_WAKE_PIN 5U
-#define BT_HOST_WAKE_NUM 5U
-#define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define BT_HOST_WAKE_INIT_DRIVESTATE 0
+#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
+#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_HOST_WAKE_ENABLED 1U
+#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
+#define CYBSP_BT_HOST_WAKE_PIN 5U
+#define CYBSP_BT_HOST_WAKE_NUM 5U
+#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_3_pin_5_HSIOM
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
-#define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_DEVICE_WAKE_PORT GPIO_PRT4
-#define BT_DEVICE_WAKE_PIN 0U
-#define BT_DEVICE_WAKE_NUM 0U
-#define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
+#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
+#define CYBSP_BT_DEVICE_WAKE_PIN 0U
+#define CYBSP_BT_DEVICE_WAKE_NUM 0U
+#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_4_pin_0_HSIOM
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
-#define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
-#define UART_TX_PORT GPIO_PRT5
-#define UART_TX_PIN 1U
-#define UART_TX_NUM 1U
-#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define UART_TX_INIT_DRIVESTATE 1
+#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
+#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#define CYBSP_DEBUG_UART_RX_ENABLED 1U
+#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
+#define CYBSP_DEBUG_UART_RX_PIN 0U
+#define CYBSP_DEBUG_UART_RX_NUM 0U
+#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_5_pin_0_HSIOM
+ #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
+#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
+#define CYBSP_DEBUG_UART_TX_ENABLED 1U
+#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
+#define CYBSP_DEBUG_UART_TX_PIN 1U
+#define CYBSP_DEBUG_UART_TX_NUM 1U
+#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_1_HSIOM
#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#define EZI2C_SCL_PORT GPIO_PRT6
-#define EZI2C_SCL_PIN 0U
-#define EZI2C_SCL_NUM 0U
-#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define EZI2C_SCL_INIT_DRIVESTATE 1
+#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
+#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_0_HSIOM
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define EZI2C_SDA_PORT GPIO_PRT6
-#define EZI2C_SDA_PIN 1U
-#define EZI2C_SDA_NUM 1U
-#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define EZI2C_SDA_INIT_DRIVESTATE 1
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_1_HSIOM
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWO_PORT GPIO_PRT6
-#define SWO_PIN 4U
-#define SWO_NUM 4U
-#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define SWO_INIT_DRIVESTATE 1
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWDIO_PORT GPIO_PRT6
-#define SWDIO_PIN 6U
-#define SWDIO_NUM 6U
-#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define SWDIO_INIT_DRIVESTATE 1
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_6_HSIOM
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWDCK_PORT GPIO_PRT6
-#define SWDCK_PIN 7U
-#define SWDCK_NUM 7U
-#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define SWDCK_INIT_DRIVESTATE 1
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define CINA_PORT GPIO_PRT7
-#define CINA_PIN 1U
-#define CINA_NUM 1U
-#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CINA_INIT_DRIVESTATE 1
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_1_HSIOM
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CINB_PORT GPIO_PRT7
-#define CINB_PIN 2U
-#define CINB_NUM 2U
-#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CINB_INIT_DRIVESTATE 1
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_2_HSIOM
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CMOD_PORT GPIO_PRT7
-#define CMOD_PIN 7U
-#define CMOD_NUM 7U
-#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CMOD_INIT_DRIVESTATE 1
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_7_HSIOM
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CSD_BTN0_PORT GPIO_PRT8
-#define CSD_BTN0_PIN 1U
-#define CSD_BTN0_NUM 1U
-#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_BTN0_INIT_DRIVESTATE 1
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_1_HSIOM
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_BTN1_PORT GPIO_PRT8
-#define CSD_BTN1_PIN 2U
-#define CSD_BTN1_NUM 2U
-#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_BTN1_INIT_DRIVESTATE 1
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_2_HSIOM
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD0_PORT GPIO_PRT8
-#define CSD_SLD0_PIN 3U
-#define CSD_SLD0_NUM 3U
-#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD0_INIT_DRIVESTATE 1
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_3_HSIOM
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD1_PORT GPIO_PRT8
-#define CSD_SLD1_PIN 4U
-#define CSD_SLD1_NUM 4U
-#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD1_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_4_HSIOM
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD2_PORT GPIO_PRT8
-#define CSD_SLD2_PIN 5U
-#define CSD_SLD2_NUM 5U
-#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD2_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_5_HSIOM
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD3_PORT GPIO_PRT8
-#define CSD_SLD3_PIN 6U
-#define CSD_SLD3_NUM 6U
-#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD3_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_6_HSIOM
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD4_PORT GPIO_PRT8
-#define CSD_SLD4_PIN 7U
-#define CSD_SLD4_NUM 7U
-#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD4_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_7_HSIOM
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-extern const cy_stc_gpio_pin_config_t WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t LED_RED_config;
-extern const cy_stc_gpio_pin_config_t SW2_config;
-extern const cy_stc_gpio_pin_config_t LED_BLUE_config;
-extern const cy_stc_gpio_pin_config_t QSPI_SS0_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config;
-extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config;
-extern const cy_stc_gpio_pin_config_t LED9_config;
-extern const cy_stc_gpio_pin_config_t CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t LED_GREEN_config;
-extern const cy_stc_gpio_pin_config_t LED8_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t BT_POWER_config;
-extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config;
-extern const cy_stc_gpio_pin_config_t UART_TX_config;
-extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t SWO_config;
-extern const cy_stc_gpio_pin_config_t SWDIO_config;
-extern const cy_stc_gpio_pin_config_t SWDCK_config;
-extern const cy_stc_gpio_pin_config_t CINA_config;
-extern const cy_stc_gpio_pin_config_t CINB_config;
-extern const cy_stc_gpio_pin_config_t CMOD_config;
-extern const cy_stc_gpio_pin_config_t CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD4_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
void init_cycfg_pins(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h
deleted file mode 100644
index aa4aeb6159..0000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_platform.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_platform.h
-*
-* Description:
-* Platform configuration
-* This file was automatically generated and should not be modified.
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PLATFORM_H)
-#define CYCFG_PLATFORM_H
-
-#include "cycfg_notices.h"
-#include "cy_sysclk.h"
-#include "cy_gpio.h"
-#include "cy_syspm.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
-#define CY_CFG_PWR_VDDA_MV 3300
-#define CY_CFG_PWR_VDDD_MV 3300
-#define CY_CFG_PWR_VBACKUP_MV 3300
-#define CY_CFG_PWR_VDD_NS_MV 3300
-#define CY_CFG_PWR_VDDIO0_MV 3300
-#define CY_CFG_PWR_VDDIO1_MV 3300
-
-void init_cycfg_platform(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PLATFORM_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.c
new file mode 100644
index 0000000000..25d22aef50
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.c
@@ -0,0 +1,264 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0xECU,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_QUAD,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0x01U,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_QUAD,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 8U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeEnCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x06U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeDisCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x04U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_eraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x21U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_chipEraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x60U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_programCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x12U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x35U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegWipCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x05U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x01U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_0 =
+{
+ /* Specifies the number of address bytes used by the memory slave device. */
+ .numOfAddrBytes = 0x04U,
+ /* The size of the memory. */
+ .memSize = 0x04000000U,
+ /* Specifies the Read command. */
+ .readCmd = &S25HL512T_SlaveSlot_0_readCmd,
+ /* Specifies the Write Enable command. */
+ .writeEnCmd = &S25HL512T_SlaveSlot_0_writeEnCmd,
+ /* Specifies the Write Disable command. */
+ .writeDisCmd = &S25HL512T_SlaveSlot_0_writeDisCmd,
+ /* Specifies the Erase command. */
+ .eraseCmd = &S25HL512T_SlaveSlot_0_eraseCmd,
+ /* Specifies the sector size of each erase. */
+ .eraseSize = 0x0001000U,
+ /* Specifies the Chip Erase command. */
+ .chipEraseCmd = &S25HL512T_SlaveSlot_0_chipEraseCmd,
+ /* Specifies the Program command. */
+ .programCmd = &S25HL512T_SlaveSlot_0_programCmd,
+ /* Specifies the page size for programming. */
+ .programSize = 0x0000100U,
+ /* Specifies the command to read the QE-containing status register. */
+ .readStsRegQeCmd = &S25HL512T_SlaveSlot_0_readStsRegQeCmd,
+ /* Specifies the command to read the WIP-containing status register. */
+ .readStsRegWipCmd = &S25HL512T_SlaveSlot_0_readStsRegWipCmd,
+ /* Specifies the command to write into the QE-containing status register. */
+ .writeStsRegQeCmd = &S25HL512T_SlaveSlot_0_writeStsRegQeCmd,
+ /* The mask for the status register. */
+ .stsRegBusyMask = 0x01U,
+ /* The mask for the status register. */
+ .stsRegQuadEnableMask = 0x02U,
+ /* The max time for the erase type-1 cycle-time in ms. */
+ .eraseTime = 42U,
+ /* The max time for the chip-erase cycle-time in ms. */
+ .chipEraseTime = 201000U,
+ /* The max time for the page-program cycle-time in us. */
+ .programTime = 418U
+};
+
+const cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_0 =
+{
+ /* Determines the slot number where the memory device is placed. */
+ .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+ /* Flags. */
+ .flags = CY_SMIF_FLAG_WR_EN,
+ /* The data-line selection options for a slave device. */
+ .dataSelect = CY_SMIF_DATA_SEL0,
+ /* The base address the memory slave is mapped to in the PSoC memory map.
+ Valid when the memory-mapped mode is enabled. */
+ .baseAddress = 0x18000000U,
+ /* The size allocated in the PSoC memory map, for the memory slave device.
+ The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+ .memMappedSize = 0x10000U,
+ /* If this memory device is one of the devices in the dual quad SPI configuration.
+ Valid when the memory mapped mode is enabled. */
+ .dualQuadSlots = 0,
+ /* The configuration of the device. */
+ .deviceCfg = &deviceCfg_S25HL512T_SlaveSlot_0
+};
+
+const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
+ &S25HL512T_SlaveSlot_0
+};
+
+const cy_stc_smif_block_config_t smifBlockConfig =
+{
+ /* The number of SMIF memories defined. */
+ .memCount = CY_SMIF_DEVICE_NUM,
+ /* The pointer to the array of memory config structures of size memCount. */
+ .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+ /* The version of the SMIF driver. */
+ .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+ /* The version of the SMIF driver. */
+ .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+};
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.h
new file mode 100644
index 0000000000..7217969c32
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_qspi_memslot.h
@@ -0,0 +1,49 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readCmd;
+extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeEnCmd;
+extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeDisCmd;
+extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_eraseCmd;
+extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_chipEraseCmd;
+extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_programCmd;
+extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegQeCmd;
+extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegWipCmd;
+extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeStsRegQeCmd;
+
+extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CY_SMIF_MEMCONFIG_H*/
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h
index 191672e599..17ec9db236 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_routing.h
@@ -32,14 +32,15 @@ extern "C" {
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
-#define ioss_0_port_11_pin_1_HSIOM P11_1_TCPWM0_LINE_COMPL1
+#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
+#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_2_pin_0_HSIOM P2_0_SDHC0_CARD_DAT_3TO00
#define ioss_0_port_2_pin_1_HSIOM P2_1_SDHC0_CARD_DAT_3TO01
#define ioss_0_port_2_pin_2_HSIOM P2_2_SDHC0_CARD_DAT_3TO02
@@ -50,22 +51,23 @@ void init_cycfg_routing(void);
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
+#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
-#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#if defined(__cplusplus)
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.c
similarity index 82%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.c
index 9cd3f7692b..b17c36bbc3 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_platform.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.c
@@ -1,8 +1,8 @@
/*******************************************************************************
-* File Name: cycfg_platform.c
+* File Name: cycfg_system.c
*
* Description:
-* Platform configuration
+* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
@@ -22,7 +22,7 @@
* limitations under the License.
********************************************************************************/
-#include "cycfg_platform.h"
+#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
@@ -38,6 +38,9 @@
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_ILO_ENABLED 1
#define CY_CFG_SYSCLK_IMO_ENABLED 1
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
@@ -51,14 +54,16 @@
#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
-#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_USING_PMIC 0
-#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD
-#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
@@ -106,9 +111,15 @@ __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
- Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
- Cy_SysClk_ClkHfEnable(2U);
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
+{
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
@@ -141,6 +152,10 @@ __STATIC_INLINE void Cy_SysClk_ClkPath4Init()
{
Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
}
+__STATIC_INLINE void Cy_SysClk_ClkPath5Init()
+{
+ Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE);
+}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(1U);
@@ -158,42 +173,58 @@ __STATIC_INLINE void Cy_SysClk_WcoInit()
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
+__STATIC_INLINE void init_cycfg_power(void)
+{
+ /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
+ #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+ if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+ {
+ Cy_SysLib_ResetBackupDomain();
+ Cy_SysClk_IloDisable();
+ Cy_SysClk_IloInit();
+ }
+ #else /* Dedicated Supply */
+ Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
+ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+ /* Configure core regulator */
+ #if CY_CFG_PWR_USING_LDO
+ Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+ Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
+ #else
+ Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
+ #endif /* CY_CFG_PWR_USING_LDO */
+ /* Configure PMIC */
+ Cy_SysPm_UnlockPmic();
+ #if CY_CFG_PWR_USING_PMIC
+ Cy_SysPm_PmicEnableOutput();
+ #else
+ Cy_SysPm_PmicDisableOutput();
+ #endif /* CY_CFG_PWR_USING_PMIC */
+}
-void init_cycfg_platform(void)
+void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
- #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD)
- if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
- {
- Cy_SysLib_ResetBackupDomain();
- Cy_SysClk_IloDisable();
- Cy_SysClk_IloInit();
- }
- #endif
#ifdef CY_CFG_PWR_ENABLED
- /* Configure power mode */
- #if CY_CFG_PWR_USING_LDO
- Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
- #else
- Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE);
- #endif
- /* Configure PMIC */
- Cy_SysPm_UnlockPmic();
- #if CY_CFG_PWR_USING_PMIC
- Cy_SysPm_PmicEnableOutput();
- #else
- Cy_SysPm_PmicDisableOutput();
- #endif
- #endif
+ #ifdef CY_CFG_PWR_INIT
+ init_cycfg_power();
+ #else
+ #warning Power system will not be configured. Update power personality to v1.20 or later.
+ #endif /* CY_CFG_PWR_INIT */
+ #endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
- Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+ {
+ (void)Cy_SysClk_PllDisable(pll);
+ }
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
@@ -209,61 +240,6 @@ void init_cycfg_platform(void)
(void)Cy_BLE_EcoReset();
#endif
- #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15);
- #endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
@@ -496,6 +472,14 @@ void init_cycfg_platform(void)
#error the IMO must be enabled for proper chip operation
#endif
+ #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+ Cy_SysClk_MfoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+ Cy_SysClk_ClkMfInit();
+ #endif
+
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.h
new file mode 100644
index 0000000000..75f065e226
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/cycfg_system.h
@@ -0,0 +1,85 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define srss_0_clock_0_hfclk_2_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF2 2UL
+#define srss_0_clock_0_hfclk_4_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF4 4UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_pathmux_5_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/qspi_config.cfg
new file mode 100644
index 0000000000..a561643dcf
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/GeneratedSource/qspi_config.cfg
@@ -0,0 +1,2 @@
+set SMIF_BANKS {
+}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/design.modus
new file mode 100644
index 0000000000..d67856d97d
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/TARGET_CY8CPROTO_062_4343W/design.modus
@@ -0,0 +1,885 @@
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diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c
index 74c28aba2c..cb430a4164 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.c
@@ -26,9 +26,9 @@
void init_cycfg_all(void)
{
+ init_cycfg_system();
init_cycfg_clocks();
+ init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
- init_cycfg_platform();
- init_cycfg_routing();
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h
index 1709481df2..3585cf91ba 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg.h
@@ -30,12 +30,12 @@ extern "C" {
#endif
#include "cycfg_notices.h"
+#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_dmas.h"
+#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
-#include "cycfg_platform.h"
-#include "cycfg_routing.h"
void init_cycfg_all(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c
index 5249f7d3a0..025d36c953 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.c
@@ -43,11 +43,15 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
- Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
- Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 1U);
- Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
-
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
+
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 5U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 5U, 6U);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 5U);
+
+ Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 6U);
+ Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 6U, 108U);
+ Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 6U);
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h
index 0da97983ce..96a4bf51aa 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_clocks.h
@@ -32,18 +32,27 @@
extern "C" {
#endif
-#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT
-#define peri_0_div_16_0_NUM 0U
-#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_0_NUM 0U
-#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_1_NUM 1U
-#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_2_NUM 2U
-#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_3_NUM 3U
-#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
-#define peri_0_div_8_4_NUM 4U
+#define CYBSP_USB_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_USB_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
+#define CYBSP_USB_UART_CLK_DIV_NUM 0U
+#define CYBSP_SDIO_CLK_DIV_ENABLED 1U
+#define CYBSP_SDIO_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_SDIO_CLK_DIV_NUM 0U
+#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
+#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CSD_CLK_DIV_NUM 4U
+#define CYBSP_SPI_CLK_DIV_ENABLED 1U
+#define CYBSP_SPI_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_SPI_CLK_DIV_NUM 5U
+#define CYBSP_WL_UART_CLK_DIV_ENABLED 1U
+#define CYBSP_WL_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_WL_UART_CLK_DIV_NUM 6U
void init_cycfg_clocks(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h
index c68d4b9ec8..69a805e959 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_dmas.h
@@ -32,15 +32,19 @@
extern "C" {
#endif
+#define cpuss_0_dw0_0_chan_0_ENABLED 1U
#define cpuss_0_dw0_0_chan_0_HW DW0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0
#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
+#define cpuss_0_dw0_0_chan_1_ENABLED 1U
#define cpuss_0_dw0_0_chan_1_HW DW0
#define cpuss_0_dw0_0_chan_1_CHANNEL 1
#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
+#define cpuss_0_dw1_0_chan_1_ENABLED 1U
#define cpuss_0_dw1_0_chan_1_HW DW1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1
#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
+#define cpuss_0_dw1_0_chan_3_ENABLED 1U
#define cpuss_0_dw1_0_chan_3_HW DW1
#define cpuss_0_dw1_0_chan_3_CHANNEL 3
#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c
index eff312bed2..3d665baafd 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.c
@@ -24,8 +24,7 @@
#include "cycfg_peripherals.h"
-#define PWM_INPUT_DISABLED 0x7U
-#define USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \
+#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
@@ -43,7 +42,31 @@ cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
-const cy_stc_scb_uart_config_t BT_UART_config =
+const cy_stc_scb_spi_config_t CYBSP_SPI_config =
+{
+ .spiMode = CY_SCB_SPI_MASTER,
+ .subMode = CY_SCB_SPI_MOTOROLA,
+ .sclkMode = CY_SCB_SPI_CPHA0_CPOL0,
+ .oversample = 16,
+ .rxDataWidth = 8UL,
+ .txDataWidth = 8UL,
+ .enableMsbFirst = true,
+ .enableInputFilter = false,
+ .enableFreeRunSclk = false,
+ .enableMisoLateSample = true,
+ .enableTransferSeperation = false,
+ .ssPolarity = ((CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT0) | \
+ (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT1) | \
+ (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT2) | \
+ (CY_SCB_SPI_ACTIVE_LOW << CY_SCB_SPI_SLAVE_SELECT3)),
+ .enableWakeFromSleep = false,
+ .rxFifoTriggerLevel = 63UL,
+ .rxFifoIntEnableMask = 0UL,
+ .txFifoTriggerLevel = 63UL,
+ .txFifoIntEnableMask = 0UL,
+ .masterSlaveIntEnableMask = 0UL,
+};
+const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@@ -71,7 +94,7 @@ const cy_stc_scb_uart_config_t BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
-const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
+const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
.slaveAddress1 = 8U,
@@ -79,7 +102,7 @@ const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
-const cy_stc_scb_uart_config_t KITPROG_UART_config =
+const cy_stc_scb_uart_config_t CYBSP_WL_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
@@ -107,14 +130,42 @@ const cy_stc_scb_uart_config_t KITPROG_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
-const cy_stc_smif_config_t QSPI_config =
+const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
+{
+ .uartMode = CY_SCB_UART_STANDARD,
+ .enableMutliProcessorMode = false,
+ .smartCardRetryOnNack = false,
+ .irdaInvertRx = false,
+ .irdaEnableLowPowerReceiver = false,
+ .oversample = 8,
+ .enableMsbFirst = false,
+ .dataWidth = 8UL,
+ .parity = CY_SCB_UART_PARITY_NONE,
+ .stopBits = CY_SCB_UART_STOP_BITS_1,
+ .enableInputFilter = false,
+ .breakWidth = 11UL,
+ .dropOnFrameError = false,
+ .dropOnParityError = false,
+ .receiverAddress = 0x0UL,
+ .receiverAddressMask = 0x0UL,
+ .acceptAddrInFifo = false,
+ .enableCts = false,
+ .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rtsRxFifoLevel = 0UL,
+ .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rxFifoTriggerLevel = 63UL,
+ .rxFifoIntEnableMask = 0UL,
+ .txFifoTriggerLevel = 63UL,
+ .txFifoIntEnableMask = 0UL,
+};
+const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
- .deselectDelay = QSPI_DESELECT_DELAY,
+ .deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
-const cy_stc_mcwdt_config_t MCWDT0_config =
+const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
.c1Match = 32768U,
@@ -127,7 +178,7 @@ const cy_stc_mcwdt_config_t MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
-const cy_stc_rtc_config_t RTC_config =
+const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
.min = 0U,
@@ -139,35 +190,7 @@ const cy_stc_rtc_config_t RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
-const cy_stc_tcpwm_pwm_config_t PWM_config =
-{
- .pwmMode = CY_TCPWM_PWM_MODE_PWM,
- .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
- .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
- .deadTimeClocks = 0,
- .runMode = CY_TCPWM_PWM_CONTINUOUS,
- .period0 = 32000,
- .period1 = 32768,
- .enablePeriodSwap = false,
- .compare0 = 16384,
- .compare1 = 16384,
- .enableCompareSwap = false,
- .interruptSources = CY_TCPWM_INT_NONE,
- .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE,
- .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE,
- .killMode = CY_TCPWM_PWM_STOP_ON_KILL,
- .swapInputMode = PWM_INPUT_DISABLED & 0x3U,
- .swapInput = CY_TCPWM_INPUT_0,
- .reloadInputMode = PWM_INPUT_DISABLED & 0x3U,
- .reloadInput = CY_TCPWM_INPUT_0,
- .startInputMode = PWM_INPUT_DISABLED & 0x3U,
- .startInput = CY_TCPWM_INPUT_0,
- .killInputMode = PWM_INPUT_DISABLED & 0x3U,
- .killInput = CY_TCPWM_INPUT_0,
- .countInputMode = PWM_INPUT_DISABLED & 0x3U,
- .countInput = CY_TCPWM_INPUT_1,
-};
-const cy_stc_usbfs_dev_drv_config_t USBUART_config =
+const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
@@ -182,7 +205,7 @@ const cy_stc_usbfs_dev_drv_config_t USBUART_config =
.dmaConfig[6] = NULL,
.dmaConfig[7] = NULL,
.enableLpm = false,
- .intrLevelSel = USBUART_INTR_LVL_SEL,
+ .intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
};
@@ -190,13 +213,15 @@ void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
+ Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 5U);
+
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
- Cy_SysClk_PeriphAssignDivider(PCLK_SCB6_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
+ Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 6U);
- Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM1_CLOCKS1, CY_SYSCLK_DIV_8_BIT, 3U);
+ Cy_SysClk_PeriphAssignDivider(PCLK_SCB6_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h
index 404b85be4a..b0503ad9f6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_peripherals.h
@@ -28,19 +28,19 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_csd.h"
+#include "cy_scb_spi.h"
#include "cy_scb_uart.h"
#include "cy_scb_ezi2c.h"
#include "cy_smif.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
-#include "cy_tcpwm_pwm.h"
-#include "cycfg_routing.h"
#include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus)
extern "C" {
#endif
+#define CYBSP_CapSense_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 100000000u
@@ -74,61 +74,73 @@ extern "C" {
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
-#define CapSense_HW CSD0
-#define CapSense_IRQ csd_interrupt_IRQn
-#define BT_UART_HW SCB2
-#define BT_UART_IRQ scb_2_interrupt_IRQn
-#define CSD_COMM_HW SCB3
-#define CSD_COMM_IRQ scb_3_interrupt_IRQn
-#define KITPROG_UART_HW SCB6
-#define KITPROG_UART_IRQ scb_6_interrupt_IRQn
-#define QSPI_HW SMIF0
-#define QSPI_IRQ smif_interrupt_IRQn
-#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
-#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
-#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
-#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
-#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
-#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
-#define QSPI_DATALINES0_1 (1UL)
-#define QSPI_DATALINES2_3 (1UL)
-#define QSPI_DATALINES4_5 (0UL)
-#define QSPI_DATALINES6_7 (0UL)
-#define QSPI_SS0 (1UL)
-#define QSPI_SS1 (0UL)
-#define QSPI_SS2 (0UL)
-#define QSPI_SS3 (0UL)
-#define QSPI_DESELECT_DELAY 7
-#define MCWDT0_HW MCWDT_STRUCT0
-#define RTC_10_MONTH_OFFSET (28U)
-#define RTC_MONTH_OFFSET (24U)
-#define RTC_10_DAY_OFFSET (20U)
-#define RTC_DAY_OFFSET (16U)
-#define RTC_1000_YEAR_OFFSET (12U)
-#define RTC_100_YEAR_OFFSET (8U)
-#define RTC_10_YEAR_OFFSET (4U)
-#define RTC_YEAR_OFFSET (0U)
-#define PWM_HW TCPWM1
-#define PWM_NUM 1UL
-#define PWM_MASK (1UL << 1)
-#define USBUART_ACTIVE_ENDPOINTS_MASK 7U
-#define USBUART_ENDPOINTS_BUFFER_SIZE 140U
-#define USBUART_ENDPOINTS_ACCESS_TYPE 0U
-#define USBUART_USB_CORE 4U
-#define USBUART_HW USBFS0
-#define USBUART_HI_IRQ usb_interrupt_hi_IRQn
-#define USBUART_MED_IRQ usb_interrupt_med_IRQn
-#define USBUART_LO_IRQ usb_interrupt_lo_IRQn
+#define CYBSP_CapSense_HW CSD0
+#define CYBSP_CapSense_IRQ csd_interrupt_IRQn
+#define CYBSP_SPI_ENABLED 1U
+#define CYBSP_SPI_HW SCB1
+#define CYBSP_SPI_IRQ scb_1_interrupt_IRQn
+#define CYBSP_BT_UART_ENABLED 1U
+#define CYBSP_BT_UART_HW SCB2
+#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
+#define CYBSP_CSD_COMM_ENABLED 1U
+#define CYBSP_CSD_COMM_HW SCB3
+#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
+#define CYBSP_WL_UART_ENABLED 1U
+#define CYBSP_WL_UART_HW SCB5
+#define CYBSP_WL_UART_IRQ scb_5_interrupt_IRQn
+#define CYBSP_DEBUG_UART_ENABLED 1U
+#define CYBSP_DEBUG_UART_HW SCB6
+#define CYBSP_DEBUG_UART_IRQ scb_6_interrupt_IRQn
+#define CYBSP_QSPI_ENABLED 1U
+#define CYBSP_QSPI_HW SMIF0
+#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
+#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
+#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
+#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
+#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
+#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
+#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
+#define CYBSP_QSPI_DATALINES0_1 (1UL)
+#define CYBSP_QSPI_DATALINES2_3 (1UL)
+#define CYBSP_QSPI_DATALINES4_5 (0UL)
+#define CYBSP_QSPI_DATALINES6_7 (0UL)
+#define CYBSP_QSPI_SS0 (1UL)
+#define CYBSP_QSPI_SS1 (0UL)
+#define CYBSP_QSPI_SS2 (0UL)
+#define CYBSP_QSPI_SS3 (0UL)
+#define CYBSP_QSPI_DESELECT_DELAY 7
+#define CYBSP_MCWDT0_ENABLED 1U
+#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
+#define CYBSP_RTC_ENABLED 1U
+#define CYBSP_RTC_10_MONTH_OFFSET (28U)
+#define CYBSP_RTC_MONTH_OFFSET (24U)
+#define CYBSP_RTC_10_DAY_OFFSET (20U)
+#define CYBSP_RTC_DAY_OFFSET (16U)
+#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
+#define CYBSP_RTC_100_YEAR_OFFSET (8U)
+#define CYBSP_RTC_10_YEAR_OFFSET (4U)
+#define CYBSP_RTC_YEAR_OFFSET (0U)
+#define CYBSP_SDIO_ENABLED 1U
+#define CYBSP_USBUART_ENABLED 1U
+#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 7U
+#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 140U
+#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
+#define CYBSP_USBUART_USB_CORE 4U
+#define CYBSP_USBUART_HW USBFS0
+#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
+#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
+#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
extern cy_stc_csd_context_t cy_csd_0_context;
-extern const cy_stc_scb_uart_config_t BT_UART_config;
-extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config;
-extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
-extern const cy_stc_smif_config_t QSPI_config;
-extern const cy_stc_mcwdt_config_t MCWDT0_config;
-extern const cy_stc_rtc_config_t RTC_config;
-extern const cy_stc_tcpwm_pwm_config_t PWM_config;
-extern const cy_stc_usbfs_dev_drv_config_t USBUART_config;
+extern const cy_stc_scb_spi_config_t CYBSP_SPI_config;
+extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
+extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
+extern const cy_stc_scb_uart_config_t CYBSP_WL_UART_config;
+extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
+extern const cy_stc_smif_config_t CYBSP_QSPI_config;
+extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
+extern const cy_stc_rtc_config_t CYBSP_RTC_config;
+extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
void init_cycfg_peripherals(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c
index 2c56839265..3832d774f6 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.c
@@ -24,912 +24,1184 @@
#include "cycfg_pins.h"
-const cy_stc_gpio_pin_config_t WCO_IN_config =
+const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = WCO_IN_HSIOM,
+ .hsiom = CYBSP_WCO_IN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t WCO_OUT_config =
+const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = WCO_OUT_HSIOM,
+ .hsiom = CYBSP_WCO_OUT_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_RED_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_RED_HSIOM,
+ .hsiom = CYBSP_LED_RED_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SW6_config =
+const cy_stc_gpio_pin_config_t CYBSP_SW6_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
- .hsiom = SW6_HSIOM,
+ .hsiom = CYBSP_SW6_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_BLUE_config =
+const cy_stc_gpio_pin_config_t CYBSP_ROW6_SPI_MOSI_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_BLUE_HSIOM,
+ .hsiom = CYBSP_ROW6_SPI_MOSI_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t WL_UART_RX_config =
+const cy_stc_gpio_pin_config_t CYBSP_COL8_SPI_MISO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
- .hsiom = WL_UART_RX_HSIOM,
+ .hsiom = CYBSP_COL8_SPI_MISO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t WL_UART_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_ROW7_SPI_CLK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = WL_UART_TX_HSIOM,
+ .hsiom = CYBSP_ROW7_SPI_CLK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_SS0_config =
+const cy_stc_gpio_pin_config_t CYBSP_COL7_SPI_CS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = QSPI_SS0_HSIOM,
+ .hsiom = CYBSP_COL7_SPI_CS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA3_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA2_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA1_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = QSPI_DATA0_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config =
+const cy_stc_gpio_pin_config_t CYBSP_BAT_MON_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = QSPI_SPI_CLOCK_HSIOM,
+ .hsiom = CYBSP_BAT_MON_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ioss_0_port_12_pin_6_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config =
{
.outVal = 1,
- .driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = ioss_0_port_12_pin_6_HSIOM,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_LED_BLUE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ioss_0_port_12_pin_7_config =
+const cy_stc_gpio_pin_config_t CYBSP_WL_WAKE_config =
{
.outVal = 1,
- .driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = ioss_0_port_12_pin_7_HSIOM,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_WL_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t UART_RX_config =
+const cy_stc_gpio_pin_config_t CYBSP_WL_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
- .hsiom = UART_RX_HSIOM,
+ .hsiom = CYBSP_WL_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t UART_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_WL_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = UART_TX_HSIOM,
+ .hsiom = CYBSP_WL_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED9_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED9_HSIOM,
+ .hsiom = CYBSP_QSPI_SS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config =
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_QSPI_D3_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_QSPI_D2_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_QSPI_D1_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_QSPI_D0_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_QSPI_SCK_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = ioss_0_port_14_pin_0_HSIOM,
+ .hsiom = CYBSP_BT_GPIO4_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO5_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = ioss_0_port_14_pin_1_HSIOM,
+ .hsiom = CYBSP_BT_GPIO5_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_TX_HSIOM,
+ .hsiom = CYBSP_BT_GPIO2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED_GREEN_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO3_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CYBSP_BT_GPIO3_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CYBSP_ECO_IN_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CYBSP_ECO_OUT_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED_GREEN_HSIOM,
+ .hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t LED8_config =
+const cy_stc_gpio_pin_config_t CYBSP_USB_DEV_VBUS_DET_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = CYBSP_USB_DEV_VBUS_DET_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_USB_HOST_EN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = LED8_HSIOM,
+ .hsiom = CYBSP_USB_HOST_EN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT0_config =
+const cy_stc_gpio_pin_config_t CYBSP_USB_INT_L_config =
{
.outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT0_HSIOM,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = CYBSP_USB_INT_L_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT1_config =
+const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
{
.outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT1_HSIOM,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CYBSP_USB_DP_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT2_config =
+const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
{
.outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT2_HSIOM,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CYBSP_USB_DM_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_DAT3_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_DAT3_HSIOM,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CYBSP_CSD_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SDHC0_CMD_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG,
- .hsiom = SDHC0_CMD_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t SDHC0_CLK_config =
+const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = SDHC0_CLK_HSIOM,
+ .hsiom = CYBSP_LED_GREEN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ENABLE_WIFI_config =
+const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_IN_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_WL_SECI_IN_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_WL_FRAM_SYNC_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_WL_FRAM_SYNC_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_WL_PRIORITY_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_WL_PRIORITY_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_OUT_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = CYBSP_WL_SECI_OUT_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_WIFI_SDIO_D0_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_WIFI_SDIO_D1_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_WIFI_SDIO_D2_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_WIFI_SDIO_D3_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = ENABLE_WIFI_HSIOM,
+ .hsiom = CYBSP_WIFI_WL_REG_ON_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_UART_RX_config =
+const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
- .hsiom = BT_UART_RX_HSIOM,
+ .hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_UART_TX_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = BT_UART_TX_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t BT_UART_RTS_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = BT_UART_RTS_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t BT_UART_CTS_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
- .hsiom = BT_UART_CTS_HSIOM,
+ .hsiom = CYBSP_BT_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_POWER_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_BT_UART_TX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_BT_UART_RTS_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = CYBSP_BT_UART_CTS_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_BT_REG_ON_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF,
- .hsiom = BT_POWER_HSIOM,
+ .hsiom = CYBSP_BT_REG_ON_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
- .driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = BT_HOST_WAKE_HSIOM,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = BT_DEVICE_WAKE_HSIOM,
+ .hsiom = CYBSP_BT_DEVICE_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t EZI2C_SCL_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
- .hsiom = EZI2C_SCL_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t EZI2C_SDA_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
- .hsiom = EZI2C_SDA_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-const cy_stc_gpio_pin_config_t SWO_config =
+const cy_stc_gpio_pin_config_t CYBSP_BT_RST_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = SWO_HSIOM,
+ .hsiom = CYBSP_BT_RST_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWDIO_config =
+const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
+ .hsiom = CYBSP_EZI2C_SCL_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
+ .hsiom = CYBSP_EZI2C_SDA_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_SWO_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
- .hsiom = SWDIO_HSIOM,
+ .hsiom = CYBSP_SWDIO_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t SWDCK_config =
+const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLDOWN,
- .hsiom = SWDCK_HSIOM,
+ .hsiom = CYBSP_SWCLK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ioss_0_port_7_pin_0_config =
+const cy_stc_gpio_pin_config_t CYBSP_TRACECLK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = ioss_0_port_7_pin_0_HSIOM,
+ .hsiom = CYBSP_TRACECLK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CINA_config =
+const cy_stc_gpio_pin_config_t CYBSP_CINTA_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CINA_HSIOM,
+ .hsiom = CYBSP_CINTA_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CINB_config =
+const cy_stc_gpio_pin_config_t CYBSP_CINTB_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CINB_HSIOM,
+ .hsiom = CYBSP_CINTB_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CMOD_config =
+const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CMOD_HSIOM,
+ .hsiom = CYBSP_CMOD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_BTN0_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_BTN0_HSIOM,
+ .hsiom = CYBSP_CSD_BTN0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_BTN1_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_BTN1_HSIOM,
+ .hsiom = CYBSP_CSD_BTN1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD0_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD0_HSIOM,
+ .hsiom = CYBSP_CSD_SLD0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD1_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD1_HSIOM,
+ .hsiom = CYBSP_CSD_SLD1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD2_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD2_HSIOM,
+ .hsiom = CYBSP_CSD_SLD2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD3_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD3_HSIOM,
+ .hsiom = CYBSP_CSD_SLD3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t CSD_SLD4_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
- .hsiom = CSD_SLD4_HSIOM,
+ .hsiom = CYBSP_CSD_SLD4_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_0_config =
+const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = ioss_0_port_9_pin_0_HSIOM,
+ .hsiom = CYBSP_TRACEDATA3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_1_config =
+const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = ioss_0_port_9_pin_1_HSIOM,
+ .hsiom = CYBSP_TRACEDATA2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_2_config =
+const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = ioss_0_port_9_pin_2_HSIOM,
+ .hsiom = CYBSP_TRACEDATA1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_3_config =
+const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = ioss_0_port_9_pin_3_HSIOM,
+ .hsiom = CYBSP_TRACEDATA0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
+ .driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
@@ -940,90 +1212,124 @@ const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_3_config =
void init_cycfg_pins(void)
{
- Cy_GPIO_Pin_Init(WCO_IN_PORT, WCO_IN_PIN, &WCO_IN_config);
+ Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
- Cy_GPIO_Pin_Init(WCO_OUT_PORT, WCO_OUT_PIN, &WCO_OUT_config);
+ Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
- Cy_GPIO_Pin_Init(LED_RED_PORT, LED_RED_PIN, &LED_RED_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
- Cy_GPIO_Pin_Init(SW6_PORT, SW6_PIN, &SW6_config);
+ Cy_GPIO_Pin_Init(CYBSP_SW6_PORT, CYBSP_SW6_PIN, &CYBSP_SW6_config);
- Cy_GPIO_Pin_Init(LED_BLUE_PORT, LED_BLUE_PIN, &LED_BLUE_config);
+ Cy_GPIO_Pin_Init(CYBSP_ROW6_SPI_MOSI_PORT, CYBSP_ROW6_SPI_MOSI_PIN, &CYBSP_ROW6_SPI_MOSI_config);
- Cy_GPIO_Pin_Init(WL_UART_RX_PORT, WL_UART_RX_PIN, &WL_UART_RX_config);
+ Cy_GPIO_Pin_Init(CYBSP_COL8_SPI_MISO_PORT, CYBSP_COL8_SPI_MISO_PIN, &CYBSP_COL8_SPI_MISO_config);
- Cy_GPIO_Pin_Init(WL_UART_TX_PORT, WL_UART_TX_PIN, &WL_UART_TX_config);
+ Cy_GPIO_Pin_Init(CYBSP_ROW7_SPI_CLK_PORT, CYBSP_ROW7_SPI_CLK_PIN, &CYBSP_ROW7_SPI_CLK_config);
- Cy_GPIO_Pin_Init(QSPI_SS0_PORT, QSPI_SS0_PIN, &QSPI_SS0_config);
+ Cy_GPIO_Pin_Init(CYBSP_COL7_SPI_CS_PORT, CYBSP_COL7_SPI_CS_PIN, &CYBSP_COL7_SPI_CS_config);
- Cy_GPIO_Pin_Init(QSPI_DATA3_PORT, QSPI_DATA3_PIN, &QSPI_DATA3_config);
+ Cy_GPIO_Pin_Init(CYBSP_BAT_MON_PORT, CYBSP_BAT_MON_PIN, &CYBSP_BAT_MON_config);
- Cy_GPIO_Pin_Init(QSPI_DATA2_PORT, QSPI_DATA2_PIN, &QSPI_DATA2_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
- Cy_GPIO_Pin_Init(QSPI_DATA1_PORT, QSPI_DATA1_PIN, &QSPI_DATA1_config);
+ Cy_GPIO_Pin_Init(CYBSP_WL_WAKE_PORT, CYBSP_WL_WAKE_PIN, &CYBSP_WL_WAKE_config);
- Cy_GPIO_Pin_Init(QSPI_DATA0_PORT, QSPI_DATA0_PIN, &QSPI_DATA0_config);
+ Cy_GPIO_Pin_Init(CYBSP_WL_UART_RX_PORT, CYBSP_WL_UART_RX_PIN, &CYBSP_WL_UART_RX_config);
- Cy_GPIO_Pin_Init(QSPI_SPI_CLOCK_PORT, QSPI_SPI_CLOCK_PIN, &QSPI_SPI_CLOCK_config);
+ Cy_GPIO_Pin_Init(CYBSP_WL_UART_TX_PORT, CYBSP_WL_UART_TX_PIN, &CYBSP_WL_UART_TX_config);
- Cy_GPIO_Pin_Init(ioss_0_port_12_pin_6_PORT, ioss_0_port_12_pin_6_PIN, &ioss_0_port_12_pin_6_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
- Cy_GPIO_Pin_Init(ioss_0_port_12_pin_7_PORT, ioss_0_port_12_pin_7_PIN, &ioss_0_port_12_pin_7_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
- Cy_GPIO_Pin_Init(UART_RX_PORT, UART_RX_PIN, &UART_RX_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
- Cy_GPIO_Pin_Init(UART_TX_PORT, UART_TX_PIN, &UART_TX_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
- Cy_GPIO_Pin_Init(LED9_PORT, LED9_PIN, &LED9_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
- Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config);
+ Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
- Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_GPIO4_PORT, CYBSP_BT_GPIO4_PIN, &CYBSP_BT_GPIO4_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_BT_GPIO5_PORT, CYBSP_BT_GPIO5_PIN, &CYBSP_BT_GPIO5_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_BT_GPIO2_PORT, CYBSP_BT_GPIO2_PIN, &CYBSP_BT_GPIO2_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_BT_GPIO3_PORT, CYBSP_BT_GPIO3_PIN, &CYBSP_BT_GPIO3_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_USB_DEV_VBUS_DET_PORT, CYBSP_USB_DEV_VBUS_DET_PIN, &CYBSP_USB_DEV_VBUS_DET_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_USB_HOST_EN_PORT, CYBSP_USB_HOST_EN_PIN, &CYBSP_USB_HOST_EN_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_USB_INT_L_PORT, CYBSP_USB_INT_L_PIN, &CYBSP_USB_INT_L_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
- Cy_GPIO_Pin_Init(LED_GREEN_PORT, LED_GREEN_PIN, &LED_GREEN_config);
+ Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
- Cy_GPIO_Pin_Init(LED8_PORT, LED8_PIN, &LED8_config);
+ Cy_GPIO_Pin_Init(CYBSP_WL_SECI_IN_PORT, CYBSP_WL_SECI_IN_PIN, &CYBSP_WL_SECI_IN_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT0_PORT, SDHC0_DAT0_PIN, &SDHC0_DAT0_config);
+ Cy_GPIO_Pin_Init(CYBSP_WL_FRAM_SYNC_PORT, CYBSP_WL_FRAM_SYNC_PIN, &CYBSP_WL_FRAM_SYNC_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT1_PORT, SDHC0_DAT1_PIN, &SDHC0_DAT1_config);
+ Cy_GPIO_Pin_Init(CYBSP_WL_PRIORITY_PORT, CYBSP_WL_PRIORITY_PIN, &CYBSP_WL_PRIORITY_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT2_PORT, SDHC0_DAT2_PIN, &SDHC0_DAT2_config);
+ Cy_GPIO_Pin_Init(CYBSP_WL_SECI_OUT_PORT, CYBSP_WL_SECI_OUT_PIN, &CYBSP_WL_SECI_OUT_config);
- Cy_GPIO_Pin_Init(SDHC0_DAT3_PORT, SDHC0_DAT3_PIN, &SDHC0_DAT3_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D0_PORT, CYBSP_WIFI_SDIO_D0_PIN, &CYBSP_WIFI_SDIO_D0_config);
- Cy_GPIO_Pin_Init(SDHC0_CMD_PORT, SDHC0_CMD_PIN, &SDHC0_CMD_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D1_PORT, CYBSP_WIFI_SDIO_D1_PIN, &CYBSP_WIFI_SDIO_D1_config);
- Cy_GPIO_Pin_Init(SDHC0_CLK_PORT, SDHC0_CLK_PIN, &SDHC0_CLK_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D2_PORT, CYBSP_WIFI_SDIO_D2_PIN, &CYBSP_WIFI_SDIO_D2_config);
- Cy_GPIO_Pin_Init(ENABLE_WIFI_PORT, ENABLE_WIFI_PIN, &ENABLE_WIFI_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D3_PORT, CYBSP_WIFI_SDIO_D3_PIN, &CYBSP_WIFI_SDIO_D3_config);
- Cy_GPIO_Pin_Init(BT_UART_RX_PORT, BT_UART_RX_PIN, &BT_UART_RX_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config);
- Cy_GPIO_Pin_Init(BT_UART_TX_PORT, BT_UART_TX_PIN, &BT_UART_TX_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
- Cy_GPIO_Pin_Init(BT_UART_RTS_PORT, BT_UART_RTS_PIN, &BT_UART_RTS_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_WL_REG_ON_PORT, CYBSP_WIFI_WL_REG_ON_PIN, &CYBSP_WIFI_WL_REG_ON_config);
- Cy_GPIO_Pin_Init(BT_UART_CTS_PORT, BT_UART_CTS_PIN, &BT_UART_CTS_config);
+ Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
- Cy_GPIO_Pin_Init(BT_POWER_PORT, BT_POWER_PIN, &BT_POWER_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
- Cy_GPIO_Pin_Init(BT_HOST_WAKE_PORT, BT_HOST_WAKE_PIN, &BT_HOST_WAKE_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
- Cy_GPIO_Pin_Init(BT_DEVICE_WAKE_PORT, BT_DEVICE_WAKE_PIN, &BT_DEVICE_WAKE_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
- Cy_GPIO_Pin_Init(EZI2C_SCL_PORT, EZI2C_SCL_PIN, &EZI2C_SCL_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
- Cy_GPIO_Pin_Init(EZI2C_SDA_PORT, EZI2C_SDA_PIN, &EZI2C_SDA_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_REG_ON_PORT, CYBSP_BT_REG_ON_PIN, &CYBSP_BT_REG_ON_config);
- Cy_GPIO_Pin_Init(SWO_PORT, SWO_PIN, &SWO_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
- Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
- Cy_GPIO_Pin_Init(SWDCK_PORT, SWDCK_PIN, &SWDCK_config);
+ Cy_GPIO_Pin_Init(CYBSP_BT_RST_PORT, CYBSP_BT_RST_PIN, &CYBSP_BT_RST_config);
- Cy_GPIO_Pin_Init(ioss_0_port_7_pin_0_PORT, ioss_0_port_7_pin_0_PIN, &ioss_0_port_7_pin_0_config);
+ Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_SWCLK_PORT, CYBSP_SWCLK_PIN, &CYBSP_SWCLK_config);
+
+ Cy_GPIO_Pin_Init(CYBSP_TRACECLK_PORT, CYBSP_TRACECLK_PIN, &CYBSP_TRACECLK_config);
@@ -1035,11 +1341,11 @@ void init_cycfg_pins(void)
- Cy_GPIO_Pin_Init(ioss_0_port_9_pin_0_PORT, ioss_0_port_9_pin_0_PIN, &ioss_0_port_9_pin_0_config);
+ Cy_GPIO_Pin_Init(CYBSP_TRACEDATA3_PORT, CYBSP_TRACEDATA3_PIN, &CYBSP_TRACEDATA3_config);
- Cy_GPIO_Pin_Init(ioss_0_port_9_pin_1_PORT, ioss_0_port_9_pin_1_PIN, &ioss_0_port_9_pin_1_config);
+ Cy_GPIO_Pin_Init(CYBSP_TRACEDATA2_PORT, CYBSP_TRACEDATA2_PIN, &CYBSP_TRACEDATA2_config);
- Cy_GPIO_Pin_Init(ioss_0_port_9_pin_2_PORT, ioss_0_port_9_pin_2_PIN, &ioss_0_port_9_pin_2_config);
+ Cy_GPIO_Pin_Init(CYBSP_TRACEDATA1_PORT, CYBSP_TRACEDATA1_PIN, &CYBSP_TRACEDATA1_config);
- Cy_GPIO_Pin_Init(ioss_0_port_9_pin_3_PORT, ioss_0_port_9_pin_3_PIN, &ioss_0_port_9_pin_3_config);
+ Cy_GPIO_Pin_Init(CYBSP_TRACEDATA0_PORT, CYBSP_TRACEDATA0_PIN, &CYBSP_TRACEDATA0_config);
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h
index fc67989d9d..a627cb71a5 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_pins.h
@@ -33,625 +33,895 @@
extern "C" {
#endif
-#define WCO_IN_PORT GPIO_PRT0
-#define WCO_IN_PIN 0U
-#define WCO_IN_NUM 0U
-#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define WCO_IN_INIT_DRIVESTATE 1
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_0_HSIOM
#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#define WCO_OUT_PORT GPIO_PRT0
-#define WCO_OUT_PIN 1U
-#define WCO_OUT_NUM 1U
-#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define WCO_OUT_INIT_DRIVESTATE 1
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_1_HSIOM
#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#define LED_RED_PORT GPIO_PRT0
-#define LED_RED_PIN 3U
-#define LED_RED_NUM 3U
-#define LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_RED_INIT_DRIVESTATE 1
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_LED_RED_ENABLED 1U
+#define CYBSP_LED_RED_PORT GPIO_PRT0
+#define CYBSP_LED_RED_PIN 3U
+#define CYBSP_LED_RED_NUM 3U
+#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED_RED_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_3_HSIOM
#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
-#define LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
-#define SW6_PORT GPIO_PRT0
-#define SW6_PIN 4U
-#define SW6_NUM 4U
-#define SW6_DRIVEMODE CY_GPIO_DM_PULLUP
-#define SW6_INIT_DRIVESTATE 1
+#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
+#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_SW6_ENABLED 1U
+#define CYBSP_SW6_PORT GPIO_PRT0
+#define CYBSP_SW6_PIN 4U
+#define CYBSP_SW6_NUM 4U
+#define CYBSP_SW6_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SW6_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SW6_HSIOM ioss_0_port_0_pin_4_HSIOM
-#define SW6_IRQ ioss_interrupts_gpio_0_IRQn
-#define LED_BLUE_PORT GPIO_PRT10
-#define LED_BLUE_PIN 6U
-#define LED_BLUE_NUM 6U
-#define LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_BLUE_INIT_DRIVESTATE 1
+#define CYBSP_SW6_HSIOM ioss_0_port_0_pin_4_HSIOM
+#define CYBSP_SW6_IRQ ioss_interrupts_gpio_0_IRQn
+#define CYBSP_ROW6_SPI_MOSI_ENABLED 1U
+#define CYBSP_ROW6_SPI_MOSI_PORT GPIO_PRT10
+#define CYBSP_ROW6_SPI_MOSI_PIN 0U
+#define CYBSP_ROW6_SPI_MOSI_NUM 0U
+#define CYBSP_ROW6_SPI_MOSI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_ROW6_SPI_MOSI_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_0_HSIOM
+ #define ioss_0_port_10_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_ROW6_SPI_MOSI_HSIOM ioss_0_port_10_pin_0_HSIOM
+#define CYBSP_ROW6_SPI_MOSI_IRQ ioss_interrupts_gpio_10_IRQn
+#define CYBSP_COL8_SPI_MISO_ENABLED 1U
+#define CYBSP_COL8_SPI_MISO_PORT GPIO_PRT10
+#define CYBSP_COL8_SPI_MISO_PIN 1U
+#define CYBSP_COL8_SPI_MISO_NUM 1U
+#define CYBSP_COL8_SPI_MISO_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_COL8_SPI_MISO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_1_HSIOM
+ #define ioss_0_port_10_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_COL8_SPI_MISO_HSIOM ioss_0_port_10_pin_1_HSIOM
+#define CYBSP_COL8_SPI_MISO_IRQ ioss_interrupts_gpio_10_IRQn
+#define CYBSP_ROW7_SPI_CLK_ENABLED 1U
+#define CYBSP_ROW7_SPI_CLK_PORT GPIO_PRT10
+#define CYBSP_ROW7_SPI_CLK_PIN 2U
+#define CYBSP_ROW7_SPI_CLK_NUM 2U
+#define CYBSP_ROW7_SPI_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_ROW7_SPI_CLK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_2_HSIOM
+ #define ioss_0_port_10_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_ROW7_SPI_CLK_HSIOM ioss_0_port_10_pin_2_HSIOM
+#define CYBSP_ROW7_SPI_CLK_IRQ ioss_interrupts_gpio_10_IRQn
+#define CYBSP_COL7_SPI_CS_ENABLED 1U
+#define CYBSP_COL7_SPI_CS_PORT GPIO_PRT10
+#define CYBSP_COL7_SPI_CS_PIN 3U
+#define CYBSP_COL7_SPI_CS_NUM 3U
+#define CYBSP_COL7_SPI_CS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_COL7_SPI_CS_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_3_HSIOM
+ #define ioss_0_port_10_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_COL7_SPI_CS_HSIOM ioss_0_port_10_pin_3_HSIOM
+#define CYBSP_COL7_SPI_CS_IRQ ioss_interrupts_gpio_10_IRQn
+#define CYBSP_BAT_MON_ENABLED 1U
+#define CYBSP_BAT_MON_PORT GPIO_PRT10
+#define CYBSP_BAT_MON_PIN 4U
+#define CYBSP_BAT_MON_NUM 4U
+#define CYBSP_BAT_MON_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BAT_MON_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_4_HSIOM
+ #define ioss_0_port_10_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BAT_MON_HSIOM ioss_0_port_10_pin_4_HSIOM
+#define CYBSP_BAT_MON_IRQ ioss_interrupts_gpio_10_IRQn
+#define CYBSP_LED_BLUE_ENABLED 1U
+#define CYBSP_LED_BLUE_PORT GPIO_PRT10
+#define CYBSP_LED_BLUE_PIN 6U
+#define CYBSP_LED_BLUE_NUM 6U
+#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
#ifndef ioss_0_port_10_pin_6_HSIOM
#define ioss_0_port_10_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED_BLUE_HSIOM ioss_0_port_10_pin_6_HSIOM
-#define LED_BLUE_IRQ ioss_interrupts_gpio_10_IRQn
-#define WL_UART_RX_PORT GPIO_PRT11
-#define WL_UART_RX_PIN 0U
-#define WL_UART_RX_NUM 0U
-#define WL_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define WL_UART_RX_INIT_DRIVESTATE 1
+#define CYBSP_LED_BLUE_HSIOM ioss_0_port_10_pin_6_HSIOM
+#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_10_IRQn
+#define CYBSP_WL_WAKE_ENABLED 1U
+#define CYBSP_WL_WAKE_PORT GPIO_PRT10
+#define CYBSP_WL_WAKE_PIN 7U
+#define CYBSP_WL_WAKE_NUM 7U
+#define CYBSP_WL_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WL_WAKE_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_10_pin_7_HSIOM
+ #define ioss_0_port_10_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_WAKE_HSIOM ioss_0_port_10_pin_7_HSIOM
+#define CYBSP_WL_WAKE_IRQ ioss_interrupts_gpio_10_IRQn
+#define CYBSP_WL_UART_RX_ENABLED 1U
+#define CYBSP_WL_UART_RX_PORT GPIO_PRT11
+#define CYBSP_WL_UART_RX_PIN 0U
+#define CYBSP_WL_UART_RX_NUM 0U
+#define CYBSP_WL_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_WL_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_0_HSIOM
#define ioss_0_port_11_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define WL_UART_RX_HSIOM ioss_0_port_11_pin_0_HSIOM
-#define WL_UART_RX_IRQ ioss_interrupts_gpio_11_IRQn
-#define WL_UART_TX_PORT GPIO_PRT11
-#define WL_UART_TX_PIN 1U
-#define WL_UART_TX_NUM 1U
-#define WL_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define WL_UART_TX_INIT_DRIVESTATE 1
+#define CYBSP_WL_UART_RX_HSIOM ioss_0_port_11_pin_0_HSIOM
+#define CYBSP_WL_UART_RX_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_WL_UART_TX_ENABLED 1U
+#define CYBSP_WL_UART_TX_PORT GPIO_PRT11
+#define CYBSP_WL_UART_TX_PIN 1U
+#define CYBSP_WL_UART_TX_NUM 1U
+#define CYBSP_WL_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WL_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_1_HSIOM
#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define WL_UART_TX_HSIOM ioss_0_port_11_pin_1_HSIOM
-#define WL_UART_TX_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_SS0_PORT GPIO_PRT11
-#define QSPI_SS0_PIN 2U
-#define QSPI_SS0_NUM 2U
-#define QSPI_SS0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define QSPI_SS0_INIT_DRIVESTATE 1
+#define CYBSP_WL_UART_TX_HSIOM ioss_0_port_11_pin_1_HSIOM
+#define CYBSP_WL_UART_TX_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_SS_ENABLED 1U
+#define CYBSP_QSPI_SS_PORT GPIO_PRT11
+#define CYBSP_QSPI_SS_PIN 2U
+#define CYBSP_QSPI_SS_NUM 2U
+#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_2_HSIOM
#define ioss_0_port_11_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_SS0_HSIOM ioss_0_port_11_pin_2_HSIOM
-#define QSPI_SS0_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA3_PORT GPIO_PRT11
-#define QSPI_DATA3_PIN 3U
-#define QSPI_DATA3_NUM 3U
-#define QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA3_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
+#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D3_ENABLED 1U
+#define CYBSP_QSPI_D3_PORT GPIO_PRT11
+#define CYBSP_QSPI_D3_PIN 3U
+#define CYBSP_QSPI_D3_NUM 3U
+#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_3_HSIOM
#define ioss_0_port_11_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
-#define QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA2_PORT GPIO_PRT11
-#define QSPI_DATA2_PIN 4U
-#define QSPI_DATA2_NUM 4U
-#define QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA2_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
+#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D2_ENABLED 1U
+#define CYBSP_QSPI_D2_PORT GPIO_PRT11
+#define CYBSP_QSPI_D2_PIN 4U
+#define CYBSP_QSPI_D2_NUM 4U
+#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_4_HSIOM
#define ioss_0_port_11_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
-#define QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA1_PORT GPIO_PRT11
-#define QSPI_DATA1_PIN 5U
-#define QSPI_DATA1_NUM 5U
-#define QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA1_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
+#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D1_ENABLED 1U
+#define CYBSP_QSPI_D1_PORT GPIO_PRT11
+#define CYBSP_QSPI_D1_PIN 5U
+#define CYBSP_QSPI_D1_NUM 5U
+#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_5_HSIOM
#define ioss_0_port_11_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
-#define QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_DATA0_PORT GPIO_PRT11
-#define QSPI_DATA0_PIN 6U
-#define QSPI_DATA0_NUM 6U
-#define QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
-#define QSPI_DATA0_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
+#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_D0_ENABLED 1U
+#define CYBSP_QSPI_D0_PORT GPIO_PRT11
+#define CYBSP_QSPI_D0_PIN 6U
+#define CYBSP_QSPI_D0_NUM 6U
+#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_QSPI_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_6_HSIOM
#define ioss_0_port_11_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
-#define QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
-#define QSPI_SPI_CLOCK_PORT GPIO_PRT11
-#define QSPI_SPI_CLOCK_PIN 7U
-#define QSPI_SPI_CLOCK_NUM 7U
-#define QSPI_SPI_CLOCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define QSPI_SPI_CLOCK_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
+#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_QSPI_SCK_ENABLED 1U
+#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
+#define CYBSP_QSPI_SCK_PIN 7U
+#define CYBSP_QSPI_SCK_NUM 7U
+#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_QSPI_SCK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_7_HSIOM
#define ioss_0_port_11_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define QSPI_SPI_CLOCK_HSIOM ioss_0_port_11_pin_7_HSIOM
-#define QSPI_SPI_CLOCK_IRQ ioss_interrupts_gpio_11_IRQn
-#define ioss_0_port_12_pin_6_PORT GPIO_PRT12
-#define ioss_0_port_12_pin_6_PIN 6U
-#define ioss_0_port_12_pin_6_NUM 6U
-#define ioss_0_port_12_pin_6_DRIVEMODE CY_GPIO_DM_ANALOG
-#define ioss_0_port_12_pin_6_INIT_DRIVESTATE 1
+#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
+#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
+#define CYBSP_BT_GPIO4_ENABLED 1U
+#define CYBSP_BT_GPIO4_PORT GPIO_PRT12
+#define CYBSP_BT_GPIO4_PIN 0U
+#define CYBSP_BT_GPIO4_NUM 0U
+#define CYBSP_BT_GPIO4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_GPIO4_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_12_pin_0_HSIOM
+ #define ioss_0_port_12_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_GPIO4_HSIOM ioss_0_port_12_pin_0_HSIOM
+#define CYBSP_BT_GPIO4_IRQ ioss_interrupts_gpio_12_IRQn
+#define CYBSP_BT_GPIO5_ENABLED 1U
+#define CYBSP_BT_GPIO5_PORT GPIO_PRT12
+#define CYBSP_BT_GPIO5_PIN 1U
+#define CYBSP_BT_GPIO5_NUM 1U
+#define CYBSP_BT_GPIO5_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_GPIO5_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_12_pin_1_HSIOM
+ #define ioss_0_port_12_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_GPIO5_HSIOM ioss_0_port_12_pin_1_HSIOM
+#define CYBSP_BT_GPIO5_IRQ ioss_interrupts_gpio_12_IRQn
+#define CYBSP_BT_GPIO2_ENABLED 1U
+#define CYBSP_BT_GPIO2_PORT GPIO_PRT12
+#define CYBSP_BT_GPIO2_PIN 2U
+#define CYBSP_BT_GPIO2_NUM 2U
+#define CYBSP_BT_GPIO2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_GPIO2_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_12_pin_2_HSIOM
+ #define ioss_0_port_12_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_GPIO2_HSIOM ioss_0_port_12_pin_2_HSIOM
+#define CYBSP_BT_GPIO2_IRQ ioss_interrupts_gpio_12_IRQn
+#define CYBSP_BT_GPIO3_ENABLED 1U
+#define CYBSP_BT_GPIO3_PORT GPIO_PRT12
+#define CYBSP_BT_GPIO3_PIN 3U
+#define CYBSP_BT_GPIO3_NUM 3U
+#define CYBSP_BT_GPIO3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_BT_GPIO3_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_12_pin_3_HSIOM
+ #define ioss_0_port_12_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_GPIO3_HSIOM ioss_0_port_12_pin_3_HSIOM
+#define CYBSP_BT_GPIO3_IRQ ioss_interrupts_gpio_12_IRQn
+#define CYBSP_ECO_IN_ENABLED 1U
+#define CYBSP_ECO_IN_PORT GPIO_PRT12
+#define CYBSP_ECO_IN_PIN 6U
+#define CYBSP_ECO_IN_NUM 6U
+#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_ECO_IN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_12_pin_6_HSIOM
#define ioss_0_port_12_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define ioss_0_port_12_pin_6_IRQ ioss_interrupts_gpio_12_IRQn
-#define ioss_0_port_12_pin_7_PORT GPIO_PRT12
-#define ioss_0_port_12_pin_7_PIN 7U
-#define ioss_0_port_12_pin_7_NUM 7U
-#define ioss_0_port_12_pin_7_DRIVEMODE CY_GPIO_DM_ANALOG
-#define ioss_0_port_12_pin_7_INIT_DRIVESTATE 1
+#define CYBSP_ECO_IN_HSIOM ioss_0_port_12_pin_6_HSIOM
+#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_12_IRQn
+#define CYBSP_ECO_OUT_ENABLED 1U
+#define CYBSP_ECO_OUT_PORT GPIO_PRT12
+#define CYBSP_ECO_OUT_PIN 7U
+#define CYBSP_ECO_OUT_NUM 7U
+#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_12_pin_7_HSIOM
#define ioss_0_port_12_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define ioss_0_port_12_pin_7_IRQ ioss_interrupts_gpio_12_IRQn
-#define UART_RX_PORT GPIO_PRT13
-#define UART_RX_PIN 0U
-#define UART_RX_NUM 0U
-#define UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define UART_RX_INIT_DRIVESTATE 1
+#define CYBSP_ECO_OUT_HSIOM ioss_0_port_12_pin_7_HSIOM
+#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_12_IRQn
+#define CYBSP_DEBUG_UART_RX_ENABLED 1U
+#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT13
+#define CYBSP_DEBUG_UART_RX_PIN 0U
+#define CYBSP_DEBUG_UART_RX_NUM 0U
+#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_0_HSIOM
#define ioss_0_port_13_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define UART_RX_HSIOM ioss_0_port_13_pin_0_HSIOM
-#define UART_RX_IRQ ioss_interrupts_gpio_13_IRQn
-#define UART_TX_PORT GPIO_PRT13
-#define UART_TX_PIN 1U
-#define UART_TX_NUM 1U
-#define UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define UART_TX_INIT_DRIVESTATE 1
+#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_13_pin_0_HSIOM
+#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_13_IRQn
+#define CYBSP_DEBUG_UART_TX_ENABLED 1U
+#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT13
+#define CYBSP_DEBUG_UART_TX_PIN 1U
+#define CYBSP_DEBUG_UART_TX_NUM 1U
+#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_1_HSIOM
#define ioss_0_port_13_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define UART_TX_HSIOM ioss_0_port_13_pin_1_HSIOM
-#define UART_TX_IRQ ioss_interrupts_gpio_13_IRQn
-#define LED9_PORT GPIO_PRT13
-#define LED9_PIN 7U
-#define LED9_NUM 7U
-#define LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED9_INIT_DRIVESTATE 1
+#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_13_pin_1_HSIOM
+#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_13_IRQn
+#define CYBSP_USB_DEV_VBUS_DET_ENABLED 1U
+#define CYBSP_USB_DEV_VBUS_DET_PORT GPIO_PRT13
+#define CYBSP_USB_DEV_VBUS_DET_PIN 4U
+#define CYBSP_USB_DEV_VBUS_DET_NUM 4U
+#define CYBSP_USB_DEV_VBUS_DET_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_USB_DEV_VBUS_DET_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_13_pin_4_HSIOM
+ #define ioss_0_port_13_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_DEV_VBUS_DET_HSIOM ioss_0_port_13_pin_4_HSIOM
+#define CYBSP_USB_DEV_VBUS_DET_IRQ ioss_interrupts_gpio_13_IRQn
+#define CYBSP_USB_HOST_EN_ENABLED 1U
+#define CYBSP_USB_HOST_EN_PORT GPIO_PRT13
+#define CYBSP_USB_HOST_EN_PIN 5U
+#define CYBSP_USB_HOST_EN_NUM 5U
+#define CYBSP_USB_HOST_EN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_USB_HOST_EN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_13_pin_5_HSIOM
+ #define ioss_0_port_13_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_USB_HOST_EN_HSIOM ioss_0_port_13_pin_5_HSIOM
+#define CYBSP_USB_HOST_EN_IRQ ioss_interrupts_gpio_13_IRQn
+#define CYBSP_USB_INT_L_ENABLED 1U
+#define CYBSP_USB_INT_L_PORT GPIO_PRT13
+#define CYBSP_USB_INT_L_PIN 7U
+#define CYBSP_USB_INT_L_NUM 7U
+#define CYBSP_USB_INT_L_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_USB_INT_L_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_7_HSIOM
#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
-#define LED9_IRQ ioss_interrupts_gpio_13_IRQn
-#define ioss_0_port_14_pin_0_PORT GPIO_PRT14
-#define ioss_0_port_14_pin_0_PIN 0U
-#define ioss_0_port_14_pin_0_NUM 0U
-#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1
+#define CYBSP_USB_INT_L_HSIOM ioss_0_port_13_pin_7_HSIOM
+#define CYBSP_USB_INT_L_IRQ ioss_interrupts_gpio_13_IRQn
+#define CYBSP_USB_DP_ENABLED 1U
+#define CYBSP_USB_DP_PORT GPIO_PRT14
+#define CYBSP_USB_DP_PIN 0U
+#define CYBSP_USB_DP_NUM 0U
+#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_USB_DP_INIT_DRIVESTATE 1
#ifndef ioss_0_port_14_pin_0_HSIOM
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn
-#define ioss_0_port_14_pin_1_PORT GPIO_PRT14
-#define ioss_0_port_14_pin_1_PIN 1U
-#define ioss_0_port_14_pin_1_NUM 1U
-#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1
+#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
+#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
+#define CYBSP_USB_DM_ENABLED 1U
+#define CYBSP_USB_DM_PORT GPIO_PRT14
+#define CYBSP_USB_DM_PIN 1U
+#define CYBSP_USB_DM_NUM 1U
+#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_USB_DM_INIT_DRIVESTATE 1
#ifndef ioss_0_port_14_pin_1_HSIOM
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn
-#define CSD_TX_PORT GPIO_PRT1
-#define CSD_TX_PIN 0U
-#define CSD_TX_NUM 0U
-#define CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_TX_INIT_DRIVESTATE 1
+#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
+#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
+#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_0_HSIOM
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
-#define LED_GREEN_PORT GPIO_PRT1
-#define LED_GREEN_PIN 1U
-#define LED_GREEN_NUM 1U
-#define LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_GREEN_INIT_DRIVESTATE 1
+#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_LED_GREEN_ENABLED 1U
+#define CYBSP_LED_GREEN_PORT GPIO_PRT1
+#define CYBSP_LED_GREEN_PIN 1U
+#define CYBSP_LED_GREEN_NUM 1U
+#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_1_HSIOM
#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
-#define LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
-#define LED8_PORT GPIO_PRT1
-#define LED8_PIN 5U
-#define LED8_NUM 5U
-#define LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED8_INIT_DRIVESTATE 1
+#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
+#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_WL_SECI_IN_ENABLED 1U
+#define CYBSP_WL_SECI_IN_PORT GPIO_PRT1
+#define CYBSP_WL_SECI_IN_PIN 2U
+#define CYBSP_WL_SECI_IN_NUM 2U
+#define CYBSP_WL_SECI_IN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WL_SECI_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_2_HSIOM
+ #define ioss_0_port_1_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_SECI_IN_HSIOM ioss_0_port_1_pin_2_HSIOM
+#define CYBSP_WL_SECI_IN_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_WL_FRAM_SYNC_ENABLED 1U
+#define CYBSP_WL_FRAM_SYNC_PORT GPIO_PRT1
+#define CYBSP_WL_FRAM_SYNC_PIN 3U
+#define CYBSP_WL_FRAM_SYNC_NUM 3U
+#define CYBSP_WL_FRAM_SYNC_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WL_FRAM_SYNC_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_3_HSIOM
+ #define ioss_0_port_1_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_FRAM_SYNC_HSIOM ioss_0_port_1_pin_3_HSIOM
+#define CYBSP_WL_FRAM_SYNC_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_WL_PRIORITY_ENABLED 1U
+#define CYBSP_WL_PRIORITY_PORT GPIO_PRT1
+#define CYBSP_WL_PRIORITY_PIN 4U
+#define CYBSP_WL_PRIORITY_NUM 4U
+#define CYBSP_WL_PRIORITY_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WL_PRIORITY_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_1_pin_4_HSIOM
+ #define ioss_0_port_1_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WL_PRIORITY_HSIOM ioss_0_port_1_pin_4_HSIOM
+#define CYBSP_WL_PRIORITY_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_WL_SECI_OUT_ENABLED 1U
+#define CYBSP_WL_SECI_OUT_PORT GPIO_PRT1
+#define CYBSP_WL_SECI_OUT_PIN 5U
+#define CYBSP_WL_SECI_OUT_NUM 5U
+#define CYBSP_WL_SECI_OUT_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_WL_SECI_OUT_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_5_HSIOM
#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
-#define LED8_IRQ ioss_interrupts_gpio_1_IRQn
-#define SDHC0_DAT0_PORT GPIO_PRT2
-#define SDHC0_DAT0_PIN 0U
-#define SDHC0_DAT0_NUM 0U
-#define SDHC0_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT0_INIT_DRIVESTATE 1
+#define CYBSP_WL_SECI_OUT_HSIOM ioss_0_port_1_pin_5_HSIOM
+#define CYBSP_WL_SECI_OUT_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_WIFI_SDIO_D0_ENABLED 1U
+#define CYBSP_WIFI_SDIO_D0_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_D0_PIN 0U
+#define CYBSP_WIFI_SDIO_D0_NUM 0U
+#define CYBSP_WIFI_SDIO_D0_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_D0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_0_HSIOM
#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
-#define SDHC0_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_DAT1_PORT GPIO_PRT2
-#define SDHC0_DAT1_PIN 1U
-#define SDHC0_DAT1_NUM 1U
-#define SDHC0_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT1_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_D0_HSIOM ioss_0_port_2_pin_0_HSIOM
+#define CYBSP_WIFI_SDIO_D0_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_D1_ENABLED 1U
+#define CYBSP_WIFI_SDIO_D1_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_D1_PIN 1U
+#define CYBSP_WIFI_SDIO_D1_NUM 1U
+#define CYBSP_WIFI_SDIO_D1_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_D1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_1_HSIOM
#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
-#define SDHC0_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_DAT2_PORT GPIO_PRT2
-#define SDHC0_DAT2_PIN 2U
-#define SDHC0_DAT2_NUM 2U
-#define SDHC0_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT2_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_D1_HSIOM ioss_0_port_2_pin_1_HSIOM
+#define CYBSP_WIFI_SDIO_D1_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_D2_ENABLED 1U
+#define CYBSP_WIFI_SDIO_D2_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_D2_PIN 2U
+#define CYBSP_WIFI_SDIO_D2_NUM 2U
+#define CYBSP_WIFI_SDIO_D2_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_D2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_2_HSIOM
#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
-#define SDHC0_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_DAT3_PORT GPIO_PRT2
-#define SDHC0_DAT3_PIN 3U
-#define SDHC0_DAT3_NUM 3U
-#define SDHC0_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_DAT3_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_D2_HSIOM ioss_0_port_2_pin_2_HSIOM
+#define CYBSP_WIFI_SDIO_D2_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_D3_ENABLED 1U
+#define CYBSP_WIFI_SDIO_D3_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_D3_PIN 3U
+#define CYBSP_WIFI_SDIO_D3_NUM 3U
+#define CYBSP_WIFI_SDIO_D3_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_D3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_3_HSIOM
#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
-#define SDHC0_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_CMD_PORT GPIO_PRT2
-#define SDHC0_CMD_PIN 4U
-#define SDHC0_CMD_NUM 4U
-#define SDHC0_CMD_DRIVEMODE CY_GPIO_DM_STRONG
-#define SDHC0_CMD_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_D3_HSIOM ioss_0_port_2_pin_3_HSIOM
+#define CYBSP_WIFI_SDIO_D3_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
+#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_CMD_PIN 4U
+#define CYBSP_WIFI_SDIO_CMD_NUM 4U
+#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
+#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_4_HSIOM
#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
-#define SDHC0_CMD_IRQ ioss_interrupts_gpio_2_IRQn
-#define SDHC0_CLK_PORT GPIO_PRT2
-#define SDHC0_CLK_PIN 5U
-#define SDHC0_CLK_NUM 5U
-#define SDHC0_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define SDHC0_CLK_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
+#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
+#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT2
+#define CYBSP_WIFI_SDIO_CLK_PIN 5U
+#define CYBSP_WIFI_SDIO_CLK_NUM 5U
+#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_5_HSIOM
#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define SDHC0_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
-#define SDHC0_CLK_IRQ ioss_interrupts_gpio_2_IRQn
-#define ENABLE_WIFI_PORT GPIO_PRT2
-#define ENABLE_WIFI_PIN 6U
-#define ENABLE_WIFI_NUM 6U
-#define ENABLE_WIFI_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define ENABLE_WIFI_INIT_DRIVESTATE 0
+#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
+#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_WL_REG_ON_ENABLED 1U
+#define CYBSP_WIFI_WL_REG_ON_PORT GPIO_PRT2
+#define CYBSP_WIFI_WL_REG_ON_PIN 6U
+#define CYBSP_WIFI_WL_REG_ON_NUM 6U
+#define CYBSP_WIFI_WL_REG_ON_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_WIFI_WL_REG_ON_INIT_DRIVESTATE 0
#ifndef ioss_0_port_2_pin_6_HSIOM
#define ioss_0_port_2_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define ENABLE_WIFI_HSIOM ioss_0_port_2_pin_6_HSIOM
-#define ENABLE_WIFI_IRQ ioss_interrupts_gpio_2_IRQn
-#define BT_UART_RX_PORT GPIO_PRT3
-#define BT_UART_RX_PIN 0U
-#define BT_UART_RX_NUM 0U
-#define BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define BT_UART_RX_INIT_DRIVESTATE 1
+#define CYBSP_WIFI_WL_REG_ON_HSIOM ioss_0_port_2_pin_6_HSIOM
+#define CYBSP_WIFI_WL_REG_ON_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
+#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT2
+#define CYBSP_WIFI_HOST_WAKE_PIN 7U
+#define CYBSP_WIFI_HOST_WAKE_NUM 7U
+#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_2_pin_7_HSIOM
+ #define ioss_0_port_2_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_2_pin_7_HSIOM
+#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_2_IRQn
+#define CYBSP_BT_UART_RX_ENABLED 1U
+#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RX_PIN 0U
+#define CYBSP_BT_UART_RX_NUM 0U
+#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_0_HSIOM
#define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
-#define BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_UART_TX_PORT GPIO_PRT3
-#define BT_UART_TX_PIN 1U
-#define BT_UART_TX_NUM 1U
-#define BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define BT_UART_TX_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_UART_TX_ENABLED 1U
+#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
+#define CYBSP_BT_UART_TX_PIN 1U
+#define CYBSP_BT_UART_TX_NUM 1U
+#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_1_HSIOM
#define ioss_0_port_3_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
-#define BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_UART_RTS_PORT GPIO_PRT3
-#define BT_UART_RTS_PIN 2U
-#define BT_UART_RTS_NUM 2U
-#define BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define BT_UART_RTS_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
+#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_UART_RTS_ENABLED 1U
+#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_RTS_PIN 2U
+#define CYBSP_BT_UART_RTS_NUM 2U
+#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_UART_RTS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_2_HSIOM
#define ioss_0_port_3_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
-#define BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_UART_CTS_PORT GPIO_PRT3
-#define BT_UART_CTS_PIN 3U
-#define BT_UART_CTS_NUM 3U
-#define BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define BT_UART_CTS_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
+#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_UART_CTS_ENABLED 1U
+#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
+#define CYBSP_BT_UART_CTS_PIN 3U
+#define CYBSP_BT_UART_CTS_NUM 3U
+#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_3_HSIOM
#define ioss_0_port_3_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
-#define BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_POWER_PORT GPIO_PRT3
-#define BT_POWER_PIN 4U
-#define BT_POWER_NUM 4U
-#define BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
-#define BT_POWER_INIT_DRIVESTATE 1
+#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
+#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_REG_ON_ENABLED 1U
+#define CYBSP_BT_REG_ON_PORT GPIO_PRT3
+#define CYBSP_BT_REG_ON_PIN 4U
+#define CYBSP_BT_REG_ON_NUM 4U
+#define CYBSP_BT_REG_ON_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
+#define CYBSP_BT_REG_ON_INIT_DRIVESTATE 1
#ifndef ioss_0_port_3_pin_4_HSIOM
#define ioss_0_port_3_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
-#define BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
-#define BT_HOST_WAKE_PORT GPIO_PRT4
-#define BT_HOST_WAKE_PIN 0U
-#define BT_HOST_WAKE_NUM 0U
-#define BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define BT_HOST_WAKE_INIT_DRIVESTATE 0
-#ifndef ioss_0_port_4_pin_0_HSIOM
- #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define BT_HOST_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
-#define BT_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
-#define BT_DEVICE_WAKE_PORT GPIO_PRT3
-#define BT_DEVICE_WAKE_PIN 5U
-#define BT_DEVICE_WAKE_NUM 5U
-#define BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#define CYBSP_BT_REG_ON_HSIOM ioss_0_port_3_pin_4_HSIOM
+#define CYBSP_BT_REG_ON_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_HOST_WAKE_ENABLED 1U
+#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
+#define CYBSP_BT_HOST_WAKE_PIN 5U
+#define CYBSP_BT_HOST_WAKE_NUM 5U
+#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_3_pin_5_HSIOM
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define BT_DEVICE_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
-#define BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
-#define EZI2C_SCL_PORT GPIO_PRT6
-#define EZI2C_SCL_PIN 0U
-#define EZI2C_SCL_NUM 0U
-#define EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define EZI2C_SCL_INIT_DRIVESTATE 1
+#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
+#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
+#define CYBSP_BT_DEVICE_WAKE_PIN 0U
+#define CYBSP_BT_DEVICE_WAKE_NUM 0U
+#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
+#ifndef ioss_0_port_4_pin_0_HSIOM
+ #define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
+#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
+#define CYBSP_BT_RST_ENABLED 1U
+#define CYBSP_BT_RST_PORT GPIO_PRT4
+#define CYBSP_BT_RST_PIN 1U
+#define CYBSP_BT_RST_NUM 1U
+#define CYBSP_BT_RST_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_BT_RST_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_4_pin_1_HSIOM
+ #define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_RST_HSIOM ioss_0_port_4_pin_1_HSIOM
+#define CYBSP_BT_RST_IRQ ioss_interrupts_gpio_4_IRQn
+#define CYBSP_EZI2C_SCL_ENABLED 1U
+#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SCL_PIN 0U
+#define CYBSP_EZI2C_SCL_NUM 0U
+#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SCL_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_0_HSIOM
#define ioss_0_port_6_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
-#define EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
-#define EZI2C_SDA_PORT GPIO_PRT6
-#define EZI2C_SDA_PIN 1U
-#define EZI2C_SDA_NUM 1U
-#define EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
-#define EZI2C_SDA_INIT_DRIVESTATE 1
+#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
+#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_EZI2C_SDA_ENABLED 1U
+#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
+#define CYBSP_EZI2C_SDA_PIN 1U
+#define CYBSP_EZI2C_SDA_NUM 1U
+#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
+#define CYBSP_EZI2C_SDA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_1_HSIOM
#define ioss_0_port_6_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
-#define EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWO_PORT GPIO_PRT6
-#define SWO_PIN 4U
-#define SWO_NUM 4U
-#define SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define SWO_INIT_DRIVESTATE 1
+#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
+#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_4_HSIOM
#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWDIO_PORT GPIO_PRT6
-#define SWDIO_PIN 6U
-#define SWDIO_NUM 6U
-#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define SWDIO_INIT_DRIVESTATE 1
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_6_HSIOM
#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#define SWDCK_PORT GPIO_PRT6
-#define SWDCK_PIN 7U
-#define SWDCK_NUM 7U
-#define SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define SWDCK_INIT_DRIVESTATE 1
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWCLK_ENABLED 1U
+#define CYBSP_SWCLK_PORT GPIO_PRT6
+#define CYBSP_SWCLK_PIN 7U
+#define CYBSP_SWCLK_NUM 7U
+#define CYBSP_SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWCLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_6_pin_7_HSIOM
#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#define ioss_0_port_7_pin_0_PORT GPIO_PRT7
-#define ioss_0_port_7_pin_0_PIN 0U
-#define ioss_0_port_7_pin_0_NUM 0U
-#define ioss_0_port_7_pin_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define ioss_0_port_7_pin_0_INIT_DRIVESTATE 1
+#define CYBSP_SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWCLK_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_TRACECLK_ENABLED 1U
+#define CYBSP_TRACECLK_PORT GPIO_PRT7
+#define CYBSP_TRACECLK_PIN 0U
+#define CYBSP_TRACECLK_NUM 0U
+#define CYBSP_TRACECLK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_TRACECLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_0_HSIOM
#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define ioss_0_port_7_pin_0_IRQ ioss_interrupts_gpio_7_IRQn
-#define CINA_PORT GPIO_PRT7
-#define CINA_PIN 1U
-#define CINA_NUM 1U
-#define CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CINA_INIT_DRIVESTATE 1
+#define CYBSP_TRACECLK_HSIOM ioss_0_port_7_pin_0_HSIOM
+#define CYBSP_TRACECLK_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CINTA_ENABLED 1U
+#define CYBSP_CINTA_PORT GPIO_PRT7
+#define CYBSP_CINTA_PIN 1U
+#define CYBSP_CINTA_NUM 1U
+#define CYBSP_CINTA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINTA_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_1_HSIOM
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#define CINB_PORT GPIO_PRT7
-#define CINB_PIN 2U
-#define CINB_NUM 2U
-#define CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CINB_INIT_DRIVESTATE 1
+#define CYBSP_CINTA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINTA_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CINTB_ENABLED 1U
+#define CYBSP_CINTB_PORT GPIO_PRT7
+#define CYBSP_CINTB_PIN 2U
+#define CYBSP_CINTB_NUM 2U
+#define CYBSP_CINTB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINTB_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_2_HSIOM
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#define CMOD_PORT GPIO_PRT7
-#define CMOD_PIN 7U
-#define CMOD_NUM 7U
-#define CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CMOD_INIT_DRIVESTATE 1
+#define CYBSP_CINTB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINTB_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_7_pin_7_HSIOM
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#define CSD_BTN0_PORT GPIO_PRT8
-#define CSD_BTN0_PIN 1U
-#define CSD_BTN0_NUM 1U
-#define CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_BTN0_INIT_DRIVESTATE 1
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_1_HSIOM
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_BTN1_PORT GPIO_PRT8
-#define CSD_BTN1_PIN 2U
-#define CSD_BTN1_NUM 2U
-#define CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_BTN1_INIT_DRIVESTATE 1
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_2_HSIOM
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD0_PORT GPIO_PRT8
-#define CSD_SLD0_PIN 3U
-#define CSD_SLD0_NUM 3U
-#define CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD0_INIT_DRIVESTATE 1
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_3_HSIOM
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD1_PORT GPIO_PRT8
-#define CSD_SLD1_PIN 4U
-#define CSD_SLD1_NUM 4U
-#define CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD1_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_4_HSIOM
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD2_PORT GPIO_PRT8
-#define CSD_SLD2_PIN 5U
-#define CSD_SLD2_NUM 5U
-#define CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD2_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_5_HSIOM
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD3_PORT GPIO_PRT8
-#define CSD_SLD3_PIN 6U
-#define CSD_SLD3_NUM 6U
-#define CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD3_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_6_HSIOM
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#define CSD_SLD4_PORT GPIO_PRT8
-#define CSD_SLD4_PIN 7U
-#define CSD_SLD4_NUM 7U
-#define CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CSD_SLD4_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_8_pin_7_HSIOM
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
-#define CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-#define ioss_0_port_9_pin_0_PORT GPIO_PRT9
-#define ioss_0_port_9_pin_0_PIN 0U
-#define ioss_0_port_9_pin_0_NUM 0U
-#define ioss_0_port_9_pin_0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define ioss_0_port_9_pin_0_INIT_DRIVESTATE 1
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_TRACEDATA3_ENABLED 1U
+#define CYBSP_TRACEDATA3_PORT GPIO_PRT9
+#define CYBSP_TRACEDATA3_PIN 0U
+#define CYBSP_TRACEDATA3_NUM 0U
+#define CYBSP_TRACEDATA3_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_TRACEDATA3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_9_pin_0_HSIOM
#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
-#define ioss_0_port_9_pin_0_IRQ ioss_interrupts_gpio_9_IRQn
-#define ioss_0_port_9_pin_1_PORT GPIO_PRT9
-#define ioss_0_port_9_pin_1_PIN 1U
-#define ioss_0_port_9_pin_1_NUM 1U
-#define ioss_0_port_9_pin_1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define ioss_0_port_9_pin_1_INIT_DRIVESTATE 1
+#define CYBSP_TRACEDATA3_HSIOM ioss_0_port_9_pin_0_HSIOM
+#define CYBSP_TRACEDATA3_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_TRACEDATA2_ENABLED 1U
+#define CYBSP_TRACEDATA2_PORT GPIO_PRT9
+#define CYBSP_TRACEDATA2_PIN 1U
+#define CYBSP_TRACEDATA2_NUM 1U
+#define CYBSP_TRACEDATA2_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_TRACEDATA2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_9_pin_1_HSIOM
#define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
-#define ioss_0_port_9_pin_1_IRQ ioss_interrupts_gpio_9_IRQn
-#define ioss_0_port_9_pin_2_PORT GPIO_PRT9
-#define ioss_0_port_9_pin_2_PIN 2U
-#define ioss_0_port_9_pin_2_NUM 2U
-#define ioss_0_port_9_pin_2_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define ioss_0_port_9_pin_2_INIT_DRIVESTATE 1
+#define CYBSP_TRACEDATA2_HSIOM ioss_0_port_9_pin_1_HSIOM
+#define CYBSP_TRACEDATA2_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_TRACEDATA1_ENABLED 1U
+#define CYBSP_TRACEDATA1_PORT GPIO_PRT9
+#define CYBSP_TRACEDATA1_PIN 2U
+#define CYBSP_TRACEDATA1_NUM 2U
+#define CYBSP_TRACEDATA1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_TRACEDATA1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_9_pin_2_HSIOM
#define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
-#define ioss_0_port_9_pin_2_IRQ ioss_interrupts_gpio_9_IRQn
-#define ioss_0_port_9_pin_3_PORT GPIO_PRT9
-#define ioss_0_port_9_pin_3_PIN 3U
-#define ioss_0_port_9_pin_3_NUM 3U
-#define ioss_0_port_9_pin_3_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define ioss_0_port_9_pin_3_INIT_DRIVESTATE 1
+#define CYBSP_TRACEDATA1_HSIOM ioss_0_port_9_pin_2_HSIOM
+#define CYBSP_TRACEDATA1_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_TRACEDATA0_ENABLED 1U
+#define CYBSP_TRACEDATA0_PORT GPIO_PRT9
+#define CYBSP_TRACEDATA0_PIN 3U
+#define CYBSP_TRACEDATA0_NUM 3U
+#define CYBSP_TRACEDATA0_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_TRACEDATA0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_9_pin_3_HSIOM
#define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
-#define ioss_0_port_9_pin_3_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_TRACEDATA0_HSIOM ioss_0_port_9_pin_3_HSIOM
+#define CYBSP_TRACEDATA0_IRQ ioss_interrupts_gpio_9_IRQn
-extern const cy_stc_gpio_pin_config_t WCO_IN_config;
-extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
-extern const cy_stc_gpio_pin_config_t LED_RED_config;
-extern const cy_stc_gpio_pin_config_t SW6_config;
-extern const cy_stc_gpio_pin_config_t LED_BLUE_config;
-extern const cy_stc_gpio_pin_config_t WL_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t WL_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t QSPI_SS0_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA3_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA2_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA1_config;
-extern const cy_stc_gpio_pin_config_t QSPI_DATA0_config;
-extern const cy_stc_gpio_pin_config_t QSPI_SPI_CLOCK_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_12_pin_6_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_12_pin_7_config;
-extern const cy_stc_gpio_pin_config_t UART_RX_config;
-extern const cy_stc_gpio_pin_config_t UART_TX_config;
-extern const cy_stc_gpio_pin_config_t LED9_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config;
-extern const cy_stc_gpio_pin_config_t CSD_TX_config;
-extern const cy_stc_gpio_pin_config_t LED_GREEN_config;
-extern const cy_stc_gpio_pin_config_t LED8_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT0_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT1_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT2_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_DAT3_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_CMD_config;
-extern const cy_stc_gpio_pin_config_t SDHC0_CLK_config;
-extern const cy_stc_gpio_pin_config_t ENABLE_WIFI_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_RX_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_TX_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_RTS_config;
-extern const cy_stc_gpio_pin_config_t BT_UART_CTS_config;
-extern const cy_stc_gpio_pin_config_t BT_POWER_config;
-extern const cy_stc_gpio_pin_config_t BT_HOST_WAKE_config;
-extern const cy_stc_gpio_pin_config_t BT_DEVICE_WAKE_config;
-extern const cy_stc_gpio_pin_config_t EZI2C_SCL_config;
-extern const cy_stc_gpio_pin_config_t EZI2C_SDA_config;
-extern const cy_stc_gpio_pin_config_t SWO_config;
-extern const cy_stc_gpio_pin_config_t SWDIO_config;
-extern const cy_stc_gpio_pin_config_t SWDCK_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_7_pin_0_config;
-extern const cy_stc_gpio_pin_config_t CINA_config;
-extern const cy_stc_gpio_pin_config_t CINB_config;
-extern const cy_stc_gpio_pin_config_t CMOD_config;
-extern const cy_stc_gpio_pin_config_t CSD_BTN0_config;
-extern const cy_stc_gpio_pin_config_t CSD_BTN1_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD0_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD1_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD2_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD3_config;
-extern const cy_stc_gpio_pin_config_t CSD_SLD4_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_0_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_1_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_2_config;
-extern const cy_stc_gpio_pin_config_t ioss_0_port_9_pin_3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SW6_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_ROW6_SPI_MOSI_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_COL8_SPI_MISO_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_ROW7_SPI_CLK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_COL7_SPI_CS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BAT_MON_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_WAKE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_UART_RX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_UART_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO4_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO5_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_GPIO3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DEV_VBUS_DET_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_HOST_EN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_INT_L_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_IN_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_FRAM_SYNC_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_PRIORITY_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WL_SECI_OUT_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_REG_ON_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_RST_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_TRACECLK_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CINTA_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CINTB_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA3_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA1_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_TRACEDATA0_config;
void init_cycfg_pins(void);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h
deleted file mode 100644
index 76dfbef7bc..0000000000
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_platform.h
-*
-* Description:
-* Platform configuration
-* This file was automatically generated and should not be modified.
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PLATFORM_H)
-#define CYCFG_PLATFORM_H
-
-#include "cycfg_notices.h"
-#include "cy_sysclk.h"
-#include "cy_systick.h"
-#include "cy_gpio.h"
-#include "cy_syspm.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
-#define CY_CFG_PWR_VDDA_MV 3300
-#define CY_CFG_PWR_VDDD_MV 3300
-#define CY_CFG_PWR_VBACKUP_MV 3300
-#define CY_CFG_PWR_VDD_NS_MV 3300
-#define CY_CFG_PWR_VDDIO0_MV 3300
-#define CY_CFG_PWR_VDDIO1_MV 3300
-
-void init_cycfg_platform(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PLATFORM_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.c
new file mode 100644
index 0000000000..12487034d7
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.c
@@ -0,0 +1,264 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0xEBU,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_QUAD,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0x01U,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_QUAD,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 4U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x06U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x04U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0xD8U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x60U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x38U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_QUAD,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x35U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x05U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x01U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+{
+ /* Specifies the number of address bytes used by the memory slave device. */
+ .numOfAddrBytes = 0x03U,
+ /* The size of the memory. */
+ .memSize = 0x04000000U,
+ /* Specifies the Read command. */
+ .readCmd = &S25FL512S_SlaveSlot_0_readCmd,
+ /* Specifies the Write Enable command. */
+ .writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
+ /* Specifies the Write Disable command. */
+ .writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
+ /* Specifies the Erase command. */
+ .eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
+ /* Specifies the sector size of each erase. */
+ .eraseSize = 0x00040000U,
+ /* Specifies the Chip Erase command. */
+ .chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
+ /* Specifies the Program command. */
+ .programCmd = &S25FL512S_SlaveSlot_0_programCmd,
+ /* Specifies the page size for programming. */
+ .programSize = 0x00000200U,
+ /* Specifies the command to read the QE-containing status register. */
+ .readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+ /* Specifies the command to read the WIP-containing status register. */
+ .readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+ /* Specifies the command to write into the QE-containing status register. */
+ .writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+ /* The mask for the status register. */
+ .stsRegBusyMask = 0x01U,
+ /* The mask for the status register. */
+ .stsRegQuadEnableMask = 0x02U,
+ /* The max time for the erase type-1 cycle-time in ms. */
+ .eraseTime = 520U,
+ /* The max time for the chip-erase cycle-time in ms. */
+ .chipEraseTime = 134000U,
+ /* The max time for the page-program cycle-time in us. */
+ .programTime = 340U
+};
+
+const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+{
+ /* Determines the slot number where the memory device is placed. */
+ .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+ /* Flags. */
+ .flags = CY_SMIF_FLAG_WR_EN,
+ /* The data-line selection options for a slave device. */
+ .dataSelect = CY_SMIF_DATA_SEL0,
+ /* The base address the memory slave is mapped to in the PSoC memory map.
+ Valid when the memory-mapped mode is enabled. */
+ .baseAddress = 0x18000000U,
+ /* The size allocated in the PSoC memory map, for the memory slave device.
+ The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+ .memMappedSize = 0x10000U,
+ /* If this memory device is one of the devices in the dual quad SPI configuration.
+ Valid when the memory mapped mode is enabled. */
+ .dualQuadSlots = 0,
+ /* The configuration of the device. */
+ .deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
+ &S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_block_config_t smifBlockConfig =
+{
+ /* The number of SMIF memories defined. */
+ .memCount = CY_SMIF_DEVICE_NUM,
+ /* The pointer to the array of memory config structures of size memCount. */
+ .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+ /* The version of the SMIF driver. */
+ .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+ /* The version of the SMIF driver. */
+ .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+};
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.h
new file mode 100644
index 0000000000..1f4fb5dfca
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_qspi_memslot.h
@@ -0,0 +1,49 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+
+extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CY_SMIF_MEMCONFIG_H*/
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c
index ce54f0f125..5dc2e16869 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.c
@@ -32,14 +32,14 @@
void init_cycfg_routing(void)
{
- Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT0, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
- Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT5, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
- Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT49, false, TRIGGER_TYPE_LEVEL);
- Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT48, false, TRIGGER_TYPE_LEVEL);
- Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT43, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT45, false, TRIGGER_TYPE_LEVEL);
+ Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT2, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
- Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT6, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h
index 8b3a102733..73304eb940 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_routing.h
@@ -32,14 +32,25 @@ extern "C" {
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
+#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
+#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
+#define ioss_0_port_10_pin_0_HSIOM P10_0_SCB1_SPI_MOSI
+#define ioss_0_port_10_pin_2_HSIOM P10_2_SCB1_SPI_CLK
+#define ioss_0_port_10_pin_3_HSIOM P10_3_SCB1_SPI_SELECT0
+#define ioss_0_port_11_pin_0_HSIOM P11_0_SCB5_UART_RX
+#define ioss_0_port_11_pin_1_HSIOM P11_1_SCB5_UART_TX
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
+#define ioss_0_port_12_pin_6_ANALOG P12_6_SRSS_ECO_IN
+#define ioss_0_port_12_pin_7_ANALOG P12_7_SRSS_ECO_OUT
#define ioss_0_port_13_pin_0_HSIOM P13_0_SCB6_UART_RX
#define ioss_0_port_13_pin_1_HSIOM P13_1_SCB6_UART_TX
+#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
+#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI
#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI
@@ -57,33 +68,33 @@ void init_cycfg_routing(void);
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_0_HSIOM P7_0_CPUSS_TRACE_CLOCK
-#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_9_pin_0_HSIOM P9_0_CPUSS_TRACE_DATA3
#define ioss_0_port_9_pin_1_HSIOM P9_1_CPUSS_TRACE_DATA2
#define ioss_0_port_9_pin_2_HSIOM P9_2_CPUSS_TRACE_DATA1
#define ioss_0_port_9_pin_3_HSIOM P9_3_CPUSS_TRACE_DATA0
+#define CYBSP_SDIO_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
+#define CYBSP_SDIO_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
+#define CYBSP_SDIO_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
+#define CYBSP_SDIO_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
+#define CYBSP_SDIO_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT1
+#define CYBSP_SDIO_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
+#define CYBSP_SDIO_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
+#define CYBSP_SDIO_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT2
#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0
#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1
#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
-#define udb_0_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
-#define udb_0_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT6
-#define udb_0_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT5
-#define udb_0_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
-#define udb_0_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT0
-#define udb_0_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
-#define udb_0_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
-#define udb_0_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT2
#if defined(__cplusplus)
}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.c
similarity index 83%
rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c
rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.c
index 877af05d9c..ffcf6d1a0a 100644
--- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_platform.c
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.c
@@ -1,8 +1,8 @@
/*******************************************************************************
-* File Name: cycfg_platform.c
+* File Name: cycfg_system.c
*
* Description:
-* Platform configuration
+* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
@@ -22,7 +22,7 @@
* limitations under the License.
********************************************************************************/
-#include "cycfg_platform.h"
+#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
@@ -65,10 +65,10 @@
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
-#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_USING_PMIC 0
-#define CY_CFG_PWR_VBAC_SUPPLY CY_CFG_PWR_VBAC_SUPPLY_VDD
-#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
@@ -141,21 +141,21 @@ __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
}
__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
{
- Cy_SysClk_ClkHfSetSource(1U, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(1U, CY_SYSCLK_CLKHF_NO_DIVIDE);
- Cy_SysClk_ClkHfEnable(1U);
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
- Cy_SysClk_ClkHfSetSource(2U, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(2U, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
- Cy_SysClk_ClkHfEnable(2U);
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
- Cy_SysClk_ClkHfSetSource(3U, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(3U, CY_SYSCLK_CLKHF_NO_DIVIDE);
- Cy_SysClk_ClkHfEnable(3U);
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
@@ -223,42 +223,58 @@ __STATIC_INLINE void Cy_SysClk_WcoInit()
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
+__STATIC_INLINE void init_cycfg_power(void)
+{
+ /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
+ #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+ if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+ {
+ Cy_SysLib_ResetBackupDomain();
+ Cy_SysClk_IloDisable();
+ Cy_SysClk_IloInit();
+ }
+ #else /* Dedicated Supply */
+ Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
+ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+ /* Configure core regulator */
+ #if CY_CFG_PWR_USING_LDO
+ Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+ Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
+ #else
+ Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
+ #endif /* CY_CFG_PWR_USING_LDO */
+ /* Configure PMIC */
+ Cy_SysPm_UnlockPmic();
+ #if CY_CFG_PWR_USING_PMIC
+ Cy_SysPm_PmicEnableOutput();
+ #else
+ Cy_SysPm_PmicDisableOutput();
+ #endif /* CY_CFG_PWR_USING_PMIC */
+}
-void init_cycfg_platform(void)
+void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
- #if (CY_CFG_PWR_VBAC_SUPPLY == CY_CFG_PWR_VBAC_SUPPLY_VDD)
- if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
- {
- Cy_SysLib_ResetBackupDomain();
- Cy_SysClk_IloDisable();
- Cy_SysClk_IloInit();
- }
- #endif
#ifdef CY_CFG_PWR_ENABLED
- /* Configure power mode */
- #if CY_CFG_PWR_USING_LDO
- Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
- #else
- Cy_SysPm_BuckEnable(CY_CFG_PWR_BUCK_VOLTAGE);
- #endif
- /* Configure PMIC */
- Cy_SysPm_UnlockPmic();
- #if CY_CFG_PWR_USING_PMIC
- Cy_SysPm_PmicEnableOutput();
- #else
- Cy_SysPm_PmicDisableOutput();
- #endif
- #endif
+ #ifdef CY_CFG_PWR_INIT
+ init_cycfg_power();
+ #else
+ #warning Power system will not be configured. Update power personality to v1.20 or later.
+ #endif /* CY_CFG_PWR_INIT */
+ #endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
- Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+ {
+ (void)Cy_SysClk_PllDisable(pll);
+ }
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
@@ -274,61 +290,6 @@ void init_cycfg_platform(void)
(void)Cy_BLE_EcoReset();
#endif
- #ifdef CY_CFG_SYSCLK_PLL1_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL2_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH3);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL3_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH4);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL4_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH5);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL5_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH6);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL6_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH7);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL7_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH8);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL8_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH9);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL9_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH10);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL10_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH11);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL11_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH12);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL12_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH13);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL13_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH14);
- #endif
-
- #ifdef CY_CFG_SYSCLK_PLL14_AVAILABLE
- (void)Cy_SysClk_PllDisable(CY_SYSCLK_CLKHF_IN_CLKPATH15);
- #endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
@@ -561,6 +522,14 @@ void init_cycfg_platform(void)
#error the IMO must be enabled for proper chip operation
#endif
+ #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+ Cy_SysClk_MfoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+ Cy_SysClk_ClkMfInit();
+ #endif
+
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.h
new file mode 100644
index 0000000000..9110cd20a6
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/cycfg_system.h
@@ -0,0 +1,91 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_systick.h"
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_eco_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define srss_0_clock_0_hfclk_1_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF1 1UL
+#define srss_0_clock_0_hfclk_2_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF2 2UL
+#define srss_0_clock_0_hfclk_3_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF3 3UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_timerclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_SLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/qspi_config.cfg
new file mode 100644
index 0000000000..a561643dcf
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/GeneratedSource/qspi_config.cfg
@@ -0,0 +1,2 @@
+set SMIF_BANKS {
+}
diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/design.modus
new file mode 100644
index 0000000000..99308ff45d
--- /dev/null
+++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/design.modus
@@ -0,0 +1,1583 @@
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