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Merge pull request #13392 from heuisam/dev_bp6a 

Adding Samsung Bioprocessor S1SBP6A target
pull/13404/head
Martin Kojtal 2020-08-13 09:00:50 +01:00 committed by GitHub
parent 408461b9de e3ba0100bb
commit aff95c0d19
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
66 changed files with 8526 additions and 2 deletions
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85
targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/PeripheralNames.h Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "PinNames.h"
#include "PeripheralNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)BP_UART0_BASE,
UART_1 = (int)BP_UART1_BASE,
UART_2 = (int)BP_UART2_BASE
} UARTName;
#define DEVICE_SPI_COUNT 5
typedef enum {
SPI_0 = (int)BP_SPI0_BASE,
SPI_1 = (int)BP_SPI1_BASE,
SPI_2 = (int)BP_SPI2_BASE,
SPI_3 = (int)BP_SPI3_BASE,
SPI_4 = (int)BP_SPI4_BASE
} SPIName;
typedef enum {
I2C_0 = (int)BP_I2C0_BASE,
I2C_1 = (int)BP_I2C1_BASE,
I2C_2 = (int)BP_I2C2_BASE,
I2C_3 = (int)BP_I2C3_BASE,
I2C_4 = (int)BP_I2C4_BASE
} I2CName;
typedef enum {
ADC_0 = 0,
ADC_1 = 1,
ADC_2 = 2,
ADC_MAX_NUM
} ADCName;
typedef enum {
PWM_0 = (int)BP_PWM_TIMER_BASE,
} PWMName;
#define _UART_NAME_(a, b) a ## b
#define _UART_NAME(a, b) _UART_NAME_(a, b)
#ifndef UART_STDIO_PORT
#define STDIO_UART_TX UART_TX0
#define STDIO_UART_RX UART_RX0
#define STDIO_UART UART_0
#else
#define STDIO_UART_TX _UART_NAME(UART_TX, UART_STDIO_PORT)
#define STDIO_UART_RX _UART_NAME(UART_RX, UART_STDIO_PORT)
#define STDIO_UART _UART_NAME(UART_, UART_STDIO_PORT)
#endif
#define USBTX UART_TX0
#define USBRX UART_RX0
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/PeripheralPins.c Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "PeripheralPins.h"
const PinMap PinMap_empty[] = {
{ NC, NC, 0 }
};
#if DEVICE_SERIAL
//*** SERIAL ***
const PinMap PinMap_UART_TX[] = {
{ UART0_TX, BP_UART0_BASE, BP6A_PIN_DATA(ALT0, PIN_OUTPUT, PullNone, 0) },
{ UART1_TX, BP_UART1_BASE, BP6A_PIN_DATA(ALT0, PIN_OUTPUT, PullNone, 1) },
{ UART2_TX, BP_UART2_BASE, BP6A_PIN_DATA(ALT0, PIN_OUTPUT, PullNone, 2) },
{ NC, NC, 0 }
};
const PinMap PinMap_UART_RX[] = {
{ UART0_RX, BP_UART0_BASE, BP6A_PIN_DATA(ALT0, PIN_INPUT, PullNone, 0) },
{ UART1_RX, BP_UART1_BASE, BP6A_PIN_DATA(ALT0, PIN_INPUT, PullNone, 1) },
{ UART2_RX, BP_UART2_BASE, BP6A_PIN_DATA(ALT0, PIN_INPUT, PullNone, 2) },
{ NC, NC, 0 }
};
const PinMap PinMap_UART_CTS[] = {
{ UART0_CTS, BP_UART0_BASE, BP6A_PIN_DATA(ALT0, PIN_INPUT, PullNone, 0)},
{ UART1_CTS, BP_UART1_BASE, BP6A_PIN_DATA(ALT0, PIN_INPUT, PullNone, 1)},
{ UART2_CTS, BP_UART2_BASE, BP6A_PIN_DATA(ALT0, PIN_INPUT, PullNone, 2)},
{NC, NC, 0}
};
const PinMap PinMap_UART_RTS[] = {
{ UART0_RTS, BP_UART0_BASE, BP6A_PIN_DATA(ALT0, PIN_OUTPUT, PullNone, 0)},
{ UART1_RTS, BP_UART1_BASE, BP6A_PIN_DATA(ALT0, PIN_OUTPUT, PullNone, 1)},
{ UART2_RTS, BP_UART2_BASE, BP6A_PIN_DATA(ALT0, PIN_OUTPUT, PullNone, 2)},
{NC, NC, 0}
};
#endif
#if DEVICE_SPI
//*** SPI ***
const PinMap PinMap_SPI_SCLK[] = {
{ SPI0_SCLK, BP_SPI0_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 0) },
{ SPI1_SCLK, BP_SPI1_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 1) },
{ SPI2_SCLK, BP_SPI2_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 2) },
{ SPI3_SCLK, BP_SPI3_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 3) },
{ SPI4_SCLK, BP_SPI4_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 4) },
{ NC, NC, 0 }
};
const PinMap PinMap_SPI_SSEL[] = {
{ SPI0_SSEL, BP_SPI0_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 0) },
{ SPI1_SSEL, BP_SPI1_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 1) },
{ SPI2_SSEL, BP_SPI2_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 2) },
{ SPI3_SSEL, BP_SPI3_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 3) },
{ SPI4_SSEL, BP_SPI4_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 4) },
{ NC, NC, 0 }
};
const PinMap PinMap_SPI_MOSI[] = {
{ SPI0_MOSI, BP_SPI0_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 0) },
{ SPI1_MOSI, BP_SPI1_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 1) },
{ SPI2_MOSI, BP_SPI2_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 2) },
{ SPI3_MOSI, BP_SPI3_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 3) },
{ SPI4_MOSI, BP_SPI4_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 4) },
{ NC, NC, 0 }
};
const PinMap PinMap_SPI_MISO[] = {
{ SPI0_MISO, BP_SPI0_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 0) },
{ SPI1_MISO, BP_SPI1_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 1) },
{ SPI2_MISO, BP_SPI2_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 2) },
{ SPI3_MISO, BP_SPI3_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 3) },
{ SPI4_MISO, BP_SPI4_BASE, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullNone, 4) },
{ NC, NC, 0 }
};
#endif
//*** I2C ***
#if DEVICE_I2C
const PinMap PinMap_I2C_SDA[] = {
{ I2C0_SDA, 0, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullUp_2200, 0) },
{ I2C1_SDA, 1, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullUp_2200, 1) },
{ I2C2_SDA, 2, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullUp_2200, 2) },
{ I2C3_SDA, 3, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullUp_2200, 3) },
{ I2C4_SDA, 4, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullUp_2200, 4) },
{ NC, NC, 0 }
};
const PinMap PinMap_I2C_SCL[] = {
{ I2C0_SCL, 0, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullUp_2200, 0) },
{ I2C1_SCL, 1, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullUp_2200, 1) },
{ I2C2_SCL, 2, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullUp_2200, 2) },
{ I2C3_SCL, 3, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullUp_2200, 3) },
{ I2C4_SCL, 4, BP6A_PIN_DATA(ALT0, (PIN_INPUT | PIN_OUTPUT), PullUp_2200, 4) },
{ NC, NC, 0 }
};
#endif
#if DEVICE_ANALOGIN
static const PinMap PinMap_ADC[] = {
{AN0, ADC_0, GPIO_FUNC1},
{AN1, ADC_1, GPIO_FUNC1},
{AN2, ADC_2, GPIO_FUNC1},
{NC, NC, 0}
};
#endif
#endif

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/PeripheralPins.h Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#define BP6A_PIN_DATA(sel, dir, mode, channel) (sel | (dir << 8) | (mode << 16) | (channel << 24))
#define GET_PIN_SEL(data) ( data & 0xff)
#define GET_PIN_DIR(data) ((data >> 8) & 0xff)
#define GET_PIN_MODE(data) ((data >> 16) & 0xff)
#define GET_PIN_CHAN(data) ((data >> 24) & 0xff)
extern const PinMap PinMap_empty[];
//*** ADC ***
#if DEVICE_ANALOGIN
extern const PinMap PinMap_ADC[];
extern const PinMap PinMap_ADC_Internal[];
#endif
//*** I2C ***
#if DEVICE_I2C
extern const PinMap PinMap_I2C_SDA[];
extern const PinMap PinMap_I2C_SCL[];
#endif
//*** PWM ***
#if DEVICE_PWMOUT
extern const PinMap PinMap_PWM[];
#endif
//*** SERIAL ***
#if DEVICE_SERIAL
extern const PinMap PinMap_UART_TX[];
extern const PinMap PinMap_UART_RX[];
extern const PinMap PinMap_UART_CTS[];
extern const PinMap PinMap_UART_RTS[];
#endif
//*** SPI ***
#if DEVICE_SPI
extern const PinMap PinMap_SPI_MOSI[];
extern const PinMap PinMap_SPI_MISO[];
extern const PinMap PinMap_SPI_SCLK[];
extern const PinMap PinMap_SPI_SSEL[];
#endif
#endif

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/PinNames.h Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#define BP6A_PORT_IDX(pin) ((uint32_t)((pin) / 16))
#define BP6A_PIN_IDX(pin) ((uint32_t)((pin) % 16))
typedef enum {
ALT0 = 0,
ALT1
} ALTx;
typedef enum {
PIN_OUTPUT = 1,
PIN_INPUT = 2
} PinDirection;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
PullUp_60K = 0x04,
PullUp_2200 = 0x08,
PUllDown_60K = 0x10,
PullDefault = PullNone
} PinMode;
typedef enum {
GPIO00,
GPIO01,
GPIO02,
GPIO03,
GPIO04,
GPIO05,
GPIO06,
GPIO07,
GPIO08,
GPIO09,
GPIO0A,
GPIO0B,
GPIO0C,
GPIO0D,
GPIO0E,
GPIO0F,
GPIO10,
GPIO11,
GPIO12,
GPIO13,
GPIO14,
GPIO15,
GPIO16,
GPIO17,
GPIO18,
GPIO19,
GPIO1A,
GPIO1B,
GPIO1C,
GPIO1D,
GPIO1E,
GPIO1F,
GPIO20,
GPIO21,
GPIO22,
GPIO23,
GPIO24,
GPIO25,
GPIO26,
GPIO27,
GPIO28,
GPIO29,
GPIO2A,
GPIO2B,
GPIO2C,
GPIO2D,
GPIO2E,
GPIO2F,
GPA0_INP,
GPA0_INN,
GPA1_INP,
GPA1_INN,
GPA24_INP0,
GPA24_INN0,
ECG_INP,
ECG_INN,
UART_TX0 = GPIO24,
UART_RX0 = GPIO25,
AN0 = GPA0_INP,
AN1 = GPA1_INP,
AN2 = GPA24_INP0,
UART0_TX = GPIO24,
UART1_TX = GPIO10,
UART2_TX = GPIO14,
UART0_RX = GPIO25,
UART1_RX = GPIO11,
UART2_RX = GPIO15,
UART0_CTS = GPIO26,
UART1_CTS = GPIO12,
UART2_CTS = GPIO16,
UART0_RTS = GPIO27,
UART1_RTS = GPIO13,
UART2_RTS = GPIO17,
SPI0_SCLK = GPIO20,
SPI1_SCLK = GPIO00,
SPI2_SCLK = GPIO04,
SPI3_SCLK = GPIO08,
SPI4_SCLK = GPIO0C,
SPI0_SSEL = GPIO21,
SPI1_SSEL = GPIO01,
SPI2_SSEL = GPIO05,
SPI3_SSEL = GPIO09,
SPI4_SSEL = GPIO0D,
SPI0_MOSI = GPIO22,
SPI1_MOSI = GPIO02,
SPI2_MOSI = GPIO06,
SPI3_MOSI = GPIO0A,
SPI4_MOSI = GPIO0E,
SPI0_MISO = GPIO23,
SPI1_MISO = GPIO03,
SPI2_MISO = GPIO07,
SPI3_MISO = GPIO08,
SPI4_MISO = GPIO0F,
I2C0_SDA = GPIO29,
I2C1_SDA = GPIO19,
I2C2_SDA = GPIO1B,
I2C3_SDA = GPIO1D,
I2C4_SDA = GPIO1F,
I2C0_SCL = GPIO28,
I2C1_SCL = GPIO18,
I2C2_SCL = GPIO1A,
I2C3_SCL = GPIO1C,
I2C4_SCL = GPIO1E,
BUZZER = GPIO03,
RED_LED = GPIO04,
LED1 = RED_LED,
BLUE_LED = GPIO05,
GREEN_LED = GPIO06,
BUTTON = GPIO07,
NC = (int)0xFFFFFFFF,
} PinName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/PortNames.h Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1,
Port2 = 2
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device.h Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/TOOLCHAIN_ARM_STD/s1sbp6a.sct Normal file
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#! armcc -E
;* Copyright (c) 2006-2019 ARM Limited
;* All rights reserved.
;* SPDX-License-Identifier: Apache-2.0
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;* specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
;#include "../memory_zones.h"
#include "../cmsis_nvic.h"
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x0000000
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x200000 // 2MB KB
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x40000 // 256 KB
#endif
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x0080000 //512K
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#if (defined(__stack_size__))
#define STACK_SIZE __stack_size__
#else
#define STACK_SIZE MBED_BOOT_STACK_SIZE
#endif
; The vector table is loaded at address 0x00000000 in Flash memory region.
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
*(+RO)
}
; NVIC_VECTORS_SIZE Total
RW_IRAM1 (MBED_RAM_START + NVIC_VECTORS_SIZE) (MBED_RAM_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
*(+RW +ZI)
}
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}
}

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/TOOLCHAIN_ARM_STD/startup_s1sbp6a.S Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD BOR_Handler ; 00: Brown Out Reset Handler
DCD UART0_Handler ; 01: UART 0 Handler
DCD UART1_Handler ; 02: UART 1 Handler
DCD UART2_Handler ; 03: UART 2 Handler
DCD SPI0_Handler ; 04: SPI 0 Handler
DCD SPI1_Handler ; 05: SPI 1 Handler
DCD SPI2_Handler ; 06: SPI 2 Handler
DCD SPI3_Handler ; 07: SPI 3 Handler
DCD SPI4_Handler ; 08: SPI 4 Handler
DCD I2C0_Handler ; 09: I2C 0 Handler
DCD I2C1_Handler ; 10: I2C 1 Handler
DCD I2C2_Handler ; 11: I2C 2 Handler
DCD I2C3_Handler ; 12: I2C 3 Handler
DCD I2C4_Handler ; 13: I2C 4 Handler
DCD TIMER0_Handler ; 14: TIMER 0 Handler
DCD TIMER1_Handler ; 15: TIMER 1 Handler
DCD TIMER2_Handler ; 16: TIMER 2 Handler
DCD TIMER3_Handler ; 17: TIMER 3 Handler
DCD TIMER4_Handler ; 18: TIMER 4 Handler
DCD TIMER5_Handler ; 19: TIMER 5 Handler
DCD TIMER6_Handler ; 20: TIMER 6 Handler
DCD PWM_TIMER_Handler ; 21: PWM TIMER Handler
DCD DUAL_TIMER_Handler ; 22: Dual TIMER Handler
DCD AFECON_Handler ; 23: Analog Front End Control Handler
DCD SRC_Handler ; 24: Sample Rate Converter Handler
DCD DMA_ERROR_Handler ; 25: DMA Error Handler
DCD FLASH_Handler ; 26: FLASH Handler
DCD RTC0_Handler ; 27: Real-Time Counter 0 Handler
DCD RTC1_Handler ; 28: Real-Time Counter 1 Handler
DCD RTC2_Handler ; 29: Real-Time Counter 2 Handler
DCD FPU_Handler ; 30: Cortex-M4 Floating-point Processing Unit exceptions Handler
DCD SRP0_Handler ; 31: SRP 0 Handler
DCD SRP1_Handler ; 32: SRP 1 Handler
DCD DELAY_MON_Handler ; 33: Delay Monitor Handler
DCD AES_Handler ; 34: AES Handler
DCD EXT_WAKEUP_Handler ; 35: External Wakeup Handler
DCD DMA0_Handler ; 36: DMA 0 Handler
DCD DMA1_Handler ; 37: DMA 1 Handler
DCD DMA2_Handler ; 38: DMA 2 Handler
DCD DMA3_Handler ; 39: DMA 3 Handler
DCD DMA4_Handler ; 40: DMA 4 Handler
DCD DMA5_Handler ; 41: DMA 5 Handler
DCD DMA6_Handler ; 42: DMA 6 Handler
DCD DMA7_Handler ; 43: DMA 7 Handler
DCD DMA8_Handler ; 44: DMA 8 Handler
DCD DMA9_Handler ; 45: DMA 9 Handler
DCD DMA10_Handler ; 46: DMA 10 Handler
DCD DMA11_Handler ; 47: DMA 11 Handler
DCD DMA12_Handler ; 48: DMA 12 Handler
DCD DMA13_Handler ; 49: DMA 13 Handler
DCD DMA14_Handler ; 50: DMA 14 Handler
DCD DMA15_Handler ; 51: DMA 15 Handler
DCD DMA16_Handler ; 52: DMA 16 Handler
DCD DMA17_Handler ; 53: DMA 17 Handler
DCD DMA18_Handler ; 54: DMA 18 Handler
DCD DMA19_Handler ; 55: DMA 19 Handler
DCD DMA20_Handler ; 56: DMA 20 Handler
DCD DMA21_Handler ; 57: DMA 21 Handler
DCD DMA22_Handler ; 58: DMA 22 Handler
DCD DMA23_Handler ; 59: DMA 23 Handler
DCD DMA24_Handler ; 60: DMA 24 Handler
DCD DMA25_Handler ; 61: DMA 25 Handler
DCD DMA26_Handler ; 62: DMA 26 Handler
DCD DMA27_Handler ; 63: DMA 27 Handler
DCD DMA28_Handler ; 64: DMA 28 Handler
DCD DMA29_Handler ; 65: DMA 29 Handler
DCD DMA30_Handler ; 66: DMA 30 Handler
DCD DMA31_Handler ; 67: DMA 31 Handler
DCD PORT0_Handler ; 68: PORT0 Handler
DCD PORT1_Handler ; 69: PORT1 Handler
DCD PORT2_Handler ; 70: PORT2 Handler
DCD PORT0_0_Handler ; 71: GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; 72: GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; 73: GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; 74: GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; 75: GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; 76: GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; 77: GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; 78: GPIO Port 0 pin 7 Handler
DCD PORT0_8_Handler ; 79: GPIO Port 0 pin 8 Handler
DCD PORT0_9_Handler ; 80: GPIO Port 0 pin 9 Handler
DCD PORT0_10_Handler ; 81: GPIO Port 0 pin 10 Handler
DCD PORT0_11_Handler ; 82: GPIO Port 0 pin 11 Handler
DCD PORT0_12_Handler ; 83: GPIO Port 0 pin 12 Handler
DCD PORT0_13_Handler ; 84: GPIO Port 0 pin 13 Handler
DCD PORT0_14_Handler ; 85: GPIO Port 0 pin 14 Handler
DCD PORT0_15_Handler ; 86: GPIO Port 0 pin 15 Handler
DCD PORT1_0_Handler ; 87: GPIO Port 1 pin 0 Handler
DCD PORT1_1_Handler ; 88: GPIO Port 1 pin 1 Handler
DCD PORT1_2_Handler ; 89: GPIO Port 1 pin 2 Handler
DCD PORT1_3_Handler ; 90: GPIO Port 1 pin 3 Handler
DCD PORT1_4_Handler ; 91: GPIO Port 1 pin 4 Handler
DCD PORT1_5_Handler ; 92: GPIO Port 1 pin 5 Handler
DCD PORT1_6_Handler ; 93: GPIO Port 1 pin 6 Handler
DCD PORT1_7_Handler ; 94: GPIO Port 1 pin 7 Handler
DCD PORT1_8_Handler ; 95: GPIO Port 1 pin 8 Handler
DCD PORT1_9_Handler ; 96: GPIO Port 1 pin 9 Handler
DCD PORT1_10_Handler ; 97: GPIO Port 1 pin 10 Handler
DCD PORT1_11_Handler ; 98: GPIO Port 1 pin 11 Handler
DCD PORT1_12_Handler ; 99: GPIO Port 1 pin 12 Handler
DCD PORT1_13_Handler ; 100: GPIO Port 1 pin 13 Handler
DCD PORT1_14_Handler ; 101: GPIO Port 1 pin 14 Handler
DCD PORT1_15_Handler ; 102: GPIO Port 1 pin 15 Handler
DCD PORT2_0_Handler ; 103: GPIO Port 2 pin 0 Handler
DCD PORT2_1_Handler ; 104: GPIO Port 2 pin 1 Handler
DCD PORT2_2_Handler ; 105: GPIO Port 2 pin 2 Handler
DCD PORT2_3_Handler ; 106: GPIO Port 2 pin 3 Handler
DCD PORT2_4_Handler ; 107: GPIO Port 2 pin 4 Handler
DCD PORT2_5_Handler ; 108: GPIO Port 2 pin 5 Handler
DCD PORT2_6_Handler ; 109: GPIO Port 2 pin 6 Handler
DCD PORT2_7_Handler ; 110: GPIO Port 2 pin 7 Handler
DCD PORT2_8_Handler ; 111: GPIO Port 2 pin 8 Handler
DCD PORT2_9_Handler ; 112: GPIO Port 2 pin 9 Handler
DCD PORT2_10_Handler ; 113: GPIO Port 2 pin 10 Handler
DCD PORT2_11_Handler ; 114: GPIO Port 2 pin 11 Handler
DCD PORT2_12_Handler ; 115: GPIO Port 2 pin 12 Handler
DCD PORT2_13_Handler ; 116: GPIO Port 2 pin 13 Handler
DCD PORT2_14_Handler ; 117: GPIO Port 2 pin 14 Handler
DCD PORT2_15_Handler ; 118: GPIO Port 2 pin 15 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
; Default exception/interrupt handler
Default_Handler PROC
EXPORT BOR_Handler [WEAK] ; 00: Brown Out Reset Handler
EXPORT UART0_Handler [WEAK] ; 01: UART 0 Handler
EXPORT UART1_Handler [WEAK] ; 02: UART 1 Handler
EXPORT UART2_Handler [WEAK] ; 03: UART 2 Handler
EXPORT SPI0_Handler [WEAK] ; 04: SPI 0 Handler
EXPORT SPI1_Handler [WEAK] ; 05: SPI 1 Handler
EXPORT SPI2_Handler [WEAK] ; 06: SPI 2 Handler
EXPORT SPI3_Handler [WEAK] ; 07: SPI 3 Handler
EXPORT SPI4_Handler [WEAK] ; 08: SPI 4 Handler
EXPORT I2C0_Handler [WEAK] ; 09: I2C 0 Handler
EXPORT I2C1_Handler [WEAK] ; 10: I2C 1 Handler
EXPORT I2C2_Handler [WEAK] ; 11: I2C 2 Handler
EXPORT I2C3_Handler [WEAK] ; 12: I2C 3 Handler
EXPORT I2C4_Handler [WEAK] ; 13: I2C 4 Handler
EXPORT TIMER0_Handler [WEAK] ; 14: TIMER 0 Handler
EXPORT TIMER1_Handler [WEAK] ; 15: TIMER 1 Handler
EXPORT TIMER2_Handler [WEAK] ; 16: TIMER 2 Handler
EXPORT TIMER3_Handler [WEAK] ; 17: TIMER 3 Handler
EXPORT TIMER4_Handler [WEAK] ; 18: TIMER 4 Handler
EXPORT TIMER5_Handler [WEAK] ; 19: TIMER 5 Handler
EXPORT TIMER6_Handler [WEAK] ; 20: TIMER 6 Handler
EXPORT PWM_TIMER_Handler [WEAK] ; 21: PWM TIMER Handler
EXPORT DUAL_TIMER_Handler [WEAK] ; 22: Dual TIMER Handler
EXPORT AFECON_Handler [WEAK] ; 23: Analog Front End Control Handler
EXPORT SRC_Handler [WEAK] ; 24: Sample Rate Converter Handler
EXPORT DMA_ERROR_Handler [WEAK] ; 25: DMA Error Handler
EXPORT FLASH_Handler [WEAK] ; 26: FLASH Handler
EXPORT RTC0_Handler [WEAK] ; 27: Real-Time Counter 0 Handler
EXPORT RTC1_Handler [WEAK] ; 28: Real-Time Counter 1 Handler
EXPORT RTC2_Handler [WEAK] ; 29: Real-Time Counter 2 Handler
EXPORT FPU_Handler [WEAK] ; 30: Cortex-M4 Floating-point Processing Unit exceptions Handler
EXPORT SRP0_Handler [WEAK] ; 31: SRP 0 Handler
EXPORT SRP1_Handler [WEAK] ; 32: SRP 1 Handler
EXPORT DELAY_MON_Handler [WEAK] ; 33: Delay Monitor Handler
EXPORT AES_Handler [WEAK] ; 34: AES Handler
EXPORT EXT_WAKEUP_Handler [WEAK] ; 35: External Wakeup Handler
EXPORT DMA0_Handler [WEAK] ; 36: DMA 0 Handler
EXPORT DMA1_Handler [WEAK] ; 37: DMA 1 Handler
EXPORT DMA2_Handler [WEAK] ; 38: DMA 2 Handler
EXPORT DMA3_Handler [WEAK] ; 39: DMA 3 Handler
EXPORT DMA4_Handler [WEAK] ; 40: DMA 4 Handler
EXPORT DMA5_Handler [WEAK] ; 41: DMA 5 Handler
EXPORT DMA6_Handler [WEAK] ; 42: DMA 6 Handler
EXPORT DMA7_Handler [WEAK] ; 43: DMA 7 Handler
EXPORT DMA8_Handler [WEAK] ; 44: DMA 8 Handler
EXPORT DMA9_Handler [WEAK] ; 45: DMA 9 Handler
EXPORT DMA10_Handler [WEAK] ; 46: DMA 10 Handler
EXPORT DMA11_Handler [WEAK] ; 47: DMA 11 Handler
EXPORT DMA12_Handler [WEAK] ; 48: DMA 12 Handler
EXPORT DMA13_Handler [WEAK] ; 49: DMA 13 Handler
EXPORT DMA14_Handler [WEAK] ; 50: DMA 14 Handler
EXPORT DMA15_Handler [WEAK] ; 51: DMA 15 Handler
EXPORT DMA16_Handler [WEAK] ; 52: DMA 16 Handler
EXPORT DMA17_Handler [WEAK] ; 53: DMA 17 Handler
EXPORT DMA18_Handler [WEAK] ; 54: DMA 18 Handler
EXPORT DMA19_Handler [WEAK] ; 55: DMA 19 Handler
EXPORT DMA20_Handler [WEAK] ; 56: DMA 20 Handler
EXPORT DMA21_Handler [WEAK] ; 57: DMA 21 Handler
EXPORT DMA22_Handler [WEAK] ; 58: DMA 22 Handler
EXPORT DMA23_Handler [WEAK] ; 59: DMA 23 Handler
EXPORT DMA24_Handler [WEAK] ; 60: DMA 24 Handler
EXPORT DMA25_Handler [WEAK] ; 61: DMA 25 Handler
EXPORT DMA26_Handler [WEAK] ; 62: DMA 26 Handler
EXPORT DMA27_Handler [WEAK] ; 63: DMA 27 Handler
EXPORT DMA28_Handler [WEAK] ; 64: DMA 28 Handler
EXPORT DMA29_Handler [WEAK] ; 65: DMA 29 Handler
EXPORT DMA30_Handler [WEAK] ; 66: DMA 30 Handler
EXPORT DMA31_Handler [WEAK] ; 67: DMA 31 Handler
EXPORT PORT0_Handler [WEAK] ; 68: PORT0 Handler
EXPORT PORT1_Handler [WEAK] ; 69: PORT1 Handler
EXPORT PORT2_Handler [WEAK] ; 70: PORT2 Handler
EXPORT PORT0_0_Handler [WEAK] ; 71: GPIO Port 0 pin 0 Handler
EXPORT PORT0_1_Handler [WEAK] ; 72: GPIO Port 0 pin 1 Handler
EXPORT PORT0_2_Handler [WEAK] ; 73: GPIO Port 0 pin 2 Handler
EXPORT PORT0_3_Handler [WEAK] ; 74: GPIO Port 0 pin 3 Handler
EXPORT PORT0_4_Handler [WEAK] ; 75: GPIO Port 0 pin 4 Handler
EXPORT PORT0_5_Handler [WEAK] ; 76: GPIO Port 0 pin 5 Handler
EXPORT PORT0_6_Handler [WEAK] ; 77: GPIO Port 0 pin 6 Handler
EXPORT PORT0_7_Handler [WEAK] ; 78: GPIO Port 0 pin 7 Handler
EXPORT PORT0_8_Handler [WEAK] ; 79: GPIO Port 0 pin 8 Handler
EXPORT PORT0_9_Handler [WEAK] ; 80: GPIO Port 0 pin 9 Handler
EXPORT PORT0_10_Handler [WEAK] ; 81: GPIO Port 0 pin 10 Handler
EXPORT PORT0_11_Handler [WEAK] ; 82: GPIO Port 0 pin 11 Handler
EXPORT PORT0_12_Handler [WEAK] ; 83: GPIO Port 0 pin 12 Handler
EXPORT PORT0_13_Handler [WEAK] ; 84: GPIO Port 0 pin 13 Handler
EXPORT PORT0_14_Handler [WEAK] ; 85: GPIO Port 0 pin 14 Handler
EXPORT PORT0_15_Handler [WEAK] ; 86: GPIO Port 0 pin 15 Handler
EXPORT PORT1_0_Handler [WEAK] ; 87: GPIO Port 1 pin 0 Handler
EXPORT PORT1_1_Handler [WEAK] ; 88: GPIO Port 1 pin 1 Handler
EXPORT PORT1_2_Handler [WEAK] ; 89: GPIO Port 1 pin 2 Handler
EXPORT PORT1_3_Handler [WEAK] ; 90: GPIO Port 1 pin 3 Handler
EXPORT PORT1_4_Handler [WEAK] ; 91: GPIO Port 1 pin 4 Handler
EXPORT PORT1_5_Handler [WEAK] ; 92: GPIO Port 1 pin 5 Handler
EXPORT PORT1_6_Handler [WEAK] ; 93: GPIO Port 1 pin 6 Handler
EXPORT PORT1_7_Handler [WEAK] ; 94: GPIO Port 1 pin 7 Handler
EXPORT PORT1_8_Handler [WEAK] ; 95: GPIO Port 1 pin 8 Handler
EXPORT PORT1_9_Handler [WEAK] ; 96: GPIO Port 1 pin 9 Handler
EXPORT PORT1_10_Handler [WEAK] ; 97: GPIO Port 1 pin 10 Handler
EXPORT PORT1_11_Handler [WEAK] ; 98: GPIO Port 1 pin 11 Handler
EXPORT PORT1_12_Handler [WEAK] ; 99: GPIO Port 1 pin 12 Handler
EXPORT PORT1_13_Handler [WEAK] ; 100: GPIO Port 1 pin 13 Handler
EXPORT PORT1_14_Handler [WEAK] ; 101: GPIO Port 1 pin 14 Handler
EXPORT PORT1_15_Handler [WEAK] ; 102: GPIO Port 1 pin 15 Handler
EXPORT PORT2_0_Handler [WEAK] ; 103: GPIO Port 2 pin 0 Handler
EXPORT PORT2_1_Handler [WEAK] ; 104: GPIO Port 2 pin 1 Handler
EXPORT PORT2_2_Handler [WEAK] ; 105: GPIO Port 2 pin 2 Handler
EXPORT PORT2_3_Handler [WEAK] ; 106: GPIO Port 2 pin 3 Handler
EXPORT PORT2_4_Handler [WEAK] ; 107: GPIO Port 2 pin 4 Handler
EXPORT PORT2_5_Handler [WEAK] ; 108: GPIO Port 2 pin 5 Handler
EXPORT PORT2_6_Handler [WEAK] ; 109: GPIO Port 2 pin 6 Handler
EXPORT PORT2_7_Handler [WEAK] ; 110: GPIO Port 2 pin 7 Handler
EXPORT PORT2_8_Handler [WEAK] ; 111: GPIO Port 2 pin 8 Handler
EXPORT PORT2_9_Handler [WEAK] ; 112: GPIO Port 2 pin 9 Handler
EXPORT PORT2_10_Handler [WEAK] ; 113: GPIO Port 2 pin 10 Handler
EXPORT PORT2_11_Handler [WEAK] ; 114: GPIO Port 2 pin 11 Handler
EXPORT PORT2_12_Handler [WEAK] ; 115: GPIO Port 2 pin 12 Handler
EXPORT PORT2_13_Handler [WEAK] ; 116: GPIO Port 2 pin 13 Handler
EXPORT PORT2_14_Handler [WEAK] ; 117: GPIO Port 2 pin 14 Handler
EXPORT PORT2_15_Handler [WEAK] ; 118: GPIO Port 2 pin 15 Handler
BOR_Handler
UART0_Handler
UART1_Handler
UART2_Handler
SPI0_Handler
SPI1_Handler
SPI2_Handler
SPI3_Handler
SPI4_Handler
I2C0_Handler
I2C1_Handler
I2C2_Handler
I2C3_Handler
I2C4_Handler
TIMER0_Handler
TIMER1_Handler
TIMER2_Handler
TIMER3_Handler
TIMER4_Handler
TIMER5_Handler
TIMER6_Handler
PWM_TIMER_Handler
DUAL_TIMER_Handler
AFECON_Handler
SRC_Handler
DMA_ERROR_Handler
FLASH_Handler
RTC0_Handler
RTC1_Handler
RTC2_Handler
FPU_Handler
SRP0_Handler
SRP1_Handler
DELAY_MON_Handler
AES_Handler
EXT_WAKEUP_Handler
DMA0_Handler
DMA1_Handler
DMA2_Handler
DMA3_Handler
DMA4_Handler
DMA5_Handler
DMA6_Handler
DMA7_Handler
DMA8_Handler
DMA9_Handler
DMA10_Handler
DMA11_Handler
DMA12_Handler
DMA13_Handler
DMA14_Handler
DMA15_Handler
DMA16_Handler
DMA17_Handler
DMA18_Handler
DMA19_Handler
DMA20_Handler
DMA21_Handler
DMA22_Handler
DMA23_Handler
DMA24_Handler
DMA25_Handler
DMA26_Handler
DMA27_Handler
DMA28_Handler
DMA29_Handler
DMA30_Handler
DMA31_Handler
PORT0_Handler
PORT1_Handler
PORT2_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT0_8_Handler
PORT0_9_Handler
PORT0_10_Handler
PORT0_11_Handler
PORT0_12_Handler
PORT0_13_Handler
PORT0_14_Handler
PORT0_15_Handler
PORT1_0_Handler
PORT1_1_Handler
PORT1_2_Handler
PORT1_3_Handler
PORT1_4_Handler
PORT1_5_Handler
PORT1_6_Handler
PORT1_7_Handler
PORT1_8_Handler
PORT1_9_Handler
PORT1_10_Handler
PORT1_11_Handler
PORT1_12_Handler
PORT1_13_Handler
PORT1_14_Handler
PORT1_15_Handler
PORT2_0_Handler
PORT2_1_Handler
PORT2_2_Handler
PORT2_3_Handler
PORT2_4_Handler
PORT2_5_Handler
PORT2_6_Handler
PORT2_7_Handler
PORT2_8_Handler
PORT2_9_Handler
PORT2_10_Handler
PORT2_11_Handler
PORT2_12_Handler
PORT2_13_Handler
PORT2_14_Handler
PORT2_15_Handler
B .
ENDP
ALIGN
END

223
targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/TOOLCHAIN_GCC_ARM/s1sbp6a.ld Normal file
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@ -0,0 +1,223 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2020 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/* Linker script to configure memory regions. */
#include "../memory_zones.h"
#include "../cmsis_nvic.h"
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = NVIC_NUM_VECTORS * 4;
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vectors))
. = ALIGN(4);
} > FLASH
.text :
{
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.interrupts_ram :
{
_ram_vectors = ABSOLUTE(.);
. = ORIGIN(RAM) + NVIC_VECTORS_SIZE;
. = ALIGN(4);
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.heap : {
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
} /* End of sections */

387
targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/TOOLCHAIN_GCC_ARM/startup_s1sbp6a.S Normal file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2020 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
;/****************************************************************************
; *
; * Copyright 2020 Samsung Electronics All Rights Reserved.
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing,
; * software distributed under the License is distributed on an
; * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
; * either express or implied. See the License for the specific
; * language governing permissions and limitations under the License.
; *
; ****************************************************************************/
/************************************************************************************
* Version: GCC for ARM Embedded Processors
************************************************************************************/
.syntax unified
.arch armv7-m
/************************************************************************************
* Vectors
************************************************************************************/
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long BOR_Handler /* 00: Brown Out Reset Handler */
.long UART0_Handler /* 01: UART 0 Handler */
.long UART1_Handler /* 02: UART 1 Handler */
.long UART2_Handler /* 03: UART 2 Handler */
.long SPI0_Handler /* 04: SPI 0 Handler */
.long SPI1_Handler /* 05: SPI 1 Handler */
.long SPI2_Handler /* 06: SPI 2 Handler */
.long SPI3_Handler /* 07: SPI 3 Handler */
.long SPI4_Handler /* 08: SPI 4 Handler */
.long I2C0_Handler /* 09: I2C 0 Handler */
.long I2C1_Handler /* 10: I2C 1 Handler */
.long I2C2_Handler /* 11: I2C 2 Handler */
.long I2C3_Handler /* 12: I2C 3 Handler */
.long I2C4_Handler /* 13: I2C 4 Handler */
.long TIMER0_Handler /* 14: TIMER 0 Handler */
.long TIMER1_Handler /* 15: TIMER 1 Handler */
.long TIMER2_Handler /* 16: TIMER 2 Handler */
.long TIMER3_Handler /* 17: TIMER 3 Handler */
.long TIMER4_Handler /* 18: TIMER 4 Handler */
.long TIMER5_Handler /* 19: TIMER 5 Handler */
.long TIMER6_Handler /* 20: TIMER 6 Handler */
.long PWM_TIMER_Handler /* 21: PWM TIMER Handler */
.long DUAL_TIMER_Handler /* 22: Dual TIMER Handler */
.long AFECON_Handler /* 23: Analog Front End Control Handler */
.long SRC_Handler /* 24: Sample Rate Converter Handler */
.long DMA_ERROR_Handler /* 25: DMA Error Handler */
.long FLASH_Handler /* 26: FLASH Handler */
.long RTC0_Handler /* 27: Real-Time Counter 0 Handler */
.long RTC1_Handler /* 28: Real-Time Counter 1 Handler */
.long RTC2_Handler /* 29: Real-Time Counter 2 Handler */
.long FPU_Handler /* 30: Cortex-M4 Floating-point Processing Unit exceptions Handler */
.long SRP0_Handler /* 31: SRP 0 Handler */
.long SRP1_Handler /* 32: SRP 1 Handler */
.long DELAY_MON_Handler /* 33: Delay Monitor Handler */
.long AES_Handler /* 34: AES Handler */
.long EXT_WAKEUP_Handler /* 35: External Wakeup Handler */
.long DMA0_Handler /* 36: DMA 0 Handler */
.long DMA1_Handler /* 37: DMA 1 Handler */
.long DMA2_Handler /* 38: DMA 2 Handler */
.long DMA3_Handler /* 39: DMA 3 Handler */
.long DMA4_Handler /* 40: DMA 4 Handler */
.long DMA5_Handler /* 41: DMA 5 Handler */
.long DMA6_Handler /* 42: DMA 6 Handler */
.long DMA7_Handler /* 43: DMA 7 Handler */
.long DMA8_Handler /* 44: DMA 8 Handler */
.long DMA9_Handler /* 45: DMA 9 Handler */
.long DMA10_Handler /* 46: DMA 10 Handler */
.long DMA11_Handler /* 47: DMA 11 Handler */
.long DMA12_Handler /* 48: DMA 12 Handler */
.long DMA13_Handler /* 49: DMA 13 Handler */
.long DMA14_Handler /* 50: DMA 14 Handler */
.long DMA15_Handler /* 51: DMA 15 Handler */
.long DMA16_Handler /* 52: DMA 16 Handler */
.long DMA17_Handler /* 53: DMA 17 Handler */
.long DMA18_Handler /* 54: DMA 18 Handler */
.long DMA19_Handler /* 55: DMA 19 Handler */
.long DMA20_Handler /* 56: DMA 20 Handler */
.long DMA21_Handler /* 57: DMA 21 Handler */
.long DMA22_Handler /* 58: DMA 22 Handler */
.long DMA23_Handler /* 59: DMA 23 Handler */
.long DMA24_Handler /* 60: DMA 24 Handler */
.long DMA25_Handler /* 61: DMA 25 Handler */
.long DMA26_Handler /* 62: DMA 26 Handler */
.long DMA27_Handler /* 63: DMA 27 Handler */
.long DMA28_Handler /* 64: DMA 28 Handler */
.long DMA29_Handler /* 65: DMA 29 Handler */
.long DMA30_Handler /* 66: DMA 30 Handler */
.long DMA31_Handler /* 67: DMA 31 Handler */
.long PORT0_Handler /* 68: PORT0 Handler */
.long PORT1_Handler /* 69: PORT1 Handler */
.long PORT2_Handler /* 70: PORT2 Handler */
.long PORT0_0_Handler /* 71: GPIO Port 0 pin 0 Handler */
.long PORT0_1_Handler /* 72: GPIO Port 0 pin 1 Handler */
.long PORT0_2_Handler /* 73: GPIO Port 0 pin 2 Handler */
.long PORT0_3_Handler /* 74: GPIO Port 0 pin 3 Handler */
.long PORT0_4_Handler /* 75: GPIO Port 0 pin 4 Handler */
.long PORT0_5_Handler /* 76: GPIO Port 0 pin 5 Handler */
.long PORT0_6_Handler /* 77: GPIO Port 0 pin 6 Handler */
.long PORT0_7_Handler /* 78: GPIO Port 0 pin 7 Handler */
.long PORT0_8_Handler /* 79: GPIO Port 0 pin 8 Handler */
.long PORT0_9_Handler /* 80: GPIO Port 0 pin 9 Handler */
.long PORT0_10_Handler /* 81: GPIO Port 0 pin 10 Handler */
.long PORT0_11_Handler /* 82: GPIO Port 0 pin 11 Handler */
.long PORT0_12_Handler /* 83: GPIO Port 0 pin 12 Handler */
.long PORT0_13_Handler /* 84: GPIO Port 0 pin 13 Handler */
.long PORT0_14_Handler /* 85: GPIO Port 0 pin 14 Handler */
.long PORT0_15_Handler /* 86: GPIO Port 0 pin 15 Handler */
.long PORT1_0_Handler /* 87: GPIO Port 1 pin 0 Handler */
.long PORT1_1_Handler /* 88: GPIO Port 1 pin 1 Handler */
.long PORT1_2_Handler /* 89: GPIO Port 1 pin 2 Handler */
.long PORT1_3_Handler /* 90: GPIO Port 1 pin 3 Handler */
.long PORT1_4_Handler /* 91: GPIO Port 1 pin 4 Handler */
.long PORT1_5_Handler /* 92: GPIO Port 1 pin 5 Handler */
.long PORT1_6_Handler /* 93: GPIO Port 1 pin 6 Handler */
.long PORT1_7_Handler /* 94: GPIO Port 1 pin 7 Handler */
.long PORT1_8_Handler /* 95: GPIO Port 1 pin 8 Handler */
.long PORT1_9_Handler /* 96: GPIO Port 1 pin 9 Handler */
.long PORT1_10_Handler /* 97: GPIO Port 1 pin 10 Handler */
.long PORT1_11_Handler /* 98: GPIO Port 1 pin 11 Handler */
.long PORT1_12_Handler /* 99: GPIO Port 1 pin 12 Handler */
.long PORT1_13_Handler /* 100: GPIO Port 1 pin 13 Handler */
.long PORT1_14_Handler /* 101: GPIO Port 1 pin 14 Handler */
.long PORT1_15_Handler /* 102: GPIO Port 1 pin 15 Handler */
.long PORT2_0_Handler /* 103: GPIO Port 2 pin 0 Handler */
.long PORT2_1_Handler /* 104: GPIO Port 2 pin 1 Handler */
.long PORT2_2_Handler /* 105: GPIO Port 2 pin 2 Handler */
.long PORT2_3_Handler /* 106: GPIO Port 2 pin 3 Handler */
.long PORT2_4_Handler /* 107: GPIO Port 2 pin 4 Handler */
.long PORT2_5_Handler /* 108: GPIO Port 2 pin 5 Handler */
.long PORT2_6_Handler /* 109: GPIO Port 2 pin 6 Handler */
.long PORT2_7_Handler /* 110: GPIO Port 2 pin 7 Handler */
.long PORT2_8_Handler /* 111: GPIO Port 2 pin 8 Handler */
.long PORT2_9_Handler /* 112: GPIO Port 2 pin 9 Handler */
.long PORT2_10_Handler /* 113: GPIO Port 2 pin 10 Handler */
.long PORT2_11_Handler /* 114: GPIO Port 2 pin 11 Handler */
.long PORT2_12_Handler /* 115: GPIO Port 2 pin 12 Handler */
.long PORT2_13_Handler /* 116: GPIO Port 2 pin 13 Handler */
.long PORT2_14_Handler /* 117: GPIO Port 2 pin 14 Handler */
.long PORT2_15_Handler /* 118: GPIO Port 2 pin 15 Handler */
.size __Vectors, . - __Vectors
/************************************************************************************
* text
************************************************************************************/
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, 0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
/* Initialize .bss */
init_bss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
ldr r3, =bss_size
cmp r3, #0
beq system_startup
mov r4, #0
zero:
strb r4, [r1], #1
subs r3, r3, #1
bne zero
system_startup:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Function to define default IRQ handler*/
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b Default_Handler
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
/* IRQ Handlers */
def_irq_handler BOR_Handler
def_irq_handler UART0_Handler
def_irq_handler UART1_Handler
def_irq_handler UART2_Handler
def_irq_handler SPI0_Handler
def_irq_handler SPI1_Handler
def_irq_handler SPI2_Handler
def_irq_handler SPI3_Handler
def_irq_handler SPI4_Handler
def_irq_handler I2C0_Handler
def_irq_handler I2C1_Handler
def_irq_handler I2C2_Handler
def_irq_handler I2C3_Handler
def_irq_handler I2C4_Handler
def_irq_handler TIMER0_Handler
def_irq_handler TIMER1_Handler
def_irq_handler TIMER2_Handler
def_irq_handler TIMER3_Handler
def_irq_handler TIMER4_Handler
def_irq_handler TIMER5_Handler
def_irq_handler TIMER6_Handler
def_irq_handler PWM_TIMER_Handler
def_irq_handler DUAL_TIMER_Handler
def_irq_handler AFECON_Handler
def_irq_handler SRC_Handler
def_irq_handler DMA_ERROR_Handler
def_irq_handler FLASH_Handler
def_irq_handler RTC0_Handler
def_irq_handler RTC1_Handler
def_irq_handler RTC2_Handler
def_irq_handler FPU_Handler
def_irq_handler SRP0_Handler
def_irq_handler SRP1_Handler
def_irq_handler DELAY_MON_Handler
def_irq_handler AES_Handler
def_irq_handler EXT_WAKEUP_Handler
def_irq_handler DMA0_Handler
def_irq_handler DMA1_Handler
def_irq_handler DMA2_Handler
def_irq_handler DMA3_Handler
def_irq_handler DMA4_Handler
def_irq_handler DMA5_Handler
def_irq_handler DMA6_Handler
def_irq_handler DMA7_Handler
def_irq_handler DMA8_Handler
def_irq_handler DMA9_Handler
def_irq_handler DMA10_Handler
def_irq_handler DMA11_Handler
def_irq_handler DMA12_Handler
def_irq_handler DMA13_Handler
def_irq_handler DMA14_Handler
def_irq_handler DMA15_Handler
def_irq_handler DMA16_Handler
def_irq_handler DMA17_Handler
def_irq_handler DMA18_Handler
def_irq_handler DMA19_Handler
def_irq_handler DMA20_Handler
def_irq_handler DMA21_Handler
def_irq_handler DMA22_Handler
def_irq_handler DMA23_Handler
def_irq_handler DMA24_Handler
def_irq_handler DMA25_Handler
def_irq_handler DMA26_Handler
def_irq_handler DMA27_Handler
def_irq_handler DMA28_Handler
def_irq_handler DMA29_Handler
def_irq_handler DMA30_Handler
def_irq_handler DMA31_Handler
def_irq_handler PORT0_Handler
def_irq_handler PORT1_Handler
def_irq_handler PORT2_Handler
def_irq_handler PORT0_0_Handler
def_irq_handler PORT0_1_Handler
def_irq_handler PORT0_2_Handler
def_irq_handler PORT0_3_Handler
def_irq_handler PORT0_4_Handler
def_irq_handler PORT0_5_Handler
def_irq_handler PORT0_6_Handler
def_irq_handler PORT0_7_Handler
def_irq_handler PORT0_8_Handler
def_irq_handler PORT0_9_Handler
def_irq_handler PORT0_10_Handler
def_irq_handler PORT0_11_Handler
def_irq_handler PORT0_12_Handler
def_irq_handler PORT0_13_Handler
def_irq_handler PORT0_14_Handler
def_irq_handler PORT0_15_Handler
def_irq_handler PORT1_0_Handler
def_irq_handler PORT1_1_Handler
def_irq_handler PORT1_2_Handler
def_irq_handler PORT1_3_Handler
def_irq_handler PORT1_4_Handler
def_irq_handler PORT1_5_Handler
def_irq_handler PORT1_6_Handler
def_irq_handler PORT1_7_Handler
def_irq_handler PORT1_8_Handler
def_irq_handler PORT1_9_Handler
def_irq_handler PORT1_10_Handler
def_irq_handler PORT1_11_Handler
def_irq_handler PORT1_12_Handler
def_irq_handler PORT1_13_Handler
def_irq_handler PORT1_14_Handler
def_irq_handler PORT1_15_Handler
def_irq_handler PORT2_0_Handler
def_irq_handler PORT2_1_Handler
def_irq_handler PORT2_2_Handler
def_irq_handler PORT2_3_Handler
def_irq_handler PORT2_4_Handler
def_irq_handler PORT2_5_Handler
def_irq_handler PORT2_6_Handler
def_irq_handler PORT2_7_Handler
def_irq_handler PORT2_8_Handler
def_irq_handler PORT2_9_Handler
def_irq_handler PORT2_10_Handler
def_irq_handler PORT2_11_Handler
def_irq_handler PORT2_12_Handler
def_irq_handler PORT2_13_Handler
def_irq_handler PORT2_14_Handler
def_irq_handler PORT2_15_Handler
.end

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/cmsis.h Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include "s1sbp6a.h"
#include "s1sbp6a_type.h"
#include "cmsis_nvic.h"
#include "s1sbp6a_type.h"
#include "s1sbp6a_cmu.h"
#include "s1sbp6a_pmu.h"
#include "s1sbp6a_uart.h"
#include "s1sbp6a_gpio.h"
#include "s1sbp6a_spi.h"
#include "s1sbp6a_i2c.h"
#include "s1sbp6a_rtc.h"
#include "s1sbp6a_flash.h"
#include "s1sbp6a_wdog.h"
#include "s1sp6a_dual_timer.h"
#endif

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/cmsis_nvic.h Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "memory_zones.h"
#define NVIC_NUM_VECTORS (16 + 119)
#define NVIC_RAM_VECTOR_ADDRESS (MBED_RAM_START) // Location of vectors in RAM
#define NVIC_VECTORS_SIZE (NVIC_NUM_VECTORS * 4)
#endif

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/*
* This file contains the information of memory zones for code and data on
* ARM Versatile Express Cortex-M Prototyping Systems (V2M-MPS2) TRM.
* It is used in startup code and linker scripts of supported compilers (ARM and
* GCC_ARM).
*
* WARNING: IAR does not include this file and re-define these values in
* MPS2.icf file. Please make sure that the two files share the same values.
*
* These memory zones are defined in section 4.2 of ARM V2M-MPS2 RTL and
* Fast Model Reference Guide.
*/
#ifndef MEMORY_ZONES_H
#define MEMORY_ZONES_H
/*
* Code memory zones
* Please note that MPS2 on Fast Models do not implemented persistent flash memory.
* The FLASH memory can be simulated via 4MB ZBT_SRAM1 block
* only to keep the same name than in the CMSDK RTL and Fast Models Reference
* Guide.
*/
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x0000000
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x200000 // 2MB KB
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x40000 // 256 KB
#endif
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x0080000 //512K
#endif
#endif /* MEMORY_ZONES_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_H
#define __S1SBP6A_H
typedef enum IRQn {
/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
/* --------------------- S5JS100 Specific Interrupt Numbers ---------------- */
BOR_IRQn = 0, /*!< Brown Out Reset Interrupt */
UARTR0_IRQn = 1, /*!< UART 0 Interrupt */
UARTR1_IRQn = 2, /*!< UART 1 Interrupt */
UARTR2_IRQn = 3, /*!< UART 2 Interrupt */
SPI0_IRQn = 4, /*!< SPI 0 Interrupt */
SPI1_IRQn = 5, /*!< SPI 1 Interrupt */
SPI2_IRQn = 6, /*!< SPI 2 Interrupt */
SPI3_IRQn = 7, /*!< SPI 3 Interrupt */
SPI4_IRQn = 8, /*!< SPI 4 Interrupt */
I2C0_IRQn = 9, /*!< I2C 0 Interrupt */
I2C1_IRQn = 10, /*!< I2C 1 Interrupt */
I2C2_IRQn = 11, /*!< I2C 2 Interrupt */
I2C3_IRQn = 12, /*!< I2C 3 Interrupt */
I2C4_IRQn = 13, /*!< I2C 4 Interrupt */
TIMER0_IRQn = 14, /*!< TIMER 0 Interrupt */
TIMER1_IRQn = 15, /*!< TIMER 1 Interrupt */
TIMER2_IRQn = 16, /*!< TIMER 2 Interrupt */
TIMER3_IRQn = 17, /*!< TIMER 3 Interrupt */
TIMER4_IRQn = 18, /*!< TIMER 4 Interrupt */
TIMER5_IRQn = 19, /*!< TIMER 5 Interrupt */
TIMER6_IRQn = 20, /*!< TIMER 6 Interrupt */
PWM_TIMER_IRQn = 21, /*!< PWM TIMER Interrupt */
DUAL_TIMER_IRQn = 22, /*!< Dual Timer Interrupt */
AFECON_IRQn = 23, /*!< Analog Front End Control Interrupt */
SRC_IRQn = 24, /*!< Sample Rate Converter Interrupt */
DMA_ERROR_IRQn = 25, /*!< DMA Error Interrupt */
FLASH_IRQn = 26, /*!< FLASH Interrupt */
RTC0_IRQn = 27, /*!< Real-Time Counter 0 Interrupt */
RTC1_IRQn = 28, /*!< Real-Time Counter 1 Interrupt */
RTC2_IRQn = 29, /*!< Real-Time Counter 2 Interrupt */
FPU_IRQn = 30, /*!< Floating-point Processing Unit Interrupt */
SRP0_IRQn = 31, /*!< SRP 0 Interrupt */
SRP1_IRQn = 32, /*!< SRP 1 Interrupt */
DELAY_MON_IRQn = 33, /*!< Delay Monitor Interrupt */
AES_IRQn = 34, /*!< AES Interrupt */
EXT_WAKEUP_IRQn = 35, /*!< External Wakeup Interrupt */
DMA0_IRQn = 36, /*!< DMA Channel 0 Done Interrupt */
DMA1_IRQn = 37, /*!< DMA Channel 1 Done Interrupt */
DMA2_IRQn = 38, /*!< DMA Channel 2 Done Interrupt */
DMA3_IRQn = 39, /*!< DMA Channel 3 Done Interrupt */
DMA4_IRQn = 40, /*!< DMA Channel 4 Done Interrupt */
DMA5_IRQn = 41, /*!< DMA Channel 5 Done Interrupt */
DMA6_IRQn = 42, /*!< DMA Channel 6 Done Interrupt */
DMA7_IRQn = 43, /*!< DMA Channel 7 Done Interrupt */
DMA8_IRQn = 44, /*!< DMA Channel 8 Done Interrupt */
DMA9_IRQn = 45, /*!< DMA Channel 9 Done Interrupt */
DMA10_IRQn = 46, /*!< DMA Channel 10 Done Interrupt */
DMA11_IRQn = 47, /*!< DMA Channel 11 Done Interrupt */
DMA12_IRQn = 48, /*!< DMA Channel 12 Done Interrupt */
DMA13_IRQn = 49, /*!< DMA Channel 13 Done Interrupt */
DMA14_IRQn = 50, /*!< DMA Channel 14 Done Interrupt */
DMA15_IRQn = 51, /*!< DMA Channel 15 Done Interrupt */
DMA16_IRQn = 52, /*!< DMA Channel 16 Done Interrupt */
DMA17_IRQn = 53, /*!< DMA Channel 17 Done Interrupt */
DMA18_IRQn = 54, /*!< DMA Channel 18 Done Interrupt */
DMA19_IRQn = 55, /*!< DMA Channel 19 Done Interrupt */
DMA20_IRQn = 56, /*!< DMA Channel 20 Done Interrupt */
DMA21_IRQn = 57, /*!< DMA Channel 21 Done Interrupt */
DMA22_IRQn = 58, /*!< DMA Channel 22 Done Interrupt */
DMA23_IRQn = 59, /*!< DMA Channel 23 Done Interrupt */
DMA24_IRQn = 60, /*!< DMA Channel 24 Done Interrupt */
DMA25_IRQn = 61, /*!< DMA Channel 25 Done Interrupt */
DMA26_IRQn = 62, /*!< DMA Channel 26 Done Interrupt */
DMA27_IRQn = 63, /*!< DMA Channel 27 Done Interrupt */
DMA28_IRQn = 64, /*!< DMA Channel 28 Done Interrupt */
DMA29_IRQn = 65, /*!< DMA Channel 29 Done Interrupt */
DMA30_IRQn = 66, /*!< DMA Channel 30 Done Interrupt */
DMA31_IRQn = 67, /*!< DMA Channel 31 Done Interrupt */
PORT0_ALL_IRQn = 68, /*!< Port 0 Combined Interrupt */
PORT1_ALL_IRQn = 69, /*!< Port 1 Combined Interrupt */
PORT2_ALL_IRQn = 70, /*!< Port 2 Combined Interrupt */
PORT0_0_IRQn = 71, /*!< All P0 I/O pins can be used as interrupt source. */
PORT0_1_IRQn = 72, /*!< There are 16 pins in total */
PORT0_2_IRQn = 73,
PORT0_3_IRQn = 74,
PORT0_4_IRQn = 75,
PORT0_5_IRQn = 76,
PORT0_6_IRQn = 77,
PORT0_7_IRQn = 78,
PORT0_8_IRQn = 79,
PORT0_9_IRQn = 80,
PORT0_10_IRQn = 81,
PORT0_11_IRQn = 82,
PORT0_12_IRQn = 83,
PORT0_13_IRQn = 84,
PORT0_14_IRQn = 85,
PORT0_15_IRQn = 86,
PORT1_0_IRQn = 87, /*!< All P1 I/O pins can be used as interrupt source. */
PORT1_1_IRQn = 88, /*!< There are 16 pins in total */
PORT1_2_IRQn = 89,
PORT1_3_IRQn = 90,
PORT1_4_IRQn = 91,
PORT1_5_IRQn = 92,
PORT1_6_IRQn = 93,
PORT1_7_IRQn = 94,
PORT1_8_IRQn = 95,
PORT1_9_IRQn = 96,
PORT1_10_IRQn = 97,
PORT1_11_IRQn = 98,
PORT1_12_IRQn = 99,
PORT1_13_IRQn = 100,
PORT1_14_IRQn = 101,
PORT1_15_IRQn = 102,
PORT2_0_IRQn = 103, /*!< All P2 I/O pins can be used as interrupt source. */
PORT2_1_IRQn = 104, /*!< There are 16 pins in total */
PORT2_2_IRQn = 105,
PORT2_3_IRQn = 106,
PORT2_4_IRQn = 107,
PORT2_5_IRQn = 108,
PORT2_6_IRQn = 109,
PORT2_7_IRQn = 110,
PORT2_8_IRQn = 111,
PORT2_9_IRQn = 112,
PORT2_10_IRQn = 113,
PORT2_11_IRQn = 114,
PORT2_12_IRQn = 115,
PORT2_13_IRQn = 116,
PORT2_14_IRQn = 117,
PORT2_15_IRQn = 118,
NUM_OF_IRQn = 119 /* Number of IRQs */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M4 Processor and Core Peripherals */
#define __CM4_REV 0x0001U /*!< Core Revision r0p1 */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __FPU_PRESENT 1 /*!< FPU present or not */
#include <core_cm4.h> /* Cortex-M4 processor and core peripherals */
#include "system_s1sbp6a.h" /* S1SBP6A System include file */
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*---------- Timer (TIMER) ---------------------------------------------------*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 Control Register */
__IOM uint32_t VALUE; /*!< Offset: 0x004 Current Value Register */
__IOM uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register */
union {
__IM uint32_t INTSTAT; /*!< Offset: 0x00C Interrupt Status Register */
__OM uint32_t INTCLR; /*!< Offset: 0x00C Interrupt Clear Register */
};
} BP_TIMER_TypeDef;
/*---------- PWM Timer (PWM_TIMER) -------------------------------------------*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 Control Register */
__IOM uint32_t VALUE; /*!< Offset: 0x004 Current Value Register */
__IOM uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register */
union {
__IM uint32_t INTSTAT; /*!< Offset: 0x00C Interrupt Status Register */
__OM uint32_t INTCLR; /*!< Offset: 0x00C Interrupt Clear Register */
};
uint32_t RESERVED[764];
__IOM uint32_t PWM_CTRL; /*!< Offset: 0xC00 PWM Control Register */
__IOM uint32_t PWM_PULSE; /*!< Offset: 0xC04 PWM Pulse Set Register */
} BP_PWM_TIMER_TypeDef;
/*---------- Dual Input Timer (DUAL_TIMER) -----------------------------------*/
typedef struct {
__IOM uint32_t LOAD; /*!< Offset: 0x000 Timer Load Value Register */
__IM uint32_t VALUE; /*!< Offset: 0x004 Timer Current Value Register */
__IOM uint32_t CTRL; /*!< Offset: 0x008 Timer Control Register */
__OM uint32_t INTCLR; /*!< Offset: 0x00C Timer Interrupt Clear Register */
__IM uint32_t RIS; /*!< Offset: 0x010 Timer Raw Interrupt Status Register */
__IM uint32_t MIS; /*!< Offset: 0x014 Timer Masked Interrupt Status Register */
__IOM uint32_t BGLOAD; /*!< Offset: 0x018 Timer Background Load Register */
} BP_DUAL_TIMER_TypeDef;
/*@}*/ /* end of group BP_DUAL_TIMER */
/*---------- Watchdog (WATCHDOG) ---------------------------------------------*/
typedef struct {
__IOM uint32_t LOAD; /*!< Offset: 0x000 Load Register */
__IM uint32_t VALUE; /*!< Offset: 0x004 Value Register */
__IOM uint32_t CTRL; /*!< Offset: 0x008 Control Register */
__OM uint32_t INTCLR; /*!< Offset: 0x00C Clear Interrupt Register */
__IM uint32_t RIS; /*!< Offset: 0x010 Raw Interrupt Status Register */
__IM uint32_t MIS; /*!< Offset: 0x014 Masked Interrupt Status Register */
uint32_t RESERVED[762];
__IOM uint32_t LOCK; /*!< Offset: 0xC00 Lock Register */
} BP_WATCHDOG_TypeDef;
/*---------- Universal Asynchronous Receiver Transmitter (UART) --------------*/
typedef struct {
__IOM uint32_t ULCON; /*!< Offset: 0x000 Line Control Register */
__IOM uint32_t UCON; /*!< Offset: 0x004 Control Register */
__IOM uint32_t UFCON; /*!< Offset: 0x008 FIFO Control Register */
__IOM uint32_t UMCON; /*!< Offset: 0x00C AFC Control Register */
__IOM uint32_t UTRSTAT; /*!< Offset: 0x010 Tx/Rx Status Register */
__IM uint32_t UERSTAT; /*!< Offset: 0x014 Rx Error Register */
__IM uint32_t UFSTAT; /*!< Offset: 0x018 FIFO Status Register */
uint32_t RESERVED;
__OM uint32_t UTXH; /*!< Offset: 0x020 Transmit Data Register */
__IM uint32_t URXH; /*!< Offset: 0x024 Receive Data Register */
__IOM uint32_t UBRDIV; /*!< Offset: 0x028 Baud Rate Division Value Register */
__IOM uint32_t UFRACVAL; /*!< Offset: 0x02C Baud Rate Fractional Part Value Register */
__IOM uint32_t UINTP; /*!< Offset: 0x030 Interrupt Pending Register */
__IM uint32_t UINTS; /*!< Offset: 0x034 Interrupt Source Register */
__IOM uint32_t UINTM; /*!< Offset: 0x038 Interrupt Mask Register */
} BP_UART_TypeDef;
/*---------- Serial Peripheral Interface (SPI) -------------------------------*/
typedef struct {
__IOM uint32_t CR0; /*!< Offset: 0x000 Control Register 0 */
__IOM uint32_t CR1; /*!< Offset: 0x004 Control Register 1 */
__IOM uint32_t DR; /*!< Offset: 0x008 Data Register */
__IM uint32_t SR; /*!< Offset: 0x00C Status Register */
__IOM uint32_t CPSR; /*!< Offset: 0x010 Clock Pre-scale Register */
__IOM uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register */
__IM uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register */
__IM uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register */
__OM uint32_t ICR; /*!< Offset: 0x020 Interrupt Clear Register */
__IOM uint32_t DMACR; /*!< Offset: 0x024 DMA Control Register */
} BP_SPI_TypeDef;
/*---------- Inter-Integrated Circuit (I2C) ----------------------------------*/
typedef struct {
__IOM uint32_t CTL; /*!< Offset: 0x000 Control register */
__OM uint32_t FIFO_CTL; /*!< Offset: 0x004 FIFO Control Register */
__IOM uint32_t TRAILING_CTL; /*!< Offset: 0x008 Trailing Bytes Control Register */
uint32_t RESERVED1[5];
__IOM uint32_t INT_EN; /*!< Offset: 0x020 Interrupt Enable Register */
__IOM uint32_t INT_STAT; /*!< Offset: 0x024 Interrupt Status Register */
uint32_t RESERVED2[2];
__IM uint32_t FIFO_STAT; /*!< Offset: 0x030 FIFO Status Register */
__OM uint32_t TXDATA; /*!< Offset: 0x034 Transmit Data Buffer Register */
__IM uint32_t RXDATA; /*!< Offset: 0x038 Received Data Buffer Register */
uint32_t RESERVED3;
__IOM uint32_t CONF; /*!< Offset: 0x040 Configuration Register */
__IOM uint32_t AUTO_CONF; /*!< Offset: 0x044 Configuration Register for Auto Mode */
__IOM uint32_t TIMEOUT; /*!< Offset: 0x048 Time Out Register for I2C Master */
__IOM uint32_t MANUAL_CMD; /*!< Offset: 0x04C Command Register for Manual Mode */
__IM uint32_t TRANS_STATUS; /*!< Offset: 0x050 Transfer Status Register */
__IOM uint32_t TIMING_HS1; /*!< Offset: 0x054 Timing Register1 for High Speed Mode */
__IOM uint32_t TIMING_HS2; /*!< Offset: 0x058 Timing Register2 for High Speed Mode */
__IOM uint32_t TIMING_HS3; /*!< Offset: 0x05C Timing Register3 for High Speed Mode */
__IOM uint32_t TIMING_FS1; /*!< Offset: 0x060 Timing Register1 for Fast Speed Mode */
__IOM uint32_t TIMING_FS2; /*!< Offset: 0x064 Timing Register2 for Fast Speed Mode */
__IOM uint32_t TIMING_FS3; /*!< Offset: 0x068 Timing Register3 for Fast Speed Mode */
__IOM uint32_t TIMING_SLA; /*!< Offset: 0x06C Data Hold Timing Register for I2C Slave */
__IOM uint32_t ADDR; /*!< Offset: 0x070 Address Register */
} BP_I2C_TypeDef;
/*---------- Delay Monitor ---------------------------------------------------*/
typedef struct {
__IOM uint32_t CFG; /*!< Offset: 0x000 Configuration Register */
__IOM uint32_t CHAINSEL_MCU; /*!< Offset: 0x004 Chain Selection Register for MCU */
__IOM uint32_t CHAINSEL_SRP; /*!< Offset: 0x008 Chain Selection Register for SRP */
__IOM uint32_t CHAINMASK_MCU; /*!< Offset: 0x00C Chain Selection Mask Register for MCU */
__IOM uint32_t CHAINMASK_SRP; /*!< Offset: 0x010 Chain Selection Mask Register for SRP */
__IM uint32_t DMONQ_MCU; /*!< Offset: 0x014 Flip-Flop Output Register for MCU */
__IM uint32_t DMONQ_SRP; /*!< Offset: 0x018 Flip-Flop Output Register for SRP */
__IM uint32_t DMONCNT_L; /*!< Offset: 0x01C Violation Counter Lower Register */
__IM uint32_t DMONCNT_H; /*!< Offset: 0x020 Violation Counter Higher Register */
} BP_DELAY_MON_TypeDef;
/*---------- Real Time Clock -------------------------------------------------*/
typedef struct {
__IOM uint32_t PMU_KA_DLY_CON0; /*!< Offset: 0x000 PMU_KA_DLY_CON0 */
__IOM uint32_t PMU_KA_DLY_CON1; /*!< Offset: 0x004 PMU_KA_DLY_CON1 */
__IOM uint32_t PMU_KA_LDO_CTRL; /*!< Offset: 0x008 PMU_KA_LDO_CTRL */
__IM uint32_t PMU_KA_LDO_POR_STATUS; /*!< Offset: 0x00C PMU_KA_LDO_POR_STATUS */
__IOM uint32_t PMU_KA_MANUAL_CTRL; /*!< Offset: 0x010 PMU_KA_MANUAL_CTRL */
__IOM uint32_t KA_AFEISO_CTRL; /*!< Offset: 0x014 KA_AFEISO_CTRL */
__IM uint32_t KA_SYSTEM_ON; /*!< Offset: 0x018 KA_SYSTEM_ON */
uint32_t RESERVED;
__IOM uint32_t CALENDAR_MODE; /*!< Offset: 0x020 CALENDAR_MODE */
__IOM uint32_t GEN_COUNT_CLR; /*!< Offset: 0x024 GEN_COUNT_CLR */
__IOM uint32_t LOAD_COUNT_SIG; /*!< Offset: 0x028 LOAD_COUNT_SIG */
struct {
__IO uint32_t SEC; /*!< Offset: 0x02C LOAD_COUNT_VALUE0 */
__IO uint32_t MIN; /*!< Offset: 0x030 LOAD_COUNT_VALUE1 */
__IO uint32_t HOUR; /*!< Offset: 0x034 LOAD_COUNT_VALUE2 */
__IO uint32_t DAY; /*!< Offset: 0x038 LOAD_COUNT_VALUE3 */
__IO uint32_t MON; /*!< Offset: 0x03C LOAD_COUNT_VALUE4 */
__IO uint32_t YEAR; /*!< Offset: 0x040 LOAD_COUNT_VALUE5 */
} BCD_W;
struct {
__IO uint32_t SEC; /*!< Offset: 0x044 CALENDAR_COUNT_VALUE0 */
__IO uint32_t MIN; /*!< Offset: 0x048 CALENDAR_COUNT_VALUE1 */
__IO uint32_t HOUR; /*!< Offset: 0x04C CALENDAR_COUNT_VALUE2 */
__IO uint32_t DAY; /*!< Offset: 0x050 CALENDAR_COUNT_VALUE3 */
__IO uint32_t MON; /*!< Offset: 0x054 CALENDAR_COUNT_VALUE4 */
__IO uint32_t YEAR; /*!< Offset: 0x058 CALENDAR_COUNT_VALUE5 */
} BCD_R;
__IOM uint32_t CALENDAR_TIME_STAMP; /*!< Offset: 0x05C CALENDAR_TIME_STAMP */
__IOM uint32_t INT_ENABLE_CPU; /*!< Offset: 0x060 INT_ENABLE_CPU */
__IOM uint32_t INT_CLEAR_CPU; /*!< Offset: 0x064 INT_CLEAR_CPU */
__IOM uint32_t RESERVED1;
__IOM uint32_t SYNC_INT_TIME0; /*!< Offset: 0x06C SYNC_INT_TIME0 */
__IOM uint32_t SYNC_INT_TIME1; /*!< Offset: 0x070 SYNC_INT_TIME1 */
__IM uint32_t INT_STATUS_CPU; /*!< Offset: 0x074 INT_STATUS_CPU */
__IOM uint32_t ALARM_ENABLE; /*!< Offset: 0x078 ALARM_ENABLE */
__IOM uint32_t ALARM_COUNT_VALUE0; /*!< Offset: 0x07C ALARM_COUNT_VALUE0 */
__IOM uint32_t ALARM_COUNT_VALUE1; /*!< Offset: 0x080 ALARM_COUNT_VALUE1 */
__IOM uint32_t ALARM_COUNT_VALUE2; /*!< Offset: 0x084 ALARM_COUNT_VALUE2 */
__IOM uint32_t ALARM_COUNT_VALUE3; /*!< Offset: 0x088 ALARM_COUNT_VALUE3 */
__IOM uint32_t ALARM_COUNT_VALUE4; /*!< Offset: 0x08C ALARM_COUNT_VALUE4 */
__IOM uint32_t ALARM_COUNT_VALUE5; /*!< Offset: 0x090 ALARM_COUNT_VALUE5 */
__IM uint32_t GENERAL_COUNT0; /*!< Offset: 0x094 GENERAL_COUNT0 */
__IM uint32_t GENERAL_COUNT1; /*!< Offset: 0x098 GENERAL_COUNT1 */
__IOM uint32_t STOP_COUNT_ENABLE; /*!< Offset: 0x09C STOP_COUNT_ENABLE */
__IOM uint32_t STOP_COUNT_CLEAR; /*!< Offset: 0x0A0 STOP_COUNT_CLEAR */
__IM uint32_t STOP_COUNT_TIME_STAMP0; /*!< Offset: 0x0A4 STOP_COUNT_TIME_STAMP0 */
__IM uint32_t STOP_COUNT_TIME_STAMP1; /*!< Offset: 0x0A8 STOP_COUNT_TIME_STAMP1 */
__IM uint32_t STOP_COUNT_TIME_STAMP2; /*!< Offset: 0x0AC STOP_COUNT_TIME_STAMP2 */
__IM uint32_t STOP_COUNT_TIME_STAMP3; /*!< Offset: 0x0B0 STOP_COUNT_TIME_STAMP3 */
__IOM uint32_t AUTO_COUNT_CLR; /*!< Offset: 0x0B4 AUTO_COUNT_CLR */
__IOM uint32_t STOP_COUNT_LOAD0; /*!< Offset: 0x0B8 STOP_COUNT_LOAD0 */
__IOM uint32_t STOP_COUNT_LOAD1; /*!< Offset: 0x0BC STOP_COUNT_LOAD1 */
__IOM uint32_t STOP_COUNT_LOAD2; /*!< Offset: 0x0C0 STOP_COUNT_LOAD2 */
__IOM uint32_t STOP_COUNT_LOAD3; /*!< Offset: 0x0C4 STOP_COUNT_LOAD3 */
__IOM uint32_t GENERAL_COUNT_SNAP_SHOT; /*!< Offset: 0x0C8 GENERAL_COUNT_SNAP_SHOT_COMMAND */
__IOM uint32_t STOP_COUNT_SNAP_SHOT; /*!< Offset: 0x0CC STOP_COUNT_SNAP_SHOT_COMMAND */
__IOM uint32_t PWMCTRL; /*!< Offset: 0x0D0 PWMCTRL */
__IOM uint32_t PWM_PULSE0; /*!< Offset: 0x0D4 PWM_PULSE0 */
__IOM uint32_t PWM_PULSE1; /*!< Offset: 0x0D8 PWM_PULSE1 */
__IOM uint32_t PWM_PULSE2; /*!< Offset: 0x0DC PWM_PULSE2 */
__IOM uint32_t PWM_PULSE3; /*!< Offset: 0x0E0 PWM_PULSE3 */
__IM uint32_t KA_BOR_INT; /*!< Offset: 0x0E4 KA_BOR_INT */
__IOM uint32_t KA_BOR_INT_CLEAR; /*!< Offset: 0x0E8 KA_BOR_INT_CLEAR */
__IOM uint32_t KA_DLY_EN; /*!< Offset: 0x0EC KA_DLY_EN */
__IOM uint32_t KA_32K_XTAL_CON; /*!< Offset: 0x0F0 KA_32K_XTAL_CON */
__IOM uint32_t KA_IOPWR_CTRL; /*!< Offset: 0x0F4 KA_IOPWR_CTRL */
__IOM uint32_t RTC_CLK_MUX; /*!< Offset: 0x0F8 RTC_CLK_MUX */
__IOM uint32_t KA_PM_IV_EN; /*!< Offset: 0x0FC KA_PM_IV_EN */
} BP_RTC_TypeDef;
/*---------- Analog Front End Top Control ------------------------------------*/
typedef struct {
__IOM uint32_t AFE_CLK_CTRL; /*!< Offset: 0x000 AFE_CLK_CTRL */
__IOM uint32_t AFE_RST_CTRL; /*!< Offset: 0x004 AFE_RST_CTRL */
__IOM uint32_t GPIO_TMUX_SEL; /*!< Offset: 0x008 GPIO_TMUX_SEL */
__IOM uint32_t GP_DAC0; /*!< Offset: 0x00C GP_DAC0 */
__IOM uint32_t GP_DAC1; /*!< Offset: 0x010 GP_DAC1 */
__IOM uint32_t GP_ADC0; /*!< Offset: 0x014 GP_ADC0 */
__IOM uint32_t GP_ADC1; /*!< Offset: 0x018 GP_ADC1 */
__IOM uint32_t REF_CTRL; /*!< Offset: 0x01C REF_CTRL */
__IOM uint32_t REGULATOR_CTRL0; /*!< Offset: 0x020 REGULATOR_CTRL0 */
__IOM uint32_t REGULATOR_CTRL1; /*!< Offset: 0x024 REGULATOR_CTRL1 */
uint32_t RESERVED1[4];
__IOM uint32_t TMPX; /*!< Offset: 0x038 TMPX */
uint32_t RESERVED2;
__IOM uint32_t V11_RESERVED0; /*!< Offset: 0x040 V11_RESERVED0 */
__IOM uint32_t V11_RESERVED1; /*!< Offset: 0x044 V11_RESERVED1 */
__IOM uint32_t V11_RESERVED2; /*!< Offset: 0x048 V11_RESERVED2 */
__IOM uint32_t V11_RESERVED3; /*!< Offset: 0x04C V11_RESERVED3 */
__IOM uint32_t V3_RESERVED0; /*!< Offset: 0x050 V3_RESERVED0 */
__IOM uint32_t V3_RESERVED1; /*!< Offset: 0x054 V3_RESERVED1 */
__IOM uint32_t TRIM_SELB; /*!< Offset: 0x058 TRIM_SELB */
__IOM uint32_t FM_SEL; /*!< Offset: 0x05C FM_SEL */
} BP_AFE_TOP_TypeDef;
/*---------- Analog Front End ADC FIFO Control ---------------------------------*/
typedef struct {
__IOM uint32_t FIFO_INTR_MASK; /*!< Offset: 0x000 FIFO_INTR_MASK */
__IOM uint32_t FIFO_SW_RESET; /*!< Offset: 0x004 FIFO_SW_RESET */
__IOM uint32_t FIFO_DMA_SIZE0; /*!< Offset: 0x008 FIFO_DMA_SIZE0 */
__IOM uint32_t FIFO_READY_SIZE0; /*!< Offset: 0x00C FIFO_READY_SIZE0 */
__IOM uint32_t FIFO_ENABLE; /*!< Offset: 0x010 FIFO_ENABLE */
__IOM uint32_t FIFO_DMA_ENABLE; /*!< Offset: 0x014 FIFO_DMA_ENABLE */
__IOM uint32_t FIFO_INT_CLEAR; /*!< Offset: 0x018 FIFO_INT_CLEAR */
__IM uint32_t FIFO0_READ_DATA; /*!< Offset: 0x01C FIFO0_READ_DATA */
__IM uint32_t FIFO1_READ_DATA; /*!< Offset: 0x020 FIFO1_READ_DATA */
__IM uint32_t FIFO2_READ_DATA; /*!< Offset: 0x024 FIFO2_READ_DATA */
__IM uint32_t FIFO3_READ_DATA; /*!< Offset: 0x028 FIFO3_READ_DATA */
__IM uint32_t FIFO4_READ_DATA; /*!< Offset: 0x02C FIFO4_READ_DATA */
__IM uint32_t FIFO5_READ_DATA; /*!< Offset: 0x030 FIFO5_READ_DATA */
__IM uint32_t FIFO6_READ_DATA; /*!< Offset: 0x034 FIFO6_READ_DATA */
__IM uint32_t FIFO7_READ_DATA; /*!< Offset: 0x038 FIFO7_READ_DATA */
__IM uint32_t FIFO8_READ_DATA; /*!< Offset: 0x03C FIFO8_READ_DATA */
uint32_t RESERVED;
__IM uint32_t FIFO_DATA_CNT_SAR; /*!< Offset: 0x044 FIFO_DATA_SAR */
__IM uint32_t FIFO_DATA_CNT_IDC; /*!< Offset: 0x048 FIFO_DATA_IDC */
__IM uint32_t FIFO_STATUS; /*!< Offset: 0x04C FIFO_STATUS */
__IOM uint32_t FIFO_RCLK_MANUAL_CG_EN; /*!< Offset: 0x050 FIFO_RCLK_MANUAL_CG_EN */
__IOM uint32_t FIFO_RCLK_MANUAL_CG; /*!< Offset: 0x054 FIFO_RCLK_MANUAL_CG */
__IOM uint32_t FIFO_DMA_SIZE1; /*!< Offset: 0x058 FIFO_DMA_SIZE1 */
__IOM uint32_t FIFO_READY_SIZE1; /*!< Offset: 0x05C FIFO_READY_SIZE1 */
__IM uint32_t FIFO_DATA_CNT_SDC; /*!< Offset: 0x060 FIFO_DATA_SDC */
__IM uint32_t FIFO_INT_STATUS; /*!< Offset: 0x064 FIFO_INT_STATUS */
} BP_ADC_FIFO_TypeDef;
/*---------- Analog Front End ADC Control ------------------------------------*/
typedef struct {
__IOM uint32_t SAR_SEL; /*!< Offset: 0x000 SAR_SEL */
__IOM uint32_t DC_COMPEN_ADC0; /*!< Offset: 0x004 DC_COMPEN_ADC0 */
__IOM uint32_t DC_COMPEN_ADC1; /*!< Offset: 0x008 DC_COMPEN_ADC1 */
__IOM uint32_t DC_COMPEN_ADC2; /*!< Offset: 0x00C DC_COMPEN_ADC2 */
uint32_t RESERVED1[3];
__IM uint32_t SAR_ADC0_CH0_DATA; /*!< Offset: 0x01C SAR_ADC0_CH0_DATA */
__IM uint32_t SAR_ADC0_CH1_DATA; /*!< Offset: 0x020 SAR_ADC0_CH1_DATA */
__IM uint32_t SAR_ADC1_CH0_DATA; /*!< Offset: 0x024 SAR_ADC1_CH0_DATA */
__IM uint32_t SAR_ADC1_CH1_DATA; /*!< Offset: 0x028 SAR_ADC1_CH1_DATA */
__IM uint32_t SAR_ADC2_CH0_DATA; /*!< Offset: 0x02C SAR_ADC2_CH0_DATA */
__IM uint32_t SAR_ADC2_CH1_DATA; /*!< Offset: 0x030 SAR_ADC2_CH1_DATA */
__IM uint32_t SD_ADC0_DATA; /*!< Offset: 0x034 SD_ADC0_DATA */
__IM uint32_t SD_ADC1_DATA; /*!< Offset: 0x038 SD_ADC1_DATA */
__IM uint32_t SD_ADC2_DATA; /*!< Offset: 0x03C SD_ADC2_DATA */
uint32_t RESERVED2;
__IOM uint32_t SAR_ADC_CON; /*!< Offset: 0x044 SAR_ADC_CON */
__IOM uint32_t SAR_ADC_CTRL; /*!< Offset: 0x048 SAR_ADC_CTRL */
} BP_ADC_CON_TypeDef;
/*---------- Analog Front End SDADC Control ----------------------------------*/
typedef struct {
__IOM uint32_t SDADC_CTRL1; /*!< Offset: 0x000 SDADC_CTRL1 */
__IOM uint32_t SDADC_CTRL2; /*!< Offset: 0x004 SDADC_CTRL2 */
__IOM uint32_t SDADC_CTRL3; /*!< Offset: 0x008 SDADC_CTRL3 */
__IOM uint32_t RESERVED;
__IOM uint32_t GPADC_TEST_MODE_CTRL; /*!< Offset: 0x010 GPADC_TEST_MODE_CTRL */
__IOM uint32_t GPADC_LDO_CTRL; /*!< Offset: 0x014 GPADC_LDO_CTRL */
} BP_SDADC_CON_TypeDef;
/*---------- Analog Front End ECG --------------------------------------------*/
typedef struct {
__IOM uint32_t ECG_EN; /*!< Offset: 0x000 ECG_EN */
__IOM uint32_t ECG_GAIN; /*!< Offset: 0x004 ECG_GAIN */
__IOM uint32_t ECG_BW; /*!< Offset: 0x008 ECG_BW */
__IOM uint32_t ECG_SET; /*!< Offset: 0x00C ECG_SET */
__IOM uint32_t ECG_INIT; /*!< Offset: 0x010 ECG_INIT */
__IOM uint32_t ECG_HPF; /*!< Offset: 0x014 ECG_HPF */
__IOM uint32_t ECG_CONT; /*!< Offset: 0x018 ECG_CONT */
} BP_AFE_ECG_TypeDef;
/*---------- Analog Front End PPG --------------------------------------------*/
typedef struct {
__IOM uint32_t PPG_GLOBALEN; /*!< Offset: 0x000 PPG_GLOBALEN */
__IOM uint32_t PPG0_FUNCEN; /*!< Offset: 0x004 PPG0_FUNCEN */
__IOM uint32_t PPG0_TIA; /*!< Offset: 0x008 PPG0_TIA */
__IOM uint32_t PPG0_IDC; /*!< Offset: 0x00C PPG0_IDC */
__IOM uint32_t PPG0_PRT; /*!< Offset: 0x010 PPG0_PRT */
__IOM uint32_t PPG0_LEDONT; /*!< Offset: 0x014 PPG0_LEDONT */
__IOM uint32_t PPG0_CONVT; /*!< Offset: 0x018 PPG0_CONVT */
__IOM uint32_t PPG0_IDCRSTT; /*!< Offset: 0x01C PPG0_IDCRSTT */
__IOM uint32_t PPG0_AFESETT; /*!< Offset: 0x020 PPG0_AFESETT */
__IOM uint32_t PPG0_PDNTCTRL; /*!< Offset: 0x024 PPG0_PDNTCTRL */
__IOM uint32_t PPG0_LEDTSCTRL; /*!< Offset: 0x028 PPG0_LEDTSCTRL */
__IOM uint32_t PPG0_LEDTSCDAC; /*!< Offset: 0x02C PPG0_LEDTSCDAC */
__IOM uint32_t PPG0_DCCCTRL; /*!< Offset: 0x030 PPG0_DCCCTRL */
uint32_t RESERVED1[4];
__IOM uint32_t PPG1_FUNCEN; /*!< Offset: 0x044 PPG1_FUNCEN */
__IOM uint32_t PPG1_TIA; /*!< Offset: 0x048 PPG1_TIA */
__IOM uint32_t PPG1_IDC; /*!< Offset: 0x04C PPG1_IDC */
__IOM uint32_t PPG1_PRT; /*!< Offset: 0x050 PPG1_PRT */
uint32_t RESERVED2;
__IOM uint32_t PPG1_CONVT; /*!< Offset: 0x058 PPG1_CONVT */
__IOM uint32_t PPG1_IDCRSTT; /*!< Offset: 0x05C PPG1_IDCRSTT */
__IOM uint32_t PPG1_AFESETT; /*!< Offset: 0x060 PPG1_AFESETT */
__IOM uint32_t PPG1_PDNTCTRL; /*!< Offset: 0x064 PPG1_PDNTCTRL */
uint32_t RESERVED3[2];
__IOM uint32_t PPG1_DCCCTRL; /*!< Offset: 0x070 PPG1_DCCCTRL */
uint32_t RESERVED4[3];
__IOM uint32_t PPG_GENERAL; /*!< Offset: 0x080 PPG_GENERAL */
__IOM uint32_t PPG_AGCLEVEL0; /*!< Offset: 0x084 PPG_AGCLEVEL0 */
__IOM uint32_t PPG_AGCLEVEL1; /*!< Offset: 0x088 PPG_AGCLEVEL1 */
__IOM uint32_t PPG_AGCLEVEL2; /*!< Offset: 0x08C PPG_AGCLEVEL2 */
__IOM uint32_t PPG_AGCTIME; /*!< Offset: 0x090 PPG_AGCTIME */
__IOM uint32_t PPG_AGCSTEP; /*!< Offset: 0x094 PPG_AGCSTEP */
__IM uint32_t PPG_AGCSTATUS_TS0; /*!< Offset: 0x098 PPG_AGCSTATUS_TS0 */
__IM uint32_t PPG_AGCDCAVG_TS0; /*!< Offset: 0x09C PPG_AGCDCAVG_TS0 */
__IM uint32_t PPG_AGCSTATUS_TS1; /*!< Offset: 0x0A0 PPG_AGCSTATUS_TS1 */
__IM uint32_t PPG_AGCDCAVG_TS1; /*!< Offset: 0x0A4 PPG_AGCDCAVG_TS1 */
__IM uint32_t PPG_AGCSTATUS_TS2; /*!< Offset: 0x0A8 PPG_AGCSTATUS_TS2 */
__IM uint32_t PPG_AGCDCAVG_TS2; /*!< Offset: 0x0AC PPG_AGCDCAVG_TS2 */
__IM uint32_t PPG_AGCSTATUS_TS3; /*!< Offset: 0x0B0 PPG_AGCSTATUS_TS3 */
__IM uint32_t PPG_AGCDCAVG_TS3; /*!< Offset: 0x0B4 PPG_AGCDCAVG_TS3 */
__IOM uint32_t PPG_MANUAL_TEST; /*!< Offset: 0x0B8 PPG_MANUAL_TEST */
uint32_t RESERVED5;
__IOM uint32_t LED_FUNCEN; /*!< Offset: 0x0C0 LED_FUNCEN */
__IOM uint32_t LED_TRIM; /*!< Offset: 0x0C4 LED_TRIM */
__IOM uint32_t LED_CDAC0; /*!< Offset: 0x0C8 LED_CDAC0 */
__IOM uint32_t LED_CDAC1; /*!< Offset: 0x0CC LED_CDAC1 */
__IOM uint32_t LED_CDAC2; /*!< Offset: 0x0D0 LED_CDAC2 */
__IOM uint32_t LED_CDAC3; /*!< Offset: 0x0D4 LED_CDAC3 */
} BP_AFE_PPG_TypeDef;
/*---------- Analog Front End BIA --------------------------------------------*/
typedef struct {
__IOM uint32_t BIA_TX_FIL; /*!< Offset: 0x000 BIA_TX_FIL */
__IOM uint32_t BIA_TX_FREQ; /*!< Offset: 0x004 BIA_TX_FREQ */
__IOM uint32_t BIA_TX_AMPL; /*!< Offset: 0x008 BIA_TX_AMPL */
__IOM uint32_t BIA_TX_CUR; /*!< Offset: 0x00C BIA_TX_CUR */
__IOM uint32_t BIA_TX_SW; /*!< Offset: 0x010 BIA_TX_SW */
__IOM uint32_t BIA_RX_INPUT; /*!< Offset: 0x014 BIA_RX_INPUT */
__IOM uint32_t BIA_RX_AMP1; /*!< Offset: 0x018 BIA_RX_AMP1 */
__IOM uint32_t BIA_RX_AMP2; /*!< Offset: 0x01C BIA_RX_AMP2 */
__IOM uint32_t BIA_RX_FIL; /*!< Offset: 0x020 BIA_RX_FIL */
__IOM uint32_t BIA_RX_AMP3; /*!< Offset: 0x024 BIA_RX_AMP3 */
__IOM uint32_t BIA_RX_COMP; /*!< Offset: 0x028 BIA_RX_COMP */
__IOM uint32_t BIA_TMUX1; /*!< Offset: 0x02C BIA_TMUX1 */
__IOM uint32_t BIA_TMUX2; /*!< Offset: 0x030 BIA_TMUX2 */
__IOM uint32_t BIA_TMUX3; /*!< Offset: 0x034 BIA_TMUX3 */
__IOM uint32_t BIA_DCTRL1; /*!< Offset: 0x038 BIA_DCTRL1 */
__IOM uint32_t BIA_IQ_GEN; /*!< Offset: 0x03C BIA_IQ_GEN */
__IOM uint32_t BIA_DCTRL3; /*!< Offset: 0x040 BIA_DCTRL3 */
uint32_t RESERVED;
__IOM uint32_t BIA_TRX_EN; /*!< Offset: 0x048 BIA_TRX_EN */
__IOM uint32_t BIA_GSR_MODE; /*!< Offset: 0x04C BIA_GSR_MODE */
__IOM uint32_t BIA_CURRENT_CTRL; /*!< Offset: 0x050 BIA_CURRENT_CTRL */
__IOM uint32_t BIA_IMP_CTRL; /*!< Offset: 0x054 BIA_IMP_CTRL */
__IOM uint32_t BIA_HPF_EN; /*!< Offset: 0x058 BIA_HPF_EN */
__IOM uint32_t BIA_TESTMUX_EN; /*!< Offset: 0x05C BIA_TESTMUX_EN */
} BP_AFE_BIA_TypeDef;
/*---------- Analog Front End GSR --------------------------------------------*/
typedef struct {
__IOM uint32_t CTRL; /*!< Offset: 0x000 GSR HW Control Register 0 */
__IOM uint32_t SW_CTRL; /*!< Offset: 0x004 GSR SW Control Register 1 */
__IOM uint32_t FIT3PCTRL; /*!< Offset: 0x008 GSR External register fitting Register */
__IOM uint32_t FIT3NCTRL; /*!< Offset: 0x00C GSR External register fitting Register */
//__IOM uint32_t FIT1PCTRL; /*!< Offset: 0x010 GSR External register fitting Register */
//__IOM uint32_t FIT1NCTRL; /*!< Offset: 0x014 GSR External register fitting Register */
} BP_AFE_GSR_TypeDef;
/*------------- PL230 uDMA (uDMA) --------------------------------------------*/
typedef struct {
__IM uint32_t DMA_STATUS; /*!< Offset: 0x000 DMA Status Register */
__OM uint32_t DMA_CFG; /*!< Offset: 0x004 DMA Configuration Register */
__IOM uint32_t CTRL_BASE_PTR; /*!< Offset: 0x008 Channel Control Data Base Pointer Register */
__IM uint32_t ALT_CTRL_BASE_PTR; /*!< Offset: 0x00C Channel Alternate Control Data Base Pointer Register */
__IM uint32_t DMA_WAITONREQ_STATUS; /*!< Offset: 0x010 Channel Wait On Request Status Register */
__OM uint32_t CHNL_SW_REQUEST; /*!< Offset: 0x014 Channel Software Request Register */
__IOM uint32_t CHNL_USEBURST_SET; /*!< Offset: 0x018 Channel UseBurst Set Register */
__OM uint32_t CHNL_USEBURST_CLR; /*!< Offset: 0x01C Channel UseBurst Clear Register */
__IOM uint32_t CHNL_REQ_MASK_SET; /*!< Offset: 0x020 Channel Request Mask Set Register */
__OM uint32_t CHNL_REQ_MASK_CLR; /*!< Offset: 0x024 Channel Request Mask Clear Register */
__IOM uint32_t CHNL_ENABLE_SET; /*!< Offset: 0x028 Channel Enable Set Register */
__OM uint32_t CHNL_ENABLE_CLR; /*!< Offset: 0x02C Channel Enable Clear Register */
__IOM uint32_t CHNL_PRI_ALT_SET; /*!< Offset: 0x030 Channel Primary-Alternate Set Register */
__OM uint32_t CHNL_PRI_ALT_CLR; /*!< Offset: 0x034 Channel Primary-Alternate Clear Register */
__IOM uint32_t CHNL_PRIORITY_SET; /*!< Offset: 0x038 Channel Priority Set Register */
__OM uint32_t CHNL_PRIORITY_CLR; /*!< Offset: 0x03C Channel Priority Clear Register */
uint32_t RESERVED1[3];
__IOM uint32_t ERR_CLR; /*!< Offset: 0x04C Bus Error Clear Register */
__IOM uint32_t DMA_MUX; /*!< Offset: 0x050 DMA Channel Mux Within I2C and SPI Peripherals */
__IOM uint32_t DMA_NOT_MUX; /*!< Offset: 0x054 DMA Channel Not Muxed Within I2C and SPI Peripherals */
__IOM uint32_t DMA_REQ_GATE; /*!< Offset: 0x058 DMA Request Gating Enable Register */
} BP_DMA_TypeDef;
/*---------- System Control (SYSCON) -----------------------------------------*/
typedef struct {
__IOM uint32_t PMU_SYSCON_CTRL; /*!< Offset: 0x000 PMU_SYSCON_CTRL */
__IOM uint32_t PMU_SYSCON_DLY_CTRL; /*!< Offset: 0x004 PMU_SYSCON_DLY_CTRL */
__IOM uint32_t PMU_MCU_DLY_CTRL; /*!< Offset: 0x008 PMU_MCU_DLY_CTRL */
__IOM uint32_t PMU_SYSCON_DLY_EN; /*!< Offset: 0x00C PMU_SYSCON_DLY_EN */
__IOM uint32_t RESERVED1;
__IOM uint32_t PMU_SYSCON_FAST_BOOT; /*!< Offset: 0x014 PMU_SYSCON_FAST_BOOT */
uint32_t RESERVED2[58];
__IOM uint32_t MCU_CLK_CTRL; /*!< Offset: 0x100 MCU_CLK_CTRL */
__IOM uint32_t MCU_CLK_GATE; /*!< Offset: 0x104 MCU_CLK_GATE */
uint32_t RESERVED3[2];
__IOM uint32_t PERI_CLK_CTRL; /*!< Offset: 0x110 PERI_CLK_CTRL */
__IOM uint32_t PERI_CLK_GATE; /*!< Offset: 0x114 PERI_CLK_GATE */
__IOM uint32_t PERI_CLK_MUX; /*!< Offset: 0x118 PERI_CLK_MUX */
uint32_t RESERVED4;
__IOM uint32_t AFE_CLK_CTRL; /*!< Offset: 0x120 AFE_CLK_CTRL */
uint32_t RESERVED8[55];
__IOM uint32_t PMU_SYSCON_PD_CTRL; /*!< Offset: 0x200 PMU_SYSCON_PD_CTRL */
__IM uint32_t PMU_SYSCON_PD_STATUS; /*!< Offset: 0x204 PMU_SYSCON_PD_STATUS */
__IOM uint32_t PMU_SYSCON_RET_CTRL; /*!< Offset: 0x208 PMU_SYSCON_RET_CTRL */
__IOM uint32_t SYSCON_FLASH_MODE; /*!< Offset: 0x20C SYSCON_FLASH_MODE */
uint32_t RESERVED9[124];
__IOM uint32_t IOCFG_GENERAL; /*!< Offset: 0x400 SYSCON_IOCFGG */
__IOM uint32_t IOCFG[14]; /*!< Offset: 0x404 SYSCON_IOCFG */
uint32_t RESERVED10[113];
__IOM uint32_t PLL_CTRL0; /*!< Offset: 0x600 PLL_CTRL0 */
__IOM uint32_t PLL_CTRL1; /*!< Offset: 0x604 PLL_CTRL1 */
__IM uint32_t PLL_STATUS; /*!< Offset: 0x608 PLL_STATUS */
__IOM uint32_t HSOSC_CTRL; /*!< Offset: 0x60C HSOSC_CTRL */
__IOM uint32_t LSOSC_CTRL; /*!< Offset: 0x610 LSOSC_CTRL */
uint32_t RESERVED11[123];
__IOM uint32_t SRP_IRQEVE; /*!< Offset: 0x800 SRP_IRQEVE */
__IM uint32_t SRP_STATUS; /*!< Offset: 0x804 SRP_STATUS */
uint32_t RESERVED12[62];
__IOM uint32_t SYSCON_IO; /*!< Offset: 0x900 SYSCON_IO */
__IM uint32_t SYSCON_WAKEUP_STATUS; /*!< Offset: 0x904 SYSCON_WAKEUP_STATUS */
__IOM uint32_t SYSCON_WAKEUP_STATUS_CLEAR; /*!< Offset: 0x908 SYSCON_WAKEUP_STATUS_CLEAR */
__IM uint32_t QSPI_MONITOR1; /*!< Offset: 0x90C QSPI_MONITOR1 */
__IM uint32_t QSPI_MONITOR2; /*!< Offset: 0x910 QSPI_MONITOR2 */
__IOM uint32_t KA_ACCESS; /*!< Offset: 0x914 KA_ACCESS */
} BP_SYSCON_TypeDef;
/*---------- Sample Rate Converter (SRC) -------------------------------------*/
typedef struct {
__OM uint32_t CTRL; /*!< Offset: 0x000 Control Register */
__IOM uint32_t CFG; /*!< Offset: 0x004 Configuration Register */
__IM uint32_t STAT; /*!< Offset: 0x008 Status Register */
__IOM uint32_t fSTART; /*!< Offset: 0x00C Start Position(float) Register */
__IOM uint32_t fINC; /*!< Offset: 0x010 Increment Value(float) Register */
__IOM uint32_t PB_PTR; /*!< Offset: 0x014 Preceding Buffer Pointer Register */
__IOM uint32_t PB_SIZE; /*!< Offset: 0x018 Preceding Buffer Size Register */
__IOM uint32_t SB_PTR; /*!< Offset: 0x01C Sample Buffer Pointer Register */
__IOM uint32_t SB_SIZE; /*!< Offset: 0x020 Sample Buffer Size Register */
__IOM uint32_t CB_PTR; /*!< Offset: 0x024 Coefficient Buffer Pointer Register */
__IOM uint32_t CB_SIZE; /*!< Offset: 0x028 Coefficient Buffer Size Register */
__IOM uint32_t RB_PTR; /*!< Offset: 0x02C Result Buffer Pointer Register */
__IOM uint32_t RB_SIZE; /*!< Offset: 0x030 Result Buffer Size Register */
__IOM uint32_t IN_SH; /*!< Offset: 0x034 Shift(in) Register */
__IOM uint32_t OUT_SH; /*!< Offset: 0x038 Shift(out) Register */
__IOM uint32_t INT; /*!< Offset: 0x03C SRC Interrupt Register */
} BP_SRC_TypeDef;
/*---------- General Purpose Input Output (GPIO) -----------------------------*/
typedef struct {
__IOM uint32_t DATA; /*!< Offset: 0x000 DATA Register */
__IOM uint32_t DATAOUT; /*!< Offset: 0x004 Data Output Latch Register */
uint32_t RESERVED1[2];
__IOM uint32_t OUTENSET; /*!< Offset: 0x010 Output Enable Set Register */
__IOM uint32_t OUTENCLR; /*!< Offset: 0x014 Output Enable Clear Register */
__IOM uint32_t ALTFUNCSET; /*!< Offset: 0x018 Alternate Function Set Register */
__IOM uint32_t ALTFUNCCLR; /*!< Offset: 0x01C Alternate Function Clear Register */
__IOM uint32_t INTENSET; /*!< Offset: 0x020 Interrupt Enable Set Register */
__IOM uint32_t INTENCLR; /*!< Offset: 0x024 Interrupt Enable Clear Register */
__IOM uint32_t INTTYPESET; /*!< Offset: 0x028 Interrupt Type Set Register */
__IOM uint32_t INTTYPECLR; /*!< Offset: 0x02C Interrupt Type Clear Register */
__IOM uint32_t INTPOLSET; /*!< Offset: 0x030 Interrupt Polarity Set Register */
__IOM uint32_t INTPOLCLR; /*!< Offset: 0x034 Interrupt Polarity Clear Register */
union {
__IM uint32_t INTSTAT; /*!< Offset: 0x038 Interrupt Status Register */
__OM uint32_t INTCLR; /*!< Offset: 0x038 Interrupt Clear Register */
};
__IOM uint32_t ALTFUNCSEL; /*!< Offset: 0x03C Alternate Function Set Register */
uint32_t RESERVED2[240];
__IOM uint32_t LB_MASKED[256]; /*!< Offset: 0x400 - 0x7FC Lower byte Masked Access Register */
__IOM uint32_t UB_MASKED[256]; /*!< Offset: 0x800 - 0xBFC Upper byte Masked Access Register */
} BP_GPIO_TypeDef;
/*---------- Advanced Encryption Standard (AES) ------------------------------*/
/** @addtogroup BP_AES S1SBP6A Advanced Encryption Standard
@{
*/
typedef struct {
__IOM uint32_t AESCON; /*!< Offset: 0x000 AES Control */
__IOM uint32_t AESSTATUS; /*!< Offset: 0x004 AES Status */
uint32_t RESERVED1[2];
__IOM uint32_t AESINDATA1; /*!< Offset: 0x010 AES Input Data[31:0] */
__IOM uint32_t AESINDATA2; /*!< Offset: 0x014 AES Input Data[63:32] */
__IOM uint32_t AESINDATA3; /*!< Offset: 0x018 AES Input Data[95:64] */
__IOM uint32_t AESINDATA4; /*!< Offset: 0x01C AES Input Data[127:96] */
__IM uint32_t AESOUTDATA1; /*!< Offset: 0x020 AES Output Data[31:0] */
__IM uint32_t AESOUTDATA2; /*!< Offset: 0x024 AES Output Data[63:32] */
__IM uint32_t AESOUTDATA3; /*!< Offset: 0x028 AES Output Data[95:64] */
__IM uint32_t AESOUTDATA4; /*!< Offset: 0x02C AES Output Data[127:96] */
uint32_t RESERVED2[8];
__IOM uint32_t AESIV1; /*!< Offset: 0x050 AES IV[31:0] */
__IOM uint32_t AESIV2; /*!< Offset: 0x054 AES IV[63:32] */
__IOM uint32_t AESIV3; /*!< Offset: 0x058 AES IV[95:64] */
__IOM uint32_t AESIV4; /*!< Offset: 0x05C AES IV[127:96] */
uint32_t RESERVED3[8];
__OM uint32_t AESKEY1; /*!< Offset: 0x080 AES KEY[31:0] */
__OM uint32_t AESKEY2; /*!< Offset: 0x084 AES KEY[63:32] */
__OM uint32_t AESKEY3; /*!< Offset: 0x088 AES KEY[95:64] */
__OM uint32_t AESKEY4; /*!< Offset: 0x08C AES KEY[127:96] */
__OM uint32_t AESKEY5; /*!< Offset: 0x090 AES KEY[159:128] */
__OM uint32_t AESKEY6; /*!< Offset: 0x094 AES KEY[191:160] */
__OM uint32_t AESKEY7; /*!< Offset: 0x098 AES KEY[223:192] */
__OM uint32_t AESKEY8; /*!< Offset: 0x09C AES KEY[255:224] */
} BP_AES_TypeDef;
/*---------- True Random Number Generator (DTRNG) ----------------------------*/
typedef struct {
__IOM uint32_t CLKDIV; /*!< Offset: 0x000 DTRNG Clock Divider */
__IOM uint32_t CTRL; /*!< Offset: 0x004 DTRNG Control */
__IOM uint32_t POST_CTRL; /*!< Offset: 0x008 DTRNG Post Processor Control */
__IOM uint32_t FIFO_CTRL; /*!< Offset: 0x00C DTRNG FIFO Control */
__IOM uint32_t FIFO_0; /*!< Offset: 0x010 DTRNG FIFO */
} BP_DTRNG_TypeDef;
/*------------- Flash Control (FLASH) ----------------------------------------*/
typedef struct {
__IOM uint32_t FRWCON0; /*!< Offset: 0x000 Flash R/W Control Register */
__IOM uint32_t FSHSTAT; /*!< Offset: 0x004 Flash Status Register */
uint32_t RESERVED1[2];
__IOM uint32_t PROTCON; /*!< Offset: 0x010 Protection Control Register */
__IM uint32_t PROTMON; /*!< Offset: 0x014 Protection Monitoring Register */
uint32_t RESERVED2[2];
__IOM uint32_t DCYCRDCON; /*!< Offset: 0x020 DCYCREAD Control Register */
uint32_t RESERVED3[3];
__IOM uint32_t LDTCON; /*!< Offset: 0x030 LDTCON Register for Test Mode Only */
__IOM uint32_t FSHCON0; /*!< Offset: 0x034 Flash Test Register #1 */
__IOM uint32_t FECCCON; /*!< Offset: 0x038 Flash Test Register #2 */
__IM uint32_t FECCFADR; /*!< Offset: 0x03C ECC Fault Address */
__IOM uint32_t DCT0; /*!< Offset: 0x040 DCT0 Option Register */
__IOM uint32_t DCT1; /*!< Offset: 0x044 DCT1 Option Register */
uint32_t RESERVED4[2];
__IOM uint32_t LDT0; /*!< Offset: 0x050 LDT0 Option Register */
__IOM uint32_t LDT1; /*!< Offset: 0x054 LDT1 Option Register */
__IOM uint32_t LDT2; /*!< Offset: 0x058 LDT2 Option Register */
__IOM uint32_t LDT3; /*!< Offset: 0x05C LDT3 Option Register */
__IM uint32_t MODE; /*!< Offset: 0x060 MODECELL Option Register */
__IM uint32_t CPA0; /*!< Offset: 0x064 CPA0 Option Register */
__IM uint32_t BPU; /*!< Offset: 0x068 BPU Option Register */
uint32_t RESERVED5[9];
__IOM uint32_t RED0; /*!< Offset: 0x090 RED0 Option Register */
__IOM uint32_t RED0_MBIT; /*!< Offset: 0x094 RED0 User Mode Register */
__IOM uint32_t RED1; /*!< Offset: 0x098 RED1 Option Register */
__IOM uint32_t RED1_MBIT; /*!< Offset: 0x09C RED1 User Mode Register */
__IOM uint32_t RED2; /*!< Offset: 0x0A0 RED2 Option Register */
__IOM uint32_t RED2_MBIT; /*!< Offset: 0x0A4 RED2 User Mode Register */
__IOM uint32_t RED3; /*!< Offset: 0x0A8 RED3 Option Register */
__IOM uint32_t RED3_MBIT; /*!< Offset: 0x0AC RED3 User Mode Register */
} BP_FLASH_TypeDef;
/*------------- System Control (SYSCTRL) -------------------------------------*/
typedef struct {
uint32_t RESERVED1;
__IOM uint32_t PMUCTRL; /*!< Offset: 0x004 Control PMU feature of system */
__IOM uint32_t RESETOP; /*!< Offset: 0x008 Determine reset function at LOCKUP state */
uint32_t RESERVED2;
__IOM uint32_t RSTINFO; /*!< Offset: 0x010 Reset information of system */
} BP_SYSCTRL_TypeDef;
/*------------- Serial Flash Control (SFLASH) --------------------------------------*/
typedef struct {
__IOM uint32_t CALL; /*!< Offset: 0x000 Call Register */
__IOM uint32_t SFCON0; /*!< Offset: 0x004 Control Register */
__IOM uint32_t ARM_MODE; /*!< Offset: 0x008 ARM Mode Register */
__IOM uint32_t THUMB_MODE; /*!< Offset: 0x00C Thumb Mode Register */
__IOM uint32_t ERASE_ADDRESS; /*!< Offset: 0x010 Erase Address Register */
__IOM uint32_t PROT_ADDRESS; /*!< Offset: 0x014 Protect Address Register */
uint32_t RESERVED0;
__IOM uint32_t CMD0; /*!< Offset: 0x01C Command 0 Register */
__IOM uint32_t CMD1; /*!< Offset: 0x020 Command 1 Register */
__IOM uint32_t CMD2; /*!< Offset: 0x024 Command 2 Register */
__IOM uint32_t CMD3; /*!< Offset: 0x028 Command 3 Register */
__IOM uint32_t CMD4; /*!< Offset: 0x02C Command 4 Register */
uint32_t RESERVED1[19];
__IOM uint32_t CMD5; /*!< Offset: 0x07C (R/W) SFLASH Command 5 Register */
} BP_SFLASH_TypeDef;
/*----- Samsung Reconfigurable Processor Special Function Register (SlimSRP) -----*/
typedef struct {
__IM uint32_t PROC_ID; /*!< Offset: 0x0000 Processor ID */
uint32_t RESERVED1[63];
__IM uint32_t PROC_STAT; /*!< Offset: 0x0100 Processor Status */
__OM uint32_t PROC_PAUSE; /*!< Offset: 0x0104 Processor Pause */
uint32_t RESERVED2[961];
__IOM uint32_t TCM_INIT; /*!< Offset: 0x100C TCM_INIT */
__IOM uint32_t SRP_INTR; /*!< Offset: 0x1010 SRP_INTR */
__IOM uint32_t SRP_RESULT; /*!< Offset: 0x1014 SRP_RESULT */
__IOM uint32_t SRP_PARAM0; /*!< Offset: 0x1018 SRP_PARAM0 */
__IOM uint32_t SRP_PARAM1; /*!< Offset: 0x101C SRP_PARAM1 */
__IOM uint32_t SRP_PARAM2; /*!< Offset: 0x1020 SRP_PARAM2 */
__IOM uint32_t SRP_PARAM3; /*!< Offset: 0x1024 SRP_PARAM3 */
uint32_t RESERVED3[5110];
__IOM uint32_t CNT_CFG; /*!< Offset: 0x6000 CNT_CFG */
uint32_t RESERVED4[3];
__IOM uint32_t CNT_FR_L; /*!< Offset: 0x6010 CNT_FR_L */
__IOM uint32_t CNT_FR_H; /*!< Offset: 0x6014 CNT_FR_H */
__IOM uint32_t CNT_ST_L; /*!< Offset: 0x6018 CNT_ST_L */
__IOM uint32_t CNT_ST_H; /*!< Offset: 0x601C CNT_ST_H */
uint32_t RESERVED5[1016];
__IM uint32_t SRP_PC; /*!< Offset: 0x7000 SRP_PC */
} BP_SRP_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Peripheral, Flash, Serial Flash and SRAM base address */
#define BP_FLASH_BASE (0x00000000UL) /*!< (Flash ) Base Address */
#define BP_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
#define BP_APB_BASE (0x40000000UL) /*!< (APB ) Base Address */
#define BP_AHB_BASE (0x40020000UL) /*!< (AHB ) Base Address */
#define BP_SFLASH_BASE (0x60000000UL) /*!< (Serial Flash ) Base Address */
#define BP_SRP_DSPM_BASE (0x80000000UL) /*!< (SRP DSPM ) Base Address */
#define BP_SRP_TDM_BASE (0x80070000UL) /*!< (SRP TCM ) Base Address */
/* Peripheral memory map */
#define BP_TIMER0_BASE (BP_APB_BASE + 0x00000UL) /*!< (Timer0 ) Base Address */
#define BP_TIMER1_BASE (BP_APB_BASE + 0x01000UL) /*!< (Timer1 ) Base Address */
#define BP_TIMER2_BASE (BP_APB_BASE + 0x02000UL) /*!< (Timer2 ) Base Address */
#define BP_TIMER3_BASE (BP_APB_BASE + 0x03000UL) /*!< (Timer3 ) Base Address */
#define BP_TIMER4_BASE (BP_APB_BASE + 0x04000UL) /*!< (Timer4 ) Base Address */
#define BP_TIMER5_BASE (BP_APB_BASE + 0x05000UL) /*!< (Timer5 ) Base Address */
#define BP_TIMER6_BASE (BP_APB_BASE + 0x06000UL) /*!< (Timer6 ) Base Address */
#define BP_TIMER7_BASE (BP_APB_BASE + 0x07000UL) /*!< (Timer7 ) Base Address */
#define BP_PWM_TIMER_BASE (BP_APB_BASE + 0x07000UL) /*!< (PWM Timer ) Base Address */
#define BP_DUAL_TIMER0_BASE (BP_APB_BASE + 0x08000UL) /*!< (Dual Timer0 ) Base Address */
#define BP_DUAL_TIMER1_BASE (BP_APB_BASE + 0x08020UL) /*!< (Dual Timer1 ) Base Address */
#define BP_WATCHDOG_BASE (BP_APB_BASE + 0x09000UL) /*!< (Watchdog Timer ) Base Address */
#define BP_UART0_BASE (BP_APB_BASE + 0x0A000UL) /*!< (UART0 ) Base Address */
#define BP_UART1_BASE (BP_APB_BASE + 0x0B000UL) /*!< (UART1 ) Base Address */
#define BP_UART2_BASE (BP_APB_BASE + 0x0C000UL) /*!< (UART2 ) Base Address */
#define BP_SPI0_BASE (BP_APB_BASE + 0x0D000UL) /*!< (SPI0 ) Base Address */
#define BP_SPI1_BASE (BP_APB_BASE + 0x0E000UL) /*!< (SPI1 ) Base Address */
#define BP_SPI2_BASE (BP_APB_BASE + 0x0F000UL) /*!< (SPI2 ) Base Address */
#define BP_SPI3_BASE (BP_APB_BASE + 0x10000UL) /*!< (SPI3 ) Base Address */
#define BP_SPI4_BASE (BP_APB_BASE + 0x11000UL) /*!< (SPI4 ) Base Address */
#define BP_I2C0_BASE (BP_APB_BASE + 0x12000UL) /*!< (I2C0 ) Base Address */
#define BP_I2C1_BASE (BP_APB_BASE + 0x13000UL) /*!< (I2C1 ) Base Address */
#define BP_I2C2_BASE (BP_APB_BASE + 0x14000UL) /*!< (I2C2 ) Base Address */
#define BP_I2C3_BASE (BP_APB_BASE + 0x15000UL) /*!< (I2C3 ) Base Address */
#define BP_I2C4_BASE (BP_APB_BASE + 0x16000UL) /*!< (I2C4 ) Base Address */
#define BP_DELAY_MON_BASE (BP_APB_BASE + 0x17000UL) /*!< (Delay Monitor ) Base Address */
#define BP_RTC_BASE (BP_APB_BASE + 0x19000UL) /*!< (Real-Time Counter ) Base Address */
#define BP_AFE_BASE (BP_APB_BASE + 0x1A000UL) /*!< (AFE TOP ) Base Address */
#define BP_DMA_BASE (BP_APB_BASE + 0x1B000UL) /*!< (DMA ) Base Address */
#define BP_SYSCON_BASE (BP_APB_BASE + 0x1C000UL) /*!< (System Control ) Base Address */
#define BP_SRC_BASE (BP_APB_BASE + 0x1D000UL) /*!< (Sample Rate Converter ) Base Address */
#define BP_GPIO0_BASE (BP_AHB_BASE + 0x00000UL) /*!< (GPIO0 ) Base Address */
#define BP_GPIO1_BASE (BP_AHB_BASE + 0x01000UL) /*!< (GPIO1 ) Base Address */
#define BP_GPIO2_BASE (BP_AHB_BASE + 0x02000UL) /*!< (GPIO2 ) Base Address */
#define BP_AES_BASE (BP_AHB_BASE + 0x03000UL) /*!< (AES ) Base Address */
#define BP_DTRNG_BASE (BP_AHB_BASE + 0x04000UL) /*!< (DTRNG ) Base Address */
#define BP_FLASH_CTRL_BASE (BP_AHB_BASE + 0x05000UL) /*!< (Flash Controller ) Base Address */
#define BP_SYSCTRL_BASE (BP_AHB_BASE + 0x0F000UL) /*!< (System Controller ) Base Address */
#define BP_SFLASH_CTRL_BASE (0x70000000UL) /*!< (Serial Flash Controller) Base Address */
#define BP_SRP_SFR_BASE (0x80078000UL) /*!< (SRP SFR ) Base Address */
#define BP_AFE_TOP_BASE (BP_AFE_BASE + 0x000UL) /*!< (AFE TOP ) Base Address */
#define BP_AFE_ECG_BASE (BP_AFE_BASE + 0x100UL) /*!< (AFE ECG ) Base Address */
#define BP_AFE_PPG_BASE (BP_AFE_BASE + 0x200UL) /*!< (AFE PPG ) Base Address */
#define BP_AFE_BIA_BASE (BP_AFE_BASE + 0x300UL) /*!< (AFE BIA ) Base Address */
#define BP_AFE_GSR_BASE (BP_AFE_BASE + 0x400UL) /*!< (AFE GSR ) Base Address */
#define BP_ADC_FIFO_BASE (BP_AFE_BASE + 0x500UL) /*!< (ADC_FIFO ) Base Address */
#define BP_ADC_CON_BASE (BP_AFE_BASE + 0x600UL) /*!< (ADC_CON ) Base Address */
#define BP_SDADC_CON_BASE (BP_AFE_BASE + 0x700UL) /*!< (SDADC_CON ) Base Address */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define BP_TIMER0 ((BP_TIMER_TypeDef *) BP_TIMER0_BASE)
#define BP_TIMER1 ((BP_TIMER_TypeDef *) BP_TIMER1_BASE)
#define BP_TIMER2 ((BP_TIMER_TypeDef *) BP_TIMER2_BASE)
#define BP_TIMER3 ((BP_TIMER_TypeDef *) BP_TIMER3_BASE)
#define BP_TIMER4 ((BP_TIMER_TypeDef *) BP_TIMER4_BASE)
#define BP_TIMER5 ((BP_TIMER_TypeDef *) BP_TIMER5_BASE)
#define BP_TIMER6 ((BP_TIMER_TypeDef *) BP_TIMER6_BASE)
#define BP_TIMER7 ((BP_TIMER_TypeDef *) BP_TIMER7_BASE)
#define BP_PWM_TIMER ((BP_PWM_TIMER_TypeDef *) BP_PWM_TIMER_BASE)
#define BP_DUAL_TIMER0 ((BP_DUAL_TIMER_TypeDef *) BP_DUAL_TIMER0_BASE)
#define BP_DUAL_TIMER1 ((BP_DUAL_TIMER_TypeDef *) BP_DUAL_TIMER1_BASE)
#define BP_WATCHDOG ((BP_WATCHDOG_TypeDef *) BP_WATCHDOG_BASE)
#define BP_UART0 ((BP_UART_TypeDef *) BP_UART0_BASE)
#define BP_UART1 ((BP_UART_TypeDef *) BP_UART1_BASE)
#define BP_UART2 ((BP_UART_TypeDef *) BP_UART2_BASE)
#define BP_SPI0 ((BP_SPI_TypeDef *) BP_SPI0_BASE)
#define BP_SPI1 ((BP_SPI_TypeDef *) BP_SPI1_BASE)
#define BP_SPI2 ((BP_SPI_TypeDef *) BP_SPI2_BASE)
#define BP_SPI3 ((BP_SPI_TypeDef *) BP_SPI3_BASE)
#define BP_SPI4 ((BP_SPI_TypeDef *) BP_SPI4_BASE)
#define BP_I2C0 ((BP_I2C_TypeDef *) BP_I2C0_BASE)
#define BP_I2C1 ((BP_I2C_TypeDef *) BP_I2C1_BASE)
#define BP_I2C2 ((BP_I2C_TypeDef *) BP_I2C2_BASE)
#define BP_I2C3 ((BP_I2C_TypeDef *) BP_I2C3_BASE)
#define BP_I2C4 ((BP_I2C_TypeDef *) BP_I2C4_BASE)
#define BP_DELAY_MON ((BP_DELAY_MON_TypeDef *) BP_DELAY_MON_BASE)
#define BP_RTC ((BP_RTC_TypeDef *) BP_RTC_BASE)
#define BP_AFE_TOP ((BP_AFE_TOP_TypeDef *) BP_AFE_TOP_BASE)
#define BP_AFE_ECG ((BP_AFE_ECG_TypeDef *) BP_AFE_ECG_BASE)
#define BP_AFE_PPG ((BP_AFE_PPG_TypeDef *) BP_AFE_PPG_BASE)
#define BP_AFE_BIA ((BP_AFE_BIA_TypeDef *) BP_AFE_BIA_BASE)
#define BP_AFE_GSR ((BP_AFE_GSR_TypeDef *) BP_AFE_GSR_BASE)
#define BP_ADC_FIFO ((BP_ADC_FIFO_TypeDef *) BP_ADC_FIFO_BASE)
#define BP_ADC_CON ((BP_ADC_CON_TypeDef *) BP_ADC_CON_BASE)
#define BP_SDADC_CON ((BP_SDADC_CON_TypeDef *) BP_SDADC_CON_BASE)
#define BP_DMA ((BP_DMA_TypeDef *) BP_DMA_BASE)
#define BP_SYSCON ((BP_SYSCON_TypeDef *) BP_SYSCON_BASE)
#define BP_SRC ((BP_SRC_TypeDef *) BP_SRC_BASE)
#define BP_GPIO0 ((BP_GPIO_TypeDef *) BP_GPIO0_BASE)
#define BP_GPIO1 ((BP_GPIO_TypeDef *) BP_GPIO1_BASE)
#define BP_GPIO2 ((BP_GPIO_TypeDef *) BP_GPIO2_BASE)
#define BP_AES ((BP_AES_TypeDef *) BP_AES_BASE)
#define BP_DTRNG ((BP_DTRNG_TypeDef *) BP_DTRNG_BASE)
#define BP_FLASH ((BP_FLASH_TypeDef *) BP_FLASH_CTRL_BASE)
#define BP_SYSCTRL ((BP_SYSCTRL_TypeDef *) BP_SYSCTRL_BASE)
#define BP_SFLASH ((BP_SFLASH_TypeDef *) BP_SFLASH_CTRL_BASE)
#define BP_SRP ((BP_SRP_TypeDef *) BP_SRP_SFR_BASE)
#define BP_SFLASH_ADDR_CMD ((uint8_t *) BP_SFLASH_CTRL_BASE + 0x59UL)
#define BP_SFALSH_SECTOR_ERASE ((uint8_t *) BP_SFLASH_CTRL_BASE + 0x5EUL)
#define BP_SFALSH_MODE ((uint8_t *) BP_SFLASH_CTRL_BASE + 0x74UL)
#define BP_SFALSH_RDID ((uint8_t *) BP_SFLASH_CTRL_BASE + 0xACUL)
#define BP_SFALSH_BLOCK_ERASE ((uint8_t *) BP_SFLASH_CTRL_BASE + 0xBEUL)
#define BP_SFALSH_CHIP_ERASE ((uint8_t *) BP_SFLASH_CTRL_BASE + 0xCEUL)
#define BP_SFALSH_RDSR ((uint8_t *) BP_SFLASH_CTRL_BASE + 0xDCUL)
#define BP_SFLASH_WRDI ((uint8_t *) BP_SFLASH_CTRL_BASE + 0xDDUL)
#define BP_SFALSH_WRSR ((uint8_t *) BP_SFLASH_CTRL_BASE + 0xDEUL)
#define BP_SFALSH_WREN ((uint8_t *) BP_SFLASH_CTRL_BASE + 0xEEUL)
#define BP_SFALSH_PROT_DIS ((uint8_t *) BP_SFLASH_CTRL_BASE + 0xF0UL)
#define BP_SFALSH_PROT_EN ((uint8_t *) BP_SFLASH_CTRL_BASE + 0xF1UL)
#endif /* __S1SBP6A_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include <stdbool.h>
#include "s1sbp6a.h"
#include "s1sbp6a_type.h"
#include "s1sbp6a_cmu.h"
void bp6a_cmu_set_mcu_clock_gate_bypass(bool en)
{
modifyreg32(&BP_SYSCON->MCU_CLK_GATE, CMU_MCU_CLK_GATE_BYPASS_MASK, CMU_MCU_CLK_GATE_BYPASS(en));
}
void bp6a_cmu_set_mcu_clock_src(cmu_src_clk_t clock)
{
modifyreg32(&BP_SYSCON->MCU_CLK_CTRL, CMU_MCU_CLK_CTRL_SEL_MCU_SRC_MASK,
CMU_MCU_CLK_CTRL_SEL_MCU_SRC(clock));
}
uint32_t bp6a_cmu_get_mcu_clock_src(void)
{
return (cmu_src_clk_t)(getreg32(&BP_SYSCON->MCU_CLK_CTRL) &
CMU_MCU_CLK_CTRL_SEL_MCU_SRC_MASK);
}
uint32_t bp6a_get_mcu_src_clock_freq(void)
{
uint32_t clk_ctrl = 0;
clk_ctrl = getreg32(&BP_SYSCON->MCU_CLK_CTRL) & CMU_MCU_CLK_CTRL_SEL_MCU_SRC_MASK;
if (clk_ctrl == CMU_SRC_CLK_LSOSC) {
return LSOSC_CLK_FREQ;
} else if (clk_ctrl == CMU_SRC_CLK_EXT_4M) {
return EXT_CLK_FREQ;
} else if (clk_ctrl == CMU_SRC_CLK_HSOSC) {
return HSOSC_CLK_FREQ;
} else {
return EXT_CLK_FREQ * CMU_PLL_AMP_GAIN;
}
}
void bp6a_cmu_set_peri_clock_src(cmu_src_clk_t clock)
{
modifyreg32(&BP_SYSCON->PERI_CLK_CTRL, CMU_PERI_CLK_CTRL_SEL_SRC_MASK,
CMU_PERI_CLK_CTRL_SEL_SRC(clock));
}
uint32_t bp6a_cmu_get_peri_clock_src(void)
{
uint32_t clk_ctrl = 0;
clk_ctrl = getreg32(&BP_SYSCON->PERI_CLK_CTRL) & CMU_PERI_CLK_CTRL_SEL_SRC_MASK;
if (clk_ctrl == CMU_SRC_CLK_LSOSC) {
return LSOSC_CLK_FREQ;
} else if (clk_ctrl == CMU_SRC_CLK_EXT_4M) {
return EXT_CLK_FREQ;
} else if (clk_ctrl == CMU_SRC_CLK_HSOSC) {
return HSOSC_CLK_FREQ;
} else {
return EXT_CLK_FREQ * CMU_PLL_AMP_GAIN;
}
}
uint32_t bp6a_cmu_get_afe_con_clock_freq(void)
{
uint32_t clk_ctrl = 0;
clk_ctrl = getreg32(&BP_SYSCON->AFE_CLK_CTRL) & CMU_MCU_CLK_CTRL_SEL_MCU_SRC_MASK;
if (clk_ctrl == CMU_SRC_CLK_LSOSC) {
return LSOSC_CLK_FREQ;
} else if (clk_ctrl == CMU_SRC_CLK_HSOSC) {
return HSOSC_CLK_FREQ;
} else {
return EXT_CLK_FREQ;
}
}
void bp6a_set_muc_clock_div(uint32_t div)
{
modifyreg32(&BP_SYSCON->MCU_CLK_CTRL,
CMU_MCU_CLK_CTRL_AHBCLK_DIV_MASK |
CMU_MCU_CLK_CTRL_APBCLK_DIV_MASK |
CMU_MCU_CLK_CTRL_SRPCLK_DIV_MASK,
CMU_MCU_CLK_CTRL_AHBCLK_DIV(div) |
CMU_MCU_CLK_CTRL_APBCLK_DIV(div) |
CMU_MCU_CLK_CTRL_SRPCLK_DIV(div));
}
void bp6a_cmu_peri_clock_div(uint32_t div)
{
modifyreg32(&BP_SYSCON->PERI_CLK_CTRL, CMU_PERI_CLK_CTRL_CLK_DIV_MASK, CMU_PERI_CLK_CTRL_CLK_DIV(div));
}
uint32_t bp6a_cmu_get_pri_clock_div(void)
{
uint32_t clk_ctrl = 0;
clk_ctrl = getreg32(&BP_SYSCON->PERI_CLK_CTRL);
return ((clk_ctrl & CMU_PERI_CLK_CTRL_CLK_DIV_MASK) >> CMU_PERI_CLK_CTRL_CLK_DIV_SHIFT);
}
uint32_t bp6a_cmu_get_ahb_clock_div(void)
{
uint32_t clk_ctrl = 0;
clk_ctrl = getreg32(&BP_SYSCON->MCU_CLK_CTRL);
return ((clk_ctrl & CMU_MCU_CLK_CTRL_AHBCLK_DIV_MASK) & CMU_MCU_CLK_CTRL_AHBCLK_DIV_SHIFT);
}
uint32_t bp6a_cmu_get_apb_clock_div(void)
{
uint32_t clk_ctrl = 0;
clk_ctrl = getreg32(&BP_SYSCON->MCU_CLK_CTRL);
return ((clk_ctrl & CMU_MCU_CLK_CTRL_APBCLK_DIV_MASK) >> CMU_MCU_CLK_CTRL_APBCLK_DIV_SHIFT);
}
uint32_t bp6a_cmu_get_srp_clock_div(void)
{
uint32_t clk_ctrl = 0;
clk_ctrl = getreg32(&BP_SYSCON->MCU_CLK_CTRL);
return ((clk_ctrl & CMU_MCU_CLK_CTRL_SRPCLK_DIV_MASK) >> CMU_MCU_CLK_CTRL_SRPCLK_DIV_SHIFT);
}
uint32_t bp6a_cmu_get_afe_smp_clock_div(void)
{
uint32_t clk_ctrl = 0;
clk_ctrl = getreg32(&BP_SYSCON->AFE_CLK_CTRL);
return ((clk_ctrl & CMU_AFE_CLK_CTRL_SMP_CLK_DIV_MASK) >> CMU_AFE_CLK_CTRL_SMP_CLK_DIV_SHIFT);
}
int bp6a_cmu_enable_clock(cmu_clock_t clock, bool en)
{
if ((clock < CMU_FCLK_AHBCLK) || (clock >= CMU_CLK_INVALID)) {
return -1;
}
if (clock <= CMU_WATCHDOG_APBCLK) {
#ifdef CMU_CTRL_UDMA_C
if (clock == CMU_UDMAC_AHBCLK) {
if (en) {
modifyreg32(&(BP_SYSCON->MCU_CLK_GATE), CMU_MCU_CLK_GATE_UDMAC_ACG_MASK, CMU_MCU_CLK_GATE_UDMAC_ACG(en));
modifyreg32(&(BP_SYSCON->MCU_CLK_GATE), 0x01 << (clock - CMU_FCLK_AHBCLK), en << (clock - CMU_FCLK_AHBCLK));
} else {
modifyreg32(&(BP_SYSCON->MCU_CLK_GATE), 0x01 << (clock - CMU_FCLK_AHBCLK), en << (clock - CMU_FCLK_AHBCLK));
modifyreg32(&(BP_SYSCON->MCU_CLK_GATE), CMU_MCU_CLK_GATE_UDMAC_ACG_MASK, CMU_MCU_CLK_GATE_UDMAC_ACG(en));
}
} else
#endif
modifyreg32(&(BP_SYSCON->MCU_CLK_GATE), 0x01 << (clock - CMU_FCLK_AHBCLK), en << (clock - CMU_FCLK_AHBCLK));
} else {
modifyreg32(&(BP_SYSCON->PERI_CLK_GATE), 0x01 << (clock - CMU_UART0_CLK), en << (clock - CMU_UART0_CLK));
}
return 0;
}
int bp6a_cmu_set_peri_clock_mux(cmu_clock_t clock, cmu_mux_peri_clock_t mux)
{
if ((clock < CMU_UART0_CLK) || (clock >= CMU_CLK_INVALID)) {
return -1;
}
modifyreg32(&BP_SYSCON->PERI_CLK_MUX, 0x01 << (clock - CMU_UART0_CLK), mux << (clock - CMU_UART0_CLK));
return 0;
}
cmu_mux_peri_clock_t CMU_GetClockMux(cmu_clock_t clock)
{
uint32_t clk_mux = 0;
clk_mux = getreg32(&BP_SYSCON->PERI_CLK_MUX);
return (cmu_mux_peri_clock_t)((clk_mux >> (clock - CMU_UART0_CLK)) & 0x01);
}
void bp6a_cmu_set_smp_clock_src(cmu_sel_smp_clk_t clock)
{
modifyreg32(&BP_SYSCON->AFE_CLK_CTRL, CMU_AFE_CLK_CTRL_SEL_AFECON32_MASK,
CMU_AFE_CLK_CTRL_SEL_AFECON32(clock));
}
static void bp6a_cmu_set_hsosc_cal(uint8_t mode, uint8_t cal, uint8_t tol)
{
modifyreg32(&BP_SYSCON->HSOSC_CTRL,
CMU_HOSC_CTRL_MODE_MASK |
CMU_HOSC_CTRL_CAL_MASK |
CMU_HOSC_CTRL_TOL_MASK,
CMU_HOSC_CTRL_MODE(mode) |
CMU_HOSC_CTRL_CAL(cal) |
CMU_HOSC_CTRL_TOL(tol));
}
static void bp6a_cmu_set_lsosc_cal(uint8_t mode, uint8_t cal, uint8_t tol)
{
modifyreg32(&BP_SYSCON->LSOSC_CTRL,
CMU_HOSC_CTRL_MODE_MASK |
CMU_HOSC_CTRL_CAL_MASK |
CMU_HOSC_CTRL_TOL_MASK,
CMU_HOSC_CTRL_MODE(mode) |
CMU_HOSC_CTRL_CAL(cal) |
CMU_HOSC_CTRL_TOL(tol));
}
static uint32_t bp6a_cmu_get_clock_div(cmu_clock_t clock)
{
uint32_t mux;
switch (clock) {
case CMU_SAMPLE_CLK_AFTER_DIV:
return bp6a_cmu_get_afe_con_clock_freq();
case CMU_SRPCLK_AFTER_DIV:
return bp6a_cmu_get_srp_clock_div();
case CMU_AHBCLK_AFTER_DIV:
return bp6a_cmu_get_ahb_clock_div();
case CMU_APBCLK_AFTER_DIV:
return bp6a_cmu_get_apb_clock_div();
case CMU_PERICLK_AFTER_DIV:
return bp6a_cmu_get_pri_clock_div();
case CMU_SRP_SRPCLK:
return bp6a_cmu_get_srp_clock_div();
case CMU_FCLK_AHBCLK:
case CMU_GPIO_AHBCLK:
case CMU_UDMAC_AHBCLK:
case CMU_DTRNG_AHBCLK:
case CMU_AES_AHBCLK:
case CMU_SRC_AHBCLK:
case CMU_QSPI_AHBCLK:
return bp6a_cmu_get_ahb_clock_div();
case CMU_TIMER0_APBCLK:
case CMU_TIMER1_APBCLK:
case CMU_TIMER2_APBCLK:
case CMU_TIMER3_APBCLK:
case CMU_TIMER4_APBCLK:
case CMU_TIMER5_APBCLK:
case CMU_TIMER6_APBCLK:
case CMU_PWMTIMER_APBCLK:
case CMU_DUALTIMER_APBCLK:
case CMU_WATCHDOG_APBCLK:
return bp6a_cmu_get_apb_clock_div();
case CMU_UART0_CLK:
case CMU_UART1_CLK:
case CMU_UART2_CLK:
case CMU_SPI0_CLK:
case CMU_SPI1_CLK:
case CMU_SPI2_CLK:
case CMU_SPI3_CLK:
case CMU_SPI4_CLK:
case CMU_I2C0_CLK:
case CMU_I2C1_CLK:
case CMU_I2C2_CLK:
case CMU_I2C3_CLK:
case CMU_I2C4_CLK:
mux = CMU_GetClockMux(clock);
if (mux == CMU_MUX_MCU_CLK) {
return bp6a_cmu_get_apb_clock_div();
} else { //(CMU_MUX_MCU_CLK == CMU_MUX_PERI_CLK)
return bp6a_cmu_get_pri_clock_div();
}
default:
break;
}
return 0;
}
bool bp6a_cmu_get_clock_enabled(cmu_clock_t clock)
{
if (clock <= CMU_WATCHDOG_APBCLK) {
return ((getreg32(&BP_SYSCON->MCU_CLK_GATE) >> (clock - CMU_FCLK_AHBCLK)) & 0x01);
} else {
return ((getreg32(&BP_SYSCON->PERI_CLK_GATE) >> (clock - CMU_UART0_CLK)) & 0x01);
}
}
uint32_t bp6a_get_clock_src_freq(cmu_clock_t clock)
{
uint32_t mux;
switch (clock) {
case CMU_SAMPLE_CLK_AFTER_DIV:
return bp6a_cmu_get_afe_con_clock_freq();
case CMU_SRPCLK_AFTER_DIV:
return bp6a_get_mcu_src_clock_freq();
case CMU_AHBCLK_AFTER_DIV:
return bp6a_get_mcu_src_clock_freq();
case CMU_APBCLK_AFTER_DIV:
return bp6a_get_mcu_src_clock_freq();
case CMU_PERICLK_AFTER_DIV:
return bp6a_cmu_get_peri_clock_src();
case CMU_SRP_SRPCLK:
if (bp6a_cmu_get_clock_enabled(clock)) {
return bp6a_get_mcu_src_clock_freq();
} else {
return 0;
}
case CMU_FCLK_AHBCLK:
case CMU_GPIO_AHBCLK:
case CMU_UDMAC_AHBCLK:
case CMU_DTRNG_AHBCLK:
case CMU_AES_AHBCLK:
case CMU_SRC_AHBCLK:
case CMU_QSPI_AHBCLK:
if (bp6a_cmu_get_clock_enabled(clock)) {
return bp6a_get_mcu_src_clock_freq();
} else {
return 0;
}
case CMU_TIMER0_APBCLK:
case CMU_TIMER1_APBCLK:
case CMU_TIMER2_APBCLK:
case CMU_TIMER3_APBCLK:
case CMU_TIMER4_APBCLK:
case CMU_TIMER5_APBCLK:
case CMU_TIMER6_APBCLK:
case CMU_PWMTIMER_APBCLK:
case CMU_DUALTIMER_APBCLK:
case CMU_WATCHDOG_APBCLK:
if (bp6a_cmu_get_clock_enabled(clock)) {
return bp6a_get_mcu_src_clock_freq();
} else {
return 0;
}
case CMU_UART0_CLK:
case CMU_UART1_CLK:
case CMU_UART2_CLK:
case CMU_SPI0_CLK:
case CMU_SPI1_CLK:
case CMU_SPI2_CLK:
case CMU_SPI3_CLK:
case CMU_SPI4_CLK:
case CMU_I2C0_CLK:
case CMU_I2C1_CLK:
case CMU_I2C2_CLK:
case CMU_I2C3_CLK:
case CMU_I2C4_CLK:
if (bp6a_cmu_get_clock_enabled(clock)) {
mux = CMU_GetClockMux(clock);
if (mux == CMU_MUX_MCU_CLK) {
return bp6a_get_mcu_src_clock_freq();
} else { //(CMU_MUX_MCU_CLK == CMU_MUX_PERI_CLK)
return bp6a_cmu_get_peri_clock_src();
}
} else {
return 0;
}
default:
break;
}
return 0;
}
uint32_t bp6a_cmu_get_clock_freq(cmu_clock_t clock)
{
uint32_t src_clk = 0;
uint32_t clk_div = 0;
if (clock >= CMU_CLK_INVALID) {
return 0;
}
src_clk = bp6a_get_clock_src_freq(clock);
clk_div = bp6a_cmu_get_clock_div(clock);
if (clk_div == 0) {
clk_div = 1;
}
return (uint32_t)(src_clk / clk_div);
}
void bp6a_cmu_init(cmu_src_clk_t mcu_clk, cmu_src_clk_t peri_clk)
{
int i;
bp6a_set_muc_clock_div(1);
bp6a_cmu_set_mcu_clock_src(mcu_clk);
bp6a_cmu_peri_clock_div(1);
bp6a_cmu_set_peri_clock_src(peri_clk);
bp6a_cmu_set_hsosc_cal(1, 0, 0);
bp6a_cmu_set_lsosc_cal(1, 0, 0);
bp6a_cmu_set_mcu_clock_gate_bypass(false);
/* clock gate */
for (i = CMU_FCLK_AHBCLK ; i < CMU_I2C4_CLK; i++) {
bp6a_cmu_enable_clock(i, (INIT_CLOCK_CONFIG >> (i - CMU_FCLK_AHBCLK)) & 0x01);
}
/* internal OSC calibration enable */
modifyreg32(0x4001C60C, 0x2, 0x2);
modifyreg32(0x4001C610, 0x2, 0x2);
/* AFE Clock disable */
putreg32(0x4001A000, 0);
modifyreg32(0x4001A000, 0x08, 0x8);
}

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_CMU_H
#define __S1SBP6A_CMU_H
#define LSOSC_CLK_FREQ (4096000)
#define HSOSC_CLK_FREQ (LSOSC_CLK_FREQ * 6)
#define EXT_CLK_FREQ (4096000)
#define CMU_PLL_AMP_GAIN (25)
#define CMU_MCU_CLK_CTRL_OFFSET (0x0100)
#define CMU_MCU_CLK_GATE_OFFSET (0x0104)
#define CMU_PERI_CLK_CTRL_OFFSET (0x0110)
#define CMU_PERI_CLK_GATE_OFFSET (0x0114)
#define CMU_PERI_CLK_MUX_OFFSET (0x0118)
#define CMU_AFE_CLK_CTRL_OFFSET (0x0120)
#define CMU_HOSC_CTRL_OFFSET (0x060C)
#define CMU_WAIT_PERI_CLK_GATE_OFFSET (0x0918)
#define CMU_MCU_CLK_CTRL_SEL_MCU_SRC_SHIFT (0)
#define CMU_MCU_CLK_CTRL_AHBCLK_DIV_SHIFT (4)
#define CMU_MCU_CLK_CTRL_APBCLK_DIV_SHIFT (12)
#define CMU_MCU_CLK_CTRL_SRPCLK_DIV_SHIFT (20)
#define CMU_MCU_CLK_CTRL_SEL_MCU_SRC_MASK (0x03 << CMU_MCU_CLK_CTRL_SEL_MCU_SRC_SHIFT)
#define CMU_MCU_CLK_CTRL_AHBCLK_DIV_MASK (0xFF << CMU_MCU_CLK_CTRL_AHBCLK_DIV_SHIFT)
#define CMU_MCU_CLK_CTRL_APBCLK_DIV_MASK (0xFF << CMU_MCU_CLK_CTRL_APBCLK_DIV_SHIFT)
#define CMU_MCU_CLK_CTRL_SRPCLK_DIV_MASK (0xFF << CMU_MCU_CLK_CTRL_SRPCLK_DIV_SHIFT)
#define CMU_MCU_CLK_CTRL_SEL_MCU_SRC(c) ((c) << CMU_MCU_CLK_CTRL_SEL_MCU_SRC_SHIFT)
#define CMU_MCU_CLK_CTRL_AHBCLK_DIV(c) ((c) << CMU_MCU_CLK_CTRL_AHBCLK_DIV_SHIFT)
#define CMU_MCU_CLK_CTRL_APBCLK_DIV(c) ((c) << CMU_MCU_CLK_CTRL_APBCLK_DIV_SHIFT)
#define CMU_MCU_CLK_CTRL_SRPCLK_DIV(c) ((c) << CMU_MCU_CLK_CTRL_SRPCLK_DIV_SHIFT)
#define CMU_MCU_CLK_GATE_FCLK_SHIFT (0)
#define CMU_MCU_CLK_GATE_SRP_SHIFT (1)
#define CMU_MCU_CLK_GATE_GPIO_SHIFT (2)
#define CMU_MCU_CLK_GATE_UDMAC_SHIFT (3)
#define CMU_MCU_CLK_GATE_DTRNG_SHIFT (4)
#define CMU_MCU_CLK_GATE_AES_SHIFT (5)
#define CMU_MCU_CLK_GATE_SRC_SHIFT (6)
#define CMU_MCU_CLK_GATE_QSPI_SHIFT (7)
#define CMU_MCU_CLK_GATE_TIMER_SHIFT (8)
#define CMU_MCU_CLK_GATE_PTIMER_SHIFT (14)
#define CMU_MCU_CLK_GATE_DTIMER_SHIFT (16)
#define CMU_MCU_CLK_GATE_WATCHDOG_SHIFT (17)
#define CMU_MCU_CLK_GATE_UDMAC_ACG_SHIFT (18)
#define CMU_MCU_CLK_GATE_BYPASS_SHIFT (19)
#define CMU_MCU_CLK_GATE_FCLK_MASK (0x01 << CMU_MCU_CLK_GATE_FCLK_SHIFT)
#define CMU_MCU_CLK_GATE_SRP_MASK (0x01 << CMU_MCU_CLK_GATE_SRP_SHIFT)
#define CMU_MCU_CLK_GATE_GPIO_MASK (0x01 << CMU_MCU_CLK_GATE_GPIO_SHIFT)
#define CMU_MCU_CLK_GATE_UDMAC_MASK (0x01 << CMU_MCU_CLK_GATE_UDMAC_SHIFT)
#define CMU_MCU_CLK_GATE_DTRNG_MASK (0x01 << CMU_MCU_CLK_GATE_DTRNG_SHIFT)
#define CMU_MCU_CLK_GATE_AES_MASK (0x01 << CMU_MCU_CLK_GATE_AES_SHIFT)
#define CMU_MCU_CLK_GATE_SRC_MASK (0x01 << CMU_MCU_CLK_GATE_SRC_SHIFT)
#define CMU_MCU_CLK_GATE_QSPI_MASK (0x01 << CMU_MCU_CLK_GATE_QSPI_SHIFT)
#define CMU_MCU_CLK_GATE_TIMER_MASK (0x3F << CMU_MCU_CLK_GATE_TIMER_SHIFT)
#define CMU_MCU_CLK_GATE_PTIMER_MASK (0x03 << CMU_MCU_CLK_GATE_PTIMER_SHIFT)
#define CMU_MCU_CLK_GATE_DTIMER_MASK (0x01 << CMU_MCU_CLK_GATE_DTIMER_SHIFT)
#define CMU_MCU_CLK_GATE_WATCHDOG_MASK (0x01 << CMU_MCU_CLK_GATE_WATCHDOG_SHIFT)
#define CMU_MCU_CLK_GATE_UDMAC_ACG_MASK (0x01 << CMU_MCU_CLK_GATE_UDMAC_ACG_SHIFT)
#define CMU_MCU_CLK_GATE_BYPASS_MASK (0x01 << CMU_MCU_CLK_GATE_BYPASS_SHIFT)
#define CMU_MCU_CLK_GATE_FCLK(c) ((c) << CMU_MCU_CLK_GATE_FCLK_SHIFT)
#define CMU_MCU_CLK_GATE_SRP(c) ((c) << CMU_MCU_CLK_GATE_SRP_SHIFT)
#define CMU_MCU_CLK_GATE_GPIO(c) ((c) << CMU_MCU_CLK_GATE_GPIO_SHIFT)
#define CMU_MCU_CLK_GATE_UDMAC(c) ((c) << CMU_MCU_CLK_GATE_UDMAC_SHIFT)
#define CMU_MCU_CLK_GATE_DTRNG(c) ((c) << CMU_MCU_CLK_GATE_DTRNG_SHIFT)
#define CMU_MCU_CLK_GATE_AES(c) ((c) << CMU_MCU_CLK_GATE_AES_SHIFT)
#define CMU_MCU_CLK_GATE_SRC(c) ((c) << CMU_MCU_CLK_GATE_SRC_SHIFT)
#define CMU_MCU_CLK_GATE_QSPI(c) ((c) << CMU_MCU_CLK_GATE_QSPI_SHIFT)
#define CMU_MCU_CLK_GATE_TIMER(c) ((c) << CMU_MCU_CLK_GATE_TIMER_SHIFT)
#define CMU_MCU_CLK_GATE_PTIMER(c) ((c) << CMU_MCU_CLK_GATE_PTIMER_SHIFT)
#define CMU_MCU_CLK_GATE_DTIMER(c) ((c) << CMU_MCU_CLK_GATE_DTIMER_SHIFT)
#define CMU_MCU_CLK_GATE_WATCHDOG(c) ((c) << CMU_MCU_CLK_GATE_WATCHDOG_SHIFT)
#define CMU_MCU_CLK_GATE_UDMAC_ACG(c) ((c) << CMU_MCU_CLK_GATE_UDMAC_ACG_SHIFT)
#define CMU_MCU_CLK_GATE_BYPASS(c) ((c) << CMU_MCU_CLK_GATE_BYPASS_SHIFT)
#define CMU_AFE_CLK_CTRL_SEL_SRC_SHIFT (0)
#define CMU_AFE_CLK_CTRL_AFE_DIV_ON_SHIFT (2)
#define CMU_AFE_CLK_CTRL_SEL_AFECON32_SHIFT (3)
#define CMU_AFE_CLK_CTRL_SMP_CLK_DIV_SHIFT (4)
#define CMU_AFE_CLK_CTRL_SEL_SRC_MASK (0x03 << CMU_AFE_CLK_CTRL_SEL_SRC_SHIFT)
#define CMU_AFE_CLK_CTRL_AFE_DIV_ON_MASK (0x01 << CMU_AFE_CLK_CTRL_AFE_DIV_ON_SHIFT)
#define CMU_AFE_CLK_CTRL_SEL_AFECON32_MASK (0x01 << CMU_AFE_CLK_CTRL_SEL_AFECON32_SHIFT)
#define CMU_AFE_CLK_CTRL_SMP_CLK_DIV_MASK (0xFFFF << CMU_AFE_CLK_CTRL_SMP_CLK_DIV_SHIFT)
#define CMU_AFE_CLK_CTRL_SEL_SRC(c) ((c) << CMU_AFE_CLK_CTRL_SEL_SRC_SHIFT)
#define CMU_AFE_CLK_CTRL_AFE_DIV_ON(c) ((c) << CMU_AFE_CLK_CTRL_AFE_DIV_ON_SHIFT)
#define CMU_AFE_CLK_CTRL_SEL_AFECON32(c) ((c) << CMU_AFE_CLK_CTRL_SEL_AFECON32_SHIFT)
#define CMU_AFE_CLK_CTRL_SMP_CLK_DIV(c) ((c) << CMU_AFE_CLK_CTRL_SMP_CLK_DIV_SHIFT)
#define CMU_PERI_CLK_MUX_UARTCLK_MUX_SHIFT (0)
#define CMU_PERI_CLK_MUX_SPICLK_MUX_SHIFT (3)
#define CMU_PERI_CLK_MUX_I2CCLK_MUX_SHIFT (8)
#define CMU_PERI_CLK_MUX_UARTCLK_MUX_MASK (0x07 << CMU_PERI_CLK_MUX_UARTCLK_MUX_SHIFT)
#define CMU_PERI_CLK_MUX_SPICLK_MUX_MASK (0x0F << CMU_PERI_CLK_MUX_SPICLK_MUX_SHIFT)
#define CMU_PERI_CLK_MUX_I2CCLK_MUX_MASK (0x1F << CMU_PERI_CLK_MUX_I2CCLK_MUX_SHIFT)
#define CMU_PERI_CLK_MUX_UARTCLK_MUX(c) ((c) << CMU_PERI_CLK_MUX_UARTCLK_MUX_SHIFT)
#define CMU_PERI_CLK_MUX_SPICLK_MUX(c) ((c) << CMU_PERI_CLK_MUX_SPICLK_MUX_SHIFT)
#define CMU_PERI_CLK_MUX_UARTCLK_MUX_SHIFT (0)
#define CMU_PERI_CLK_MUX_SPICLK_MUX_SHIFT (3)
#define CMU_PERI_CLK_MUX_I2CCLK_MUX_SHIFT (8)
#define CMU_PERI_CLK_MUX_UARTCLK_MUX_MASK (0x07 << CMU_PERI_CLK_MUX_UARTCLK_MUX_SHIFT)
#define CMU_PERI_CLK_MUX_SPICLK_MUX_MASK (0x0F << CMU_PERI_CLK_MUX_SPICLK_MUX_SHIFT)
#define CMU_PERI_CLK_MUX_I2CCLK_MUX_MASK (0x1F << CMU_PERI_CLK_MUX_I2CCLK_MUX_SHIFT)
#define CMU_PERI_CLK_MUX_UARTCLK_MUX(c) ((c) << CMU_PERI_CLK_MUX_UARTCLK_MUX_SHIFT)
#define CMU_PERI_CLK_MUX_SPICLK_MUX(c) ((c) << CMU_PERI_CLK_MUX_SPICLK_MUX_SHIFT)
#define CMU_PERI_CLK_CTRL_SEL_SRC_SHIFT (0)
#define CMU_PERI_CLK_CTRL_CLK_DIV_SHIFT (4)
#define CMU_PERI_CLK_CTRL_SEL_SRC_MASK (0x03 << CMU_PERI_CLK_CTRL_SEL_SRC_SHIFT)
#define CMU_PERI_CLK_CTRL_CLK_DIV_MASK (0xFF << CMU_PERI_CLK_CTRL_CLK_DIV_SHIFT)
#define CMU_PERI_CLK_CTRL_SEL_SRC(c) ((c) << CMU_PERI_CLK_CTRL_SEL_SRC_SHIFT)
#define CMU_PERI_CLK_CTRL_CLK_DIV(c) ((c) << CMU_PERI_CLK_CTRL_CLK_DIV_SHIFT)
#define CMU_HOSC_CTRL_MODE_SHIFT (1)
#define CMU_HOSC_CTRL_CAL_SHIFT (2)
#define CMU_HOSC_CTRL_TOL_SHIFT (10)
#define CMU_HOSC_CTRL_MODE_MASK (0x01 << CMU_HOSC_CTRL_MODE_SHIFT)
#define CMU_HOSC_CTRL_CAL_MASK (0xFF << CMU_HOSC_CTRL_CAL_SHIFT)
#define CMU_HOSC_CTRL_TOL_MASK (0x03 << CMU_HOSC_CTRL_TOL_SHIFT)
#define CMU_HOSC_CTRL_MODE(c) ((c) << CMU_HOSC_CTRL_MODE_SHIFT)
#define CMU_HOSC_CTRL_CAL(c) ((c) << CMU_HOSC_CTRL_CAL_SHIFT)
#define CMU_HOSC_CTRL_TOL(c) ((c) << CMU_HOSC_CTRL_TOL_SHIFT)
#define ENABLE 1
#define DISABLE 0
#define CONFIG_CMU_FCLK_AHBCLK (ENABLE << 0)
#define CONFIG_CMU_SRP_SRPCLK (DISABLE << 1)
#define CONFIG_CMU_GPIO_AHBCLK (ENABLE << 2)
#define CONFIG_CMU_UDMAC_AHBCLK (ENABLE << 3)
#define CONFIG_CMU_DTRNG_AHBCLK (DISABLE << 4)
#define CONFIG_CMU_AES_AHBCLK (DISABLE << 5)
#define CONFIG_CMU_SRC_AHBCLK (DISABLE << 6)
#define CONFIG_CMU_QSPI_AHBCLK (DISABLE << 7)
#define CONFIG_CMU_TIMER0_APBCLK (DISABLE << 8)
#define CONFIG_CMU_TIMER1_APBCLK (DISABLE << 9)
#define CONFIG_CMU_TIMER2_APBCLK (DISABLE << 10)
#define CONFIG_CMU_TIMER3_APBCLK (DISABLE << 11)
#define CONFIG_CMU_TIMER4_APBCLK (DISABLE << 12)
#define CONFIG_CMU_TIMER5_APBCLK (DISABLE << 13)
#define CONFIG_CMU_TIMER6_APBCLK (DISABLE << 14)
#define CONFIG_CMU_PWMTIMER_APBCLK (DISABLE << 15)
#define CONFIG_CMU_DUALTIMER_APBCLK (ENABLE << 16)
#define CONFIG_CMU_WATCHDOG_APBCLK (ENABLE << 17)
#define CONFIG_CMU_UART0_CLK (DISABLE << 18)
#define CONFIG_CMU_UART1_CLK (DISABLE << 19)
#define CONFIG_CMU_UART2_CLK (DISABLE << 20)
#define CONFIG_CMU_SPI0_CLK (DISABLE << 21)
#define CONFIG_CMU_SPI1_CLK (DISABLE << 22)
#define CONFIG_CMU_SPI2_CLK (DISABLE << 23)
#define CONFIG_CMU_SPI3_CLK (DISABLE << 24)
#define CONFIG_CMU_SPI4_CLK (DISABLE << 25)
#define CONFIG_CMU_I2C0_CLK (DISABLE << 26)
#define CONFIG_CMU_I2C1_CLK (DISABLE << 27)
#define CONFIG_CMU_I2C2_CLK (DISABLE << 28)
#define CONFIG_CMU_I2C3_CLK (DISABLE << 29)
#define CONFIG_CMU_I2C4_CLK (DISABLE << 30)
#define INIT_CLOCK_CONFIG (CONFIG_CMU_FCLK_AHBCLK | CONFIG_CMU_SRP_SRPCLK | \
CONFIG_CMU_GPIO_AHBCLK | CONFIG_CMU_UDMAC_AHBCLK | \
CONFIG_CMU_DTRNG_AHBCLK |CONFIG_CMU_AES_AHBCLK | \
CONFIG_CMU_SRC_AHBCLK | CONFIG_CMU_QSPI_AHBCLK | \
CONFIG_CMU_TIMER0_APBCLK | CONFIG_CMU_TIMER1_APBCLK | \
CONFIG_CMU_TIMER2_APBCLK | CONFIG_CMU_TIMER3_APBCLK | \
CONFIG_CMU_TIMER4_APBCLK | CONFIG_CMU_TIMER5_APBCLK | \
CONFIG_CMU_TIMER6_APBCLK | CONFIG_CMU_PWMTIMER_APBCLK | \
CONFIG_CMU_DUALTIMER_APBCLK | CONFIG_CMU_WATCHDOG_APBCLK | \
CONFIG_CMU_UART0_CLK | CONFIG_CMU_UART1_CLK | \
CONFIG_CMU_UART2_CLK | CONFIG_CMU_SPI0_CLK | \
CONFIG_CMU_SPI1_CLK | CONFIG_CMU_SPI2_CLK | \
CONFIG_CMU_SPI3_CLK | CONFIG_CMU_SPI4_CLK | \
CONFIG_CMU_I2C0_CLK | CONFIG_CMU_I2C1_CLK | \
CONFIG_CMU_I2C2_CLK | CONFIG_CMU_I2C3_CLK | \
CONFIG_CMU_I2C4_CLK )
typedef enum _cmu_sel_sample_clk_t {
CMU_SELECT_INTERNAL_CLK = 0,
CMU_SELECT_EXTERNAL_XTAL_32768_CLK,
CMU_SELECT_INVALID
} cmu_sel_smp_clk_t;
typedef enum {
CMU_SRC_CLK_LSOSC = 0, // Internal LOSC 4.096MHz
CMU_SRC_CLK_EXT_4M, // External XTAL 4.096MHz
CMU_SRC_CLK_HSOSC, // Internal HOSC 24.576MHz
CMU_SRC_CLK_PLL, // Internal PLL 102.4MHz
CMU_SRC_32768Hz, // External XTAL 32.768KHz
CMU_SOURCE_CLK_INVALID
} cmu_src_clk_t;
typedef enum {
CMU_SAMPLE_CLK_AFTER_DIV = 0,
CMU_SRPCLK_AFTER_DIV,
CMU_AHBCLK_AFTER_DIV,
CMU_APBCLK_AFTER_DIV,
CMU_PERICLK_AFTER_DIV,
CMU_RTC_CLK,
CMU_AFECON_CLK,
CMU_SAMPLE_CLK,
CMU_FCLK_AHBCLK, // eFlash, MCU core clock
CMU_SRP_SRPCLK,
CMU_GPIO_AHBCLK,
CMU_UDMAC_AHBCLK,
CMU_DTRNG_AHBCLK,
CMU_AES_AHBCLK,
CMU_SRC_AHBCLK,
CMU_QSPI_AHBCLK,
CMU_TIMER0_APBCLK,
CMU_TIMER1_APBCLK,
CMU_TIMER2_APBCLK,
CMU_TIMER3_APBCLK,
CMU_TIMER4_APBCLK,
CMU_TIMER5_APBCLK,
CMU_TIMER6_APBCLK,
CMU_PWMTIMER_APBCLK,
CMU_DUALTIMER_APBCLK,
CMU_WATCHDOG_APBCLK,
CMU_UART0_CLK,
CMU_UART1_CLK,
CMU_UART2_CLK,
CMU_SPI0_CLK,
CMU_SPI1_CLK,
CMU_SPI2_CLK,
CMU_SPI3_CLK,
CMU_SPI4_CLK,
CMU_I2C0_CLK,
CMU_I2C1_CLK,
CMU_I2C2_CLK,
CMU_I2C3_CLK,
CMU_I2C4_CLK,
CMU_CLK_INVALID
} cmu_clock_t;
typedef enum {
CMU_MUX_MCU_CLK = 0,
CMU_MUX_PERI_CLK,
CMU_MUX_INVALID
} cmu_mux_peri_clock_t;
void bp6a_cmu_init(cmu_src_clk_t mcu_clk, cmu_src_clk_t peri_clk);
bool bp6a_cmu_get_clock_enabled(cmu_clock_t clock);
int bp6a_cmu_enable_clock(cmu_clock_t clock, bool en);
uint32_t bp6a_get_clock_src_freq(cmu_clock_t clock);
uint32_t bp6a_cmu_get_clock_freq(cmu_clock_t clock);
#endif /*__S1SBP6A_CMU_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_FLASH_H
#define __S1SBP6A_FLASH_H
#define FLASH_PAGE_SIZE 2048
#define UFC_FRWCON0_OFFSET 0x0000
#define UFC_FSHSTAT_OFFSET 0x0004
#define UFC_PROTCON_OFFSET 0x0010
#define UFC_PROTMON_OFFSET 0x0014
#define UFC_DCYCRDCON_OFFSET 0x0020
#define UFC_LDTCON_OFFSET 0x0030
#define UFC_FSHCON0_OFFSET 0x0034
#define UFC_FECCCON_OFFSET 0x0038
#define UFC_FECCFADR_OFFSET 0x003C
#define UFC_DCT0_OFFSET 0x0040
#define UFC_DCT1_OFFSET 0x0044
#define UFC_LDT0_OFFSET 0x0050
#define UFC_LDT1_OFFSET 0x0054
#define UFC_LDT2_OFFSET 0x0058
#define UFC_LDT3_OFFSET 0x005C
#define UFC_MODE_OFFSET 0x0060
#define UFC_CPA0_OFFSET 0x0064
#define UFC_RED0_OFFSET 0x0090
#define UFC_RED0_MBIT_OFFSET 0x0094
#define UFC_RED1_OFFSET 0x0098
#define UFC_RED1_MBIT_OFFSET 0x009C
#define PAGE_ERASE (0)
#define SECTOR_ERASE (1)
#define MAT_ERASE (2)
#define UFC_FRWCON_PROG_EN_SHIFT (0)
#define UFC_FRWCON_ERASE_MODE_SHIFT (2)
#define UFC_FRWCON_ECC_DATA_SHIFT (3)
#define UFC_FRWCON_ERASE_WRITE_SEL_SHIFT (8)
#define UFC_FRWCON_ECC_FAIL_SHIFT (15)
#define UFC_FRWCON_WRMD_SHIFT (0)
#define UFC_FRWCON_HVEN_SHIFT (2)
#define UFC_FRWCON_ERSMD_SHIFT (3)
#define UFC_FRWCON_BURSTPRM_SHIFT (8)
#define UFC_FRWCON_HVERSFAIL_SHIFT (10)
#define UFC_FRWCON_RED_ADDR_EN_SHIFT (11)
#define UFC_FRWCON_ECC_FAIL_SHIFT (15)
#define UFC_FRWCON_WRMD_MASK (0x03<<UFC_FRWCON_WRMD_SHIFT)
#define UFC_FRWCON_HVEN_MASK (0x01<<UFC_FRWCON_HVEN_SHIFT)
#define UFC_FRWCON_ERSMD_MASK (0x03<<UFC_FRWCON_ERSMD_SHIFT)
#define UFC_FRWCON_BURSTPRM_MASK (0x01<<UFC_FRWCON_BURSTPRM_SHIFT)
#define UFC_FRWCON_HVERSFAIL_MASK (0x01<<UFC_FRWCON_HVERSFAIL_SHIFT)
#define UFC_FRWCON_RED_ADDR_EN_MASK (0x01<<UFC_FRWCON_RED_ADDR_EN_SHIFT)
#define UFC_FRWCON_ECC_FAIL_MASK (0x01<<UFC_FRWCON_ECC_FAIL_SHIFT)
#define UFC_FRWCON_WRMD(c) ((c)<<UFC_FRWCON_WRMD_SHIFT)
#define UFC_FRWCON_HVEN(c) ((c)<<UFC_FRWCON_HVEN_SHIFT)
#define UFC_FRWCON_ERSMD(c) ((c)<<UFC_FRWCON_ERSMD_SHIFT)
#define UFC_FRWCON_BURSTPRM(c) ((c)<<UFC_FRWCON_BURSTPRM_SHIFT)
#define UFC_FRWCON_HVERSFAIL(c) ((c)<<UFC_FRWCON_HVERSFAIL_SHIFT)
#define UFC_FRWCON_RED_ADDR_EN(c) ((c)<<UFC_FRWCON_RED_ADDR_EN_SHIFT)
#define UFC_FRWCON_ECC_FAILT(c) ((c)<<UFC_FRWCON_ECC_FAIL_SHIFT)
#define PAGE_ERASE_MODE (0)
#define SECTOR_ERASE_MODE (1)
#define MAT_ERASE_MODE (2)
#define NO_OP_MODE (0)
#define ERASE_MODE (1)
#define WRITE_MODE (2)
#endif /* __S1SBP6A_FLASH_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include <stdbool.h>
#include "s1sbp6a.h"
#include "s1sbp6a_type.h"
#include "s1sbp6a_gpio.h"
void bp6a_gpio_set_dir(uint8_t port, uint8_t pin, bool is_input)
{
BP_GPIO_TypeDef *gpio_base = (BP_GPIO_TypeDef *)GPIO_PORT_BASE(port);
uint32_t mask = 1 << pin;
putreg32(&(gpio_base->ALTFUNCCLR), mask);//, mask);
if (is_input) {
putreg32(&(gpio_base->OUTENCLR), mask);//, mask);
} else {
putreg32(&(gpio_base->OUTENSET), mask);//, mask);
}
}
void bp6a_gpio_set_int(uint8_t port, uint8_t pin, bool enable)
{
BP_GPIO_TypeDef *gpio_base = (BP_GPIO_TypeDef *)GPIO_PORT_BASE(port);
if (enable) {
putreg32(&(gpio_base->INTENSET), 0x01 << pin);
} else {
putreg32(&(gpio_base->INTENCLR), 0x01 << pin);
}
}
void bp6a_gpio_clear_pend(uint8_t port, uint8_t pin)
{
BP_GPIO_TypeDef *gpio_base = (BP_GPIO_TypeDef *)GPIO_PORT_BASE(port);
putreg32(&(gpio_base->INTCLR), 0x01 << pin);
}
void bp6a_gpio_set_int_type(uint8_t port, uint8_t pin, bool isHigh, bool isEadge)
{
BP_GPIO_TypeDef *gpio_base = (BP_GPIO_TypeDef *)GPIO_PORT_BASE(port);
if (isHigh) {
putreg32(&(gpio_base->INTPOLSET), 0x01 << pin);
} else {
putreg32(&(gpio_base->INTPOLCLR), 0x01 << pin);
}
if (isEadge) {
putreg32(&(gpio_base->INTTYPESET), 0x01 << pin);
} else {
putreg32(&(gpio_base->INTTYPECLR), 0x01 << pin);
}
}
void bp6a_set_pin_config(uint8_t port, uint8_t pin, uint8_t cfg)
{
uint8_t idx = port * 4 + pin / 4 + 2;
uint8_t bit = (pin << 3) % 32;
modifyreg32(&BP_SYSCON->IOCFG[idx], 0x3 << bit, cfg << bit);
}

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_GPIO_H
#define __S1SBP6A_GPIO_H
#define GPIO_BASE (BP_AHB_BASE)
#define GPIO_PORT_BASE(c) (GPIO_BASE + (c << 12))
#define GPIO_DATA_OFFSET 0x0000
#define GPIO_DATAOUT_OFFSET 0x0004
#define GPIO_OUTENSET_OFFSET 0x0010
#define GPIO_OUTENCLR_OFFSET 0x0014
#define GPIO_ALTFUNCSET_OFFSET 0x0018
#define GPIO_ALTFUNCCLR_OFFSET 0x001C
#define GPIO_INTENSET_OFFSET 0x0020
#define GPIO_INTENCLR_OFFSET 0x0024
#define GPIO_INTTYPESET_OFFSET 0x0028
#define GPIO_INTTYPECLR_OFFSET 0x002C
#define GPIO_INTPOLSET_OFFSET 0x0030
#define GPIO_INTPOLCLR_OFFSET 0x0034
#define GPIO_INTSTAT_OFFSET 0x0038
#define GPIO_INTCLR_OFFSET 0x0038
#define GPIO_ALTFUNCSEL_OFFSET 0x003c
typedef enum {
GPIO_PORT_0 = 0,
GPIO_PORT_1,
GPIO_PORT_2,
GPIO_PORT_MAX
} gpio_port_e;
typedef enum {
GPIO_PIN_0 = 0,
GPIO_PIN_1,
GPIO_PIN_2,
GPIO_PIN_3,
GPIO_PIN_4,
GPIO_PIN_5,
GPIO_PIN_6,
GPIO_PIN_7,
GPIO_PIN_8,
GPIO_PIN_9,
GPIO_PIN_10,
GPIO_PIN_11,
GPIO_PIN_12,
GPIO_PIN_13,
GPIO_PIN_14,
GPIO_PIN_15,
GPIO_PIN_MAX
} gpio_pin_e;
typedef enum {
GPIO_MODE_INPUT = 0x0,
GPIO_MODE_OUTPUT,
GPIO_MODE_ALT_FUNC_0,
GPIO_MODE_ALT_FUNC_1,
GPIO_MODE_MAX,
} gpio_mode_e;
void bp6a_gpio_set_dir(uint8_t port, uint8_t pin, bool is_input);
void bp6a_gpio_set_int(uint8_t port, uint8_t pin, bool enable);
void bp6a_gpio_clear_pend(uint8_t port, uint8_t pin);
void bp6a_gpio_set_int_type(uint8_t port, uint8_t pin, bool isHigh, bool isEadge);
void bp6a_set_pin_config(uint8_t port, uint8_t pin, uint8_t cfg);
#endif /* __S1SBP6A_GPIO_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifdef DEVICE_I2C
#include <stdbool.h>
#include "s1sbp6a.h"
#include "s1sbp6a_cmu.h"
#include "s1sbp6a_type.h"
#include "s1sbp6a_i2c.h"
#define BP6A_I2C_DEFAULT_MODE (I2C_AUTO |I2C_INTERRUPT)
#define I2C_MAX_FIFO_SIZE 16
bp6a_i2c_priv_t bp6a_i2c_priv[5] = {
{
.index = 0,
.xfer_speed = DEFAULT_I2CXFER_CLOCK,
.master = true,
.mode = BP6A_I2C_DEFAULT_MODE,
.slave_addr = DEFAULT_I2CSLAVE_ADDR,
.addrlen = 7,
.timeout = DEFAULT_I2C_TIMEOUT,
},
{
.index = 1,
.xfer_speed = DEFAULT_I2CXFER_CLOCK,
.master = true,
.mode = BP6A_I2C_DEFAULT_MODE,
.slave_addr = DEFAULT_I2CSLAVE_ADDR,
.addrlen = 7,
.timeout = DEFAULT_I2C_TIMEOUT,
},
{
.index = 2,
.xfer_speed = DEFAULT_I2CXFER_CLOCK,
.master = true,
.mode = BP6A_I2C_DEFAULT_MODE,
.slave_addr = DEFAULT_I2CSLAVE_ADDR,
.addrlen = 7,
.timeout = DEFAULT_I2C_TIMEOUT,
},
{
.index = 3,
.xfer_speed = DEFAULT_I2CXFER_CLOCK,
.master = true,
.mode = BP6A_I2C_DEFAULT_MODE,
.slave_addr = DEFAULT_I2CSLAVE_ADDR,
.addrlen = 7,
.timeout = DEFAULT_I2C_TIMEOUT,
},
{
.index = 4,
.xfer_speed = DEFAULT_I2CXFER_CLOCK,
.master = true,
.mode = BP6A_I2C_DEFAULT_MODE,
.slave_addr = DEFAULT_I2CSLAVE_ADDR,
.addrlen = 7,
.timeout = DEFAULT_I2C_TIMEOUT,
}
};
static uint32_t bp6a_get_i2c_base_addr(uint32_t ch)
{
return (BP_I2C0_BASE + ch * 0x1000);
}
static void bp6a_i2c_run_auto_mode(bp6a_i2c_priv_t *priv, bool enable)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
modifyreg32(&(i2c->AUTO_CONF), I2C_AUTO_CONF_MASTER_RUN_MASK,
I2C_AUTO_CONF_MASTER_RUN(enable));
modifyreg32(&(i2c->INT_EN), I2C_INT_EN_XFER_DONE_MANUAL_EN_MASK,
I2C_INT_EN_XFER_DONE_MANUAL_EN(!enable));
}
static int bp6a_i2c_xfer_wait_done_auto(bp6a_i2c_priv_t *priv)
{
int timeout = priv->timeout;
while (timeout-- > 0) {
if (priv->int_stat & I2C_INT_STAT_XFER_DONE_AUTO_MASK) {
return 0;
}
}
return -1;
}
static int bp6a_i2c_xfer_wait_done_manual(bp6a_i2c_priv_t *priv)
{
uint32_t timeout = priv->timeout;
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
while (timeout-- > 0) {
if (getreg32(&(i2c->INT_STAT)) & I2C_INT_STAT_XFER_DONE_MANUAL_MASK) {
return 0;
}
}
return -1;
}
static void bp6a_i2c_set_channel(bp6a_i2c_priv_t *priv, bool tx, bool rx)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
modifyreg32(&(i2c->CTL), I2C_CTL_RXCHON_MASK | I2C_CTL_TXCHON_MASK,
I2C_CTL_RXCHON(rx) | I2C_CTL_TXCHON(tx));
}
static void bp6a_i2c_set_ctl_mode(bp6a_i2c_priv_t *priv)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
modifyreg32(&(i2c->CTL), I2C_CTL_MASTER_MASK, I2C_CTL_MASTER(priv->master));
}
static void bp6a_i2c_set_master_addr(bp6a_i2c_priv_t *priv, uint32_t addr)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
/* For auto mode and HS mode only */
modifyreg32(&(i2c->ADDR), I2C_ADDR_MASTERID_MASK, I2C_ADDR_MASTERID(addr));
}
static void bp6a_i2c_set_slave_addr(bp6a_i2c_priv_t *priv)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
if (priv->addrlen == 10) {
modifyreg32(&(i2c->CONF), I2C_CONF_ADDR_MODE_MASK, I2C_CONF_ADDR_MODE(1));
} else {
modifyreg32(&(i2c->CONF), I2C_CONF_ADDR_MODE_MASK, I2C_CONF_ADDR_MODE(0));
}
if (priv->master) {
modifyreg32(&(i2c->ADDR), I2C_ADDR_SLAVE_ADDR_MAS_MASK,
I2C_ADDR_SLAVE_ADDR_MAS(priv->slave_addr));
modifyreg32(&(i2c->ADDR), I2C_ADDR_SLAVE_ADDR_SLA_MASK,
I2C_ADDR_SLAVE_ADDR_SLA(0));
} else
modifyreg32(&(i2c->ADDR), I2C_ADDR_SLAVE_ADDR_SLA_MASK,
I2C_ADDR_SLAVE_ADDR_SLA(priv->slave_addr));
}
static void bp6a_i2c_set_hs_mode_timing(BP_I2C_TypeDef *i2c, uint8_t clkDiv,
uint8_t tSTART_SU, uint16_t tSTART_HD, uint8_t tSTOP_SU,
uint8_t tDATA_SU, uint8_t tDATA_HD, uint8_t tSCL_L,
uint8_t tSCL_H, uint8_t tSR_RELEASE)
{
putreg32(&(i2c->TIMING_HS1),
I2C_TIMING_HS1_TSDA_SU_HS(0) |
I2C_TIMING_HS1_TSTOP_SU_HS(tSTOP_SU) |
I2C_TIMING_HS1_TSTART_HD_HS(tSTART_HD) |
I2C_TIMING_HS1_TSTART_SU_HS(tSTART_SU));
putreg32(&(i2c->TIMING_HS2),
I2C_TIMING_HS2_TSCL_H_HS(tSCL_H) |
I2C_TIMING_HS2_TSCL_L_HS(tSCL_L) |
I2C_TIMING_HS2_TDATA_SU_HS(tDATA_SU));
putreg32(&(i2c->TIMING_HS3),
I2C_TIMING_HS3_TSR_RELEASE(tSR_RELEASE) |
I2C_TIMING_HS3_CLK_DIV(clkDiv));
putreg32(&(i2c->TIMING_SLA), tDATA_HD & 0xFFFF);
}
static void bp6a_set_fs_mode_timing(BP_I2C_TypeDef *i2c, uint8_t clkDiv,
uint8_t tSTART_SU, uint8_t tSTART_HD, uint8_t tSTOP_SU,
uint8_t tDATA_SU, uint16_t tDATA_HD, uint8_t tSCL_L,
uint8_t tSCL_H, uint8_t tSR_RELEASE)
{
putreg32(&(i2c->TIMING_FS1),
I2C_TIMING_FS1_TSDA_SU_FS(0) |
I2C_TIMING_FS1_TSTOP_SU_FS(tSTOP_SU) |
I2C_TIMING_FS1_TSTART_HD_FS(tSTART_HD) |
I2C_TIMING_FS1_TSTART_SU_FS(tSTART_SU));
putreg32(&(i2c->TIMING_FS2),
I2C_TIMING_FS2_TSCL_H_FS(tSCL_H) |
I2C_TIMING_FS2_TSCL_L_FS(tSCL_L) |
I2C_TIMING_FS2_TDATA_SU_FS(tDATA_SU));
putreg32(&(i2c->TIMING_FS3),
I2C_TIMING_FS3_TSR_RELEASE(tSR_RELEASE) |
I2C_TIMING_FS3_CLK_DIV(clkDiv));
putreg32(&(i2c->TIMING_SLA), 0); //tDATA_HD);
}
static void bp6a_i2c_calculate_timing(bp6a_i2c_priv_t *priv)
{
uint32_t clkDiv;
uint32_t tFTL_CYCLE_SCL;
int32_t i = 0;
int32_t uTemp0 = 0;
int32_t uTemp1 = 0;
int32_t uTemp2 = 0;
uint32_t ipClk = bp6a_cmu_get_clock_freq(CMU_I2C0_CLK + priv->index);
uint32_t opClk = priv->xfer_speed;
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
modifyreg32(&(i2c->CONF),
I2C_CONF_FLT_CYCLE_SDA_MASK |
I2C_CONF_FLT_CYCLE_SCL_MASK,
I2C_CONF_FLT_CYCLE_SDA(0) |
I2C_CONF_FLT_CYCLE_SCL(0));
tFTL_CYCLE_SCL = (getreg32(&(i2c->CONF)) & I2C_CONF_FLT_CYCLE_SCL_MASK)
>> I2C_CONF_FLT_CYCLE_SCL_SHIFT;
if (tFTL_CYCLE_SCL > 0x2) {
uTemp0 = (uint32_t)((float)(ipClk / opClk) - (tFTL_CYCLE_SCL + 3) * 2);
} else {
uTemp0 = (uint32_t)((float)(ipClk / opClk) - (tFTL_CYCLE_SCL + 1 + 3) * 2);
}
for (i = 0; i < 256; i++) {
uTemp1 = uTemp0 / (i + 1);
if (uTemp1 < 256) {
uTemp2 = uTemp1 - 2;
break;
}
}
clkDiv = i;
uint32_t tSCL_H;
if (opClk > I2C_FREQ_400KHZ) {
tSCL_H = ((uTemp2 + 10) / 3) - 5;
} else {
tSCL_H = uTemp2 / 2;
}
uint32_t tSCL_L = uTemp2 - tSCL_H;
uint32_t tSTART_SU = tSCL_L;
uint32_t tSTART_HD = tSCL_L;
uint32_t tSTOP_SU = tSCL_L;
uint32_t tDATA_SU = tSCL_L / 2;
uint32_t tDATA_HD = tSCL_L / 2;
uint32_t tSR_RELEASE = uTemp2;
if (opClk > I2C_FREQ_400KHZ) {
bp6a_set_fs_mode_timing(i2c, 1, 37, 37, 37, 18, 18, 37, 37, 74);
bp6a_i2c_set_hs_mode_timing(i2c, clkDiv, tSTART_SU, tSTART_HD, tSTOP_SU,
tDATA_SU, tDATA_HD, tSCL_L, tSCL_H, tSR_RELEASE);
} else
bp6a_set_fs_mode_timing(i2c, clkDiv, tSTART_SU, tSTART_HD, tSTOP_SU,
tDATA_SU, tDATA_HD, tSCL_L, tSCL_H, tSR_RELEASE);
}
static void bp6a_i2c_set_fifo_level(bp6a_i2c_priv_t *priv, uint32_t tx, uint32_t rx)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
modifyreg32(&(i2c->FIFO_CTL), I2C_FIFO_CTL_RXFIFO_TRIG_MASK |
I2C_FIFO_CTL_TXFIFO_TRIG_MASK |
I2C_FIFO_CTL_RXFIFO_EN_MASK |
I2C_FIFO_CTL_TXFIFO_EN_MASK,
I2C_FIFO_CTL_RXFIFO_EN(!!rx) |
I2C_FIFO_CTL_TXFIFO_EN(!!tx) |
I2C_FIFO_CTL_RXFIFO_TRIG(rx) |
I2C_FIFO_CTL_TXFIFO_TRIG(tx));
}
static void bp6a_i2c_set_timeout(bp6a_i2c_priv_t *priv)
{
uint32_t en = 1;
uint32_t timeoutCount = priv->timeout;
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
if (priv->timeout == 0) {
timeoutCount = 0xFF;
en = 0;
}
modifyreg32(&(i2c->TIMEOUT), I2C_TIMEOUT_TIMEOUT_EN_MASK |
I2C_TIMEOUT_TOUT_COUNT_MASK,
I2C_TIMEOUT_TIMEOUT_EN(en) |
I2C_TIMEOUT_TOUT_COUNT(timeoutCount | 0xFF00));
}
static void bp6a_i2c_reset_txFIFO(bp6a_i2c_priv_t *priv)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
modifyreg32(&(i2c->FIFO_CTL), I2C_FIFO_CTL_TXFIFO_RST_MASK, I2C_FIFO_CTL_TXFIFO_RST(1));
modifyreg32(&(i2c->FIFO_CTL), I2C_FIFO_CTL_TXFIFO_RST_MASK, I2C_FIFO_CTL_TXFIFO_RST(0));
}
static void bp6a_i2c_reset_rxFIFO(bp6a_i2c_priv_t *priv)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
modifyreg32(&(i2c->FIFO_CTL), I2C_FIFO_CTL_RXFIFO_RST_MASK, I2C_FIFO_CTL_RXFIFO_RST(1));
modifyreg32(&(i2c->FIFO_CTL), I2C_FIFO_CTL_RXFIFO_RST_MASK, I2C_FIFO_CTL_RXFIFO_RST(0));
}
static int bp6a_i2c_out_byte(bp6a_i2c_priv_t *priv, uint8_t data)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
/* Set Data to TX buffer and Send 1 byte */
modifyreg32(&(i2c->MANUAL_CMD), I2C_MANUAL_CMD_TX_DATA_MASK, I2C_MANUAL_CMD_TX_DATA(data));
modifyreg32(&(i2c->MANUAL_CMD), I2C_MANUAL_CMD_SEND_DATA_MASK, I2C_MANUAL_CMD_SEND_DATA(1));
return bp6a_i2c_xfer_wait_done_manual(priv);
}
static int bp6a_i2c_in_byte(bp6a_i2c_priv_t *priv, bool is_ack)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
/* Looks awkward, but if I2C_RX_ACK is set, ACK is NOT generated */
if (!is_ack)
modifyreg32((&i2c->MANUAL_CMD), I2C_MANUAL_CMD_RX_ACK_MASK |
I2C_MANUAL_CMD_READ_DATA_MASK,
I2C_MANUAL_CMD_RX_ACK(1) |
I2C_MANUAL_CMD_READ_DATA(1));
else
modifyreg32((&i2c->MANUAL_CMD), I2C_MANUAL_CMD_READ_DATA_MASK,
I2C_MANUAL_CMD_READ_DATA(1));
if (bp6a_i2c_xfer_wait_done_manual(priv) < 0) {
return -1;
}
return ((getreg32(&i2c->MANUAL_CMD) & I2C_MANUAL_CMD_RX_DATA_MASK)
>> I2C_MANUAL_CMD_RX_DATA_SHIFT);
}
static void bp6a_i2c_set_buffer(bp6a_i2c_priv_t *priv, struct i2c_msg_s *msgv)
{
priv->mptr = msgv->buffer;
priv->mcnt = msgv->length;
priv->cur_msg = 0;
}
static void bp6a_i2c_set_auto_config(bp6a_i2c_priv_t *priv, bool stop,
bool is_read, uint32_t len)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
/* Set Auto Stop */
modifyreg32(&(i2c->AUTO_CONF), I2C_AUTO_CONF_STOP_AFTER_TRANS_MASK,
I2C_AUTO_CONF_STOP_AFTER_TRANS(stop));
/* Set Type of transaction : 0(Tx), 1(Rx) */
modifyreg32(&(i2c->AUTO_CONF), I2C_AUTO_CONF_READ_WRITE_MASK,
I2C_AUTO_CONF_READ_WRITE(is_read));
/* Set Length of transaction */
modifyreg32(&(i2c->AUTO_CONF), I2C_AUTO_CONF_TRANS_LEN_MASK, I2C_AUTO_CONF_TRANS_LEN(len));
}
static uint8_t bp6a_i2c_get_tx_fifo_level(bp6a_i2c_priv_t *priv)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
return (uint8_t)((getreg32(&i2c->FIFO_STAT) & I2C_FIFO_STAT_TX_FIFO_LEVEL_MASK) >> I2C_FIFO_STAT_TX_FIFO_LEVEL_SHIFT);
}
static uint8_t bp6a_i2c_get_rx_fifo_level(bp6a_i2c_priv_t *priv)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
return (uint8_t)((getreg32(&i2c->FIFO_STAT) & I2C_FIFO_STAT_RX_FIFO_LEVEL_MASK) >> I2C_FIFO_STAT_RX_FIFO_LEVEL_SHIFT);
}
static void bp6a_i2c_tx_handle(bp6a_i2c_priv_t *priv)
{
int xferCount;
int i;
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
xferCount = I2C_MAX_FIFO_SIZE - bp6a_i2c_get_tx_fifo_level(priv);
if (priv->mcnt < xferCount) {
xferCount = priv->mcnt;
}
for (i = 0; i < xferCount; i++) {
putreg32(&(i2c->TXDATA), priv->mptr[priv->cur_msg++]);
priv->mcnt--;
}
if (priv->mcnt == 0) {
modifyreg32(&(i2c->INT_EN), I2C_INT_EN_TX_ALMOST_EMPTY_EN_MASK,
I2C_INT_EN_TX_ALMOST_EMPTY_EN(0));
}
}
static void bp6a_i2c_rx_handle(bp6a_i2c_priv_t *priv)
{
uint32_t fifoCount;
uint32_t i;
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
fifoCount = bp6a_i2c_get_rx_fifo_level(priv);
for (i = 0; i < fifoCount; i++) {
priv->mptr[priv->cur_msg++] = getreg32(&(i2c->RXDATA));
}
if (priv->mcnt <= priv->cur_msg)
modifyreg32(&(i2c->INT_EN), I2C_INT_EN_RX_ALMOST_FULL_EN_MASK,
I2C_INT_EN_RX_ALMOST_FULL_EN(0));
}
static void i2c_handler(uint32_t ch)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[ch];
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
uint32_t status = getreg32(&(i2c->INT_STAT));
priv->int_stat |= status;
if (status & I2C_INT_STAT_TX_ALMOST_EMPTY_MASK) {
priv->st_slave_rx_master_tx = 1;
bp6a_i2c_tx_handle(priv);
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_TX_ALMOST_EMPTY_MASK);
}
if (status & I2C_INT_STAT_RX_ALMOST_FULL_MASK) {
priv->st_slave_tx_master_rx = 1;
bp6a_i2c_rx_handle(priv);
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_RX_ALMOST_FULL_MASK);
}
if (status & I2C_INT_STAT_TRAILING_MASK) {
bp6a_i2c_rx_handle(priv);
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_TRAILING_MASK);
}
if (status & I2C_INT_STAT_XFER_DONE_AUTO_MASK) {
bp6a_i2c_rx_handle(priv);
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_XFER_DONE_AUTO_MASK);
}
if (status & I2C_INT_STAT_TX_OVERRUN_MASK) {
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_TX_OVERRUN_MASK);
}
if (status & I2C_INT_STAT_RX_OVERRUN_MASK) {
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_RX_OVERRUN_MASK);
}
if (status & I2C_INT_STAT_RX_UNDERRUN_MASK) {
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_RX_UNDERRUN_MASK);
}
if (status & I2C_INT_STAT_XFER_ABORT_AUTO_MASK) {
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_XFER_ABORT_AUTO_MASK);
}
if (status & I2C_INT_STAT_NO_DEV_ACK_AUTO_MASK) {
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_NO_DEV_ACK_AUTO_MASK);
}
if (status & I2C_INT_STAT_NO_DEV_AUTO_MASK) {
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_NO_DEV_AUTO_MASK);
}
if (status & I2C_INT_STAT_TIMEOUT_AUTO_MASK) {
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_TIMEOUT_AUTO_MASK);
}
if (status & I2C_INT_STAT_SLAVE_ADDR_MATCH_SHIFT) {
putreg32(&(i2c->INT_STAT), I2C_INT_STAT_SLAVE_ADDR_MATCH_MASK);
}
}
void I2C0_Handler(void)
{
i2c_handler(0);
NVIC_ClearPendingIRQ(I2C0_IRQn);
}
void I2C1_Handler(void)
{
i2c_handler(1);
NVIC_ClearPendingIRQ(I2C1_IRQn);
}
void I2C2_Handler(void)
{
i2c_handler(2);
NVIC_ClearPendingIRQ(I2C2_IRQn);
}
void I2C3_Handler(void)
{
i2c_handler(3);
NVIC_ClearPendingIRQ(I2C3_IRQn);
}
void I2C4_Handler(void)
{
i2c_handler(4);
NVIC_ClearPendingIRQ(I2C4_IRQn);
}
static void bp6a_i2c_set_interruptmode(bp6a_i2c_priv_t *priv)
{
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
/* disable interrupt */
uint32_t reg_val = 0;
putreg32(&(i2c->INT_EN), 0);
if (!(priv->mode & I2C_INTERRUPT)) {
return;
}
if (priv->master) {
reg_val = I2C_INT_EN_XFER_DONE_AUTO_EN(1) |
I2C_INT_EN_XFER_ABORT_AUTO_EN(1) |
I2C_INT_EN_NO_DEV_ACK_AUTO_EN(1) |
I2C_INT_EN_NO_DEV_AUTO_EN(1) |
I2C_INT_EN_TIMEOUT_AUTO_EN(1);
if (priv->mode & I2C_M_READ) {
reg_val |= I2C_INT_EN_RX_ALMOST_FULL_EN(1) |
I2C_INT_EN_RX_UNDERRUN_EN(1) |
I2C_INT_EN_RX_OVERRUN_EN(1) |
I2C_INT_EN_TRAILING_EN(1);
} else {
reg_val |= I2C_INT_EN_TX_ALMOST_EMPTY_EN(1) |
I2C_INT_EN_TX_UNDERRUN_EN(1) |
I2C_INT_EN_TX_OVERRUN_EN(1);
}
} else {
reg_val = I2C_INT_EN_SLAVE_ADDR_MATCH_EN(1) |
I2C_INT_EN_TIMEOUT_AUTO_EN(1);
if (priv->mode & I2C_M_READ) {
reg_val |= I2C_INT_EN_TRAILING_EN(1) |
I2C_INT_EN_RX_UNDERRUN_EN(1) |
I2C_INT_EN_RX_ALMOST_FULL_EN(1) |
I2C_INT_EN_RX_OVERRUN_EN(1);
} else {
reg_val |= I2C_INT_EN_TX_ALMOST_EMPTY_EN(1) |
I2C_INT_EN_TX_UNDERRUN_EN(1) |
I2C_INT_EN_TX_OVERRUN_EN(1);
}
}
putreg32(&(i2c->INT_EN), reg_val);
}
static void bp6a_i2c_enable_isr(bp6a_i2c_priv_t *priv)
{
NVIC_DisableIRQ((IRQn_Type)(I2C0_IRQn + priv->index));
if (priv->mode & I2C_INTERRUPT) {
NVIC_ClearPendingIRQ((IRQn_Type)(I2C0_IRQn + priv->index));
if (priv->index == 0) {
NVIC_SetVector((IRQn_Type)(I2C0_IRQn + priv->index), (uint32_t)I2C0_Handler);
} else if (priv->index == 1) {
NVIC_SetVector((IRQn_Type)(I2C0_IRQn + priv->index), (uint32_t)I2C1_Handler);
} else if (priv->index == 2) {
NVIC_SetVector((IRQn_Type)(I2C0_IRQn + priv->index), (uint32_t)I2C2_Handler);
} else if (priv->index == 3) {
NVIC_SetVector((IRQn_Type)(I2C0_IRQn + priv->index), (uint32_t)I2C3_Handler);
} else if (priv->index == 4) {
NVIC_SetVector((IRQn_Type)(I2C0_IRQn + priv->index), (uint32_t)I2C4_Handler);
}
NVIC_EnableIRQ((IRQn_Type)(I2C0_IRQn + priv->index));
}
}
static int bp6a_i2c_xfer_slave(bp6a_i2c_priv_t *priv, struct i2c_msg_s *msgv)
{
priv->slave_addr = msgv->addr;
bp6a_i2c_set_slave_addr(priv);
bp6a_i2c_set_auto_config(priv, !!(msgv->flags & I2C_M_NOSTOP),
!!(msgv->flags & I2C_M_READ), msgv->length);
bp6a_i2c_set_fifo_level(priv, DEFAULT_I2C_TX_TRIGLVL, DEFAULT_I2C_RX_TRIGLVL);
bp6a_i2c_set_channel(priv, !(msgv->flags & I2C_M_NOSTOP), !!(msgv->flags & I2C_M_NOSTOP));
bp6a_i2c_set_interruptmode(priv);
bp6a_i2c_run_auto_mode(priv, true);
return bp6a_i2c_xfer_wait_done_auto(priv);
}
static int bp6a_i2c_xfer_master_auto(bp6a_i2c_priv_t *priv, struct i2c_msg_s *msgv)
{
priv->slave_addr = msgv->addr;
bp6a_i2c_set_slave_addr(priv);
bp6a_i2c_set_auto_config(priv, !!(msgv->flags & I2C_M_NOSTOP),
!!(msgv->flags & I2C_M_READ), msgv->length);
bp6a_i2c_set_fifo_level(priv, DEFAULT_I2C_TX_TRIGLVL, DEFAULT_I2C_RX_TRIGLVL);
bp6a_i2c_set_channel(priv, !(msgv->flags & I2C_M_NOSTOP), !!(msgv->flags & I2C_M_NOSTOP));
bp6a_i2c_set_interruptmode(priv);
bp6a_i2c_run_auto_mode(priv, true);
return bp6a_i2c_xfer_wait_done_auto(priv);
}
static int bp6a_i2c_transfer(uint32_t index, struct i2c_msg_s *msgv)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
priv->mode = BP6A_I2C_DEFAULT_MODE;
priv->mode |= msgv->flags;
bp6a_i2c_set_buffer(priv, msgv);
if (priv->master) {
if (priv->mode & I2C_AUTO) {
return bp6a_i2c_xfer_master_auto(priv, msgv);
} else {
return -1;
}
// return bp6a_i2c_xfer_master_manual(priv, msgv);
} else {
return bp6a_i2c_xfer_slave(priv, msgv);
}
}
/******************************************************************************
* Public function
******************************************************************************/
void bp6a_i2c_master_init(uint32_t index, uint32_t freq, int addr_len)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
priv->master = true;
priv->xfer_speed = freq;
priv->addrlen = addr_len;
bp6a_cmu_enable_clock((cmu_clock_t)(CMU_I2C0_CLK + index), true);
bp6a_i2c_reset(index);
bp6a_i2c_set_master_addr(priv, I2C_DEFAULT_MASTER_ADDRESS);
/* Set master mode */
bp6a_i2c_set_ctl_mode(priv);
priv->timeout = 0xFFFF;
bp6a_i2c_set_timeout(priv);
/* Set speed */
bp6a_i2c_calculate_timing(priv);
bp6a_i2c_reset_rxFIFO(priv);
bp6a_i2c_reset_txFIFO(priv);
bp6a_i2c_enable_isr(priv);
}
void bp6a_i2c_slave_init(uint32_t index)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
bp6a_cmu_enable_clock((cmu_clock_t)(CMU_I2C0_CLK + index), true);
priv->master = false;
priv->mode |= I2C_AUTO | I2C_INTERRUPT;
priv->st_slave_tx_master_rx = 0;
priv->st_slave_rx_master_tx = 0;
/* Set slave mode */
bp6a_i2c_set_ctl_mode(priv);
/* Set slave address */
bp6a_i2c_set_slave_addr(priv);
/* Enable stretch-mode */
modifyreg32(&(i2c->CONF), I2C_CONF_STRCH_EN_MASK, I2C_CONF_STRCH_EN(1));
/* set tx/rx channel */
bp6a_i2c_set_channel(priv, true, true);
/* Enable interrupt */
bp6a_i2c_set_interruptmode(priv);
}
int bp6a_i2c_get_slave_status(uint32_t index)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
if (priv->st_slave_tx_master_rx) {
priv->st_slave_tx_master_rx = 0;
return 1; // Master read
}
if (priv->st_slave_rx_master_tx) {
priv->st_slave_rx_master_tx = 0;
return 3; // Master is writing
}
return 0;
}
int bp6a_i2c_start(uint32_t index)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
modifyreg32(&(i2c->MANUAL_CMD), I2C_MANUAL_CMD_SEND_START_MASK,
I2C_MANUAL_CMD_SEND_START(1));
return bp6a_i2c_xfer_wait_done_manual(priv);
}
int bp6a_i2c_stop(uint32_t index)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
modifyreg32(&(i2c->MANUAL_CMD), I2C_MANUAL_CMD_SEND_STOP_MASK,
I2C_MANUAL_CMD_SEND_STOP(1));
return bp6a_i2c_xfer_wait_done_manual(priv);
}
void bp6a_i2c_reset(uint32_t index)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
BP_I2C_TypeDef *i2c = (BP_I2C_TypeDef *)bp6a_get_i2c_base_addr(priv->index);
modifyreg32(&(i2c->CTL), I2C_CTL_SW_RST_MASK, I2C_CTL_SW_RST(1));
_Wait(100);
modifyreg32(&(i2c->CTL), I2C_CTL_SW_RST_MASK, I2C_CTL_SW_RST(0));
}
int bp6a_i2c_setaddress(uint32_t index, int addr, int nbits)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
priv->slave_addr = addr;
if (nbits == 1) {
priv->msgv->flags |= I2C_M_TEN;
}
return 0;
}
int bp6a_i2c_write_byte(uint32_t index, int data)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
return bp6a_i2c_out_byte(priv, data);
}
int bp6a_i2c_read_byte(uint32_t index, bool last)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
return bp6a_i2c_in_byte(priv, last);
}
int bp6a_i2c_read(uint32_t index, uint8_t *buffer, int buflen, int start, int stop)
{
struct i2c_msg_s msg;
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
priv->int_stat = 0;
/* 7- or 10-bit? */
msg.flags = (priv->addrlen == 10) ? I2C_M_TEN : 0;
/* Setup for the transfer */
msg.addr = priv->slave_addr;
msg.flags |= I2C_M_READ;
if (start) {
msg.flags |= I2C_M_NOSTART;
}
if (stop) {
msg.flags |= I2C_M_NOSTOP;
}
msg.buffer = (uint8_t *) buffer;
msg.length = buflen;
return bp6a_i2c_transfer(index, &msg);
}
int bp6a_i2c_write(uint32_t index, const uint8_t *buffer, int buflen, int start, int stop)
{
struct i2c_msg_s msg;
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
priv->int_stat = 0;
/* Setup for the transfer */
msg.addr = priv->slave_addr;
msg.flags = (priv->addrlen == 10) ? I2C_M_TEN : 0;
if (start) {
msg.flags |= I2C_M_NOSTART;
}
if (stop) {
msg.flags |= I2C_M_NOSTOP;
}
msg.buffer = (uint8_t *) buffer; /* Override const */
msg.length = buflen;
return bp6a_i2c_transfer(index, &msg);
}
void bp6a_i2c_set_slave_address(uint32_t index, int addr, bool is_slave)
{
bp6a_i2c_priv_t *priv = &bp6a_i2c_priv[index];
priv->slave_addr = addr;
if (is_slave) {
priv->master = false;
bp6a_i2c_set_slave_addr(priv);
}
}
#endif // DEVICE_I2C

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/s1sbp6a_i2c.h Normal file
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@ -0,0 +1,516 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_I2C_H
#define __S1SBP6A_I2C_H
#define I2C_CTL_OFFSET (0x0000)
#define I2C_FIFO_CTL_OFFSET (0x0004)
#define I2C_TRAILING_CTL_OFFSET (0x0008)
#define I2C_INT_EN_OFFSET (0x0020)
#define I2C_INT_STAT_OFFSET (0x0024)
#define I2C_FIFO_STAT_OFFSET (0x0030)
#define I2C_TX_DATA_OFFSET (0x0034)
#define I2C_RX_DATA_OFFSET (0x0038)
#define I2C_CONF_OFFSET (0x0040)
#define I2C_AUTO_CONF_OFFSET (0x0044)
#define I2C_TIMEOUT_OFFSET (0x0048)
#define I2C_MANUAL_CMD_OFFSET (0x004C)
#define I2C_TRANS_STATUS_OFFSET (0x0050)
#define I2C_TIMING_HS1_OFFSET (0x0054)
#define I2C_TIMING_HS2_OFFSET (0x0058)
#define I2C_TIMING_HS3_OFFSET (0x005C)
#define I2C_TIMING_FS1_OFFSET (0x0060)
#define I2C_TIMING_FS2_OFFSET (0x0064)
#define I2C_TIMING_FS3_OFFSET (0x0068)
#define I2C_TIMING_SLA_OFFSET (0x006C)
#define I2C_TIMING_ADDR_OFFSET (0x0070)
/* I2C_CTL */
#define I2C_CTL_CS_EN_SHIFT (0)
#define I2C_CTL_NO_TSCLH_SHIFT (1)
#define I2C_CTL_NO_1CYC_EDG_SDA_SHIFT (2)
#define I2C_CTL_MASTER_SHIFT (3)
#define I2C_CTL_RX_MODE_SHIFT (4)
#define I2C_CTL_TX_MODE_SHIFT (5)
#define I2C_CTL_RXCHON_SHIFT (6)
#define I2C_CTL_TXCHON_SHIFT (7)
#define I2C_CTL_CH_WIDTH_SHIFT (10)
#define I2C_CTL_BUS_WIDTH_SHIFT (12)
#define I2C_CTL_RX_BIT_SWAP_SHIFT (16)
#define I2C_CTL_TX_BIT_SWAP_SHIFT (19)
#define I2C_CTL_NO_ARB_FAST_SDA_SHIFT (28)
#define I2C_CTL_SW_RST_SHIFT (31)
#define I2C_CTL_CS_EN_MASK ((0x01) << I2C_CTL_CS_EN_SHIFT)
#define I2C_CTL_NO_TSCLH_MASK ((0x01) << I2C_CTL_NO_TSCLH_SHIFT)
#define I2C_CTL_NO_1CYC_EDG_SDA_MASK ((0x01) << I2C_CTL_NO_1CYC_EDG_SDA_SHIFT)
#define I2C_CTL_MASTER_MASK ((0x01) << I2C_CTL_MASTER_SHIFT)
#define I2C_CTL_RX_MODE_MASK ((0x01) << I2C_CTL_RX_MODE_SHIFT)
#define I2C_CTL_TX_MODE_MASK ((0x01) << I2C_CTL_TX_MODE_SHIFT)
#define I2C_CTL_RXCHON_MASK ((0x01) << I2C_CTL_RXCHON_SHIFT)
#define I2C_CTL_TXCHON_MASK ((0x01) << I2C_CTL_TXCHON_SHIFT)
#define I2C_CTL_CH_WIDTH_MASK ((0x03) << I2C_CTL_CH_WIDTH_SHIFT)
#define I2C_CTL_BUS_WIDTH_MASK ((0x03) << I2C_CTL_BUS_WIDTH_SHIFT)
#define I2C_CTL_RX_BIT_SWAP_MASK ((0x01) << I2C_CTL_RX_BIT_SWAP_SHIFT)
#define I2C_CTL_TX_BIT_SWAP_MASK ((0x01) << I2C_CTL_TX_BIT_SWAP_SHIFT)
#define I2C_CTL_NO_ARB_FAST_SDA_MASK ((0x01) << I2C_CTL_NO_ARB_FAST_SDA_SHIFT)
#define I2C_CTL_SW_RST_MASK ((0x01) << I2C_CTL_SW_RST_SHIFT)
#define I2C_CTL_CS_EN(c) ((c) << I2C_CTL_CS_EN_SHIFT)
#define I2C_CTL_NO_TSCLH(c) ((c) << I2C_CTL_NO_TSCLH_SHIFT)
#define I2C_CTL_NO_1CYC_EDG_SDA(c) ((c) << I2C_CTL_NO_1CYC_EDG_SDA_SHIFT)
#define I2C_CTL_MASTER(c) ((c) << I2C_CTL_MASTER_SHIFT)
#define I2C_CTL_RX_MODE(c) ((c) << I2C_CTL_RX_MODE_SHIFT)
#define I2C_CTL_TX_MODE(c) ((c) << I2C_CTL_TX_MODE_SHIFT)
#define I2C_CTL_RXCHON(c) ((c) << I2C_CTL_RXCHON_SHIFT)
#define I2C_CTL_TXCHON(c) ((c) << I2C_CTL_TXCHON_SHIFT)
#define I2C_CTL_CH_WIDTH(c) ((c) << I2C_CTL_CH_WIDTH_SHIFT)
#define I2C_CTL_BUS_WIDTH(c) ((c) << I2C_CTL_BUS_WIDTH_SHIFT)
#define I2C_CTL_RX_BIT_SWAP(c) ((c) << I2C_CTL_RX_BIT_SWAP_SHIFT)
#define I2C_CTL_TX_BIT_SWAP(c) ((c) << I2C_CTL_TX_BIT_SWAP_SHIFT)
#define I2C_CTL_NO_ARB_FAST_SDA(c) ((c) << I2C_CTL_NO_ARB_FAST_SDA_SHIFT)
#define I2C_CTL_SW_RST(c) ((c) << I2C_CTL_SW_RST_SHIFT)
/* I2C_FIFO_CTL */
#define I2C_FIFO_CTL_RXFIFO_EN_SHIFT (0)
#define I2C_FIFO_CTL_TXFIFO_EN_SHIFT (1)
#define I2C_FIFO_CTL_RXFIFO_RST_SHIFT (2)
#define I2C_FIFO_CTL_TXFIFO_RST_SHIFT (3)
#define I2C_FIFO_CTL_RXFIFO_TRIG_SHIFT (4)
#define I2C_FIFO_CTL_TXFIFO_TRIG_SHIFT (16)
#define I2C_FIFO_CTL_RXFIFO_EN_MASK (0x01 << I2C_FIFO_CTL_RXFIFO_EN_SHIFT)
#define I2C_FIFO_CTL_TXFIFO_EN_MASK (0x01 << I2C_FIFO_CTL_TXFIFO_EN_SHIFT)
#define I2C_FIFO_CTL_RXFIFO_RST_MASK (0x01 << I2C_FIFO_CTL_RXFIFO_RST_SHIFT)
#define I2C_FIFO_CTL_TXFIFO_RST_MASK (0x01 << I2C_FIFO_CTL_TXFIFO_RST_SHIFT)
#define I2C_FIFO_CTL_RXFIFO_TRIG_MASK (0x7F << I2C_FIFO_CTL_RXFIFO_TRIG_SHIFT)
#define I2C_FIFO_CTL_TXFIFO_TRIG_MASK (0x7F << I2C_FIFO_CTL_TXFIFO_TRIG_SHIFT)
#define I2C_FIFO_CTL_RXFIFO_EN(c) ((c) << I2C_FIFO_CTL_RXFIFO_EN_SHIFT)
#define I2C_FIFO_CTL_TXFIFO_EN(c) ((c) << I2C_FIFO_CTL_TXFIFO_EN_SHIFT)
#define I2C_FIFO_CTL_RXFIFO_RST(c) ((c) << I2C_FIFO_CTL_RXFIFO_RST_SHIFT)
#define I2C_FIFO_CTL_TXFIFO_RST(c) ((c) << I2C_FIFO_CTL_TXFIFO_RST_SHIFT)
#define I2C_FIFO_CTL_RXFIFO_TRIG(c) ((c) << I2C_FIFO_CTL_RXFIFO_TRIG_SHIFT)
#define I2C_FIFO_CTL_TXFIFO_TRIG(c) ((c) << I2C_FIFO_CTL_TXFIFO_TRIG_SHIFT)
/* I2C_TRAILING_CTL */
/* I2C_INT_EN */
#define I2C_INT_EN_TX_ALMOST_EMPTY_EN_SHIFT (0)
#define I2C_INT_EN_RX_ALMOST_FULL_EN_SHIFT (1)
#define I2C_INT_EN_TX_UNDERRUN_EN_SHIFT (2)
#define I2C_INT_EN_TX_OVERRUN_EN_SHIFT (3)
#define I2C_INT_EN_RX_UNDERRUN_EN_SHIFT (4)
#define I2C_INT_EN_RX_OVERRUN_EN_SHIFT (5)
#define I2C_INT_EN_TRAILING_EN_SHIFT (6)
#define I2C_INT_EN_XFER_DONE_AUTO_EN_SHIFT (7)
#define I2C_INT_EN_XFER_ABORT_AUTO_EN_SHIFT (8)
#define I2C_INT_EN_NO_DEV_ACK_AUTO_EN_SHIFT (9)
#define I2C_INT_EN_NO_DEV_AUTO_EN_SHIFT (10)
#define I2C_INT_EN_TIMEOUT_AUTO_EN_SHIFT (11)
#define I2C_INT_EN_XFER_DONE_NOACK_MANUAL_EN_SHIFT (12)
#define I2C_INT_EN_XFER_DONE_MANUAL_EN_SHIFT (13)
#define I2C_INT_EN_LOSE_ARB_MANUAL_EN_SHIFT (14)
#define I2C_INT_EN_SLAVE_ADDR_MATCH_EN_SHIFT (15)
#define I2C_INT_EN_ALL_MASK (0xFFFF)
#define I2C_INT_EN_TX_ALMOST_EMPTY_EN_MASK (0x01 << I2C_INT_EN_TX_ALMOST_EMPTY_EN_SHIFT)
#define I2C_INT_EN_RX_ALMOST_FULL_EN_MASK (0x01 << I2C_INT_EN_RX_ALMOST_FULL_EN_SHIFT)
#define I2C_INT_EN_TX_UNDERRUN_EN_MASK (0x01 << I2C_INT_EN_TX_UNDERRUN_EN_SHIFT)
#define I2C_INT_EN_TX_OVERRUN_EN_MASK (0x01 << I2C_INT_EN_TX_OVERRUN_EN_SHIFT)
#define I2C_INT_EN_RX_UNDERRUN_EN_MASK (0x01 << I2C_INT_EN_RX_UNDERRUN_EN_SHIFT)
#define I2C_INT_EN_RX_OVERRUN_EN_MASK (0x01 << I2C_INT_EN_RX_OVERRUN_EN_SHIFT)
#define I2C_INT_EN_TRAILING_EN_MASK (0x01 << I2C_INT_EN_TRAILING_EN_SHIFT)
#define I2C_INT_EN_XFER_DONE_AUTO_EN_MASK (0x01 << I2C_INT_EN_XFER_DONE_AUTO_EN_SHIFT)
#define I2C_INT_EN_XFER_ABORT_AUTO_EN_MASK (0x01 << I2C_INT_EN_XFER_ABORT_AUTO_EN_SHIFT)
#define I2C_INT_EN_NO_DEV_ACK_AUTO_EN_MASK (0x01 << I2C_INT_EN_NO_DEV_ACK_AUTO_EN_SHIFT)
#define I2C_INT_EN_NO_DEV_AUTO_EN_MASK (0x01 << I2C_INT_EN_NO_DEV_AUTO_EN_SHIFT)
#define I2C_INT_EN_TIMEOUT_AUTO_EN_MASK (0x01 << I2C_INT_EN_TIMEOUT_AUTO_EN_SHIFT)
#define I2C_INT_EN_XFER_DONE_NOACK_MANUAL_EN_MASK (0x01 << I2C_INT_EN_XFER_DONE_NOACK_MANUAL_EN_SHIFT)
#define I2C_INT_EN_XFER_DONE_MANUAL_EN_MASK (0x01 << I2C_INT_EN_XFER_DONE_MANUAL_EN_SHIFT)
#define I2C_INT_EN_LOSE_ARB_MANUAL_EN_MASK (0x01 << I2C_INT_EN_LOSE_ARB_MANUAL_EN_SHIFT)
#define I2C_INT_EN_SLAVE_ADDR_MATCH_EN_MASK (0x01 << I2C_INT_EN_SLAVE_ADDR_MATCH_EN_SHIFT)
#define I2C_INT_EN_TX_ALMOST_EMPTY_EN(c) ((c) << I2C_INT_EN_TX_ALMOST_EMPTY_EN_SHIFT)
#define I2C_INT_EN_RX_ALMOST_FULL_EN(c) ((c) << I2C_INT_EN_RX_ALMOST_FULL_EN_SHIFT)
#define I2C_INT_EN_TX_UNDERRUN_EN(c) ((c) << I2C_INT_EN_TX_UNDERRUN_EN_SHIFT)
#define I2C_INT_EN_TX_OVERRUN_EN(c) ((c) << I2C_INT_EN_TX_OVERRUN_EN_SHIFT)
#define I2C_INT_EN_RX_UNDERRUN_EN(c) ((c) << I2C_INT_EN_RX_UNDERRUN_EN_SHIFT)
#define I2C_INT_EN_RX_OVERRUN_EN(c) ((c) << I2C_INT_EN_RX_OVERRUN_EN_SHIFT)
#define I2C_INT_EN_TRAILING_EN(c) ((c) << I2C_INT_EN_TRAILING_EN_SHIFT)
#define I2C_INT_EN_XFER_DONE_AUTO_EN(c) ((c) << I2C_INT_EN_XFER_DONE_AUTO_EN_SHIFT)
#define I2C_INT_EN_XFER_ABORT_AUTO_EN(c) ((c) << I2C_INT_EN_XFER_ABORT_AUTO_EN_SHIFT)
#define I2C_INT_EN_NO_DEV_ACK_AUTO_EN(c) ((c) << I2C_INT_EN_NO_DEV_ACK_AUTO_EN_SHIFT)
#define I2C_INT_EN_NO_DEV_AUTO_EN(c) ((c) << I2C_INT_EN_NO_DEV_AUTO_EN_SHIFT)
#define I2C_INT_EN_TIMEOUT_AUTO_EN(c) ((c) << I2C_INT_EN_TIMEOUT_AUTO_EN_SHIFT)
#define I2C_INT_EN_XFER_DONE_NOACK_MANUAL_EN(c) ((c) << I2C_INT_EN_XFER_DONE_NOACK_MANUAL_EN_SHIFT)
#define I2C_INT_EN_XFER_DONE_MANUAL_EN(c) ((c) << I2C_INT_EN_XFER_DONE_MANUAL_EN_SHIFT)
#define I2C_INT_EN_LOSE_ARB_MANUAL_EN(c) ((c) << I2C_INT_EN_LOSE_ARB_MANUAL_EN_SHIFT)
#define I2C_INT_EN_SLAVE_ADDR_MATCH_EN(c) ((c) << I2C_INT_EN_SLAVE_ADDR_MATCH_EN_SHIFT)
/* I2C_INT_STAT */
#define I2C_INT_STAT_TX_ALMOST_EMPTY_SHIFT (0)
#define I2C_INT_STAT_RX_ALMOST_FULL_SHIFT (1)
#define I2C_INT_STAT_TX_OVERRUN_SHIFT (3)
#define I2C_INT_STAT_RX_UNDERRUN_SHIFT (4)
#define I2C_INT_STAT_RX_OVERRUN_SHIFT (5)
#define I2C_INT_STAT_TRAILING_SHIFT (6)
#define I2C_INT_STAT_XFER_DONE_AUTO_SHIFT (7)
#define I2C_INT_STAT_XFER_ABORT_AUTO_SHIFT (8)
#define I2C_INT_STAT_NO_DEV_ACK_AUTO_SHIFT (9)
#define I2C_INT_STAT_NO_DEV_AUTO_SHIFT (10)
#define I2C_INT_STAT_TIMEOUT_AUTO_SHIFT (11)
#define I2C_INT_STAT_XFER_DONE_NOACK_MANUAL_SHIFT (12)
#define I2C_INT_STAT_XFER_DONE_MANUAL_SHIFT (13)
#define I2C_INT_STAT_LOSE_ARB_MANUAL_SHIFT (14)
#define I2C_INT_STAT_SLAVE_ADDR_MATCH_SHIFT (15)
#define I2C_INT_STAT_TX_ALMOST_EMPTY_MASK (0x01 << I2C_INT_STAT_TX_ALMOST_EMPTY_SHIFT)
#define I2C_INT_STAT_RX_ALMOST_FULL_MASK (0x01 << I2C_INT_STAT_RX_ALMOST_FULL_SHIFT)
#define I2C_INT_STAT_TX_OVERRUN_MASK (0x01 << I2C_INT_STAT_TX_OVERRUN_SHIFT)
#define I2C_INT_STAT_RX_UNDERRUN_MASK (0x01 << I2C_INT_STAT_RX_UNDERRUN_SHIFT)
#define I2C_INT_STAT_RX_OVERRUN_MASK (0x01 << I2C_INT_STAT_RX_OVERRUN_SHIFT)
#define I2C_INT_STAT_TRAILING_MASK (0x01 << I2C_INT_STAT_TRAILING_SHIFT)
#define I2C_INT_STAT_XFER_DONE_AUTO_MASK (0x01 << I2C_INT_STAT_XFER_DONE_AUTO_SHIFT)
#define I2C_INT_STAT_XFER_ABORT_AUTO_MASK (0x01 << I2C_INT_STAT_XFER_ABORT_AUTO_SHIFT)
#define I2C_INT_STAT_NO_DEV_ACK_AUTO_MASK (0x01 << I2C_INT_STAT_NO_DEV_ACK_AUTO_SHIFT)
#define I2C_INT_STAT_NO_DEV_AUTO_MASK (0x01 << I2C_INT_STAT_NO_DEV_AUTO_SHIFT)
#define I2C_INT_STAT_TIMEOUT_AUTO_MASK (0x01 << I2C_INT_STAT_TIMEOUT_AUTO_SHIFT)
#define I2C_INT_STAT_XFER_DONE_NOACK_MANUAL_MASK (0x01 << I2C_INT_STAT_XFER_DONE_NOACK_MANUAL_SHIFT)
#define I2C_INT_STAT_XFER_DONE_MANUAL_MASK (0x01 << I2C_INT_STAT_XFER_DONE_MANUAL_SHIFT)
#define I2C_INT_STAT_LOSE_ARB_MANUAL_MASK (0x01 << I2C_INT_STAT_LOSE_ARB_MANUAL_SHIFT)
#define I2C_INT_STAT_SLAVE_ADDR_MATCH_MASK (0x01 << I2C_INT_STAT_SLAVE_ADDR_MATCH_SHIFT)
#define I2C_INT_STAT_TX_ALMOST_EMPTY(c) ((c) << I2C_INT_STAT_TX_ALMOST_EMPTY_SHIFT)
#define I2C_INT_STAT_RX_ALMOST_FULL(c) ((c) << I2C_INT_STAT_RX_ALMOST_FULL_SHIFT)
#define I2C_INT_STAT_TX_OVERRUN(c) ((c) << I2C_INT_STAT_TX_OVERRUN_SHIFT)
#define I2C_INT_STAT_RX_UNDERRUN(c) ((c) << I2C_INT_STAT_RX_UNDERRUN_SHIFT)
#define I2C_INT_STAT_RX_OVERRUN(c) ((c) << I2C_INT_STAT_RX_OVERRUN_SHIFT)
#define I2C_INT_STAT_TRAILING(c) ((c) << I2C_INT_STAT_TRAILING_SHIFT)
#define I2C_INT_STAT_XFER_DONE_AUTO(c) ((c) << I2C_INT_STAT_XFER_DONE_AUTO_SHIFT)
#define I2C_INT_STAT_XFER_ABORT_AUTO(c) ((c) << I2C_INT_STAT_XFER_ABORT_AUTO_SHIFT)
#define I2C_INT_STAT_NO_DEV_ACK_AUTO(c) ((c) << I2C_INT_STAT_NO_DEV_ACK_AUTO_SHIFT)
#define I2C_INT_STAT_NO_DEV_AUTO(c) ((c) << I2C_INT_STAT_NO_DEV_AUTO_SHIFT)
#define I2C_INT_STAT_TIMEOUT_AUTO(c) ((c) << I2C_INT_STAT_TIMEOUT_AUTO_SHIFT)
#define I2C_INT_STAT_XFER_DONE_NOACK_MANUAL(c) ((c) << I2C_INT_STAT_XFER_DONE_NOACK_MANUAL_SHIFT)
#define I2C_INT_STAT_XFER_DONE_MANUAL(c) ((c) << I2C_INT_STAT_XFER_DONE_MANUAL_SHIFT)
#define I2C_INT_STAT_LOSE_ARB_MANUAL(c) ((c) << I2C_INT_STAT_LOSE_ARB_MANUAL_SHIFT)
#define I2C_INT_STAT_SLAVE_ADDR_MATCH_(c) ((c) << I2C_INT_STAT_SLAVE_ADDR_MATCH_SHIFT)
/* I2C_FIFO_STAT */
#define I2C_FIFO_STAT_TX_FIFO_LEVEL_SHIFT (0)
#define I2C_FIFO_STAT_TX_FIFO_FULL_SHIFT (7)
#define I2C_FIFO_STAT_TX_FIFO_EMPTY_SHIFT (8)
#define I2C_FIFO_STAT_RX_FIFO_LEVEL_SHIFT (16)
#define I2C_FIFO_STAT_RX_FIFO_FULL_SHIFT (23)
#define I2C_FIFO_STAT_RX_FIFO_EMPTY_SHIFT (24)
#define I2C_FIFO_STAT_TX_FIFO_LEVEL_MASK (0x7F << I2C_FIFO_STAT_TX_FIFO_LEVEL_SHIFT)
#define I2C_FIFO_STAT_TX_FIFO_FULL_MASK (0x01 << I2C_FIFO_STAT_TX_FIFO_FULL_SHIFT)
#define I2C_FIFO_STAT_TX_FIFO_EMPTY_MASK (0x01 << I2C_FIFO_STAT_TX_FIFO_EMPTY_SHIFT)
#define I2C_FIFO_STAT_RX_FIFO_LEVEL_MASK (0x7F << I2C_FIFO_STAT_RX_FIFO_LEVEL_SHIFT)
#define I2C_FIFO_STAT_RX_FIFO_FULL_MASK (0x01 << I2C_FIFO_STAT_RX_FIFO_FULL_SHIFT)
#define I2C_FIFO_STAT_RX_FIFO_EMPTY_MASK (0x01 << I2C_FIFO_STAT_RX_FIFO_EMPTY_SHIFT)
#define I2C_FIFO_STAT_TX_FIFO_LEVEL(c) ((c) << I2C_FIFO_STAT_TX_FIFO_LEVEL_SHIFT)
#define I2C_FIFO_STAT_TX_FIFO_FULL(c) ((c) << I2C_FIFO_STAT_TX_FIFO_FULL_SHIFT)
#define I2C_FIFO_STAT_TX_FIFO_EMPTY(c) ((c) << I2C_FIFO_STAT_TX_FIFO_EMPTY_SHIFT)
#define I2C_FIFO_STAT_RX_FIFO_LEVEL(c) ((c) << I2C_FIFO_STAT_RX_FIFO_LEVEL_SHIFT)
#define I2C_FIFO_STAT_RX_FIFO_FULL(c) ((c) << I2C_FIFO_STAT_RX_FIFO_FULL_SHIFT)
#define I2C_FIFO_STAT_RX_FIFO_EMPTY(c) ((c) << I2C_FIFO_STAT_RX_FIFO_EMPTY_SHIFT)
#define I2C_CONF_TSTOPTOIDLE_SHIFT (0)
#define I2C_CONF_STRCH_EN_SHIFT (8)
#define I2C_CONF_STRCH_MANUAL_SHIFT (9)
#define I2C_CONF_FLT_CYCLE_SDA_SHIFT (13)
#define I2C_CONF_FLT_CYCLE_SCL_SHIFT (16)
#define I2C_CONF_FILTER_EN_SDA_SHIFT (27)
#define I2C_CONF_FILTER_EN_SCL_SHIFT (28)
#define I2C_CONF_HS_MODE_SHIFT (29)
#define I2C_CONF_ADDR_MODE_SHIFT (30)
#define I2C_CONF_AUTO_MODE_SHIFT (31)
#define I2C_CONF_TSTOPTOIDLE_MASK (0xFF << I2C_CONF_TSTOPTOIDLE_SHIFT)
#define I2C_CONF_STRCH_EN_MASK (0x01 << I2C_CONF_STRCH_EN_SHIFT)
#define I2C_CONF_STRCH_MANUAL_MASK (0x01 << I2C_CONF_STRCH_MANUAL_SHIFT)
#define I2C_CONF_FLT_CYCLE_SDA_MASK (0x07 << I2C_CONF_FLT_CYCLE_SDA_SHIFT)
#define I2C_CONF_FLT_CYCLE_SCL_MASK (0x07 << I2C_CONF_FLT_CYCLE_SCL_SHIFT)
#define I2C_CONF_FILTER_EN_SDA_MASK (0x01 << I2C_CONF_FILTER_EN_SDA_SHIFT)
#define I2C_CONF_FILTER_EN_SCL_MASK (0x01 << I2C_CONF_FILTER_EN_SCL_SHIFT)
#define I2C_CONF_HS_MODE_MASK (0x01 << I2C_CONF_HS_MODE_SHIFT)
#define I2C_CONF_ADDR_MODE_MASK (0x01 << I2C_CONF_ADDR_MODE_SHIFT)
#define I2C_CONF_AUTO_MODE_MASK (0x01 << I2C_CONF_AUTO_MODE_SHIFT)
#define I2C_CONF_TSTOPTOIDLE(c) ((c) << I2C_CONF_TSTOPTOIDLE_SHIFT)
#define I2C_CONF_STRCH_EN(c) ((c) << I2C_CONF_STRCH_EN_SHIFT)
#define I2C_CONF_STRCH_MANUAL(c) ((c) << I2C_CONF_STRCH_MANUAL_SHIFT)
#define I2C_CONF_FLT_CYCLE_SDA(c) ((c) << I2C_CONF_FLT_CYCLE_SDA_SHIFT)
#define I2C_CONF_FLT_CYCLE_SCL(c) ((c) << I2C_CONF_FLT_CYCLE_SCL_SHIFT)
#define I2C_CONF_FILTER_EN_SDA(c) ((c) << I2C_CONF_FILTER_EN_SDA_SHIFT)
#define I2C_CONF_FILTER_EN_SCL(c) ((c) << I2C_CONF_FILTER_EN_SCL_SHIFT)
#define I2C_CONF_HS_MODE(c) ((c) << I2C_CONF_HS_MODE_SHIFT)
#define I2C_CONF_ADDR_MODE(c) ((c) << I2C_CONF_ADDR_MODE_SHIFT)
#define I2C_CONF_AUTO_MODE(c) ((c) << I2C_CONF_AUTO_MODE_SHIFT)
/* I2C_AUTO_CONF */
#define I2C_AUTO_CONF_TRANS_LEN_SHIFT (0)
#define I2C_AUTO_CONF_READ_WRITE_SHIFT (16)
#define I2C_AUTO_CONF_STOP_AFTER_TRANS_SHIFT (17)
#define I2C_AUTO_CONF_MASTER_RUN_SHIFT (31)
#define I2C_AUTO_CONF_TRANS_LEN_MASK (0xFF << I2C_AUTO_CONF_TRANS_LEN_SHIFT)
#define I2C_AUTO_CONF_READ_WRITE_MASK (0x01 << I2C_AUTO_CONF_READ_WRITE_SHIFT)
#define I2C_AUTO_CONF_STOP_AFTER_TRANS_MASK (0x01 << I2C_AUTO_CONF_STOP_AFTER_TRANS_SHIFT)
#define I2C_AUTO_CONF_MASTER_RUN_MASK (0x01 << I2C_AUTO_CONF_MASTER_RUN_SHIFT)
#define I2C_AUTO_CONF_TRANS_LEN(c) ((c) << I2C_AUTO_CONF_TRANS_LEN_SHIFT)
#define I2C_AUTO_CONF_READ_WRITE(c) ((c) << I2C_AUTO_CONF_READ_WRITE_SHIFT)
#define I2C_AUTO_CONF_STOP_AFTER_TRANS(c) ((c) << I2C_AUTO_CONF_STOP_AFTER_TRANS_SHIFT)
#define I2C_AUTO_CONF_MASTER_RUN(c) ((c) << I2C_AUTO_CONF_MASTER_RUN_SHIFT)
/* I2C_TIMEOUT */
#define I2C_TIMEOUT_TOUT_COUNT_SHIFT (0)
#define I2C_TIMEOUT_TIMEOUT_EN_SHIFT (31)
#define I2C_TIMEOUT_TOUT_COUNT_MASK (0xFF << I2C_TIMEOUT_TOUT_COUNT_SHIFT)
#define I2C_TIMEOUT_TIMEOUT_EN_MASK (0x01 << I2C_TIMEOUT_TIMEOUT_EN_SHIFT)
#define I2C_TIMEOUT_TOUT_COUNT(c) ((c) << I2C_TIMEOUT_TOUT_COUNT_SHIFT)
#define I2C_TIMEOUT_TIMEOUT_EN(c) ((c) << I2C_TIMEOUT_TIMEOUT_EN_SHIFT)
/* I2C_MANUAL_CMD */
#define I2C_MANUAL_CMD_SEND_START_SHIFT (0)
#define I2C_MANUAL_CMD_SEND_RESTART_SHIFT (1)
#define I2C_MANUAL_CMD_SEND_STOP_SHIFT (2)
#define I2C_MANUAL_CMD_SEND_DATA_SHIFT (3)
#define I2C_MANUAL_CMD_READ_DATA_SHIFT (4)
#define I2C_MANUAL_CMD_RX_ACK_SHIFT (6)
#define I2C_MANUAL_CMD_RX_DATA_SHIFT (16)
#define I2C_MANUAL_CMD_TX_DATA_SHIFT (24)
#define I2C_MANUAL_CMD_SEND_START_MASK (0x01 << I2C_MANUAL_CMD_SEND_START_SHIFT)
#define I2C_MANUAL_CMD_SEND_RESTART_MASK (0x01 << I2C_MANUAL_CMD_SEND_RESTART_SHIFT)
#define I2C_MANUAL_CMD_SEND_STOP_MASK (0x01 << I2C_MANUAL_CMD_SEND_STOP_SHIFT)
#define I2C_MANUAL_CMD_SEND_DATA_MASK (0x01 << I2C_MANUAL_CMD_SEND_DATA_SHIFT)
#define I2C_MANUAL_CMD_READ_DATA_MASK (0x01 << I2C_MANUAL_CMD_READ_DATA_SHIFT)
#define I2C_MANUAL_CMD_RX_ACK_MASK (0x01 << I2C_MANUAL_CMD_RX_ACK_SHIFT)
#define I2C_MANUAL_CMD_RX_DATA_MASK (0xFF << I2C_MANUAL_CMD_RX_DATA_SHIFT)
#define I2C_MANUAL_CMD_TX_DATA_MASK (0xFF << I2C_MANUAL_CMD_TX_DATA_SHIFT)
#define I2C_MANUAL_CMD_SEND_START(c) ((c) << I2C_MANUAL_CMD_SEND_START_SHIFT)
#define I2C_MANUAL_CMD_SEND_RESTART(c) ((c) << I2C_MANUAL_CMD_SEND_RESTART_SHIFT)
#define I2C_MANUAL_CMD_SEND_STOP(c) ((c) << I2C_MANUAL_CMD_SEND_STOP_SHIFT)
#define I2C_MANUAL_CMD_SEND_DATA(c) ((c) << I2C_MANUAL_CMD_SEND_DATA_SHIFT)
#define I2C_MANUAL_CMD_READ_DATA(c) ((c) << I2C_MANUAL_CMD_READ_DATA_SHIFT)
#define I2C_MANUAL_CMD_RX_ACK(c) ((c) << I2C_MANUAL_CMD_RX_ACK_SHIFT)
#define I2C_MANUAL_CMD_RX_DATA(c) ((c) << I2C_MANUAL_CMD_RX_DATA_SHIFT)
#define I2C_MANUAL_CMD_TX_DATA(c) ((c) << I2C_MANUAL_CMD_TX_DATA_SHIFT)
/* I2C_TRANS_STATUS */
#define I2C_TRANS_STATUS_MASTER_ST_SHIFT (0)
#define I2C_TRANS_STATUS_SLAVE_SCL_STRETCH_SHIFT (15)
#define I2C_TRANS_STATUS_SLAVE_BUSY_SHIFT (16)
#define I2C_TRANS_STATUS_MASTER_BUSY_SHIFT (17)
#define I2C_TRANS_STATUS_STOP_COND_SHIFT (18)
#define I2C_TRANS_STATUS_SLAVE_RW_SHIFT (19)
#define I2C_TRANS_STATUS_MASTER_ST_MASK (0x0F << I2C_TRANS_STATUS_MASTER_ST_SHIFT)
#define I2C_TRANS_STATUS_SLAVE_SCL_STRETCH_MASK (0x00 << I2C_TRANS_STATUS_SLAVE_SCL_STRETCH_SHIFT)
#define I2C_TRANS_STATUS_SLAVE_BUSY_MASK (0x00 << I2C_TRANS_STATUS_SLAVE_BUSY_SHIFT)
#define I2C_TRANS_STATUS_MASTER_BUSY_MASK (0x00 << I2C_TRANS_STATUS_MASTER_BUSY_SHIFT)
#define I2C_TRANS_STATUS_STOP_COND_MASK (0x00 << I2C_TRANS_STATUS_STOP_COND_SHIFT)
#define I2C_TRANS_STATUS_SLAVE_RW_MASK (0x00 << I2C_TRANS_STATUS_SLAVE_RW_SHIFT)
#define I2C_TRANS_STATUS_MASTER_ST(c) ((c) << I2C_TRANS_STATUS_MASTER_ST_SHIFT)
#define I2C_TRANS_STATUS_SLAVE_SCL_STRETCH(c) ((c) << I2C_TRANS_STATUS_SLAVE_SCL_STRETCH_SHIFT)
#define I2C_TRANS_STATUS_SLAVE_BUSY(c) ((c) << I2C_TRANS_STATUS_SLAVE_BUSY_SHIFT)
#define I2C_TRANS_STATUS_MASTER_BUSY(c) ((c) << I2C_TRANS_STATUS_MASTER_BUSY_SHIFT)
#define I2C_TRANS_STATUS_STOP_COND(c) ((c) << I2C_TRANS_STATUS_STOP_COND_SHIFT)
#define I2C_TRANS_STATUS_SLAVE_RW(c) ((c) << I2C_TRANS_STATUS_SLAVE_RW_SHIFT)
/* I2C_TIMING_HS1 */
#define I2C_TIMING_HS1_TSDA_SU_HS_SHIFT (0)
#define I2C_TIMING_HS1_TSTOP_SU_HS_SHIFT (8)
#define I2C_TIMING_HS1_TSTART_HD_HS_SHIFT (16)
#define I2C_TIMING_HS1_TSTART_SU_HS_SHIFT (24)
#define I2C_TIMING_HS1_TSDA_SU_HS_MASK (0xFF << I2C_TIMING_HS1_TSDA_SU_HS_SHIFT)
#define I2C_TIMING_HS1_TSTOP_SU_HS_MASK (0xFF << I2C_TIMING_HS1_TSTOP_SU_HS_SHIFT)
#define I2C_TIMING_HS1_TSTART_HD_HS_MASK (0xFF << I2C_TIMING_HS1_TSTART_HD_HS_SHIFT)
#define I2C_TIMING_HS1_TSTART_SU_HS_MASK (0xFF << I2C_TIMING_HS1_TSTART_SU_HS_SHIFT)
#define I2C_TIMING_HS1_TSDA_SU_HS(c) ((c) << I2C_TIMING_HS1_TSDA_SU_HS_SHIFT)
#define I2C_TIMING_HS1_TSTOP_SU_HS(c) ((c) << I2C_TIMING_HS1_TSTOP_SU_HS_SHIFT)
#define I2C_TIMING_HS1_TSTART_HD_HS(c) ((c) << I2C_TIMING_HS1_TSTART_HD_HS_SHIFT)
#define I2C_TIMING_HS1_TSTART_SU_HS(c) ((c) << I2C_TIMING_HS1_TSTART_SU_HS_SHIFT)
/* I2C_TIMING_HS2 */
#define I2C_TIMING_HS2_TSCL_H_HS_SHIFT (0)
#define I2C_TIMING_HS2_TSCL_L_HS_SHIFT (8)
#define I2C_TIMING_HS2_TDATA_SU_HS_SHIFT (24)
#define I2C_TIMING_HS2_TSCL_H_HS_MASK (0xFF << I2C_TIMING_HS2_TSCL_H_HS_SHIFT)
#define I2C_TIMING_HS2_TSCL_L_HS_MASK (0xFF << I2C_TIMING_HS2_TSCL_L_HS_SHIFT)
#define I2C_TIMING_HS2_TDATA_SU_HS_MASK (0xFF << I2C_TIMING_HS2_TDATA_SU_HS_SHIFT)
#define I2C_TIMING_HS2_TSCL_H_HS(c) ((c) << I2C_TIMING_HS2_TSCL_H_HS_SHIFT)
#define I2C_TIMING_HS2_TSCL_L_HS(c) ((c) << I2C_TIMING_HS2_TSCL_L_HS_SHIFT)
#define I2C_TIMING_HS2_TDATA_SU_HS(c) ((c) << I2C_TIMING_HS2_TDATA_SU_HS_SHIFT)
/* I2C_TIMING_HS3 */
#define I2C_TIMING_HS3_TSR_RELEASE_SHIFT (0)
#define I2C_TIMING_HS3_CLK_DIV_SHIFT (16)
#define I2C_TIMING_HS3_TSR_RELEASE_MASK (0xFF << I2C_TIMING_HS3_TSR_RELEASE_SHIFT)
#define I2C_TIMING_HS3_CLK_DIV_MASK (0xFF << I2C_TIMING_HS3_CLK_DIV_SHIFT)
#define I2C_TIMING_HS3_TSR_RELEASE(c) ((c) << I2C_TIMING_HS3_TSR_RELEASE_SHIFT)
#define I2C_TIMING_HS3_CLK_DIV(c) ((c) << I2C_TIMING_HS3_CLK_DIV_SHIFT)
/* I2C_TIMING_FS1 */
#define I2C_TIMING_FS1_TSDA_SU_FS_SHIFT (0)
#define I2C_TIMING_FS1_TSTOP_SU_FS_SHIFT (8)
#define I2C_TIMING_FS1_TSTART_HD_FS_SHIFT (16)
#define I2C_TIMING_FS1_TSTART_SU_FS_SHIFT (24)
#define I2C_TIMING_FS1_TSDA_SU_FS_MASK (0xFF << I2C_TIMING_FS1_TSDA_SU_FS_SHIFT)
#define I2C_TIMING_FS1_TSTOP_SU_FS_MASK (0xFF << I2C_TIMING_FS1_TSTOP_SU_FS_SHIFT)
#define I2C_TIMING_FS1_TSTART_HD_FS_MASK (0xFF << I2C_TIMING_FS1_TSTART_HD_FS_SHIFT)
#define I2C_TIMING_FS1_TSTART_SU_FS_MASK (0xFF << I2C_TIMING_FS1_TSTART_SU_FS_SHIFT)
#define I2C_TIMING_FS1_TSDA_SU_FS(c) ((c) << I2C_TIMING_FS1_TSDA_SU_FS_SHIFT)
#define I2C_TIMING_FS1_TSTOP_SU_FS(c) ((c) << I2C_TIMING_FS1_TSTOP_SU_FS_SHIFT)
#define I2C_TIMING_FS1_TSTART_HD_FS(c) ((c) << I2C_TIMING_FS1_TSTART_HD_FS_SHIFT)
#define I2C_TIMING_FS1_TSTART_SU_FS(c) ((c) << I2C_TIMING_FS1_TSTART_SU_FS_SHIFT)
/* I2C_TIMING_FS2 */
#define I2C_TIMING_FS2_TSCL_H_FS_SHIFT (0)
#define I2C_TIMING_FS2_TSCL_L_FS_SHIFT (8)
#define I2C_TIMING_FS2_TDATA_SU_FS_SHIFT (24)
#define I2C_TIMING_FS2_TSCL_H_FS_MASK (0xFF << I2C_TIMING_FS2_TSCL_H_FS_SHIFT)
#define I2C_TIMING_FS2_TSCL_L_FS_MASK (0xFF << I2C_TIMING_FS2_TSCL_L_FS_SHIFT)
#define I2C_TIMING_FS2_TDATA_SU_FS_MASK (0xFF << I2C_TIMING_FS2_TDATA_SU_FS_SHIFT)
#define I2C_TIMING_FS2_TSCL_H_FS(c) ((c) << I2C_TIMING_FS2_TSCL_H_FS_SHIFT)
#define I2C_TIMING_FS2_TSCL_L_FS(c) ((c) << I2C_TIMING_FS2_TSCL_L_FS_SHIFT)
#define I2C_TIMING_FS2_TDATA_SU_FS(c) ((c) << I2C_TIMING_FS2_TDATA_SU_FS_SHIFT)
/* I2C_TIMING_FS3 */
#define I2C_TIMING_FS3_TSR_RELEASE_SHIFT (0)
#define I2C_TIMING_FS3_CLK_DIV_SHIFT (8)
#define I2C_TIMING_FS3_TSR_RELEASE_MASK (0xFF << I2C_TIMING_FS3_TSR_RELEASE_SHIFT)
#define I2C_TIMING_FS3_CLK_DIV_MASK (0xFF << I2C_TIMING_FS3_CLK_DIV_SHIFT)
#define I2C_TIMING_FS3_TSR_RELEASE(c) ((c) << I2C_TIMING_FS3_TSR_RELEASE_SHIFT)
#define I2C_TIMING_FS3_CLK_DIV(c) ((c) << I2C_TIMING_FS3_CLK_DIV_SHIFT)
/* I2C_TIMING_SLA */
/* I2C_ADDR */
#define I2C_ADDR_SLAVE_ADDR_SLA_SHIFT (0)
#define I2C_ADDR_SLAVE_ADDR_MAS_SHIFT (10)
#define I2C_ADDR_MASTERID_SHIFT (24)
#define I2C_ADDR_SLAVE_ADDR_SLA_MASK (0x3FFul << I2C_ADDR_SLAVE_ADDR_SLA_SHIFT)
#define I2C_ADDR_SLAVE_ADDR_MAS_MASK (0x3FFul << I2C_ADDR_SLAVE_ADDR_MAS_SHIFT)
#define I2C_ADDR_MASTERID_MASK (0x3FFul << I2C_ADDR_MASTERID_SHIFT)
#define I2C_ADDR_SLAVE_ADDR_SLA(c) ((c) << I2C_ADDR_SLAVE_ADDR_SLA_SHIFT)
#define I2C_ADDR_SLAVE_ADDR_MAS(c) ((c) << I2C_ADDR_SLAVE_ADDR_MAS_SHIFT)
#define I2C_ADDR_MASTERID(c) ((c) << I2C_ADDR_MASTERID_SHIFT)
#define I2C_FREQ_400KHZ (400000)
#define DEFAULT_I2CXFER_CLOCK I2C_FREQ_400KHZ
#define DEFAULT_I2CSLAVE_ADDR (0x5Fu)
#define DEFAULT_I2C_TIMEOUT (10000)
#define DEFAULT_I2C_TX_TRIGLVL (8u)
#define DEFAULT_I2C_RX_TRIGLVL (8u)
#define I2C_DEFAULT_I2CSLAVE_ADDR (0x77)
#define I2C_DEFAULT_MASTER_ADDRESS (0x09)
/* Msg flag */
#define I2C_M_WRITE (0x0000u)
#define I2C_M_READ (0x0001u)
#define I2C_M_TEN (0x0002u)
#define I2C_M_NORESTART (0x0080u)
#define I2C_M_IGNORE_NAK (0x1000u)
#define I2C_M_NOSTART (0x4000u)
#define I2C_M_NOSTOP (0x8000u)
/* Mode */
#define I2C_MANUAL (0x0000u)
#define I2C_AUTO (0x0010u)
#define I2C_INTERRUPT (0x0020u)
#define I2C_DMA (0x0040u)
#define I2C_MODE_Msk (0x0060u)
struct i2c_msg_s {
uint16_t addr; /**< Slave address */
uint32_t timeout;
uint16_t flags; /**< I2C flags; See I2C_M_* definitions */
uint16_t length; /**< The length of buffer */
uint8_t *buffer; /**< The Buffer for transferring message */
};
typedef struct _bp6a_i2c_priv_t_ {
uint32_t index;
int xfer_speed;
bool master;
uint32_t mode;
uint32_t slave_addr;
uint32_t addrlen;
uint32_t timeout;
/* master data */
uint8_t msgc; ///< Message count
struct i2c_msg_s *msgv; ///< Message list
uint16_t mflags; ///< Current message flags
/* slave data */
uint8_t *mptr; ///< Current message buffer
int mcnt; ///< Current message length
int cur_msg;
struct i2c_msg_s *msg;
volatile uint8_t st_slave_tx_master_rx;
volatile uint8_t st_slave_rx_master_tx;
volatile uint16_t int_stat;
} bp6a_i2c_priv_t;
void bp6a_i2c_master_init(uint32_t index, uint32_t freq, int addr_len);
void bp6a_i2c_slave_init(uint32_t index);
int bp6a_i2c_setaddress(uint32_t index, int addr, int nbits);
int bp6a_i2c_start(uint32_t index);
int bp6a_i2c_stop(uint32_t index);
void bp6a_i2c_reset(uint32_t index);
int bp6a_i2c_read_byte(uint32_t index, bool last);
int bp6a_i2c_write_byte(uint32_t index, int data);
int bp6a_i2c_read(uint32_t index, uint8_t *buffer, int buflen, int start, int stop);
int bp6a_i2c_write(uint32_t index, const uint8_t *buffer, int buflen, int start, int stop);
int bp6a_i2c_get_slave_status(uint32_t index);
void bp6a_i2c_set_slave_address(uint32_t index, int addr, bool is_slave);
#endif /*__S1SBP6A_I2C_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include <stdbool.h>
#include "s1sbp6a.h"
#include "s1sbp6a_type.h"
#include "s1sbp6a_pmu.h"
void PMU_SetSysconControl(pmu_syscon_ctrl_t field, bool enable)
{
modifyreg32(&BP_SYSCON->PMU_SYSCON_CTRL, 0x01 << field, enable << field);
}
bool PMU_GetSysconControl(pmu_syscon_ctrl_t field)
{
return !!((getreg32(&BP_SYSCON->PMU_SYSCON_CTRL) >> field) & 0x01);
}
void PMU_SetDelayControl(pmu_delay_ctrl_t field, uint32_t val)
{
uint32_t reg = (uint32_t)(&BP_SYSCON->PMU_SYSCON_DLY_CTRL);
uint32_t mask = 0x0F;
if (field > PMU_DLEAY_MCU_RESET_POWN_PD) {
reg = (uint32_t)(&BP_SYSCON->PMU_MCU_DLY_CTRL);
mask = 0xFF;
}
modifyreg32(reg, mask << field, (val & mask) << field);
}
uint32_t PMU_GetDelayControl(pmu_delay_ctrl_t field)
{
uint32_t reg = (uint32_t)(&BP_SYSCON->PMU_SYSCON_DLY_CTRL);
uint32_t mask = 0x0F;
if (field > PMU_DLEAY_MCU_RESET_POWN_PD) {
reg = (uint32_t)(&BP_SYSCON->PMU_MCU_DLY_CTRL);
mask = 0xFF;
}
return ((getreg32(reg) >> field) & mask);
}
void PMU_SetSysconDelayEnable(bool val)
{
putreg32(&BP_SYSCON->PMU_SYSCON_DLY_EN, (uint32_t)val);
}
bool PMU_GetSysconDelayEnable(void)
{
return !!(getreg32(&BP_SYSCON->PMU_SYSCON_DLY_EN));
}
void PMU_SetSysconFastBoot(bool val)
{
putreg32(&BP_SYSCON->PMU_SYSCON_FAST_BOOT, (uint32_t)val);
}
bool PMU_GetSysconFastBoot(void)
{
return !!(getreg32(&BP_SYSCON->PMU_SYSCON_FAST_BOOT));
}
void PMU_SetPowerControl(pmu_power_ctrl_t field, bool enable)
{
modifyreg32(&BP_SYSCON->PMU_SYSCON_PD_CTRL, 0x01 << field, enable << field);
}
bool PMU_GetPowerControl(pmu_power_ctrl_t field)
{
return !!((getreg32(&BP_SYSCON->PMU_SYSCON_PD_CTRL) >> field) & 0x01);
}
bool PMU_GetPowerStatus(pmu_power_ctrl_t field)
{
return !!((getreg32(&BP_SYSCON->PMU_SYSCON_PD_CTRL) >> field) & 0x01);
}
void PMU_SetRetentionControl(pmu_retention_ctrl_t field, bool enable)
{
modifyreg32(&BP_SYSCON->PMU_SYSCON_RET_CTRL, 0x1 << field, enable << field);
}
bool PMU_GetRetentionControl(pmu_retention_ctrl_t field, bool *pEnable)
{
return !!((getreg32(&BP_SYSCON->PMU_SYSCON_RET_CTRL) >> field) & 0x01);
}
void bp6a_power_mode(pmu_LPM_t mode)
{
switch (mode) {
case PMU_LPM0:
putreg32(&BP_SYSCTRL->PMUCTRL, 0x1);
PMU_SetRetentionControl(PMU_RETENTION_SYSTEM_POWER, true);
PMU_SetSysconControl(PMU_RTC_MODE_READY, true);
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__DSB();
__WFI();
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
break;
case PMU_LPM1:
putreg32(&BP_SYSCTRL->PMUCTRL, 0x1);
PMU_SetRetentionControl(PMU_RETENTION_SYSTEM_POWER, true);
modifyreg32(&BP_SYSCON->PMU_SYSCON_CTRL,
PMU_SYSCON_CTRL_RTCMODEREADY_MASK |
PMU_SYSCON_CTRL_STANBYTEADY_MASK |
PMU_SYSCON_CTRL_CORE_RETENTION_MASK |
PMU_SYSCON_CTRL_SYSTEM_RETENTION_MASK |
PMU_SYSCON_CTRL_HOSCEN_CTRL_MASK |
PMU_SYSCON_CTRL_LOSCEN_CTRL_MASK |
PMU_SYSCON_CTRL_PLLEN_CTRL_MASK |
PMU_SYSCON_CTRL_HOSCEN_SEQ_MASK |
PMU_SYSCON_CTRL_LOSCEN_SEQ_MASK |
PMU_SYSCON_CTRL_PLLEN_SEQ_MASK |
PMU_SYSCON_CTRL_MANUAL_OSC_MASK,
PMU_SYSCON_CTRL_RTCMODEREADY(0) |
PMU_SYSCON_CTRL_STANBYTEADY(0) |
PMU_SYSCON_CTRL_CORE_RETENTION(1) |
PMU_SYSCON_CTRL_SYSTEM_RETENTION(1) |
PMU_SYSCON_CTRL_HOSCEN_CTRL(1) |
PMU_SYSCON_CTRL_LOSCEN_CTRL(1) |
PMU_SYSCON_CTRL_PLLEN_CTRL(1) |
PMU_SYSCON_CTRL_HOSCEN_SEQ(1) |
PMU_SYSCON_CTRL_LOSCEN_SEQ(1) |
PMU_SYSCON_CTRL_PLLEN_SEQ(0) |
PMU_SYSCON_CTRL_MANUAL_OSC(1));
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PMU_SetSysconControl(PMU_STANDBY_MODE_READY, true);
__DSB();
__WFI();
PMU_SetSysconControl(PMU_STANDBY_MODE_READY, false);
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
PMU_SetRetentionControl(PMU_RETENTION_SYSTEM_POWER, false);
break;
case PMU_LPM2:
putreg32(&BP_SYSCTRL->PMUCTRL, 0x1);
PMU_SetRetentionControl(PMU_RETENTION_SYSTEM_POWER, true);
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__DSB();
__WFI();
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
PMU_SetRetentionControl(PMU_RETENTION_SYSTEM_POWER, false);
break;
case PMU_LPM3:
putreg32(&BP_SYSCTRL->PMUCTRL, 0x1);
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__DSB();
__WFI();
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
break;
case PMU_LPM4:
putreg32(&BP_SYSCTRL->PMUCTRL, 0x1);
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
__DSB();
__WFI();
break;
}
}
void bp6a_pum_init(void)
{
modifyreg32(&(BP_SYSCON->PMU_SYSCON_CTRL),
PMU_SYSCON_CTRL_RTCMODEREADY_MASK |
PMU_SYSCON_CTRL_STANBYTEADY_MASK |
PMU_SYSCON_CTRL_HOSCEN_CTRL_MASK |
PMU_SYSCON_CTRL_LOSCEN_CTRL_MASK |
PMU_SYSCON_CTRL_PLLEN_CTRL_MASK |
PMU_SYSCON_CTRL_HOSCEN_SEQ_MASK |
PMU_SYSCON_CTRL_LOSCEN_SEQ_MASK |
PMU_SYSCON_CTRL_PLLEN_SEQ_MASK |
PMU_SYSCON_CTRL_MANUAL_OSC_MASK,
PMU_SYSCON_CTRL_RTCMODEREADY(1) |
PMU_SYSCON_CTRL_STANBYTEADY(0) |
PMU_SYSCON_CTRL_HOSCEN_CTRL(1) |
PMU_SYSCON_CTRL_LOSCEN_CTRL(1) |
PMU_SYSCON_CTRL_PLLEN_CTRL(0) |
PMU_SYSCON_CTRL_HOSCEN_SEQ(1) |
PMU_SYSCON_CTRL_LOSCEN_SEQ(1) |
PMU_SYSCON_CTRL_PLLEN_SEQ(0) |
PMU_SYSCON_CTRL_MANUAL_OSC(1));
modifyreg32(&(BP_SYSCON->PMU_SYSCON_PD_CTRL),
PMU_SYSCON_PD_DSP_TMEM_MASK |
PMU_SYSCON_PD_DSP_DMEM_MASK |
PMU_SYSCON_PD_DECIM_MASK |
PMU_SYSCON_PD_DSP_MASK,
PMU_SYSCON_PD_DSP_TMEM(1) |
PMU_SYSCON_PD_DSP_DMEM(0x0F) |
PMU_SYSCON_PD_DSP(1) |
PMU_SYSCON_PD_DECIM(1));
modifyreg32(&(BP_SYSCON->PMU_SYSCON_PD_CTRL),
PMU_SYSCON_CHG_PWR_STATE_MASK,
PMU_SYSCON_CHG_PWR_STATE(1));
modifyreg32(&(BP_SYSCON->PMU_SYSCON_DLY_EN),
PMU_SYSCON_MCU_DLY_CTRL_PWR_GATING_MASK,
PMU_SYSCON_MCU_DLY_CTRL_PWR_GATING(0));
}

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_PMU_H
#define __S1SBP6A_PMU_H
#define PMU_SYSCON_CTRL_OFFSET (0x0000)
#define PMU_SYSCON_DLY_CTRL_OFFSET (0x0004)
#define PMU_SYSCON_MCU_DLY_CTRL_OFFSET (0x0008)
#define PMU_SYSCON_PD_CTRL_OFFSET (0x0200)
#define PMU_SYSCON_PD_STATUS_OFFSET (0x0204)
#define PMU_SYSCON_PMU_RET_CTRL_OFFSET (0x0208)
#define PMU_SYSCON_PMU_FLASH_MODE_OFFSET (0x020C)
/* PMU_SYSCON_CTRL */
#define PMU_SYSCON_CTRL_RTCMODEREADY_SHIFT (0)
#define PMU_SYSCON_CTRL_STANBYTEADY_SHIFT (1)
#define PMU_SYSCON_CTRL_CORE_RETENTION_SHIFT (2)
#define PMU_SYSCON_CTRL_SYSTEM_RETENTION_SHIFT (3)
#define PMU_SYSCON_CTRL_HOSCEN_CTRL_SHIFT (4)
#define PMU_SYSCON_CTRL_LOSCEN_CTRL_SHIFT (5)
#define PMU_SYSCON_CTRL_PLLEN_CTRL_SHIFT (6)
#define PMU_SYSCON_CTRL_HOSCEN_SEQ_SHIFT (7)
#define PMU_SYSCON_CTRL_LOSCEN_SEQ_SHIFT (8)
#define PMU_SYSCON_CTRL_PLLEN_SEQ_SHIFT (9)
#define PMU_SYSCON_CTRL_MANUAL_OSC_SHIFT (10)
#define PMU_SYSCON_CTRL_RTCMODEREADY_MASK (0x01 << PMU_SYSCON_CTRL_RTCMODEREADY_SHIFT)
#define PMU_SYSCON_CTRL_STANBYTEADY_MASK (0x01 << PMU_SYSCON_CTRL_STANBYTEADY_SHIFT)
#define PMU_SYSCON_CTRL_CORE_RETENTION_MASK (0x01 << PMU_SYSCON_CTRL_CORE_RETENTION_SHIFT)
#define PMU_SYSCON_CTRL_SYSTEM_RETENTION_MASK (0x01 << PMU_SYSCON_CTRL_SYSTEM_RETENTION_SHIFT)
#define PMU_SYSCON_CTRL_HOSCEN_CTRL_MASK (0x01 << PMU_SYSCON_CTRL_HOSCEN_CTRL_SHIFT)
#define PMU_SYSCON_CTRL_LOSCEN_CTRL_MASK (0x01 << PMU_SYSCON_CTRL_LOSCEN_CTRL_SHIFT)
#define PMU_SYSCON_CTRL_PLLEN_CTRL_MASK (0x01 << PMU_SYSCON_CTRL_PLLEN_CTRL_SHIFT)
#define PMU_SYSCON_CTRL_HOSCEN_SEQ_MASK (0x01 << PMU_SYSCON_CTRL_HOSCEN_SEQ_SHIFT)
#define PMU_SYSCON_CTRL_LOSCEN_SEQ_MASK (0x01 << PMU_SYSCON_CTRL_LOSCEN_SEQ_SHIFT)
#define PMU_SYSCON_CTRL_PLLEN_SEQ_MASK (0x01 << PMU_SYSCON_CTRL_PLLEN_SEQ_SHIFT)
#define PMU_SYSCON_CTRL_MANUAL_OSC_MASK (0x01 << PMU_SYSCON_CTRL_MANUAL_OSC_SHIFT)
#define PMU_SYSCON_CTRL_RTCMODEREADY(c) ((c) << PMU_SYSCON_CTRL_RTCMODEREADY_SHIFT)
#define PMU_SYSCON_CTRL_STANBYTEADY(c) ((c) << PMU_SYSCON_CTRL_STANBYTEADY_SHIFT)
#define PMU_SYSCON_CTRL_CORE_RETENTION(c) ((c) << PMU_SYSCON_CTRL_CORE_RETENTION_SHIFT)
#define PMU_SYSCON_CTRL_SYSTEM_RETENTION(c) ((c) << PMU_SYSCON_CTRL_SYSTEM_RETENTION_SHIFT)
#define PMU_SYSCON_CTRL_HOSCEN_CTRL(c) ((c) << PMU_SYSCON_CTRL_HOSCEN_CTRL_SHIFT)
#define PMU_SYSCON_CTRL_LOSCEN_CTRL(c) ((c) << PMU_SYSCON_CTRL_LOSCEN_CTRL_SHIFT)
#define PMU_SYSCON_CTRL_PLLEN_CTRL(c) ((c) << PMU_SYSCON_CTRL_PLLEN_CTRL_SHIFT)
#define PMU_SYSCON_CTRL_HOSCEN_SEQ(c) ((c) << PMU_SYSCON_CTRL_HOSCEN_SEQ_SHIFT)
#define PMU_SYSCON_CTRL_LOSCEN_SEQ(c) ((c) << PMU_SYSCON_CTRL_LOSCEN_SEQ_SHIFT)
#define PMU_SYSCON_CTRL_PLLEN_SEQ(c) ((c) << PMU_SYSCON_CTRL_PLLEN_SEQ_SHIFT)
#define PMU_SYSCON_CTRL_MANUAL_OSC(c) ((c) << PMU_SYSCON_CTRL_MANUAL_OSC_SHIFT)
/* PMU_SYSCON_DLY_CTRL_ */
#define PMU_SYSCON_DLY_CTRL_CLK_PU_SHIFT (0)
#define PMU_SYSCON_DLY_CTRL_MCURSTN_PU_SHIFT (4)
#define PMU_SYSCON_DLY_CTRL_FLASH_PU_SHIFT (8)
#define PMU_SYSCON_DLY_CTRL_FLASH_PD_SHIFT (12)
#define PMU_SYSCON_DLY_CTRL_MCURSTN_PD_SHIFT (16)
/* PMU_SYSCON_MCU_DLY_CTRL */
#define PMU_SYSCON_MCU_DLY_CTRL_ISO_SHIFT (0)
#define PMU_SYSCON_MCU_DLY_CTRL_RET_SHIFT (8)
#define PMU_SYSCON_MCU_DLY_CTRL_PWR_GATING_SHIFT (16)
#define PMU_SYSCON_MCU_DLY_CTRL_RSTN_SHIFT (24)
#define PMU_SYSCON_MCU_DLY_CTRL_ISO_MASK (0xff << PMU_SYSCON_MCU_DLY_CTRL_ISO_SHIFT)
#define PMU_SYSCON_MCU_DLY_CTRL_RET_MASK (0xff << PMU_SYSCON_MCU_DLY_CTRL_RET_SHIFT)
#define PMU_SYSCON_MCU_DLY_CTRL_PWR_GATING_MASK (0xff << PMU_SYSCON_MCU_DLY_CTRL_PWR_GATING_SHIFT)
#define PMU_SYSCON_MCU_DLY_CTRL_RSTN_MASK (0xff << PMU_SYSCON_MCU_DLY_CTRL_RSTN_SHIFT)
#define PMU_SYSCON_MCU_DLY_CTRL_ISO(c) ((c) << PMU_SYSCON_MCU_DLY_CTRL_ISO_SHIFT)
#define PMU_SYSCON_MCU_DLY_CTRL_RET(c) ((c) << PMU_SYSCON_MCU_DLY_CTRL_RET_SHIFT)
#define PMU_SYSCON_MCU_DLY_CTRL_PWR_GATING(c) ((c) << PMU_SYSCON_MCU_DLY_CTRL_PWR_GATING_SHIFT)
#define PMU_SYSCON_MCU_DLY_CTRL_RSTN(c) ((c) << PMU_SYSCON_MCU_DLY_CTRL_RSTN_SHIFT)
/* PMU_SYSCON_CTRL */
#define PMU_SYSCON_PD_MCU_SRAM_SHIFT (0)
#define PMU_SYSCON_PD_DSP_TMEM_SHIFT (8)
#define PMU_SYSCON_PD_DSP_DMEM_SHIFT (9)
#define PMU_SYSCON_PD_DSP_SHIFT (13)
#define PMU_SYSCON_PD_FCACHE_SHIFT (15)
#define PMU_SYSCON_PD_DECIM_SHIFT (16)
#define PMU_SYSCON_PD_FLASH_SHIFT (17)
#define PMU_SYSCON_CHG_PWR_STATE_SHIFT (19)
#define PMU_SYSCON_PD_MCU_SRAM_MASK (0xFF << PMU_SYSCON_PD_MCU_SRAM_SHIFT)
#define PMU_SYSCON_PD_DSP_TMEM_MASK (0x01 << PMU_SYSCON_PD_DSP_TMEM_SHIFT)
#define PMU_SYSCON_PD_DSP_DMEM_MASK (0x0F << PMU_SYSCON_PD_DSP_DMEM_SHIFT)
#define PMU_SYSCON_PD_DSP_MASK (0x01 << PMU_SYSCON_PD_DSP_SHIFT)
#define PMU_SYSCON_PD_FCACHE_MASK (0x01 << PMU_SYSCON_PD_FCACHE_SHIFT)
#define PMU_SYSCON_PD_DECIM_MASK (0x01 << PMU_SYSCON_PD_DECIM_SHIFT)
#define PMU_SYSCON_PD_FLASH_MASK (0x01 << PMU_SYSCON_PD_FLASH_SHIFT)
#define PMU_SYSCON_CHG_PWR_STATE_MASK (0x01 << PMU_SYSCON_CHG_PWR_STATE_SHIFT)
#define PMU_SYSCON_PD_MCU_SRAM(c) ((c) << PMU_SYSCON_PD_MCU_SRAM_SHIFT)
#define PMU_SYSCON_PD_DSP_TMEM(c) ((c) << PMU_SYSCON_PD_DSP_TMEM_SHIFT)
#define PMU_SYSCON_PD_DSP_DMEM(c) ((c) << PMU_SYSCON_PD_DSP_DMEM_SHIFT)
#define PMU_SYSCON_PD_DSP(c) ((c) << PMU_SYSCON_PD_DSP_SHIFT)
#define PMU_SYSCON_PD_FCACHE(c) ((c) << PMU_SYSCON_PD_FCACHE_SHIFT)
#define PMU_SYSCON_PD_DECIM(c) ((c) << PMU_SYSCON_PD_DECIM_SHIFT)
#define PMU_SYSCON_PD_FLASH(c) ((c) << PMU_SYSCON_PD_FLASH_SHIFT)
#define PMU_SYSCON_CHG_PWR_STATE(c) ((c) << PMU_SYSCON_CHG_PWR_STATE_SHIFT)
#define PMU_SYSCON_PD_MCU_SRAM_STATUS_SHIFT (0)
#define PMU_SYSCON_PD_DSP_TMEM_STATAUS_SHIFT (8)
#define PMU_SYSCON_PD_DSP_DMEM_STATUS_SHIFT (9)
#define PMU_SYSCON_PD_DSP_STATUS_SHIFT (13)
#define PMU_SYSCON_PD_FCACHE_STATUS_SHIFT (15)
#define PMU_SYSCON_PD_DECIM_STATUS_SHIFT (16)
#define PMU_SYSCON_PD_MCU_SRAM_STATUS_MASK (0xFF << PMU_SYSCON_PD_MCU_SRAM_STATUS_SHIFT)
#define PMU_SYSCON_PD_DSP_TMEM_STAUS_MASK (0x01 << PMU_SYSCON_PD_DSP_TMEM_STATAUS_SHIFT)
#define PMU_SYSCON_PD_DSP_DMEM_STATUS_MASK (0x0F << PMU_SYSCON_PD_DSP_DMEM_STATUS_SHIFT)
#define PMU_SYSCON_PD_DSP_STATUS_MASK (0x01 << PMU_SYSCON_PD_DSP_STATUS_SHIFT)
#define PMU_SYSCON_PD_FCACHE_STATUS_MASK (0x01 << PMU_SYSCON_PD_FCACHE_STATUS_SHIFT)
#define PMU_SYSCON_PD_DECIM_STATUS_MASK (0x01 << PMU_SYSCON_PD_DECIM_STATUS_SHIFT)
#define PMU_SYSCON_PD_MCU_SRAM_STATUS(c) ((c) << PMU_SYSCON_PD_MCU_SRAM_STATUS_SHIFT)
#define PMU_SYSCON_PD_DSP_TMEM_STAUS(c) ((c) << PMU_SYSCON_PD_DSP_TMEM_STATAUS_SHIFT)
#define PMU_SYSCON_PD_DSP_DMEM_STATUS(c) ((c) << PMU_SYSCON_PD_DSP_DMEM_STATUS_SHIFT)
#define PMU_SYSCON_PD_DSP_STATUS(c) ((c) << PMU_SYSCON_PD_DSP_STATUS_SHIFT)
#define PMU_SYSCON_PD_FCACHE_STATUS(c) ((c) << PMU_SYSCON_PD_FCACHE_STATUS_SHIFT)
#define PMU_SYSCON_PD_DECIM_STATUS(c) ((c) << PMU_SYSCON_PD_DECIM_STATUS_SHIFT)
#define PMU_SYSCON_PMU_RET_CTRL_MCU_SRAM_SHIFT (0)
#define PMU_SYSCON_PMU_RET_CTRL_DSP_TMEM_SHIFT (8)
#define PMU_SYSCON_PMU_RET_CTRL_DSP_DMEM_SHIFT (9)
#define PMU_SYSCON_PMU_RET_CTRL_FCHCHE_SHIFT (15)
#define PMU_SYSCON_PMU_RET_CTRL_DECIM_SHIFT (16)
#define PMU_SYSCON_PMU_RET_CTRL_SYSPWR_CTRL_SHIFT (19)
#define PMU_SYSCON_PMU_RET_CTRL_MCUMEM_PD_M_SHIFT (20)
#define PMU_SYSCON_PMU_RET_CTRL_DSP_RESET_SHIFT (21)
#define PMU_SYSCON_PMU_RET_CTRL_MCU_SRAM(c) ((c) << PMU_SYSCON_PMU_RET_CTRL_MCU_SRAM_SHIFT)
#define PMU_SYSCON_PMU_RET_CTRL_DSP_TMEM(c) ((c) << PMU_SYSCON_PMU_RET_CTRL_DSP_TMEM_SHIFT)
#define PMU_SYSCON_PMU_RET_CTRL_DSP_DMEM(c) ((c) << PMU_SYSCON_PMU_RET_CTRL_DSP_DMEM_SHIFT)
#define PMU_SYSCON_PMU_RET_CTRL_FCHCHE(c) ((c) << PMU_SYSCON_PMU_RET_CTRL_FCHCHE_SHIFT)
#define PMU_SYSCON_PMU_RET_CTRL_DECIM(c) ((c) << PMU_SYSCON_PMU_RET_CTRL_DECIM_SHIFT)
#define PMU_SYSCON_PMU_RET_CTRL_SYSPWR_CTRL(c) ((c) << PMU_SYSCON_PMU_RET_CTRL_SYSPWR_CTRL_SHIFT)
#define PMU_SYSCON_PMU_RET_CTRL_MCUMEM_PD_M(c) ((c) << PMU_SYSCON_PMU_RET_CTRL_MCUMEM_PD_M_SHIFT)
#define PMU_SYSCON_PMU_RET_CTRL_DSP_RESET(c) ((c) << PMU_SYSCON_PMU_RET_CTRL_DSP_RESET_SHIFT)
#define PMU_SYSCON_PMU_FLASH_MODE_OFFSET (0x020C)
typedef enum _pmu_retention_ctrl_t {
PMU_RETENTION_MCU_SRAM0 = PMU_SYSCON_PMU_RET_CTRL_MCU_SRAM_SHIFT,
PMU_RETENTION_MCU_SRAM1,
PMU_RETENTION_MCU_SRAM2,
PMU_RETENTION_MCU_SRAM3,
PMU_RETENTION_MCU_SRAM4,
PMU_RETENTION_MCU_SRAM5,
PMU_RETENTION_MCU_SRAM6,
PMU_RETENTION_MCU_SRAM7,
PMU_RETENTION_DSP_TMEM,
PMU_RETENTION_DSP_DMEM0,
PMU_RETENTION_DSP_DMEM1,
PMU_RETENTION_DSP_DMEM2,
PMU_RETENTION_DSP_DMEM3,
PMU_RETENTION_FCACHE = PMU_SYSCON_PMU_RET_CTRL_FCHCHE_SHIFT,
PMU_RETENTION_DECIM,
PMU_RETENTION_SYSTEM_POWER = PMU_SYSCON_PMU_RET_CTRL_SYSPWR_CTRL_SHIFT,
PMU_SRP_RESET_CTRL,
} pmu_retention_ctrl_t;
typedef enum {
PMU_POWER_DOWN_MCU_SRAM0 = PMU_SYSCON_PD_MCU_SRAM_SHIFT,
PMU_POWER_DOWN_MCU_SRAM1,
PMU_POWER_DOWN_MCU_SRAM2,
PMU_POWER_DOWN_MCU_SRAM3,
PMU_POWER_DOWN_MCU_SRAM4,
PMU_POWER_DOWN_MCU_SRAM5,
PMU_POWER_DOWN_MCU_SRAM6,
PMU_POWER_DOWN_MCU_SRAM7,
PMU_POWER_DOWN_DSP_TMEM = PMU_SYSCON_PD_DSP_TMEM_SHIFT,
PMU_POWER_DOWN_DSP_DMEM0,
PMU_POWER_DOWN_DSP_DMEM1,
PMU_POWER_DOWN_DSP_DMEM2,
PMU_POWER_DOWN_DSP_DMEM3,
PMU_POWER_DOWN_DSP = PMU_SYSCON_PD_DSP_SHIFT,
PMU_POWER_DOWN_FCACHE = PMU_SYSCON_PD_FCACHE_SHIFT,
PMU_POWER_DOWN_DECIM = PMU_SYSCON_PD_DECIM_SHIFT,
PMU_POWER_DOWN_FLASH = PMU_SYSCON_PD_FLASH_SHIFT,
PMU_CHANGE_POWER_STATE = PMU_SYSCON_CHG_PWR_STATE_SHIFT,
} pmu_power_ctrl_t;
typedef enum {
PMU_RTC_MODE_READY = PMU_SYSCON_CTRL_RTCMODEREADY_SHIFT,
PMU_STANDBY_MODE_READY = PMU_SYSCON_CTRL_STANBYTEADY_SHIFT,
PMU_CORE_RETENTION = PMU_SYSCON_CTRL_CORE_RETENTION_SHIFT,
PMU_SYSTEM_RETENTION = PMU_SYSCON_CTRL_SYSTEM_RETENTION_SHIFT,
PMU_HOSC_ENABLE_PD = PMU_SYSCON_CTRL_HOSCEN_CTRL_SHIFT,
PMU_LOSC_ENABLE_PD = PMU_SYSCON_CTRL_LOSCEN_CTRL_SHIFT,
PMU_PLL_ENABLE_PD = PMU_SYSCON_CTRL_PLLEN_CTRL_SHIFT,
PMU_HOSC_ENABLE_PU = PMU_SYSCON_CTRL_HOSCEN_SEQ_SHIFT,
PMU_LOSC_ENABLE_PU = PMU_SYSCON_CTRL_LOSCEN_SEQ_SHIFT,
PMU_PLL_ENABLE_PU = PMU_SYSCON_CTRL_PLLEN_SEQ_SHIFT,
PMU_MANUAL_OSC_CTRL = PMU_SYSCON_CTRL_MANUAL_OSC_SHIFT,
} pmu_syscon_ctrl_t;
typedef enum {
PMU_DELAY_CLOCK_ENABLE_PU = PMU_SYSCON_DLY_CTRL_CLK_PU_SHIFT,
PMU_DELAY_MCU_RESET_RELEASE_PU = PMU_SYSCON_DLY_CTRL_MCURSTN_PU_SHIFT,
PMU_DELAY_FLASH_POWER_DOWN_PU = PMU_SYSCON_DLY_CTRL_FLASH_PU_SHIFT,
PMU_DELAY_FLASH_POWER_DOWN_PD = PMU_SYSCON_DLY_CTRL_FLASH_PD_SHIFT,
PMU_DLEAY_MCU_RESET_POWN_PD = PMU_SYSCON_DLY_CTRL_MCURSTN_PD_SHIFT,
PMU_DELAY_ISOLATION_STATE_PUPD = PMU_SYSCON_MCU_DLY_CTRL_ISO_SHIFT,
PMU_DELAY_RETENTION_STATE_PUPD = PMU_SYSCON_MCU_DLY_CTRL_RET_SHIFT,
PMU_DELAY_POWER_GATING = PMU_SYSCON_MCU_DLY_CTRL_PWR_GATING_SHIFT,
PMU_DELAY_RESET_STATE_PUPD = PMU_SYSCON_MCU_DLY_CTRL_RSTN_SHIFT,
} pmu_delay_ctrl_t;
typedef enum {
PMU_LPM0,
PMU_LPM1,
PMU_LPM2,
PMU_LPM3,
PMU_LPM4,
} pmu_LPM_t;
void bp6a_pum_init(void);
void bp6a_power_mode(pmu_LPM_t mode);
#endif /* __S1SBP6A_PMU_H*/

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include <stdbool.h>
#include "s1sbp6a.h"
#include "s1sbp6a_type.h"
#include "s1sbp6a_rtc.h"
#include "mbed_debug.h"
static uint32_t grtc_load_delay = 1500;
static void bp6a_rtc_unlock(bool unlock)
{
BP_SYSCON->KA_ACCESS = unlock;
}
int bp6a_rtc_bcd2bin(uint8_t bcd)
{
return ((bcd & 0xF0u) >> 4u) * 10 + (bcd & 0x0Fu);
}
uint32_t bp6a_rtc_bin2bcd(uint8_t bin)
{
return ((bin / 10u) << 4u) + (bin % 10);
}
void bp6a_rtc_getdatetime(struct rtc_bcd_s *rtc)
{
bp6a_rtc_unlock(true);
BP_RTC->CALENDAR_TIME_STAMP = 1;
_Wait(grtc_load_delay);
/* read bcd counters */
do {
rtc->sec = BP_RTC->BCD_R.SEC;
rtc->min = BP_RTC->BCD_R.MIN;
rtc->hour = BP_RTC->BCD_R.HOUR;
rtc->day = BP_RTC->BCD_R.DAY;
rtc->mon = (BP_RTC->BCD_R.MON >> 3) & 0x0F;
rtc->year = BP_RTC->BCD_R.YEAR & 0x3Fu;
} while (rtc->sec != BP_RTC->BCD_R.SEC);
bp6a_rtc_unlock(false);
}
void bp6a_rtc_setdatetime(struct rtc_bcd_s *rtc)
{
bp6a_rtc_unlock(true);
/* update BCD counters */
BP_RTC->BCD_W.SEC = rtc->sec;
BP_RTC->BCD_W.MIN = rtc->min;
BP_RTC->BCD_W.HOUR = rtc->hour;
BP_RTC->BCD_W.DAY = rtc->day;
BP_RTC->BCD_W.MON = ((uint32_t)rtc->mon << 4);
BP_RTC->BCD_W.YEAR = rtc->year & 0x3Fu;
BP_RTC->LOAD_COUNT_SIG = 0x7F;
_Wait(grtc_load_delay);
bp6a_rtc_unlock(false);
}
void bp6a_set_rtc_delay(uint32_t delay)
{
grtc_load_delay = delay;
}
void bp6a_rtc_init(void)
{
bp6a_rtc_unlock(true);
BP_RTC->ALARM_ENABLE = 0;
BP_RTC->INT_ENABLE_CPU = 0;
BP_RTC->INT_CLEAR_CPU = 0;
BP_RTC->CALENDAR_MODE = 0x03;
bp6a_rtc_unlock(false);
}

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_RTC_H
#define __S1SBP6A_RTC_H
#include <stdbool.h>
struct rtc_bcd_s {
uint8_t sec;
uint8_t min;
uint8_t hour;
uint8_t day;
uint8_t mon;
uint16_t year;
};
int bp6a_rtc_bcd2bin(uint8_t bcd);
uint32_t bp6a_rtc_bin2bcd(uint8_t bin);
void bp6a_rtc_getdatetime(struct rtc_bcd_s *rtc);
void bp6a_rtc_setdatetime(struct rtc_bcd_s *rtc);
void bp6a_rtc_init(void);
void bp6a_set_rtc_delay(uint32_t delay);
#endif /*__S1SBP6A_RTC_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_SPI_H
#define __S1SBP6A_SPI_H
#define SSP_CR0_OFFSET (0x0000) /* Control Register 0 */
#define SSP_CR1_OFFSET (0x0004) /* Control Register 1 */
#define SSP_DR_OFFSET (0x0008) /* Data Register */
#define SSP_SR_OFFSET (0x000c) /* Status Register */
#define SSP_CPSR_OFFSET (0x0010) /* Clock Prescale Register */
#define SSP_IMSC_OFFSET (0x0014) /* Interrupt Mask Set and Clear Register */
#define SSP_RIS_OFFSET (0x0018) /* Raw Interrupt Status Register */
#define SSP_MIS_OFFSET (0x001c) /* Masked Interrupt Status Register */
#define SSP_ICR_OFFSET (0x0020) /* Interrupt Clear Register */
#define SSP_DMACR_OFFSET (0x0024) /* DMA Control Register */
/* Control Register 0 */
#define SSP_CR0_DSS_SHIFT (0)
#define SSP_CR0_FRF_SHIFT (4)
#define SSP_CR0_SPO_SHIFT (6)
#define SSP_CR0_SPH_SHIFT (7)
#define SSP_CR0_SCR_SHIFT (8)
#define SSP_CR0_DSS_MASK (0x0f << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_FRF_MASK (0x03 << SSP_CR0_FRF_SHIFT)
#define SSP_CR0_SPO_MASK (0x01 << SSP_CR0_SPO_SHIFT)
#define SSP_CR0_SPH_MASK (0x01 << SSP_CR0_SPH_SHIFT)
#define SSP_CR0_SCR_MASK (0xff << SSP_CR0_SCR_SHIFT)
#define SSP_CR0_DSS(c) ((c) << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_FRF(c) ((c) << SSP_CR0_FRF_SHIFT)
#define SSP_CR0_SPO(c) ((c) << SSP_CR0_SPO_SHIFT)
#define SSP_CR0_SPH(c) ((c) << SSP_CR0_SPH_SHIFT)
#define SSP_CR0_SCR(c) ((c) << SSP_CR0_SCR_SHIFT)
#define SSP_CR0_DSS_4BIT (3 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_5BIT (4 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_6BIT (5 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_7BIT (6 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_8BIT (7 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_9BIT (8 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_10BIT (9 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_11BIT (10 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_12BIT (11 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_13BIT (12 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_14BIT (13 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_15BIT (14 << SSP_CR0_DSS_SHIFT)
#define SSP_CR0_DSS_16BIT (15 << SSP_CR0_DSS_SHIFT)
/* Control Register 1 */
#define SSP_CR1_LBM_SHIFT (0)
#define SSP_CR1_SSE_SHIFT (1)
#define SSP_CR1_MS_SHIFT (2)
#define SSP_CR1_SOD_SHIFT (3)
#define SSP_CR1_RXIFLSEL_SHIFT (4)
#define SSP_CR1_MFSS_SHIFT (7)
#define SSP_CR1_RXFIFOCLR_SHIFT (8)
#define SSP_CR1_TXFIFOCLR_SHIFT (9)
#define SSP_CR1_TXIFLSEL_SHIFT (10)
#define SSP_CR1_LBM_MASK (0x01 << SSP_CR1_LBM_SHIFT)
#define SSP_CR1_SSE_MASK (0x01 << SSP_CR1_SSE_SHIFT)
#define SSP_CR1_MS_MASK (0x01 << SSP_CR1_MS_SHIFT)
#define SSP_CR1_SOD_MASK (0x01 << SSP_CR1_SOD_SHIFT)
#define SSP_CR1_RXIFLSEL_MASK (0x07 << SSP_CR1_RXIFLSEL_SHIFT)
#define SSP_CR1_MFSS_MASK (0x01 << SSP_CR1_MFSS_SHIFT)
#define SSP_CR1_RXFIFOCLR_MASK (0x01 << SSP_CR1_RXFIFOCLR_SHIFT)
#define SSP_CR1_TXFIFOCLR_MASK (0x01 << SSP_CR1_TXFIFOCLR_SHIFT)
#define SSP_CR1_TXIFLSEL_MASK (0x07 << SSP_CR1_TXIFLSEL_SHIFT)
#define SSP_CR1_LBM(c) ((c) << SSP_CR1_LBM_SHIFT)
#define SSP_CR1_SSE(c) ((c) << SSP_CR1_SSE_SHIFT)
#define SSP_CR1_MS(c) ((c) << SSP_CR1_MS_SHIFT)
#define SSP_CR1_SOD(c) ((c) << SSP_CR1_SOD_SHIFT)
#define SSP_CR1_RXIFLSEL(c) ((c) << SSP_CR1_RXIFLSEL_SHIFT)
#define SSP_CR1_MFSS(c) ((c) << SSP_CR1_MFSS_SHIFT)
#define SSP_CR1_RXFIFOCLR(c) ((c) << SSP_CR1_RXFIFOCLR_SHIFT)
#define SSP_CR1_TXFIFOCLR(c) ((c) << SSP_CR1_TXFIFOCLR_SHIFT)
#define SSP_CR1_TXIFLSEL(c) ((c) << SSP_CR1_TXIFLSEL_SHIFT)
/* Status Register */
#define SSP_SR_TFE_SHIFT (0)
#define SSP_SR_TNF_SHIFT (1)
#define SSP_SR_RNE_SHIFT (2)
#define SSP_SR_RFF_SHIFT (3)
#define SSP_SR_BSY_SHIFT (4)
#define SSP_SR_RXFIFO_SHIFT (5)
#define SSP_SR_TXFIFO_SHIFT (9)
#define SSP_SR_TFE_MASK ((0x01) << SSP_SR_TFE_SHIFT)
#define SSP_SR_TNF_MASK ((0x01) << SSP_SR_TNF_SHIFT)
#define SSP_SR_RNE_MASK ((0x01) << SSP_SR_RNE_SHIFT)
#define SSP_SR_RFF_MASK ((0x01) << SSP_SR_RFF_SHIFT)
#define SSP_SR_BSY_MASK ((0x01) << SSP_SR_BSY_SHIFT)
#define SSP_SR_RXFIFO_MASK ((0x0F) << SSP_SR_RXFIFO_SHIFT)
#define SSP_SR_TXFIFO_MASK ((0x0F) << SSP_SR_TXFIFO_SHIFT)
#define SSP_SR_TFE(c) ((c) << SSP_SR_TFE_SHIFT)
#define SSP_SR_TNF(c) ((c) << SSP_SR_TNF_SHIFT)
#define SSP_SR_RNE(c) ((c) << SSP_SR_RNE_SHIFT)
#define SSP_SR_RFF(c) ((c) << SSP_SR_RFF_SHIFT)
#define SSP_SR_BSY(c) ((c) << SSP_SR_BSY_SHIFT)
#define SSP_SR_RXFIFO(c) ((c) << SSP_SR_RXFIFO_SHIFT)
#define SSP_SR_TXFIFO(c) ((c) << SSP_SR_TXFIFO_SHIFT)
#define isTXFIFOEmpty(c) (((c)& SSP_SR_TFE_MASK) >> SSP_SR_TFE_SHIFT)
#define isTXFIFOFull(c) (!((c)& SSP_SR_TNF_MASK))
#define isRXFIFOEmpty(c) (((c)& SSP_SR_RNE_MASK) >> SSP_SR_RNE_SHIFT)
#define isRXFIFOFull(c) (!((c)& SSP_SR_RFF_MASK))
#define isBusy(c) (((c)& SSP_SR_BSY_MASK) >> SSP_SR_BSY_SHIFT)
/* Interrupt mask Regsiter */
#define SSP_IMSC_RORIM_SHIFT (0)
#define SSP_IMSC_RTIM_SHIFT (1)
#define SSP_IMSC_RXIM_SHIFT (2)
#define SSP_IMSC_TXIM_SHIFT (3)
#define SSP_IMSC_RORIM_MASK ((0x01) << SSP_IMSC_RORIM_SHIFT)
#define SSP_IMSC_RTIM_MASK ((0x01) << SSP_IMSC_RTIM_SHIFT)
#define SSP_IMSC_RXIM_MASK ((0x01) << SSP_IMSC_RXIM_SHIFT)
#define SSP_IMSC_TXIM_MASK ((0x01) << SSP_IMSC_TXIM_SHIFT)
#define SSP_IMSC_RORIM(c) ((c) << SSP_IMSC_RORIM_SHIFT
#define SSP_IMSC_RTIM(c) ((c) << SSP_IMSC_RTIM_SHIFT)
#define SSP_IMSC_RXIM(c) ((c) << SSP_IMSC_RXIM_SHIFT)
#define SSP_IMSC_TXIM(c) ((c) << SSP_IMSC_TXIM_SHIFT)
/* Interrupt status Regsiter */
#define SSP_RIS_ROROS_SHIFT (0)
#define SSP_RIS_RTRIS_SHIFT (1)
#define SSP_RIS_RXRIS_SHIFT (2)
#define SSP_RIS_TXRIS_SHIFT (3)
#define SSP_RIS_ROROS_MASK ((0x01) << SSP_RIS_ROROS_SHIFT)
#define SSP_RIS_RTRIS_MASK ((0x01) << SSP_RIS_RTRIS_SHIFT)
#define SSP_RIS_RXRIS_MASK ((0x01) << SSP_RIS_RXRIS_SHIFT)
#define SSP_RIS_TXRIS_MASK ((0x01) << SSP_RIS_TXRIS_SHIFT)
#define SSP_RIS_ROROS(c) ((c) << SSP_RIS_ROROS_SHIFT)
#define SSP_RIS_RTRIS(c) ((c) << SSP_RIS_RTRIS_SHIFT)
#define SSP_RIS_RXRIS(c) ((c) << SSP_RIS_RXRIS_SHIFT)
#define SSP_RIS_TXRIS(c) ((c) << SSP_RIS_TXRIS_SHIFT)
/* Interrupt clear Regsiter */
#define SSP_ICR_RORIC_SHIFT (0)
#define SSP_ICR_RTIC_SHIFT (1)
#define SSP_RORIC_MASK ((0x01) << SSP_ICR_RORIC_SHIFT)
#define SSP_RTIC_MASK ((0x01) << SSP_ICR_RTIC_SHIFT)
#define SSP_RORIC(c) ((c) << SSP_ICR_RORIC_SHIFT)
#define SSP_RTIC(c) ((c) << SSP_ICR_RTIC_SHIFT)
/* DMA Control Regsiter */
#define SSP_DMACTR_RXDMAE_SHIFT (0)
#define SSP_DMACTR_TXDMAE_SHIFT (1)
#define SSP_DMACTR_RXDMAE_MASK ((0x01) << SSP_DMACTR_RXDMAE_SHIFT)
#define SSP_DMACTR_TXDMAE_MASK ((0x01) << SSP_DMACTR_TXDMAE_SHIFT)
#define SSP_DMACTR_RXDMAE(c) ((c) << SSP_DMACTR_RXDMAE_SHIFT)
#define SSP_DMACTR_TXDMAE(c) ((c) << SSP_DMACTR_TXDMAE_SHIFT)
#endif /*__S1SBP6A_SPI_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_TYPE_H
#define __S1SBP6A_TYPE_H
#define _Wait(tick) { \
volatile uint32_t cnt = tick; \
while(cnt--); \
}
#define UNUSED(a) ((void)(a))
#define getreg8(a) (*(volatile uint8_t *)(a))
#define putreg8(a, v) (*(volatile uint8_t *)(a) = (v))
#define getreg32(a) (*(volatile uint32_t *)(a))
#define putreg32(a, v) (*(volatile uint32_t *)(a) = (v))
#define modifyreg32(a, m, v) putreg32((a),(((getreg32(a)) & ~(m)) | ((v) & (m))))
#endif /* __S1SBP6A_TYPE_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_UART_H
#define __S1SBP6A_UART_H
#define UART_ULCON_OFFSET 0x0000
#define UART_UCON_OFFSET 0x0004
#define UART_UFCON_OFFSET 0x0008
#define UART_UMCON_OFFSET 0x000C
#define UART_UTRSTAT_OFFSET 0x0010
#define UART_UERSTAT_OFFSET 0x0014
#define UART_UFSTAT_OFFSET 0x0018
#define UART_UTXH_OFFSET 0x0020
#define UART_URXH_OFFSET 0x0024
#define UART_UBRDIV_OFFSET 0x0028
#define UART_UFRAC_OFFSET 0x002C
#define UART_UINTP_OFFSET 0x0030
#define UART_UINTS_OFFSET 0x0034
#define UART_UINTM_OFFSET 0x0038
#define RCV_BUF_DATA_READY (0x01<<0)
#define TX_BUF_EMPTY (0x01<<1)
#define TX_EMPTY (0x01<<2)
#define RX_TIMEOUT_CLR (0x01<<3)
#define RX_DMA_FSM_STA (0x0F<<8)
#define TX_DMA_FSM_STA (0x0F<<12)
#define RX_FIFO_CNT (0xFF<<16)
/* UART ULCON */
#define UART_ULCON_WORD_LEN_SHIFT (0)
#define UART_ULCON_N_STOP_BIT_SHIFT (2)
#define UART_ULCON_PARITY_MODE_SHIFT (3)
#define UART_ULCON_WORD_LEN(c) ((c)<<UART_ULCON_WORD_LEN_SHIFT)
#define UART_ULCON_N_STOP_BIT(c) ((c)<<UART_ULCON_N_STOP_BIT_SHIFT)
#define UART_ULCON_PARITY_MODE(c) ((c)<<UART_ULCON_PARITY_MODE_SHIFT)
#define UART_ULCON_WORD_LEN_MASK (0x03<<UART_ULCON_WORD_LEN_SHIFT)
#define UART_ULCON_N_STOP_BIT_MASK (0x01<<UART_ULCON_N_STOP_BIT_SHIFT)
#define UART_ULCON_PARITY_MODE_MASK (0x07<<UART_ULCON_PARITY_MODE_SHIFT)
#define UART_WL_5BIT 0x00
#define UART_WL_6BIT 0x01
#define UART_WL_7BIT 0x02
#define UART_WL_8BIT 0x03
#define UART_NO_PARITY 0x00
#define UART_ODD_PARITY 0x04
#define UART_EVEN_PARITY 0x05
#define UART_FORCE_1_PARITY 0x06
#define UART_FORCE_0_PARITY 0x07
#define UART_1_STOP_BIT 0x00
#define UART_2_STOP_BIT 0x01
/* UART UCON */
#define UART_UCON_RCV_MODE_SHIFT (0)
#define UART_UCON_TX_MODE_SHIFT (2)
#define UART_UCON_SND_BRK_SIG_SHIFT (4)
#define UART_UCON_LOOP_BACK_SHIFT (5)
#define UART_UCON_RX_ERR_INT_EN_SHIFT (6)
#define UART_UCON_RX_TIMEOUT_EN_SHIFT (7)
#define UART_UCON_RX_INT_TYPE_SHIFT (8)
#define UART_UCON_TX_INT_TYPE_SHIFT (9)
#define UART_UCON_RX_TIMEOUT_DMA_SPD_EN_SHIFT (10)
#define UART_UCON_RX_TIMEOUT_EMPTY_FIFO_SHIFT (11)
#define UART_UCON_RX_TIMOUT_INT_INTER_SHIFT (12)
#define UART_UCON_RX_DMA_BURST_SIZE_SHIFT (16)
#define UART_UCON_TX_DMA_BURST_SIZE_SHIFT (20)
#define UART_UCON_RCV_MODE_MASK (0x03<<UART_UCON_RCV_MODE_SHIFT)
#define UART_UCON_TX_MODE_MASK (0x03<<UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_SND_BRK_SIG_MASK (0x01<<UART_UCON_SND_BRK_SIG_SHIFT)
#define UART_UCON_LOOP_BACK_MASK (0x01<<UART_UCON_LOOP_BACK_SHIFT)
#define UART_UCON_RX_ERR_INT_EN_MASK (0x01<<UART_UCON_RX_ERR_INT_EN_SHIFT)
#define UART_UCON_RX_TIMEOUT_EN_MASK (0x01<<UART_UCON_RX_TIMEOUT_EN_SHIFT)
#define UART_UCON_RX_INT_TYPE_MASK (0x01<<UART_UCON_RX_INT_TYPE_SHIFT)
#define UART_UCON_TX_INT_TYPE_MASK (0x01<<UART_UCON_TX_INT_TYPE_SHIFT)
#define UART_UCON_RX_TIMEOUT_DMA_SPD_EN_MASK (0x01<<UART_UCON_RX_TIMEOUT_DMA_SPD_EN_SHIFT)
#define UART_UCON_RX_TIMEOUT_EMPTY_FIFO_MASK (0x01<<UART_UCON_RX_TIMEOUT_EMPTY_FIFO_SHIFT)
#define UART_UCON_RX_TIMOUT_INT_INTER_MASK (0x0F<<UART_UCON_RX_TIMOUT_INT_INTER_SHIFT)
#define UART_UCON_RX_DMA_BURST_SIZE_MASK (0x03<<UART_UCON_RX_DMA_BURST_SIZE_SHIFT)
#define UART_UCON_TX_DMA_BURST_SIZE_MASK (0x07<<UART_UCON_TX_DMA_BURST_SIZE_SHIFT)
#define UART_UCON_RCV_MODE(c) ((c)<<UART_UCON_RCV_MODE_SHIFT)
#define UART_UCON_TX_MODE(c) ((c)<<UART_UCON_TX_MODE_SHIFT)
#define UART_UCON_SND_BRK_SIG(c) ((c)<<UART_UCON_SND_BRK_SIG_SHIFT)
#define UART_UCON_LOOP_BACK(c) ((c)<<UART_UCON_LOOP_BACK_SHIFT)
#define UART_UCON_RX_ERR_INT_EN(c) ((c)<<UART_UCON_RX_ERR_INT_EN_SHIFT)
#define UART_UCON_RX_TIMEOUT_EN(c) ((c)<<UART_UCON_RX_TIMEOUT_EN_SHIFT)
#define UART_UCON_RX_INT_TYPE(c) ((c)<<UART_UCON_RX_INT_TYPE_SHIFT)
#define UART_UCON_TX_INT_TYPE(c) ((c)<<UART_UCON_TX_INT_TYPE_SHIFT)
#define UART_UCON_RX_TIMEOUT_DMA_SPD_EN(c) ((c)<<UART_UCON_RX_TIMEOUT_DMA_SPD_EN_SHIFT)
#define UART_UCON_RX_TIMEOUT_EMPTY_FIFO(c) ((c)<<UART_UCON_RX_TIMEOUT_EMPTY_FIFO_SHIFT)
#define UART_UCON_RX_TIMOUT_INT_INTER(c) ((c)<<UART_UCON_RX_TIMOUT_INT_INTER_SHIFT)
#define UART_UCON_RX_DMA_BURST_SIZE(c) ((c)<<UART_UCON_RX_DMA_BURST_SIZE_SHIFT)
#define UART_UCON_TX_DMA_BURST_SIZE(c) ((c)<<UART_UCON_TX_DMA_BURST_SIZE_SHIFT)
/* UART UFCON */
#define UART_UFCON_FIFO_EN_SHIFT (0)
#define UART_UFCON_RX_FIFO_RESET_SHIFT (1)
#define UART_UFCON_TX_FIFO_RESET_SHIFT (2)
#define UART_UFCON_RX_FIFO_TRIG_LVL_SHIFT (4)
#define UART_UFCON_TX_FIFO_TRIG_LVL_SHIFT (8)
#define UART_UFCON_FIFO_EN_MASK (0x01<<UART_UFCON_FIFO_EN_SHIFT)
#define UART_UFCON_RX_FIFO_RESET_MASK (0x01<<UART_UFCON_RX_FIFO_RESET_SHIFT)
#define UART_UFCON_TX_FIFO_RESET_MASK (0x01<<UART_UFCON_TX_FIFO_RESET_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_LVL_MASK (0x07<<UART_UFCON_RX_FIFO_TRIG_LVL_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_LVL_MASK (0x07<<UART_UFCON_TX_FIFO_TRIG_LVL_SHIFT)
#define UART_UFCON_FIFO_EN(c) ((c)<<UART_UFCON_FIFO_EN_SHIFT)
#define UART_UFCON_RX_FIFO_RESET(c) ((c)<<UART_UFCON_RX_FIFO_RESET_SHIFT)
#define UART_UFCON_TX_FIFO_RESET(c) ((c)<<UART_UFCON_TX_FIFO_RESET_SHIFT)
#define UART_UFCON_RX_FIFO_TRIG_LVL(c) ((c)<<UART_UFCON_RX_FIFO_TRIG_LVL_SHIFT)
#define UART_UFCON_TX_FIFO_TRIG_LVL(c) ((c)<<UART_UFCON_TX_FIFO_TRIG_LVL_SHIFT)
/* UART UMCON */
#define UART_UMCON_RTS_SHIFT (0)
#define UART_UMCON_AFC_SHIFT (4)
#define UART_UMCON_RTS_TRIGGER_LEVEL_SHIFT (5)
#define UART_UMCON_RTS_MASK (0x01<<UART_UMCON_RTS_SHIFT)
#define UART_UMCON_AFC_MASK (0x01<<UART_UMCON_AFC_SHIFT)
#define UART_UMCON_RTS_TRIGGER_LEVEL_MASK (0x07<<UART_UMCON_RTS_TRIGGER_LEVEL_SHIFT)
#define UART_UMCON_RTS(c) ((c)<<UART_UMCON_RTS_MASK)
#define UART_UMCON_AFC(c) ((c)<<UART_UMCON_AFC_MASK)
#define UART_UMCON_RTS_TRIGGER_LEVEL(c) ((c)<<UART_UMCON_RTS_TRIGGER_LEVEL_MASK)
/* UART UTRSTAT */
#define UART_UTRSTAT_RCV_BUF_DATA_READY_SHIFT (0)
#define UART_UTRSTAT_TX_BUF_EMPTY_SHIFT (1)
#define UART_UTRSTAT_TX_EMPTY_SHIFT (2)
#define UART_UTRSTAT_RX_TIMEOUT_CLR_SHIFT (3)
#define UART_UTRSTAT_RX_DMA_FSM_STA_SHIFT (8)
#define UART_UTRSTAT_TX_DMA_FSM_STA_SHIFT (12)
#define UART_UTRSTAT_RX_FIFO_CNT_SHIFT (16)
#define UART_UTRSTAT_RCV_BUF_DATA_READY_MASK (0x01<<UART_UTRSTAT_RCV_BUF_DATA_READY_SHIFT)
#define UART_UTRSTAT_TX_BUF_EMPTY_MASK (0x01<<UART_UTRSTAT_TX_BUF_EMPTY_SHIFT)
#define UART_UTRSTAT_TX_EMPTY_MASK (0x01<<UART_UTRSTAT_TX_EMPTY_SHIFT)
#define UART_UTRSTAT_RX_TIMEOUT_CLR_MASK (0x01<<UART_UTRSTAT_RX_TIMEOUT_CLR_SHIFT)
#define UART_UTRSTAT_RX_DMA_FSM_STA_MASK (0x0F<<UART_UTRSTAT_RX_DMA_FSM_STA_SHIFT)
#define UART_UTRSTAT_TX_DMA_FSM_STA_MASK (0x0F<<UART_UTRSTAT_TX_DMA_FSM_STA_SHIFT)
#define UART_UTRSTAT_RX_FIFO_CNT_MASK (0xFF<<UART_UTRSTAT_RX_FIFO_CNT_SHIFT)
#define UART_UTRSTAT_RCV_BUF_DATA_READY(c) ((c)<<UART_UTRSTAT_RCV_BUF_DATA_READY_SHIFT)
#define UART_UTRSTAT_TX_BUF_EMPTY(c) ((c)<<UART_UTRSTAT_TX_BUF_EMPTY_SHIFT)
#define UART_UTRSTAT_TX_EMPTY(c) ((c)<<UART_UTRSTAT_TX_EMPTY_SHIFT)
#define UART_UTRSTAT_RX_TIMEOUT_CLR(c) ((c)<<UART_UTRSTAT_RX_TIMEOUT_CLR_SHIFT)
#define UART_UTRSTAT_RX_DMA_FSM_STA(c) ((c)<<UART_UTRSTAT_RX_DMA_FSM_STA_SHIFT)
#define UART_UTRSTAT_TX_DMA_FSM_STA(c) ((c)<<UART_UTRSTAT_TX_DMA_FSM_STA_SHIFT)
#define UART_UTRSTAT_RX_FIFO_CNT(c) ((c)<<UART_UTRSTAT_RX_FIFO_CNT_SHIFT)
/* UART UERSTAT */
#define UART_UERSTAT_OVERRUN_ERR_SHIFT (0)
#define UART_UERSTAT_PRITY_ERR_SHIFT (1)
#define UART_UERSTAT_FRAME_ERR_SHIFT (2)
#define UART_UERSTAT_BREAK_DETECT_SHIFT (3)
#define UART_UERSTAT_OVERRUN_ERR_MASK (0x01<<UART_UERSTAT_OVERRUN_ERR_SHIFT)
#define UART_UERSTAT_PRITY_ERR_MASK (0x01<<UART_UERSTAT_PRITY_ERR_SHIFT)
#define UART_UERSTAT_FRAME_ERR_MASK (0x01<<UART_UERSTAT_FRAME_ERR_SHIFT)
#define UART_UERSTAT_BREAK_DETECT_MASK (0x01<<UART_UERSTAT_BREAK_DETECT_SHIFT)
#define UART_UERSTAT_OVERRUN_ERR(c) ((c)<<UART_UERSTAT_OVERRUN_ERR_SHIFT)
#define UART_UERSTAT_PRITY_ERR(c) ((c)<<UART_UERSTAT_PRITY_ERR_SHIFT)
#define UART_UERSTAT_FRAME_ERR(c) ((c)<<UART_UERSTAT_FRAME_ERR_SHIFT)
#define UART_UERSTAT_BREAK_DETECT(c) ((c)<<UART_UERSTAT_BREAK_DETECT_SHIFT)
/* UART UFSTAT */
#define UART_UFSTAT_RX_FIFO_CNT_SHIFT (0)
#define UART_UFSTAT_RX_FIFO_FULL_SHIFT (8)
#define UART_UFSTAT_RX_FIFO_ERR_SHIFT (9)
#define UART_UFSTAT_TX_FIFO_CNT_SHIFT (16)
#define UART_UFSTAT_TX_FIFO_FULL_SHIFT (24)
#define UART_UFSTAT_RX_FIFO_CNT_MASK (0xFF<<UART_UFSTAT_RX_FIFO_CNT_SHIFT)
#define UART_UFSTAT_RX_FIFO_FULL_MASK (0x01<<UART_UFSTAT_RX_FIFO_FULL_SHIFT)
#define UART_UFSTAT_RX_FIFO_ERR_MASK (0x01<<UART_UFSTAT_RX_FIFO_ERR_SHIFT)
#define UART_UFSTAT_TX_FIFO_CNT_MASK (0xFF<<UART_UFSTAT_TX_FIFO_CNT_SHIFT)
#define UART_UFSTAT_TX_FIFO_FULL_MASK (0x01<<UART_UFSTAT_TX_FIFO_FULL_SHIFT)
#define UART_UFSTAT_RX_FIFO_CNT(c) ((c)<<UART_UFSTAT_RX_FIFO_CNT_SHIFT)
#define UART_UFSTAT_RX_FIFO_FULL(c) ((c)<<UART_UFSTAT_RX_FIFO_FULL_SHIFT)
#define UART_UFSTAT_RX_FIFO_ERR(c) ((c)<<UART_UFSTAT_RX_FIFO_ERR_SHIFT)
#define UART_UFSTAT_TX_FIFO_CNT(c) ((c)<<UART_UFSTAT_TX_FIFO_CNT_SHIFT)
#define UART_UFSTAT_TX_FIFO_FULL(c) ((c)<<UART_UFSTAT_TX_FIFO_FULL_SHIFT)
/* UART_UINTP */
#define UART_UINTP_RXD_SHIFT (0)
#define UART_UINTP_ERR_SHIFT (1)
#define UART_UINTP_TXD_SHIFT (2)
#define UART_UINTP_RXD_MASK (0x01<<UART_UINTP_RXD_SHIFT)
#define UART_UINTP_ERR_MASK (0x01<<UART_UINTP_ERR_SHIFT)
#define UART_UINTP_TXD_MASK (0x01<<UART_UINTP_TXD_SHIFT)
#define UART_UINTP_RXD(c) ((c)<<UART_UINTP_RXD_SHIFT)
#define UART_UINTP_ERR(c) ((c)<<UART_UINTP_ERR_SHIFT)
#define UART_UINTP_TXD(c) ((c)<<UART_UINTP_TXD_SHIFT)
/* UART_UINTS */
#define UART_UINTS_RXD_SHIFT (0)
#define UART_UINTS_ERR_SHIFT (1)
#define UART_UINTS_TXD_SHIFT (2)
#define UART_UINTS_RXD_MASK (0x01<<UART_UINTS_RXD_SHIFT)
#define UART_UINTS_ERR_MASK (0x01<<UART_UINTS_ERR_SHIFT)
#define UART_UINTS_TXD_MASK (0x01<<UART_UINTS_TXD_SHIFT)
#define UART_UINTS_RXD(c) ((c)<<UART_UINTS_RXD_SHIFT)
#define UART_UINTS_ERR(c) ((c)<<UART_UINTS_ERR_SHIFT)
#define UART_UINTS_TXD(c) ((c)<<UART_UINTS_TXD_SHIFT)
/* UART_UINTM */
#define UART_UINTM_RXD_SHIFT (0)
#define UART_UINTM_ERR_SHIFT (1)
#define UART_UINTM_TXD_SHIFT (2)
#define UART_UINTM_RXD_MASK (0x01 << UART_UINTM_RXD_SHIFT)
#define UART_UINTM_ERR_MASK (0x01 << UART_UINTM_ERR_SHIFT)
#define UART_UINTM_TXD_MASK (0x01 << UART_UINTM_TXD_SHIFT)
#define UART_UINTM_RXD(c) ((c) << UART_UINTM_RXD_SHIFT)
#define UART_UINTM_ERR(c) ((c) << UART_UINTM_ERR_SHIFT)
#define UART_UINTM_TXD(c) ((c) << UART_UINTM_TXD_SHIFT)
#endif /*__S1SBP6A_UART_H */

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/s1sbp6a_wdog.c Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include <stdbool.h>
#include "s1sbp6a.h"
#include "s1sbp6a_type.h"
#include "s1sbp6a_wdog.h"
#include "s1sbp6a_cmu.h"
#define WATCHDOG_RESET_ENABLED 1
static void bp6a_watchdog_lock(bool enable)
{
putreg32(&(BP_WATCHDOG->LOCK), enable ? 0 : 0x1ACCE551);
}
void bp6a_watchdog_enable(bool enable)
{
bp6a_watchdog_lock(false);
modifyreg32(&(BP_WATCHDOG->CTRL), WDOGCTRL_INT_ENABLE_MASK,
WDOGCTRL_INT_ENABLE(enable));
bp6a_watchdog_lock(true);
}
void bp6a_wdog_reset_enable(bool enable)
{
bp6a_watchdog_lock(false);
modifyreg32(&(BP_WATCHDOG->CTRL), WDOGCTRL_RESET_ENABLE_MASK,
WDOGCTRL_RESET_ENABLE(enable));
bp6a_watchdog_lock(true);
}
void bp6a_wdog_set_reload_time(uint32_t ms)
{
uint32_t clk = bp6a_cmu_get_clock_freq(CMU_WATCHDOG_APBCLK);
uint32_t load_val = (uint32_t)((ms * clk) / 1000 + 0.5);
bp6a_watchdog_lock(false);
putreg32(&(BP_WATCHDOG->LOAD), load_val);
bp6a_watchdog_lock(true);
}
void bp6a_nmi_handler(void)
{
if (getreg32(&(BP_WATCHDOG->CTRL)) & WDOGCTRL_INT_ENABLE_MASK) {
if (getreg32(&(BP_WATCHDOG->MIS))) {
putreg32(&BP_WATCHDOG->INTCLR, 0x1);
}
}
}
void bp6a_wdog_init(uint32_t timeout)
{
bp6a_watchdog_enable(false);
NVIC_SetVector(NonMaskableInt_IRQn, (uint32_t) bp6a_nmi_handler);
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
SCB_InvalidateICache();
#endif
#if WATCHDOG_RESET_ENABLED
bp6a_wdog_reset_enable(true);
#endif
bp6a_wdog_set_reload_time(timeout);
bp6a_watchdog_enable(true);
}

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/s1sbp6a_wdog.h Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_WATCHDOG_H
#define __S1SBP6A_WATCHDOG_H
/* Control Register 0 */
#define WDOGCTRL_RESET_ENABLE_SHIFT (0)
#define WDOGCTRL_INT_ENABLE_SHIFT (1)
#define WDOGCTRL_RESET_ENABLE_MASK (0x01 << WDOGCTRL_RESET_ENABLE_SHIFT)
#define WDOGCTRL_INT_ENABLE_MASK (0x01 << WDOGCTRL_INT_ENABLE_SHIFT)
#define WDOGCTRL_RESET_ENABLE(c) ((c) << WDOGCTRL_RESET_ENABLE_SHIFT)
#define WDOGCTRL_INT_ENABLE(c) ((c) << WDOGCTRL_INT_ENABLE_SHIFT)
void bp6a_wdog_init(uint32_t timeout);
void bp6a_watchdog_enable(bool enable);
void bp6a_wdog_reset_enable(bool enable);
void bp6a_wdog_set_reload_time(uint32_t ms);
#endif /* __S1SBP6A_WATCHDOG_H */

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/s1sp6a_dual_timer.h Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __S1SBP6A_TIMER_H
#define __S1SBP6A_TIMER_H
/****************************************************************************
* Include
****************************************************************************/
#include "s1sbp6a.h"
#define TIMER0_BASE (BP_TIMER0_BASE)
#define TIMER_BASE(c) (TIMER0_BASE + (c << 12))
#define TIMER_CTRL_OFFSET 0x0000
#define TIMER_VALUE_OFFSET 0x0004
#define TIMER_RELOAD_OFFSET 0x0008
#define TIMER_INTCLR_OFFSET 0x000C
#define TIMER_INT_OFFSET 0x000C
#define TIMER_INT_OFFSET 0x000C
#define TIMER_INT_OFFSET 0x000C
#define TIMER_INT_OFFSET 0x000C
#define DUALTIMER_LOAD_SHIFT (0)
#define DUALTIMER_VALUE_SHIFT (0)
#define DUALTIMER_CTRL_EN_SHIFT (7)
#define DUALTIMER_CTRL_MODE_SHIFT (6)
#define DUALTIMER_CTRL_INTEN_SHIFT (5)
#define DUALTIMER_CTRL_PRESCALE_SHIFT (2)
#define DUALTIMER_CTRL_SIZE_SHIFT (1)
#define DUALTIMER_CTRL_ONESHOOT_SHIFT (0)
#define DUALTIMER_LOAD_MASK (0xFFFFFFFFul << DUALTIMER_LOAD_SHIFT)
#define DUALTIMER_VALUE_MASK (0xFFFFFFFFul << DUALTIMER_VALUE_SHIFT)
#define DUALTIMER_CTRL_EN_MASK (0x1ul << DUALTIMER_CTRL_EN_SHIFT)
#define DUALTIMER_CTRL_MODE_MASK (0x1ul << DUALTIMER_CTRL_MODE_SHIFT)
#define DUALTIMER_CTRL_INTEN_MASK (0x1ul << DUALTIMER_CTRL_INTEN_SHIFT)
#define DUALTIMER_CTRL_PRESCALE_MASK (0x3ul << DUALTIMER_CTRL_PRESCALE_SHIFT)
#define DUALTIMER_CTRL_SIZE_MASK (0x1ul << DUALTIMER_CTRL_SIZE_SHIFT)
#define DUALTIMER_CTRL_ONESHOOT_MASK (0x1ul << DUALTIMER_CTRL_ONESHOOT_SHIFT)
#define DUALTIMER_LOAD(c) ((c) << DUALTIMER_LOAD_SHIFT)
#define DUALTIMER_VALUE(c) ((c) << DUALTIMER_VALUE_SHIFT)
#define DUALTIMER_CTRL_EN(c) ((c) << DUALTIMER_CTRL_EN_SHIFT)
#define DUALTIMER_CTRL_MODE(c) ((c) << DUALTIMER_CTRL_MODE_SHIFT)
#define DUALTIMER_CTRL_INTEN(c) ((c) << DUALTIMER_CTRL_INTEN_SHIFT)
#define DUALTIMER_CTRL_PRESCALE(c) ((c) << DUALTIMER_CTRL_PRESCALE_SHIFT)
#define DUALTIMER_CTRL_SIZE(c) ((c) << DUALTIMER_CTRL_SIZE_SHIFT)
#define DUALTIMER_CTRL_ONESHOOT(c) ((c) << DUALTIMER_CTRL_ONESHOOT_SHIFT)
#define DUALTIMER_INTCLR_SHIFT (0)
#define DUALTIMER_INTCLR_MASK (0x01 << DUALTIMER_INTCLR_SHIFT)
#endif //__S1SBP6A_TIMER_H

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/device/system_s1sbp6a.c Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include "cmsis.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define PERI_CLOCK (4096000UL)
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = HSOSC_CLK_FREQ ;//LSOSC_CLK_FREQ; /* System Clock Frequency (Core Clock)*/
uint32_t PeriPheralClock = PERI_CLOCK;
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
static void peripheral_init(void)
{
/*AFE Voltage Config */
putreg32(&BP_AFE_TOP->REF_CTRL, 0x7A68201F);
putreg32(&BP_AFE_TOP->AFE_CLK_CTRL, 0x0);
}
void SystemCoreClockUpdate(void) /* Get Core Clock Frequency */
{
SystemCoreClock = bp6a_cmu_get_clock_freq(CMU_FCLK_AHBCLK);
}
static void pin_disable(void)
{
int i;
for (i = 2; i < 14; i++) {
putreg32(&BP_SYSCON->IOCFG[i], 0);
}
}
void SystemInit(void)
{
/* Set floating point coprosessor access mode. */
#if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
/* USAGE/BUS/MEM FAULT ENABLE chenzhao */
SCB->SHCSR |= (1 << 18) | (1 << 17) | (1 << 16);
bp6a_pum_init();
bp6a_cmu_init(CMU_SRC_CLK_HSOSC, CMU_SRC_CLK_LSOSC);
bp6a_watchdog_enable(false);
SystemCoreClock = bp6a_cmu_get_clock_freq(CMU_FCLK_AHBCLK);
peripheral_init();
pin_disable();
}

56
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef __SYSTEM_S1SBP6A_H
#define __SYSTEM_S1SBP6A_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit(void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_S1SBP6A_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#if DEVICE_FLASH
#include "flash_api.h"
#include "mbed_critical.h"
#include "cmsis.h"
#define BP6A_FLASH_WRITE_SIZE 4
#define BP6A_FLASH_PAGE_SIZE 2048
#define BP6A_FLASH_MEM_BASE 0
#define BP6A_FLASH_FULL_SIZE (2*1024*1024)
int32_t flash_init(flash_t *obj)
{
modifyreg32(BP_FLASH_CTRL_BASE + UFC_DCYCRDCON_OFFSET, 0xFFFF, 0x9F4); // flash wait setting
return 0;
}
int32_t flash_free(flash_t *obj)
{
return 0;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
modifyreg32(BP_FLASH_CTRL_BASE + UFC_FRWCON0_OFFSET,
UFC_FRWCON_WRMD_MASK |
UFC_FRWCON_ERSMD_MASK,
UFC_FRWCON_WRMD(ERASE_MODE) |
UFC_FRWCON_ERSMD(SECTOR_ERASE_MODE));
putreg32(address, 0xFFFFFFFF); //load dummy
modifyreg32(BP_FLASH_CTRL_BASE + UFC_FRWCON0_OFFSET,
UFC_FRWCON_HVEN_MASK,
UFC_FRWCON_HVEN(1));
while (getreg32(BP_FLASH_CTRL_BASE + UFC_FRWCON0_OFFSET) & (0x01 << UFC_FRWCON_HVEN_SHIFT));
return 0;
}
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
{
uint32_t i;
for (i = 0; i < size; i += 4) {
modifyreg32(BP_FLASH_CTRL_BASE + UFC_FRWCON0_OFFSET,
UFC_FRWCON_WRMD_MASK,
UFC_FRWCON_WRMD(WRITE_MODE));
*((uint32_t *)(address + i)) = (uint32_t)(data[i] | data[i + 1] << 8 |
data[i + 3] << 24 | data[i + 2] << 16);
modifyreg32(BP_FLASH_CTRL_BASE + UFC_FRWCON0_OFFSET,
UFC_FRWCON_HVEN_MASK,
UFC_FRWCON_HVEN(1));
while (getreg32(BP_FLASH_CTRL_BASE + UFC_FRWCON0_OFFSET) & (0x01 << UFC_FRWCON_HVEN_SHIFT));
}
return 0;
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
/* 1 sector = 1 page */
if (address >= (BP6A_FLASH_MEM_BASE + BP6A_FLASH_FULL_SIZE)) {
return MBED_FLASH_INVALID_SIZE;
} else {
return BP6A_FLASH_PAGE_SIZE;
}
}
uint32_t flash_get_page_size(const flash_t *obj)
{
return BP6A_FLASH_WRITE_SIZE;
}
uint32_t flash_get_start_address(const flash_t *obj)
{
return BP6A_FLASH_MEM_BASE;
}
uint32_t flash_get_size(const flash_t *obj)
{
return BP6A_FLASH_FULL_SIZE;
}
uint8_t flash_get_erase_value(const flash_t *obj)
{
UNUSED(obj);
return 0xFF;
}
#endif

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include "mbed_assert.h"
#include "gpio_api.h"
#include "pinmap.h"
#include "cmsis.h"
void gpio_init(gpio_t *obj, PinName pin)
{
obj->pin = pin;
if (pin == (PinName)NC) {
return;
}
uint32_t port = BP6A_PORT_IDX(obj->pin);
uint32_t mask = 1 << pin;
uint8_t pin_n = BP6A_PIN_IDX(pin);
bp6a_set_pin_config(port, pin_n, (PIN_INPUT | PIN_OUTPUT));
BP_GPIO_TypeDef *gpio_base = (BP_GPIO_TypeDef *)GPIO_PORT_BASE(port);
putreg32(&(gpio_base->ALTFUNCCLR), mask);
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
{
bp6a_gpio_set_dir(BP6A_PORT_IDX(obj->pin), BP6A_PIN_IDX(obj->pin), (PIN_INPUT == direction));
}
void gpio_write(gpio_t *obj, int value)
{
if (obj->pin == (PinName)NC) {
return;
}
uint32_t port = BP6A_PORT_IDX(obj->pin);
uint32_t mask = 1 << BP6A_PIN_IDX(obj->pin);
BP_GPIO_TypeDef *gpio_base = (BP_GPIO_TypeDef *)GPIO_PORT_BASE(port);
modifyreg32(&(gpio_base->DATAOUT), mask, (value > 0) ? mask : 0);
}
int gpio_read(gpio_t *obj)
{
if (obj->pin == (PinName)NC) {
return 0;
}
uint32_t port = BP6A_PORT_IDX(obj->pin);
uint32_t pin_n = BP6A_PIN_IDX(obj->pin);
BP_GPIO_TypeDef *gpio_base = (BP_GPIO_TypeDef *)GPIO_PORT_BASE(port);
return (getreg32(&(gpio_base->DATA)) >> pin_n) & 0x01;
}
uint32_t gpio_set(PinName pin)
{
uint32_t port = BP6A_PORT_IDX(pin);
uint32_t pin_n = BP6A_PIN_IDX(pin);
bp6a_gpio_set_dir(port, pin_n, true);
return (1u << (uint32_t) pin);
}
int gpio_is_connected(const gpio_t *obj)
{
if (obj->pin == (PinName) NC) {
return 0;
}
uint32_t port = BP6A_PORT_IDX(obj->pin);
uint32_t pin_n = BP6A_PIN_IDX(obj->pin);
BP_GPIO_TypeDef *gpio_base = (BP_GPIO_TypeDef *)GPIO_PORT_BASE(port);
return !(getreg32(&(gpio_base->ALTFUNCSET)) >> pin_n);
}

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stddef.h>
#include "cmsis.h"
#include "gpio_irq_api.h"
#include "mbed_error.h"
/****************************************************************************
* Pre-processor definitions
****************************************************************************/
#define CHANNEL_NUM 48
#define MAX_PIN_PER_PORT 16
static gpio_irq_handler irq_handler;
static uint32_t channel_ids[CHANNEL_NUM];
static gpio_irq_event pins_event[CHANNEL_NUM];
static inline void handle_gpio_irq(uint32_t port)
{
int i;
uint32_t pin_name = port << 4;
BP_GPIO_TypeDef *gpio_base = (BP_GPIO_TypeDef *)GPIO_PORT_BASE(port);
for (i = 0; i < MAX_PIN_PER_PORT; i++) {
if (gpio_base->INTSTAT & (1u << i)) {
pin_name += i;
NVIC_ClearPendingIRQ(PORT0_0_IRQn + port * 16 + i);
gpio_base->INTCLR = 1u << i;
irq_handler(channel_ids[pin_name], pins_event[pin_name]);
break;
}
}
}
void gpio0_irq(void)
{
handle_gpio_irq(0);
NVIC_ClearPendingIRQ(PORT0_ALL_IRQn);
}
void gpio1_irq(void)
{
handle_gpio_irq(1);
NVIC_ClearPendingIRQ(PORT1_ALL_IRQn);
}
void gpio2_irq(void)
{
handle_gpio_irq(2);
NVIC_ClearPendingIRQ(PORT2_ALL_IRQn);
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin,
gpio_irq_handler handler, uint32_t id)
{
if (pin == (PinName)NC) {
return -1;
}
obj->pin = pin;
irq_handler = handler;
channel_ids[pin] = id;
bp6a_gpio_set_dir(BP6A_PORT_IDX(obj->pin), BP6A_PIN_IDX(obj->pin), true);
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
channel_ids[obj->pin] = 0;
gpio_irq_disable(obj);
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
pins_event[obj->pin] = event;
if (event == IRQ_NONE) {
return;
}
if (event == IRQ_RISE) {
bp6a_gpio_set_int_type(BP6A_PORT_IDX(obj->pin), BP6A_PIN_IDX(obj->pin),
true, true);
} else {
bp6a_gpio_set_int_type(BP6A_PORT_IDX(obj->pin), BP6A_PIN_IDX(obj->pin),
false, true);
}
if (enable) {
gpio_irq_enable(obj);
} else {
gpio_irq_disable(obj);
}
}
void gpio_irq_enable(gpio_irq_t *obj)
{
uint32_t port = BP6A_PORT_IDX(obj->pin);
bp6a_gpio_set_int(port, BP6A_PIN_IDX(obj->pin), true);
void (*port_irq)(void) = NULL;
switch (port) {
case 0:
port_irq = &gpio0_irq;
break;
case 1:
port_irq = &gpio1_irq;
break;
case 2:
port_irq = &gpio2_irq;
break;
}
NVIC_SetVector((IRQn_Type)(PORT0_0_IRQn + port * 16 + BP6A_PIN_IDX(obj->pin)), (uint32_t)port_irq);
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
SCB_InvalidateICache();
#endif
NVIC_EnableIRQ((IRQn_Type)(PORT0_0_IRQn + port * 16 + BP6A_PIN_IDX(obj->pin)));
}
void gpio_irq_disable(gpio_irq_t *obj)
{
uint32_t port_n = BP6A_PORT_IDX(obj->pin);
uint32_t pin_n = BP6A_PIN_IDX(obj->pin);
NVIC_ClearPendingIRQ((IRQn_Type)(PORT0_ALL_IRQn + port_n));
bp6a_gpio_clear_pend(port_n, pin_n);
NVIC_DisableIRQ((IRQn_Type)(PORT0_ALL_IRQn + port_n));
bp6a_gpio_set_int(port_n, pin_n, false);
}

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
} gpio_t;
#ifdef __cplusplus
}
#endif
#endif

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#if DEVICE_I2C
#include "i2c_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "mbed_wait_api.h"
#include "PeripheralPins.h"
#if DEVICE_I2C_ASYNCH
#define I2C_S(obj) (struct i2c_s *) (&((obj)->i2c))
#else
#define I2C_S(obj) (struct i2c_s *) (obj)
#endif
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
struct i2c_s *obj_s = I2C_S(obj);
/* Determine the I2C to use */
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
obj_s->index = pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT((int)obj_s->i2c != NC);
pinmap_pinout(sda, PinMap_I2C_SDA);
pinmap_pinout(scl, PinMap_I2C_SCL);
if (obj_s->xfer_freq == 0) {
obj_s->xfer_freq = DEFAULT_I2CXFER_CLOCK;
}
obj_s->addrlen = 7;
bp6a_i2c_master_init(obj_s->index, obj_s->xfer_freq, obj_s->addrlen);
}
void i2c_frequency(i2c_t *obj, int hz)
{
struct i2c_s *obj_s = I2C_S(obj);
obj_s->xfer_freq = hz;
bp6a_i2c_master_init(obj_s->index, hz, obj_s->addrlen);
}
int i2c_start(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
return bp6a_i2c_start(obj_s->index);
}
int i2c_stop(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
return bp6a_i2c_stop(obj_s->index);
}
void i2c_reset(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
bp6a_i2c_reset(obj_s->index);
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
struct i2c_s *obj_s = I2C_S(obj);
bp6a_i2c_set_slave_address(obj_s->index, address, false);
return bp6a_i2c_read(obj_s->index, (uint8_t *)data, length, 1, stop);
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
struct i2c_s *obj_s = I2C_S(obj);
bp6a_i2c_set_slave_address(obj_s->index, address, false);
return bp6a_i2c_write(obj_s->index, (const uint8_t *)(data), length, 1, stop);
}
int i2c_byte_read(i2c_t *obj, int last)
{
struct i2c_s *obj_s = I2C_S(obj);
return bp6a_i2c_read_byte(obj_s->index, (bool)last);
}
int i2c_byte_write(i2c_t *obj, int data)
{
struct i2c_s *obj_s = I2C_S(obj);
return bp6a_i2c_write_byte(obj_s->index, data);
}
const PinMap *i2c_master_sda_pinmap(void)
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_master_scl_pinmap(void)
{
return PinMap_I2C_SCL;
}
const PinMap *i2c_slave_sda_pinmap(void)
{
return PinMap_I2C_SDA;
}
const PinMap *i2c_slave_scl_pinmap(void)
{
return PinMap_I2C_SCL;
}
#if DEVICE_I2CSLAVE
void i2c_slave_mode(i2c_t *obj, int enable_slave)
{
struct i2c_s *obj_s = I2C_S(obj);
if (enable_slave) {
bp6a_i2c_slave_init(obj_s->index);
}
}
int i2c_slave_receive(i2c_t *obj)
{
struct i2c_s *obj_s = I2C_S(obj);
return bp6a_i2c_get_slave_status(obj_s->index);
}
int i2c_slave_read(i2c_t *obj, char *data, int length)
{
struct i2c_s *obj_s = I2C_S(obj);
return bp6a_i2c_read(obj_s->index, (uint8_t *) data, length, 1, 1);
}
int i2c_slave_write(i2c_t *obj, const char *data, int length)
{
struct i2c_s *obj_s = I2C_S(obj);
return bp6a_i2c_write(obj_s->index, (const uint8_t *) data, length, 1, 1);
}
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
{
struct i2c_s *obj_s = I2C_S(obj);
UNUSED(idx);
UNUSED(mask);
bp6a_i2c_set_slave_address(obj_s->index, address, true);
}
#endif // DEVICE_I2CSLAVE
#endif // DEVICE_I2C

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_MBED_RTX_H
#define MBED_MBED_RTX_H
#include "memory_zones.h"
#if defined(TARGET_S1SBP6A)
#ifndef INITIAL_SP
#define INITIAL_SP (MBED_RAM_START + MBED_RAM_SIZE)
#endif
#endif /* defined(TARGET_...) */
#endif /* MBED_MBED_RTX_H */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#include "gpio_object.h"
#ifdef __cplusplus
extern "C" {
#endif
#if DEVICE_SERIAL
struct serial_s {
UARTName uart;
int index; // Used by irq
uint32_t baudrate;
uint32_t databits;
uint32_t stopbits;
uint32_t parity;
PinName pin_tx;
PinName pin_rx;
#if DEVICE_SERIAL_ASYNCH
uint32_t events;
#endif
#if DEVICE_SERIAL_FC
uint32_t hw_flow_ctl;
PinName pin_rts;
PinName pin_cts;
#endif
};
#endif
struct gpio_irq_s {
PinName pin;
};
#if DEVICE_SPI
struct spi_s {
BP_SPI_TypeDef *spi;
uint32_t freq;
uint32_t freq_r;
gpio_t cs;
};
#endif
#if DEVICE_I2C
struct i2c_s {
BP_I2C_TypeDef *i2c;
uint32_t index;
unsigned int addrlen;
uint32_t xfer_freq;
};
#endif
#if DEVICE_ANALOGIN
struct analogin_s {
uint8_t channel;
};
#endif
#if DEVICE_FLASH
struct flash_s {
uint32_t dummy;
};
#endif
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include "cmsis.h"
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "PeripheralPins.h"
void set_alt(uint8_t port, uint8_t pin, uint8_t alt)
{
switch (alt) {
case ALT0 :
case ALT1 :
modifyreg32(GPIO_PORT_BASE(port) + GPIO_ALTFUNCSET_OFFSET,
0x01 << pin, 0x01 << pin);
modifyreg32(GPIO_PORT_BASE(port) + GPIO_ALTFUNCSEL_OFFSET,
0x01 << pin, 0x01 << pin);
modifyreg32(GPIO_PORT_BASE(port) + GPIO_ALTFUNCSEL_OFFSET,
0x1 << (pin), alt << (pin));
break;
default:
break;
}
}
void set_pullup(uint8_t port, uint8_t pin, uint8_t pullup)
{
if (pullup == PullNone) {
return;
}
uint8_t idx = port * 4 + pin / 4 + 2;
uint8_t bit = (pin << 3) % 32;
modifyreg32(&BP_SYSCON->IOCFG[idx], 0x1C << bit, pullup << bit);
}
void set_drvstr(uint8_t port, uint8_t pin, uint8_t str)
{
modifyreg32(&BP_SYSCON->IOCFG_GENERAL, 0x3, str);
}
void pin_function(PinName pin, int function)
{
uint8_t port_n = BP6A_PORT_IDX(pin);
uint8_t pin_n = BP6A_PIN_IDX(pin);
MBED_ASSERT(port_n < 3 && pin_n < 16);
bp6a_set_pin_config(port_n, pin_n, GET_PIN_DIR(function));
set_alt(port_n, pin_n, GET_PIN_SEL(function));
set_pullup(port_n, pin_n, GET_PIN_MODE(function));
}
void pin_mode(PinName pin, PinMode mode)
{
MBED_ASSERT(pin != (PinName)NC);
uint8_t port_n = BP6A_PORT_IDX(pin);
uint8_t pin_n = BP6A_PIN_IDX(pin);
set_pullup(port_n, pin_n, mode);
}

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#if DEVICE_RTC
#include <stdlib.h>
#include "cmsis.h"
#include "rtc_api.h"
#include "mbed_mktime.h"
#include "mbed_critical.h"
#include "mbed_error.h"
#include "mbed_debug.h"
#define BP6A_RTC_START_TIME 946684800
static bool rtc_initialized = false;
static bool g_before2000 = false;
void rtc_init(void)
{
if (!rtc_initialized) {
uint32_t sys_clk = bp6a_cmu_get_clock_freq(CMU_FCLK_AHBCLK);
bp6a_set_rtc_delay((uint32_t)((float)sys_clk * 2 / 32789));
bp6a_rtc_init();
rtc_initialized = true;
}
}
void rtc_free(void)
{
rtc_initialized = 0;
}
int rtc_isenabled(void)
{
return 1;
}
time_t rtc_read(void)
{
struct rtc_bcd_s rtc_val;
struct tm timeinfo;
time_t t;
bp6a_rtc_getdatetime(&rtc_val);
timeinfo.tm_sec = bp6a_rtc_bcd2bin(rtc_val.sec);
timeinfo.tm_min = bp6a_rtc_bcd2bin(rtc_val.min);
timeinfo.tm_hour = bp6a_rtc_bcd2bin(rtc_val.hour);
timeinfo.tm_mday = bp6a_rtc_bcd2bin(rtc_val.day);
timeinfo.tm_mon = bp6a_rtc_bcd2bin(rtc_val.mon);
timeinfo.tm_year = bp6a_rtc_bcd2bin(rtc_val.year);
timeinfo.tm_year += 100;
if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
return 0;
}
if (g_before2000) {
t -= BP6A_RTC_START_TIME;
}
return t;
}
void rtc_write(time_t t)
{
struct rtc_bcd_s rtc_val;
struct tm timeinfo;
/*BP6A : The implicit number of thousands place is 20.*/
if (t < BP6A_RTC_START_TIME) {
g_before2000 = true;
t += BP6A_RTC_START_TIME;
} else {
g_before2000 = false;
}
if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
return;
}
rtc_val.sec = timeinfo.tm_sec;
rtc_val.min = timeinfo.tm_min;
rtc_val.hour = timeinfo.tm_hour;
rtc_val.day = timeinfo.tm_mday;
rtc_val.mon = timeinfo.tm_mon;
rtc_val.year = timeinfo.tm_year - 100;
bp6a_rtc_setdatetime(&rtc_val);
}
#endif /* DEVICE_RTC */

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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#if DEVICE_SERIAL
#include <math.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "mbed_assert.h"
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define UART_NUM 3
#define UART_HWCONTROL_NONE 0
#define UART_HWCONTROL_RTS 1
#define UART_HWCONTROL_CTS 2
#define UART_HWCONTROL_RTS_CTS 3
static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
//#define _USE_UART_FIFO
#if DEVICE_SERIAL_ASYNCH
#define serial_s(obj) (&((obj)->serial))
#else
#define serial_s(obj) (obj)
#endif
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
struct serial_s *objs = serial_s(obj);
// determine the UART to use
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart != NC);
/* Configure the TX and RX pins */
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// Configure UART
objs->baudrate = 115200; // baudrate default value
if (uart == STDIO_UART) {
#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE
objs->baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json
#endif /* MBED_CONF_PLATFORM_STDIO_BAUD_RATE */
} else {
#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE
objs->baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; // baudrate takes value from platform/mbed_lib.json
#endif /* MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE */
}
objs->databits = UART_WL_8BIT;
objs->stopbits = UART_1_STOP_BIT;
objs->parity = UART_NO_PARITY;
#if DEVICE_SERIAL_FC
objs->hw_flow_ctl = UART_HWCONTROL_NONE;
#endif
objs->pin_tx = uart_tx;
objs->pin_rx = uart_rx;
objs->index = 0;
objs->uart = uart;
switch (uart) {
case UART_0:
obj->index = 0;
break;
case UART_1:
obj->index = 1;
break;
case UART_2:
obj->index = 2;
break;
}
bp6a_cmu_enable_clock(obj->index + CMU_UART0_CLK, true);
modifyreg32(uart + UART_ULCON_OFFSET,
UART_ULCON_WORD_LEN_MASK |
UART_ULCON_N_STOP_BIT_MASK |
UART_ULCON_PARITY_MODE_MASK,
UART_ULCON_WORD_LEN(UART_WL_8BIT) |
UART_ULCON_N_STOP_BIT(UART_1_STOP_BIT) |
UART_ULCON_PARITY_MODE(UART_NO_PARITY));
modifyreg32(uart + UART_UCON_OFFSET,
UART_UCON_RCV_MODE_MASK |
UART_UCON_TX_MODE_MASK |
UART_UCON_RX_TIMOUT_INT_INTER_MASK,
UART_UCON_RCV_MODE(0x01) |
UART_UCON_TX_MODE(0x01));
modifyreg32(uart + UART_UFCON_OFFSET,
UART_UFCON_RX_FIFO_RESET_MASK |
UART_UFCON_TX_FIFO_RESET_MASK,
UART_UFCON_RX_FIFO_RESET(0x01) |
UART_UFCON_TX_FIFO_RESET(0x01));
serial_baud(obj, objs->baudrate);
if (uart == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
bp6a_cmu_enable_clock(obj->index + CMU_UART0_CLK, false);
}
void serial_baud(serial_t *obj, int baudrate)
{
struct serial_s *objs = serial_s(obj);
float fFrac = 0;
float fDiv = 0;
uint32_t Peri_Clock = bp6a_cmu_get_clock_freq(CMU_UART0_CLK);
fDiv = ((float)Peri_Clock / ((float)baudrate * 16)) - (float)1.0;
fFrac = (uint32_t)((fDiv - (int32_t)fDiv) * 16.0f);
putreg32(objs->uart + UART_UBRDIV_OFFSET, (uint32_t)fDiv);
putreg32(objs->uart + UART_UFRAC_OFFSET, (uint32_t)fFrac);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
struct serial_s *objs = serial_s(obj);
uint8_t prity_bits[] = {UART_NO_PARITY, UART_ODD_PARITY, UART_EVEN_PARITY, \
UART_FORCE_1_PARITY, UART_FORCE_0_PARITY
};
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
modifyreg32(objs->uart + UART_ULCON_OFFSET,
UART_ULCON_WORD_LEN_MASK |
UART_ULCON_N_STOP_BIT_MASK |
UART_ULCON_PARITY_MODE_MASK,
UART_ULCON_WORD_LEN(data_bits - 5) |
UART_ULCON_N_STOP_BIT(stop_bits - 1) |
UART_ULCON_PARITY_MODE(prity_bits[parity]));
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void _uart_irq_handler(SerialIrq irq_type, uint32_t index)
{
if (serial_irq_ids[index] != 0) {
irq_handler(serial_irq_ids[index], irq_type);
}
}
void uart0_irq(void)
{
uint32_t uints = getreg32(BP_UART0_BASE + UART_UINTP_OFFSET);
if (uints & UART_UINTS_RXD_MASK) {
_uart_irq_handler(RxIrq, 0);
modifyreg32(BP_UART0_BASE + UART_UINTP_OFFSET,
UART_UINTP_RXD_MASK,
UART_UINTP_RXD(1));
} else if (uints & UART_UINTS_TXD_MASK) {
_uart_irq_handler(TxIrq, 0);
modifyreg32(BP_UART0_BASE + UART_UINTP_OFFSET,
UART_UINTP_TXD_MASK,
UART_UINTP_TXD(1));
}
NVIC_ClearPendingIRQ((IRQn_Type)UARTR0_IRQn);
}
void uart1_irq(void)
{
uint32_t uints = getreg32(BP_UART1_BASE + UART_UINTP_OFFSET);
if (uints & UART_UINTS_RXD_MASK) {
_uart_irq_handler(RxIrq, 1);
modifyreg32(BP_UART1_BASE + UART_UINTP_OFFSET,
UART_UINTP_RXD_MASK,
UART_UINTP_RXD(1));
} else if (uints & UART_UINTS_TXD_MASK) {
_uart_irq_handler(TxIrq, 1);
modifyreg32(BP_UART1_BASE + UART_UINTP_OFFSET,
UART_UINTP_TXD_MASK,
UART_UINTP_TXD(1));
}
NVIC_ClearPendingIRQ((IRQn_Type)UARTR1_IRQn);
}
void uart2_irq(void)
{
uint32_t uints = getreg32(BP_UART0_BASE + UART_UINTP_OFFSET);
if (uints & UART_UINTS_RXD_MASK) {
_uart_irq_handler(RxIrq, 2);
modifyreg32(BP_UART2_BASE + UART_UINTP_OFFSET,
UART_UINTP_TXD_MASK,
UART_UINTP_TXD(1));
} else if (uints & UART_UINTS_TXD_MASK) {
_uart_irq_handler(TxIrq, 2);
modifyreg32(BP_UART2_BASE + UART_UINTP_OFFSET,
UART_UINTP_TXD_MASK,
UART_UINTP_TXD(1));
}
NVIC_ClearPendingIRQ((IRQn_Type)UARTR2_IRQn);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
struct serial_s *objs = serial_s(obj);
uint8_t en = (enable != 0) ? 1 : 0;
uint32_t vector = 0;
switch ((int)objs->uart) {
case UART_0:
vector = (uint32_t)&uart0_irq;
break;
case UART_1:
vector = (uint32_t)&uart1_irq;
break;
case UART_2:
vector = (uint32_t)&uart2_irq;
break;
}
if (irq == RxIrq) {
modifyreg32(obj->uart + UART_UCON_OFFSET,
UART_UCON_RCV_MODE_MASK |
UART_UCON_RX_INT_TYPE_MASK,
UART_UCON_RCV_MODE(1) |
UART_UCON_RX_INT_TYPE(1));
modifyreg32(obj->uart + UART_UINTM_OFFSET,
UART_UINTM_RXD_MASK |
UART_UINTM_TXD_MASK,
UART_UINTM_RXD(!en) |
UART_UINTM_TXD(en));
} else {
modifyreg32(obj->uart + UART_UCON_OFFSET,
UART_UCON_TX_MODE_MASK |
UART_UCON_TX_INT_TYPE_MASK,
UART_UCON_TX_MODE(1) |
UART_UCON_TX_INT_TYPE(1));
modifyreg32(obj->uart + UART_UINTM_OFFSET,
UART_UINTM_TXD_MASK |
UART_UINTM_TXD_MASK,
UART_UINTM_RXD(en) |
UART_UINTM_TXD(!en));
}
#ifdef _USE_UART_FIFO
modifyreg32(obj->uart + UART_UFCON_OFFSET,
UART_UFCON_FIFO_EN_MASK,
UART_UFCON_FIFO_EN(1));
#endif
if (enable) {
NVIC_ClearPendingIRQ((IRQn_Type)(UARTR0_IRQn + objs->index));
NVIC_SetVector((IRQn_Type)(UARTR0_IRQn + objs->index), vector);
NVIC_EnableIRQ((IRQn_Type)(UARTR0_IRQn + objs->index));
} else {
uint32_t intm = getreg32(obj->uart + UART_UINTM_OFFSET);
if (intm == 0) {
NVIC_DisableIRQ((IRQn_Type)(UARTR0_IRQn + objs->index));
}
}
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj)
{
struct serial_s *objs = serial_s(obj);
while (!serial_readable(obj));
return getreg8(objs->uart + UART_URXH_OFFSET);
}
void serial_putc(serial_t *obj, int c)
{
struct serial_s *objs = serial_s(obj);
while (!serial_writable(obj));
putreg8(objs->uart + UART_UTXH_OFFSET, (uint8_t)c);
}
int serial_readable(serial_t *obj)
{
struct serial_s *objs = serial_s(obj);
return (getreg32(objs->uart + UART_UTRSTAT_OFFSET) & UART_UTRSTAT_RCV_BUF_DATA_READY_MASK);
}
int serial_writable(serial_t *obj)
{
struct serial_s *objs = serial_s(obj);
#ifdef _USE_UART_FIFO
return !((getreg32(objs->uart + UART_UFSTAT_OFFSET) & UART_UFSTAT_TX_FIFO_FULL_MASK) >> UART_UFSTAT_TX_FIFO_FULL_SHIFT);
#else
return ((getreg32(objs->uart + UART_UTRSTAT_OFFSET) & UART_UTRSTAT_TX_BUF_EMPTY_MASK));
#endif
}
void serial_clear(serial_t *obj)
{
struct serial_s *objs = serial_s(obj);
modifyreg32(objs->uart + UART_UFCON_OFFSET, UART_UFCON_RX_FIFO_RESET_MASK |
UART_UFCON_TX_FIFO_RESET_MASK,
UART_UFCON_RX_FIFO_RESET(1) |
UART_UFCON_TX_FIFO_RESET(1));
}
#if DEVICE_SERIAL_FC
void serial_set_flow_control(serial_t *obj, FlowControl type,
PinName rxflow, PinName txflow)
{
struct serial_s *objs = serial_s(obj);
UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
if (((UARTName)pinmap_merge(uart_rts, objs->uart) == (UARTName)NC) || ((UARTName)pinmap_merge(uart_cts, objs->uart) == (UARTName)NC)) {
MBED_ASSERT(0);
return;
}
if (type == FlowControlNone) {
// Disable hardware flow control
objs->hw_flow_ctl = UART_HWCONTROL_NONE;
}
if (type == FlowControlRTS) {
// Enable RTS
MBED_ASSERT(uart_rts != (UARTName)NC);
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
objs->pin_rts = rxflow;
}
if (type == FlowControlCTS) {
// Enable CTS
MBED_ASSERT(uart_cts != (UARTName)NC);
// Enable the pin for CTS function
pinmap_pinout(txflow, PinMap_UART_CTS);
objs->hw_flow_ctl = UART_HWCONTROL_CTS;
objs->pin_cts = txflow;
}
if (type == FlowControlRTSCTS) {
// Enable CTS & RTS
MBED_ASSERT(uart_rts != (UARTName)NC);
MBED_ASSERT(uart_cts != (UARTName)NC);
// Enable the pin for CTS function
pinmap_pinout(txflow, PinMap_UART_CTS);
// Enable the pin for RTS function
pinmap_pinout(rxflow, PinMap_UART_RTS);
objs->hw_flow_ctl = UART_HWCONTROL_RTS_CTS;
objs->pin_rts = rxflow;
objs->pin_cts = txflow;
}
modifyreg32(objs->uart + UART_UMCON_OFFSET, UART_UMCON_AFC_MASK |
UART_UMCON_AFC_MASK,
UART_UMCON_RTS(1) |
UART_UMCON_AFC(1));
}
#endif
void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj)
{
struct serial_s *objs = serial_s(obj);
modifyreg32(objs->uart + UART_UCON_OFFSET, UART_UCON_SND_BRK_SIG_MASK, UART_UCON_SND_BRK_SIG(1));
}
void serial_break_clear(serial_t *obj)
{
struct serial_s *objs = serial_s(obj);
modifyreg32(objs->uart + UART_UCON_OFFSET, UART_UCON_SND_BRK_SIG_MASK, UART_UCON_SND_BRK_SIG(0));
}
const PinMap *serial_tx_pinmap()
{
return PinMap_UART_TX;
}
const PinMap *serial_rx_pinmap()
{
return PinMap_UART_RX;
}
const PinMap *serial_cts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_CTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_CTS;
}
const PinMap *serial_rts_pinmap()
{
#if !DEVICE_SERIAL_FC
static const PinMap PinMap_UART_RTS[] = {
{NC, NC, 0}
};
#endif
return PinMap_UART_RTS;
}
#endif

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/sleep_api.c Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdio.h>
#include <stdint.h>
#include "cmsis.h"
#include "s1sbp6a_pmu.h"
/****************************************************************************
* Public function
****************************************************************************/
void hal_sleep(void)
{
bp6a_power_mode(PMU_LPM4);
}
void hal_deepsleep(void)
{
bp6a_power_mode(PMU_LPM3);
}

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/spi_api.c Normal file
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/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#if DEVICE_SPI
#include "cmsis.h"
#include "spi_api.h"
#include "gpio_api.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "PeripheralPins.h"
static void ssp_cs_manual(spi_t *obj)
{
modifyreg32(&(obj->spi->CR1), SSP_CR1_MFSS_MASK, SSP_CR1_MFSS(1));
gpio_dir(&obj->cs, PIN_OUTPUT);
}
static void ssp_exchange(spi_t *obj, const void *txbuffer, void *rxbuffer, size_t nwords)
{
size_t sent = 0;
size_t received = 0;
int word_length;
BP_SPI_TypeDef *base_reg;
base_reg = (BP_SPI_TypeDef *)obj->spi;
word_length = (base_reg->CR0 & SSP_CR0_DSS_MASK) >> SSP_CR0_DSS_SHIFT;
if ((rxbuffer == NULL) && (txbuffer == NULL)) {
while (received < nwords) {
if (sent < nwords)
if (!isTXFIFOFull(base_reg->SR)) {
base_reg->DR = 0;
sent++;
}
if (isRXFIFOEmpty(base_reg->SR)) {
received++;
}
}
return;
}
if (rxbuffer == NULL) {
while (received < nwords) {
if (sent < nwords)
if (!isTXFIFOFull(base_reg->SR)) {
if (word_length > SSP_CR0_DSS_8BIT) {
base_reg->DR = ((uint16_t *) txbuffer)[sent++];
} else {
base_reg->DR = ((uint8_t *) txbuffer)[sent++];
}
}
if (isRXFIFOEmpty(base_reg->SR)) {
received++;
}
}
return;
}
if (txbuffer == NULL) {
while (received < nwords) {
if (sent < nwords)
if (!isTXFIFOFull(base_reg->SR)) {
if (word_length > SSP_CR0_DSS_8BIT) {
base_reg->DR = ((uint16_t *) rxbuffer)[sent++];
} else {
base_reg->DR = ((uint8_t *) rxbuffer)[sent++];
}
}
if (isRXFIFOEmpty(base_reg->SR)) {
if (word_length > SSP_CR0_DSS_8BIT) {
((uint16_t *) rxbuffer)[received++] = base_reg->DR;
} else {
((uint8_t *) rxbuffer)[received++] = base_reg->DR;
}
}
}
return;
}
while (received < nwords) {
if (sent < nwords)
if (isTXFIFOEmpty(base_reg->SR)) {
if (word_length > SSP_CR0_DSS_8BIT) {
base_reg->DR = ((uint16_t *) txbuffer)[sent++];
} else {
base_reg->DR = ((uint8_t *) txbuffer)[sent++];
}
}
if (isRXFIFOEmpty(base_reg->SR)) {
if (word_length > SSP_CR0_DSS_8BIT) {
((uint16_t *) rxbuffer)[received++] = base_reg->DR;
} else {
((uint8_t *) rxbuffer)[received++] = base_reg->DR;
}
}
}
}
static inline int ssp_disable(spi_t *obj)
{
return obj->spi->CR1 &= ~(1 << 1);
}
static inline int ssp_enable(spi_t *obj)
{
return obj->spi->CR1 |= SSP_CR1_SSE_MASK;
}
static inline int ssp_readable(spi_t *obj)
{
return obj->spi->SR & (1 << 2);
}
static inline int ssp_writeable(spi_t *obj)
{
return obj->spi->SR & SSP_SR_BSY_MASK;
}
static inline void ssp_write(spi_t *obj, int value)
{
obj->spi->DR = value;
while (ssp_writeable(obj));
}
static inline int ssp_read(spi_t *obj)
{
int read_DR = obj->spi->DR;
return read_DR;
}
static inline int ssp_busy(spi_t *obj)
{
return (obj->spi->SR & (1 << 4)) ? (1) : (0);
}
static void spi_select(spi_t *obj, int selected)
{
gpio_write(&obj->cs, selected);
}
int spi_master_write(spi_t *obj, int value)
{
unsigned char txbyte;
unsigned char rxbyte;
txbyte = (unsigned char)value;
rxbyte = (unsigned char)0;
spi_select(obj, 0);
ssp_exchange(obj, &txbyte, &rxbyte, 1);
spi_select(obj, 1);
return (unsigned int)rxbyte;
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
spi_select(obj, 0);
ssp_exchange(obj, tx_buffer, rx_buffer, total);
spi_select(obj, 1);
return total;
}
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk)
{
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_per;
// If 3 wire SPI is used, the miso is not connected.
if (miso == NC) {
spi_per = (SPIName)pinmap_merge(spi_mosi, spi_sclk);
} else {
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
spi_per = (SPIName)pinmap_merge(spi_data, spi_sclk);
}
return spi_per;
}
static int get_spi_channel(uint32_t spi)
{
int i;
for (i = 0; i < 4; i++) {
if (PinMap_SPI_SCLK[i].peripheral == (int)spi) {
return i;
}
}
return -1;
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (BP_SPI_TypeDef *)pinmap_merge(spi_data, spi_cntl);
if ((int)obj->spi == NC) {
error("SPI pinout mapping failed");
}
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
pinmap_pinout(ssel, PinMap_SPI_SSEL);
gpio_init(&obj->cs, spi_ssel);
modifyreg32(&(obj->spi->CR1), SSP_CR1_RXIFLSEL_MASK |
SSP_CR1_TXIFLSEL_MASK,
SSP_CR1_RXIFLSEL(4) |
SSP_CR1_TXIFLSEL(4));
int spi_idx = get_spi_channel((uint32_t)(obj->spi));
bp6a_cmu_enable_clock(spi_idx + CMU_SPI0_CLK, true);
ssp_cs_manual(obj);
spi_select(obj, 1);
ssp_enable(obj);
}
void spi_free(spi_t *obj)
{
int spi_idx = get_spi_channel((uint32_t)obj->spi);
bp6a_cmu_enable_clock(spi_idx + CMU_SPI0_CLK, false);
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
error("SPI format error");
}
modifyreg32(&(obj->spi->CR1), SSP_CR1_MS_MASK, SSP_CR1_MS(slave));
modifyreg32(&(obj->spi->CR0),
SSP_CR0_DSS_MASK |
SSP_CR0_FRF_MASK |
SSP_CR0_SPO_MASK |
SSP_CR0_SPH_MASK,
SSP_CR0_DSS(bits - 1) |
SSP_CR0_FRF(0) |
SSP_CR0_SPO(!!(mode & 0x01)) |
SSP_CR0_SPH(!!(mode & 0x02)));
}
void spi_frequency(spi_t *obj, int hz)
{
uint32_t cpsdvsr;
uint32_t scr;
uint32_t freq = bp6a_get_clock_src_freq(CMU_SPI0_CLK);
if (!obj && hz > (int)(freq / 2)) {
error("SPI Clock error");
}
for (scr = 1; scr <= 256; scr++) {
cpsdvsr = (freq / scr) / hz;
if (cpsdvsr < 255) {
break;
}
}
if (scr > 256 || cpsdvsr > 255) {
error("Couldn't setup requested SPI frequency");
}
if (cpsdvsr < 2) {
cpsdvsr = 2;
} else if (cpsdvsr > 254) {
cpsdvsr = 254;
}
cpsdvsr = (cpsdvsr + 1) & ~1;
putreg32(&(obj->spi->CPSR), cpsdvsr);
modifyreg32(&(obj->spi->CR0), SSP_CR0_SCR_MASK, SSP_CR0_SCR(scr));
obj->freq = hz;
obj->freq_r = (freq / cpsdvsr) / scr;
}
int spi_slave_receive(spi_t *obj)
{
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
}
int spi_slave_read(spi_t *obj)
{
return obj->spi->DR;
}
void spi_slave_write(spi_t *obj, int value)
{
while (ssp_writeable(obj) == 0) ;
obj->spi->DR = value;
}
int spi_busy(spi_t *obj)
{
return isBusy(obj->spi->SR);
}
const PinMap *spi_master_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_master_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_master_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_master_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
const PinMap *spi_slave_mosi_pinmap()
{
return PinMap_SPI_MOSI;
}
const PinMap *spi_slave_miso_pinmap()
{
return PinMap_SPI_MISO;
}
const PinMap *spi_slave_clk_pinmap()
{
return PinMap_SPI_SCLK;
}
const PinMap *spi_slave_cs_pinmap()
{
return PinMap_SPI_SSEL;
}
#endif

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targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/us_ticker.c Normal file
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@ -0,0 +1,122 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#include "cmsis.h"
#define US_TICKER_COUNTER BP_DUAL_TIMER0
#define US_TICKER_INTERRUPT BP_DUAL_TIMER1
#define US_TICKER_TIMER_IRQn DUAL_TIMER_IRQn
static int us_ticker_inited = 0;
void __us_ticker_irq_handler(void *arg)
{
UNUSED(arg);
us_ticker_disable_interrupt();
us_ticker_clear_interrupt();
us_ticker_irq_handler();
}
void us_ticker_init(void)
{
if (us_ticker_inited) {
us_ticker_disable_interrupt();
return;
}
if (!bp6a_cmu_get_clock_enabled(CMU_DUALTIMER_APBCLK)) {
bp6a_cmu_enable_clock(CMU_DUALTIMER_APBCLK, true);
}
US_TICKER_COUNTER->CTRL = 0x0ul; // disable TIMER1 and reset all control
US_TICKER_INTERRUPT->CTRL = 0x0ul; // disable TIMER2 and reset all control
US_TICKER_COUNTER->LOAD = 0xFFFFFFFFul;
US_TICKER_INTERRUPT->LOAD = 0xFFFFFFFFul;
US_TICKER_INTERRUPT->BGLOAD = 0xFFFFFFFFul;
US_TICKER_COUNTER->CTRL |= DUALTIMER_CTRL_SIZE(1); // set TIMER1 to 32 bit counter
US_TICKER_INTERRUPT->CTRL |= DUALTIMER_CTRL_SIZE(1); // set TIMER2 to 32 bit counter
US_TICKER_COUNTER->CTRL |= DUALTIMER_CTRL_PRESCALE(1); // set TIMER1 with 1 stages prescale
US_TICKER_INTERRUPT->CTRL |= DUALTIMER_CTRL_PRESCALE(1); // set TIMER2 with 1 stages prescale
US_TICKER_INTERRUPT->CTRL |= DUALTIMER_CTRL_MODE(1); // set TIMER2 periodic mode
US_TICKER_INTERRUPT->CTRL |= DUALTIMER_CTRL_ONESHOOT(1); // set TIMER2 one-shot mode
US_TICKER_COUNTER->CTRL |= DUALTIMER_CTRL_EN(1); // enable TIMER1 counter
NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)__us_ticker_irq_handler);
us_ticker_inited = 1;
}
void us_ticker_free(void)
{
US_TICKER_COUNTER->CTRL &= ~DUALTIMER_CTRL_EN_MASK; // disable TIMER1
US_TICKER_INTERRUPT->CTRL &= ~DUALTIMER_CTRL_EN_MASK; // disable TIMER2
us_ticker_disable_interrupt();
us_ticker_inited = 0;
}
uint32_t us_ticker_read()
{
return ~US_TICKER_COUNTER->VALUE;
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
uint32_t delta = timestamp - us_ticker_read();
US_TICKER_INTERRUPT->CTRL &= ~DUALTIMER_CTRL_EN_MASK; // disable TIMER2
US_TICKER_INTERRUPT->LOAD = delta; // Set TIMER2 load value
US_TICKER_INTERRUPT->CTRL |= DUALTIMER_CTRL_INTEN_MASK; // enable TIMER2 interrupt
US_TICKER_INTERRUPT->CTRL |= DUALTIMER_CTRL_EN_MASK; // enable TIMER2 counter
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
void us_ticker_fire_interrupt(void)
{
NVIC_EnableIRQ(US_TICKER_TIMER_IRQn);
NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
}
void us_ticker_disable_interrupt(void)
{
US_TICKER_INTERRUPT->CTRL &= ~DUALTIMER_CTRL_INTEN_MASK;
US_TICKER_INTERRUPT->CTRL &= ~DUALTIMER_CTRL_EN_MASK; // disable TIMER2
NVIC_DisableIRQ(US_TICKER_TIMER_IRQn);
}
void us_ticker_clear_interrupt(void)
{
US_TICKER_INTERRUPT->INTCLR = DUALTIMER_INTCLR_MASK;
}
const ticker_info_t *us_ticker_get_info(void)
{
uint32_t timer_clk = bp6a_get_clock_src_freq(CMU_DUALTIMER_APBCLK);
static ticker_info_t info;
info.frequency = timer_clk / 16;
info.bits = 32;
return &info;
}

81
targets/TARGET_Samsung/TARGET_SIDK_S1SBP6A/watchdog_api.c Normal file
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@ -0,0 +1,81 @@
/****************************************************************************
*
* Copyright 2020 Samsung Electronics All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
* either express or implied. See the License for the specific
* language governing permissions and limitations under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#if DEVICE_WATCHDOG
#include <string.h>
#include <stdio.h>
#include "cmsis_os.h"
#include "cmsis.h"
#include "watchdog_api.h"
static uint32_t wdt_timeout_reload_ms = 0;
watchdog_status_t hal_watchdog_init(const watchdog_config_t *config)
{
/* Check validity of arguments */
if (!config || !config->timeout_ms) {
return WATCHDOG_STATUS_INVALID_ARGUMENT;
}
wdt_timeout_reload_ms = config->timeout_ms;
bp6a_wdog_init(wdt_timeout_reload_ms);
return WATCHDOG_STATUS_OK;
}
void hal_watchdog_kick(void)
{
bp6a_wdog_set_reload_time(wdt_timeout_reload_ms);
}
watchdog_status_t hal_watchdog_stop(void)
{
bp6a_watchdog_enable(false);
bp6a_wdog_reset_enable(false);
return WATCHDOG_STATUS_OK;
}
uint32_t hal_watchdog_get_reload_value(void)
{
return wdt_timeout_reload_ms;
}
watchdog_features_t hal_watchdog_get_platform_features(void)
{
watchdog_features_t wdt_feat;
uint32_t wdog_clock = bp6a_cmu_get_clock_freq(CMU_WATCHDOG_APBCLK);
/* We can support timeout values between 1 and UINT32_MAX by cascading. */
wdt_feat.max_timeout = (uint32_t)(UINT32_MAX / wdog_clock);
/* Support re-configuring watchdog timer */
wdt_feat.update_config = 1;
/* Support stopping watchdog timer */
wdt_feat.disable_watchdog = 1;
wdt_feat.clock_typical_frequency = wdog_clock;
wdt_feat.clock_max_frequency = wdog_clock * 1.1;
return wdt_feat;
}
#endif

0
targets/TARGET_Samsung/security_subsystem/api/trng_api.c → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/api/trng_api.c
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0
targets/TARGET_Samsung/security_subsystem/drivers/mb_cmd_hash.c → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/mb_cmd_hash.c
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0
targets/TARGET_Samsung/security_subsystem/drivers/mb_cmd_hash.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/mb_cmd_hash.h
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0
targets/TARGET_Samsung/security_subsystem/drivers/mb_cmd_rng.c → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/mb_cmd_rng.c
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0
targets/TARGET_Samsung/security_subsystem/drivers/mb_cmd_rng.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/mb_cmd_rng.h
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0
targets/TARGET_Samsung/security_subsystem/drivers/mb_cmd_system.c → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/mb_cmd_system.c
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0
targets/TARGET_Samsung/security_subsystem/drivers/mb_cmd_system.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/mb_cmd_system.h
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0
targets/TARGET_Samsung/security_subsystem/drivers/sss_common.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/sss_common.h
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0
targets/TARGET_Samsung/security_subsystem/drivers/sss_driver_error.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/sss_driver_error.h
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0
targets/TARGET_Samsung/security_subsystem/drivers/sss_driver_rng.c → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/sss_driver_rng.c
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0
targets/TARGET_Samsung/security_subsystem/drivers/sss_driver_rng.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/sss_driver_rng.h
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0
targets/TARGET_Samsung/security_subsystem/drivers/sss_driver_sha2.c → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/sss_driver_sha2.c
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0
targets/TARGET_Samsung/security_subsystem/drivers/sss_driver_sha2.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/sss_driver_sha2.h
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0
targets/TARGET_Samsung/security_subsystem/drivers/sss_driver_util.c → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/sss_driver_util.c
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0
targets/TARGET_Samsung/security_subsystem/drivers/sss_driver_util.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/sss_driver_util.h
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0
targets/TARGET_Samsung/security_subsystem/drivers/sss_map.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/sss_map.h
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0
targets/TARGET_Samsung/security_subsystem/drivers/sss_oid.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/drivers/sss_oid.h
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2
targets/TARGET_Samsung/security_subsystem/sss_common.h → targets/TARGET_Samsung/TARGET_SIDK_S5JS100/security_subsystem/sss_common.h
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@ -1,5 +1,5 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2020 ARM Limited
* Copyright (c) 2006-2019 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.

29
targets/targets.json
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@ -6661,7 +6661,34 @@
"macros_add": [
"CONFIG_GPIO_AS_PINRESET"
]
},
},
"S1SBP6A": {
"inherits": ["Target"],
"core": "Cortex-M4F",
"supported_toolchains": [
"GCC_ARM",
"ARMC6"
],
"default_toolchain": "GCC_ARM",
"extra_labels": [
"Samsung",
"SIDK_S1SBP6A"
],
"device_has": [
"USTICKER",
"INTERRUPTIN",
"SERIAL",
"MPU",
"SPI",
"I2C",
"RTC",
"FLASH",
"SLEEP",
"WATCHDOG"
],
"release_versions": ["5"],
"detect_code": ["3703"]
},
"__build_tools_metadata__": {
"version": "1",
"public": false