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Add SPIF_ULBPR command also to QSPIFBlockDevice and SPIFReducedBlockDevice

pull/9507/head
Philipp Steiner 2019-01-17 15:33:02 +01:00 committed by adbridge
parent 331c66d4fb
commit afd7f4133a
2 changed files with 4 additions and 2 deletions
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3
components/storage/blockdevice/COMPONENT_QSPIF/QSPIFBlockDevice.cpp
View File

@ -95,6 +95,7 @@ enum qspif_default_instructions {
QSPIF_RSTEN = 0x66, // Reset Enable QSPIF_RSTEN = 0x66, // Reset Enable
QSPIF_RST = 0x99, // Reset QSPIF_RST = 0x99, // Reset
QSPIF_RDID = 0x9f, // Read Manufacturer and JDEC Device ID QSPIF_RDID = 0x9f, // Read Manufacturer and JDEC Device ID
QSPIF_ULBPR = 0x98, // Clears all write-protection bits in the Block-Protection register
}; };
// Local Function // Local Function
@ -206,7 +207,7 @@ int QSPIFBlockDevice::init()
// SST devices come preset with block protection // SST devices come preset with block protection
// enabled for some regions, issue write disable instruction to clear // enabled for some regions, issue write disable instruction to clear
_set_write_enable(); _set_write_enable();
_qspi_send_general_command(QSPIF_WRDI, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0); _qspi_send_general_command(QSPIF_ULBPR, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0);
break; break;
} }

3
components/storage/blockdevice/COMPONENT_RSPIF/SPIFReducedBlockDevice.cpp
View File

@ -40,6 +40,7 @@ enum ops {
SPIF_WRDI = 0x04, // Write Disable SPIF_WRDI = 0x04, // Write Disable
SPIF_RDSR = 0x05, // Read Status Register SPIF_RDSR = 0x05, // Read Status Register
SPIF_RDID = 0x9f, // Read Manufacturer and JDEC Device ID SPIF_RDID = 0x9f, // Read Manufacturer and JDEC Device ID
SPIF_ULBPR = 0x98, // Clears all write-protection bits in the Block-Protection register
}; };
// Status register from RDSR // Status register from RDSR
@ -68,7 +69,7 @@ int SPIFReducedBlockDevice::init()
// SST devices come preset with block protection // SST devices come preset with block protection
// enabled for some regions, issue gbpu instruction to clear // enabled for some regions, issue gbpu instruction to clear
_wren(); _wren();
_cmdwrite(0x98, 0, 0, 0x0, NULL); _cmdwrite(SPIF_ULBPR, 0, 0, 0x0, NULL);
break; break;
} }