From 16ac412807ee515e33a9d303c5a0baa4ae591d5d Mon Sep 17 00:00:00 2001 From: George Beckstein Date: Thu, 21 May 2020 23:04:13 -0400 Subject: [PATCH 1/9] Add NUCLEO_G031K8 target configuration --- .../TARGET_NUCLEO_G031K8/PeripheralNames.h | 58 +++++ .../TARGET_NUCLEO_G031K8/PeripheralPins.c | 210 +++++++++++++++++ .../TARGET_NUCLEO_G031K8/PinNames.h | 222 ++++++++++++++++++ .../TARGET_NUCLEO_G031K8/system_clock.c | 173 ++++++++++++++ .../TARGET_STM/TARGET_STM32G0/serial_device.c | 5 + targets/TARGET_STM/lp_ticker.c | 2 +- targets/targets.json | 19 +- 7 files changed, 687 insertions(+), 2 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralNames.h new file mode 100644 index 0000000000..71cc971a62 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralNames.h @@ -0,0 +1,58 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2015 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + LPUART_1 = (int)LPUART1_BASE +} UARTName; + +#define DEVICE_SPI_COUNT 2 +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_14 = (int)TIM14_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c new file mode 100644 index 0000000000..4f837d713c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c @@ -0,0 +1,210 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 +// {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 // Connected to STDIO_UART_TX +// {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 // Connected to STDIO_UART_RX + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PA_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PA_13, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_IN17 // Connected to T_JTMS + {PA_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_IN18 // Connected to T_JTCK + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PB_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PB_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {NC, NC, 0} +}; + +// !!! SECTION TO BE CHECKED WITH DEVICE REFERENCE MANUAL +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_12, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PA_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM2 cannot be used because already used by the us_ticker +// You have to comment all PWM using TIM_MST defined in hal_tick.h file +// or update python script (check TIM_MST_LIST) and re-run it +MBED_WEAK const PinMap PinMap_PWM[] = { + // {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 + // {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 + // {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX + // {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX + {PA_4, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + // {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 + {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_9_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_10_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 + // {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 + {PB_3, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + // {PB_3_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 + {PC_6, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 // Connected to LD3 [Green] + {PC_6_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 // Connected to LD3 [Green] + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX + {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_9_ALT0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to T_JTCK + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX + {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_RX + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_10_ALT0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { +// {PA_2, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, // Connected to STDIO_UART_TX + {PA_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PA_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, + {PA_10_ALT0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, + {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_7, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { +// {PA_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, // Connected to STDIO_UART_RX + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_SPI2)}, + {PA_9_ALT0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_SPI2)}, + {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_6, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_SPI2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI2)}, + {PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_8, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PA_8, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_SPI2)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF0_SPI1)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h new file mode 100644 index 0000000000..46fa1635de --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h @@ -0,0 +1,222 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_1_ALT0 = PA_1 | ALT0, + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, + PA_2_ALT1 = PA_2 | ALT1, + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, + PA_3_ALT1 = PA_3 | ALT1, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, + PA_7_ALT1 = PA_7 | ALT1, + PA_7_ALT2 = PA_7 | ALT2, + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_14_ALT0 = PA_14 | ALT0, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, + + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, + PB_1_ALT1 = PB_1 | ALT1, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, + PB_4_ALT1 = PB_4 | ALT1, + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, + PB_5_ALT1 = PB_5 | ALT1, + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13 | ALT0, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, + PB_15_ALT1 = PB_15 | ALT1, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_8 = 0x38, + PD_9 = 0x39, + + PF_0 = 0x50, + PF_1 = 0x51, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino connector namings + A0 = PA_0, + A1 = PA_1, + A2 = PA_4, + A3 = PA_5, + A4 = PA_12, + A5 = PA_11, + A6 = PA_6, + A7 = PA_7, + D0 = PB_7, + D1 = PB_6, + D2 = PA_15, + D3 = PB_1, + D4 = PA_10, + D5 = PA_9, + D6 = PB_0, + D7 = PB_2, + D8 = PB_8, + D9 = PA_8, + D10 = PB_9, + D11 = PB_5, + D12 = PB_4, + D13 = PB_3, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_3, +#endif + + // Generic signals namings + LED1 = PC_6, + LED2 = PC_6, + LED3 = PC_6, + LED4 = PC_6, + + + + // This board does not have any buttons (aside from reset) + USER_BUTTON = PC_13, + // Standardized button names + BUTTON1 = USER_BUTTON, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, + I2C_SCL = PB_8, + I2C_SDA = PB_9, + SPI_MOSI = PA_7, + SPI_MISO = PA_6, + SPI_SCK = PA_5, + SPI_CS = PB_0, + PWM_OUT = PB_3, + + + + /**** OSCILLATOR pins ****/ + RCC_OSC32_EN = PC_15, + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_EN = PC_15, + RCC_OSC_IN = PC_14, + + /**** DEBUG pins ****/ + SYS_PVD_IN = PB_7, + SYS_SWCLK = PA_14, + SYS_SWDIO = PA_13, + SYS_WKUP1 = PA_0, + SYS_WKUP2 = PA_4, + SYS_WKUP4 = PA_2, + SYS_WKUP6 = PB_5, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c new file mode 100644 index 0000000000..5b79cdf058 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c @@ -0,0 +1,173 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + *----------------------------------------------------------------- + * SYSCLK(MHz) | 64 + * AHBCLK (MHz) | 64 + * APB1CLK (MHz) | 64 + * USB capable | NO + *----------------------------------------------------------------- + */ + +#include "stm32g0xx.h" +#include "mbed_error.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x100. */ + +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + { + error("SetSysClock failed\n"); + } + } + } + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; + RCC_OscInitStruct.PLL.PLLN = 16; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; + RCC_OscInitStruct.PLL.PLLN = 8; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; + RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/serial_device.c b/targets/TARGET_STM/TARGET_STM32G0/serial_device.c index b94924bd7b..41cd3a6993 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32G0/serial_device.c @@ -19,6 +19,11 @@ #define UART_NUM (5) +// Retarget this IRQn symbol for chips without USART3/4 +#if defined(STM32G031xx) +#define USART3_4_LPUART1_IRQn LPUART1_IRQn +#endif + uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index 48fea628ba..a702fbb141 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -112,7 +112,7 @@ #define RCC_LPTIMCLKSOURCE_LSE RCC_LPTIM1CLKSOURCE_LSE #define RCC_LPTIMCLKSOURCE_LSI RCC_LPTIM1CLKSOURCE_LSI -#if defined(STM32G0) +#if defined(STM32G071xx) #define LPTIM_MST_IRQ TIM6_DAC_LPTIM1_IRQn #else #define LPTIM_MST_IRQ LPTIM1_IRQn diff --git a/targets/targets.json b/targets/targets.json index c97cb630a1..da5d384b9b 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2363,7 +2363,6 @@ "lpticker_delay_ticks": 0 }, "device_has_add": [ - "ANALOGOUT", "SERIAL_ASYNCH", "FLASH", "MPU" @@ -2379,6 +2378,9 @@ ], "macros_add": [ "STM32G071xx" + ], + "device_has_add": [ + "ANALOGOUT" ] }, "NUCLEO_G071RB": { @@ -2401,6 +2403,21 @@ ], "device_name": "STM32G071RBTx" }, + "NUCLEO_G031K8": { + "inherits": [ + "MCU_STM32G0" + ], + "extra_labels_add": [ + "STM32G031xx" + ], + "macros_add": [ + "STM32G031xx" + ], + "detect_code": [ + "0852" + ], + "device_name": "STM32G031K8Tx" + }, "MCU_STM32G4": { "inherits": [ "MCU_STM32" From e3d26ed888492178d8f95730a7ee6a1520fca131 Mon Sep 17 00:00:00 2001 From: Pavel Slama Date: Thu, 13 Aug 2020 15:52:12 +0200 Subject: [PATCH 2/9] delete LED2-4 and buttons --- .../TARGET_NUCLEO_G031K8/PinNames.h | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h index 46fa1635de..902354bbc1 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h @@ -171,16 +171,6 @@ typedef enum { // Generic signals namings LED1 = PC_6, - LED2 = PC_6, - LED3 = PC_6, - LED4 = PC_6, - - - - // This board does not have any buttons (aside from reset) - USER_BUTTON = PC_13, - // Standardized button names - BUTTON1 = USER_BUTTON, SERIAL_TX = STDIO_UART_TX, SERIAL_RX = STDIO_UART_RX, USBTX = STDIO_UART_TX, @@ -193,8 +183,6 @@ typedef enum { SPI_CS = PB_0, PWM_OUT = PB_3, - - /**** OSCILLATOR pins ****/ RCC_OSC32_EN = PC_15, RCC_OSC32_IN = PC_14, From 25ea7be2ff307f4145402c49ff13d091c223ea0b Mon Sep 17 00:00:00 2001 From: Pavel Slama Date: Fri, 31 Jul 2020 13:01:45 +0200 Subject: [PATCH 3/9] add NUCLEO_G031K8 target --- .../STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h | 2 +- .../TARGET_NUCLEO_G031K8/PinNames.h | 1 - targets/TARGET_STM/TARGET_STM32G0/serial_device.c | 1 - targets/targets.json | 11 ++++++++++- 4 files changed, 11 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h index d220592e90..dff7098db2 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h @@ -3074,7 +3074,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t Backup */ __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister) { - const register __IO uint32_t *tmp; + register __IO uint32_t *tmp; tmp = &(TAMPx->BKP0R) + BackupRegister; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h index 902354bbc1..5f3e73f3d6 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h @@ -155,7 +155,6 @@ typedef enum { D10 = PB_9, D11 = PB_5, D12 = PB_4, - D13 = PB_3, // STDIO for console print #ifdef MBED_CONF_TARGET_STDIO_UART_TX diff --git a/targets/TARGET_STM/TARGET_STM32G0/serial_device.c b/targets/TARGET_STM/TARGET_STM32G0/serial_device.c index 41cd3a6993..4e586550fa 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32G0/serial_device.c @@ -24,7 +24,6 @@ #define USART3_4_LPUART1_IRQn LPUART1_IRQn #endif - uint32_t serial_irq_ids[UART_NUM] = {0}; UART_HandleTypeDef uart_handlers[UART_NUM]; diff --git a/targets/targets.json b/targets/targets.json index da5d384b9b..6f3012db7d 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2403,16 +2403,25 @@ ], "device_name": "STM32G071RBTx" }, - "NUCLEO_G031K8": { + "MCU_STM32G031xx": { "inherits": [ "MCU_STM32G0" ], + "public": false, "extra_labels_add": [ "STM32G031xx" ], "macros_add": [ "STM32G031xx" ], + "device_has_remove": [ + "ANALOGOUT" + ] + }, + "NUCLEO_G031K8": { + "inherits": [ + "MCU_STM32G031xx" + ], "detect_code": [ "0852" ], From ab6fd6e1eb5ff99591bb0a4689ff5023dcf348ef Mon Sep 17 00:00:00 2001 From: Pavel Slama Date: Sat, 1 Aug 2020 09:43:05 +0200 Subject: [PATCH 4/9] add D13 pin --- .../TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h index 5f3e73f3d6..902354bbc1 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h @@ -155,6 +155,7 @@ typedef enum { D10 = PB_9, D11 = PB_5, D12 = PB_4, + D13 = PB_3, // STDIO for console print #ifdef MBED_CONF_TARGET_STDIO_UART_TX From 8165bca233b4b4471c98e9a3a6b53e03285175c3 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Mon, 10 Aug 2020 16:52:28 +0200 Subject: [PATCH 5/9] STM32G0 review and test --- .../STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h | 2 +- .../TARGET_NUCLEO_G031K8/PeripheralPins.c | 65 ++++---- .../TARGET_NUCLEO_G031K8/PinNames.h | 152 ++++++------------ .../TARGET_NUCLEO_G031K8/system_clock.c | 46 +----- .../TARGET_STM32G031xx/cmsis_nvic.h | 13 +- .../TARGET_STM32G071xx/cmsis_nvic.h | 2 +- .../TARGET_STM/TARGET_STM32G0/serial_device.c | 26 +-- targets/targets.json | 45 +++--- 8 files changed, 131 insertions(+), 220 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h index dff7098db2..d220592e90 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h @@ -3074,7 +3074,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t Backup */ __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister) { - register __IO uint32_t *tmp; + const register __IO uint32_t *tmp; tmp = &(TAMPx->BKP0R) + BackupRegister; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c index 4f837d713c..3169043d68 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PeripheralPins.c @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2018 STMicroelectronics. + * Copyright (c) 2016-2020 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -11,6 +11,8 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32G031K(4-6-8)Tx.xml */ #include "PeripheralPins.h" @@ -86,15 +88,14 @@ MBED_WEAK const PinMap PinMap_I2C_SCL[] = { //*** PWM *** // TIM2 cannot be used because already used by the us_ticker -// You have to comment all PWM using TIM_MST defined in hal_tick.h file -// or update python script (check TIM_MST_LIST) and re-run it +// (update us_ticker_data.h file if another timer is chosen) MBED_WEAK const PinMap PinMap_PWM[] = { - // {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 - // {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 - // {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX - // {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 // Connected to STDIO_UART_TX +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)}, // TIM2_CH4 // Connected to STDIO_UART_RX {PA_4, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM14, 1, 0)}, // TIM14_CH1 - // {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM16, 1, 0)}, // TIM16_CH1 {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 1, 1)}, // TIM1_CH1N @@ -107,14 +108,14 @@ MBED_WEAK const PinMap PinMap_PWM[] = { {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 {PA_10_ALT0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 0)}, // TIM1_CH3 {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 4, 0)}, // TIM1_CH4 - // {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)}, // TIM2_CH1 {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 2, 1)}, // TIM1_CH2N {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 3, 0)}, // TIM3_CH3 {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM1, 3, 1)}, // TIM1_CH3N {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 4, 0)}, // TIM3_CH4 {PB_1_ALT1, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM14, 1, 0)}, // TIM14_CH1 {PB_3, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 - // {PB_3_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)}, // TIM2_CH2 {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 2, 0)}, // TIM3_CH2 {PB_6, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 @@ -122,46 +123,46 @@ MBED_WEAK const PinMap PinMap_PWM[] = { {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 1)}, // TIM17_CH1N {PB_8, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM16, 1, 0)}, // TIM16_CH1 {PB_9, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM17, 1, 0)}, // TIM17_CH1 - {PC_6, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 // Connected to LD3 [Green] - {PC_6_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 // Connected to LD3 [Green] +// {PC_6, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)}, // TIM2_CH3 // Connected to LD3 [Green] + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM3, 1, 0)}, // TIM3_CH1 // Connected to LD3 [Green] {NC, NC, 0} }; //*** SERIAL *** MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, - {PA_9_ALT0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, - {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to T_JTCK - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_TX +// {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_TX + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_9_ALT0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, +// {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to T_JTCK + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX - {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_RX - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, - {PA_10_ALT0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, - {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, // Connected to STDIO_UART_RX +// {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Connected to STDIO_UART_RX + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PA_10_ALT0, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, +// {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, - {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART2)}, + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_USART1)}, + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h index 902354bbc1..c0c538a6cd 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/PinNames.h @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2018 STMicroelectronics. + * Copyright (c) 2016-2020 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -11,6 +11,8 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32G031K(4-6-8)Tx.xml */ #ifndef MBED_PINNAMES_H @@ -31,109 +33,56 @@ typedef enum { } ALTx; typedef enum { - PA_0 = 0x00, - PA_1 = 0x01, - PA_1_ALT0 = PA_1 | ALT0, - PA_2 = 0x02, - PA_2_ALT0 = PA_2 | ALT0, - PA_2_ALT1 = PA_2 | ALT1, - PA_3 = 0x03, - PA_3_ALT0 = PA_3 | ALT0, - PA_3_ALT1 = PA_3 | ALT1, - PA_4 = 0x04, - PA_5 = 0x05, - PA_6 = 0x06, - PA_6_ALT0 = PA_6 | ALT0, - PA_7 = 0x07, - PA_7_ALT0 = PA_7 | ALT0, - PA_7_ALT1 = PA_7 | ALT1, - PA_7_ALT2 = PA_7 | ALT2, - PA_8 = 0x08, - PA_9 = 0x09, - PA_9_ALT0 = PA_9 | ALT0, - PA_10 = 0x0A, - PA_10_ALT0 = PA_10 | ALT0, - PA_11 = 0x0B, - PA_12 = 0x0C, - PA_13 = 0x0D, - PA_14 = 0x0E, - PA_14_ALT0 = PA_14 | ALT0, - PA_15 = 0x0F, - PA_15_ALT0 = PA_15 | ALT0, - PB_0 = 0x10, - PB_0_ALT0 = PB_0 | ALT0, - PB_1 = 0x11, - PB_1_ALT0 = PB_1 | ALT0, - PB_1_ALT1 = PB_1 | ALT1, - PB_2 = 0x12, - PB_3 = 0x13, - PB_4 = 0x14, - PB_4_ALT0 = PB_4 | ALT0, - PB_4_ALT1 = PB_4 | ALT1, - PB_5 = 0x15, - PB_5_ALT0 = PB_5 | ALT0, - PB_5_ALT1 = PB_5 | ALT1, - PB_6 = 0x16, - PB_6_ALT0 = PB_6 | ALT0, - PB_7 = 0x17, - PB_8 = 0x18, - PB_9 = 0x19, - PB_10 = 0x1A, - PB_11 = 0x1B, - PB_12 = 0x1C, - PB_13 = 0x1D, - PB_13_ALT0 = PB_13 | ALT0, - PB_14 = 0x1E, - PB_14_ALT0 = PB_14 | ALT0, - PB_15 = 0x1F, - PB_15_ALT0 = PB_15 | ALT0, - PB_15_ALT1 = PB_15 | ALT1, + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PC_6 = 0x26, + PC_14 = 0x2E, + PC_15 = 0x2F, - PC_0 = 0x20, - PC_1 = 0x21, - PC_2 = 0x22, - PC_3 = 0x23, - PC_4 = 0x24, - PC_4_ALT0 = PC_4 | ALT0, - PC_5 = 0x25, - PC_5_ALT0 = PC_5 | ALT0, - PC_6 = 0x26, - PC_6_ALT0 = PC_6 | ALT0, - PC_7 = 0x27, - PC_7_ALT0 = PC_7 | ALT0, - PC_8 = 0x28, - PC_8_ALT0 = PC_8 | ALT0, - PC_9 = 0x29, - PC_9_ALT0 = PC_9 | ALT0, - PC_10 = 0x2A, - PC_10_ALT0 = PC_10 | ALT0, - PC_11 = 0x2B, - PC_11_ALT0 = PC_11 | ALT0, - PC_12 = 0x2C, - PC_13 = 0x2D, - PC_14 = 0x2E, - PC_15 = 0x2F, + /**** ADC internal channels ****/ - PD_0 = 0x30, - PD_1 = 0x31, - PD_2 = 0x32, - PD_3 = 0x33, - PD_4 = 0x34, - PD_5 = 0x35, - PD_6 = 0x36, - PD_8 = 0x38, - PD_9 = 0x39, + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value - PF_0 = 0x50, - PF_1 = 0x51, - - // ADC internal channels - ADC_TEMP = 0xF0, - ADC_VREF = 0xF1, - ADC_VBAT = 0xF2, - - // Arduino connector namings + // Arduino Nano Header pin connection naming A0 = PA_0, A1 = PA_1, A2 = PA_4, @@ -170,7 +119,8 @@ typedef enum { #endif // Generic signals namings - LED1 = PC_6, + LED1 = PC_6, // LD3 [Green] + SERIAL_TX = STDIO_UART_TX, SERIAL_RX = STDIO_UART_RX, USBTX = STDIO_UART_TX, diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c index 5b79cdf058..e2f541a310 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2019 STMicroelectronics. + * Copyright (c) 2020 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -16,9 +16,7 @@ /** * This file configures the system clock as follows: *----------------------------------------------------------------- - * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) - * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) - * | 3- USE_PLL_HSI (internal 16 MHz) + * System clock source | USE_PLL_HSI (internal 16 MHz) *----------------------------------------------------------------- * SYSCLK(MHz) | 64 * AHBCLK (MHz) | 64 @@ -30,12 +28,6 @@ #include "stm32g0xx.h" #include "mbed_error.h" -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. - This value must be a multiple of 0x100. */ - #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) #define USE_PLL_HSI 0x2 // Use HSI internal clock @@ -92,39 +84,7 @@ void SetSysClock(void) /******************************************************************************/ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - - /** Configure the main internal regulator output voltage - */ - HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1; - RCC_OscInitStruct.PLL.PLLN = 16; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2; - RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - return 0; // FAIL - } - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - return 0; // FAIL - } - - return 1; // OK + return 0; } #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/cmsis_nvic.h index 2c994fd383..6f590036b5 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/cmsis_nvic.h @@ -22,10 +22,11 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x4000 - // 0x4000 STM32G031F4Px STM32G031J4Mx STM32G031C4Ux STM32G031K4Tx STM32G031G4Ux STM32G031C4Tx STM32G031K4Ux - // 0x8000 STM32G031F6Px STM32G031C6Tx STM32G031G6Ux STM32G031K6Tx STM32G031C6Ux STM32G031J6Mx STM32G031K6Ux - // 0x10000 STM32G031K8Tx STM32G031G8Ux STM32G031C8Tx STM32G031K8Ux STM32G031C8Ux STM32G031Y8Yx STM32G031F8Px +#if defined (TARGET_NUCLEO_G031K8) +#define MBED_ROM_SIZE 0x10000 // 64 KB +#else +#error "MBED_ROM_SIZE not defined" +#endif #endif #if !defined(MBED_RAM_START) @@ -33,10 +34,10 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x2000 +#define MBED_RAM_SIZE 0x2000 // 8 KB #endif -#define NVIC_NUM_VECTORS 46 +#define NVIC_NUM_VECTORS 48 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h index 90dd67406a..02e1da1b2e 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h @@ -40,7 +40,7 @@ #define MBED_RAM_SIZE 0x9000 #endif -#define NVIC_NUM_VECTORS 47 +#define NVIC_NUM_VECTORS 48 #define NVIC_RAM_VECTOR_ADDRESS MBED_RAM_START #endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/serial_device.c b/targets/TARGET_STM/TARGET_STM32G0/serial_device.c index 4e586550fa..288fbbd297 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32G0/serial_device.c @@ -17,11 +17,11 @@ #include "serial_api_hal.h" -#define UART_NUM (5) -// Retarget this IRQn symbol for chips without USART3/4 -#if defined(STM32G031xx) -#define USART3_4_LPUART1_IRQn LPUART1_IRQn +#if defined (STM32G031xx) +#define UART_NUM (3) +#else +#define UART_NUM (5) #endif uint32_t serial_irq_ids[UART_NUM] = {0}; @@ -143,7 +143,11 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) #if defined(LPUART1_BASE) if (obj_s->uart == LPUART_1) { +#if defined(STM32G031xx) + irq_n = LPUART1_IRQn; +#else irq_n = USART3_4_LPUART1_IRQn; +#endif vector = (uint32_t)&lpuart1_irq; } #endif @@ -162,19 +166,13 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) if (irq == RxIrq) { __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); // Check if TxIrq is disabled too -#if defined(STM32G0) -#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE -#endif - if ((huart->Instance->CR1 & USART_CR1_TXEIE) == 0) { + if ((huart->Instance->CR1 & USART_CR1_TXEIE_TXFNFIE) == 0) { all_disabled = 1; } } else { // TxIrq __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); // Check if RxIrq is disabled too -#if defined(STM32G0) -#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE -#endif - if ((huart->Instance->CR1 & USART_CR1_RXNEIE) == 0) { + if ((huart->Instance->CR1 & USART_CR1_RXNEIE_RXFNEIE) == 0) { all_disabled = 1; } } @@ -339,7 +337,11 @@ static IRQn_Type serial_get_irq_n(UARTName uart_name) #if defined(LPUART1_BASE) case LPUART_1: +#if defined(STM32G031xx) + irq_n = LPUART1_IRQn; +#else irq_n = USART3_4_LPUART1_IRQn; +#endif break; #endif default: diff --git a/targets/targets.json b/targets/targets.json index 6f3012db7d..eb974f70f5 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2368,6 +2368,27 @@ "MPU" ] }, + "MCU_STM32G031xx": { + "inherits": [ + "MCU_STM32G0" + ], + "public": false, + "extra_labels_add": [ + "STM32G031xx" + ], + "macros_add": [ + "STM32G031xx" + ] + }, + "NUCLEO_G031K8": { + "inherits": [ + "MCU_STM32G031xx" + ], + "detect_code": [ + "0852" + ], + "device_name": "STM32G031K8Tx" + }, "MCU_STM32G071xx": { "inherits": [ "MCU_STM32G0" @@ -2403,30 +2424,6 @@ ], "device_name": "STM32G071RBTx" }, - "MCU_STM32G031xx": { - "inherits": [ - "MCU_STM32G0" - ], - "public": false, - "extra_labels_add": [ - "STM32G031xx" - ], - "macros_add": [ - "STM32G031xx" - ], - "device_has_remove": [ - "ANALOGOUT" - ] - }, - "NUCLEO_G031K8": { - "inherits": [ - "MCU_STM32G031xx" - ], - "detect_code": [ - "0852" - ], - "device_name": "STM32G031K8Tx" - }, "MCU_STM32G4": { "inherits": [ "MCU_STM32" From c569dcce79de6109aeea909216d49999d723ab39 Mon Sep 17 00:00:00 2001 From: George Beckstein Date: Thu, 13 Aug 2020 16:50:03 -0400 Subject: [PATCH 6/9] Removed const from register declaration --- .../STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h index d220592e90..dff7098db2 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h @@ -3074,7 +3074,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t Backup */ __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister) { - const register __IO uint32_t *tmp; + register __IO uint32_t *tmp; tmp = &(TAMPx->BKP0R) + BackupRegister; From 470ef492b309c0eaf413e5a8333b4c347433fc3d Mon Sep 17 00:00:00 2001 From: George Beckstein Date: Fri, 14 Aug 2020 12:03:25 -0400 Subject: [PATCH 7/9] Revert "Removed const from register declaration" This reverts commit c569dcce79de6109aeea909216d49999d723ab39. --- .../STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h index dff7098db2..d220592e90 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32G0/STM32Cube_FW/STM32G0xx_HAL_Driver/stm32g0xx_ll_rtc.h @@ -3074,7 +3074,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t Backup */ __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister) { - register __IO uint32_t *tmp; + const register __IO uint32_t *tmp; tmp = &(TAMPx->BKP0R) + BackupRegister; From 167241a9dfcad6354f3a19660c1a4f57942f7db5 Mon Sep 17 00:00:00 2001 From: George Beckstein Date: Mon, 24 Aug 2020 08:52:40 -0400 Subject: [PATCH 8/9] Limit NUCLEO_G031K8 to bare-metal builds due to memory constraints --- targets/targets.json | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index eb974f70f5..9a6aff3917 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2387,7 +2387,24 @@ "detect_code": [ "0852" ], - "device_name": "STM32G031K8Tx" + "device_name": "STM32G031K8Tx", + "supported_c_libs": { + "arm": [ + "std", + "small" + ], + "gcc_arm": [ + "std", + "small" + ], + "iar": [ + "std" + ] + }, + "c_lib": "small", + "supported_application_profiles": [ + "bare-metal" + ] }, "MCU_STM32G071xx": { "inherits": [ From 5b3eb52f0969b873f03d404c765edb28d63e4a13 Mon Sep 17 00:00:00 2001 From: George Beckstein Date: Tue, 25 Aug 2020 09:20:03 -0400 Subject: [PATCH 9/9] Fix indentation within G031K8 definition --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 9a6aff3917..46c1e67f0a 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2388,7 +2388,7 @@ "0852" ], "device_name": "STM32G031K8Tx", - "supported_c_libs": { + "supported_c_libs": { "arm": [ "std", "small"