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Updated cypress target code with latest configurator and PDL 

library (1.4.0).
pull/12167/head
Dustin Crossman 2019-12-16 12:49:19 -08:00
parent c374f529a1
commit af5abae283
64 changed files with 77 additions and 119 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -5,7 +5,7 @@
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
View File

@ -5,7 +5,7 @@
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
View File

@ -5,7 +5,7 @@
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -5,7 +5,7 @@
* Clock configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -5,7 +5,7 @@
* Clock configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
View File

@ -6,7 +6,7 @@
* design.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -5,7 +5,7 @@
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -5,7 +5,7 @@
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -5,7 +5,7 @@
* Pin configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -5,7 +5,7 @@
* Pin configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
View File

@ -5,7 +5,7 @@
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

14
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -5,7 +5,7 @@
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -38,13 +38,13 @@ void init_cycfg_routing(void);
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_AMUXB
#if defined(__cplusplus)

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -5,7 +5,7 @@
* System configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
@ -242,14 +242,14 @@ __STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#else /* Dedicated Supply */
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
#endif /* CY_CFG_SYSCLK_ILO_ENABLED */
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* Configure core regulator */

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -5,7 +5,7 @@
* System configuration
* This file was automatically generated and should not be modified.
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../psoc6pdl): 1.3.1.1499
* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.4.0.1889
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3">
<Design version="12" xmlns="http://cypress.com/xsd/cydesignfile_v3">
<ToolInfo version="1.0.0"/>
<Devices>
<Device mpn="CY8C6245LQI-S3D72">

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -4,7 +4,7 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
View File

@ -4,7 +4,7 @@
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
View File

@ -4,7 +4,7 @@
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -4,7 +4,7 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -4,7 +4,7 @@
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
View File

@ -5,7 +5,7 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -4,7 +4,7 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -4,7 +4,7 @@
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************
@ -38,7 +38,7 @@ extern "C" {
#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 50000000u
#define CY_CAPSENSE_PERI_CLK 100000000u
#define CY_CAPSENSE_VDDA_MV 3300u
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
#define CY_CAPSENSE_PERI_DIV_INDEX 0u

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -4,7 +4,7 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -4,7 +4,7 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
View File

@ -4,7 +4,7 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -4,7 +4,7 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************
@ -42,12 +42,12 @@ void init_cycfg_routing(void);
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -4,7 +4,7 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************
@ -226,7 +226,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPath5Init()
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkPeriSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_Pll1Init()
{

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -4,7 +4,7 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

29
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -75,15 +75,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[0].pin[4]"/>
<Block location="ioss[0].port[11].pin[2]"/>
<Block location="ioss[0].port[11].pin[3]"/>
<Block location="ioss[0].port[11].pin[4]"/>
<Block location="ioss[0].port[11].pin[5]"/>
<Block location="ioss[0].port[11].pin[6]"/>
<Block location="ioss[0].port[11].pin[7]"/>
<Block location="ioss[0].port[14].pin[0]"/>
<Block location="ioss[0].port[14].pin[1]"/>
<Block location="ioss[0].port[1].pin[0]">
<Alias value="CYBSP_CSD_TX"/>
<Personality template="mxs40pin" version="1.1">
@ -97,15 +88,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[3].pin[0]"/>
<Block location="ioss[0].port[3].pin[1]"/>
<Block location="ioss[0].port[3].pin[2]"/>
<Block location="ioss[0].port[3].pin[3]"/>
<Block location="ioss[0].port[3].pin[4]"/>
<Block location="ioss[0].port[3].pin[5]"/>
<Block location="ioss[0].port[4].pin[0]"/>
<Block location="ioss[0].port[6].pin[0]"/>
<Block location="ioss[0].port[6].pin[1]"/>
<Block location="ioss[0].port[6].pin[4]">
<Alias value="CYBSP_SWO"/>
<Personality template="mxs40pin" version="1.1">
@ -275,7 +257,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_16[0]"/>
<Block location="peri[0].div_8[0]">
<Alias value="CYBSP_CSD_CLK_DIV"/>
<Personality template="mxs40peripheralclock" version="1.0">
@ -284,11 +265,6 @@
<Param id="startOnReset" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_8[1]"/>
<Block location="peri[0].div_8[3]"/>
<Block location="scb[2]"/>
<Block location="scb[3]"/>
<Block location="smif[0]"/>
<Block location="srss[0].clock[0]">
<Personality template="mxs40sysclocks" version="1.2"/>
</Block>
@ -379,7 +355,7 @@
</Block>
<Block location="srss[0].clock[0].periclk[0]">
<Personality template="mxs40periclk" version="1.0">
<Param id="divider" value="2"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pll[1]">
@ -405,7 +381,6 @@
<Param id="accuracyPpm" value="150"/>
</Personality>
</Block>
<Block location="srss[0].mcwdt[0]"/>
<Block location="srss[0].power[0]">
<Personality template="mxs40power" version="1.2">
<Param id="pwrMode" value="LDO_1_1"/>
@ -423,8 +398,6 @@
<Param id="vddio1Mv" value="3300"/>
</Personality>
</Block>
<Block location="srss[0].rtc[0]"/>
<Block location="usb[0]"/>
</BlockConfig>
<Netlist>
<Net>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -4,7 +4,7 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
View File

@ -4,7 +4,7 @@
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp
View File

@ -4,7 +4,7 @@
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h
View File

@ -5,7 +5,7 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -4,7 +4,7 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -4,7 +4,7 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
View File

@ -4,7 +4,7 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -4,7 +4,7 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -4,7 +4,7 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************
@ -203,7 +203,7 @@ __STATIC_INLINE void Cy_SysClk_ClkPath4Init()
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkPeriSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_Pll0Init()
{

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -4,7 +4,7 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
* cfg-backend-cli: 1.2.0.1478
* Device Configurator: 2.0.0.1483
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
*
********************************************************************************

17
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -36,12 +36,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[11].pin[2]"/>
<Block location="ioss[0].port[11].pin[3]"/>
<Block location="ioss[0].port[11].pin[4]"/>
<Block location="ioss[0].port[11].pin[5]"/>
<Block location="ioss[0].port[11].pin[6]"/>
<Block location="ioss[0].port[11].pin[7]"/>
<Block location="ioss[0].port[12].pin[6]">
<Alias value="CYBSP_ECO_IN"/>
<Personality template="mxs40pin" version="1.1">
@ -68,10 +62,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="ioss[0].port[14].pin[0]"/>
<Block location="ioss[0].port[14].pin[1]"/>
<Block location="ioss[0].port[6].pin[0]"/>
<Block location="ioss[0].port[6].pin[1]"/>
<Block location="ioss[0].port[6].pin[4]">
<Alias value="CYBSP_SWO"/>
<Personality template="mxs40pin" version="1.1">
@ -111,10 +101,6 @@
<Param id="inFlash" value="true"/>
</Personality>
</Block>
<Block location="peri[0].div_16[0]"/>
<Block location="peri[0].div_8[1]"/>
<Block location="scb[3]"/>
<Block location="smif[0]"/>
<Block location="srss[0].clock[0]">
<Personality template="mxs40sysclocks" version="1.2"/>
</Block>
@ -194,7 +180,7 @@
</Block>
<Block location="srss[0].clock[0].periclk[0]">
<Personality template="mxs40periclk" version="1.0">
<Param id="divider" value="2"/>
<Param id="divider" value="1"/>
</Personality>
</Block>
<Block location="srss[0].clock[0].pll[0]">
@ -237,7 +223,6 @@
<Param id="vddio1Mv" value="3300"/>
</Personality>
</Block>
<Block location="usb[0]"/>
</BlockConfig>
<Netlist>
<Net>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -441,7 +441,7 @@
</Mux>
</Netlist>
</Device>
<Device mpn="CYW43012TC0KFFBH">
<Device mpn="CYW43012TC0EKUBG">
<BlockConfig/>
<Netlist/>
</Device>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp.c
View File

@ -85,7 +85,7 @@ cy_rslt_t cybsp_init(void)
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
init_cycfg_all();
#endif

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/cybsp.h
View File

@ -26,7 +26,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(COMPONENT_BSP_DESIGN_MODUS)
#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
#include "cycfg.h"
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)