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Merge pull request #14746 from jeromecoutant/PR_WB15CC 

STM32WB: introduce STM32WB15CC NUCLEO
pull/14760/head
Martin Kojtal 2021-06-10 14:16:10 +02:00 committed by GitHub
parent b74f62c974 1a370ed02a
commit aeaac0e70c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
20 changed files with 711 additions and 516 deletions
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18
connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/HCIDriver.cpp
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@ -84,7 +84,9 @@ static bool get_bd_address(uint8_t *bd_addr);
static bool sysevt_wait(void);
static bool sysevt_check(void);
#if DEVICE_FLASH
extern int BLE_inited;
#endif
namespace ble {
namespace vendor {
@ -490,6 +492,20 @@ public:
tr_info("WIRELESS COPROCESSOR FW VERSION ID = %d.%d.%d", p_wireless_info->VersionMajor, p_wireless_info->VersionMinor, p_wireless_info->VersionSub);
tr_info("WIRELESS COPROCESSOR FW STACK TYPE = %d (ROM size 0x%x)", p_wireless_info->StackType, MBED_ROM_SIZE);
#if STM32WB15xx
switch (p_wireless_info->StackType) {
case INFO_STACK_TYPE_BLE_FULL:
error("Wrong BLE FW\n");
break;
case INFO_STACK_TYPE_BLE_HCI:
if (MBED_ROM_SIZE > 0x32800) {
error("Wrong MBED_ROM_SIZE with HCI FW\n");
}
break;
default:
tr_error("StackType %u not expected\n", p_wireless_info->StackType);
}
#endif
#if STM32WB55xx
switch (p_wireless_info->StackType) {
case INFO_STACK_TYPE_BLE_FULL:
@ -681,8 +697,10 @@ private:
*/
SHCI_C2_BLE_Init(&ble_init_cmd_packet);
#if DEVICE_FLASH
/* Used in flash_api.c */
BLE_inited = 1;
#endif
}
TL_CmdPacket_t *bleCmdBuf;

16
targets/TARGET_STM/TARGET_STM32WB/PeripheralNames.h
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@ -35,28 +35,42 @@ typedef enum {
#define DEVICE_SPI_COUNT 2
typedef enum {
SPI_1 = (int)SPI1_BASE,
SPI_2 = (int)SPI2_BASE
#if defined SPI2_BASE
SPI_2 = (int)SPI2_BASE,
#endif
} SPIName;
typedef enum {
I2C_1 = (int)I2C1_BASE,
#if defined I2C3_BASE
I2C_3 = (int)I2C3_BASE
#endif
} I2CName;
typedef enum {
PWM_1 = (int)TIM1_BASE,
#if defined TIM2_BASE
PWM_2 = (int)TIM2_BASE,
#endif
#if defined TIM16_BASE
PWM_16 = (int)TIM16_BASE,
#endif
#if defined TIM17_BASE
PWM_17 = (int)TIM17_BASE
#endif
} PWMName;
#if defined QUADSPI_R_BASE
typedef enum {
QSPI_1 = (int)QUADSPI_R_BASE
} QSPIName;
#endif
#if defined USB_BASE
typedef enum {
USB_FS = (int)USB_BASE,
} USBName;
#endif
#ifdef __cplusplus
}

40
targets/TARGET_STM/TARGET_STM32WB/README.md
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@ -72,6 +72,33 @@ mbedls -m 0884:DISCO_WB5MMG
```
## NUCLEO_WB15CC (NUCLEO-WB15CC)
[st.com STM32WB15CC module page](https://www.st.com/en/microcontrollers-microprocessors/stm32wb15cc.html)
[st.com NUCLEO board page]()
[mbed.com platform page](https://os.mbed.com/platforms/ST-NUCLEO-WB15CC/)
- Total FLASH is 320KB
But FLASH is shared by M4 and M0 cores, [see BLE FW](#ble-fw)
- RAM: 48 KB
- SRAM1: 12 KB
- SRAM2a: 32 KB
- SRAM2b: 4 KB
SRAM1 is dedicated for M4 core, and then for mbed-os applications.
SRAM2 is dedicated for M0 core and inter CPU communication, and some part can not be addressed by M4.
NB: MBED CLI1 tool can be used thanks to this command:
```
mbedls -m 0883:NUCLEO_WB15CC
```
# BLE
## MBED-OS support
@ -90,6 +117,8 @@ Official ST Application Note :
All available BLE FW for M0 core are provided in ths ST STM32CubeWB repo:
### STM32WB5x
https://github.com/STMicroelectronics/STM32CubeWB/tree/master/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x
Default BLE FW in ST boards is **stm32wb5x_BLE_Stack_full_fw.bin**
@ -108,6 +137,17 @@ Example in your local mbed_app.json:
}
```
### STM32WB1x
https://github.com/STMicroelectronics/STM32CubeWB/tree/master/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB1x
Default BLE FW in ST boards is **stm32wb1x_BLE_Stack_full_fw.bin**
- **this is not supported in mbed**
It is mandatory to use **stm32wb1x_BLE_HCILayer_fw.bin**
- As explained in Release_Notes.html, this FW is flashed at @ 0x08032800
- Then "mbed_rom_size" is "0x32800" (202K) (default configuration in targets.json)
## BLE FW update

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/app_conf.h
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@ -148,7 +148,11 @@
* Maximum number of simultaneous connections that the device will support.
* Valid values are from 1 to 8
*/
#ifdef TARGET_MCU_STM32WB15xC
#define CFG_BLE_NUM_LINK 4
#else
#define CFG_BLE_NUM_LINK 8
#endif
/**
* Maximum number of Services that can be stored in the GATT database.

4
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/stm32_lpm_if.c
View File

@ -122,7 +122,11 @@ void PWR_EnterStopMode( void )
/************************************************************************************
* ENTER STOP MODE
***********************************************************************************/
#if defined(PWR_SUPPORT_STOP2)
LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 );
#else
LL_PWR_SetPowerMode( LL_PWR_MODE_STOP1 );
#endif
LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */

3
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/CMakeLists.txt
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@ -1,6 +1,8 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_subdirectory(TARGET_NUCLEO_WB15CC EXCLUDE_FROM_ALL)
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wb15xx.S)
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wb15xc.ld)
@ -19,6 +21,7 @@ target_include_directories(mbed-stm32wb15xc
target_sources(mbed-stm32wb15xc
INTERFACE
${STARTUP_FILE}
system_clock.c
)
mbed_set_linker_script(mbed-stm32wb15xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})

16
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/CMakeLists.txt Normal file
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@ -0,0 +1,16 @@
# Copyright (c) 2020 ARM Limited. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
add_library(mbed-nucleo-wb15cc INTERFACE)
target_sources(mbed-nucleo-wb15cc
INTERFACE
PeripheralPins.c
)
target_include_directories(mbed-nucleo-wb15cc
INTERFACE
.
)
target_link_libraries(mbed-nucleo-wb15cc INTERFACE mbed-stm32wb15xc)

168
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/PeripheralPins.c Normal file
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@ -0,0 +1,168 @@
/* mbed Microcontroller Library
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
*
* Copyright (c) 2016-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*
* Automatically generated from STM32CubeMX/db/mcu/STM32WB15CCUx.xml
*/
#include "PeripheralPins.h"
#include "mbed_toolchain.h"
//==============================================================================
// Notes
//
// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
// HW peripheral instances. You can use them the same way as any other "normal"
// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
// pinout image on mbed.org.
//
// - The pins which are connected to other components present on the board have
// the comment "Connected to xxx". The pin function may not work properly in this
// case. These pins may not be displayed on the board pinout image on mbed.org.
// Please read the board reference manual and schematic for more information.
//
// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
//
//==============================================================================
//*** ADC ***
MBED_WEAK const PinMap PinMap_ADC[] = {
{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to B1 [Push Button]
{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
{PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
{PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to B3 [Push Button]
{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
{PA_8, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
// {PA_9, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to STDIO_UART_TX
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
{NC, NC, 0}
};
//*** I2C ***
MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
// {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_RX
{PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
// {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_TX
{PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
{NC, NC, 0}
};
//*** PWM ***
// TIM2 cannot be used because already used by the us_ticker
// (update us_ticker_data.h file if another timer is chosen)
MBED_WEAK const PinMap PinMap_PWM[] = {
// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to B1 [Push Button]
// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to STDIO_UART_TX
// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to STDIO_UART_RX
{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to JTDO
{PB_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM1, 3, 0)}, // TIM1_CH3
{PB_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
{PB_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
{NC, NC, 0}
};
//*** SERIAL ***
MBED_WEAK const PinMap PinMap_UART_TX[] = {
{PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX
{PB_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD1 [Blue Led]
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RX[] = {
{PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX
{PA_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD3 [Red Led]
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to JTDO
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
{PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to B3 [Push Button]
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{NC, NC, 0}
};
//*** SPI ***
MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_SPI1)},
{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to JTMS
{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD1 [Blue Led]
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to B3 [Push Button]
{PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
{PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to JTDO
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PA_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to JTCK
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_2, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{PB_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
{NC, NC, 0}
};

138
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/PinNames.h Normal file
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@ -0,0 +1,138 @@
/* mbed Microcontroller Library
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
*
* Copyright (c) 2016-2021 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*
* Automatically generated from STM32CubeMX/db/mcu/STM32WB15CCUx.xml
*/
/* MBED TARGET LIST: NUCLEO_WB15CC */
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#include "PinNamesTypes.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PA_0 = 0x00,
PA_1 = 0x01,
PA_2 = 0x02,
PA_3 = 0x03,
PA_4 = 0x04,
PA_5 = 0x05,
PA_6 = 0x06,
PA_7 = 0x07,
PA_8 = 0x08,
PA_9 = 0x09,
PA_10 = 0x0A,
PA_11 = 0x0B,
PA_12 = 0x0C,
PA_13 = 0x0D,
PA_14 = 0x0E,
PA_15 = 0x0F,
PB_0 = 0x10,
PB_1 = 0x11,
PB_2 = 0x12,
PB_3 = 0x13,
PB_4 = 0x14,
PB_5 = 0x15,
PB_6 = 0x16,
PB_7 = 0x17,
PB_8 = 0x18,
PB_9 = 0x19,
PC_14 = 0x2E,
PC_15 = 0x2F,
PE_4 = 0x44,
PH_3 = 0x73,
/**** ADC internal channels ****/
ADC_TEMP = 0xF0, // Internal pin virtual value
ADC_VREF = 0xF1, // Internal pin virtual value
ADC_VBAT = 0xF2, // Internal pin virtual value
#ifdef TARGET_FF_ARDUINO_UNO
// Arduino Uno (Rev3) pins
ARDUINO_UNO_A0 = PA_4,
ARDUINO_UNO_A1 = PA_6,
ARDUINO_UNO_A2 = PA_1,
ARDUINO_UNO_A3 = PA_0,
ARDUINO_UNO_A4 = PA_2,
ARDUINO_UNO_A5 = PA_3,
ARDUINO_UNO_D0 = PB_7,
ARDUINO_UNO_D1 = PB_6,
ARDUINO_UNO_D2 = PB_0,
ARDUINO_UNO_D3 = PA_12,
ARDUINO_UNO_D4 = PB_1,
ARDUINO_UNO_D5 = PA_11,
ARDUINO_UNO_D6 = PA_8,
ARDUINO_UNO_D7 = PE_4,
ARDUINO_UNO_D8 = PB_5,
ARDUINO_UNO_D9 = PA_15,
ARDUINO_UNO_D10 = PB_2,
ARDUINO_UNO_D11 = PA_7,
ARDUINO_UNO_D12 = PB_4,
ARDUINO_UNO_D13 = PA_5,
ARDUINO_UNO_D14 = PB_9,
ARDUINO_UNO_D15 = PB_8,
#endif
// STDIO for console print
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX,
#else
CONSOLE_TX = PA_9,
#endif
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX,
#else
CONSOLE_RX = PA_10,
#endif
/**** OSCILLATOR pins ****/
RCC_OSC32_IN = PC_14,
RCC_OSC32_OUT = PC_15,
/**** DEBUG pins ****/
SYS_JTCK_SWCLK = PA_14,
SYS_JTDI = PA_15,
SYS_JTDO_SWO = PB_3,
SYS_JTMS_SWDIO = PA_13,
SYS_JTRST = PB_4,
SYS_PVD_IN = PB_7,
SYS_WKUP1 = PA_0,
SYS_WKUP4 = PA_2,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
// Standardized LED and button names
#define LED1 PB_5 // LD1 [Blue Led]
#define LED2 PB_0 // LD2 [Green Led]
#define LED3 PB_1 // LD3 [Red Led]
#define BUTTON1 PA_0 // B1 [Push Button]
#define BUTTON2 PE_4 // B2 [Push Button]
#define BUTTON3 PA_6 // B3 [Push Button]
#ifdef __cplusplus
}
#endif
#endif

17
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_ARM/stm32wb15xc.sct
View File

@ -22,7 +22,9 @@
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
// MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH
// Size is defined in json with "mbed_rom_size"
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
@ -37,6 +39,7 @@
/* Round up VECTORS_SIZE to 8 bytes */
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
; RAM_SIZE = 12KB SRAM (0x3000) + Shared mem (part of SRAM2)
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE {
@ -49,9 +52,17 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE {
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + 0x3000 - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
}
ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
ARM_LIB_STACK (MBED_RAM_START + 0x3000) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
}
; SRAM2 - Shared memory
RW_IRAM2 0x20030000 0x2800 { ; RW data
*(MAPPING_TABLE)
*(MB_MEM1)
*(MB_MEM2)
}
}

25
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_GCC_ARM/stm32wb15xc.ld
View File

@ -23,7 +23,9 @@
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
/* MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH */
/* Size is defined in json with "mbed_rom_size" */
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
@ -35,10 +37,12 @@
/* Round up VECTORS_SIZE to 8 bytes */
#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
/* RAM_SIZE = 12KB SRAM (0x3000) + Shared mem (part of SRAM2) */
MEMORY
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE
{
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = 0x3000 - VECTORS_SIZE
RAM2 (rw) : ORIGIN = 0x20030000, LENGTH = 10K
}
/* Linker script to place sections and symbol values. Should be used together
@ -191,6 +195,19 @@ SECTIONS
*(.stack*)
} > RAM
.ble_stby_mem (NOLOAD) :
{
*(MAPPING_TABLE);
*(MB_MEM1);
} >RAM2
.ble_shared_no_ret (NOLOAD) :
{
_sMB_MEM2 = . ;
*(MB_MEM2);
_eMB_MEM2 = . ;
} >RAM2
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);

432
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_IAR/startup_stm32wb15xx.S
View File

@ -1,432 +0,0 @@
;******************************************************************************
;* File Name : startup_stm32wb15xx_cm4.s
;* Author : MCD Application Team
;* Description : M4 core vector table of the STM32WB15xx devices for the
;* IAR (EWARM) toolchain.
;*
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
;* All rights reserved.</center></h2>
;*
;* This software component is licensed by ST under Apache License, Version 2.0,
;* the "License"; You may not use this file except in compliance with the
;* License. You may obtain a copy of the License at:
;* opensource.org/licenses/Apache-2.0
;*
;******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
DCD FLASH_IRQHandler ; FLASH global Interrupt
DCD RCC_IRQHandler ; RCC Interrupt
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
DCD ADC1_IRQHandler ; ADC1 Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
DCD COMP_IRQHandler ; COMP1 Interrupts
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
DCD PKA_IRQHandler ; PKA Interrupt
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1 Interrupt
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1 Interrupt
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
DCD 0 ; Reserved
DCD TSC_IRQHandler ; TSC Interrupt
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
DCD 0 ; Reserved
DCD PWR_SOTF_BLEACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
DCD HSEM_IRQHandler ; HSEM0 Interrupt
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD AES2_IRQHandler ; AES2 Interrupt
DCD RNG_IRQHandler ; RNG1 Interrupt
DCD FPU_IRQHandler ; FPU Interrupt
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_LSECSS_IRQHandler
B TAMP_STAMP_LSECSS_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK C2SEV_PWR_C2H_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
C2SEV_PWR_C2H_IRQHandler
B C2SEV_PWR_C2H_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_IRQHandler
B TIM1_BRK_IRQHandler
PUBWEAK TIM1_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_IRQHandler
B TIM1_UP_IRQHandler
PUBWEAK TIM1_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_IRQHandler
B TIM1_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK PKA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PKA_IRQHandler
B PKA_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK TSC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TSC_IRQHandler
B TSC_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK PWR_SOTF_BLEACT_RFPHASE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PWR_SOTF_BLEACT_RFPHASE_IRQHandler
B PWR_SOTF_BLEACT_RFPHASE_IRQHandler
PUBWEAK IPCC_C1_RX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_RX_IRQHandler
B IPCC_C1_RX_IRQHandler
PUBWEAK IPCC_C1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
IPCC_C1_TX_IRQHandler
B IPCC_C1_TX_IRQHandler
PUBWEAK HSEM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
HSEM_IRQHandler
B HSEM_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK AES2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AES2_IRQHandler
B AES2_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK DMAMUX1_OVR_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMAMUX1_OVR_IRQHandler
B DMAMUX1_OVR_IRQHandler
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

59
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_IAR/stm32wb15xc.icf
View File

@ -1,59 +0,0 @@
/* Linker script to configure memory regions.
*
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
* @attention
*
* Copyright (c) 2016-2020 STMicroelectronics.
* All rights reserved.
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Device specific values */
/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
define symbol VECTORS = 79; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
define symbol HEAP_SIZE = 0x1000;
/* Common - Do not change */
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = MBED_ROM_START;
}
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
}
if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
/* This value is normally defined by the tools
to 0x1000 for bare metal and 0x400 for RTOS */
define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
}
/* Round up VECTORS_SIZE to 8 bytes */
define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
define memory mem with size = 4G;
define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { };
define block HEAP with alignment = 8, size = HEAP_SIZE { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem: MBED_APP_START { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

6
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/cmsis_nvic.h
View File

@ -22,7 +22,9 @@
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x0 // 0 B
// MBED_ROM_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH
// Size is defined in json with "mbed_rom_size"
#error "mbed_rom_size is missing"
#endif
#if !defined(MBED_RAM_START)
@ -30,7 +32,7 @@
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x0 // 0 B
#define MBED_RAM_SIZE 0xC000 // 48 KB
#endif
#define NVIC_NUM_VECTORS 79

119
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/system_clock.c Normal file
View File

@ -0,0 +1,119 @@
/* mbed Microcontroller Library
* Copyright (c) 2019 ARM Limited
* Copyright (c) 2019 STMicroelectronics
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* This file configures the system clock as follows:
*-----------------------------------------------------------------------------
* System clock source | HSE (external 32 MHz clock)
*-----------------------------------------------------------------------------
* SYSCLK(MHz) | 32
* AHBCLK (MHz) | 32
* APB1CLK (MHz) | 32
* APB2CLK (MHz) | 32
* USB capable | YES
*-----------------------------------------------------------------------------
**/
#include "stm32wbxx.h"
#include "mbed_error.h"
#include "stm32wbxx_ll_hsem.h"
#include "otp.h"
static void Config_HSE(void)
{
OTP_ID0_t *p_otp;
/**
* Read HSE_Tuning from OTP
*/
p_otp = (OTP_ID0_t *) OTP_Read(0);
if (p_otp) {
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
}
return;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers
* @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
void SetSysClock(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
__HAL_RCC_HSEM_CLK_ENABLE();
/* This prevents the CPU2 (M0+) to configure RCC */
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
Config_HSE();
/* Initializes the CPU, AHB and APB busses clocks */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
error("HAL_RCC_OscConfig error\n");
}
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
error("HAL_RCC_ClockConfig error\n");
}
/* Initializes the peripherals clocks */
/* RNG needs to be configured like in M0 core, i.e. with HSI48 */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG ;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_LSE;
PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
error("HAL_RCCEx_PeriphCLKConfig error\n");
}
LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA);
LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40);
// LL_PWR_SMPS_Enable();
/* Select HSI as system clock source after Wake Up from Stop mode */
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
}

25
targets/TARGET_STM/TARGET_STM32WB/analogin_device.c
View File

@ -66,12 +66,19 @@ void analogin_init(analogin_t *obj, PinName pin)
obj->handle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig
obj->handle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled
obj->handle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled
obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled
obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; // Software start to trig the 1st conversion manually, without external event
obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
obj->handle.Init.DMAContinuousRequests = DISABLE;
obj->handle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; // DR register is overwritten with the last conversion result in case of overrun
#if defined (ADC_SUPPORT_2_5_MSPS)
obj->handle.Init.LowPowerAutoPowerOff = DISABLE;
obj->handle.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_79CYCLES_5;
obj->handle.Init.SamplingTimeCommon2 = ADC_SAMPLETIME_160CYCLES_5;
obj->handle.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
#else
obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled
obj->handle.Init.OversamplingMode = DISABLE; // No oversampling
#endif
// Enable ADC core clock
__HAL_RCC_ADC_CLK_ENABLE();
@ -96,15 +103,23 @@ uint16_t adc_read(analogin_t *obj)
// Configure ADC channel
sConfig.Rank = ADC_REGULAR_RANK_1;
#if !defined (ADC_SUPPORT_2_5_MSPS)
sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
#else
sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_1;
#endif
switch (obj->channel) {
case 0:
sConfig.Channel = ADC_CHANNEL_VREFINT;
#if !defined (ADC_SUPPORT_2_5_MSPS)
sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; // Minimum ADC sampling time when reading the internal reference voltage is 4us
#else
sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_2;
#endif
break;
case 1:
sConfig.Channel = ADC_CHANNEL_1;
@ -156,11 +171,19 @@ uint16_t adc_read(analogin_t *obj)
break;
case 17:
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
#if !defined (ADC_SUPPORT_2_5_MSPS)
sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; // Minimum ADC sampling time when reading the temperature is 5us
#else
sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_2;
#endif
break;
case 18:
sConfig.Channel = ADC_CHANNEL_VBAT;
#if !defined (ADC_SUPPORT_2_5_MSPS)
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5; // Minimum ADC sampling time when reading the VBAT is 12us
#else
sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_2;
#endif
break;
default:
return 0;

2
targets/TARGET_STM/TARGET_STM32WB/spi_api.c
View File

@ -45,9 +45,11 @@ int spi_get_clock_freq(spi_t *obj)
case SPI_1:
spi_hz = HAL_RCC_GetPCLK2Freq();
break;
#if defined SPI2_BASE
case SPI_2:
spi_hz = HAL_RCC_GetPCLK1Freq();
break;
#endif
default:
error("CLK: SPI instance not set");
break;

38
targets/TARGET_STM/TARGET_STM32WB/us_ticker_data.h
View File

@ -1,18 +1,16 @@
/* mbed Microcontroller Library
* Copyright (c) 2019 ARM Limited
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: BSD-3-Clause
******************************************************************************
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* Copyright (c) 2016-2021 STMicroelectronics.
* All rights reserved.
*
* http://www.apache.org/licenses/LICENSE-2.0
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************
*/
#ifndef __US_TICKER_DATA_H
@ -26,22 +24,34 @@ extern "C" {
#include "stm32wbxx_ll_tim.h"
#include "cmsis_nvic.h"
#if defined TIM16_BASE
#define TIM_MST TIM16
#define TIM_MST_IRQ TIM1_UP_TIM16_IRQn
#define TIM_MST_RCC __HAL_RCC_TIM16_CLK_ENABLE()
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM16()
#define TIM_MST_RESET_ON __HAL_RCC_TIM16_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM16_RELEASE_RESET()
#define TIM_MST_BIT_WIDTH 16 // 16 or 32
#define TIM_MST_PCLK 2 // Select the peripheral clock number (1 or 2)
#else
#define TIM_MST TIM2
#define TIM_MST_IRQ TIM2_IRQn
#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE()
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2()
#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET()
#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET()
#define TIM_MST_BIT_WIDTH 32 // 16 or 32
#endif
#define TIM_MST_PCLK 2 // Select the peripheral clock number (1 or 2)
#ifdef __cplusplus
}
#endif
#endif // __US_TICKER_DATA_H

32
targets/targets.json
View File

@ -4189,6 +4189,38 @@
"BLE"
]
},
"MCU_STM32WB15xC": {
"inherits": [
"MCU_STM32WB"
],
"public": false,
"supported_application_profiles": [
"bare-metal"
],
"c_lib": "small",
"extra_labels_add": [
"STM32WB15xC"
],
"mbed_rom_size": "0x32800",
"overrides": {
"boot-stack-size": "0x400"
},
"macros_add": [
"STM32WB15xx"
]
},
"NUCLEO_WB15CC": {
"inherits": [
"MCU_STM32WB15xC"
],
"supported_form_factors": [
"ARDUINO_UNO"
],
"detect_code": [
"0883"
],
"device_name": "STM32WB15CCUx"
},
"MCU_STM32WB55xG": {
"inherits": [
"MCU_STM32WB"

65
tools/arm_pack_manager/index.json
View File

@ -480223,6 +480223,71 @@
],
"sub_family": "STM32WL55"
},
"STM32WB15CCUx": {
"name": "STM32WB15CCUx",
"memories": {
"IROM1": {
"access": {
"read": true,
"write": false,
"execute": true,
"peripheral": false,
"secure": false,
"non_secure": false,
"non_secure_callable": false
},
"start": 134217728,
"size": 327680,
"startup": true,
"default": true
},
"IRAM1": {
"access": {
"read": true,
"write": true,
"execute": false,
"peripheral": false,
"secure": false,
"non_secure": false,
"non_secure_callable": false
},
"start": 536870912,
"size": 49152,
"startup": false,
"default": true
}
},
"algorithms": [
{
"file_name": "CMSIS/Flash/STM32WB_M4.FLM",
"start": 134217728,
"size": 1048576,
"default": true,
"ram_start": null,
"ram_size": null
}
],
"processor": {
"Symmetric": {
"units": 1,
"core": "CortexM4",
"fpu": "SinglePrecision",
"mpu": "Present"
}
},
"from_pack": {
"vendor": "Keil",
"pack": "STM32WBxx_DFP",
"version": "1.2.0",
"url": "http://www.keil.com/pack"
},
"sectors" : [
[ 134217728, 4096 ]
],
"vendor": "STMicroelectronics:13",
"family": "STM32WB Series",
"sub_family": "STM32WB15"
},
"STM32WB55CCUx": {
"name": "STM32WB55CCUx",
"memories": {