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Merge pull request #6818 from ARMmbed/release-candidate 

Release candidate for mbed-os-5.8.4
pull/6829/merge mbed-os-5.8.4
Cruz Monrreal 2018-05-07 10:57:26 -05:00 committed by GitHub
parent c05d72c3c0 09132ce8ce
commit ae6c7c60f9
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GPG Key ID: 4AEE18F83AFDEB23
271 changed files with 22854 additions and 16783 deletions
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18
.github/pull_request_template.md vendored
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@ -3,7 +3,7 @@
<!--
Required
Add here detailed changes summary, testing results, dependencies
Good example: https://os.mbed.com/docs/latest/reference/guidelines.html#workflow (Pull request template)
Good example: https://os.mbed.com/docs/latest/reference/workflow.html (Pull request template)
-->
@ -11,18 +11,14 @@
<!--
Required
Please add only one X to one of the following types. Do not fill multiple types (split the pull request otherwise) or
change the layout.
[X] Fix
Please add only one X to one of the following types. Do not fill multiple types (split the pull request otherwise).
Please note this is not a GitHub task list, indenting the boxes or changing the format to add a '.' or '*' in front
of them would change the meaning incorrectly. The only changes to be made are to add a description text under the
description heading and to add a 'x' to the correct box.
-->
[ ] Fix
[ ] Refactor
[ ] New target
[ ] Feature
[ ] Breaking change
-->
[ ] Fix
[ ] Refactor
[ ] New target
[ ] Feature
[ ] Breaking change

32
TESTS/host_tests/device_echo.py Normal file
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@ -0,0 +1,32 @@
"""
mbed SDK
Copyright (c) 2011-2016 ARM Limited
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
"""
import uuid
from mbed_host_tests import BaseHostTest
class Device_Echo(BaseHostTest):
def _callback_repeat(self, key, value, _):
self.send_kv(key, value)
def setup(self):
self.register_callback("echo", self._callback_repeat)
self.register_callback("echo_count", self._callback_repeat)
def teardown(self):
pass

39
TESTS/mbed_drivers/echo/main.cpp
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@ -21,28 +21,49 @@
#include "unity/unity.h"
#include "utest/utest.h"
#define PAYLOAD_LENGTH 36
using namespace utest::v1;
// Fill a buffer with a slice of the ASCII alphabet.
void fill_buffer(char* buffer, unsigned int length, unsigned int index) {
unsigned int start = length * index;
for (int i = 0; i < length - 1; i++) {
buffer[i] = 'a' + ((start + i) % 26);
}
buffer[length - 1] = '\0';
}
// Echo server (echo payload to host)
template<int N>
void test_case_echo_server_x() {
char _key[11] = {};
char _value[128] = {};
char _tx_value[PAYLOAD_LENGTH + 1] = {};
char _rx_value[PAYLOAD_LENGTH + 1] = {};
const int echo_count = N;
const char _key_const[] = "echo_count";
const char _echo_count_key_const[] = "echo_count";
const char _echo_key_const[] = "echo";
int expected_key = 1;
greentea_send_kv(_key_const, echo_count);
// Send up the echo count
greentea_send_kv(_echo_count_key_const, echo_count);
// Handshake with host
do {
greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
expected_key = strcmp(_key_const, _key);
greentea_parse_kv(_key, _rx_value, sizeof(_key), sizeof(_rx_value));
// Ensure the key received is "echo_count" and not some old data
expected_key = strcmp(_echo_count_key_const, _key);
} while (expected_key);
TEST_ASSERT_EQUAL_INT(echo_count, atoi(_value));
TEST_ASSERT_EQUAL_INT(echo_count, atoi(_rx_value));
for (int i=0; i < echo_count; ++i) {
greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value));
greentea_send_kv(_key, _value);
fill_buffer(_tx_value, PAYLOAD_LENGTH, i);
greentea_send_kv(_echo_key_const, _tx_value);
do {
greentea_parse_kv(_key, _rx_value, sizeof(_key), sizeof(_rx_value));
// Ensure the key received is "echo" and not some old data
expected_key = strcmp(_echo_key_const, _key);
} while (expected_key);
TEST_ASSERT(strncmp(_tx_value, _rx_value, PAYLOAD_LENGTH) == 0);
}
}
@ -56,7 +77,7 @@ Case cases[] = {
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {
GREENTEA_SETUP(30, "echo");
GREENTEA_SETUP(30, "device_echo");
return greentea_test_setup_handler(number_of_cases);
}

8
TESTS/mbed_hal/flash/functional_tests/main.cpp
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@ -28,7 +28,13 @@
using namespace utest::v1;
#define TEST_CYCLES 10000000
#ifdef TARGET_NRF52
/* The increased tolerance is to account for the imprecise timers on the NRF52. */
#define ALLOWED_DRIFT_PPM (1000000/50000) //5.0%
#else
#define ALLOWED_DRIFT_PPM (1000000/5000) //0.5%
#endif
/*
return values to be checked are documented at:
@ -279,9 +285,7 @@ Case cases[] = {
Case("Flash - erase sector", flash_erase_sector_test),
Case("Flash - program page", flash_program_page_test),
Case("Flash - buffer alignment test", flash_buffer_alignment_test),
#ifndef MCU_NRF52
Case("Flash - clock and cache test", flash_clock_and_cache_test),
#endif
};
utest::v1::status_t greentea_test_setup(const size_t number_of_cases) {

0
TESTS/mbed_drivers/stats/main.cpp → TESTS/mbed_platform/stats_heap/main.cpp
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1
doxygen_options.json
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@ -9,5 +9,6 @@
"PREDEFINED": "DOXYGEN_ONLY DEVICE_ANALOGIN DEVICE_ANALOGOUT DEVICE_CAN DEVICE_ETHERNET DEVICE_EMAC DEVICE_FLASH DEVICE_I2C DEVICE_I2CSLAVE DEVICE_I2C_ASYNCH DEVICE_INTERRUPTIN DEVICE_ITM DEVICE_LOWPOWERTIMER DEVICE_PORTIN DEVICE_PORTINOUT DEVICE_PORTOUT DEVICE_PWMOUT DEVICE_RTC DEVICE_TRNG DEVICE_SERIAL DEVICE_SERIAL_ASYNCH DEVICE_SERIAL_FC DEVICE_SLEEP DEVICE_SPI DEVICE_SPI_ASYNCH DEVICE_SPISLAVE DEVICE_STORAGE \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\" \"MBED_DEPRECATED(s)=\"",
"EXPAND_AS_DEFINED": "",
"SKIP_FUNCTION_MACROS": "NO",
"STRIP_CODE_COMMENTS": "NO",
"EXCLUDE_PATTERNS": "*/tools/* */targets/* */features/mbedtls/* */features/storage/* */features/unsupported/* */BUILD/* */rtos/TARGET_CORTEX/rtx*/* */cmsis/* */features/FEATURE_COMMON_PAL/* */features/FEATURE_LWIP/* */features/FEATURE_UVISOR/* */features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/* */features/nanostack/FEATURE_NANOSTACK/coap-service/* */ble/generic/* */ble/pal/*"
}

5
drivers/UARTSerial.cpp
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@ -305,12 +305,11 @@ void UARTSerial::rx_irq(void)
void UARTSerial::tx_irq(void)
{
bool was_full = _txbuf.full();
char data;
/* Write to the peripheral if there is something to write
* and if the peripheral is available to write. */
while (!_txbuf.empty() && SerialBase::writeable()) {
char data;
_txbuf.pop(data);
while (SerialBase::writeable() && _txbuf.pop(data)) {
SerialBase::_base_putc(data);
}

2
features/FEATURE_COMMON_PAL/nanostack-hal-mbed-cmsis-rtos/mbed_lib.json
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@ -6,7 +6,7 @@
"value": false
},
"event_loop_thread_stack_size": {
"help": "Define event-loop thread stack size.",
"help": "Define event-loop thread stack size. [bytes]",
"value": 6144
},
"critical-section-usable-from-interrupt": {

2
features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17_emac.c
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@ -611,7 +611,7 @@ static err_t lpc_low_level_output(struct netif *netif, struct pbuf *p)
/* Wait until enough descriptors are available for the transfer. */
/* THIS WILL BLOCK UNTIL THERE ARE ENOUGH DESCRIPTORS AVAILABLE */
#if NO_SYS == 0
for (idx = 0; idx < dn; idx++) {
for (s32_t count = 0; count < dn; count++) {
osSemaphoreAcquire(lpc_enetif->xTXDCountSem.id, osWaitForever);
}
MBED_ASSERT(dn <= lpc_tx_ready(netif));

100
features/filesystem/littlefs/littlefs/lfs.c
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@ -783,26 +783,19 @@ static int lfs_dir_find(lfs_t *lfs, lfs_dir_t *dir,
lfs_entry_t *entry, const char **path) {
const char *pathname = *path;
size_t pathlen;
entry->d.type = LFS_TYPE_DIR;
entry->d.elen = sizeof(entry->d) - 4;
entry->d.alen = 0;
entry->d.nlen = 0;
entry->d.u.dir[0] = lfs->root[0];
entry->d.u.dir[1] = lfs->root[1];
while (true) {
nextname:
nextname:
// skip slashes
pathname += strspn(pathname, "/");
pathlen = strcspn(pathname, "/");
// special case for root dir
if (pathname[0] == '\0') {
*entry = (lfs_entry_t){
.d.type = LFS_TYPE_DIR,
.d.elen = sizeof(entry->d) - 4,
.d.alen = 0,
.d.nlen = 0,
.d.u.dir[0] = lfs->root[0],
.d.u.dir[1] = lfs->root[1],
};
return 0;
}
// skip '.' and root '..'
if ((pathlen == 1 && memcmp(pathname, ".", 1) == 0) ||
(pathlen == 2 && memcmp(pathname, "..", 2) == 0)) {
@ -834,10 +827,25 @@ static int lfs_dir_find(lfs_t *lfs, lfs_dir_t *dir,
suffix += sufflen;
}
// found path
if (pathname[0] == '\0') {
return 0;
}
// update what we've found
*path = pathname;
// find path
// continue on if we hit a directory
if (entry->d.type != LFS_TYPE_DIR) {
return LFS_ERR_NOTDIR;
}
int err = lfs_dir_fetch(lfs, dir, entry->d.u.dir);
if (err) {
return err;
}
// find entry matching name
while (true) {
int err = lfs_dir_next(lfs, dir, entry);
if (err) {
@ -873,21 +881,8 @@ static int lfs_dir_find(lfs_t *lfs, lfs_dir_t *dir,
entry->d.type &= ~0x80;
}
// to next name
pathname += pathlen;
pathname += strspn(pathname, "/");
if (pathname[0] == '\0') {
return 0;
}
// continue on if we hit a directory
if (entry->d.type != LFS_TYPE_DIR) {
return LFS_ERR_NOTDIR;
}
int err = lfs_dir_fetch(lfs, dir, entry->d.u.dir);
if (err) {
return err;
}
}
}
@ -904,13 +899,8 @@ int lfs_mkdir(lfs_t *lfs, const char *path) {
// fetch parent directory
lfs_dir_t cwd;
int err = lfs_dir_fetch(lfs, &cwd, lfs->root);
if (err) {
return err;
}
lfs_entry_t entry;
err = lfs_dir_find(lfs, &cwd, &entry, &path);
int err = lfs_dir_find(lfs, &cwd, &entry, &path);
if (err != LFS_ERR_NOENT || strchr(path, '/') != NULL) {
return err ? err : LFS_ERR_EXIST;
}
@ -954,13 +944,8 @@ int lfs_dir_open(lfs_t *lfs, lfs_dir_t *dir, const char *path) {
dir->pair[0] = lfs->root[0];
dir->pair[1] = lfs->root[1];
int err = lfs_dir_fetch(lfs, dir, dir->pair);
if (err) {
return err;
}
lfs_entry_t entry;
err = lfs_dir_find(lfs, dir, &entry, &path);
int err = lfs_dir_find(lfs, dir, &entry, &path);
if (err) {
return err;
} else if (entry.d.type != LFS_TYPE_DIR) {
@ -1302,13 +1287,8 @@ int lfs_file_open(lfs_t *lfs, lfs_file_t *file,
// allocate entry for file if it doesn't exist
lfs_dir_t cwd;
int err = lfs_dir_fetch(lfs, &cwd, lfs->root);
if (err) {
return err;
}
lfs_entry_t entry;
err = lfs_dir_find(lfs, &cwd, &entry, &path);
int err = lfs_dir_find(lfs, &cwd, &entry, &path);
if (err && (err != LFS_ERR_NOENT || strchr(path, '/') != NULL)) {
return err;
}
@ -1814,13 +1794,8 @@ lfs_soff_t lfs_file_size(lfs_t *lfs, lfs_file_t *file) {
/// General fs operations ///
int lfs_stat(lfs_t *lfs, const char *path, struct lfs_info *info) {
lfs_dir_t cwd;
int err = lfs_dir_fetch(lfs, &cwd, lfs->root);
if (err) {
return err;
}
lfs_entry_t entry;
err = lfs_dir_find(lfs, &cwd, &entry, &path);
int err = lfs_dir_find(lfs, &cwd, &entry, &path);
if (err) {
return err;
}
@ -1855,13 +1830,8 @@ int lfs_remove(lfs_t *lfs, const char *path) {
}
lfs_dir_t cwd;
int err = lfs_dir_fetch(lfs, &cwd, lfs->root);
if (err) {
return err;
}
lfs_entry_t entry;
err = lfs_dir_find(lfs, &cwd, &entry, &path);
int err = lfs_dir_find(lfs, &cwd, &entry, &path);
if (err) {
return err;
}
@ -1916,24 +1886,14 @@ int lfs_rename(lfs_t *lfs, const char *oldpath, const char *newpath) {
// find old entry
lfs_dir_t oldcwd;
int err = lfs_dir_fetch(lfs, &oldcwd, lfs->root);
if (err) {
return err;
}
lfs_entry_t oldentry;
err = lfs_dir_find(lfs, &oldcwd, &oldentry, &oldpath);
int err = lfs_dir_find(lfs, &oldcwd, &oldentry, &oldpath);
if (err) {
return err;
}
// allocate new entry
lfs_dir_t newcwd;
err = lfs_dir_fetch(lfs, &newcwd, lfs->root);
if (err) {
return err;
}
lfs_entry_t preventry;
err = lfs_dir_find(lfs, &newcwd, &preventry, &newpath);
if (err && (err != LFS_ERR_NOENT || strchr(newpath, '/') != NULL)) {

16
features/filesystem/littlefs/littlefs/tests/test_paths.sh
View File

@ -90,6 +90,22 @@ tests/test.py << TEST
lfs_unmount(&lfs) => 0;
TEST
echo "--- Trailing dot path tests ---"
tests/test.py << TEST
lfs_mount(&lfs, &cfg) => 0;
lfs_stat(&lfs, "tea/hottea/", &info) => 0;
strcmp(info.name, "hottea") => 0;
lfs_stat(&lfs, "tea/hottea/.", &info) => 0;
strcmp(info.name, "hottea") => 0;
lfs_stat(&lfs, "tea/hottea/./.", &info) => 0;
strcmp(info.name, "hottea") => 0;
lfs_stat(&lfs, "tea/hottea/..", &info) => 0;
strcmp(info.name, "tea") => 0;
lfs_stat(&lfs, "tea/hottea/../.", &info) => 0;
strcmp(info.name, "tea") => 0;
lfs_unmount(&lfs) => 0;
TEST
echo "--- Root dot dot path tests ---"
tests/test.py << TEST
lfs_mount(&lfs, &cfg) => 0;

4
features/lorawan/lorastack/phy/LoRaPHY.cpp
View File

@ -888,9 +888,7 @@ bool LoRaPHY::tx_config(tx_config_params_t* tx_conf, int8_t* tx_power,
band_t *bands = (band_t *)phy_params.bands.table;
// limit TX power if set to too much
if (tx_conf->tx_power > bands[band_idx].max_tx_pwr) {
tx_conf->tx_power = bands[band_idx].max_tx_pwr;
}
tx_conf->tx_power = MAX(tx_conf->tx_power, bands[band_idx].max_tx_pwr);
uint8_t bandwidth = get_bandwidth(tx_conf->datarate);
int8_t phy_tx_power = 0;

30
features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json
View File

@ -2,15 +2,15 @@
"name": "mbed-mesh-api",
"config": {
"heap-size": {
"help": "Nanostack's heap size (bytes: 0-65534)",
"help": "Nanostack's heap size [bytes: 0-65534]",
"value": 32500
},
"use-malloc-for-heap": {
"help": "Use `malloc()` for reserving the internal heap.",
"help": "Use `malloc()` for reserving the Nanostack's internal heap.",
"value": false
},
"6lowpan-nd-channel-mask": {
"help": "Channel mask, bit mask of channels to use.",
"help": "Channel mask, bit-mask of channels to use. [0-0x07fff800]",
"value": "0x7fff800"
},
"6lowpan-nd-channel-page": {
@ -18,11 +18,11 @@
"value": 0
},
"6lowpan-nd-channel": {
"help": "RF channel to use when `channel_mask` is not defined (0-26).",
"help": "RF channel to use when `channel_mask` is not defined. [0-26].",
"value": 0
},
"6lowpan-nd-panid-filter": {
"help": "Beacon PAN ID filter, 0xffff means no filtering.",
"help": "Beacon PAN ID filter, 0xffff means no filtering. [0-0xffff]",
"value": "0xffff"
},
"6lowpan-nd-security-mode": {
@ -34,7 +34,7 @@
"value": 1
},
"6lowpan-nd-psk-key": {
"help": "Pre-shared network key.",
"help": "Pre-shared network key. Byte array of 16 bytes. In form of: {0x00, 0x11, ... 0xff}",
"value": "{0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf}"
},
"6lowpan-nd-sec-level": {
@ -54,7 +54,7 @@
"value": true
},
"thread-config-channel-mask": {
"help": "Channel mask, 0x7ffff800 scans all channels.",
"help": "Channel bit mask, 0x7ffff800 scans all channels. [0-0x07fff800]",
"value": "0x7fff800"
},
"thread-config-channel-page": {
@ -62,15 +62,15 @@
"value": 0
},
"thread-config-channel": {
"help": "RF channel to use. (11-26)",
"help": "RF channel to use. [11-26]",
"value": 22
},
"thread-config-panid": {
"help": "Network identifier (0-0xFFFF)",
"help": "Network identifier [0-0xFFFF]",
"value": "0x0700"
},
"thread-config-network-name": {
"help": "Network name (max 16 characters)",
"help": "Network name [string, max 16 characters]",
"value": "\"Thread Network\""
},
"thread-config-commissioning-dataset-timestamp": {
@ -78,19 +78,19 @@
"value": "0x10000"
},
"thread-config-extended-panid": {
"help": "Extended PAN ID.",
"help": "Extended PAN ID. [8 byte array]",
"value": "{0xf1, 0xb5, 0xa1, 0xb2,0xc4, 0xd5, 0xa1, 0xbd }"
},
"thread-master-key": {
"help": "Network master key.",
"help": "Network master key. [16 byte array]",
"value": "{0x10, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff}"
},
"thread-config-ml-prefix": {
"help": "Mesh Local prefix.",
"help": "Mesh Local prefix. [8 byte array]",
"value": "{0xfd, 0x0, 0x0d, 0xb8, 0x0, 0x0, 0x0, 0x0}"
},
"thread-config-pskc": {
"help": "Pre-Shared Key for the Commissioner.",
"help": "Pre-Shared Key for the Commissioner. [16 byte array]",
"value": "{0xc8, 0xa6, 0x2e, 0xae, 0xf3, 0x68, 0xf3, 0x46, 0xa9, 0x9e, 0x57, 0x85, 0x98, 0x9d, 0x1c, 0xd0}"
},
"thread-device-type": {
@ -98,7 +98,7 @@
"value": "MESH_DEVICE_TYPE_THREAD_ROUTER"
},
"thread-security-policy": {
"help": "Commissioning security policy bits (0-0xFF)",
"help": "Commissioning security policy bits [0-0xFF]",
"value": 255
}
}

5
features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/mbed_lib.json
View File

@ -1,7 +1,10 @@
{
"name": "nanostack",
"config": {
"configuration": "nanostack_full"
"configuration": {
"help": "Build time configuration. Refer to Handbook for valid values. Default: full stack",
"value": "nanostack_full"
}
},
"macros": ["NS_USE_EXTERNAL_MBED_TLS"]
}

131
features/nanostack/FEATURE_NANOSTACK/targets/TARGET_SL_RAIL/NanostackRfPhyEfr32.cpp
View File

@ -46,6 +46,13 @@
#define RF_QUEUE_SIZE 8
#endif
/* 802.15.4 maximum size of a single packet including PHY byte is 128 bytes */
#define MAC_PACKET_MAX_LENGTH 128
/* Offsets of prepended data in packet buffer */
#define MAC_PACKET_OFFSET_RSSI 0
#define MAC_PACKET_OFFSET_LQI 1
/* This driver prepends RSSI and LQI */
#define MAC_PACKET_INFO_LENGTH 2
/* RFThreadSignal used to signal from interrupts to the adaptor thread */
enum RFThreadSignal {
@ -68,12 +75,12 @@ enum RFThreadSignal {
/* Adaptor thread definitions */
static void rf_thread_loop(const void *arg);
static osThreadDef(rf_thread_loop, osPriorityRealtime, RF_THREAD_STACK_SIZE);
static osThreadId rf_thread_id;
static osThreadId rf_thread_id = 0;
/* Queue for passing messages from interrupt to adaptor thread */
static volatile void* rx_queue[8];
static volatile size_t rx_queue_head;
static volatile size_t rx_queue_tail;
static volatile uint8_t rx_queue[RF_QUEUE_SIZE][MAC_PACKET_MAX_LENGTH + MAC_PACKET_INFO_LENGTH];
static volatile size_t rx_queue_head = 0;
static volatile size_t rx_queue_tail = 0;
/* Silicon Labs headers */
extern "C" {
@ -123,7 +130,7 @@ static const RAIL_CsmaConfig_t csma_config = RAIL_CSMA_CONFIG_802_15_4_2003_2p4_
#error "Not a valid target."
#endif
#ifdef MBED_CONF_SL_RAIL_HAS_SUBGIG
#if MBED_CONF_SL_RAIL_HAS_SUBGIG
static RAIL_ChannelConfigEntryAttr_t entry_868;
static RAIL_ChannelConfigEntryAttr_t entry_915;
static const RAIL_ChannelConfigEntry_t entry[] = {
@ -151,7 +158,7 @@ static const RAIL_ChannelConfigEntry_t entry[] = {
#endif
#if MBED_CONF_SL_RAIL_BAND == 868
#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG
#if !MBED_CONF_SL_RAIL_HAS_SUBGIG
#error "Sub-Gigahertz band is not supported on this target."
#endif
static const RAIL_ChannelConfig_t channels = {
@ -161,7 +168,7 @@ static const RAIL_ChannelConfig_t channels = {
1
};
#elif MBED_CONF_SL_RAIL_BAND == 915
#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG
#if !MBED_CONF_SL_RAIL_HAS_SUBGIG
#error "Sub-Gigahertz band is not supported on this target."
#endif
static const RAIL_ChannelConfig_t channels = {
@ -187,7 +194,7 @@ static const RAIL_TxPowerConfig_t paInit2p4 = {
};
#endif
#if defined (MBED_CONF_SL_RAIL_HAS_SUBGIG)
#if MBED_CONF_SL_RAIL_HAS_SUBGIG
// Set up the PA for sub-GHz operation
static const RAIL_TxPowerConfig_t paInitSubGhz = {
.mode = RAIL_TX_POWER_MODE_SUBGIG,
@ -270,16 +277,13 @@ static void rf_thread_loop(const void *arg)
if (event.value.signals & SL_RX_DONE) {
while(rx_queue_tail != rx_queue_head) {
uint8_t* packet = (uint8_t*) rx_queue[rx_queue_tail];
SL_DEBUG_PRINT("rPKT %d\n", packet[2] - 2);
SL_DEBUG_PRINT("rPKT %d\n", packet[MAC_PACKET_INFO_LENGTH] - 2);
device_driver.phy_rx_cb(
&packet[3], /* Data payload for Nanostack starts at FCS */
packet[2] - 2, /* Payload length is part of frame, but need to subtract CRC bytes */
packet[1], /* LQI in second byte */
packet[0], /* RSSI in first byte */
&packet[MAC_PACKET_INFO_LENGTH + 1], /* Data payload for Nanostack starts at FCS */
packet[MAC_PACKET_INFO_LENGTH] - 2, /* Payload length is part of frame, but need to subtract CRC bytes */
packet[MAC_PACKET_OFFSET_LQI], /* LQI in second byte */
packet[MAC_PACKET_OFFSET_RSSI], /* RSSI in first byte */
rf_radio_driver_id);
free(packet);
rx_queue[rx_queue_tail] = NULL;
rx_queue_tail = (rx_queue_tail + 1) % RF_QUEUE_SIZE;
}
@ -887,6 +891,12 @@ static void radioEventHandler(RAIL_Handle_t railHandle,
if (railHandle != gRailHandle)
return;
#ifdef MBED_CONF_RTOS_PRESENT
if(rf_thread_id == 0) {
return;
}
#endif
size_t index = 0;
do {
if (events & 1ull) {
@ -956,43 +966,20 @@ static void radioEventHandler(RAIL_Handle_t railHandle,
/* Only process the packet if it had a correct CRC */
if(rxPacketInfo.packetStatus == RAIL_RX_PACKET_READY_SUCCESS) {
/* Get RSSI and LQI information about this packet */
RAIL_RxPacketDetails_t rxPacketDetails;
rxPacketDetails.timeReceived.timePosition = RAIL_PACKET_TIME_DEFAULT;
rxPacketDetails.timeReceived.totalPacketBytes = 0;
RAIL_GetRxPacketDetails(gRailHandle, rxHandle, &rxPacketDetails);
uint8_t header[4];
RAIL_PeekRxPacket(gRailHandle, rxHandle, header, 4, 0);
/* Allocate a contiguous buffer for this packet's payload */
uint8_t* packetBuffer = (uint8_t*) malloc(rxPacketInfo.packetBytes + 2);
if(packetBuffer == NULL) {
SL_DEBUG_PRINT("Out of memory\n");
break;
}
/* First two bytes are RSSI and LQI, respecitvely */
packetBuffer[0] = (uint8_t)rxPacketDetails.rssi;
packetBuffer[1] = (uint8_t)rxPacketDetails.lqi;
/* Copy packet payload from circular FIFO into contiguous memory */
memcpy(&packetBuffer[2], rxPacketInfo.firstPortionData, rxPacketInfo.firstPortionBytes);
if (rxPacketInfo.firstPortionBytes < rxPacketInfo.packetBytes) {
memcpy(&packetBuffer[2+rxPacketInfo.firstPortionBytes],
rxPacketInfo.lastPortionData,
rxPacketInfo.packetBytes - rxPacketInfo.firstPortionBytes);
}
/* Release RAIL resources early */
RAIL_ReleaseRxPacket(gRailHandle, rxHandle);
/* If this is an ACK, deal with it */
if( packetBuffer[2] == 5 &&
packetBuffer[2+3] == (current_tx_sequence) &&
/* If this is an ACK, deal with it early */
if( (header[0] == 5) &&
(header[3] == current_tx_sequence) &&
waiting_for_ack) {
/* Tell the radio to not ACK an ACK */
RAIL_CancelAutoAck(gRailHandle);
waiting_for_ack = false;
/* Save the pending bit */
last_ack_pending_bit = (packetBuffer[2+1] & (1 << 4)) != 0;
last_ack_pending_bit = (header[1] & (1 << 4)) != 0;
/* Release packet */
RAIL_ReleaseRxPacket(gRailHandle, rxHandle);
/* Tell the stack we got an ACK */
#ifdef MBED_CONF_RTOS_PRESENT
osSignalSet(rf_thread_id, SL_ACK_RECV | (last_ack_pending_bit ? SL_ACK_PEND : 0));
@ -1004,8 +991,37 @@ static void radioEventHandler(RAIL_Handle_t railHandle,
1,
1);
#endif
free(packetBuffer);
} else {
/* Get RSSI and LQI information about this packet */
RAIL_RxPacketDetails_t rxPacketDetails;
rxPacketDetails.timeReceived.timePosition = RAIL_PACKET_TIME_DEFAULT;
rxPacketDetails.timeReceived.totalPacketBytes = 0;
RAIL_GetRxPacketDetails(gRailHandle, rxHandle, &rxPacketDetails);
#ifdef MBED_CONF_RTOS_PRESENT
/* Drop this packet if we're out of space */
if (((rx_queue_head + 1) % RF_QUEUE_SIZE) == rx_queue_tail) {
osSignalSet(rf_thread_id, SL_QUEUE_FULL);
RAIL_ReleaseRxPacket(gRailHandle, rxHandle);
break;
}
/* Copy into queue */
uint8_t* packetBuffer = (uint8_t*)rx_queue[rx_queue_head];
#else
/* Packet going temporarily onto stack for bare-metal apps */
uint8_t packetBuffer[MAC_PACKET_MAX_LENGTH + MAC_PACKET_INFO_LENGTH];
#endif
/* First two bytes are RSSI and LQI, respecitvely */
packetBuffer[MAC_PACKET_OFFSET_RSSI] = (uint8_t)rxPacketDetails.rssi;
packetBuffer[MAC_PACKET_OFFSET_LQI] = (uint8_t)rxPacketDetails.lqi;
/* Copy packet payload from circular FIFO into contiguous memory */
RAIL_CopyRxPacket(&packetBuffer[MAC_PACKET_INFO_LENGTH], &rxPacketInfo);
/* Release RAIL resources early */
RAIL_ReleaseRxPacket(gRailHandle, rxHandle);
/* Figure out whether we want to not ACK this packet */
/*
@ -1015,27 +1031,20 @@ static void radioEventHandler(RAIL_Handle_t railHandle,
* [1] => b[0:2] frame type, b[3] = security enabled, b[4] = frame pending, b[5] = ACKreq, b[6] = intrapan
* [2] => b[2:3] destmode, b[4:5] version, b[6:7] srcmode
*/
if( (packetBuffer[2+1] & (1 << 5)) == 0 ) {
if( (packetBuffer[MAC_PACKET_INFO_LENGTH + 1] & (1 << 5)) == 0 ) {
/* Cancel the ACK if the sender did not request one */
RAIL_CancelAutoAck(gRailHandle);
}
#ifdef MBED_CONF_RTOS_PRESENT
if (((rx_queue_head + 1) % RF_QUEUE_SIZE) != rx_queue_tail) {
rx_queue[rx_queue_head] = (void*)packetBuffer;
rx_queue_head = (rx_queue_head + 1) % RF_QUEUE_SIZE;
osSignalSet(rf_thread_id, SL_RX_DONE);
} else {
free(packetBuffer);
osSignalSet(rf_thread_id, SL_QUEUE_FULL);
}
#else
SL_DEBUG_PRINT("rPKT %d\n", rxPacket[2] - 2);
device_driver.phy_rx_cb(&rxPacket[3], /* Data payload for Nanostack starts at FCS */
rxPacket[2] - 2, /* Payload length is part of frame, but need to subtract CRC bytes */
rxPacket[1], /* LQI in second byte */
rxPacket[0], /* RSSI in first byte */
SL_DEBUG_PRINT("rPKT %d\n", packetBuffer[MAC_PACKET_INFO_LENGTH] - 2);
device_driver.phy_rx_cb(&packetBuffer[MAC_PACKET_INFO_LENGTH + 1], /* Data payload for Nanostack starts at FCS */
packetBuffer[MAC_PACKET_INFO_LENGTH] - 2, /* Payload length is part of frame, but need to subtract CRC bytes */
packetBuffer[MAC_PACKET_OFFSET_LQI], /* LQI in second byte */
packetBuffer[MAC_PACKET_OFFSET_RSSI], /* RSSI in first byte */
rf_radio_driver_id);
free(packetBuffer);
#endif
}
}

4
mbed.h
View File

@ -16,13 +16,13 @@
#ifndef MBED_H
#define MBED_H
#define MBED_LIBRARY_VERSION 161
#define MBED_LIBRARY_VERSION 162
#if MBED_CONF_RTOS_PRESENT
// RTOS present, this is valid only for mbed OS 5
#define MBED_MAJOR_VERSION 5
#define MBED_MINOR_VERSION 8
#define MBED_PATCH_VERSION 3
#define MBED_PATCH_VERSION 4
#else
// mbed 2

2
platform/mbed_retarget.cpp
View File

@ -1339,7 +1339,7 @@ extern "C" void __cxa_guard_abort(int *guard_object_p)
#endif
#if defined(MBED_MEM_TRACING_ENABLED) && (defined(__CC_ARM) || defined(__ICCARM__))
#if defined(MBED_MEM_TRACING_ENABLED) && (defined(__CC_ARM) || defined(__ICCARM__) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)))
// If the memory tracing is enabled, the wrappers in mbed_alloc_wrappers.cpp
// provide the implementation for these. Note: this needs to use the wrappers

1
requirements.txt
View File

@ -13,3 +13,4 @@ beautifulsoup4>=4
fuzzywuzzy>=0.11
pyelftools>=0.24
jsonschema>=2.6
future>=0.16.0

2
targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.S
View File

@ -22,7 +22,7 @@
*
*/
#include "memory_zones.h"
#include "../memory_zones.h"
__initial_sp EQU ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE ; Top of ZBT SSRAM2 and 3, used for data

9
targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.c
View File

@ -6,7 +6,7 @@
* @date: $Date: $
*-----------------------------------------------------------------------------
*
Copyright (c) 2010-2017 Analog Devices, Inc.
Copyright (c) 2010-2018 Analog Devices, Inc.
All rights reserved.
@ -44,7 +44,6 @@ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
#include <stdint.h>
#ifdef __ARMCC_VERSION
#include <rt_misc.h>
#endif
@ -52,7 +51,6 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include <startup_ADuCM3029.h>
#include <mbed_rtx.h>
/*----------------------------------------------------------------------------
External function Declaration
*----------------------------------------------------------------------------*/
@ -61,9 +59,8 @@ extern void SramInit(void);
/*----------------------------------------------------------------------------
Checksum options
*----------------------------------------------------------------------------*/
#if defined (__ARMCC_VERSION)
__attribute__((section(".ARM.__at_0x000001A0")))
#elif defined( __ICCARM__)
#if defined( __ICCARM__)
__root
#endif /* __ICCARM__ */
const uint32_t SECTION_PLACE(blank_checksum[],".checksum") =

13
targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/startup_ADuCM3029.h
View File

@ -7,7 +7,7 @@
* @date: $Date: $
*-----------------------------------------------------------------------------
*
Copyright (c) 2010-2017 Analog Devices, Inc.
Copyright (c) 2010-2018 Analog Devices, Inc.
All rights reserved.
@ -62,6 +62,8 @@ RESET_EXCPT_HNDLR
#define __STARTUP_H__
#define VECTOR_SECTION ".vectors"
/* IVT typedefs. */
typedef void( *pFunc )( void );
#ifdef __ARMCC_VERSION
void Default_Handler(void);
@ -71,6 +73,8 @@ void Default_Handler(void);
#define RESET_EXCPT_HNDLR __main
#define COMPILER_NAME "ARMCC"
#define WEAK_FUNCTION(x) void x (void) __attribute__((weak, alias("Default_Handler")));
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
#elif defined(__ICCARM__)
#pragma diag_suppress=Pm093,Pm140
@ -80,6 +84,8 @@ void Default_Handler(void);
#define RESET_EXCPT_HNDLR __iar_program_start
#define COMPILER_NAME "ICCARM"
#define WEAK_FUNCTION(x) WEAK_FUNC ( void x (void)) { while(1){} }
#pragma section=VECTOR_SECTION
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(VECTOR_SECTION))
#elif defined(__GNUC__)
extern unsigned __etext;
@ -105,8 +111,11 @@ extern int __START(void) __attribute__((noreturn)); /* main entry point */
#define IVT_NAME __Vectors
#define COMPILER_NAME "GNUC"
#define WEAK_FUNCTION(x) void x (void) __attribute__ ((weak, alias("Default_Handler")));
extern const pFunc IVT_NAME[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)IVT_NAME)
#define __STARTUP_CLEAR_BSS_MULTIPLE
#endif // __GNUC__
#define LASTCRCPAGE 0
#define BLANKX4 0xFFFFFFFF
#define BLANKX20 BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4
@ -115,8 +124,6 @@ extern int __START(void) __attribute__((noreturn)); /* main entry point */
#define BLANKX60 BLANKX20,BLANKX20,BLANKX20
void RESET_EXCPT_HNDLR(void);
void Reset_Handler(void);
/* IVT typedefs. */
typedef void( *pFunc )( void );
#define ADUCM3029_VECTORS /* Cortex-M3 Exceptions Handler */ \
Reset_Handler, /* -15 */ \

28
targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_ARM_STD/ADuCM3029.sct
View File

@ -1,9 +1,10 @@
#! armcc -E
;******************************************************************************
; File: ADuCM3029.sct
; Scatter loading file for Analog Devices ADuCM3029 processor
;
; Copyright (c) 2011 - 2014 ARM LIMITED
; Copyright (c) 2016 - 2017 Analog Devices, Inc.
; Copyright (c) 2016 - 2018 Analog Devices, Inc.
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
@ -32,13 +33,30 @@
; Portions Copyright (c) 2017 Analog Devices, Inc.
;
;******************************************************************************
#if !defined(MBED_APP_START)
#define MBED_APP_START 0
#endif
LR_IROM1 0x00000000 0x00040000 {
ADUCM_IROM1 0x00000000 0x00040000 { ; romflash start address
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
#define ADUCM_SECTOR_SIZE 0x800
#define ADUCM_VECTOR_SIZE 0x1A0
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
FLASH0 MBED_APP_START ADUCM_VECTOR_SIZE {
*(.vectors, +First)
*(.checksum)
}
FLASH1 (MBED_APP_START + ADUCM_VECTOR_SIZE) (ADUCM_SECTOR_SIZE - ADUCM_VECTOR_SIZE) {
*(.checksum, +Last)
}
ER_IROM1 (MBED_APP_START + ADUCM_SECTOR_SIZE) (MBED_APP_SIZE - ADUCM_SECTOR_SIZE) {
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
RW_IRAM1 0x20000200 { ; data section

20
targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld
View File

@ -1,17 +1,27 @@
/*
* Portions Copyright (c) 2016 - 2017 Analog Devices, Inc.
* Portions Copyright (c) 2016 - 2018 Analog Devices, Inc.
*
* Based on Device/ARM/ARMCM3/Source/GCC/gcc_arm.ld file in
* ARM.CMSIS.4.5.0.pack.
*/
#if !defined(MBED_APP_START)
#define MBED_APP_START 0
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
#define ADUCM_SECTOR_SIZE 0x800
/* Linker script to configure memory regions. */
MEMORY
{
/* Flash bank0 */
FLASH0 (rx) : ORIGIN = 0x00000000, LENGTH = 0x800
/* Flash bank0 - bank127*/
FLASH (rx) : ORIGIN = 0x00000800, LENGTH = 256k - 0x800
/* The first 0x800 bytes of flash */
FLASH0 (rx) : ORIGIN = MBED_APP_START, LENGTH = ADUCM_SECTOR_SIZE
/* The rest of the flash */
FLASH (rx) : ORIGIN = MBED_APP_START + ADUCM_SECTOR_SIZE, LENGTH = MBED_APP_SIZE - ADUCM_SECTOR_SIZE
/* SRAM bank 0+1 */
DSRAM_V (rwx) : ORIGIN = 0x20000000, LENGTH = 0x200
DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 16k - 0x200

21
targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_IAR/ADuCM3029.icf
View File

@ -3,7 +3,7 @@
* ILINK Configuration File for Analog Devices ADuCM3029 processor
*
* Copyright (c) 2011 - 2014 ARM LIMITED
* Copyright (c) 2016 - 2017 Analog Devices, Inc.
* Copyright (c) 2016 - 2018 Analog Devices, Inc.
*
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
@ -29,10 +29,23 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = 0;
}
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = 0x40000;
}
define symbol ADUCM_SECTOR_SIZE = 0x800;
define symbol ADUCM_VECTOR_SIZE = 0x1A0;
define memory mem with size = 4G;
define region ROM_PAGE0_INTVEC = mem:[from 0x00000000 size 0x000001A0];
define region ROM_PAGE0_CHECKSUM = mem:[from 0x000001A0 size 0x00000660];
define region ROM_REGION = mem:[from 0x00000800 size 254K];
define region ROM_PAGE0_INTVEC = mem:[from MBED_APP_START size ADUCM_VECTOR_SIZE];
define region ROM_PAGE0_CHECKSUM = mem:[from MBED_APP_START+ADUCM_VECTOR_SIZE size ADUCM_SECTOR_SIZE-ADUCM_VECTOR_SIZE];
define region ROM_REGION = mem:[from MBED_APP_START+ADUCM_SECTOR_SIZE size MBED_APP_SIZE-ADUCM_SECTOR_SIZE];
define region RAM_bank1_region = mem:[from 0x20000200 size 0x00003E00];
define region RAM_bank2_region = mem:[from 0x20004000 size 0x00004000]
| mem:[from 0x20040000 size 0x00008000];

3
targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/cmsis_nvic.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2010-2017 Analog Devices, Inc.
* Copyright (c) 2010-2018 Analog Devices, Inc.
*
* All rights reserved.
*
@ -48,7 +48,6 @@
#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000
#define NVIC_FLASH_VECTOR_ADDRESS 0x0
#ifdef __cplusplus
extern "C" {

4
targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2010-2017 Analog Devices, Inc.
* Copyright (c) 2010-2018 Analog Devices, Inc.
*
* All rights reserved.
*
@ -68,7 +68,7 @@ static const flash_algo_t flash_algo_config = {
.erase_sector = 0x0000006F,
.program_page = 0x000000AB,
.static_base = 0x0000017C,
.algo_blob = FLASH_ALGO
.algo_blob = (uint32_t *)FLASH_ALGO
};
static const sector_info_t sectors_info[] = {

19
targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.c
View File

@ -6,7 +6,7 @@
* @date: $Date: $
*-----------------------------------------------------------------------------
*
Copyright (c) 2010-2017 Analog Devices, Inc.
Copyright (c) 2010-2018 Analog Devices, Inc.
All rights reserved.
@ -45,19 +45,22 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
#ifdef __ARMCC_VERSION
#include <stdint.h>
#include <rt_misc.h>
#endif
#include <cmsis.h>
#include <startup_ADuCM4050.h>
#include <mbed_rtx.h>
/*----------------------------------------------------------------------------
External function Declaration
*----------------------------------------------------------------------------*/
extern void SramInit(void);
/*----------------------------------------------------------------------------
Checksum options
*----------------------------------------------------------------------------*/
#if defined (__ARMCC_VERSION)
__attribute__((section(".ARM.__at_0x000001A0")))
#elif defined(__ICCARM__)
#if defined(__ICCARM__)
__root
#endif
const uint32_t SECTION_PLACE(blank_checksum[],".checksum") =
@ -65,12 +68,6 @@ const uint32_t SECTION_PLACE(blank_checksum[],".checksum") =
BLANKX60,BLANKX600
};
/*----------------------------------------------------------------------------
External function Declaration
*----------------------------------------------------------------------------*/
extern void SramInit(void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/

36
targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/startup_ADuCM4050.h
View File

@ -7,7 +7,7 @@
* @date: $Date: $
*-----------------------------------------------------------------------------
*
Copyright (c) 2010-2017 Analog Devices, Inc.
Copyright (c) 2010-2018 Analog Devices, Inc.
All rights reserved.
@ -63,6 +63,9 @@ RESET_EXCPT_HNDLR
#include <adi_types.h>
#define VECTOR_SECTION ".vectors"
/* IVT typedefs. */
typedef void( *pFunc )( void );
#ifdef __ARMCC_VERSION
void Default_Handler(void);
#define SECTION_NAME(sectionname) __attribute__((section(sectionname)))
@ -71,6 +74,9 @@ void Default_Handler(void);
#define RESET_EXCPT_HNDLR __main
#define COMPILER_NAME "ARMCC"
#define WEAK_FUNCTION(x) void x (void) __attribute__((weak, alias("Default_Handler")));
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
#elif defined(__ICCARM__)
/*
* IAR MISRA C 2004 error suppressions:
@ -89,17 +95,20 @@ void Default_Handler(void);
#define RESET_EXCPT_HNDLR __iar_program_start
#define COMPILER_NAME "ICCARM"
#define WEAK_FUNCTION(x) WEAK_FUNC ( void x (void)) { while(1){} }
#pragma section=VECTOR_SECTION
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(VECTOR_SECTION))
#elif defined(__GNUC__)
extern unsigned __etext;
extern unsigned __data_start__;
extern unsigned __data_end__;
extern unsigned __copy_table_start__;
extern unsigned __copy_table_end__;
extern unsigned __zero_table_start__;
extern unsigned __zero_table_end__;
extern unsigned __bss_start__;
extern unsigned __bss_end__;
extern unsigned __StackTop;
extern uint32_t __etext;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __copy_table_start__;
extern uint32_t __copy_table_end__;
extern uint32_t __zero_table_start__;
extern uint32_t __zero_table_end__;
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __StackTop;
void Default_Handler(void);
/*----------------------------------------------------------------------------
External References
@ -122,8 +131,11 @@ extern int __START(void) __attribute__((noreturn)); /* main entry point */
#define IVT_NAME __Vectors
#define COMPILER_NAME "GNUC"
#define WEAK_FUNCTION(x) void x (void) __attribute__ ((weak, alias("Default_Handler")));
extern const pFunc IVT_NAME[];
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)IVT_NAME)
#define __STARTUP_CLEAR_BSS_MULTIPLE
#endif // __GNUC__
#define LASTCRCPAGE 0
#define BLANKX4 0xFFFFFFFF
#define BLANKX20 BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4,BLANKX4
@ -132,8 +144,6 @@ extern int __START(void) __attribute__((noreturn)); /* main entry point */
#define BLANKX60 BLANKX20,BLANKX20,BLANKX20
void RESET_EXCPT_HNDLR(void);
void Reset_Handler(void);
/* IVT typedefs. */
typedef void( *pFunc )( void );
#define ADUCM4050_VECTORS \
/* Configure Initial Stack Pointer, using linker-generated symbols */\

27
targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct
View File

@ -1,9 +1,10 @@
#! armcc -E
;******************************************************************************
; File: ADuCM4050.sct
; Scatter loading file for Analog Devices ADuCM4050 processor
;
; Copyright (c) 2011 - 2014 ARM LIMITED
; Copyright (c) 2016 - 2017 Analog Devices, Inc.
; Copyright (c) 2016 - 2018 Analog Devices, Inc.
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
@ -29,14 +30,28 @@
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;******************************************************************************
LR_IROM1 0x00000000 0x0007F000 {
FLASH0 0x00000000 0x00000800 {
#if !defined(MBED_APP_START)
#define MBED_APP_START 0
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x7F000
#endif
#define ADUCM_SECTOR_SIZE 0x800
#define ADUCM_VECTOR_SIZE 0x1A0
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
FLASH0 MBED_APP_START ADUCM_VECTOR_SIZE {
*(.vectors, +First)
*(.checksum)
}
ER_IROM1 AlignExpr(ImageLimit(FLASH0), 16) 0x0007E800 {
; load address = execution address
FLASH1 (MBED_APP_START + ADUCM_VECTOR_SIZE) (ADUCM_SECTOR_SIZE - ADUCM_VECTOR_SIZE) {
*(.checksum, +Last)
}
ER_IROM1 (MBED_APP_START + ADUCM_SECTOR_SIZE) (MBED_APP_SIZE - ADUCM_SECTOR_SIZE) {
*(InRoot$$Sections)
*(+RO)
}

25
targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld
View File

@ -1,17 +1,27 @@
/*
* Portions Copyright (c) 2016 Analog Devices, Inc.
* Portions Copyright (c) 2016 - 2018 Analog Devices, Inc.
*
* Based on Device/ARM/ARMCM4/Source/GCC/gcc_arm.ld file in
* ARM.CMSIS.4.5.0.pack.
*/
#if !defined(MBED_APP_START)
#define MBED_APP_START 0
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x7F000
#endif
#define ADUCM_SECTOR_SIZE 0x800
/* Linker script to configure memory regions. */
MEMORY
{
/* The first 0x800 bytes of flash */
FLASH0 (rx) : ORIGIN = 0x00000000, LENGTH = 0x800
/* The remaining bytes of flash minus 4KB Protected Key Storage */
FLASH (rx) : ORIGIN = 0x00000800, LENGTH = 512k - 4k - 0x800
FLASH0 (rx) : ORIGIN = MBED_APP_START, LENGTH = ADUCM_SECTOR_SIZE
/* The rest of the flash */
FLASH (rx) : ORIGIN = MBED_APP_START + ADUCM_SECTOR_SIZE, LENGTH = MBED_APP_SIZE - ADUCM_SECTOR_SIZE
/* SRAM bank 0 */
DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 32k - 0x200
/* SRAM bank 3+4+5+6+7 */
@ -76,13 +86,6 @@ SECTIONS
KEEP(*(.checksum))
} > FLASH0
.security_options :
{
. = ALIGN(4);
KEEP(*(.security_options))
. = ALIGN(4);
} > FLASH0
.text :
{
*(.text*)

21
targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf
View File

@ -3,7 +3,7 @@
* ILINK Configuration File for Analog Devices ADuCM4050 processor
*
* Copyright (c) 2011 - 2014 ARM LIMITED
* Copyright (c) 2016 - 2017 Analog Devices, Inc.
* Copyright (c) 2016 - 2018 Analog Devices, Inc.
*
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
@ -29,10 +29,23 @@
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = 0;
}
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = 0x7F000;
}
define symbol ADUCM_SECTOR_SIZE = 0x800;
define symbol ADUCM_VECTOR_SIZE = 0x1A0;
define memory mem with size = 4G;
define region ROM_PAGE0_INTVEC = mem:[from 0x00000000 size 0x000001A0];
define region ROM_PAGE0_CHECKSUM = mem:[from 0x000001A0 size 0x00000660];
define region ROM_REGION = mem:[from 0x00000800 size 506K];
define region ROM_PAGE0_INTVEC = mem:[from MBED_APP_START size ADUCM_VECTOR_SIZE];
define region ROM_PAGE0_CHECKSUM = mem:[from MBED_APP_START+ADUCM_VECTOR_SIZE size ADUCM_SECTOR_SIZE-ADUCM_VECTOR_SIZE];
define region ROM_REGION = mem:[from MBED_APP_START+ADUCM_SECTOR_SIZE size MBED_APP_SIZE-ADUCM_SECTOR_SIZE];
define region RAM_bank1_region = mem:[from 0x20040000 size 0x00008000];
define region RAM_bank2_region = mem:[from 0x20000200 size 0x00007E00]
| mem:[from 0x20048000 size 0x00010000];

3
targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/cmsis_nvic.h
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2010-2017 Analog Devices, Inc.
* Copyright (c) 2010-2018 Analog Devices, Inc.
*
* All rights reserved.
*
@ -48,7 +48,6 @@
#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000
#define NVIC_FLASH_VECTOR_ADDRESS 0x0
#ifdef __cplusplus
extern "C" {

4
targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (c) 2010-2017 Analog Devices, Inc.
* Copyright (c) 2010-2018 Analog Devices, Inc.
*
* All rights reserved.
*
@ -66,7 +66,7 @@ static const flash_algo_t flash_algo_config = {
.erase_sector = 0x00000057,
.program_page = 0x0000007F,
.static_base = 0x0000013C,
.algo_blob = FLASH_ALGO
.algo_blob = (uint32_t *)FLASH_ALGO
};
static const sector_info_t sectors_info[] = {

4
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/pwmout_api.c
View File

@ -36,9 +36,9 @@ void pwmout_init(pwmout_t* obj, PinName pin)
uint32_t pwm_base_clock;
/* Set the TPM clock source to be IRC 48M */
/* Set the TPM clock source to be MCG FLL clock */
CLOCK_SetTpmClock(1U);
pwm_base_clock = CLOCK_GetFreq(kCLOCK_McgIrc48MClk);
pwm_base_clock = CLOCK_GetFreq(kCLOCK_PllFllSelClk);
float clkval = (float)pwm_base_clock / 1000000.0f;
uint32_t clkdiv = 0;
while (clkval > 1) {

21
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/MKW41Z4_features.h
View File

@ -1680,14 +1680,29 @@
#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
/* @brief Has external trigger selection. */
#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
/* @brief Has TPM_COMBINE. */
/* @brief Has TPM_COMBINE register. */
#define FSL_FEATURE_TPM_HAS_COMBINE (1)
/* @brief Whether COMBINE register has effect. */
#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \
((x) == TPM0 ? (0) : \
((x) == TPM1 ? (1) : \
((x) == TPM2 ? (1) : (-1))))
/* @brief Has TPM_POL. */
#define FSL_FEATURE_TPM_HAS_POL (1)
/* @brief Has TPM_FILTER. */
/* @brief Has TPM_FILTER register. */
#define FSL_FEATURE_TPM_HAS_FILTER (1)
/* @brief Has TPM_QDCTRL. */
/* @brief Whether FILTER register has effect. */
#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \
((x) == TPM0 ? (0) : \
((x) == TPM1 ? (1) : \
((x) == TPM2 ? (1) : (-1))))
/* @brief Has TPM_QDCTRL register. */
#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
/* @brief Whether QDCTRL register has effect. */
#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \
((x) == TPM0 ? (0) : \
((x) == TPM1 ? (1) : \
((x) == TPM2 ? (1) : (-1))))
/* TRNG0 module features */

10
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_tpm.c
View File

@ -162,6 +162,12 @@ status_t TPM_SetupPwm(TPM_Type *base,
assert(pwmFreq_Hz);
assert(numOfChnls);
assert(srcClock_Hz);
#if defined(FSL_FEATURE_TPM_HAS_COMBINE) && FSL_FEATURE_TPM_HAS_COMBINE
if(mode == kTPM_CombinedPwm)
{
assert(FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(base));
}
#endif
uint32_t mod;
uint32_t tpmClock = (srcClock_Hz / (1U << (base->SC & TPM_SC_PS_MASK)));
@ -169,8 +175,12 @@ status_t TPM_SetupPwm(TPM_Type *base,
uint8_t i;
#if defined(FSL_FEATURE_TPM_HAS_QDCTRL) && FSL_FEATURE_TPM_HAS_QDCTRL
/* The TPM's QDCTRL register required to be effective */
if( FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(base) )
{
/* Clear quadrature Decoder mode because in quadrature Decoder mode PWM doesn't operate*/
base->QDCTRL &= ~TPM_QDCTRL_QUADEN_MASK;
}
#endif
switch (mode)

3
targets/TARGET_Maxim/TARGET_MAX32620C/analogin_api.c
View File

@ -50,7 +50,7 @@ void analogin_init(analogin_t *obj, PinName pin)
// Set the object pointer and channel encoding
obj->adc = MXC_ADC;
obj->channel = pinmap_find_function(pin, PinMap_ADC);
obj->channel = (mxc_adc_chsel_t)pinmap_find_function(pin, PinMap_ADC);
if (!initialized) {
MBED_ASSERT(ADC_Init() == E_NO_ERROR);
@ -93,4 +93,3 @@ uint16_t analogin_read_u16(analogin_t *obj)
return result;
}

7
targets/TARGET_Maxim/TARGET_MAX32620C/i2c_api.c
View File

@ -78,7 +78,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
//******************************************************************************
void i2c_frequency(i2c_t *obj, int hz)
{
I2CM_Init(obj->i2c, &obj->sys_cfg, hz);
I2CM_Init(obj->i2c, &obj->sys_cfg, (i2cm_speed_t)hz);
}
//******************************************************************************
@ -145,11 +145,6 @@ int i2c_byte_read(i2c_t *obj, int last)
if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK) != E_NO_ERROR) {
goto byte_read_err;
}
// Send the stop condition
if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP) != E_NO_ERROR) {
goto byte_read_err;
}
} else {
if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT) != E_NO_ERROR) {
goto byte_read_err;

2
targets/TARGET_Maxim/TARGET_MAX32620C/mxc/lp.c
View File

@ -179,7 +179,7 @@ int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_
return result;
}
uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio)
int LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio)
{
uint8_t gpioWokeUp = 0;

2
targets/TARGET_Maxim/TARGET_MAX32620C/mxc/lp.h
View File

@ -138,7 +138,7 @@ int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio);
* nonzero = at least one of the gpio passed in triggered a wake up
* the bit set represents which pin is the wake up source
*/
uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio);
int LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio);
/**
* @brief Wake on USB plug or unplug

8
targets/TARGET_Maxim/TARGET_MAX32620C/mxc/mxc_sys.h
View File

@ -240,13 +240,13 @@ int SYS_SPIX_Init(const sys_cfg_spix_t *sys_cfg, uint32_t baud);
* @brief System level shutdown for SPIX module
* @returns E_NO_ERROR if everything is successful
*/
int SYS_SPIX_Shutdown();
int SYS_SPIX_Shutdown(void);
/**
* @brief Get the frequency of the SPIX module source clock
* @returns frequency in Hz
*/
uint32_t SYS_SPIX_GetFreq();
uint32_t SYS_SPIX_GetFreq(void);
/**
* @brief System level initialization for SPIS module.
@ -259,13 +259,13 @@ int SYS_SPIS_Init(const sys_cfg_spix_t *sys_cfg);
* @brief System level shutdown for SPIS module
* @returns E_NO_ERROR if everything is successful
*/
int SYS_SPIS_Shutdown();
int SYS_SPIS_Shutdown(void);
/**
* @brief Get the frequency of the SPIS module source clock
* @returns frequency in Hz
*/
uint32_t SYS_SPIS_GetFreq();
uint32_t SYS_SPIS_GetFreq(void);
/**
* @brief System level initialization for OWM module.

2
targets/TARGET_Maxim/TARGET_MAX32620C/mxc/spis.c
View File

@ -119,7 +119,7 @@ int SPIS_Shutdown(mxc_spis_regs_t *spis)
}
// Clear system level configurations
if ((err = SYS_SPIS_Shutdown(spis)) != E_NO_ERROR) {
if ((err = SYS_SPIS_Shutdown()) != E_NO_ERROR) {
return err;
}

4
targets/TARGET_Maxim/TARGET_MAX32620C/rtc_api.c
View File

@ -35,6 +35,7 @@
#include "lp_ticker_api.h"
#include "rtc.h"
#include "lp.h"
#include <string.h>
// LOG2 for 32-bit powers of 2
#define LOG2_1(n) (((n) >= (1 << 1)) ? 1 : 0)
@ -65,7 +66,8 @@ static void init_rtc(void)
* if it is already running.
*/
if (!RTC_IsActive()) {
rtc_cfg_t cfg = { 0 };
rtc_cfg_t cfg;
memset(&cfg, 0, sizeof(rtc_cfg_t));
cfg.prescaler = LP_TIMER_PRESCALE;
cfg.snoozeMode = RTC_SNOOZE_DISABLE;

3
targets/TARGET_Maxim/TARGET_MAX32625/analogin_api.c
View File

@ -50,7 +50,7 @@ void analogin_init(analogin_t *obj, PinName pin)
// Set the object pointer and channel encoding
obj->adc = MXC_ADC;
obj->channel = pinmap_find_function(pin, PinMap_ADC);
obj->channel = (mxc_adc_chsel_t)pinmap_find_function(pin, PinMap_ADC);
if (!initialized) {
MBED_ASSERT(ADC_Init() == E_NO_ERROR);
@ -93,4 +93,3 @@ uint16_t analogin_read_u16(analogin_t *obj)
return result;
}

7
targets/TARGET_Maxim/TARGET_MAX32625/gpio_api.c
View File

@ -67,6 +67,13 @@ void gpio_init(gpio_t *obj, PinName name)
void gpio_mode(gpio_t *obj, PinMode mode)
{
#ifdef OPEN_DRAIN_LEDS
if ((obj->name == LED1) || (obj->name == LED2) ||
(obj->name == LED3) || (obj->name == LED4)) {
mode = OpenDrain;
}
#endif
obj->mode = mode;
pin_mode(obj->name, mode);
}

2
targets/TARGET_Maxim/TARGET_MAX32625/i2c_api.c
View File

@ -79,7 +79,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
//******************************************************************************
void i2c_frequency(i2c_t *obj, int hz)
{
I2CM_SetFrequency(obj->i2c, hz);
I2CM_SetFrequency(obj->i2c, (i2cm_speed_t)hz);
}
//******************************************************************************

2
targets/TARGET_Maxim/TARGET_MAX32625/mxc/lp.c
View File

@ -178,7 +178,7 @@ int LP_ConfigGPIOWakeUpDetect(const gpio_cfg_t *gpio, unsigned int act_high, lp_
return result;
}
uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio)
int LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio)
{
uint8_t gpioWokeUp = 0;

2
targets/TARGET_Maxim/TARGET_MAX32625/mxc/lp.h
View File

@ -138,7 +138,7 @@ int LP_ClearGPIOWakeUpDetect(const gpio_cfg_t *gpio);
* nonzero = at least one of the gpio passed in triggered a wake up
* the bit set represents which pin is the wake up source
*/
uint8_t LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio);
int LP_IsGPIOWakeUpSource(const gpio_cfg_t *gpio);
/**
* @brief Wake on USB plug or unplug

4
targets/TARGET_Maxim/TARGET_MAX32625/rtc_api.c
View File

@ -35,6 +35,7 @@
#include "lp_ticker_api.h"
#include "rtc.h"
#include "lp.h"
#include <string.h>
// LOG2 for 32-bit powers of 2
#define LOG2_1(n) (((n) >= (1 << 1)) ? 1 : 0)
@ -65,7 +66,8 @@ static void init_rtc(void)
* if it is already running.
*/
if (!RTC_IsActive()) {
rtc_cfg_t cfg = { 0 };
rtc_cfg_t cfg;
memset(&cfg, 0, sizeof(rtc_cfg_t));
cfg.prescaler = LP_TIMER_PRESCALE;
cfg.snoozeMode = RTC_SNOOZE_DISABLE;

3
targets/TARGET_Maxim/TARGET_MAX32630/analogin_api.c
View File

@ -50,7 +50,7 @@ void analogin_init(analogin_t *obj, PinName pin)
// Set the object pointer and channel encoding
obj->adc = MXC_ADC;
obj->channel = pinmap_find_function(pin, PinMap_ADC);
obj->channel = (mxc_adc_chsel_t)pinmap_find_function(pin, PinMap_ADC);
if (!initialized) {
MBED_ASSERT(ADC_Init() == E_NO_ERROR);
@ -93,4 +93,3 @@ uint16_t analogin_read_u16(analogin_t *obj)
return result;
}

2
targets/TARGET_Maxim/TARGET_MAX32630/i2c_api.c
View File

@ -78,7 +78,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
//******************************************************************************
void i2c_frequency(i2c_t *obj, int hz)
{
I2CM_Init(obj->i2c, &obj->sys_cfg, hz);
I2CM_Init(obj->i2c, &obj->sys_cfg, (i2cm_speed_t)hz);
}
//******************************************************************************

4
targets/TARGET_Maxim/TARGET_MAX32630/mxc/mxc_sys.h
View File

@ -299,14 +299,14 @@ int SYS_SPIX_Init(const sys_cfg_spix_t *sys_cfg, uint32_t baud);
* @return #E_NO_ERROR if everything is successful
* @ingroup spix
*/
int SYS_SPIX_Shutdown();
int SYS_SPIX_Shutdown(void);
/**
* @brief Get the frequency of the SPIX module source clock
* @return frequency in Hz
* @ingroup spix
*/
uint32_t SYS_SPIX_GetFreq();
uint32_t SYS_SPIX_GetFreq(void);
/**
* @brief System level initialization for OWM module.

4
targets/TARGET_Maxim/TARGET_MAX32630/rtc_api.c
View File

@ -35,6 +35,7 @@
#include "lp_ticker_api.h"
#include "rtc.h"
#include "lp.h"
#include <string.h>
// LOG2 for 32-bit powers of 2
#define LOG2_1(n) (((n) >= (1 << 1)) ? 1 : 0)
@ -65,7 +66,8 @@ static void init_rtc(void)
* if it is already running.
*/
if (!RTC_IsActive()) {
rtc_cfg_t cfg = {0};
rtc_cfg_t cfg;
memset(&cfg, 0, sizeof(rtc_cfg_t));
cfg.prescaler = LP_TIMER_PRESCALE;
cfg.snoozeMode = RTC_SNOOZE_DISABLE;

6
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_irq_api.c
View File

@ -25,6 +25,8 @@
#include "fsl_pint.h"
#include "mbed_error.h"
#define INTERRUPT_PORTS 2
static uint32_t channel_ids[NUMBER_OF_GPIO_INTS] = {0};
static gpio_irq_handler irq_handler;
/* Array of PORT IRQ number. */
@ -83,6 +85,10 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
obj->pin = pin & 0x1F;
obj->port = pin / 32;
if (obj->port >= INTERRUPT_PORTS) {
return -1;
}
/* Connect trigger sources to PINT */
INPUTMUX_Init(INPUTMUX);

3
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/pinmap.c
View File

@ -29,6 +29,9 @@ void pin_function(PinName pin, int function)
CLOCK_EnableClock(gpio_clocks[port_number]);
CLOCK_EnableClock(kCLOCK_Iocon);
/* Set the DIGIMODE bit */
IOCON->PIO[port_number][pin_number] |= IOCON_PIO_DIGIMODE_MASK;
reg = IOCON->PIO[port_number][pin_number];
reg = (reg & ~0x7) | (function & 0x7);
IOCON->PIO[port_number][pin_number] = reg;

15
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c
View File

@ -32,13 +32,6 @@
#include "stm32f4xx.h"
#include "mbed_assert.h"
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
// clock source is selected with CLOCK_SOURCE in json config
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
@ -88,14 +81,6 @@ void SystemInit(void)
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}

15
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_STD/stm32f411re.sct
View File

@ -1,3 +1,4 @@
#! armcc -E
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2014, STMicroelectronics
@ -27,10 +28,18 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
LR_IROM1 0x08000000 0x80000 { ; load region size_region
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x08000000
#endif
ER_IROM1 0x08000000 0x80000 { ; load address = execution address
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x80000
#endif
; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)

10
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_GCC_ARM/STM32F411XE.ld
View File

@ -1,7 +1,15 @@
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x08000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 512K
#endif
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
}

9
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_IAR/stm32f411xe.icf
View File

@ -1,7 +1,10 @@
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x80000; }
/* [ROM = 512kb = 0x80000] */
define symbol __intvec_start__ = 0x08000000;
define symbol __region_ROM_start__ = 0x08000000;
define symbol __region_ROM_end__ = 0x0807FFFF;
define symbol __intvec_start__ = MBED_APP_START;
define symbol __region_ROM_start__ = MBED_APP_START;
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_ARM_MICRO/startup_stm32l011xx.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l011xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l011xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l011xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l011xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l011xx devices.
@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -752,7 +750,7 @@ typedef struct
/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
@ -5736,7 +5734,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l0xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.h
View File

@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32l031xx.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_ARM_STD/startup_stm32l031xx.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32l031xx.S
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file startup_stm32l031xx.s
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @brief STM32L031xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_IAR/startup_stm32l031xx.S
View File

@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l031xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32L031xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l031xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l031xx devices.
@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -761,7 +759,7 @@ typedef struct
/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
@ -5857,7 +5855,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l0xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/system_stm32l0xx.h
View File

@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_ARM_MICRO/startup_stm32l073xx.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_ARM_STD/startup_stm32l073xx.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_GCC_ARM/startup_stm32l073xx.S
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file startup_stm32l073xx.s
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @brief STM32L073xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/TOOLCHAIN_IAR/startup_stm32l073xx.S
View File

@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l073xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32L073xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l073xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l073xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l073xx devices.
@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -950,7 +948,7 @@ typedef struct
/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
@ -7532,7 +7530,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/stm32l0xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_stm32l0xx.h
View File

@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

5
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S
View File

@ -1,8 +1,8 @@
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
@ -12,7 +12,6 @@
;* calls main()).
;* After Reset the Cortex-M0+ processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file startup_stm32l053xx.s
* @author MCD Application Team
* @version V1.5.0
* @date 8-January-2016
* @brief STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/TOOLCHAIN_IAR/startup_stm32l053xx.S
View File

@ -1,8 +1,8 @@
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
;* File Name : startup_stm32l053xx.s
;* Author : MCD Application Team
;* Version : V1.5.0
;* Date : 8-January-2016
;* Version : V1.7.1
;* Date : 25-November-2016
;* Description : STM32L053xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/stm32l053xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l053xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l053xx devices.
@ -16,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -921,7 +919,7 @@ typedef struct
/******************* Bits definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_TOVS_Pos (9U)
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
@ -7235,7 +7233,7 @@ typedef struct
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2))
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/stm32l0xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/system_stm32l0xx.h
View File

@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/TOOLCHAIN_GCC_ARM/startup_stm32l072xx.S
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file startup_stm32l072xx.s
* @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief STM32L072xx Devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/stm32l072xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l072xx.h
* @author MCD Application Team
* @version V1.7.1
* @date 25-November-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for stm32l072xx devices.

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/stm32l0xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L072xZ/device/system_stm32l0xx.h
View File

@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

8
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/device/stm32l0xx.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32L0xx devices.
@ -20,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.7.0
* @brief CMSIS Device version number V1.7.1
*/
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\

4
targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/device/system_stm32l0xx.h
View File

@ -2,13 +2,11 @@
******************************************************************************
* @file system_stm32l0xx.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

2
targets/TARGET_STM/TARGET_STM32L0/analogin_device.c
View File

@ -72,7 +72,7 @@ void analogin_init(analogin_t *obj, PinName pin)
obj->handle.Init.OversamplingMode = DISABLE;
obj->handle.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1;
obj->handle.Init.Resolution = ADC_RESOLUTION_12B;
obj->handle.Init.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;
obj->handle.Init.SamplingTime = ADC_SAMPLETIME_160CYCLES_5;
obj->handle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD;
obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
obj->handle.Init.ContinuousConvMode = DISABLE;

163
targets/TARGET_STM/TARGET_STM32L0/device/stm32_hal_legacy.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
@ -138,6 +136,9 @@
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
@ -196,6 +197,7 @@
#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
#endif
#if defined(STM32L0)
@ -263,7 +265,6 @@
#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
@ -354,6 +355,7 @@
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
/**
* @}
*/
@ -454,6 +456,78 @@
* @}
*/
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32H7)
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#endif /* STM32H7 */
/**
* @}
*/
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{
*/
@ -667,7 +741,6 @@
#define FORMAT_BCD RTC_FORMAT_BCD
#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
@ -675,9 +748,6 @@
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
@ -851,6 +921,8 @@
#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
#define __DIV_LPUART UART_DIV_LPUART
#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
@ -941,9 +1013,12 @@
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
@ -1304,7 +1379,6 @@
#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
#define __HAL_ADC_JSQR ADC_JSQR
#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
@ -2223,26 +2297,26 @@
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
@ -2402,7 +2476,6 @@
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
@ -2435,8 +2508,6 @@
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
@ -2458,8 +2529,6 @@
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
@ -2644,10 +2713,22 @@
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
#if defined(STM32L0)
#define RCC_IT_LSECSS RCC_IT_CSSLSE
#define RCC_IT_CSS RCC_IT_CSSHSE
#endif
#define RCC_IT_CSSLSE RCC_IT_LSECSS
#define RCC_IT_CSSHSE RCC_IT_CSS
#define RCC_PLLMUL_3 RCC_PLL_MUL3
#define RCC_PLLMUL_4 RCC_PLL_MUL4
#define RCC_PLLMUL_6 RCC_PLL_MUL6
#define RCC_PLLMUL_8 RCC_PLL_MUL8
#define RCC_PLLMUL_12 RCC_PLL_MUL12
#define RCC_PLLMUL_16 RCC_PLL_MUL16
#define RCC_PLLMUL_24 RCC_PLL_MUL24
#define RCC_PLLMUL_32 RCC_PLL_MUL32
#define RCC_PLLMUL_48 RCC_PLL_MUL48
#define RCC_PLLDIV_2 RCC_PLL_DIV2
#define RCC_PLLDIV_3 RCC_PLL_DIV3
#define RCC_PLLDIV_4 RCC_PLL_DIV4
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
@ -2672,7 +2753,10 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32WB) || defined(STM32G0)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
@ -2768,7 +2852,6 @@
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
/**
* @}
*/
@ -2785,8 +2868,10 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT

8
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -86,11 +84,11 @@ __IO uint32_t uwTick;
*/
/**
* @brief STM32L0xx HAL Driver version number V1.7.0
* @brief STM32L0xx HAL Driver version number
*/
#define __STM32L0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32L0xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
#define __STM32L0xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32L0xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */
#define __STM32L0xx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32L0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24U)\
|(__STM32L0xx_HAL_VERSION_SUB1 << 16U)\

6
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@ -346,7 +344,7 @@
* @arg SYSCFG_FASTMODEPLUS_PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
SET_BIT(SYSCFG->CFGR2, __FASTMODEPLUS__); \
SET_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
}while(0)
/** @brief Fast mode Plus driving capability disable macro
* @param __FASTMODEPLUS__: This parameter can be a value of :
@ -356,7 +354,7 @@
* @arg SYSCFG_FASTMODEPLUS_PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
CLEAR_BIT(SYSCFG->CFGR2, __FASTMODEPLUS__); \
CLEAR_BIT(SYSCFG->CFGR2, (__FASTMODEPLUS__)); \
}while(0)

311
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_adc.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
@ -11,7 +9,7 @@
* ++ Initialization and Configuration of ADC
* + Operation functions
* ++ Start, stop, get result of conversions of regular
* group, using 3 possible modes : polling, interruption or DMA.
* group, using 3 possible modes: polling, interruption or DMA.
* + Control functions
* ++ Channels configuration on regular group
* ++ Analog Watchdog configuration
@ -26,10 +24,7 @@
##### ADC peripheral features #####
==============================================================================
[..]
(+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
(+) A built-in hardware oversampler can handle multiple conversions and average
them into a single data with increased data width, up to 16-bit.
(+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
(+) Interrupt generation at the end of regular conversion and in case of
analog watchdog or overrun events.
@ -42,16 +37,15 @@
(+) Programmable sampling time (common for all channels)
(+) ADC conversion of regular group.
(+) External trigger (timer or EXTI) with configurable polarity
(+) DMA request generation for transfer of conversions data of regular group.
(+) ADC calibration
(+) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at
slower speed.
(+) ADC conversion of regular group.
(+) ADC supply requirements: 1.62 V to 3.6 V.
(+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
Vdda or to an external voltage reference).
@ -89,7 +83,7 @@
other device clock parameters configuration:
(+++) __HAL_RCC_ADC1_CLK_ENABLE(); (mandatory)
HSI16 enable : (optional: if asynchronous clock selected)
HSI enable (optional: if asynchronous clock selected)
(+++) RCC_OscInitTypeDef RCC_OscInitStructure;
(+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;
(+++) RCC_OscInitStructure.HSI16CalibrationValue = RCC_HSICALIBRATION_DEFAULT;
@ -126,7 +120,7 @@
================================================================
[..]
(#) Configure the ADC parameters (resolution, data alignment, oversampler, continuous mode, ...)
(#) Configure the ADC parameters (resolution, data alignment, ...)
and regular group parameters (conversion trigger, sequencer, ...)
using function HAL_ADC_Init().
@ -266,20 +260,20 @@
* @{
*/
/** @defgroup ADC ADC
* @brief ADC HAL module driver
* @{
*/
#ifdef HAL_ADC_MODULE_ENABLED
/** @addtogroup ADC
* @brief ADC driver modules
* @{
*/
/** @addtogroup ADC_Private
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup ADC_Private_Constants ADC Private Constants
* @{
*/
/* Delay for ADC stabilization time. */
/* Maximum delay is 1us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
@ -296,7 +290,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup ADC_Private
/** @defgroup ADC_Private_Functions ADC Private Functions
* @{
*/
static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
@ -310,12 +304,14 @@ static void ADC_DelayMicroSecond(uint32_t microSecond);
* @}
*/
/** @addtogroup ADC_Exported_Functions
/* Exported functions ---------------------------------------------------------*/
/** @defgroup ADC_Exported_Functions ADC Exported Functions
* @{
*/
/** @addtogroup ADC_Exported_Functions_Group1
* @brief Initialization and Configuration functions
/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief ADC Initialization and Configuration functions
*
@verbatim
===============================================================================
@ -324,17 +320,15 @@ static void ADC_DelayMicroSecond(uint32_t microSecond);
[..] This section provides functions allowing to:
(+) Initialize and configure the ADC.
(+) De-initialize the ADC.
@endverbatim
* @{
*/
/**
* @brief Initializes the ADC peripheral and regular group according to
* @brief Initialize the ADC peripheral and regular group according to
* parameters specified in structure "ADC_InitTypeDef".
* @note As prerequisite, ADC clock must be configured at RCC top level
* depending on both possible clock sources: APB clock of HSI clock.
* depending on possible clock sources: APB clock of HSI clock.
* See commented example code below that can be copied and uncommented
* into HAL_ADC_MspInit().
* @note Possibility to update parameters on the fly:
@ -371,18 +365,19 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
/* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured */
@ -482,7 +477,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
ADC_CFGR1_OVRMOD |
ADC_CFGR1_AUTDLY |
ADC_CFGR1_AUTOFF |
ADC_CFGR1_DISCEN);
ADC_CFGR1_DISCEN );
hadc->Instance->CFGR1 |= (hadc->Init.DataAlign |
ADC_SCANDIR(hadc->Init.ScanConvMode) |
@ -703,9 +698,8 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
return tmp_hal_status;
}
/**
* @brief Initializes the ADC MSP.
* @brief Initialize the ADC MSP.
* @param hadc: ADC handle
* @retval None
*/
@ -714,13 +708,13 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_MspInit could be implemented in the user file
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_MspInit must be implemented in the user file.
*/
}
/**
* @brief DeInitializes the ADC MSP.
* @brief DeInitialize the ADC MSP.
* @param hadc: ADC handle
* @retval None
*/
@ -738,8 +732,8 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group2
* @brief I/O operation functions
/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
* @brief ADC IO operation functions
*
@verbatim
===============================================================================
@ -749,7 +743,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
(+) Start conversion of regular group.
(+) Stop conversion of regular group.
(+) Poll for conversion complete on regular group.
(+) poll for conversion event.
(+) Poll for conversion event.
(+) Get result of regular channel conversion.
(+) Start conversion of regular group and enable interruptions.
(+) Stop conversion of regular group and disable interruptions.
@ -760,10 +754,9 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
* @{
*/
/**
* @brief Enables ADC, starts conversion of regular group.
* Interruptions enabled in this function: None.
* @brief Enable ADC, start conversion of regular group.
* @note Interruptions enabled in this function: None.
* @param hadc: ADC handle
* @retval HAL status
*/
@ -828,7 +821,8 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
}
/**
* @brief Stop ADC conversion of regular group, disable ADC peripheral.
* @brief Stop ADC conversion of regular group (and injected channels in
* case of auto_injection mode), disable ADC peripheral.
* @param hadc: ADC handle
* @retval HAL status.
*/
@ -842,7 +836,7 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
/* Process locked */
__HAL_LOCK(hadc);
/* 1. Stop potential conversion on going, on regular group */
/* 1. Stop potential conversion on going, on ADC group regular */
tmp_hal_status = ADC_ConversionStop(hadc);
/* Disable ADC peripheral if conversions are effectively stopped */
@ -888,19 +882,18 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
*/
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
{
uint32_t tickstart;
uint32_t tmp_Flag_EOC;
uint32_t tickstart = 0;
uint32_t tmp_Flag_EOC = 0x00;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
/* If end of conversion selected to end of sequence */
/* If end of conversion selected to end of sequence conversions */
if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
{
tmp_Flag_EOC = ADC_FLAG_EOS;
}
/* If end of conversion selected to end of each conversion */
/* If end of conversion selected to end of unitary conversion */
else /* ADC_EOC_SINGLE_CONV */
{
/* Verification that ADC configuration is compliant with polling for */
@ -928,7 +921,7 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
/* Get tick count */
tickstart = HAL_GetTick();
/* Wait until End of Conversion flag is raised */
/* Wait until End of unitary conversion or sequence conversions flag is raised */
while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC))
{
/* Check if timeout is disabled (set to infinite wait) */
@ -993,18 +986,24 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
/* Return ADC state */
/* Return function status */
return HAL_OK;
}
/**
* @brief Poll for conversion event.
* @brief Poll for ADC event.
* @param hadc: ADC handle
* @param EventType: the ADC event type.
* This parameter can be one of the following values:
* @arg ADC_AWD_EVENT: ADC Analog watchdog event
* @arg ADC_OVR_EVENT: ADC Overrun event
* @param Timeout: Timeout value in millisecond.
* @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
* Indeed, the latter is reset only if hadc->Init.Overrun field is set
* to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
* by a new converted data as soon as OVR is cleared.
* To reset OVR flag once the preserved data is retrieved, the user can resort
* to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
@ -1024,7 +1023,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
/* Check if timeout is disabled (set to infinite wait) */
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
if((Timeout == 0U) ||((HAL_GetTick() - tickstart ) > Timeout))
{
/* Update ADC state machine to timeout */
SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
@ -1068,18 +1067,25 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
break;
}
/* Return ADC state */
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables ADC, starts conversion of regular group with interruption.
* Interruptions enabled in this function:
* - EOC (end of conversion of regular group) or EOS (end of
* sequence of regular group) depending on ADC initialization
* parameter "EOCSelection"
* - overrun (if available)
* @brief Enable ADC, start conversion of regular group with interruption.
* @note Interruptions enabled in this function according to initialization
* setting : EOC (end of conversion), EOS (end of sequence),
* OVR overrun.
* Each of these interruptions has its dedicated callback function.
* @note To guarantee a proper reset of all interruptions once all the needed
* conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
* a correct stop of the IT-based conversions.
* @note By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling
* interruption. If required (e.g. in case of oversampling with trigger
* mode), the user must:
* 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
* 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
* before calling HAL_ADC_Start_IT().
* @param hadc: ADC handle
* @retval HAL status
*/
@ -1129,7 +1135,6 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Enable ADC end of conversion interrupt */
/* Enable ADC overrun interrupt */
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
switch(hadc->Init.EOCSelection)
{
case ADC_EOC_SEQ_CONV:
@ -1159,7 +1164,8 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
}
/**
* @brief Stop ADC conversion of regular group, disable interruption of
* @brief Stop ADC conversion of regular group (and injected group in
* case of auto_injection mode), disable interrution of
* end-of-conversion, disable ADC peripheral.
* @param hadc: ADC handle
* @retval HAL status.
@ -1174,7 +1180,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
/* Process locked */
__HAL_LOCK(hadc);
/* 1. Stop potential conversion on going, on regular group */
/* 1. Stop potential conversion on going, on ADC group regular */
tmp_hal_status = ADC_ConversionStop(hadc);
/* Disable ADC peripheral if conversions are effectively stopped */
@ -1205,17 +1211,14 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
}
/**
* @brief Enables ADC, starts conversion of regular group and transfers result
* through DMA.
* Interruptions enabled in this function:
* - DMA transfer complete
* - DMA half transfer
* - overrun
* @brief Enable ADC, start conversion of regular group and transfer result through DMA.
* @note Interruptions enabled in this function:
* overrun (if applicable), DMA half transfer, DMA transfer complete.
* Each of these interruptions has its dedicated callback function.
* @param hadc: ADC handle
* @param pData: The destination Buffer address.
* @param Length: The length of data to be transferred from ADC peripheral to memory.
* @retval None
* @param pData: Destination Buffer address.
* @param Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
{
@ -1300,7 +1303,8 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
}
/**
* @brief Stop ADC conversion of regular group, disable ADC DMA transfer, disable
* @brief Stop ADC conversion of regular group (and injected group in
* case of auto_injection mode), disable ADC DMA transfer, disable
* ADC peripheral.
* Each of these interruptions has its dedicated callback function.
* @param hadc: ADC handle
@ -1316,16 +1320,16 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
/* Process locked */
__HAL_LOCK(hadc);
/* 1. Stop potential conversion on going, on regular group */
/* 1. Stop potential ADC group regular conversion on going */
tmp_hal_status = ADC_ConversionStop(hadc);
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
hadc->Instance->CFGR1 &= ~ADC_CFGR1_DMAEN;
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* Disable the DMA channel (in case of DMA in circular mode or stop */
/* while DMA transfer is on going) */
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
@ -1359,6 +1363,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_READY);
}
}
/* Process unlocked */
@ -1370,8 +1375,8 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
/**
* @brief Get ADC regular group conversion result.
* @note Reading DR register automatically clears EOC (end of conversion of
* regular group) flag.
* @note Reading register DR automatically clears ADC flag EOC
* (ADC group regular end of unitary conversion).
* @note This function does not clear ADC flag EOS
* (ADC group regular end of sequence conversion).
* Occurrence of flag EOS rising:
@ -1385,7 +1390,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
* model polling: @ref HAL_ADC_PollForConversion()
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
* @param hadc: ADC handle
* @retval Converted value
* @retval ADC group regular conversion data
*/
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{
@ -1400,7 +1405,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
}
/**
* @brief Handles ADC interrupt request.
* @brief Handle ADC interrupt request.
* @param hadc: ADC handle
* @retval None
*/
@ -1409,6 +1414,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
/* ========== Check End of Conversion flag for regular group ========== */
if( (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC)) ||
@ -1461,22 +1467,29 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
HAL_ADC_ConvCpltCallback(hadc);
/* Clear regular group conversion flag */
/* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
/* conversion flags clear induces the release of the preserved data.*/
/* Therefore, if the preserved data value is needed, it must be */
/* read preliminarily into HAL_ADC_ConvCpltCallback(). */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
/* Note: Management of low power auto-wait enabled: flags must be cleared */
/* by user when fetching ADC conversion data. */
/* This case is managed in IRQ handler, but this low-power mode */
/* should not be used with programming model IT or DMA. */
/* Refer to comment of parameter "LowPowerAutoWait". */
if (hadc->Init.LowPowerAutoWait != ENABLE)
{
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
}
/* ========== Check Analog watchdog flags ========== */
/* ========== Check analog watchdog 1 flag ========== */
if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD) && __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
/* Level out of window callback */
/* Level out of window 1 callback */
HAL_ADC_LevelOutOfWindowCallback(hadc);
/* Clear ADC Analog watchdog flag */
@ -1510,10 +1523,11 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
/* Clear the Overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
}
/**
* @brief Conversion complete callback in non blocking mode
* @brief Conversion complete callback in non-blocking mode.
* @param hadc: ADC handle
* @retval None
*/
@ -1528,7 +1542,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
}
/**
* @brief Conversion DMA half-transfer callback in non blocking mode
* @brief Conversion DMA half-transfer callback in non-blocking mode.
* @param hadc: ADC handle
* @retval None
*/
@ -1543,7 +1557,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
}
/**
* @brief Analog watchdog callback in non blocking mode.
* @brief Analog watchdog 1 callback in non-blocking mode.
* @param hadc: ADC handle
* @retval None
*/
@ -1553,13 +1567,19 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_LevelOoutOfWindowCallback must be implemented in the user file.
function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
*/
}
/**
* @brief ADC error callback in non blocking mode
* (ADC conversion with interruption or transfer by DMA)
* @brief ADC error callback in non-blocking mode
* (ADC conversion with interruption or transfer by DMA).
* @note In case of error due to overrun when using ADC with DMA transfer
* (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
* - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
* - If needed, restart a new ADC conversion using function
* "HAL_ADC_Start_DMA()"
* (this function is also clearing overrun flag)
* @param hadc: ADC handle
* @retval None
*/
@ -1577,7 +1597,7 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group3
/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
@ -1592,10 +1612,8 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
* @{
*/
/**
* @brief Configures the the selected channel to be linked to the regular
* group.
* @brief Configure a channel to be assigned to ADC group regular.
* @note In case of usage of internal measurement channels:
* VrefInt/Vlcd(STM32L0x3xx only)/TempSensor.
* Sampling time constraints must be respected (sampling time can be
@ -1606,15 +1624,14 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
* These internal paths can be be disabled using function
* HAL_ADC_DeInit().
* @note Possibility to update parameters on the fly:
* This function initializes channel into regular group, following
* calls to this function can be used to reconfigure some parameters
* of structure "ADC_ChannelConfTypeDef" on the fly, without reseting
* the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_ChannelConfTypeDef".
* This function initializes channel into ADC group regular,
* following calls to this function can be used to reconfigure
* some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
* without resetting the ADC.
* The setting of these parameters is conditioned to ADC state:
* Refer to comments of structure "ADC_ChannelConfTypeDef".
* @param hadc: ADC handle
* @param sConfig: Structure of ADC channel for regular group.
* @param sConfig: Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
@ -1711,15 +1728,23 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
}
/**
* @brief Configures the analog watchdog.
* @brief Configure the analog watchdog.
* @note Possibility to update parameters on the fly:
* This function initializes the selected analog watchdog, following
* This function initializes the selected analog watchdog, successive
* calls to this function can be used to reconfigure some parameters
* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without reseting
* of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
* the ADC.
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_AnalogWDGConfTypeDef".
* @note Analog watchdog thresholds can be modified while ADC conversion
* is on going.
* In this case, some constraints must be taken into account:
* the programmed threshold values are effective from the next
* ADC EOC (end of unitary conversion).
* Considering that registers write delay may happen due to
* bus activity, this might cause an uncertainty on the
* effective timing of the new programmed threshold values.
* @param hadc: ADC handle
* @param AnalogWDGConfig: Structure of ADC analog watchdog configuration
* @retval HAL status
@ -1734,18 +1759,17 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
/* Verify if threshold is within the selected ADC resolution */
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
{
assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
}
/* Verify if threshold is within the selected ADC resolution */
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
/* Process locked */
__HAL_LOCK(hadc);
@ -1793,6 +1817,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
/* Set the low threshold */
hadc->Instance->TR |= tmpAWDLowThresholdShifted;
}
/* If a conversion is on going on regular group, no update could be done */
/* on neither of the AWD configuration structure parameters. */
else
{
/* Update ADC state machine to error */
@ -1801,7 +1827,6 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
tmp_hal_status = HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
@ -1809,51 +1834,60 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
return tmp_hal_status;
}
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group4
/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
* @brief ADC Peripheral State functions
*
@verbatim
===============================================================================
##### ADC Peripheral State functions #####
##### Peripheral state and errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the ADC state.
(+) handle ADC interrupt request.
This subsection provides functions to get in run-time the status of the
peripheral.
(+) Check the ADC state
(+) Check the ADC error code
@endverbatim
* @{
*/
/**
* @brief return the ADC state
* @brief Return the ADC handle state.
* @note ADC state machine is managed by bitfields, ADC status must be
* compared with states bits.
* For example:
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
* @param hadc: ADC handle
* @retval HAL state
* @retval ADC handle state (bitfield on 32 bits)
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Return ADC state */
/* Return ADC handle state */
return hadc->State;
}
/**
* @brief Return the ADC error code
* @brief Return the ADC error code.
* @param hadc: ADC handle
* @retval ADC Error Code
* @retval ADC error code (bitfield on 32 bits)
*/
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
return hadc->ErrorCode;
}
/**
* @}
*/
@ -1862,8 +1896,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
* @}
*/
/** @addtogroup ADC_Private
/** @defgroup ADC_Private_Functions ADC Private Functions
* @{
*/
@ -1914,7 +1947,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
/* Wait for ADC effectively enabled */
while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@ -1925,7 +1958,6 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
return HAL_ERROR;
}
}
}
/* Return HAL status */
@ -1946,7 +1978,7 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if (ADC_IS_ENABLE(hadc) != RESET )
if (ADC_IS_ENABLE(hadc) != RESET)
{
/* Check if conditions to disable the ADC are fulfilled */
if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
@ -1971,7 +2003,7 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
{
if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@ -1988,6 +2020,7 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
return HAL_OK;
}
/**
* @brief Stop ADC conversion.
* @note Prerequisite condition to use this function: ADC conversions must be
@ -2040,6 +2073,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc)
return HAL_OK;
}
/**
* @brief DMA transfer complete callback.
* @param hdma: pointer to DMA handle.
@ -2092,13 +2126,12 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
/* Conversion complete callback */
HAL_ADC_ConvCpltCallback(hadc);
}
}
else
{
/* Call DMA error callback */
hadc->DMA_Handle->XferErrorCallback(hdma);
}
}
/**
@ -2116,7 +2149,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
}
/**
* @brief DMA error callback
* @brief DMA error callback.
* @param hdma: pointer to DMA handle.
* @retval None
*/
@ -2151,17 +2184,13 @@ static void ADC_DelayMicroSecond(uint32_t microSecond)
}
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

434
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.h
View File

@ -2,10 +2,7 @@
******************************************************************************
* @file stm32l0xx_hal_adc.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
@ -37,8 +34,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L0xx_ADC_H
#define __STM32L0xx_ADC_H
#ifndef __STM32L0xx_HAL_ADC_H
#define __STM32L0xx_HAL_ADC_H
#ifdef __cplusplus
extern "C" {
@ -51,142 +48,234 @@
* @{
*/
/** @defgroup ADC ADC
* @{
*/
/** @defgroup ADC_Exported_Types ADC Exported Types
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
* @brief ADC Oversampler structure definition
* @brief ADC group regular oversampling structure definition
*/
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_Oversampling_Ratio */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_Right_Bit_Shift */
uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode
This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
}ADC_OversamplingTypeDef;
/**
* @brief ADC Init structure definition
* @note The setting of these parameters with function HAL_ADC_Init() is conditioned by the ADC state.
* @brief Structure definition of ADC instance and ADC group regular.
* @note Parameters of this structure are shared within 2 scopes:
* - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
* ScanConvMode, EOCSelection, LowPowerAutoWait.
* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
* - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly).
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
* (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator) and clock prescaler.
This parameter can be a value of @ref ADC_ClockPrescaler.
Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level.
Note: This parameter can be modified only if the ADC is disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
Refer to reference manual for alignments formats versus resolutions.
This parameter can be a value of @ref ADC_Data_align */
uint32_t ScanConvMode; /*!< Configure the sequencer of regular group.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
If only 1 channel is set: Conversion is performed in single mode.
If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0).
This parameter can be a value of @ref ADC_Scan_mode */
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
This parameter can be a value of @ref ADC_EOCSelection. */
uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
conversion (for ADC group regular) has been retrieved by user software,
using function HAL_ADC_GetValue().
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
ADC_OversamplingTypeDef Oversample; /*!< Specifies the Oversampling parameters
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t ClockPrescaler; /*!< Selects the ADC clock frequency.
This parameter can be a value of @ref ADC_ClockPrescaler
Note: This parameter can be modified only if ADC is disabled.
Note: In case of Synchronous clock mode divided by 1, this configuration must be enabled only
if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC
must be bypassed and the system clock must by 50% duty cycle). Refer to reference manual for details */
uint32_t Resolution; /*!< Configures the ADC resolution mode.
This parameter can be a value of @ref ADC_Resolution
Note: This parameter can be modified only if ADC is disabled. */
uint32_t SamplingTime; /*!< The sample time value to be set for all channels.
This parameter can be a value of @ref ADC_sampling_times
Note: This parameter can be modified only if there is no conversion ongoing. */
uint32_t ScanConvMode; /*!< The scan sequence direction.
If several channels are set: Conversions are performed in sequence mode
(ranks defined by each channel number: channel 0 fixed on rank 0,
channel 1 fixed on rank1, ...).
This parameter can be a value of @ref ADC_Scan_mode
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
to free the IRQ vector sequencer.
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
uint32_t LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed
in Complete-sequence/Discontinuous-sequence.
Discontinuous mode can be enabled only if continuous mode is disabled.
Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
(main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
If set to ADC_SOFTWARE_START, external triggers are disabled.
This parameter can be a value of @ref ADC_External_trigger_Source
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer max pointer is reached.
Note: On this STM32 serie, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
This parameter can be a value of @ref ADC_regular_external_trigger_source.
Caution: external trigger source is common to all ADC instances. */
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
or in continuous mode (DMA transfer unlimited, whatever number of conversions).
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion polling and interruption:
end of single channel conversion or end of channels conversions sequence.
This parameter can be a value of @ref ADC_EOCSelection */
uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
This parameter has an effect on regular channels only, including in DMA mode.
This parameter can be a value of @ref ADC_Overrun
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t LowPowerAutoWait; /*!< Specifies the usage of dynamic low power Auto Delay: new conversion start only
when the previous conversion (for regular channel) is completed.
This avoids risk of overrun for low frequency application.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter can be a value of @ref ADC_Overrun.
Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
Note: Error reporting with respect to the conversion mode:
- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
it is mandatory to first enable the Low Frequency Mode.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
uint32_t LowPowerAutoPowerOff; /*!< When setting the AutoOff feature, the ADC is always powered off when not converting and automatically
wakes-up when a conversion is started (by software or hardware trigger).
uint32_t SamplingTime; /*!< The sample time common to all channels.
Unit: ADC clock cycles
This parameter can be a value of @ref ADC_sampling_times
Note: This parameter can be modified only if there is no conversion ongoing. */
uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing. */
Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
ADC_OversamplingTypeDef Oversample; /*!< Specify the Oversampling parameters
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
}ADC_InitTypeDef;
/**
* @brief Structure definition of ADC channel for regular group
* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled or enabled without conversion on going on regular group.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
This parameter can be a value of @ref ADC_rank */
}ADC_ChannelConfTypeDef;
/**
* @brief Structure definition of ADC analog watchdog
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC group regular
* - For parameters 'HighThreshold' and 'LowThreshold': ADC enabled with conversion on going on regular group (AWD thresholds can be modify on the fly while ADC conversion is on going)
*/
typedef struct
{
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all channels.
This parameter can be a value of @ref ADC_analog_watchdog_mode */
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
This parameter can be a value of @ref ADC_channels */
uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
}ADC_AnalogWDGConfTypeDef;
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
* @note ADC state machine is managed by bitfields, state must be compared
* with bit by bit.
* For example:
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy due to an internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on this STM32 serie: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on this STM32 serie: Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on this STM32 serie: Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available) */
/**
* @brief ADC handle Structure definition
*/
@ -204,43 +293,6 @@ typedef struct
__IO uint32_t ErrorCode; /*!< ADC Error code */
}ADC_HandleTypeDef;
/**
* @brief ADC Configuration regular Channel structure definition
*/
typedef struct
{
uint32_t Channel; /*!< the ADC channel to configure
This parameter can be a value of @ref ADC_channels */
uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
This parameter can be a value of @ref ADC_rank */
}ADC_ChannelConfTypeDef;
/**
* @brief ADC Configuration analog watchdog definition
*/
typedef struct
{
uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels.
This parameter can be a value of @ref ADC_analog_watchdog_mode */
uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
This parameter can be a value of @ref ADC_channels */
uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits),
this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
}ADC_AnalogWDGConfTypeDef;
/**
* @}
*/
@ -256,9 +308,9 @@ typedef struct
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< OVR error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error (problem of clocking,
enable/disable, erroneous state, ...) */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
/**
* @}
@ -322,17 +374,16 @@ typedef struct
* @}
*/
/** @defgroup ADC_data_align ADC Data Align
/** @defgroup ADC_Data_align ADC conversion data alignment
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
/**
* @}
*/
/** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
/** @defgroup ADC_regular_external_trigger_edge ADC External Trigger Source Edge for Regular Group
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
@ -417,24 +468,21 @@ typedef struct
* @}
*/
/** @defgroup ADC_sampling_times ADC Sampling Cycles
* @{
*/
#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< ADC sampling time 1.5 cycle */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 7.5 CYCLES */
#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 13.5 CYCLES */
#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 28.5 CYCLES */
#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /*!< ADC sampling time 41.5 CYCLES */
#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 55.5 CYCLES */
#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 71.5 CYCLES */
#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 239.5 CYCLES */
#define ADC_SAMPLETIME_3CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 3.5 CYCLES */
#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 7.5 CYCLES */
#define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 12.5 CYCLES */
#define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /*!< ADC sampling time 19.5 CYCLES */
#define ADC_SAMPLETIME_39CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 39.5 CYCLES */
#define ADC_SAMPLETIME_79CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 79.5 CYCLES */
#define ADC_SAMPLETIME_160CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 160.5 CYCLES */
/**
* @}
*/
/** @defgroup ADC_Scan_mode ADC Scan mode
* @{
*/
@ -539,12 +587,10 @@ typedef struct
* @}
*/
/** @defgroup ADC_flags_definition ADC Flags Definition
/** @defgroup ADC_flags_definition ADC flags definition
* @{
*/
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
#define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */
@ -562,9 +608,11 @@ typedef struct
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Macro ADC Exported Macro
/** @defgroup ADC_Exported_Macros ADC Exported Macros
* @{
*/
/** @brief Reset ADC handle state
@ -813,8 +861,6 @@ typedef struct
((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
/**
* @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
* @param __HANDLE__: ADC handle
@ -925,13 +971,13 @@ typedef struct
#endif
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \
((TIME) == ADC_SAMPLETIME_3CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_239CYCLES_5))
((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) || \
((TIME) == ADC_SAMPLETIME_160CYCLES_5))
#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \
((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
@ -989,22 +1035,23 @@ typedef struct
* @}
*/
/**
/**
* @}
*/
/* Include ADC HAL Extension module */
/* Include ADC HAL Extended module */
#include "stm32l0xx_hal_adc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup ADC_Exported_Functions ADC Exported Functions
/** @addtogroup ADC_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions **********************************/
/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
/** @addtogroup ADC_Exported_Functions_Group1
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
@ -1013,10 +1060,12 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
* @}
*/
/* IO operation functions *****************************************************/
/** @defgroup ADC_Exported_Functions_Group2 I/O operation functions
/** @addtogroup ADC_Exported_Functions_Group2
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
@ -1044,10 +1093,11 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
/**
@ -1055,7 +1105,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_Analog
*/
/* Peripheral State functions *************************************************/
/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
/** @addtogroup ADC_Exported_Functions_Group4
* @{
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
@ -1069,16 +1119,6 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
* @}
*/
/* Define the private group ***********************************/
/**************************************************************/
/** @defgroup ADC_Private ADC Private
* @{
*/
/**
* @}
*/
/**************************************************************/
/**
* @}
*/
@ -1091,7 +1131,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
}
#endif
#endif /*__STM32L0xx_ADC_H */
#endif /*__STM32L0xx_HAL_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

103
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.c
View File

@ -2,33 +2,21 @@
******************************************************************************
* @file stm32l0xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
* + Start calibration.
* + Read the calibration factor.
* + Set a calibration factor.
* + Operation functions
* ++ Calibration
* +++ ADC automatic self-calibration
* +++ Calibration factors get or set
* Other functions (generic functions) are available in file
* "stm32l0xx_hal_adc.c".
*
@verbatim
==============================================================================
##### ADC specific features #####
==============================================================================
[..]
(#) Self calibration.
##### How to use this driver #####
==============================================================================
(@) Sections "ADC peripheral features" and "How to use this driver" are
available in file of generic functions "stm32l0xx_hal_adc.c".
[..]
(#) Call HAL_ADCEx_Calibration_Start() to start calibration
(#) Read the calibration factor using HAL_ADCEx_Calibration_GetValue()
(#) User can set a his calibration factor using HAL_ADCEx_Calibration_SetValue()
@endverbatim
******************************************************************************
* @attention
@ -67,18 +55,21 @@
* @{
*/
#ifdef HAL_ADC_MODULE_ENABLED
/** @addtogroup ADCEx
* @brief ADC driver modules
/** @defgroup ADCEx ADCEx
* @brief ADC Extended HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
#ifdef HAL_ADC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Fixed timeout values for ADC calibration, enable settling time, disable */
/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
* @{
*/
/* Fixed timeout values for ADC calibration, enable settling time, disable */
/* settling time. */
/* Values defined to be higher than worst cases: low clock frequency, */
/* maximum prescaler. */
@ -98,38 +89,32 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
* @{
*/
/** @addtogroup ADCEx_Exported_Functions
* @brief ADC Extended features functions
/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
* @brief Extended IO operation functions
*
@verbatim
===============================================================================
##### ADC Extended features functions #####
##### IO operation functions #####
===============================================================================
[..]
This subsection provides functions allowing to:
(+) Start calibration.
(+) Get calibration factor.
(+) Set calibration factor.
(+) Enable VREFInt.
(+) Disable VREFInt.
(+) Enable VREFInt TempSensor.
(+) Disable VREFInt TempSensor.
[..] This section provides functions allowing to:
(+) Perform the ADC calibration.
@endverbatim
* @{
*/
/** @addtogroup ADCEx_Exported_Functions_Group3
* @{
*/
/**
* @brief Start an automatic calibration
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @brief Perform an ADC automatic self-calibration
* Calibration prerequisite: ADC must be disabled (execute this
* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
* @note Calibration factor can be read after calibration, using function
* HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
* @param hadc ADC handle
* @param SingleDiff: Selection of single-ended or differential input
* This parameter can be only of the following values:
* @arg ADC_SINGLE_ENDED: Channel in mode input single ended
@ -138,7 +123,8 @@ This subsection provides functions allowing to:
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tickstart=0U;
uint32_t tickstart = 0U;
uint32_t backup_setting_adc_dma_transfer = 0U; /* Note: Variable not declared as volatile because register read is already declared as volatile */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@ -154,6 +140,15 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Disable ADC DMA transfer request during calibration */
/* Note: Specificity of this STM32 serie: Calibration factor is */
/* available in data register and also transfered by DMA. */
/* To not insert ADC calibration factor among ADC conversion data */
/* in array variable, DMA transfer must be disabled during */
/* calibration. */
backup_setting_adc_dma_transfer = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG);
/* Start ADC calibration */
hadc->Instance->CR |= ADC_CR_ADCAL;
@ -176,6 +171,9 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
}
}
/* Restore ADC DMA transfer request after calibration */
SET_BIT(hadc->Instance->CFGR1, backup_setting_adc_dma_transfer);
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_BUSY_INTERNAL,
@ -196,7 +194,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
return tmp_hal_status;
}
/**
* @brief Get the calibration factor.
* @param hadc: ADC handle.
@ -352,13 +349,13 @@ void HAL_ADCEx_DisableVREFINTTempSensor(void)
* @}
*/
/**
* @}
*/
#endif /* HAL_ADC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

33
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc_ex.h
View File

@ -2,10 +2,7 @@
******************************************************************************
* @file stm32l0xx_hal_adc_ex.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
* @brief Header file of ADC HAL extended module.
******************************************************************************
* @attention
*
@ -37,8 +34,8 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32L0xx_ADC_EX_H
#define __STM32L0xx_ADC_EX_H
#ifndef __STM32L0xx_HAL_ADC_EX_H
#define __STM32L0xx_HAL_ADC_EX_H
#ifdef __cplusplus
extern "C" {
@ -51,14 +48,14 @@
* @{
*/
/** @defgroup ADCEx ADCEx
* @brief ADC driver modules
/** @addtogroup ADCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
* @{
*/
@ -70,7 +67,7 @@
* @}
*/
/** @defgroup ADC_External_trigger_Source ADC External Trigger Source
/** @defgroup ADC_regular_external_trigger_source ADC External Trigger Source
* @{
*/
#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000U)
@ -185,18 +182,22 @@
* @}
*/
/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADCEx_Exported_Functions
* @{
*/
/** @defgroup ADCEx_Exported_Functions_Group3 Peripheral Control functions
/** @addtogroup ADCEx_Exported_Functions_Group1
* @{
*/
/* Exported functions --------------------------------------------------------*/
/* Peripheral Control functions ***********************************************/
/* IO operation functions *****************************************************/
/* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
/* ADC VrefInt and Temperature sensor functions specific to this STM32 serie */
HAL_StatusTypeDef HAL_ADCEx_EnableVREFINT(void);
void HAL_ADCEx_DisableVREFINT(void);
HAL_StatusTypeDef HAL_ADCEx_EnableVREFINTTempSensor(void);
@ -209,6 +210,7 @@ void HAL_ADCEx_DisableVREFINTTempSensor(void);
* @}
*/
/**
* @}
*/
@ -221,8 +223,7 @@ void HAL_ADCEx_DisableVREFINTTempSensor(void);
}
#endif
#endif /*__STM32L0xx_ADC_H */
#endif /*__STM32L0xx_HAL_ADC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

72
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.c
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_comp.c
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
@ -320,41 +318,45 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
/* Note : COMP1 can be connected to the input 1 of LPTIM if requested */
assert_param(IS_COMP1_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
if (hcomp->Init.LPTIMConnection == COMP_LPTIMCONNECTION_IN1_ENABLED)
{
/* Note: Compatibility with previous driver version using */
/* generic literal COMP_LPTIMCONNECTION_ENABLED corresponding */
/* to LPTIM input 1 for COMP1. */
tmp_csr |= (COMP_CSR_COMP1LPTIM1IN1);
}
}
else
{
/* Check the MCU_ID in order to allow or not the COMP2 connection to LPTIM-input2 */
if (((HAL_GetDEVID() == C_DEV_ID_L073) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_Z)))
{
/* Note : COMP2 can be connected only to input 1 of LPTIM if requested */
assert_param(IS_COMP2_LPTIMCONNECTION_RESTRICTED(hcomp->Init.LPTIMConnection));
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN1);
}
/* LPTIM connexion requested on COMP2 */
else
{
/* Note : COMP2 can be connected to input 1 or input2 of LPTIM if requested */
/* Note : COMP2 can be connected to input 1 or input 2 of LPTIM if requested */
assert_param(IS_COMP2_LPTIMCONNECTION(hcomp->Init.LPTIMConnection));
switch (hcomp->Init.LPTIMConnection)
{
case COMP_LPTIMCONNECTION_IN1_ENABLED :
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN1);
break;
case COMP_LPTIMCONNECTION_IN2_ENABLED :
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN2);
break;
default :
break;
/* Note: Default case for compatibility with previous driver version*/
/* using generic literal COMP_LPTIMCONNECTION_ENABLED corresponding */
/* to LPTIM input 2 for COMP2. */
/* Check the MCU_ID in order to allow or not the COMP2 connection to LPTIM input 2 */
if (((HAL_GetDEVID() == C_DEV_ID_L073) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_A))
||
((HAL_GetDEVID() == C_DEV_ID_L053) && (HAL_GetREVID() == C_REV_ID_Z)))
{
assert_param(IS_COMP2_LPTIMCONNECTION_RESTRICTED(hcomp->Init.LPTIMConnection));
/* Error: On the selected device, COMP2 cannot be connected to LPTIM input 2 */
status = HAL_ERROR;
}
else
{
tmp_csr |= (COMP_CSR_COMP2LPTIM1IN2);
}
break;
}
}
}
@ -442,8 +444,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
}
else
{
/* Disable EXTI event generation */
/* Disable EXTI event mode */
CLEAR_BIT(EXTI->EMR, exti_line);
/* Disable EXTI interrupt mode */
CLEAR_BIT(EXTI->IMR, exti_line);
}
/* Set HAL COMP handle state */
@ -641,8 +646,23 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
/* Check COMP EXTI flag */
if(READ_BIT(EXTI->PR, exti_line) != RESET)
{
/* Clear COMP EXTI pending bit */
/* Check whether comparator is in independent or window mode */
if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0)
{
/* Clear COMP EXTI line pending bit of the pair of comparators */
/* in window mode. */
/* Note: Pair of comparators in window mode can both trig IRQ when */
/* input voltage is changing from "out of window" area */
/* (low or high ) to the other "out of window" area (high or low).*/
/* Both flags must be cleared to call comparator trigger */
/* callback is called once. */
WRITE_REG(EXTI->PR, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI->PR, exti_line);
}
/* COMP trigger user callback */
HAL_COMP_TriggerCallback(hcomp);

4
targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_comp.h
View File

@ -2,8 +2,6 @@
******************************************************************************
* @file stm32l0xx_hal_comp.h
* @author MCD Application Team
* @version V1.7.0
* @date 31-May-2016
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
@ -586,7 +584,7 @@ typedef struct
((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN2_ENABLED))
#define IS_COMP2_LPTIMCONNECTION_RESTRICTED(LPTIMCONNECTION) (((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_DISABLED) || \
((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN2_ENABLED))
((LPTIMCONNECTION) == COMP_LPTIMCONNECTION_IN1_ENABLED))
#define IS_COMP_OUTPUTPOL(POL) (((POL) == COMP_OUTPUTPOL_NONINVERTED) || \
((POL) == COMP_OUTPUTPOL_INVERTED))

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