From 4b3412c5e5395fe93de34fa2c93443c0ca2706b2 Mon Sep 17 00:00:00 2001 From: Rob Meades Date: Thu, 1 Mar 2018 14:52:42 +0000 Subject: [PATCH 001/118] Call i2c_init() before i2c_frequency() (since i2c_frequency() requires the object to be set up) and zero the I2C object before giving it to i2c_init() as i2_init() has to set up a default frequency for its timeouts to work and it will only do this if the hz field in the object was zero to begin with (otherwise you end up with a random but usually very large indeed timeout). --- .../TARGET_UBLOX_C030/min_battery_voltage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.c index 396a26483f..44d77f5459 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.c @@ -27,10 +27,10 @@ void HAL_MspInit(void) void set_minimum_battery_voltage() { - i2c_t i2c_obj; + i2c_t i2c_obj = {0}; int data_read; - i2c_frequency(&i2c_obj, I2C_FREQUENCY); i2c_init(&i2c_obj, I2C_SDA_B, I2C_SCL_B); + i2c_frequency(&i2c_obj, I2C_FREQUENCY); if (read_from_i2c(BQ24295_I2C_ADDRESS, 0, &data_read, i2c_obj)) { data_read = data_read & MIN_BATTERY_VOLTAGE_MASK; From 99a250e9d89aea912e3d3d07a4c42100f1210f8d Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 22 Feb 2018 14:26:10 +0800 Subject: [PATCH 002/118] Rework us_ticker and lp_ticker with one H/W timer Originally, we use 2 H/W timers for us_ticker/lp_ticker, one for counting and the other for alarm. With H/W timer running in continuous mode, we could use just one H/W timer for counting/alarm simultaneously. --- .../TARGET_NUVOTON/TARGET_M451/lp_ticker.c | 205 +++++------------ .../TARGET_NUVOTON/TARGET_M451/us_ticker.c | 190 ++++------------ .../TARGET_NUVOTON/TARGET_M480/lp_ticker.c | 208 +++++------------- .../TARGET_NUVOTON/TARGET_M480/us_ticker.c | 193 ++++------------ .../TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c | 206 +++++------------ .../TARGET_NUVOTON/TARGET_NANO100/us_ticker.c | 192 ++++------------ .../TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c | 204 +++++------------ .../TARGET_NUVOTON/TARGET_NUC472/us_ticker.c | 189 ++++------------ 8 files changed, 406 insertions(+), 1181 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c index f8c3a71692..0ae86455d8 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c @@ -35,18 +35,14 @@ /* Timer max counter */ #define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) -static void tmr2_vec(void); -static void tmr3_vec(void); -/* Configure scheduled alarm */ -static void arm_alarm(uint32_t cd_clk); - -static int ticker_inited = 0; -static uint32_t ticker_last_read_clk = 0; +static void tmr1_vec(void); /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ -/* NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled alarm */ -static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec}; -static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec}; +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; + +#define TIMER_MODINIT timer1_modinit + +static int ticker_inited = 0; #define TMR_CMP_MIN 2 #define TMR_CMP_MAX 0xFFFFFFu @@ -58,43 +54,37 @@ void lp_ticker_init(void) } ticker_inited = 1; - ticker_last_read_clk = 0; - // Reset module - SYS_ResetModule(timer2_modinit.rsetidx); - SYS_ResetModule(timer3_modinit.rsetidx); + SYS_ResetModule(TIMER_MODINIT.rsetidx); // Select IP clock source - CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv); - CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv); + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + // Enable IP clock - CLK_EnableModuleClock(timer2_modinit.clkidx); - CLK_EnableModuleClock(timer3_modinit.clkidx); + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); // Configure clock - uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - uint32_t prescale_timer2 = clk_timer2 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127); - MBED_ASSERT((clk_timer2 % NU_TMRCLK_PER_SEC) == 0); - uint32_t cmp_timer2 = TMR_CMP_MAX; - MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX); + uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); // Continuous mode // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default. - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/; - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer; // Set vector - NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var); - NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var); + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); - NVIC_EnableIRQ(timer2_modinit.irq_n); - NVIC_EnableIRQ(timer3_modinit.irq_n); + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); - TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); + TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); - TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); + TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } timestamp_t lp_ticker_read() @@ -103,145 +93,49 @@ timestamp_t lp_ticker_read() lp_ticker_init(); } - TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname); + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - ticker_last_read_clk = TIMER_GetCounter(timer2_base); - return (ticker_last_read_clk / NU_TMRCLK_PER_TICK); + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); } void lp_ticker_set_interrupt(timestamp_t timestamp) { - TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - /* We need to get alarm interval from alarm timestamp `timestamp` to configure H/W timer. - * - * Because both `timestamp` and xx_ticker_read() would wrap around, we have difficulties in distinguishing - * long future event and past event. To distinguish them, we need `tick_last_read` against which - * `timestamp` is calculated out. In timeline, we would always have below after fixing wrap-around: - * (1) tick_last_read <= present_clk - * (2) tick_last_read <= alarm_ts_clk - * - * - * 1. Future event case: - * - * tick_last_read present_clk alarm_ts_clk - * | | | - * -------------------------------------------------------- - * |-alarm_intvl1_clk-| - * |-------------------alarm_intvl2_clk-------------------| - * - * 2. Past event case: - * - * tick_last_read alarm_ts_clk present_clk - * | | | - * -------------------------------------------------------- - * |-------------------alarm_intvl1_clk-------------------| - * |-alarm_intvl2_clk-| - * - * Unfortunately, `tick_last_read` is not passed along the xx_ticker_set_interrupt() call. To solve it, we - * assume that `tick_last_read` tick is exactly the one returned by the last xx_ticker_read() call before - * xx_ticker_set_interrupt() is invoked. With this assumption, we can hold it via `xx_ticker_last_read_clk` - * in xx_ticker_read(). - */ - - /* ticker_last_read_clk will update in lp_ticker_read(). Keep it beforehand. */ - uint32_t last_read_clk = ticker_last_read_clk; - uint32_t present_clk = lp_ticker_read() * NU_TMRCLK_PER_TICK; - uint32_t alarm_ts_clk = timestamp * NU_TMRCLK_PER_TICK; - uint32_t alarm_intvl1_clk, alarm_intvl2_clk; - - /* alarm_intvl1_clk = present_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (present_clk >= last_read_clk) { - alarm_intvl1_clk = present_clk - last_read_clk; - } else { - alarm_intvl1_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + present_clk - last_read_clk); - } + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; - /* alarm_intvl2_clk = alarm_ts_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (alarm_ts_clk >= last_read_clk) { - alarm_intvl2_clk = alarm_ts_clk - last_read_clk; - } else { - alarm_intvl2_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + alarm_ts_clk - last_read_clk); - } - - /* Distinguish (long) future event and past event - * - * NOTE: No '=' sign here. Alarm should go off immediately in equal case. - */ - if (alarm_intvl2_clk > alarm_intvl1_clk) { - /* Schedule for future event */ - arm_alarm(alarm_intvl2_clk - alarm_intvl1_clk); - } else { - /* Go off immediately for past event, including equal case */ - lp_ticker_fire_interrupt(); - } + /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ + wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + TIMER_Start(timer_base); } void lp_ticker_disable_interrupt(void) { - TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void lp_ticker_clear_interrupt(void) { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void lp_ticker_fire_interrupt(void) { // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. // This prevents a recursive loop under heavy load which can lead to a stack overflow. - NVIC_SetPendingIRQ(timer3_modinit.irq_n); -} - -static void tmr2_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); -} - -static void tmr3_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - - // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); - lp_ticker_irq_handler(); - -} - -static void arm_alarm(uint32_t cd_clk) -{ - TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname); - - // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit - timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk; - // One-shot mode, Clock = 1 KHz - uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - uint32_t prescale_timer3 = clk_timer3 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127); - MBED_ASSERT((clk_timer3 % NU_TMRCLK_PER_SEC) == 0); - // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default. - timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/); - timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/; - - /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of - * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ - uint32_t cmp_timer3 = cd_clk; - cmp_timer3 = NU_CLAMP(cmp_timer3, TMR_CMP_MIN, TMR_CMP_MAX); - timer3_base->CMP = cmp_timer3; - - TIMER_EnableInt(timer3_base); - TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ - wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); - TIMER_Start(timer3_base); + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); } const ticker_info_t* lp_ticker_get_info() @@ -253,4 +147,13 @@ const ticker_info_t* lp_ticker_get_info() return &info; } +static void tmr1_vec(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + + // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); + lp_ticker_irq_handler(); +} + #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c index 8b8d4efc2d..7f451bd336 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c @@ -32,16 +32,12 @@ #define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) static void tmr0_vec(void); -static void tmr1_vec(void); -/* Configure scheduled alarm */ -static void arm_alarm(uint32_t cd_clk); + +static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; + +#define TIMER_MODINIT timer0_modinit static int ticker_inited = 0; -static uint32_t ticker_last_read_clk = 0; - -/* NOTE: TIMER_0 for normal counting and TIMER_1 for scheduled alarm. */ -static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; -static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; #define TMR_CMP_MIN 2 #define TMR_CMP_MAX 0xFFFFFFu @@ -53,38 +49,32 @@ void us_ticker_init(void) } ticker_inited = 1; - ticker_last_read_clk = 0; - // Reset IP - SYS_ResetModule(timer0hires_modinit.rsetidx); - SYS_ResetModule(timer1hires_modinit.rsetidx); + SYS_ResetModule(TIMER_MODINIT.rsetidx); // Select IP clock source - CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv); - CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv); + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + // Enable IP clock - CLK_EnableModuleClock(timer0hires_modinit.clkidx); - CLK_EnableModuleClock(timer1hires_modinit.clkidx); + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); // Timer for normal counter - uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - uint32_t prescale_timer0 = clk_timer0 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127); - MBED_ASSERT((clk_timer0 % NU_TMRCLK_PER_SEC) == 0); - uint32_t cmp_timer0 = TMR_CMP_MAX; - MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX); + uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default. - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/; - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer; - NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var); - NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var); + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); - NVIC_EnableIRQ(timer0hires_modinit.irq_n); - NVIC_EnableIRQ(timer1hires_modinit.irq_n); + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); - TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); + TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } uint32_t us_ticker_read() @@ -93,139 +83,45 @@ uint32_t us_ticker_read() us_ticker_init(); } - TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname); + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - ticker_last_read_clk = TIMER_GetCounter(timer0_base); - return (ticker_last_read_clk / NU_TMRCLK_PER_TICK); + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); } void us_ticker_set_interrupt(timestamp_t timestamp) { - TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - /* We need to get alarm interval from alarm timestamp `timestamp` to configure H/W timer. - * - * Because both `timestamp` and xx_ticker_read() would wrap around, we have difficulties in distinguishing - * long future event and past event. To distinguish them, we need `tick_last_read` against which - * `timestamp` is calculated out. In timeline, we would always have below after fixing wrap-around: - * (1) tick_last_read <= present_clk - * (2) tick_last_read <= alarm_ts_clk - * - * - * 1. Future event case: - * - * tick_last_read present_clk alarm_ts_clk - * | | | - * -------------------------------------------------------- - * |-alarm_intvl1_clk-| - * |-------------------alarm_intvl2_clk-------------------| - * - * 2. Past event case: - * - * tick_last_read alarm_ts_clk present_clk - * | | | - * -------------------------------------------------------- - * |-------------------alarm_intvl1_clk-------------------| - * |-alarm_intvl2_clk-| - * - * Unfortunately, `tick_last_read` is not passed along the xx_ticker_set_interrupt() call. To solve it, we - * assume that `tick_last_read` tick is exactly the one returned by the last xx_ticker_read() call before - * xx_ticker_set_interrupt() is invoked. With this assumption, we can hold it via `xx_ticker_last_read_clk` - * in xx_ticker_read(). - */ - - /* ticker_last_read_clk will update in us_ticker_read(). Keep it beforehand. */ - uint32_t last_read_clk = ticker_last_read_clk; - uint32_t present_clk = us_ticker_read() * NU_TMRCLK_PER_TICK; - uint32_t alarm_ts_clk = timestamp * NU_TMRCLK_PER_TICK; - uint32_t alarm_intvl1_clk, alarm_intvl2_clk; - - /* alarm_intvl1_clk = present_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (present_clk >= last_read_clk) { - alarm_intvl1_clk = present_clk - last_read_clk; - } else { - alarm_intvl1_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + present_clk - last_read_clk); - } - - /* alarm_intvl2_clk = alarm_ts_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (alarm_ts_clk >= last_read_clk) { - alarm_intvl2_clk = alarm_ts_clk - last_read_clk; - } else { - alarm_intvl2_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + alarm_ts_clk - last_read_clk); - } - - /* Distinguish (long) future event and past event - * - * NOTE: No '=' sign here. Alarm should go off immediately in equal case. - */ - if (alarm_intvl2_clk > alarm_intvl1_clk) { - /* Schedule for future event */ - arm_alarm(alarm_intvl2_clk - alarm_intvl1_clk); - } else { - /* Go off immediately for past event, including equal case */ - us_ticker_fire_interrupt(); - } + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; } void us_ticker_disable_interrupt(void) { - TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void us_ticker_clear_interrupt(void) { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void us_ticker_fire_interrupt(void) { // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. // This prevents a recursive loop under heavy load which can lead to a stack overflow. - NVIC_SetPendingIRQ(timer1hires_modinit.irq_n); -} - -static void tmr0_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); -} - -static void tmr1_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - - // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); - us_ticker_irq_handler(); -} - -static void arm_alarm(uint32_t cd_clk) -{ - TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname); - - // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit - timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk; - // One-shot mode, Clock = 1 MHz - uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - uint32_t prescale_timer1 = clk_timer1 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127); - MBED_ASSERT((clk_timer1 % NU_TMRCLK_PER_SEC) == 0); - // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default. - timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/); - timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/; - - /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of - * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ - uint32_t cmp_timer1 = cd_clk; - cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX); - timer1_base->CMP = cmp_timer1; - - TIMER_EnableInt(timer1_base); - TIMER_Start(timer1_base); + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); } const ticker_info_t* us_ticker_get_info() @@ -236,3 +132,11 @@ const ticker_info_t* us_ticker_get_info() }; return &info; } + +static void tmr0_vec(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + + // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); + us_ticker_irq_handler(); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c index f74e65b644..e1f71f59c3 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c @@ -35,18 +35,14 @@ /* Timer max counter */ #define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) -static void tmr2_vec(void); -static void tmr3_vec(void); -/* Configure scheduled alarm */ -static void arm_alarm(uint32_t cd_clk); - -static int ticker_inited = 0; -static uint32_t ticker_last_read_clk = 0; +static void tmr1_vec(void); /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ -/* NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled alarm */ -static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec}; -static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec}; +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; + +#define TIMER_MODINIT timer1_modinit + +static int ticker_inited = 0; #define TMR_CMP_MIN 2 #define TMR_CMP_MAX 0xFFFFFFu @@ -58,43 +54,37 @@ void lp_ticker_init(void) } ticker_inited = 1; - ticker_last_read_clk = 0; - // Reset module - SYS_ResetModule(timer2_modinit.rsetidx); - SYS_ResetModule(timer3_modinit.rsetidx); + SYS_ResetModule(TIMER_MODINIT.rsetidx); // Select IP clock source - CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv); - CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv); + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + // Enable IP clock - CLK_EnableModuleClock(timer2_modinit.clkidx); - CLK_EnableModuleClock(timer3_modinit.clkidx); + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); // Configure clock - uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - uint32_t prescale_timer2 = clk_timer2 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127); - MBED_ASSERT((clk_timer2 % NU_TMRCLK_PER_SEC) == 0); - uint32_t cmp_timer2 = TMR_CMP_MAX; - MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX); + uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); // Continuous mode // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default. - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/; - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer; // Set vector - NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var); - NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var); + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); - NVIC_EnableIRQ(timer2_modinit.irq_n); - NVIC_EnableIRQ(timer3_modinit.irq_n); + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); - TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); + TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); - TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); + TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } timestamp_t lp_ticker_read() @@ -103,148 +93,49 @@ timestamp_t lp_ticker_read() lp_ticker_init(); } - TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname); + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - ticker_last_read_clk = TIMER_GetCounter(timer2_base); - return (ticker_last_read_clk / NU_TMRCLK_PER_TICK); + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); } void lp_ticker_set_interrupt(timestamp_t timestamp) { - TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - /* We need to get alarm interval from alarm timestamp `timestamp` to configure H/W timer. - * - * Because both `timestamp` and xx_ticker_read() would wrap around, we have difficulties in distinguishing - * long future event and past event. To distinguish them, we need `tick_last_read` against which - * `timestamp` is calculated out. In timeline, we would always have below after fixing wrap-around: - * (1) tick_last_read <= present_clk - * (2) tick_last_read <= alarm_ts_clk - * - * - * 1. Future event case: - * - * tick_last_read present_clk alarm_ts_clk - * | | | - * -------------------------------------------------------- - * |-alarm_intvl1_clk-| - * |-------------------alarm_intvl2_clk-------------------| - * - * 2. Past event case: - * - * tick_last_read alarm_ts_clk present_clk - * | | | - * -------------------------------------------------------- - * |-------------------alarm_intvl1_clk-------------------| - * |-alarm_intvl2_clk-| - * - * Unfortunately, `tick_last_read` is not passed along the xx_ticker_set_interrupt() call. To solve it, we - * assume that `tick_last_read` tick is exactly the one returned by the last xx_ticker_read() call before - * xx_ticker_set_interrupt() is invoked. With this assumption, we can hold it via `xx_ticker_last_read_clk` - * in xx_ticker_read(). - */ - - /* ticker_last_read_clk will update in lp_ticker_read(). Keep it beforehand. */ - uint32_t last_read_clk = ticker_last_read_clk; - uint32_t present_clk = lp_ticker_read() * NU_TMRCLK_PER_TICK; - uint32_t alarm_ts_clk = timestamp * NU_TMRCLK_PER_TICK; - uint32_t alarm_intvl1_clk, alarm_intvl2_clk; - - /* alarm_intvl1_clk = present_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (present_clk >= last_read_clk) { - alarm_intvl1_clk = present_clk - last_read_clk; - } else { - alarm_intvl1_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + present_clk - last_read_clk); - } + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; - /* alarm_intvl2_clk = alarm_ts_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (alarm_ts_clk >= last_read_clk) { - alarm_intvl2_clk = alarm_ts_clk - last_read_clk; - } else { - alarm_intvl2_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + alarm_ts_clk - last_read_clk); - } - - /* Distinguish (long) future event and past event - * - * NOTE: No '=' sign here. Alarm should go off immediately in equal case. - */ - if (alarm_intvl2_clk > alarm_intvl1_clk) { - /* Schedule for future event */ - arm_alarm(alarm_intvl2_clk - alarm_intvl1_clk); - } else { - /* Go off immediately for past event, including equal case */ - lp_ticker_fire_interrupt(); - } + /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ + wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + TIMER_Start(timer_base); } void lp_ticker_disable_interrupt(void) { - TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void lp_ticker_clear_interrupt(void) { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void lp_ticker_fire_interrupt(void) { // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. // This prevents a recursive loop under heavy load which can lead to a stack overflow. - NVIC_SetPendingIRQ(timer3_modinit.irq_n); -} - -static void tmr2_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); -} - -static void tmr3_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - - // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); - lp_ticker_irq_handler(); - -} - -static void arm_alarm(uint32_t cd_clk) -{ - TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname); - - // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit - // NUC472/M451: See TIMER_CTL_RSTCNT_Msk - // M480 - timer3_base->CNT = 0; - while (timer3_base->CNT & TIMER_CNT_RSTACT_Msk); - // One-shot mode, Clock = 1 KHz - uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - uint32_t prescale_timer3 = clk_timer3 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127); - MBED_ASSERT((clk_timer3 % NU_TMRCLK_PER_SEC) == 0); - // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default. - timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/); - timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/; - - /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of - * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ - uint32_t cmp_timer3 = cd_clk; - cmp_timer3 = NU_CLAMP(cmp_timer3, TMR_CMP_MIN, TMR_CMP_MAX); - timer3_base->CMP = cmp_timer3; - - TIMER_EnableInt(timer3_base); - TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ - wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); - TIMER_Start(timer3_base); + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); } const ticker_info_t* lp_ticker_get_info() @@ -256,4 +147,13 @@ const ticker_info_t* lp_ticker_get_info() return &info; } +static void tmr1_vec(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + + // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); + lp_ticker_irq_handler(); +} + #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c index ff92bd275f..e007646cdb 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c @@ -32,16 +32,12 @@ #define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) static void tmr0_vec(void); -static void tmr1_vec(void); -/* Configure scheduled alarm */ -static void arm_alarm(uint32_t cd_clk); + +static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; + +#define TIMER_MODINIT timer0_modinit static int ticker_inited = 0; -static uint32_t ticker_last_read_clk = 0; - -/* NOTE: TIMER_0 for normal counting and TIMER_1 for scheduled alarm. */ -static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; -static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; #define TMR_CMP_MIN 2 #define TMR_CMP_MAX 0xFFFFFFu @@ -53,38 +49,32 @@ void us_ticker_init(void) } ticker_inited = 1; - ticker_last_read_clk = 0; - // Reset IP - SYS_ResetModule(timer0hires_modinit.rsetidx); - SYS_ResetModule(timer1hires_modinit.rsetidx); + SYS_ResetModule(TIMER_MODINIT.rsetidx); // Select IP clock source - CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv); - CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv); + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + // Enable IP clock - CLK_EnableModuleClock(timer0hires_modinit.clkidx); - CLK_EnableModuleClock(timer1hires_modinit.clkidx); + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); // Timer for normal counter - uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - uint32_t prescale_timer0 = clk_timer0 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127); - MBED_ASSERT((clk_timer0 % NU_TMRCLK_PER_SEC) == 0); - uint32_t cmp_timer0 = TMR_CMP_MAX; - MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX); + uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default. - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/; - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer; - NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var); - NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var); + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); - NVIC_EnableIRQ(timer0hires_modinit.irq_n); - NVIC_EnableIRQ(timer1hires_modinit.irq_n); + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); - TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); + TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } uint32_t us_ticker_read() @@ -93,142 +83,45 @@ uint32_t us_ticker_read() us_ticker_init(); } - TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname); + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - ticker_last_read_clk = TIMER_GetCounter(timer0_base); - return (ticker_last_read_clk / NU_TMRCLK_PER_TICK); + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); } void us_ticker_set_interrupt(timestamp_t timestamp) { - TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - /* We need to get alarm interval from alarm timestamp `timestamp` to configure H/W timer. - * - * Because both `timestamp` and xx_ticker_read() would wrap around, we have difficulties in distinguishing - * long future event and past event. To distinguish them, we need `tick_last_read` against which - * `timestamp` is calculated out. In timeline, we would always have below after fixing wrap-around: - * (1) tick_last_read <= present_clk - * (2) tick_last_read <= alarm_ts_clk - * - * - * 1. Future event case: - * - * tick_last_read present_clk alarm_ts_clk - * | | | - * -------------------------------------------------------- - * |-alarm_intvl1_clk-| - * |-------------------alarm_intvl2_clk-------------------| - * - * 2. Past event case: - * - * tick_last_read alarm_ts_clk present_clk - * | | | - * -------------------------------------------------------- - * |-------------------alarm_intvl1_clk-------------------| - * |-alarm_intvl2_clk-| - * - * Unfortunately, `tick_last_read` is not passed along the xx_ticker_set_interrupt() call. To solve it, we - * assume that `tick_last_read` tick is exactly the one returned by the last xx_ticker_read() call before - * xx_ticker_set_interrupt() is invoked. With this assumption, we can hold it via `xx_ticker_last_read_clk` - * in xx_ticker_read(). - */ - - /* ticker_last_read_clk will update in us_ticker_read(). Keep it beforehand. */ - uint32_t last_read_clk = ticker_last_read_clk; - uint32_t present_clk = us_ticker_read() * NU_TMRCLK_PER_TICK; - uint32_t alarm_ts_clk = timestamp * NU_TMRCLK_PER_TICK; - uint32_t alarm_intvl1_clk, alarm_intvl2_clk; - - /* alarm_intvl1_clk = present_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (present_clk >= last_read_clk) { - alarm_intvl1_clk = present_clk - last_read_clk; - } else { - alarm_intvl1_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + present_clk - last_read_clk); - } - - /* alarm_intvl2_clk = alarm_ts_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (alarm_ts_clk >= last_read_clk) { - alarm_intvl2_clk = alarm_ts_clk - last_read_clk; - } else { - alarm_intvl2_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + alarm_ts_clk - last_read_clk); - } - - /* Distinguish (long) future event and past event - * - * NOTE: No '=' sign here. Alarm should go off immediately in equal case. - */ - if (alarm_intvl2_clk > alarm_intvl1_clk) { - /* Schedule for future event */ - arm_alarm(alarm_intvl2_clk - alarm_intvl1_clk); - } else { - /* Go off immediately for past event, including equal case */ - us_ticker_fire_interrupt(); - } + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; } void us_ticker_disable_interrupt(void) { - TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void us_ticker_clear_interrupt(void) { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void us_ticker_fire_interrupt(void) { // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. // This prevents a recursive loop under heavy load which can lead to a stack overflow. - NVIC_SetPendingIRQ(timer1hires_modinit.irq_n); -} - -static void tmr0_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); -} - -static void tmr1_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - - // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); - us_ticker_irq_handler(); -} - -static void arm_alarm(uint32_t cd_clk) -{ - TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname); - - // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit - // NUC472/M451: See TIMER_CTL_RSTCNT_Msk - // M480 - timer1_base->CNT = 0; - while (timer1_base->CNT & TIMER_CNT_RSTACT_Msk); - // One-shot mode, Clock = 1 MHz - uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - uint32_t prescale_timer1 = clk_timer1 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127); - MBED_ASSERT((clk_timer1 % NU_TMRCLK_PER_SEC) == 0); - // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default. - timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/); - timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/; - - /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of - * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ - uint32_t cmp_timer1 = cd_clk; - cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX); - timer1_base->CMP = cmp_timer1; - - TIMER_EnableInt(timer1_base); - TIMER_Start(timer1_base); + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); } const ticker_info_t* us_ticker_get_info() @@ -239,3 +132,11 @@ const ticker_info_t* us_ticker_get_info() }; return &info; } + +static void tmr0_vec(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + + // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); + us_ticker_irq_handler(); +} diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c index c1ee5ea5ce..1650821176 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c @@ -37,18 +37,14 @@ /* NOTE: Don't add static modifier here. These IRQ handler symbols are for linking. Vector table relocation is not actually supported for low-resource target. */ -void TMR2_IRQHandler(void); -void TMR3_IRQHandler(void); -/* Configure scheduled alarm */ -static void arm_alarm(uint32_t cd_clk); - -static uint32_t ticker_last_read_clk = 0; -static int ticker_inited = 0; +void TMR1_IRQHandler(void); /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ -/* NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled alarm */ -static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL2_TMR2_S_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) TMR2_IRQHandler}; -static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL2_TMR3_S_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) TMR3_IRQHandler}; +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1_S_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) TMR1_IRQHandler}; + +#define TIMER_MODINIT timer1_modinit + +static int ticker_inited = 0; #define TMR_CMP_MIN 2 #define TMR_CMP_MAX 0xFFFFFFu @@ -60,43 +56,37 @@ void lp_ticker_init(void) } ticker_inited = 1; - ticker_last_read_clk = 0; - // Reset module - SYS_ResetModule(timer2_modinit.rsetidx); - SYS_ResetModule(timer3_modinit.rsetidx); + SYS_ResetModule(TIMER_MODINIT.rsetidx); // Select IP clock source - CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv); - CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv); + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + // Enable IP clock - CLK_EnableModuleClock(timer2_modinit.clkidx); - CLK_EnableModuleClock(timer3_modinit.clkidx); + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); // Configure clock - uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - uint32_t prescale_timer2 = clk_timer2 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127); - MBED_ASSERT((clk_timer2 % NU_TMRCLK_PER_SEC) == 0); - uint32_t cmp_timer2 = TMR_CMP_MAX; - MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX); + uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); // Continuous mode - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE; - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->PRECNT = prescale_timer2; - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMPR = cmp_timer2; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->PRECNT = prescale_timer; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMPR = cmp_timer; // Set vector - NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var); - NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var); + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); - NVIC_EnableIRQ(timer2_modinit.irq_n); - NVIC_EnableIRQ(timer3_modinit.irq_n); + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); - TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); + TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); - TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); + TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } timestamp_t lp_ticker_read() @@ -105,144 +95,49 @@ timestamp_t lp_ticker_read() lp_ticker_init(); } - TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname); + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - ticker_last_read_clk = TIMER_GetCounter(timer2_base); - return (ticker_last_read_clk / NU_TMRCLK_PER_TICK); + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); } void lp_ticker_set_interrupt(timestamp_t timestamp) { - TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - /* We need to get alarm interval from alarm timestamp `timestamp` to configure H/W timer. - * - * Because both `timestamp` and xx_ticker_read() would wrap around, we have difficulties in distinguishing - * long future event and past event. To distinguish them, we need `tick_last_read` against which - * `timestamp` is calculated out. In timeline, we would always have below after fixing wrap-around: - * (1) tick_last_read <= present_clk - * (2) tick_last_read <= alarm_ts_clk - * - * - * 1. Future event case: - * - * tick_last_read present_clk alarm_ts_clk - * | | | - * -------------------------------------------------------- - * |-alarm_intvl1_clk-| - * |-------------------alarm_intvl2_clk-------------------| - * - * 2. Past event case: - * - * tick_last_read alarm_ts_clk present_clk - * | | | - * -------------------------------------------------------- - * |-------------------alarm_intvl1_clk-------------------| - * |-alarm_intvl2_clk-| - * - * Unfortunately, `tick_last_read` is not passed along the xx_ticker_set_interrupt() call. To solve it, we - * assume that `tick_last_read` tick is exactly the one returned by the last xx_ticker_read() call before - * xx_ticker_set_interrupt() is invoked. With this assumption, we can hold it via `xx_ticker_last_read_clk` - * in xx_ticker_read(). - */ - - /* ticker_last_read_clk will update in lp_ticker_read(). Keep it beforehand. */ - uint32_t last_read_clk = ticker_last_read_clk; - uint32_t present_clk = lp_ticker_read() * NU_TMRCLK_PER_TICK; - uint32_t alarm_ts_clk = timestamp * NU_TMRCLK_PER_TICK; - uint32_t alarm_intvl1_clk, alarm_intvl2_clk; - - /* alarm_intvl1_clk = present_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (present_clk >= last_read_clk) { - alarm_intvl1_clk = present_clk - last_read_clk; - } else { - alarm_intvl1_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + present_clk - last_read_clk); - } + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMPR = cmp_timer; - /* alarm_intvl2_clk = alarm_ts_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (alarm_ts_clk >= last_read_clk) { - alarm_intvl2_clk = alarm_ts_clk - last_read_clk; - } else { - alarm_intvl2_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + alarm_ts_clk - last_read_clk); - } - - /* Distinguish (long) future event and past event - * - * NOTE: No '=' sign here. Alarm should go off immediately in equal case. - */ - if (alarm_intvl2_clk > alarm_intvl1_clk) { - /* Schedule for future event */ - arm_alarm(alarm_intvl2_clk - alarm_intvl1_clk); - } else { - /* Go off immediately for past event, including equal case */ - lp_ticker_fire_interrupt(); - } + /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ + wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + TIMER_Start(timer_base); } void lp_ticker_disable_interrupt(void) { - TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void lp_ticker_clear_interrupt(void) { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void lp_ticker_fire_interrupt(void) { // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. // This prevents a recursive loop under heavy load which can lead to a stack overflow. - NVIC_SetPendingIRQ(timer3_modinit.irq_n); -} -void TMR2_IRQHandler(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); -} - -void TMR3_IRQHandler(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - - // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); - lp_ticker_irq_handler(); - -} - -static void arm_alarm(uint32_t cd_clk) -{ - TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname); - - // Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_CTL [TMR_EN] bit - timer3_base->CTL |= TIMER_CTL_SW_RST_Msk; - // One-shot mode, Clock = 1 KHz - uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - uint32_t prescale_timer3 = clk_timer3 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127); - MBED_ASSERT((clk_timer3 % NU_TMRCLK_PER_SEC) == 0); - timer3_base->CTL &= ~TIMER_CTL_MODE_SEL_Msk; - timer3_base->CTL |= TIMER_ONESHOT_MODE; - timer3_base->PRECNT = prescale_timer3; - - /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of - * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ - uint32_t cmp_timer3 = cd_clk; - cmp_timer3 = NU_CLAMP(cmp_timer3, TMR_CMP_MIN, TMR_CMP_MAX); - timer3_base->CMPR = cmp_timer3; - - TIMER_EnableInt(timer3_base); - TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ - wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); - TIMER_Start(timer3_base); + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); } const ticker_info_t* lp_ticker_get_info() @@ -254,4 +149,13 @@ const ticker_info_t* lp_ticker_get_info() return &info; } +void TMR1_IRQHandler(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + + // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); + lp_ticker_irq_handler(); +} + #endif diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c index b3a8ffc65f..124161ced2 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c @@ -34,17 +34,13 @@ /* NOTE: Don't add static modifier here. These IRQ handler symbols are for linking. Vector table relocation is not actually supported for low-resource target. */ void TMR0_IRQHandler(void); -void TMR1_IRQHandler(void); -/* Configure scheduled alarm */ -static void arm_alarm(uint32_t cd_clk); -static uint32_t ticker_last_read_clk = 0; +static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, 0, TMR0_RST, TMR0_IRQn, (void *) TMR0_IRQHandler}; + +#define TIMER_MODINIT timer0_modinit + static int ticker_inited = 0; -/* NOTE: TIMER_0 for normal counting and TIMER_1 for scheduled alarm. */ -static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, 0, TMR0_RST, TMR0_IRQn, (void *) TMR0_IRQHandler}; -static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1_S_HXT, 0, TMR1_RST, TMR1_IRQn, (void *) TMR1_IRQHandler}; - #define TMR_CMP_MIN 2 #define TMR_CMP_MAX 0xFFFFFFu @@ -55,38 +51,32 @@ void us_ticker_init(void) } ticker_inited = 1; - ticker_last_read_clk = 0; - // Reset IP - SYS_ResetModule(timer0hires_modinit.rsetidx); - SYS_ResetModule(timer1hires_modinit.rsetidx); + SYS_ResetModule(TIMER_MODINIT.rsetidx); // Select IP clock source - CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv); - CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv); + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + // Enable IP clock - CLK_EnableModuleClock(timer0hires_modinit.clkidx); - CLK_EnableModuleClock(timer1hires_modinit.clkidx); + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); // Timer for normal counter - uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - uint32_t prescale_timer0 = clk_timer0 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127); - MBED_ASSERT((clk_timer0 % NU_TMRCLK_PER_SEC) == 0); - uint32_t cmp_timer0 = TMR_CMP_MAX; - MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX); - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE; - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->PRECNT = prescale_timer0; - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMPR = cmp_timer0; + uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->PRECNT = prescale_timer; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMPR = cmp_timer; - NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var); - NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var); + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); - NVIC_EnableIRQ(timer0hires_modinit.irq_n); - NVIC_EnableIRQ(timer1hires_modinit.irq_n); + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); - TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); + TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } uint32_t us_ticker_read() @@ -95,139 +85,45 @@ uint32_t us_ticker_read() us_ticker_init(); } - TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname); + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - ticker_last_read_clk = TIMER_GetCounter(timer0_base); - return (ticker_last_read_clk / NU_TMRCLK_PER_TICK); + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); } void us_ticker_set_interrupt(timestamp_t timestamp) { - TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - /* We need to get alarm interval from alarm timestamp `timestamp` to configure H/W timer. - * - * Because both `timestamp` and xx_ticker_read() would wrap around, we have difficulties in distinguishing - * long future event and past event. To distinguish them, we need `tick_last_read` against which - * `timestamp` is calculated out. In timeline, we would always have below after fixing wrap-around: - * (1) tick_last_read <= present_clk - * (2) tick_last_read <= alarm_ts_clk - * - * - * 1. Future event case: - * - * tick_last_read present_clk alarm_ts_clk - * | | | - * -------------------------------------------------------- - * |-alarm_intvl1_clk-| - * |-------------------alarm_intvl2_clk-------------------| - * - * 2. Past event case: - * - * tick_last_read alarm_ts_clk present_clk - * | | | - * -------------------------------------------------------- - * |-------------------alarm_intvl1_clk-------------------| - * |-alarm_intvl2_clk-| - * - * Unfortunately, `tick_last_read` is not passed along the xx_ticker_set_interrupt() call. To solve it, we - * assume that `tick_last_read` tick is exactly the one returned by the last xx_ticker_read() call before - * xx_ticker_set_interrupt() is invoked. With this assumption, we can hold it via `xx_ticker_last_read_clk` - * in xx_ticker_read(). - */ - - /* ticker_last_read_clk will update in us_ticker_read(). Keep it beforehand. */ - uint32_t last_read_clk = ticker_last_read_clk; - uint32_t present_clk = us_ticker_read() * NU_TMRCLK_PER_TICK; - uint32_t alarm_ts_clk = timestamp * NU_TMRCLK_PER_TICK; - uint32_t alarm_intvl1_clk, alarm_intvl2_clk; - - /* alarm_intvl1_clk = present_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (present_clk >= last_read_clk) { - alarm_intvl1_clk = present_clk - last_read_clk; - } else { - alarm_intvl1_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + present_clk - last_read_clk); - } - - /* alarm_intvl2_clk = alarm_ts_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (alarm_ts_clk >= last_read_clk) { - alarm_intvl2_clk = alarm_ts_clk - last_read_clk; - } else { - alarm_intvl2_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + alarm_ts_clk - last_read_clk); - } - - /* Distinguish (long) future event and past event - * - * NOTE: No '=' sign here. Alarm should go off immediately in equal case. - */ - if (alarm_intvl2_clk > alarm_intvl1_clk) { - /* Schedule for future event */ - arm_alarm(alarm_intvl2_clk - alarm_intvl1_clk); - } else { - /* Go off immediately for past event, including equal case */ - us_ticker_fire_interrupt(); - } + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMPR = cmp_timer; } void us_ticker_disable_interrupt(void) { - TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void us_ticker_clear_interrupt(void) { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void us_ticker_fire_interrupt(void) { // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. // This prevents a recursive loop under heavy load which can lead to a stack overflow. - NVIC_SetPendingIRQ(timer1hires_modinit.irq_n); -} - -void TMR0_IRQHandler(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); -} - -void TMR1_IRQHandler(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - - // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); - us_ticker_irq_handler(); -} - -static void arm_alarm(uint32_t cd_clk) -{ - TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname); - - // Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_CTL [TMR_EN] bit - timer1_base->CTL |= TIMER_CTL_SW_RST_Msk; - // One-shot mode, Clock = 1 MHz - uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - uint32_t prescale_timer1 = clk_timer1 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127); - MBED_ASSERT((clk_timer1 % NU_TMRCLK_PER_SEC) == 0); - timer1_base->CTL &= ~TIMER_CTL_MODE_SEL_Msk; - timer1_base->CTL |= TIMER_ONESHOT_MODE; - timer1_base->PRECNT = prescale_timer1; - - /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of - * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ - uint32_t cmp_timer1 = cd_clk; - cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX); - timer1_base->CMPR = cmp_timer1; - - TIMER_EnableInt(timer1_base); - TIMER_Start(timer1_base); + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); } const ticker_info_t* us_ticker_get_info() @@ -238,3 +134,11 @@ const ticker_info_t* us_ticker_get_info() }; return &info; } + +void TMR0_IRQHandler(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + + // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); + us_ticker_irq_handler(); +} diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c index 042e298797..6c4aa88193 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c @@ -35,18 +35,14 @@ /* Timer max counter */ #define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) -static void tmr2_vec(void); -static void tmr3_vec(void); -/* Configure scheduled alarm */ -static void arm_alarm(uint32_t cd_clk); - -static int ticker_inited = 0; -static uint32_t ticker_last_read_clk = 0; +static void tmr1_vec(void); /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ -/* NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled alarm */ -static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec}; -static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec}; +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; + +#define TIMER_MODINIT timer1_modinit + +static int ticker_inited = 0; #define TMR_CMP_MIN 2 #define TMR_CMP_MAX 0xFFFFFFu @@ -58,42 +54,36 @@ void lp_ticker_init(void) } ticker_inited = 1; - ticker_last_read_clk = 0; - // Reset module - SYS_ResetModule(timer2_modinit.rsetidx); - SYS_ResetModule(timer3_modinit.rsetidx); + SYS_ResetModule(TIMER_MODINIT.rsetidx); // Select IP clock source - CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv); - CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv); + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + // Enable IP clock - CLK_EnableModuleClock(timer2_modinit.clkidx); - CLK_EnableModuleClock(timer3_modinit.clkidx); + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); // Configure clock - uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - uint32_t prescale_timer2 = clk_timer2 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127); - MBED_ASSERT((clk_timer2 % NU_TMRCLK_PER_SEC) == 0); - uint32_t cmp_timer2 = TMR_CMP_MAX; - MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX); + uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); // Continuous mode - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2 | TIMER_CTL_CNTDATEN_Msk; - ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer; // Set vector - NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var); - NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var); + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); - NVIC_EnableIRQ(timer2_modinit.irq_n); - NVIC_EnableIRQ(timer3_modinit.irq_n); + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); - TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); + TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); - TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); + TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } timestamp_t lp_ticker_read() @@ -102,144 +92,49 @@ timestamp_t lp_ticker_read() lp_ticker_init(); } - TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname); + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - ticker_last_read_clk = TIMER_GetCounter(timer2_base); - return (ticker_last_read_clk / NU_TMRCLK_PER_TICK); + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); } void lp_ticker_set_interrupt(timestamp_t timestamp) { - TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - /* We need to get alarm interval from alarm timestamp `timestamp` to configure H/W timer. - * - * Because both `timestamp` and xx_ticker_read() would wrap around, we have difficulties in distinguishing - * long future event and past event. To distinguish them, we need `tick_last_read` against which - * `timestamp` is calculated out. In timeline, we would always have below after fixing wrap-around: - * (1) tick_last_read <= present_clk - * (2) tick_last_read <= alarm_ts_clk - * - * - * 1. Future event case: - * - * tick_last_read present_clk alarm_ts_clk - * | | | - * -------------------------------------------------------- - * |-alarm_intvl1_clk-| - * |-------------------alarm_intvl2_clk-------------------| - * - * 2. Past event case: - * - * tick_last_read alarm_ts_clk present_clk - * | | | - * -------------------------------------------------------- - * |-------------------alarm_intvl1_clk-------------------| - * |-alarm_intvl2_clk-| - * - * Unfortunately, `tick_last_read` is not passed along the xx_ticker_set_interrupt() call. To solve it, we - * assume that `tick_last_read` tick is exactly the one returned by the last xx_ticker_read() call before - * xx_ticker_set_interrupt() is invoked. With this assumption, we can hold it via `xx_ticker_last_read_clk` - * in xx_ticker_read(). - */ - - /* ticker_last_read_clk will update in lp_ticker_read(). Keep it beforehand. */ - uint32_t last_read_clk = ticker_last_read_clk; - uint32_t present_clk = lp_ticker_read() * NU_TMRCLK_PER_TICK; - uint32_t alarm_ts_clk = timestamp * NU_TMRCLK_PER_TICK; - uint32_t alarm_intvl1_clk, alarm_intvl2_clk; - - /* alarm_intvl1_clk = present_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (present_clk >= last_read_clk) { - alarm_intvl1_clk = present_clk - last_read_clk; - } else { - alarm_intvl1_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + present_clk - last_read_clk); - } + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; - /* alarm_intvl2_clk = alarm_ts_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (alarm_ts_clk >= last_read_clk) { - alarm_intvl2_clk = alarm_ts_clk - last_read_clk; - } else { - alarm_intvl2_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + alarm_ts_clk - last_read_clk); - } - - /* Distinguish (long) future event and past event - * - * NOTE: No '=' sign here. Alarm should go off immediately in equal case. - */ - if (alarm_intvl2_clk > alarm_intvl1_clk) { - /* Schedule for future event */ - arm_alarm(alarm_intvl2_clk - alarm_intvl1_clk); - } else { - /* Go off immediately for past event, including equal case */ - lp_ticker_fire_interrupt(); - } + /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ + wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + TIMER_Start(timer_base); } void lp_ticker_disable_interrupt(void) { - TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void lp_ticker_clear_interrupt(void) { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void lp_ticker_fire_interrupt(void) { // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. // This prevents a recursive loop under heavy load which can lead to a stack overflow. - NVIC_SetPendingIRQ(timer3_modinit.irq_n); -} - -static void tmr2_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); - TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname)); -} - -static void tmr3_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - - // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); - lp_ticker_irq_handler(); - -} - -static void arm_alarm(uint32_t cd_clk) -{ - TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname); - - // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit - timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk; - // One-shot mode, Clock = 1 KHz - uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - uint32_t prescale_timer3 = clk_timer3 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127); - MBED_ASSERT((clk_timer3 % NU_TMRCLK_PER_SEC) == 0); - timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk); - timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3 | TIMER_CTL_CNTDATEN_Msk; - - /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of - * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ - uint32_t cmp_timer3 = cd_clk; - cmp_timer3 = NU_CLAMP(cmp_timer3, TMR_CMP_MIN, TMR_CMP_MAX); - timer3_base->CMP = cmp_timer3; - - TIMER_EnableInt(timer3_base); - TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname)); - /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ - wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); - TIMER_Start(timer3_base); + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); } const ticker_info_t* lp_ticker_get_info() @@ -251,4 +146,13 @@ const ticker_info_t* lp_ticker_get_info() return &info; } +static void tmr1_vec(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + + // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); + lp_ticker_irq_handler(); +} + #endif diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c index fd10ded30c..a18e2cc0d0 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c @@ -32,16 +32,12 @@ #define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) static void tmr0_vec(void); -static void tmr1_vec(void); -/* Configure alarm exactly after scheduled clocks */ -static void arm_alarm(uint32_t cd_clk); + +static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; + +#define TIMER_MODINIT timer0_modinit static int ticker_inited = 0; -static uint32_t ticker_last_read_clk = 0; - -/* NOTE: TIMER_0 for normal counting and TIMER_1 for scheduled alarm. */ -static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec}; -static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; #define TMR_CMP_MIN 2 #define TMR_CMP_MAX 0xFFFFFFu @@ -53,37 +49,31 @@ void us_ticker_init(void) } ticker_inited = 1; - ticker_last_read_clk = 0; - // Reset IP - SYS_ResetModule(timer0hires_modinit.rsetidx); - SYS_ResetModule(timer1hires_modinit.rsetidx); + SYS_ResetModule(TIMER_MODINIT.rsetidx); // Select IP clock source - CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv); - CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv); + CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + // Enable IP clock - CLK_EnableModuleClock(timer0hires_modinit.clkidx); - CLK_EnableModuleClock(timer1hires_modinit.clkidx); + CLK_EnableModuleClock(TIMER_MODINIT.clkidx); // Timer for normal counter - uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - uint32_t prescale_timer0 = clk_timer0 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127); - MBED_ASSERT((clk_timer0 % NU_TMRCLK_PER_SEC) == 0); - uint32_t cmp_timer0 = TMR_CMP_MAX; - MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX); - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0 | TIMER_CTL_CNTDATEN_Msk; - ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0; + uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk; + ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer; - NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var); - NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var); + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); - NVIC_EnableIRQ(timer0hires_modinit.irq_n); - NVIC_EnableIRQ(timer1hires_modinit.irq_n); + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); - TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); - TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); + TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } uint32_t us_ticker_read() @@ -92,138 +82,45 @@ uint32_t us_ticker_read() us_ticker_init(); } - TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname); + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - ticker_last_read_clk = TIMER_GetCounter(timer0_base); - return (ticker_last_read_clk / NU_TMRCLK_PER_TICK); + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); } void us_ticker_set_interrupt(timestamp_t timestamp) { - TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); - /* We need to get alarm interval from alarm timestamp `timestamp` to configure H/W timer. - * - * Because both `timestamp` and xx_ticker_read() would wrap around, we have difficulties in distinguishing - * long future event and past event. To distinguish them, we need `tick_last_read` against which - * `timestamp` is calculated out. In timeline, we would always have below after fixing wrap-around: - * (1) tick_last_read <= present_clk - * (2) tick_last_read <= alarm_ts_clk - * - * - * 1. Future event case: - * - * tick_last_read present_clk alarm_ts_clk - * | | | - * -------------------------------------------------------- - * |-alarm_intvl1_clk-| - * |-------------------alarm_intvl2_clk-------------------| - * - * 2. Past event case: - * - * tick_last_read alarm_ts_clk present_clk - * | | | - * -------------------------------------------------------- - * |-------------------alarm_intvl1_clk-------------------| - * |-alarm_intvl2_clk-| - * - * Unfortunately, `tick_last_read` is not passed along the xx_ticker_set_interrupt() call. To solve it, we - * assume that `tick_last_read` tick is exactly the one returned by the last xx_ticker_read() call before - * xx_ticker_set_interrupt() is invoked. With this assumption, we can hold it via `xx_ticker_last_read_clk` - * in xx_ticker_read(). - */ - - /* ticker_last_read_clk will update in us_ticker_read(). Keep it beforehand. */ - uint32_t last_read_clk = ticker_last_read_clk; - uint32_t present_clk = us_ticker_read() * NU_TMRCLK_PER_TICK; - uint32_t alarm_ts_clk = timestamp * NU_TMRCLK_PER_TICK; - uint32_t alarm_intvl1_clk, alarm_intvl2_clk; - - /* alarm_intvl1_clk = present_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (present_clk >= last_read_clk) { - alarm_intvl1_clk = present_clk - last_read_clk; - } else { - alarm_intvl1_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + present_clk - last_read_clk); - } - - /* alarm_intvl2_clk = alarm_ts_clk - last_read_clk - * - * NOTE: Don't miss the `=` sign here. Otherwise, we would get the wrong result. - */ - if (alarm_ts_clk >= last_read_clk) { - alarm_intvl2_clk = alarm_ts_clk - last_read_clk; - } else { - alarm_intvl2_clk = (uint32_t) (((uint64_t) NU_TMR_MAXCNT) + 1 + alarm_ts_clk - last_read_clk); - } - - /* Distinguish (long) future event and past event - * - * NOTE: No '=' sign here. Alarm should go off immediately in equal case. - */ - if (alarm_intvl2_clk > alarm_intvl1_clk) { - /* Schedule for future event */ - arm_alarm(alarm_intvl2_clk - alarm_intvl1_clk); - } else { - /* Go off immediately for past event, including equal case */ - us_ticker_fire_interrupt(); - } + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; } void us_ticker_disable_interrupt(void) { - TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void us_ticker_clear_interrupt(void) { - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); } void us_ticker_fire_interrupt(void) { // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. // This prevents a recursive loop under heavy load which can lead to a stack overflow. - NVIC_SetPendingIRQ(timer1hires_modinit.irq_n); -} - -static void tmr0_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname)); -} - -static void tmr1_vec(void) -{ - TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - - // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); - us_ticker_irq_handler(); -} - -static void arm_alarm(uint32_t cd_clk) -{ - TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname); - - // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit - timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk; - // One-shot mode, Clock = 1 MHz - uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname)); - uint32_t prescale_timer1 = clk_timer1 / NU_TMRCLK_PER_SEC - 1; - MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127); - MBED_ASSERT((clk_timer1 % NU_TMRCLK_PER_SEC) == 0); - timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk); - timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1 | TIMER_CTL_CNTDATEN_Msk; - - /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of - * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ - uint32_t cmp_timer1 = cd_clk; - cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX); - timer1_base->CMP = cmp_timer1; - - TIMER_EnableInt(timer1_base); - TIMER_Start(timer1_base); + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); } const ticker_info_t* us_ticker_get_info() @@ -234,3 +131,11 @@ const ticker_info_t* us_ticker_get_info() }; return &info; } + +static void tmr0_vec(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + + // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); + us_ticker_irq_handler(); +} From 6ddb13573aa7ca558a2f81bcc8b5403cc416cbe8 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 20 Feb 2018 10:44:16 -0600 Subject: [PATCH 003/118] Correct mbed export with multiple --source params --- tools/project.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tools/project.py b/tools/project.py index 141dfe8783..db659117f7 100644 --- a/tools/project.py +++ b/tools/project.py @@ -4,7 +4,7 @@ supported IDEs or project structures. from __future__ import absolute_import, print_function import sys from os.path import (join, abspath, dirname, exists, basename, normpath, - realpath, basename) + realpath, relpath, basename) from os import remove ROOT = abspath(join(dirname(__file__), "..")) sys.path.insert(0, ROOT) @@ -48,7 +48,7 @@ def setup_project(ide, target, program=None, source_dir=None, build=None, export project_name = TESTS[program] else: project_name = basename(normpath(realpath(source_dir[0]))) - src_paths = source_dir + src_paths = {relpath(path, project_dir): [path] for path in source_dir} lib_paths = None else: test = Test(program) @@ -254,7 +254,10 @@ def main(): except (NotImplementedError, IOError, OSError): pass for f in EXPORTERS.values()[0].CLEAN_FILES: - remove(f) + try: + remove(f) + except (IOError, OSError): + pass try: export(mcu, options.ide, build=options.build, src=options.source_dir, macros=options.macros, From bf40cb5b4418cf14ba5f4c75215fdd8edf2f55e0 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Tue, 20 Feb 2018 10:44:42 -0600 Subject: [PATCH 004/118] Specify --build in mbed export: consistency with compile --- tools/project.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/project.py b/tools/project.py index db659117f7..e1fbae5136 100644 --- a/tools/project.py +++ b/tools/project.py @@ -163,6 +163,12 @@ def main(): default=False, help="writes tools/export/README.md") + parser.add_argument("--build", + type=argparse_filestring_type, + dest="build_dir", + default=None, + help="Directory for the exported project files") + parser.add_argument("--source", action="append", type=argparse_filestring_type, @@ -262,7 +268,8 @@ def main(): export(mcu, options.ide, build=options.build, src=options.source_dir, macros=options.macros, project_id=options.program, zip_proj=zip_proj, - build_profile=profile, app_config=options.app_config) + build_profile=profile, app_config=options.app_config, + export_path=options.build_dir) except NotSupportedException as exc: print("[ERROR] %s" % str(exc)) From 2279c8b098dfb2fdd70f1b29013364b252fb4a7d Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Fri, 16 Feb 2018 13:29:05 -0600 Subject: [PATCH 005/118] Correct gcc m33 floating point handling --- tools/toolchains/__init__.py | 6 ++++-- tools/toolchains/gcc.py | 29 +++++++++++++++-------------- 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/tools/toolchains/__init__.py b/tools/toolchains/__init__.py index 715fc60951..39f0fa75a9 100644 --- a/tools/toolchains/__init__.py +++ b/tools/toolchains/__init__.py @@ -337,8 +337,10 @@ class mbedToolchain: "Cortex-A9" : ["__CORTEX_A9", "ARM_MATH_CA9", "__FPU_PRESENT", "__CMSIS_RTOS", "__EVAL", "__MBED_CMSIS_RTOS_CA9"], "Cortex-M23-NS": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "__DOMAIN_NS=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], "Cortex-M23": ["__CORTEX_M23", "ARM_MATH_ARMV8MBL", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], - "Cortex-M33-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__DOMAIN_NS=1", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], - "Cortex-M33": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], + "Cortex-M33-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__DOMAIN_NS=1", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], + "Cortex-M33": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], + "Cortex-M33F-NS": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__DOMAIN_NS=1", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], + "Cortex-M33F": ["__CORTEX_M33", "ARM_MATH_ARMV8MML", "__FPU_PRESENT", "__CMSIS_RTOS", "__MBED_CMSIS_RTOS_CM"], } MBED_CONFIG_FILE_NAME="mbed_config.h" diff --git a/tools/toolchains/gcc.py b/tools/toolchains/gcc.py index dfc83b8bc4..4c0eca2c82 100644 --- a/tools/toolchains/gcc.py +++ b/tools/toolchains/gcc.py @@ -48,21 +48,20 @@ class GCC(mbedToolchain): self.flags["ld"].append("--specs=nano.specs") if target.core == "Cortex-M0+": - cpu = "cortex-m0plus" - elif target.core == "Cortex-M4F": - cpu = "cortex-m4" - elif target.core == "Cortex-M7F": - cpu = "cortex-m7" - elif target.core == "Cortex-M7FD": - cpu = "cortex-m7" - elif target.core == "Cortex-M23-NS": - cpu = "cortex-m23" - elif target.core == "Cortex-M33-NS": - cpu = "cortex-m33" + self.cpu = ["-mcpu=cortex-m0plus"] + elif target.core.startswith("Cortex-M4"): + self.cpu = ["-mcpu=cortex-m4"] + elif target.core.startswith("Cortex-M7"): + self.cpu = ["-mcpu=cortex-m7"] + elif target.core.startswith("Cortex-M23"): + self.cpu = ["-mcpu=cortex-m23"] + elif target.core.startswith("Cortex-M33F"): + self.cpu = ["-mcpu=cortex-m33"] + elif target.core.startswith("Cortex-M33"): + self.cpu = ["-march=armv8-m.main"] else: - cpu = target.core.lower() + self.cpu = ["-mcpu={}".format(target.core.lower())] - self.cpu = ["-mcpu=%s" % cpu] if target.core.startswith("Cortex-M"): self.cpu.append("-mthumb") @@ -85,7 +84,9 @@ class GCC(mbedToolchain): self.cpu.append("-mfloat-abi=hard") self.cpu.append("-mno-unaligned-access") - if target.core == "Cortex-M23" or target.core == "Cortex-M33": + if ((target.core.startswith("Cortex-M23") or + target.core.startswith("Cortex-M33")) and + not target.core.endswith("-NS")): self.cpu.append("-mcmse") elif target.core == "Cortex-M23-NS" or target.core == "Cortex-M33-NS": self.flags["ld"].append("-D__DOMAIN_NS=1") From 87b903509d076abe3a8b6c9e4629b30b0fc7cbe8 Mon Sep 17 00:00:00 2001 From: Cruz Monrreal II Date: Mon, 5 Mar 2018 13:38:55 -0600 Subject: [PATCH 006/118] Modified underflow error text to print overflow instead. End users are more familiar with handling overflow errors, even if underflow may be technically correct --- rtos/TARGET_CORTEX/mbed_rtx_handlers.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/rtos/TARGET_CORTEX/mbed_rtx_handlers.c b/rtos/TARGET_CORTEX/mbed_rtx_handlers.c index 882d4636af..ebbd3979e3 100644 --- a/rtos/TARGET_CORTEX/mbed_rtx_handlers.c +++ b/rtos/TARGET_CORTEX/mbed_rtx_handlers.c @@ -45,7 +45,8 @@ __NO_RETURN uint32_t osRtxErrorNotify (uint32_t code, void *object_id) switch (code) { case osRtxErrorStackUnderflow: // Stack underflow detected for thread (thread_id=object_id) - error("CMSIS-RTOS error: Stack underflow (status: 0x%X, task ID: 0x%X, task name: %s)\n\r", + // Note: "overflow" is printed instead of "underflow" due to end user familiarity with overflow errors + error("CMSIS-RTOS error: Stack overflow (status: 0x%X, task ID: 0x%X, task name: %s)\n\r", code, object_id, osThreadGetName(object_id)); break; case osRtxErrorISRQueueOverflow: From ef8dc122094073e19adca7cd556d28661006dfc5 Mon Sep 17 00:00:00 2001 From: Antti Kauppila Date: Mon, 5 Mar 2018 15:10:49 +0200 Subject: [PATCH 007/118] Cellular tests: nsapi_socket_t errors fixed in unittests --- .../test_at_cellularstack.cpp | 41 +++++++++---------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/features/cellular/UNITTESTS/at/at_cellularstack/test_at_cellularstack.cpp b/features/cellular/UNITTESTS/at/at_cellularstack/test_at_cellularstack.cpp index eef98a7ce1..331dde5027 100644 --- a/features/cellular/UNITTESTS/at/at_cellularstack/test_at_cellularstack.cpp +++ b/features/cellular/UNITTESTS/at/at_cellularstack/test_at_cellularstack.cpp @@ -35,6 +35,7 @@ public: bool max_sock_value; nsapi_error_t create_error; int max_packet_size; + CellularSocket socket; MyStack(ATHandler &atr, int cid, nsapi_ip_stack_t typ) : AT_CellularStack(atr, cid, typ) { @@ -143,14 +144,14 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_open() st.bool_value = true; st.max_sock_value = 0; - nsapi_socket_t sock; + nsapi_socket_t sock = &st.socket; CHECK(NSAPI_ERROR_NO_SOCKET == st.socket_open(&sock, NSAPI_TCP)); MyStack st2(at, 0, IPV6_STACK); st2.bool_value = true; st2.max_sock_value = 1; - nsapi_socket_t sock2; - CHECK(NSAPI_ERROR_OK == st2.socket_open(&sock2, NSAPI_TCP)); + sock = &st2.socket; + CHECK(NSAPI_ERROR_OK == st2.socket_open(&sock, NSAPI_TCP)); } void Test_AT_CellularStack::test_AT_CellularStack_socket_close() @@ -160,12 +161,11 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_close() ATHandler at(&fh1, que, 0, ","); MyStack st(at, 0, IPV6_STACK); - nsapi_socket_t soc = NULL; - CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_close(soc)); + CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_close(&st.socket)); + nsapi_socket_t sock = &st.socket; st.bool_value = true; st.max_sock_value = 1; - nsapi_socket_t sock; CHECK(NSAPI_ERROR_OK == st.socket_open(&sock, NSAPI_TCP)); st.max_sock_value = 0; CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_close(sock)); @@ -173,9 +173,9 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_close() MyStack st2(at, 0, IPV6_STACK); st2.max_sock_value = 1; st2.bool_value = true; - nsapi_socket_t sock2; - CHECK(NSAPI_ERROR_OK == st2.socket_open(&sock2, NSAPI_TCP)); - CHECK(NSAPI_ERROR_OK == st2.socket_close(sock2)); + sock = &st2.socket; + CHECK(NSAPI_ERROR_OK == st2.socket_open(&sock, NSAPI_TCP)); + CHECK(NSAPI_ERROR_OK == st2.socket_close(sock)); } void Test_AT_CellularStack::test_AT_CellularStack_socket_bind() @@ -185,12 +185,11 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_bind() ATHandler at(&fh1, que, 0, ","); MyStack st(at, 0, IPV6_STACK); - nsapi_socket_t sock; SocketAddress addr; ATHandler_stub::nsapi_error_value = NSAPI_ERROR_ALREADY; CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_bind(NULL, addr)); - CHECK(NSAPI_ERROR_ALREADY == st.socket_bind(sock, addr)); + CHECK(NSAPI_ERROR_ALREADY == st.socket_bind(&st.socket, addr)); } void Test_AT_CellularStack::test_AT_CellularStack_socket_listen() @@ -200,8 +199,7 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_listen() ATHandler at(&fh1, que, 0, ","); MyStack st(at, 0, IPV6_STACK); - nsapi_socket_t sock; - CHECK(0 == st.socket_listen(sock, 4)); + CHECK(NSAPI_ERROR_UNSUPPORTED == st.socket_listen(&st.socket, 4)); } void Test_AT_CellularStack::test_AT_CellularStack_socket_connect() @@ -214,8 +212,7 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_connect() SocketAddress addr; CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_connect(NULL, addr)); - nsapi_socket_t sock; - CHECK(NSAPI_ERROR_OK == st.socket_connect(sock, addr)); + CHECK(NSAPI_ERROR_OK == st.socket_connect(&st.socket, addr)); } void Test_AT_CellularStack::test_AT_CellularStack_socket_accept() @@ -225,8 +222,8 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_accept() ATHandler at(&fh1, que, 0, ","); MyStack st(at, 0, IPV6_STACK); - nsapi_socket_t sock; - CHECK(0 == st.socket_accept(NULL, &sock)); + nsapi_socket_t sock = &st.socket; + CHECK(NSAPI_ERROR_UNSUPPORTED == st.socket_accept(NULL, &sock)); } void Test_AT_CellularStack::test_AT_CellularStack_socket_send() @@ -238,12 +235,12 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_send() MyStack st(at, 0, IPV6_STACK); CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_send(NULL, "addr", 4)); - nsapi_socket_t sock; - CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_send(sock, "addr", 4)); + CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_send(&st.socket, "addr", 4)); SocketAddress addr; st.max_sock_value = 1; st.bool_value = true; + nsapi_socket_t sock = &st.socket; st.socket_open(&sock, NSAPI_TCP); st.socket_connect(sock, addr); CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_send(sock, "addr", 4)); @@ -257,12 +254,12 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_sendto() MyStack st(at, 0, IPV6_STACK); - nsapi_socket_t sock; SocketAddress addr; CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_sendto(NULL, addr, "addr", 4)); st.max_sock_value = 1; st.bool_value = true; + nsapi_socket_t sock = &st.socket; st.socket_open(&sock, NSAPI_TCP); st.socket_connect(sock, addr); st.create_error = NSAPI_ERROR_CONNECTION_LOST; @@ -294,10 +291,10 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_recvfrom() char table[4]; CHECK(NSAPI_ERROR_DEVICE_ERROR == st.socket_recvfrom(NULL, NULL, table, 4)); - nsapi_socket_t sock; SocketAddress addr; st.max_sock_value = 1; st.bool_value = true; + nsapi_socket_t sock = &st.socket; st.socket_open(&sock, NSAPI_TCP); st.socket_connect(sock, addr); st.create_error = NSAPI_ERROR_CONNECTION_LOST; @@ -317,9 +314,9 @@ void Test_AT_CellularStack::test_AT_CellularStack_socket_attach() MyStack st(at, 0, IPV6_STACK); st.socket_attach(NULL, NULL, NULL); - nsapi_socket_t sock; st.max_sock_value = 1; st.bool_value = true; + nsapi_socket_t sock = &st.socket; st.socket_open(&sock, NSAPI_TCP); st.socket_attach(sock, NULL, NULL); } From 3ca392c8e6aaaf0e289132c42b824693dc4c7dae Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Fri, 2 Feb 2018 10:47:48 -0600 Subject: [PATCH 008/118] Fix missing serial object for interrupts Save serial objects when setting interrupt requests. Improve uart interrupt handler. --- .../TARGET_Maxim/TARGET_MAX32625/serial_api.c | 32 +++++++++++++------ 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/serial_api.c b/targets/TARGET_Maxim/TARGET_MAX32625/serial_api.c index 6b2d85b75d..d6c007f998 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/serial_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32625/serial_api.c @@ -48,8 +48,8 @@ MXC_F_UART_INTFL_RX_FIFO_OVERFLOW) // Variables for managing the stdio UART -int stdio_uart_inited; -serial_t stdio_uart; +int stdio_uart_inited = 0; +serial_t stdio_uart = {0}; // Variables for interrupt driven static uart_irq_handler irq_handler; @@ -75,12 +75,6 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->index = MXC_UART_GET_IDX(obj->uart); obj->fifo = (mxc_uart_fifo_regs_t*)MXC_UART_GET_BASE_FIFO(obj->index); - // Manage stdio UART - if (uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } - // Record the pins requested obj->tx = tx; obj->rx = rx; @@ -111,6 +105,12 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) obj->cfg.size = UART_DATA_SIZE_8_BITS; obj->cfg.parity = UART_PARITY_DISABLE; + // Manage stdio UART + if (uart == STDIO_UART) { + stdio_uart_inited = 1; + stdio_uart = *obj; + } + int retval = UART_Init(obj->uart, &obj->cfg, &obj->sys_cfg); MBED_ASSERT(retval == E_NO_ERROR); } @@ -181,7 +181,16 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b void uart_handler(serial_t *obj) { if (obj && obj->id) { - irq_handler(obj->id, RxIrq); + // Check for errors or RX Threshold + if (obj->uart->intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) { + irq_handler(obj->id, RxIrq); + obj->uart->intfl = (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS); + } + // Check for TX Threshold + if (obj->uart->intfl & MXC_F_UART_INTFL_TX_FIFO_AE) { + irq_handler(obj->id, TxIrq); + obj->uart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE; + } } } @@ -199,6 +208,9 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) //****************************************************************************** void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { + MBED_ASSERT(obj->index < MXC_CFG_UART_INSTANCES); + objs[obj->index] = obj; + switch (obj->index) { case 0: NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler); @@ -250,7 +262,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) //****************************************************************************** int serial_getc(serial_t *obj) { - int c = 0; + int c = -1; if (obj->rx != NC) { // Wait for data to be available From 7c6321b303548db168c965bcbdee92c8a7c754aa Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Fri, 2 Feb 2018 10:51:07 -0600 Subject: [PATCH 009/118] Improve SPI block write Replace looping construct with actual block writes. --- .../TARGET_Maxim/TARGET_MAX32625/spi_api.c | 60 +++++++++++++++---- 1 file changed, 49 insertions(+), 11 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c b/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c index a30e145502..b04f7602db 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c @@ -167,19 +167,58 @@ int spi_master_write(spi_t *obj, int value) return *req.rx_data; } -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; +//****************************************************************************** +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill) +{ + spim_req_t req; - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } + if (!(tx_length | rx_length) || + (tx_length < 0) || + (rx_length < 0)) { + return 0; } - return total; + req.width = SPIM_WIDTH_1; + req.ssel = 0; + req.deass = 1; + req.callback = NULL; + + __disable_irq(); + if (tx_length == rx_length) { + req.tx_data = (uint8_t *)tx_buffer; + req.rx_data = (uint8_t *)rx_buffer; + req.len = tx_length; + SPIM_Trans(obj->spi, &req); + } else if (tx_length < rx_length) { + req.tx_data = (tx_length > 0) ? (uint8_t *)tx_buffer : NULL; + req.rx_data = (uint8_t *)rx_buffer; + req.len = (tx_length > 0) ? tx_length : rx_length; + SPIM_Trans(obj->spi, &req); + + if (tx_length) { + req.tx_data = NULL; + req.rx_data = (uint8_t *)(rx_buffer + tx_length); + req.len = rx_length - tx_length; + SPIM_Trans(obj->spi, &req); + } + } else { + req.tx_data = (uint8_t *)tx_buffer; + req.rx_data = (rx_length > 0) ? (uint8_t *)rx_buffer : NULL; + req.len = (rx_length > 0) ? rx_length : tx_length; + SPIM_Trans(obj->spi, &req); + + if (rx_length) { + req.tx_data = (uint8_t *)(tx_buffer + rx_length); + req.rx_data = NULL; + req.len = tx_length - rx_length; + SPIM_Trans(obj->spi, &req); + } + } + __enable_irq(); + + while (SPIM_Busy(obj->spi)); + + return tx_length > rx_length ? tx_length : rx_length; } //****************************************************************************** @@ -193,4 +232,3 @@ uint8_t spi_get_module(spi_t *obj) { return obj->index; } - From 39d589ddbacb4eb437c29aaf42835c5351f0d2a8 Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Fri, 2 Feb 2018 10:55:49 -0600 Subject: [PATCH 010/118] Improve us ticker performance Improves accuracy during heavy work load. --- .../TARGET_Maxim/TARGET_MAX32625/us_ticker.c | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/us_ticker.c b/targets/TARGET_Maxim/TARGET_MAX32625/us_ticker.c index d577f65392..e8988e821e 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/us_ticker.c +++ b/targets/TARGET_Maxim/TARGET_MAX32625/us_ticker.c @@ -33,9 +33,11 @@ #include #include "mbed_error.h" +#include "mbed_critical.h" #include "us_ticker_api.h" #include "PeripheralNames.h" #include "tmr.h" +#include "assert.h" #define US_TIMER MXC_TMR0 #define US_TIMER_IRQn TMR0_0_IRQn @@ -49,7 +51,7 @@ static volatile uint64_t event_cnt; // Holds the value of the next event #define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us) //****************************************************************************** -static inline void inc_current_cnt(uint32_t inc) +static inline void inc_current_cnt_no_crit(uint32_t inc) { // Overflow the ticker when the us ticker overflows current_cnt += inc; @@ -58,6 +60,14 @@ static inline void inc_current_cnt(uint32_t inc) } } +//****************************************************************************** +static inline void inc_current_cnt(uint32_t inc) +{ + core_util_critical_section_enter(); + inc_current_cnt_no_crit(inc); + core_util_critical_section_exit(); +} + //****************************************************************************** static inline int event_passed(uint64_t current, uint64_t event) { @@ -89,11 +99,12 @@ static void tmr_handler(void) { uint32_t cmp = TMR32_GetCompare(US_TIMER); TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // reset to max value to prevent further interrupts + if (TMR32_GetFlag(US_TIMER)) { + inc_current_cnt_no_crit(cmp); + } TMR32_ClearFlag(US_TIMER); NVIC_ClearPendingIRQ(US_TIMER_IRQn); - inc_current_cnt(cmp); - if (event_passed(current_cnt + TMR32_GetCount(US_TIMER), event_cnt)) { // the timestamp has expired event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value @@ -162,6 +173,7 @@ uint32_t us_ticker_read(void) uint64_t current_cnt1, current_cnt2; uint32_t cmp, cnt; uint32_t flag1, flag2; + static uint32_t last = 0; if (!us_ticker_inited) { us_ticker_init(); @@ -179,12 +191,19 @@ uint32_t us_ticker_read(void) // Account for an unserviced interrupt if (flag1) { + // Clear peripheral interrupt flag; leaving NVIC pending set + TMR32_ClearFlag(US_TIMER); + // Advance global count + inc_current_cnt(cmp + cnt); + current_cnt1 += cmp; } current_cnt1 += cnt; - return (current_cnt1 / ticks_per_us); + assert(last <= (current_cnt1 / ticks_per_us)); + last = (current_cnt1 / ticks_per_us); + return last; } //****************************************************************************** @@ -228,6 +247,7 @@ void us_ticker_set_interrupt(timestamp_t timestamp) TMR32_Start(US_TIMER); } +//****************************************************************************** void us_ticker_fire_interrupt(void) { TMR32_SetCompare(US_TIMER, 1); From dce8d29f75376c6cc8f893b06ce0e772f08dfddc Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Fri, 2 Feb 2018 10:58:50 -0600 Subject: [PATCH 011/118] Enable ADC scaling and enable internal channels Increases input range by 2x(now, 0-2.4v) --- targets/TARGET_Maxim/TARGET_MAX32625/PeripheralPins.c | 4 ++++ .../TARGET_MAX32625/TARGET_MAX32625MBED/PinNames.h | 2 +- .../TARGET_MAX32625/TARGET_MAX32625NEXPAQ/PinNames.h | 2 +- targets/TARGET_Maxim/TARGET_MAX32625/analogin_api.c | 4 ++-- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/PeripheralPins.c b/targets/TARGET_Maxim/TARGET_MAX32625/PeripheralPins.c index 488150ecf1..06003960e2 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/PeripheralPins.c +++ b/targets/TARGET_Maxim/TARGET_MAX32625/PeripheralPins.c @@ -163,6 +163,10 @@ const PinMap PinMap_ADC[] = { { AIN_3, ADC, ADC_CH_3 }, { AIN_4, ADC, ADC_CH_0_DIV_5 }, { AIN_5, ADC, ADC_CH_1_DIV_5 }, + { AIN_6, ADC, ADC_CH_VDDB_DIV_4 }, + { AIN_7, ADC, ADC_CH_VDD18 }, + { AIN_8, ADC, ADC_CH_VDD12 }, + { AIN_9, ADC, ADC_CH_VRTC_DIV_2 }, { NC, NC, 0 } }; diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625MBED/PinNames.h b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625MBED/PinNames.h index be72f7ca08..6d3debf7b7 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625MBED/PinNames.h +++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625MBED/PinNames.h @@ -60,7 +60,7 @@ typedef enum { P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, // Analog input pins - AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, + AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9, LED_GREEN = P3_1, LED_RED = P3_0, diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625NEXPAQ/PinNames.h b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625NEXPAQ/PinNames.h index a42da3330f..57e8e35d0b 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625NEXPAQ/PinNames.h +++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625NEXPAQ/PinNames.h @@ -60,7 +60,7 @@ typedef enum { P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, // Analog input pins - AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, + AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9, // LEDs LED1 = P2_4, diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/analogin_api.c b/targets/TARGET_Maxim/TARGET_MAX32625/analogin_api.c index 2f6d348d65..560d535314 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/analogin_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32625/analogin_api.c @@ -65,7 +65,7 @@ float analogin_read(analogin_t *obj) float result; // Start conversion with no input scaling and no input buffer bypass - ADC_StartConvert(obj->channel, 0, 0); + ADC_StartConvert(obj->channel, 1, 0); if (ADC_GetData(&tmp) == E_OVERFLOW) { result = FLOAT_FULL_SCALE; @@ -83,7 +83,7 @@ uint16_t analogin_read_u16(analogin_t *obj) uint16_t result; // Start conversion with no input scaling and no input buffer bypass - ADC_StartConvert(obj->channel, 0, 0); + ADC_StartConvert(obj->channel, 1, 0); if (ADC_GetData(&tmp) == E_OVERFLOW) { result = INT_FULL_SCALE; From eca06e1ca1143728aa8056fc205dd6a556795730 Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Fri, 2 Feb 2018 11:06:52 -0600 Subject: [PATCH 012/118] Remove automatic I2C stop after each read Automatic stop prevents sending repeated start. --- targets/TARGET_Maxim/TARGET_MAX32625/i2c_api.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/i2c_api.c b/targets/TARGET_Maxim/TARGET_MAX32625/i2c_api.c index 6886bee048..a068a23efe 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/i2c_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32625/i2c_api.c @@ -101,7 +101,6 @@ int i2c_stop(i2c_t *obj) //****************************************************************************** int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - MBED_ASSERT(stop != 0); return I2CM_Read(obj->i2c, address >> 1, NULL, 0, (uint8_t *)data, length); } @@ -147,11 +146,6 @@ int i2c_byte_read(i2c_t *obj, int last) if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK) != E_NO_ERROR) { goto byte_write_err; } - - // Send the stop condition - if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP) != E_NO_ERROR) { - goto byte_write_err; - } } else { if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT) != E_NO_ERROR) { goto byte_write_err; From b471d9706288f2b4d40cd7b6b2c722d4f331ef34 Mon Sep 17 00:00:00 2001 From: Keyur Hariya Date: Mon, 26 Feb 2018 11:57:33 -0600 Subject: [PATCH 013/118] Replace enable/disable irq with critical section enter/exit --- targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c b/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c index b04f7602db..7267edfa0d 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c +++ b/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c @@ -183,7 +183,7 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, cha req.deass = 1; req.callback = NULL; - __disable_irq(); + core_util_critical_section_enter(); if (tx_length == rx_length) { req.tx_data = (uint8_t *)tx_buffer; req.rx_data = (uint8_t *)rx_buffer; @@ -214,7 +214,7 @@ int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, cha SPIM_Trans(obj->spi, &req); } } - __enable_irq(); + core_util_critical_section_exit(); while (SPIM_Busy(obj->spi)); From e30b81ab97fa6e741735423af31ba0973997670e Mon Sep 17 00:00:00 2001 From: daid Date: Wed, 14 Feb 2018 18:00:01 +0100 Subject: [PATCH 014/118] Add support for STEVAL-3DP001V1 board, which has an STM32F401VE chip. This support is based on the NUCLEO-F401RE board. Which has the same amount of flash/ram but less pins available on the chip. --- .../targets/TARGET_STM/USBHAL_IP_OTGFSHS.h | 6 + .../targets/TARGET_STM/USBHAL_STM32.h | 1 + .../targets/TARGET_STM/USBHALHost_STM.h | 5 + .../TARGET_STEVAL_3DP001V1/PeripheralNames.h | 77 ++++++ .../TARGET_STEVAL_3DP001V1/PeripheralPins.c | 255 ++++++++++++++++++ .../TARGET_STEVAL_3DP001V1/PinNames.h | 198 ++++++++++++++ .../TARGET_STEVAL_3DP001V1/system_clock.c | 239 ++++++++++++++++ .../device/stm32f4xx_hal_gpio_ex.h | 1 + targets/TARGET_STM/mbed_rtx.h | 3 +- targets/targets.json | 17 ++ tools/build_travis.py | 1 + 11 files changed, 802 insertions(+), 1 deletion(-) create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h index 84c535a04d..73f3b8db15 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_IP_OTGFSHS.h @@ -202,6 +202,12 @@ USBHAL::USBHAL(void) { __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); +#elif defined(TARGET_STEVAL_3DP001V1) + __HAL_RCC_GPIOB_CLK_ENABLE(); + pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM + pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + #else #error "USB pins are not configured !" #endif diff --git a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h index bb6cdda740..f758754951 100644 --- a/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h +++ b/features/unsupported/USBDevice/targets/TARGET_STM/USBHAL_STM32.h @@ -20,6 +20,7 @@ #if defined(TARGET_NUCLEO_F207ZG) || \ defined(TARGET_NUCLEO_F401RE) || \ + defined(TARGET_STEVAL_3DP001V1) || \ defined(TARGET_NUCLEO_F411RE) || \ defined(TARGET_NUCLEO_F412ZG) || \ defined(TARGET_NUCLEO_F413ZH) || \ diff --git a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h index 4f8b5c58a4..02fb5ef4c9 100644 --- a/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h +++ b/features/unsupported/USBHost/targets/TARGET_STM/USBHALHost_STM.h @@ -259,6 +259,11 @@ USBHALHost::USBHALHost() pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); // ID pin_function(PC_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // VBUS +#elif defined(TARGET_STEVAL_3DP001V1) + __HAL_RCC_GPIOA_CLK_ENABLE(); + pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DM + pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); // DP + #else #error "USB pins are not configured !" #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralNames.h new file mode 100644 index 0000000000..bf3ae14ca4 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralNames.h @@ -0,0 +1,77 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE +} ADCName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_6 = (int)USART6_BASE +} UARTName; + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE, + SPI_4 = (int)SPI4_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_9 = (int)TIM9_BASE, + PWM_10 = (int)TIM10_BASE, + PWM_11 = (int)TIM11_BASE +} PWMName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c new file mode 100644 index 0000000000..84ce6c598c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c @@ -0,0 +1,255 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2017, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentionned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: some pins are connected to the default STDIO_UART_TX and STDIO_UART_RX pins. +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)}, + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)}, + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {NC, NC, 0} +}; + +//*** PWM *** + +MBED_WEAK const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // TIM5 used by the us_ticker + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // TIM5 used by the us_ticker + {PA_2_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // TIM5 used by the us_ticker + {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // TIM5 used by the us_ticker + {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 +#endif + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + + {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX (default) + {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX (default) + {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h new file mode 100644 index 0000000000..6e4266e516 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h @@ -0,0 +1,198 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2014, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_2_ALT0 = PA_2|ALT0, + PA_3 = 0x03, + PA_3_ALT0 = PA_3|ALT0, + PA_4 = 0x04, + PA_4_ALT0 = PA_4|ALT0, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_7_ALT0 = PA_7|ALT0, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15|ALT0, + + PB_0 = 0x10, + PB_0_ALT0 = PB_0|ALT0, + PB_1 = 0x11, + PB_1_ALT0 = PB_1|ALT0, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3|ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PB_4|ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5|ALT0, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_8_ALT0 = PB_8|ALT0, + PB_9 = 0x19, + PB_9_ALT0 = PB_9|ALT0, + PB_10 = 0x1A, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_15 = 0x1F, + + PC_0 = 0x20, + PC_1 = 0x21, + PC_2 = 0x22, + PC_3 = 0x23, + PC_4 = 0x24, + PC_5 = 0x25, + PC_6 = 0x26, + PC_7 = 0x27, + PC_8 = 0x28, + PC_9 = 0x29, + PC_10 = 0x2A, + PC_11 = 0x2B, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PH_0 = 0x70, // Connected to RCC_OSC_IN + PH_1 = 0x71, // Connected to RCC_OSC_OUT + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + + // Generic signals namings + LED1 = PA_5, + LED2 = PA_5, + LED3 = PA_5, + LED4 = PA_5, + LED_RED = LED1, + USER_BUTTON = PE_7, + // Standardized button names + BUTTON1 = USER_BUTTON, + SERIAL_TX = STDIO_UART_TX, + SERIAL_RX = STDIO_UART_RX, + USBTX = STDIO_UART_TX, + USBRX = STDIO_UART_RX, + I2C_SCL = PB_8, + I2C_SDA = PB_9, + SPI_MOSI = PA_7, + SPI_MISO = PA_6, + SPI_SCK = PA_5, + SPI_CS = PB_6, + PWM_OUT = PB_3, + + //USB pins + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c new file mode 100644 index 0000000000..c39f4bcb2d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c @@ -0,0 +1,239 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 25 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 25 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 84 + * AHBCLK (MHz) | 84 + * APB1CLK (MHz) | 42 + * APB2CLK (MHz) | 84 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32f4xx.h" +#include "mbed_assert.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (Not connected on board) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (Y1 on board) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + +/* + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + while(1) { + MBED_ASSERT(1); + } + } + } + } + + /* Output clock on MCO2 pin(PC9) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 25 MHz xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 25 MHz clock on OSC_IN + } + + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25) + RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + /* + if (bypass == 0) + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + else + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz + */ + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct; + RCC_ClkInitTypeDef RCC_ClkInitStruct; + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16) + RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336) + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4) + RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { + return 0; // FAIL + } + + /* Output clock on MCO1 pin(PA8) for debugging purpose */ + //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h index b958e4b998..8ff6ae0da7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h @@ -542,6 +542,7 @@ */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ #define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */ diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index b405a29d3d..f4935483be 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -82,7 +82,8 @@ #elif defined(TARGET_STM32L152RE) #define INITIAL_SP (0x20014000UL) -#elif defined(TARGET_STM32F401RE) +#elif (defined(TARGET_STM32F401RE) ||\ + defined(TARGET_STM32F401VE)) #define INITIAL_SP (0x20018000UL) #elif (defined(TARGET_STM32F207ZG) ||\ diff --git a/targets/targets.json b/targets/targets.json index 2e93c15b00..cb93d2b2c8 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1036,6 +1036,23 @@ "release_versions": ["2", "5"], "device_name": "STM32F401RE" }, + "STEVAL_3DP001V1": { + "inherits": ["FAMILY_STM32"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32F4", "STM32F401xE", "STM32F401VE"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI", + "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI", + "macro_name": "CLOCK_SOURCE" + } + }, + "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "HSE_VALUE=25000000"], + "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH", "LOWPOWERTIMER"], + "overrides": {"lse_available": 0}, + "release_versions": ["2", "5"], + "device_name": "STM32F401VE" + }, "NUCLEO_F410RB": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO", "MORPHO"], diff --git a/tools/build_travis.py b/tools/build_travis.py index 6822be1f7f..1ba4efe4a5 100644 --- a/tools/build_travis.py +++ b/tools/build_travis.py @@ -50,6 +50,7 @@ build_list = [ { "target": "NUCLEO_F303ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "NUCLEO_F334R8", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "NUCLEO_F401RE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, + { "target": "STEVAL_3DP001V1", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "NUCLEO_F410RB", "toolchains": "GCC_ARM", "libs": ["dsp"] }, { "target": "NUCLEO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] }, { "target": "NUCLEO_F412ZG", "toolchains": "GCC_ARM", "libs": ["dsp"] }, From c80ff8a8d1b496e1b3c0de1504df1724e98d8356 Mon Sep 17 00:00:00 2001 From: gorazd Date: Wed, 28 Feb 2018 13:16:01 +0100 Subject: [PATCH 015/118] mcu_lpc546xx: move "release_versions" to children --- targets/targets.json | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index cb93d2b2c8..1986e7ec97 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -755,18 +755,19 @@ "inherits": ["Target"], "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], "features": ["LWIP"], - "release_versions": ["2", "5"], "device_name" : "LPC54628J512ET180" }, "LPC546XX": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_LPC546XX"], - "detect_code": ["1056"] + "detect_code": ["1056"], + "release_versions": ["2", "5"] }, "FF_LPC546XX": { "inherits": ["MCU_LPC546XX"], "extra_labels_remove" : ["LPCXpresso"], - "detect_code": ["8081"] + "detect_code": ["8081"], + "release_versions": ["2", "5"] }, "NUCLEO_F030R8": { "inherits": ["FAMILY_STM32"], From 21256b1f2d30dd8c79179fb35170f7d3ad773bb9 Mon Sep 17 00:00:00 2001 From: gorazd Date: Wed, 28 Feb 2018 13:23:38 +0100 Subject: [PATCH 016/118] lpc546xx and lpc54114: fix clock --- .../TARGET_LPC54114/TARGET_LPCXpresso/mbed_overrides.c | 1 - .../TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c | 2 -- .../TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c | 2 -- 3 files changed, 5 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/mbed_overrides.c index 3d49a8cca5..037b2515bf 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/mbed_overrides.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/mbed_overrides.c @@ -41,7 +41,6 @@ void ADC_ClockPower_Configuration(void) POWER_DisablePD(kPDRUNCFG_PD_TEMPS); /* Power on the temperature sensor. */ /* Enable the clock. */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); CLOCK_EnableClock(kCLOCK_Adc0); } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c index a17af3a634..e5418bf47f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c @@ -73,8 +73,6 @@ void ADC_ClockPower_Configuration(void) POWER_DisablePD(kPDRUNCFG_PD_VREFP); /* Power on the reference voltage source. */ POWER_DisablePD(kPDRUNCFG_PD_TS); /* Power on the temperature sensor. */ - /* Enable the clock. */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */ /* Sync clock source is not used. Using sync clock source and would be divided by 2. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c index ccce4750c5..0d95d0345e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c @@ -121,8 +121,6 @@ void ADC_ClockPower_Configuration(void) POWER_DisablePD(kPDRUNCFG_PD_VREFP); /* Power on the reference voltage source. */ POWER_DisablePD(kPDRUNCFG_PD_TS); /* Power on the temperature sensor. */ - /* Enable the clock. */ - CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */ /* Sync clock source is not used. Using sync clock source and would be divided by 2. From ef58ece498790df909d6dca3bfaab5ee2cd4edab Mon Sep 17 00:00:00 2001 From: Paul Thompson Date: Sun, 4 Mar 2018 12:44:21 -0800 Subject: [PATCH 017/118] Clarify intention between comparison to zero and the shift operation Building with (GNU Tools for Arm Embedded Processors 7-2017-q4-major) 7.2.1 20170904 gives this warning ../events/equeue/equeue.c: In function 'equeue_incid': ../events/equeue/equeue.c:40:17: warning: '<<' in boolean context, did you mean '<' ? [-Wint-in-bool-context] if (!(e->id << q->npw2)) { --- events/equeue/equeue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/events/equeue/equeue.c b/events/equeue/equeue.c index 436b45c3eb..173a35db81 100644 --- a/events/equeue/equeue.c +++ b/events/equeue/equeue.c @@ -37,7 +37,7 @@ static inline int equeue_clampdiff(unsigned a, unsigned b) { // Increment the unique id in an event, hiding the event from cancel static inline void equeue_incid(equeue_t *q, struct equeue_event *e) { e->id += 1; - if (!(e->id << q->npw2)) { + if (0 == (e->id << q->npw2)) { e->id = 1; } } From 379b71fbc0e3d9e690d6a12df13d9b5ae4372f52 Mon Sep 17 00:00:00 2001 From: Paul Thompson Date: Mon, 5 Mar 2018 09:40:41 -0800 Subject: [PATCH 018/118] Flip order of comparison --- events/equeue/equeue.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/events/equeue/equeue.c b/events/equeue/equeue.c index 173a35db81..54b29e89b1 100644 --- a/events/equeue/equeue.c +++ b/events/equeue/equeue.c @@ -37,7 +37,7 @@ static inline int equeue_clampdiff(unsigned a, unsigned b) { // Increment the unique id in an event, hiding the event from cancel static inline void equeue_incid(equeue_t *q, struct equeue_event *e) { e->id += 1; - if (0 == (e->id << q->npw2)) { + if ((e->id << q->npw2) == 0) { e->id = 1; } } @@ -469,7 +469,7 @@ void equeue_event_dtor(void *p, void (*dtor)(void *)) { } -// simple callbacks +// simple callbacks struct ecallback { void (*cb)(void*); void *data; From 42d46f93ce6e3034a331f1af248d6ea525f1e3cc Mon Sep 17 00:00:00 2001 From: Jasper de Winkel Date: Tue, 6 Mar 2018 19:07:03 +0100 Subject: [PATCH 019/118] Small typo fixes in readme.md files --- events/README.md | 2 +- features/mbedtls/README.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/events/README.md b/events/README.md index 9e0263ce37..de471f2893 100644 --- a/events/README.md +++ b/events/README.md @@ -113,7 +113,7 @@ queue.dispatch(); // Events can also pass arguments to the underlying callback when both // initially constructed and posted. -Event event(&queue, printf, "recieved %d and %d\n"); +Event event(&queue, printf, "received %d and %d\n"); // Events can be posted multiple times and enqueue gracefully until // the dispatch function is called. diff --git a/features/mbedtls/README.md b/features/mbedtls/README.md index 913cd2cbf1..efb1ceace9 100644 --- a/features/mbedtls/README.md +++ b/features/mbedtls/README.md @@ -10,7 +10,7 @@ This edition of mbed TLS has been adapted for mbed OS and imported from its stan Getting Help and Support ------------------------ -The [mbed TLS website](https://tls.mbed.org/) contains fulll documentation for the library, including function by function descriptions, knowledgebase articles, blogs and a support forum for questions to the community. +The [mbed TLS website](https://tls.mbed.org/) contains full documentation for the library, including function by function descriptions, knowledgebase articles, blogs and a support forum for questions to the community. Contributing to the Project From 98b6f9a30d997fa3beed5e41b4f23a3ac06c457b Mon Sep 17 00:00:00 2001 From: jiangkun1994 Date: Wed, 7 Mar 2018 03:23:42 +0800 Subject: [PATCH 020/118] fixes a typo in README.md --- features/nvstore/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/nvstore/README.md b/features/nvstore/README.md index bd31055ad3..625c7ebb4e 100644 --- a/features/nvstore/README.md +++ b/features/nvstore/README.md @@ -33,7 +33,7 @@ Each item is kept in an entry containing a header and data, where the header hol ### Enabling NVStore and configuring it for your board NVStore is enabled by default for all devices with the internal flash driver (have "FLASH" in the device_has attribute). One can disable it by setting its "enabled" attribute to false. -Unless specifically configured by the user, NVStore selects the last two flash sectors as its areas, with the mininum size of 4KBs, +Unless specifically configured by the user, NVStore selects the last two flash sectors as its areas, with the minimum size of 4KBs, meaning that if the sectors are smaller, few continuous ones will be used for each area. The user can override this by setting the addresses and sizes of both areas in` mbed_lib.json` on a per board basis. In this case, all following four attributes need to be set: From 3ce040aaf2b419bce501579cdad166b878a3ec9b Mon Sep 17 00:00:00 2001 From: jiangkun1994 Date: Wed, 7 Mar 2018 03:27:45 +0800 Subject: [PATCH 021/118] fixes some typos in README.md --- features/FEATURE_BLE/targets/TARGET_CORDIO/README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/README.md b/features/FEATURE_BLE/targets/TARGET_CORDIO/README.md index b6c208d2dc..ba27e139e3 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/README.md +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/README.md @@ -1,10 +1,10 @@ # BLE API Cordio Implementation The BLE API Cordio implementation allows Cordio licensee to easily deliver a -complete and up to date implementation of mbed BLE to their custommers using +complete and up to date implementation of mbed BLE to their customers using mbed OS. -To deliver a BLE port, vendors simply have to provide an HCI driver taillored +To deliver a BLE port, vendors simply have to provide an HCI driver tailored for the BLE module present on the board they want to support. ## Source Organization From 4c67a9f041e935900c2b7dd858b2b03b1260be14 Mon Sep 17 00:00:00 2001 From: jiangkun1994 Date: Wed, 7 Mar 2018 03:33:31 +0800 Subject: [PATCH 022/118] fixes a typo in README.md --- .../targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/README.md b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/README.md index e174e2ce06..0610ab7559 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/README.md +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/README.md @@ -8,7 +8,7 @@ The files are kept the same as much as possible to the Nordic SDK. Modifications ## Porting new versions of Nordic SDK -A list of files currently requierd by mbed is maintained in [script/required_files.txt](https://github.com/ARMmbed/nrf51-sdk/blob/master/script/required_files.txt). [A python script](https://github.com/ARMmbed/nrf51-sdk/blob/master/script/pick_nrf51_files.py) is written to help porting from nordic sdk releases. **required_files.txt** is parsed to find a list of filenames. The script searches for these filenames in the sdk folder, and copy then into the yotta module mirroring the folder structure in the sdk. **extraIncludes** is automatically added to module.json to allow direct inclusion of noridc headers with just the filename. +A list of files currently required by mbed is maintained in [script/required_files.txt](https://github.com/ARMmbed/nrf51-sdk/blob/master/script/required_files.txt). [A python script](https://github.com/ARMmbed/nrf51-sdk/blob/master/script/pick_nrf51_files.py) is written to help porting from nordic sdk releases. **required_files.txt** is parsed to find a list of filenames. The script searches for these filenames in the sdk folder, and copy then into the yotta module mirroring the folder structure in the sdk. **extraIncludes** is automatically added to module.json to allow direct inclusion of noridc headers with just the filename. ### Script usage ``` From bedf76c8bb3f544b257aaa2f1097d4139ba4ffef Mon Sep 17 00:00:00 2001 From: Laurence de Bruxelles Date: Fri, 2 Mar 2018 17:27:38 +0000 Subject: [PATCH 023/118] Allow build profiles to omit language entries --- tools/build_api.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/build_api.py b/tools/build_api.py index 5012e30c70..fcf2687818 100644 --- a/tools/build_api.py +++ b/tools/build_api.py @@ -330,7 +330,7 @@ def prepare_toolchain(src_paths, build_dir, target, toolchain_name, profile = {'c': [], 'cxx': [], 'common': [], 'asm': [], 'ld': []} for contents in build_profile or []: for key in profile: - profile[key].extend(contents[toolchain_name][key]) + profile[key].extend(contents[toolchain_name].get(key, [])) toolchain = cur_tc(target, notify, macros, silent, build_dir=build_dir, extra_verbose=extra_verbose, build_profile=profile) From f8d0c279cdaba2912a7fcfd250409bc667cbd624 Mon Sep 17 00:00:00 2001 From: zzw Date: Tue, 27 Feb 2018 11:49:38 +0800 Subject: [PATCH 024/118] mbed-os_ci-test-fixed_rtl8195am fix section error, ARM compiler uses IRAM1.bss to calculate the heap size fix conflict of _memset between Ameba's library and ARM compiler's library, use standard memset() instead of _memset() in case of ARM compiler --- .../TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c | 4 +++- .../TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct | 3 --- .../TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c | 8 ++++---- .../TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c | 4 ++++ .../TARGET_AMEBA/TARGET_RTL8195A/pwmout_api.c | 4 ++++ .../TARGET_AMEBA/TARGET_RTL8195A/serial_api.c | 5 +++++ .../TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c | 4 ++++ .../TARGET_AMEBA/TARGET_RTL8195A/trng_api.c | 4 ++++ .../sdk/common/api/platform/platform_stdlib.h | 1 + 9 files changed, 29 insertions(+), 8 deletions(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c index 3011f412b1..44ce5b66cd 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c @@ -19,7 +19,9 @@ #include "hal_adc.h" #include "analogin_api.h" - +#ifdef CONFIG_MBED_ENABLED +#include "platform_stdlib.h" +#endif #if CONFIG_ADC_EN #include "pinmap.h" diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct index 03f74e0f69..1485827255 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct @@ -29,9 +29,6 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { *libc.a (+RW) *(.sdram.data*) *lib_peripheral_mbed_arm.ar (+RW) - } - - RW_IRAM2 +0 UNINIT FIXED { *rtl8195a_crypto*.o(+ZI, COMMON) *libc.a (+ZI, COMMON) *(.bss.thread_stack_main) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c index 68d7f44edf..4e7b39657d 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c @@ -18,14 +18,14 @@ #if defined(__CC_ARM) || \ (defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050) -extern uint8_t Image$$RW_IRAM2$$ZI$$Base[]; -extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[]; +extern uint8_t Image$$RW_IRAM1$$ZI$$Base[]; +extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[]; extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[]; extern uint8_t Image$$TCM_OVERLAY$$ZI$$Limit[]; extern uint8_t Image$$RW_DRAM2$$ZI$$Base[]; extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[]; -#define __bss_sram_start__ Image$$RW_IRAM2$$ZI$$Base -#define __bss_sram_end__ Image$$RW_IRAM2$$ZI$$Limit +#define __bss_sram_start__ Image$$RW_IRAM1$$ZI$$Base +#define __bss_sram_end__ Image$$RW_IRAM1$$ZI$$Limit #define __bss_dtcm_start__ Image$$TCM_OVERLAY$$ZI$$Base #define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit #define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c index 9015c81066..621d403a33 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c @@ -17,6 +17,10 @@ #include "objects.h" #include "log_uart_api.h" +#ifdef CONFIG_MBED_ENABLED +#include "platform_stdlib.h" +#endif + #include const u32 log_uart_support_rate[] = { diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/pwmout_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/pwmout_api.c index 47b55c62e8..a73b3418ef 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/pwmout_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/pwmout_api.c @@ -18,6 +18,10 @@ #include "objects.h" #include "pinmap.h" +#ifdef CONFIG_MBED_ENABLED +#include "platform_stdlib.h" +#endif + #if DEVICE_PWMOUT #ifdef CONFIG_PWM_EN diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c index 5a1034da2c..ef0c2228fa 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c @@ -17,6 +17,11 @@ #include "rtl8195a.h" #include "objects.h" #include "serial_api.h" + +#ifdef CONFIG_MBED_ENABLED +#include "platform_stdlib.h" +#endif + #if CONFIG_UART_EN #include "pinmap.h" diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c index 90dd72ffd0..225d29d0bd 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c @@ -21,6 +21,10 @@ #include "pinmap.h" #include "hal_ssi.h" +#ifdef CONFIG_MBED_ENABLED +#include "platform_stdlib.h" +#endif + extern u32 SystemGetCpuClk(VOID); extern VOID HAL_GPIO_PullCtrl(u32 pin, u32 mode); diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/trng_api.c b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/trng_api.c index 06d795220e..5dd1b92faa 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/trng_api.c +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/trng_api.c @@ -17,6 +17,10 @@ #include "analogin_api.h" #include "analogin_ext.h" +#ifdef CONFIG_MBED_ENABLED +#include "platform_stdlib.h" +#endif + #ifdef DEVICE_TRNG diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h index 5bf5c6d1e8..c6dfcf1f69 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h @@ -51,6 +51,7 @@ #include #include "diag.h" #define strsep(str, delim) _strsep(str, delim) + #define _memset(dst, val, sz) memset(dst, val, sz) #else #include #include From 46e7fa873cd93fdb4a42298038567f62aebf276c Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Thu, 22 Feb 2018 11:49:58 +0000 Subject: [PATCH 025/118] Adding Laird BL652 as new target --- .../TARGET_MTB_LAIRD_BL652/PinNames.h | 243 ++++++++++++++++++ .../TARGET_MTB_LAIRD_BL652/device.h | 23 ++ targets/targets.json | 23 ++ 3 files changed, 289 insertions(+) create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/PinNames.h create mode 100644 targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/device.h diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/PinNames.h new file mode 100644 index 0000000000..292aa1e2f5 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/PinNames.h @@ -0,0 +1,243 @@ +/* mbed Microcontroller Library + * Copyright (c) 2013 Nordic Semiconductor + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +#define PORT_SHIFT 3 + +typedef enum { + p0 = 0, + p1 = 1, + p2 = 2, + p3 = 3, + p4 = 4, + p5 = 5, + p6 = 6, + p7 = 7, + p8 = 8, + p9 = 9, + p10 = 10, + p11 = 11, + p12 = 12, + p13 = 13, + p14 = 14, + p15 = 15, + p16 = 16, + p17 = 17, + p18 = 18, + p19 = 19, + p20 = 20, + p21 = 21, + p22 = 22, + p23 = 23, + p24 = 24, + p25 = 25, + p26 = 26, + p27 = 27, + p28 = 28, + p29 = 29, + p30 = 30, + p31 = 31, + + + P0_0 = p0, + P0_1 = p1, + P0_2 = p2, + P0_3 = p3, + P0_4 = p4, + P0_5 = p5, + P0_6 = p6, + P0_7 = p7, + + P0_8 = p8, + P0_9 = p9, + P0_10 = p10, + P0_11 = p11, + P0_12 = p12, + P0_13 = p13, + P0_14 = p14, + P0_15 = p15, + + P0_16 = p16, + P0_17 = p17, + P0_18 = p18, + P0_19 = p19, + P0_20 = p20, + P0_21 = p21, + P0_22 = p22, + P0_23 = p23, + + P0_24 = p24, + P0_25 = p25, + P0_26 = p26, + P0_27 = p27, + P0_28 = p28, + P0_29 = p29, + P0_30 = p30, + P0_31 = p31, + + // Module pins. Refer datasheet for pin numbers. + SIO_1 = P0_1, + SIO_2 = P0_2, + SIO_3 = P0_3, + SIO_4 = P0_4, + SIO_5 = P0_5, + SIO_6 = P0_6, + SIO_7 = P0_7, + SIO_8 = P0_8, + SIO_9 = P0_9, //NFC1 + SIO_10 = P0_10, //NFC2 + SIO_11 = P0_11, + SIO_12 = P0_12, + SIO_13 = P0_13, + SIO_14 = P0_14, + SIO_15 = P0_15, + SIO_16 = P0_16, + SIO_17 = P0_17, + SIO_18 = P0_18, + SIO_19 = P0_19, + SIO_20 = P0_20, + + SIO_22 = P0_22, + SIO_23 = P0_23, + SIO_24 = P0_24, + SIO_25 = P0_25, + SIO_26 = P0_26, + SIO_27 = P0_27, + SIO_28 = P0_28, + SIO_29 = P0_29, + SIO_30 = P0_30, + SIO_31 = P0_31, + SIO_0 = P0_0, + + // Not connected + NC = (int)0xFFFFFFFF, + + //Mbed MTB pin defines. + P_1 = NC, + P_2 = SIO_24, //MISO + P_3 = SIO_23, //MOSI + P_4 = SIO_22, +// P_5 = SWDIO, +// P_6 = SWDCLK, +// P_7 = NRST, + P_8 = SIO_20, + P_9 = SIO_18, + P_10 = SIO_16, + P_11 = SIO_14, + P_12 = SIO_12, + P_13 = SIO_11, + P_14 = SIO_10, + P_15 = SIO_9, + P_16 = NC, + P_17 = SIO_8, + P_18 = SIO_7, + P_19 = SIO_6, + P_20 = SIO_5, + P_21 = SIO_4, + P_22 = SIO_3, + P_23 = SIO_2, + P_24 = SIO_1, + P_25 = SIO_0, + P_26 = NC, + P_27 = NC, + P_28 = SIO_13, + P_29 = SIO_15, + P_30 = SIO_17, + P_31 = SIO_19, + P_32 = SIO_31, + P_33 = SIO_30, + P_34 = SIO_29, + P_35 = SIO_28, + P_36 = SIO_27, + P_37 = SIO_26, + P_38 = SIO_25, + P_39 = NC, + + //LEDs + LED1 = SIO_28, + LED2 = SIO_29, + LED3 = SIO_30, + LED_RED = LED1, + LED_GREEN = LED2, + LED_BLUE = LED3, + + GP0 = SIO_11, + //Standardized button name + BUTTON1 = GP0, + + //Nordic SDK pin names + RX_PIN_NUMBER = SIO_8, + TX_PIN_NUMBER = SIO_6, + CTS_PIN_NUMBER = SIO_7, + RTS_PIN_NUMBER = SIO_5, + + // mBed interface Pins + USBTX = TX_PIN_NUMBER, + USBRX = RX_PIN_NUMBER, + + SPI_MOSI = SIO_23, + SPI_MISO = SIO_24, + SPI_SS0 = SIO_17, //CS for LCD on MTB + SPI_SS1 = SIO_10, //CS for SD card on MTB + SPI_SCK1 = SIO_25, + SPI_SCK2 = SIO_31, + + //Default SPI + SPI_SCK = SPI_SCK1, + SPI_CS = SPI_SS1, + + I2C_SDA = SIO_26, + I2C_SCL = SIO_27, + + //MTB aliases + GP1 = SIO_13, + AIN0 = SIO_2, + AIN1 = SIO_3, + AIN2 = SIO_4, + GP2 = SIO_10, + GP3 = SIO_9, + GP4 = SIO_22, + GP5 = SIO_19, //A0 for LCD on MTB + GP6 = SIO_18, //RESET for LCD on MTB + GP7 = SIO_17, + GP8 = SIO_15, + +} PinName; + +typedef enum { + PullNone = 0, + PullDown = 1, + PullUp = 3, + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/device.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/device.h new file mode 100644 index 0000000000..493844b801 --- /dev/null +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/device.h @@ -0,0 +1,23 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif diff --git a/targets/targets.json b/targets/targets.json index 1986e7ec97..3352528afe 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3535,6 +3535,29 @@ } } }, + "MTB_LAIRD_BL652": { + "inherits": ["MCU_NRF52"], + "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"], + "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"], + "extra_labels_add": ["MTB_LAIRD_BL652"], + "release_versions": ["5"], + "device_name": "nRF52832_xxAA", + "bootloader_supported": true, + "config": { + "usb_tx": { + "help": "Value SIO_06", + "value": "SIO_6" + }, + "usb_rx": { + "help": "Value SIO_08", + "value": "SIO_8" + } + }, + "overrides": { + "lf_clock_src": "NRF_LF_SRC_RC", + "uart_hwfc": 0 + } + }, "DELTA_DFBM_NQ620": { "supported_form_factors": ["ARDUINO"], "inherits": ["MCU_NRF52"], From dc0beb7293d48a4163ac887fd6851d5a788baf36 Mon Sep 17 00:00:00 2001 From: Ashok Rao Date: Tue, 6 Mar 2018 15:38:02 +0000 Subject: [PATCH 026/118] Incorporating review comments --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 3352528afe..4aeb2bdadb 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3555,7 +3555,7 @@ }, "overrides": { "lf_clock_src": "NRF_LF_SRC_RC", - "uart_hwfc": 0 + "uart_hwfc": 0 } }, "DELTA_DFBM_NQ620": { From 4aa652f5f82cc174ca04e8105560a19151073769 Mon Sep 17 00:00:00 2001 From: Senthil Ramakrishnan Date: Mon, 5 Mar 2018 15:26:01 -0600 Subject: [PATCH 027/118] Fix linefeed issues in crash dump output --- .../TARGET_CORTEX_M/mbed_rtx_fault_handler.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.c b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.c index ffa323ea28..0fa7321530 100644 --- a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.c +++ b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.c @@ -194,17 +194,13 @@ void fault_print_str(char *fmtstr, uint32_t *values) char hex_str[9]={0}; while(fmtstr[i] != '\0') { - if(fmtstr[i] == '\n' || fmtstr[i] == '\r') { - serial_putc(&stdio_uart, '\r'); - } else { - if(fmtstr[i]=='%') { - hex_to_str(values[vidx++],hex_str); - for(idx=7; idx>=0; idx--) { - serial_putc(&stdio_uart, hex_str[idx]); - } - } else { - serial_putc(&stdio_uart, fmtstr[i]); + if(fmtstr[i]=='%') { + hex_to_str(values[vidx++],hex_str); + for(idx=7; idx>=0; idx--) { + serial_putc(&stdio_uart, hex_str[idx]); } + } else { + serial_putc(&stdio_uart, fmtstr[i]); } i++; } From 997a69c8ee568b6002e3aebe7db4269e8425be20 Mon Sep 17 00:00:00 2001 From: Senthil Ramakrishnan Date: Mon, 5 Mar 2018 15:30:01 -0600 Subject: [PATCH 028/118] Add mode and privilege info to crash dump --- .../TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S | 9 ++++++-- .../TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S | 7 +++++- .../TARGET_CORTEX_M/TOOLCHAIN_IAR/except.S | 11 +++++++--- .../TARGET_CORTEX_M/mbed_rtx_fault_handler.c | 22 ++++++++++++++++++- .../TARGET_CORTEX_M/mbed_rtx_fault_handler.h | 2 ++ 5 files changed, 44 insertions(+), 7 deletions(-) diff --git a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S index c1b46e054c..036663ca34 100644 --- a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S +++ b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S @@ -144,13 +144,18 @@ Fault_Handler_Continue2 MRS R2,MSP ; Get MSP STR R2,[R1] ADDS R1,#4 - LDR R3,=mbed_fault_handler ; Load address of mbedFaultHandler + MOV R2,LR ; Get current LR(EXC_RETURN) + STR R2,[R1] + ADDS R1,#4 + MRS R2,CONTROL ; Get CONTROL Reg + STR R2,[R1] + LDR R3,=mbed_fault_handler ; Load address of mbedFaultHandler MOV R0,R12 LDR R1,=mbed_fault_context LDR R2,=osRtxInfo BLX R3 #endif - B . ; Just in case we come back here + B . ; Just in case we come back here ENDP #endif diff --git a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S index f6f081007a..94937384b1 100644 --- a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S +++ b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S @@ -176,7 +176,12 @@ Fault_Handler_Continue2: MRS R2,MSP // Get MSP STR R2,[R1] ADDS R1,#4 - LDR R3,=mbed_fault_handler // Load address of mbedFaultHandler + MOV R2,LR // Get current LR(EXC_RETURN) + STR R2,[R1] + ADDS R1,#4 + MRS R2,CONTROL // Get CONTROL Reg + STR R2,[R1] + LDR R3,=mbed_fault_handler // Load address of mbedFaultHandler MOV R0,R12 LDR R1,=mbed_fault_context LDR R2,=osRtxInfo diff --git a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_IAR/except.S b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_IAR/except.S index 1e5b5a6dbb..7b85e25a98 100644 --- a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_IAR/except.S +++ b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_IAR/except.S @@ -139,13 +139,18 @@ Fault_Handler_Continue2 MRS R2,MSP ; Get MSP STR R2,[R1] ADDS R1,#4 - LDR R3,=mbed_fault_handler ; Load address of mbedFaultHandler + MOV R2,LR ; Get current LR(EXC_RETURN) + STR R2,[R1] + ADDS R1,#4 + MRS R2,CONTROL ; Get CONTROL Reg + STR R2,[R1] + LDR R3,=mbed_fault_handler ; Load address of mbedFaultHandler MOV R0,R12 LDR R1,=mbed_fault_context LDR R2,=osRtxInfo BLX R3 #endif - B . ; Just in case we come back here -#endif ; #if (MBED_FAULT_HANDLER_SUPPORT == 1) + B . ; Just in case we come back here +#endif ; #if (MBED_FAULT_HANDLER_SUPPORT == 1) END diff --git a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.c b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.c index 0fa7321530..4cb3762b1d 100644 --- a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.c +++ b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.c @@ -143,7 +143,27 @@ void print_context_info() fault_print_str("\nBFAR : %",(uint32_t *)&SCB->BFAR); } #endif - + //Print Mode + if(mbed_fault_context.EXC_RETURN & 0x8) { + fault_print_str("\nMode : Thread", NULL); + //Print Priv level in Thread mode - We capture CONTROL reg which reflects the privilege. + //Note that the CONTROL register captured still reflects the privilege status of the + //thread mode eventhough we are in Handler mode by the time we capture it. + if(mbed_fault_context.CONTROL & 0x1) { + fault_print_str("\nPriv : User", NULL); + } else { + fault_print_str("\nPriv : Privileged", NULL); + } + } else { + fault_print_str("\nMode : Handler", NULL); + fault_print_str("\nPriv : Privileged", NULL); + } + //Print Return Stack + if(mbed_fault_context.EXC_RETURN & 0x4) { + fault_print_str("\nStack: PSP", NULL); + } else { + fault_print_str("\nStack: MSP", NULL); + } } /* Prints thread info from a list */ diff --git a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.h b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.h index 75628876d0..54c85c736f 100644 --- a/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.h +++ b/rtos/TARGET_CORTEX/TARGET_CORTEX_M/mbed_rtx_fault_handler.h @@ -37,6 +37,8 @@ typedef struct { uint32_t xPSR; uint32_t PSP; uint32_t MSP; + uint32_t EXC_RETURN; + uint32_t CONTROL; } mbed_fault_context_t; //Fault type definitions From c279da61fc701a0e8ff2edc722ce9455c624eb57 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Wed, 7 Mar 2018 12:45:49 +0200 Subject: [PATCH 029/118] Fixed Cellular unit tests by adding one missing stub after changes in mbed-os. --- .../target_h/platform/mbed_power_mgmt.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 features/cellular/UNITTESTS/target_h/platform/mbed_power_mgmt.h diff --git a/features/cellular/UNITTESTS/target_h/platform/mbed_power_mgmt.h b/features/cellular/UNITTESTS/target_h/platform/mbed_power_mgmt.h new file mode 100644 index 0000000000..2810b22dae --- /dev/null +++ b/features/cellular/UNITTESTS/target_h/platform/mbed_power_mgmt.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) , Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + From aa05e889925e026bf4c16972b40e3e8982af51d5 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Tue, 6 Mar 2018 09:29:40 -0600 Subject: [PATCH 030/118] MCUXpresso_MCUS: Apply K64F us_ticker fix across all MCU's Applied changes from commit b6a01de0705e2385be516ea8b2f90cfabd295465 for other MCUXpresso MCUs Signed-off-by: Mahesh Mahadevan --- .../TARGET_K66F/us_ticker.c | 8 ++++++-- .../TARGET_K82F/us_ticker.c | 8 ++++++-- .../TARGET_KL27Z/us_ticker.c | 8 ++++++-- .../TARGET_KL43Z/us_ticker.c | 8 ++++++-- .../TARGET_KL82Z/us_ticker.c | 8 ++++++-- .../TARGET_KW24D/us_ticker.c | 8 ++++++-- .../TARGET_KW41Z/us_ticker.c | 18 +++++++++++------- .../TARGET_MCU_K22F/us_ticker.c | 8 ++++++-- .../TARGET_MCU_K24F/us_ticker.c | 8 ++++++-- .../TARGET_MCU_K64F/us_ticker.c | 1 - .../TARGET_IMX/us_ticker.c | 8 ++++++-- 11 files changed, 65 insertions(+), 26 deletions(-) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c index dc6ab710f4..a7e1a96896 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c @@ -83,10 +83,14 @@ void us_ticker_clear_interrupt(void) void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); + uint32_t now_us, delta_us; + + now_us = us_ticker_read(); + delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); + PIT_StopTimer(PIT, kPIT_Chnl_3); PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us); PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); PIT_StartTimer(PIT, kPIT_Chnl_3); PIT_StartTimer(PIT, kPIT_Chnl_2); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c index dc6ab710f4..a7e1a96896 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c @@ -83,10 +83,14 @@ void us_ticker_clear_interrupt(void) void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); + uint32_t now_us, delta_us; + + now_us = us_ticker_read(); + delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); + PIT_StopTimer(PIT, kPIT_Chnl_3); PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us); PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); PIT_StartTimer(PIT, kPIT_Chnl_3); PIT_StartTimer(PIT, kPIT_Chnl_2); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c index 43f7dc0bb4..e2af074052 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c @@ -90,9 +90,13 @@ void us_ticker_clear_interrupt(void) void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); + uint32_t now_us, delta_us; + + now_us = us_ticker_read(); + delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); + LPTMR_StopTimer(LPTMR0); - LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta); + LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta_us); LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable); LPTMR_StartTimer(LPTMR0); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c index 43f7dc0bb4..e2af074052 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c @@ -90,9 +90,13 @@ void us_ticker_clear_interrupt(void) void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); + uint32_t now_us, delta_us; + + now_us = us_ticker_read(); + delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); + LPTMR_StopTimer(LPTMR0); - LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta); + LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta_us); LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable); LPTMR_StartTimer(LPTMR0); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c index 3914226759..7205210a3f 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c @@ -83,10 +83,14 @@ void us_ticker_clear_interrupt(void) void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); + uint32_t now_us, delta_us; + + now_us = us_ticker_read(); + delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); + PIT_StopTimer(PIT, kPIT_Chnl_3); PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us); PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); PIT_StartTimer(PIT, kPIT_Chnl_3); PIT_StartTimer(PIT, kPIT_Chnl_2); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c index dc6ab710f4..a7e1a96896 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c @@ -83,10 +83,14 @@ void us_ticker_clear_interrupt(void) void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); + uint32_t now_us, delta_us; + + now_us = us_ticker_read(); + delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); + PIT_StopTimer(PIT, kPIT_Chnl_3); PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us); PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); PIT_StartTimer(PIT, kPIT_Chnl_3); PIT_StartTimer(PIT, kPIT_Chnl_2); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c index 5246cf8d62..e2af074052 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c @@ -30,7 +30,7 @@ static void lptmr_isr(void) us_ticker_irq_handler(); } -void us_ticker_init(void) +void us_ticker_init(void) { if (us_ticker_inited) { return; @@ -69,7 +69,7 @@ void us_ticker_init(void) } -uint32_t us_ticker_read() +uint32_t us_ticker_read() { if (!us_ticker_inited) { us_ticker_init(); @@ -78,21 +78,25 @@ uint32_t us_ticker_read() return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1)); } -void us_ticker_disable_interrupt(void) +void us_ticker_disable_interrupt(void) { LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable); } -void us_ticker_clear_interrupt(void) +void us_ticker_clear_interrupt(void) { LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag); } -void us_ticker_set_interrupt(timestamp_t timestamp) +void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); + uint32_t now_us, delta_us; + + now_us = us_ticker_read(); + delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); + LPTMR_StopTimer(LPTMR0); - LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta); + LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta_us); LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable); LPTMR_StartTimer(LPTMR0); } diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c index dc6ab710f4..a7e1a96896 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c @@ -83,10 +83,14 @@ void us_ticker_clear_interrupt(void) void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); + uint32_t now_us, delta_us; + + now_us = us_ticker_read(); + delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); + PIT_StopTimer(PIT, kPIT_Chnl_3); PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us); PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); PIT_StartTimer(PIT, kPIT_Chnl_3); PIT_StartTimer(PIT, kPIT_Chnl_2); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c index a4b32f8c3f..3ce51d72d3 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c @@ -83,10 +83,14 @@ void us_ticker_clear_interrupt(void) void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); + uint32_t now_us, delta_us; + + now_us = us_ticker_read(); + delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); + PIT_StopTimer(PIT, kPIT_Chnl_3); PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us); PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); PIT_StartTimer(PIT, kPIT_Chnl_3); PIT_StartTimer(PIT, kPIT_Chnl_2); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c index e4796608a0..a7e1a96896 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c @@ -88,7 +88,6 @@ void us_ticker_set_interrupt(timestamp_t timestamp) now_us = us_ticker_read(); delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); - uint32_t delta = timestamp - us_ticker_read(); PIT_StopTimer(PIT, kPIT_Chnl_3); PIT_StopTimer(PIT, kPIT_Chnl_2); PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c index 35235eaa86..3724dd0d7e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c @@ -87,10 +87,14 @@ void us_ticker_clear_interrupt(void) void us_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delta = timestamp - us_ticker_read(); + uint32_t now_us, delta_us; + + now_us = us_ticker_read(); + delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us); + PIT_StopTimer(PIT, kPIT_Chnl_3); PIT_StopTimer(PIT, kPIT_Chnl_2); - PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta); + PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us); PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable); PIT_StartTimer(PIT, kPIT_Chnl_3); PIT_StartTimer(PIT, kPIT_Chnl_2); From 2a3d6d4349a5a32693edf92223ee008b5b9e8a4b Mon Sep 17 00:00:00 2001 From: amq Date: Fri, 9 Mar 2018 16:10:10 +0100 Subject: [PATCH 031/118] Make gpio interrupts faster by offloading expected state check to user --- targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c index b47627f76f..4816d0f25e 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c @@ -61,15 +61,11 @@ static void handle_interrupt_in(uint8_t pin) return; } - //we are storing two ports in each uint8, so we must aquire the one we want. - // If pin is odd, the port is encoded in the 4 most significant bits. If pin is even, the port is encoded in the 4 least significant bits - uint8_t isRise = GPIO_PinInGet((pin & 0x1) ? channel_ports[(pin>>1) & 0x7] >> 4 & 0xF : channel_ports[(pin>>1) & 0x7] & 0xF, pin); - // Get trigger event gpio_irq_event event = IRQ_NONE; - if ((GPIO->EXTIFALL & (1 << pin)) && !isRise) { + if (GPIO->EXTIFALL & (1 << pin)) { event = IRQ_FALL; - } else if ((GPIO->EXTIRISE & (1 << pin)) && isRise) { + } else if (GPIO->EXTIRISE & (1 << pin)) { event = IRQ_RISE; } GPIO_IntClear(pin); From 5f848b175dd83a840716ad90bf189d9996ae65fb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Fri, 9 Mar 2018 14:03:17 +0200 Subject: [PATCH 032/118] Cellular: ATHandler write improvements. --- features/cellular/framework/AT/ATHandler.cpp | 65 ++++++-------------- features/cellular/framework/AT/ATHandler.h | 2 +- 2 files changed, 19 insertions(+), 48 deletions(-) diff --git a/features/cellular/framework/AT/ATHandler.cpp b/features/cellular/framework/AT/ATHandler.cpp index 2c3d6006c5..eda2aa912a 100644 --- a/features/cellular/framework/AT/ATHandler.cpp +++ b/features/cellular/framework/AT/ATHandler.cpp @@ -314,7 +314,7 @@ void ATHandler::fill_buffer() } while ((uint32_t)timer.read_ms() < _at_timeout); set_error(NSAPI_ERROR_DEVICE_ERROR); - tr_error("AT TIMEOUT, scope: %d timeout: %lu", _current_scope, _at_timeout); + tr_debug("AT TIMEOUT, scope: %d timeout: %lu", _current_scope, _at_timeout); } int ATHandler::get_char() @@ -846,7 +846,7 @@ bool ATHandler::consume_to_tag(const char *tag, bool consume_tag) match_pos = 0; } } - tr_error("consume_to_tag not found"); + tr_debug("consume_to_tag not found"); return false; } @@ -862,7 +862,7 @@ bool ATHandler::consume_to_stop_tag() return true; } - tr_error("consume_to_stop_tag not found"); + tr_debug("consume_to_stop_tag not found"); set_error(NSAPI_ERROR_DEVICE_ERROR); return false; } @@ -942,13 +942,7 @@ void ATHandler::cmd_start(const char* cmd) return; } - // write command - for (size_t i = 0; i < strlen(cmd); i++) { - if (write_char(cmd[i]) == false) { - // writing failed ---> write_char have set the last error, return... - return; - } - } + (void)write(cmd, strlen(cmd)); _cmd_start = true; } @@ -966,12 +960,7 @@ void ATHandler::write_int(int32_t param) char number_string[str_len]; int32_t result = sprintf(number_string, "%ld", param); if (result > 0 && result < str_len) { - for (size_t i = 0; number_string[i]; i++) { - if (write_char(number_string[i]) == false) { - // writing failed ---> write_char have set the last error, break out - break; - } - } + (void)write(number_string, strlen(number_string)); } } @@ -984,20 +973,15 @@ void ATHandler::write_string(const char* param, bool useQuotations) } // we are writing string, surround it with quotes - if (useQuotations && write_char('\"') == false) { + if (useQuotations && write("\"", 1) != 1) { return; } - for (size_t i = 0; i < strlen(param); i++) { - if (write_char(param[i]) == false) { - // writing failed ---> write_char have set the last error, return - break; - } - } + (void)write(param, strlen(param)); if (useQuotations) { // we are writing string, surround it with quotes - write_char('\"'); + (void)write("\"", 1); } } @@ -1007,11 +991,7 @@ void ATHandler::cmd_stop() return; } // Finish with CR - for (size_t i = 0; i < _output_delimiter_length; i++) { - if (write_char(_output_delimiter[i]) == false) { - break; - } - } + (void)write(_output_delimiter, _output_delimiter_length); } size_t ATHandler::write_bytes(const uint8_t *data, size_t len) @@ -1020,36 +1000,27 @@ size_t ATHandler::write_bytes(const uint8_t *data, size_t len) return 0; } - size_t i = 0; - for (; i < len; i++) { - if (write_char(data[i]) == false) { - // writing failed ---> write_char have set the last error, return - break; - } - } - - return i; + ssize_t write_len = write(data, len); + return write_len < 0 ? 0 : (size_t)write_len; } -bool ATHandler::write_char(char c) +ssize_t ATHandler::write(const void *data, size_t len) { pollfh fhs; fhs.fh = _fileHandle; fhs.events = POLLOUT; - bool retVal = true; + ssize_t write_len = -1; int count = poll(&fhs, 1, _at_timeout); if (count > 0 && (fhs.revents & POLLOUT)) { - retVal = _fileHandle->write(&c, 1) == 1 ? true : false; - } else { - retVal = false; + write_len = _fileHandle->write(data, len); } - if (retVal == false) { + if (write_len < 0 || (size_t)write_len != len) { set_error(NSAPI_ERROR_DEVICE_ERROR); } - return retVal; + return write_len; } // do common checks before sending subparameters @@ -1063,8 +1034,8 @@ bool ATHandler::check_cmd_send() if (_cmd_start) { _cmd_start = false; } else { - if (write_char(_delimiter) == false) { - // writing of delimiter failed, return. write_char already have set the _last_err + if (write(&_delimiter, 1) != 1) { + // writing of delimiter failed, return. write() already have set the _last_err return false; } } diff --git a/features/cellular/framework/AT/ATHandler.h b/features/cellular/framework/AT/ATHandler.h index accabe5c79..5410d6f709 100644 --- a/features/cellular/framework/AT/ATHandler.h +++ b/features/cellular/framework/AT/ATHandler.h @@ -446,7 +446,7 @@ private: void set_3gpp_error(int err, DeviceErrorType error_type); bool check_cmd_send(); - bool write_char(char c); + ssize_t write(const void *data, size_t len); /** Copy content of one char buffer to another buffer and sets NULL terminator * From 923541089f83e54da61b4a86f61954f7f6f843c3 Mon Sep 17 00:00:00 2001 From: Evan Hosseini Date: Thu, 8 Mar 2018 16:37:48 -0600 Subject: [PATCH 033/118] mts_mdot_f411re: Fix for Multi-Tech mDot IAR linker script --- .../TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf index d472306bb0..1d635eea62 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf @@ -1,5 +1,5 @@ /* [ROM = 512kb = 0x80000] */ -define symbol __intvec_start__ = 0x08000000; +define symbol __intvec_start__ = 0x08010000; define symbol __region_ROM_start__ = 0x08010000; define symbol __region_ROM_end__ = 0x0807FFFF; From 28f5d8e47d3f3e901e4c2c1d7e3332ef8fdb772a Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 9 Mar 2018 08:04:54 -0600 Subject: [PATCH 034/118] K82F: Fix I2C test failures seen with ci-test shield I2C3 clock define was missing. I2C3 is connected to the Arduino connector which is used by the ci-test shield Signed-off-by: Mahesh Mahadevan --- .../TARGET_K82F/peripheral_clock_defines.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/peripheral_clock_defines.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/peripheral_clock_defines.h index f65b2d9e4d..115b5975c4 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/peripheral_clock_defines.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/peripheral_clock_defines.h @@ -36,7 +36,7 @@ /* Array for I2C module clocks */ #define I2C_CLOCK_FREQS \ { \ - I2C0_CLK_SRC, I2C1_CLK_SRC, I2C2_CLK_SRC \ + I2C0_CLK_SRC, I2C1_CLK_SRC, I2C2_CLK_SRC, I2C3_CLK_SRC \ } /* Array for DSPI module clocks */ From 4cd58fe41a081448a0a7608235ec8233a9c2faac Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 9 Mar 2018 08:18:21 -0600 Subject: [PATCH 035/118] MCUXpresso: Enable I2C SDA & SCL pins internal pullup resistors Signed-off-by: Mahesh Mahadevan --- .../TARGET_MCUXpresso_MCUS/api/i2c_api.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c index 7ff72f3881..a731d5b193 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c @@ -36,6 +36,9 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) { uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); + PORT_Type *port_addrs[] = PORT_BASE_PTRS; + PORT_Type *base = port_addrs[sda >> GPIO_PORT_SHIFT]; + obj->instance = pinmap_merge(i2c_sda, i2c_scl); obj->next_repeated_start = 0; MBED_ASSERT((int)obj->instance != NC); @@ -49,10 +52,11 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) pinmap_pinout(sda, PinMap_I2C_SDA); pinmap_pinout(scl, PinMap_I2C_SCL); -#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN - PORT_Type *port_addrs[] = PORT_BASE_PTRS; - PORT_Type *base = port_addrs[sda >> GPIO_PORT_SHIFT]; + /* Enable internal pullup resistor */ + base->PCR[sda & 0xFF] |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK); + base->PCR[scl & 0xFF] |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK); +#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN base->PCR[sda & 0xFF] |= PORT_PCR_ODE_MASK; base->PCR[scl & 0xFF] |= PORT_PCR_ODE_MASK; #endif From 29ab0cd3a1f237dcb63e1a9e944f76f81cf4b639 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 9 Mar 2018 08:32:22 -0600 Subject: [PATCH 036/118] MCUXpresso: Update the I2C implmentation for byte read and write 1. Start function: Issue repeat start when bus is busy 2. Byte write function: Do not call SDK function as this does not work for some of the Kinetis device 3. Byte read function: Do not call SDK function as this would issue a START and STOP signal which is not required for I2C byte functions Signed-off-by: Mahesh Mahadevan --- .../TARGET_MCUXpresso_MCUS/api/i2c_api.c | 82 ++++++++++++------- 1 file changed, 54 insertions(+), 28 deletions(-) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c index a731d5b193..452faf781d 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c @@ -67,12 +67,14 @@ int i2c_start(i2c_t *obj) I2C_Type *base = i2c_addrs[obj->instance]; uint32_t statusFlags = I2C_MasterGetStatusFlags(base); - /* Return an error if the bus is already in use. */ + /* Check if the bus is already in use. */ if (statusFlags & kI2C_BusBusyFlag) { - return 1; + /* Send a repeat START signal. */ + base->C1 |= I2C_C1_RSTA_MASK; + } else { + /* Send the START signal. */ + base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; } - /* Send the START signal. */ - base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK; #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING while (!(base->S2 & I2C_S2_EMPTY_MASK)) @@ -85,7 +87,6 @@ int i2c_start(i2c_t *obj) int i2c_stop(i2c_t *obj) { - obj->next_repeated_start = 0; if (I2C_MasterStop(i2c_addrs[obj->instance]) != kStatus_Success) { return 1; } @@ -183,39 +184,64 @@ int i2c_byte_read(i2c_t *obj, int last) { uint8_t data; I2C_Type *base = i2c_addrs[obj->instance]; - i2c_master_transfer_t master_xfer; - memset(&master_xfer, 0, sizeof(master_xfer)); - master_xfer.slaveAddress = i2c_address; - master_xfer.direction = kI2C_Read; - master_xfer.data = &data; - master_xfer.dataSize = 1; + /* Setup the I2C peripheral to receive data. */ + base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK); - /* The below function will issue a STOP signal at the end of the transfer. - * This is required by the hardware in order to receive the last byte - */ - if (I2C_MasterTransferBlocking(base, &master_xfer) != kStatus_Success) { - return I2C_ERROR_NO_SLAVE; + if (last) { + base->C1 |= I2C_C1_TXAK_MASK; // NACK } + + data = (base->D & 0xFF); + + /* Change direction to Tx to avoid extra clocks. */ + base->C1 |= I2C_C1_TX_MASK; + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) + { + } + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + return data; } int i2c_byte_write(i2c_t *obj, int data) { - status_t ret_value; -#if FSL_I2C_DRIVER_VERSION > MAKE_VERSION(2, 0, 1) - ret_value = I2C_MasterWriteBlocking(i2c_addrs[obj->instance], (uint8_t *)(&data), 1, kI2C_TransferNoStopFlag); -#else - ret_value = I2C_MasterWriteBlocking(i2c_addrs[obj->instance], (uint8_t *)(&data), 1); -#endif + int ret_value = 1; + uint8_t statusFlags = 0; + I2C_Type *base = i2c_addrs[obj->instance]; - if (ret_value == kStatus_Success) { - return 1; - } else if (ret_value == kStatus_I2C_Nak) { - return 0; - } else { - return 2; + /* Setup the I2C peripheral to transmit data. */ + base->C1 |= I2C_C1_TX_MASK; + + /* Send a byte of data. */ + base->D = data; + + /* Wait until data transfer complete. */ + while (!(base->S & kI2C_IntPendingFlag)) { } + + statusFlags = base->S; + + /* Clear the IICIF flag. */ + base->S = kI2C_IntPendingFlag; + + /* Check if arbitration lost */ + if (statusFlags & kI2C_ArbitrationLostFlag) { + base->S = kI2C_ArbitrationLostFlag; + ret_value = 2; + } + + /* Check if no acknowledgement (NAK) */ + if (statusFlags & kI2C_ReceiveNakFlag) { + base->S = kI2C_ReceiveNakFlag; + ret_value = 0; + } + + return ret_value; } From 7c7d89731bebbfd8c0414e1fda08108891351c27 Mon Sep 17 00:00:00 2001 From: Wolfgang Betz Date: Thu, 8 Mar 2018 13:57:37 +0100 Subject: [PATCH 037/118] Align `ATCmdParser::process_oob()` to `ATCmdParser::vrecv()`'s newline handling --- platform/ATCmdParser.cpp | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/platform/ATCmdParser.cpp b/platform/ATCmdParser.cpp index a787b58b2a..50478c2c49 100644 --- a/platform/ATCmdParser.cpp +++ b/platform/ATCmdParser.cpp @@ -394,6 +394,19 @@ bool ATCmdParser::process_oob() if (c < 0) { return false; } + // Simplify newlines (borrowed from retarget.cpp) + if ((c == CR && _in_prev != LF) || + (c == LF && _in_prev != CR)) { + _in_prev = c; + c = '\n'; + } else if ((c == CR && _in_prev == LF) || + (c == LF && _in_prev == CR)) { + _in_prev = c; + // onto next character + continue; + } else { + _in_prev = c; + } _buffer[i++] = c; _buffer[i] = 0; @@ -411,9 +424,7 @@ bool ATCmdParser::process_oob() // Clear the buffer when we hit a newline or ran out of space // running out of space usually means we ran into binary data - if (i+1 >= _buffer_size || - strcmp(&_buffer[i-_output_delim_size], _output_delimiter) == 0) { - + if (((i+1) >= _buffer_size) || (c == '\n')) { debug_if(_dbg_on, "AT< %s", _buffer); i = 0; } From a8915ba45f4a95adc119436167b19f543dde0a4e Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Thu, 8 Mar 2018 12:46:54 +0200 Subject: [PATCH 038/118] Fix initialization of phy_params.payloads_with_repeater.size --- features/lorawan/lorastack/phy/LoRaPHYAS923.cpp | 2 +- features/lorawan/lorastack/phy/LoRaPHYAU915.cpp | 2 +- features/lorawan/lorastack/phy/LoRaPHYCN470.cpp | 2 +- features/lorawan/lorastack/phy/LoRaPHYCN779.cpp | 2 +- features/lorawan/lorastack/phy/LoRaPHYEU433.cpp | 2 +- features/lorawan/lorastack/phy/LoRaPHYEU868.cpp | 2 +- features/lorawan/lorastack/phy/LoRaPHYIN865.cpp | 2 +- features/lorawan/lorastack/phy/LoRaPHYKR920.cpp | 2 +- features/lorawan/lorastack/phy/LoRaPHYUS915.cpp | 2 +- features/lorawan/lorastack/phy/LoRaPHYUS915Hybrid.cpp | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/features/lorawan/lorastack/phy/LoRaPHYAS923.cpp b/features/lorawan/lorastack/phy/LoRaPHYAS923.cpp index 5a10bca24b..bd9ededc37 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYAS923.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYAS923.cpp @@ -280,7 +280,7 @@ LoRaPHYAS923::LoRaPHYAS923(LoRaWANTimeHandler &lora_time) phy_params.payloads.table = (void *) max_payload_table; phy_params.payloads.size = 8; phy_params.payloads_with_repeater.table = (void *) max_payload_table_with_repeater; - phy_params.payloads.size = 8; + phy_params.payloads_with_repeater.size = 8; // dwell time setting, 400 ms phy_params.ul_dwell_time_setting = 1; diff --git a/features/lorawan/lorastack/phy/LoRaPHYAU915.cpp b/features/lorawan/lorastack/phy/LoRaPHYAU915.cpp index c1e1ecd2f9..9c262a9a62 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYAU915.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYAU915.cpp @@ -279,7 +279,7 @@ LoRaPHYAU915::LoRaPHYAU915(LoRaWANTimeHandler &lora_time) phy_params.payloads.table = (void *) max_payload_AU915; phy_params.payloads.size = 16; phy_params.payloads_with_repeater.table = (void *) max_payload_with_repeater_AU915; - phy_params.payloads.size = 16; + phy_params.payloads_with_repeater.size = 16; // dwell time setting phy_params.ul_dwell_time_setting = 0; diff --git a/features/lorawan/lorastack/phy/LoRaPHYCN470.cpp b/features/lorawan/lorastack/phy/LoRaPHYCN470.cpp index 68ff3f5525..c3415a554d 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYCN470.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYCN470.cpp @@ -252,7 +252,7 @@ LoRaPHYCN470::LoRaPHYCN470(LoRaWANTimeHandler &lora_time) phy_params.payloads.table = (void *) max_payloads_CN470; phy_params.payloads.size = 6; phy_params.payloads_with_repeater.table = (void *)max_payloads_with_repeater_CN470; - phy_params.payloads.size = 6; + phy_params.payloads_with_repeater.size = 6; // dwell time setting phy_params.ul_dwell_time_setting = 0; diff --git a/features/lorawan/lorastack/phy/LoRaPHYCN779.cpp b/features/lorawan/lorastack/phy/LoRaPHYCN779.cpp index 66783d32a2..a5e2137396 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYCN779.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYCN779.cpp @@ -268,7 +268,7 @@ LoRaPHYCN779::LoRaPHYCN779(LoRaWANTimeHandler &lora_time) phy_params.payloads.table = (void *) max_payloads_CN779; phy_params.payloads.size = 8; phy_params.payloads_with_repeater.table = (void *) max_payloads_with_repeater_CN779; - phy_params.payloads.size = 8; + phy_params.payloads_with_repeater.size = 8; // dwell time setting phy_params.ul_dwell_time_setting = 0; diff --git a/features/lorawan/lorastack/phy/LoRaPHYEU433.cpp b/features/lorawan/lorastack/phy/LoRaPHYEU433.cpp index 6345b5395c..b0e5f3841e 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYEU433.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYEU433.cpp @@ -269,7 +269,7 @@ LoRaPHYEU433::LoRaPHYEU433(LoRaWANTimeHandler &lora_time) phy_params.payloads.table = (void *) max_payloads_EU433; phy_params.payloads.size = 8; phy_params.payloads_with_repeater.table = (void *) max_payloads_with_repeater_EU433; - phy_params.payloads.size = 8; + phy_params.payloads_with_repeater.size = 8; // dwell time setting phy_params.ul_dwell_time_setting = 0; diff --git a/features/lorawan/lorastack/phy/LoRaPHYEU868.cpp b/features/lorawan/lorastack/phy/LoRaPHYEU868.cpp index fcf8c4ce7f..4c0b1a369b 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYEU868.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYEU868.cpp @@ -299,7 +299,7 @@ LoRaPHYEU868::LoRaPHYEU868(LoRaWANTimeHandler &lora_time) phy_params.payloads.table = (void *) max_payloads_EU868; phy_params.payloads.size = 8; phy_params.payloads_with_repeater.table = (void *) max_payloads_repeater_EU868; - phy_params.payloads.size = 8; + phy_params.payloads_with_repeater.size = 8; // dwell time setting phy_params.ul_dwell_time_setting = 0; diff --git a/features/lorawan/lorastack/phy/LoRaPHYIN865.cpp b/features/lorawan/lorastack/phy/LoRaPHYIN865.cpp index 5ab3bc8f35..80aa112c0c 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYIN865.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYIN865.cpp @@ -270,7 +270,7 @@ LoRaPHYIN865::LoRaPHYIN865(LoRaWANTimeHandler &lora_time) phy_params.payloads.table = (void *) max_payloads_IN865; phy_params.payloads.size = 8; phy_params.payloads_with_repeater.table = (void *) max_payloads_with_repeater; - phy_params.payloads.size = 8; + phy_params.payloads_with_repeater.size = 8; // dwell time setting phy_params.ul_dwell_time_setting = 0; diff --git a/features/lorawan/lorastack/phy/LoRaPHYKR920.cpp b/features/lorawan/lorastack/phy/LoRaPHYKR920.cpp index 74f67c5cc8..b8afc36b7c 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYKR920.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYKR920.cpp @@ -279,7 +279,7 @@ LoRaPHYKR920::LoRaPHYKR920(LoRaWANTimeHandler &lora_time) phy_params.payloads.table = (void *) max_payloads_KR920; phy_params.payloads.size = 6; phy_params.payloads_with_repeater.table = (void *) max_payloads_with_repeater_KR920; - phy_params.payloads.size = 6; + phy_params.payloads_with_repeater.size = 6; // dwell time setting phy_params.ul_dwell_time_setting = 0; diff --git a/features/lorawan/lorastack/phy/LoRaPHYUS915.cpp b/features/lorawan/lorastack/phy/LoRaPHYUS915.cpp index b89d3550eb..13a33a339b 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYUS915.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYUS915.cpp @@ -271,7 +271,7 @@ LoRaPHYUS915::LoRaPHYUS915(LoRaWANTimeHandler &lora_time) phy_params.payloads.table = (void *) max_payloads_US915; phy_params.payloads.size = 16; phy_params.payloads_with_repeater.table = (void *) max_payloads_with_repeater_US915; - phy_params.payloads.size = 16; + phy_params.payloads_with_repeater.size = 16; // dwell time setting phy_params.ul_dwell_time_setting = 0; diff --git a/features/lorawan/lorastack/phy/LoRaPHYUS915Hybrid.cpp b/features/lorawan/lorastack/phy/LoRaPHYUS915Hybrid.cpp index 9ab99e30fb..2e628908b6 100644 --- a/features/lorawan/lorastack/phy/LoRaPHYUS915Hybrid.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHYUS915Hybrid.cpp @@ -269,7 +269,7 @@ LoRaPHYUS915Hybrid::LoRaPHYUS915Hybrid(LoRaWANTimeHandler &lora_time) phy_params.payloads.table = (void *) max_payloads_US915_HYBRID; phy_params.payloads.size = 16; phy_params.payloads_with_repeater.table = (void *) max_payloads_with_repeater_US915_HYBRID; - phy_params.payloads.size = 16; + phy_params.payloads_with_repeater.size = 16; // dwell time setting phy_params.ul_dwell_time_setting = 0; From 92f4b989ced7dc7bab8436590ddb7608d6cdebae Mon Sep 17 00:00:00 2001 From: Kimmo Vaisanen Date: Thu, 8 Mar 2018 12:47:49 +0200 Subject: [PATCH 039/118] Fix verification of RX2 datarate Datarate verification passed only if given datarate was a minimum possible value. Instead datarate should be checked that it is less than maximum value. --- features/lorawan/lorastack/phy/LoRaPHY.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/features/lorawan/lorastack/phy/LoRaPHY.cpp b/features/lorawan/lorastack/phy/LoRaPHY.cpp index 47ba84f03d..b134da7045 100644 --- a/features/lorawan/lorastack/phy/LoRaPHY.cpp +++ b/features/lorawan/lorastack/phy/LoRaPHY.cpp @@ -657,11 +657,11 @@ bool LoRaPHY::verify(verification_params_t* verify, phy_attributes_t phy_attribu if (phy_params.dl_dwell_time_setting == 0) { return val_in_range(verify->datarate, phy_params.min_rx_datarate, - phy_params.min_rx_datarate); + phy_params.max_rx_datarate); } else { return val_in_range(verify->datarate, phy_params.dwell_limit_datarate, - phy_params.min_rx_datarate ); + phy_params.max_rx_datarate); } } case PHY_DEF_TX_POWER: From b2e31fb0d9dc4b977346c57425ed2683aac289a9 Mon Sep 17 00:00:00 2001 From: TomoYamanaka Date: Wed, 7 Mar 2018 14:27:19 +0900 Subject: [PATCH 040/118] Fix macro definition of iodefine_typedef for RZ_A1H Regarding RZ_A1H, Since I removed the macro definition accidentally in iodefine_typedef, I fixed the lack of it. --- .../TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h index 09ad7a584b..434b931933 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h @@ -54,7 +54,9 @@ typedef enum iodefine_byte_select_t { R_IO_L = 0, R_IO_H = 1, - R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3 + R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3, + L = 0, H = 1, + LL= 0, LH = 1, HL = 2, HH = 3 } iodefine_byte_select_t; From 2e9a0ebd25b3d06bd8fb042000f0ef2053de26c3 Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Mon, 5 Mar 2018 11:07:28 -0600 Subject: [PATCH 041/118] events: Added note about immediate firing of periodic events --- events/EventQueue.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/events/EventQueue.h b/events/EventQueue.h index 9b15edb6fa..4ec28203a1 100644 --- a/events/EventQueue.h +++ b/events/EventQueue.h @@ -701,6 +701,9 @@ public: } /** Calls an event on the queue periodically + * + * @note The first call_every event occurs after the specified delay. + * To create a periodic event that fires immediately, @see Event. * * The specified callback will be executed in the context of the event * queue's dispatch loop. From d6dcebeabad2ec0ec84eb4427a72ef5ca64aa2c0 Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Fri, 23 Feb 2018 11:59:14 -0600 Subject: [PATCH 042/118] Flash support: Add flash support for LPC54114 & LPC546XX Signed-off-by: Mahesh Mahadevan --- .../TARGET_LPC/flash_api.c | 129 ++++++++++++++++++ .../TARGET_LPC/objects.h | 6 + targets/targets.json | 4 +- 3 files changed, 137 insertions(+), 2 deletions(-) create mode 100644 targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/flash_api.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/flash_api.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/flash_api.c new file mode 100644 index 0000000000..0a3d35120e --- /dev/null +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/flash_api.c @@ -0,0 +1,129 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "flash_api.h" +#include "mbed_critical.h" + +#if DEVICE_FLASH + +#include "fsl_flashiap.h" + +int32_t flash_init(flash_t *obj) +{ + return 0; +} + +int32_t flash_free(flash_t *obj) +{ + return 0; +} + +int32_t flash_erase_sector(flash_t *obj, uint32_t address) +{ + uint32_t n; + uint32_t status; + int32_t ret = -1; + + /* We need to prevent flash accesses during erase operation */ + core_util_critical_section_enter(); + + n = address / FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES; // Get Sector Number + + status = FLASHIAP_PrepareSectorForWrite(n, n); + if (status == kStatus_FLASHIAP_Success) { + status = FLASHIAP_EraseSector(n, n, SystemCoreClock); + if (status == kStatus_FLASHIAP_Success) { + ret = 0; + } + } + + core_util_critical_section_exit(); + + return ret; +} + +int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) +{ + uint32_t n; + uint32_t sector_number; + + uint32_t status; + int32_t ret = -1; + uint8_t buf[FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES]; + + if (address == 0) { // Check for Vector Table + n = *((unsigned long *)(data + 0)) + + *((unsigned long *)(data + 1)) + + *((unsigned long *)(data + 2)) + + *((unsigned long *)(data + 3)) + + *((unsigned long *)(data + 4)) + + *((unsigned long *)(data + 5)) + + *((unsigned long *)(data + 6)); + *((unsigned long *)(data + 7)) = 0 - n; // Signature at Reserved Vector + } + + /* Copy into a local buffer to ensure address is word-aligned */ + memcpy(&buf, data, FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES); + + /* We need to prevent flash accesses during program operation */ + core_util_critical_section_enter(); + + sector_number = address / FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES; // Get Sector Number + + status = FLASHIAP_PrepareSectorForWrite(sector_number, sector_number); + if (status == kStatus_FLASHIAP_Success) { + status = FLASHIAP_CopyRamToFlash(address, (uint32_t *)&buf, + FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES, SystemCoreClock); + if (status == kStatus_FLASHIAP_Success) { + ret = 0; + } + } + + core_util_critical_section_exit(); + + return ret; +} + +uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) +{ + uint32_t sectorsize = MBED_FLASH_INVALID_SIZE; + uint32_t devicesize = FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES; + uint32_t startaddr = 0; + + if ((address >= startaddr) && (address < (startaddr + devicesize))) { + sectorsize = FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES; + } + + return sectorsize; +} + +uint32_t flash_get_page_size(const flash_t *obj) +{ + return FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES; +} + +uint32_t flash_get_start_address(const flash_t *obj) +{ + uint32_t startaddr = 0; + + return startaddr; +} + +uint32_t flash_get_size(const flash_t *obj) +{ + return FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES; +} + +#endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h index cf50e377dd..a7e19cf2d8 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h @@ -58,6 +58,12 @@ struct spi_s { uint8_t bits; }; +#if DEVICE_FLASH +struct flash_s { + uint8_t dummy; +}; +#endif + #include "gpio_object.h" #ifdef __cplusplus diff --git a/targets/targets.json b/targets/targets.json index 4aeb2bdadb..c67a0c338c 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -742,7 +742,7 @@ "macros": ["CPU_LPC54114J256BD64_cm4", "FSL_RTOS_MBED"], "inherits": ["Target"], "detect_code": ["1054"], - "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"], "release_versions": ["2", "5"], "device_name" : "LPC54114J256BD64" }, @@ -753,7 +753,7 @@ "is_disk_virtual": true, "macros": ["CPU_LPC54628J512ET180", "FSL_RTOS_MBED"], "inherits": ["Target"], - "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"], + "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"], "features": ["LWIP"], "device_name" : "LPC54628J512ET180" }, From f94dd8d2e7e051105c2eeea5718331c0e882623d Mon Sep 17 00:00:00 2001 From: Brendan McDonnell Date: Tue, 16 Jan 2018 16:08:14 -0500 Subject: [PATCH 043/118] typos --- TESTS/mbedmicro-mbed/static_assert/test_c.c | 2 +- .../mbedmicro-mbed/static_assert/test_cpp.cpp | 2 +- TESTS/netsocket/host_tests/udp_shotgun.py | 2 +- TESTS/netsocket/tcp_packet_pressure/main.cpp | 2 +- .../tcp_packet_pressure_parallel/main.cpp | 2 +- TESTS/netsocket/udp_packet_pressure/main.cpp | 2 +- .../udp_packet_pressure_parallel/main.cpp | 2 +- drivers/Ethernet.h | 10 +++--- drivers/I2C.cpp | 2 +- drivers/I2C.h | 4 +-- drivers/RawSerial.h | 2 +- drivers/SPI.cpp | 12 +++---- drivers/SPI.h | 6 ++-- drivers/SPISlave.h | 2 +- drivers/SerialBase.h | 8 ++--- events/Event.h | 12 +++---- events/EventQueue.h | 2 +- features/FEATURE_BLE/ble/BLEInstanceBase.h | 2 +- features/FEATURE_BLE/ble/pal/AttClient.h | 2 +- features/FEATURE_BLE/ble/pal/GapEvents.h | 2 +- .../ws-core/sw/wsf/include/wsf_buf.h | 2 +- .../TARGET_MCU_NRF51822/hal_patch/sleep.c | 2 +- .../sdk/source/ble/peer_manager/id_manager.c | 2 +- .../libraries/bootloader_dfu/dfu_types.h | 8 ++--- .../source/softdevice/s130/headers/ble_gap.h | 4 +-- .../softdevice/s130/headers/ble_gattc.h | 2 +- .../softdevice/s130/headers/ble_l2cap.h | 2 +- .../lwip-interface/EthernetInterface.h | 6 ++-- .../TARGET_LPCTarget/lpc17xx_emac.h | 12 +++---- .../lwip-interface/lwip/CHANGELOG | 2 +- .../lwip/src/apps/snmp/lwip_snmp_msg.c | 2 +- .../lwip/src/apps/tftp/lwip_tftp_server.c | 2 +- .../lwip/src/netif/ppp/lwip_ipcp.c | 2 +- .../lwip/src/netif/ppp/lwip_ipv6cp.c | 2 +- .../lwip/src/netif/ppp/lwip_lcp.c | 2 +- features/filesystem/bd/BlockDevice.h | 4 +-- features/filesystem/bd/ChainingBlockDevice.h | 4 +-- features/filesystem/bd/HeapBlockDevice.h | 4 +-- features/filesystem/bd/MBRBlockDevice.h | 4 +-- features/filesystem/bd/ProfilingBlockDevice.h | 4 +-- features/filesystem/bd/SlicingBlockDevice.h | 4 +-- features/filesystem/fat/ChaN/ff.cpp | 2 +- features/filesystem/littlefs/littlefs/lfs.h | 4 +-- features/lorawan/LoRaWANStack.cpp | 2 +- features/mbedtls/inc/mbedtls/bignum.h | 2 +- features/mbedtls/inc/mbedtls/x509.h | 6 ++-- features/mbedtls/src/ecp.c | 2 +- features/mbedtls/src/error.c | 2 +- features/mbedtls/targets/TARGET_STM/aes_alt.h | 2 +- .../nanostack-interface/NanostackInterface.h | 2 +- .../6LoWPAN/Thread/thread_dhcpv6_client.c | 2 +- .../6LoWPAN/Thread/thread_management_server.c | 8 ++--- features/netsocket/NetworkInterface.h | 6 ++-- features/netsocket/NetworkStack.h | 2 +- features/netsocket/Socket.h | 6 ++-- .../PPPCellularInterface.h | 6 ++-- features/netsocket/nsapi_types.h | 2 +- .../doc/design/configuration_store_hld.md | 4 +-- .../cfstore/source/configuration_store.c | 4 +-- .../unsupported/USBDevice/USBMSD/USBMSD.cpp | 4 +-- .../TARGET_Silicon_Labs/src/em_usbdep.c | 4 +-- .../tests/libs/SPIHalfDuplex/SPIHalfDuplex.h | 2 +- hal/ethernet_api.h | 2 +- hal/spi_api.h | 2 +- platform/ATCmdParser.cpp | 2 +- platform/Callback.h | 12 +++---- platform/NonCopyable.h | 22 ++++++------ platform/mbed_retarget.h | 4 +-- .../TARGET_CM3DS_MPS2/ethernet_api.c | 6 ++-- .../TARGET_IOTSS/SDK/ETH_MPS2.c | 2 +- .../TARGET_IOTSS/SDK/mps2_ethernet_api.h | 2 +- .../TARGET_IOTSS/ethernet_api.c | 6 ++-- .../TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c | 2 +- .../TARGET_MPS2/SDK/mps2_ethernet_api.h | 2 +- .../TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c | 6 ++-- .../TARGET_ADUCM3029/api/spi_api.c | 2 +- .../TARGET_ADUCM3029/bsp/tmr/adi_tmr.c | 2 +- .../TARGET_ADUCM3029/bsp/uart/adi_uart.c | 2 +- .../TARGET_ADUCM4050/api/spi_api.c | 2 +- .../TARGET_ADUCM4050/bsp/tmr/adi_tmr.c | 2 +- .../TARGET_ADUCM4050/bsp/uart/adi_uart.c | 2 +- .../TARGET_SAM_CortexM0P/drivers/tcc/tcc.c | 6 ++-- .../TARGET_SAM_CortexM0P/drivers/tcc/tcc.h | 2 +- .../TARGET_SAM_CortexM0P/serial_api.c | 2 +- .../include/component/comp_rstc.h | 2 +- .../TARGET_K66F/drivers/fsl_sai.c | 2 +- .../TARGET_K82F/drivers/fsl_qspi.c | 2 +- .../TARGET_K82F/drivers/fsl_sai.c | 2 +- .../TARGET_K82F/drivers/fsl_trng.c | 2 +- .../TARGET_KL43Z/drivers/fsl_sai.c | 2 +- .../TARGET_KL43Z/drivers/fsl_sai_dma.h | 2 +- .../TARGET_KL82Z/drivers/fsl_qspi.c | 2 +- .../TARGET_KL82Z/drivers/fsl_trng.c | 2 +- .../TARGET_KW24D/drivers/fsl_sai.c | 2 +- .../TARGET_KW41Z/drivers/fsl_trng.c | 2 +- .../TARGET_MCU_K22F/drivers/fsl_sai.c | 2 +- .../TARGET_MCU_K24F/drivers/fsl_sai.c | 2 +- .../TARGET_MCU_K64F/drivers/fsl_sai.c | 2 +- .../TARGET_MAX32625/mxc/tmr_utils.h | 2 +- .../TARGET_Maxim/TARGET_MAX32630/mxc/aes.h | 4 +-- .../TARGET_MAX32630/mxc/tmr_utils.h | 2 +- .../softdevice/s130/headers/nrf_ble_gattc.h | 2 +- .../softdevice/s130/headers/nrf_ble_l2cap.h | 2 +- .../softdevice/s132/headers/nrf_ble_gattc.h | 2 +- .../softdevice/s132/headers/nrf_ble_l2cap.h | 2 +- .../softdevice/s140/headers/nrf_ble_gattc.h | 2 +- .../softdevice/s140/headers/nrf_ble_l2cap.h | 2 +- .../ble/ble_error_log/ble_error_log.h | 6 ++-- .../ble/peer_manager/gattc_cache_manager.c | 2 +- .../ble/peer_manager/gatts_cache_manager.c | 2 +- .../ble/peer_manager/id_manager.c | 2 +- .../TARGET_SDK11/device/nrf52_bitfields.h | 4 +-- .../libraries/bootloader_dfu/dfu_types.h | 8 ++--- .../ble/ble_error_log/ble_error_log.h | 6 ++-- .../ble/peer_manager/gatts_cache_manager.c | 2 +- .../ble/peer_manager/id_manager.c | 2 +- .../TARGET_SDK13/device/nrf52840_bitfields.h | 4 +-- .../TARGET_SDK13/device/nrf52_bitfields.h | 4 +-- .../TARGET_NORDIC/TARGET_NRF5/serial_api.c | 20 +++++------ targets/TARGET_NORDIC/TARGET_NRF5/sleep.c | 2 +- .../TARGET_NUC472/device/NUC472_442.h | 2 +- targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c | 2 +- targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c | 2 +- .../TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c | 2 +- targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c | 2 +- .../TARGET_NXP/TARGET_LPC176X/ethernet_api.c | 30 ++++++++-------- targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c | 2 +- .../TARGET_LPC4088/ethernet_api.c | 36 +++++++++---------- .../TARGET_LPC408X/TARGET_LPC4088/i2c_api.c | 2 +- .../TARGET_LPC4088_DM/ethernet_api.c | 30 ++++++++-------- .../TARGET_LPC4088_DM/i2c_api.c | 2 +- .../TARGET_NXP/TARGET_LPC43XX/ethernet_api.c | 2 +- targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c | 2 +- targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c | 2 +- targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c | 2 +- .../TARGET_LPC546XX/drivers/fsl_mcan.h | 6 ++-- .../TARGET_LPC546XX/drivers/fsl_sdif.h | 4 +-- .../TARGET_MIMXRT1050/drivers/fsl_adc.h | 2 +- .../TARGET_MIMXRT1050/drivers/fsl_sai.c | 2 +- .../TARGET_MIMXRT1050/drivers/fsl_spdif.c | 2 +- .../TARGET_MIMXRT1050/drivers/fsl_trng.c | 2 +- .../TARGET_NCS36510/char_driver.h | 2 +- .../TARGET_NCS36510/ncs36510_i2c.c | 4 +-- .../TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c | 2 +- .../TARGET_AMEBA/RTWInterface.h | 6 ++-- .../drivers/wlan/realtek/src/osdep/wireless.h | 2 +- .../8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h | 2 +- .../device/stm32f0xx_hal_flash.c | 4 +-- .../TARGET_STM32F0/device/stm32f0xx_hal_i2s.c | 4 +-- .../TARGET_STM32F0/device/stm32f0xx_hal_tsc.c | 4 +-- .../device/system_clock.c | 2 +- .../TARGET_DISCO_F100RB/device/system_clock.c | 2 +- .../device/stm32f1xx_hal_flash.c | 4 +-- .../TARGET_STM32F1/device/stm32f1xx_hal_i2s.c | 2 +- .../TARGET_STM32F1/device/stm32f1xx_ll_i2c.h | 2 +- .../TARGET_STM32F2/device/stm32f2xx_ll_i2c.h | 2 +- .../device/stm32f3xx_hal_flash.c | 4 +-- .../device/stm32f3xx_hal_hrtim.c | 12 +++---- .../TARGET_STM32F3/device/stm32f3xx_hal_i2s.c | 4 +-- .../device/stm32f3xx_hal_i2s_ex.c | 8 ++--- .../device/stm32f3xx_hal_irda.c | 2 +- .../device/stm32f3xx_hal_uart.c | 4 +-- .../device/stm32f3xx_hal_usart.c | 2 +- .../device/system_clock.c | 2 +- .../device/system_clock.c | 2 +- .../device/system_clock.c | 2 +- .../TARGET_DISCO_F401VC/system_clock.c | 2 +- .../TARGET_ARCH_MAX/system_clock.c | 2 +- .../TARGET_STM32F407xG/device/stm32f407xx.h | 2 +- .../TARGET_ELMO_F411RE/system_clock.c | 2 +- .../TARGET_STM32F429xI/device/stm32f429xx.h | 2 +- .../TARGET_STM32F437xG/device/stm32f437xx.h | 2 +- .../ublox-odin-w2-drivers/OdinWiFiInterface.h | 4 +-- .../TARGET_STM32F439xI/device/stm32f439xx.h | 2 +- .../TARGET_B96B_F446VE/system_clock.c | 2 +- .../TARGET_STM32F469xI/device/stm32f469xx.h | 2 +- .../TARGET_STM32F4/device/stm32f4xx_hal_i2s.c | 2 +- .../device/stm32f4xx_hal_i2s_ex.c | 8 ++--- .../TARGET_STM32F4/device/stm32f4xx_hal_sai.c | 2 +- .../TARGET_STM32F4/device/stm32f4xx_ll_i2c.h | 2 +- .../device/stm32f4xx_ll_lptim.h | 2 +- .../TARGET_STM32F746xG/device/stm32f746xx.h | 2 +- .../TARGET_STM32F756xG/device/stm32f756xx.h | 2 +- .../TARGET_STM32F767xI/device/stm32f767xx.h | 2 +- .../TARGET_STM32F769xI/device/stm32f769xx.h | 2 +- .../device/stm32f7xx_hal_mdios.c | 4 +-- .../TARGET_STM32F7/device/stm32f7xx_hal_sai.c | 2 +- .../device/stm32f7xx_ll_lptim.h | 2 +- .../TARGET_STM32L0/device/stm32l0xx_hal_i2s.c | 4 +-- .../device/stm32l0xx_hal_irda.c | 8 ++--- .../device/stm32l0xx_hal_smartcard.c | 8 ++--- .../TARGET_STM32L0/device/stm32l0xx_hal_tsc.c | 4 +-- .../device/stm32l0xx_hal_uart.c | 12 +++---- .../device/stm32l0xx_hal_usart.c | 8 ++--- .../device/stm32l0xx_ll_lptim.h | 2 +- targets/TARGET_STM/TARGET_STM32L0/flash_api.c | 2 +- .../TARGET_MOTE_L152RC/device/system_clock.c | 2 +- .../TARGET_MTB_MTS_XDOT/device/system_clock.c | 2 +- .../TARGET_NZ32_SC151/device/system_clock.c | 2 +- .../TARGET_XDOT_L151CC/device/system_clock.c | 2 +- .../device/stm32l1xx_hal_flash_ex.c | 2 +- .../TARGET_STM32L1/device/stm32l1xx_hal_i2s.c | 6 ++-- .../TARGET_STM32L1/device/stm32l1xx_hal_sd.c | 2 +- .../TARGET_STM32L1/device/stm32l1xx_ll_i2c.h | 2 +- targets/TARGET_STM/TARGET_STM32L1/flash_api.c | 2 +- .../TARGET_STM32L4/device/stm32l4xx_hal_sai.c | 2 +- .../device/stm32l4xx_ll_lptim.h | 2 +- targets/TARGET_STM/TARGET_STM32L4/flash_api.c | 2 +- .../TARGET_EFM32/serial_api.c | 4 +-- .../Periph_Driver/inc/tmpm066_uart.h | 2 +- .../Periph_Driver/src/tmpm066_i2c.c | 4 +-- .../Periph_Driver/src/tmpm066_uart.c | 2 +- .../crash_log_parser/crash_log_parser.py | 2 +- 213 files changed, 401 insertions(+), 401 deletions(-) diff --git a/TESTS/mbedmicro-mbed/static_assert/test_c.c b/TESTS/mbedmicro-mbed/static_assert/test_c.c index 476c3b044f..e0f9923415 100644 --- a/TESTS/mbedmicro-mbed/static_assert/test_c.c +++ b/TESTS/mbedmicro-mbed/static_assert/test_c.c @@ -2,7 +2,7 @@ #define THE_ANSWER 42 // Tests for static asserts in different contexts -// multiple asserts are used to garuntee no conflicts occur in generated labels +// multiple asserts are used to guarantee no conflicts occur in generated labels // Test for static asserts in global context MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char), diff --git a/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp b/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp index 987c01ab9a..05741d3215 100644 --- a/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp +++ b/TESTS/mbedmicro-mbed/static_assert/test_cpp.cpp @@ -2,7 +2,7 @@ #define THE_ANSWER 42 // Tests for static asserts in different contexts -// multiple asserts are used to garuntee no conflicts occur in generated labels +// multiple asserts are used to guarantee no conflicts occur in generated labels // Test for static asserts in global context MBED_STATIC_ASSERT(sizeof(int) >= sizeof(char), diff --git a/TESTS/netsocket/host_tests/udp_shotgun.py b/TESTS/netsocket/host_tests/udp_shotgun.py index cdf18f963b..535fa10600 100644 --- a/TESTS/netsocket/host_tests/udp_shotgun.py +++ b/TESTS/netsocket/host_tests/udp_shotgun.py @@ -34,7 +34,7 @@ class UDPEchoClientHandler(BaseRequestHandler): data, sock = self.request pattern = [ord(d) << 4 for d in data] - # Each byte in request indicates size of packet to recieve + # Each byte in request indicates size of packet to receive # Each packet size is shifted over by 4 to fit in a byte, which # avoids any issues with endianess or decoding for packet in pattern: diff --git a/TESTS/netsocket/tcp_packet_pressure/main.cpp b/TESTS/netsocket/tcp_packet_pressure/main.cpp index e4fe0df937..d0ae9b9490 100644 --- a/TESTS/netsocket/tcp_packet_pressure/main.cpp +++ b/TESTS/netsocket/tcp_packet_pressure/main.cpp @@ -226,7 +226,7 @@ void test_tcp_packet_pressure() } } - // Verify recieved data + // Verify received data while (rx_count < size) { int rd = sock.recv(buffer, buffer_size); TEST_ASSERT(rd > 0 || rd == NSAPI_ERROR_WOULD_BLOCK); diff --git a/TESTS/netsocket/tcp_packet_pressure_parallel/main.cpp b/TESTS/netsocket/tcp_packet_pressure_parallel/main.cpp index bfd6ed0524..85f5cb2f27 100644 --- a/TESTS/netsocket/tcp_packet_pressure_parallel/main.cpp +++ b/TESTS/netsocket/tcp_packet_pressure_parallel/main.cpp @@ -232,7 +232,7 @@ public: } } - // Verify recieved data + // Verify received data while (rx_count < size) { int rd = sock.recv(buffer, buffer_size); TEST_ASSERT(rd > 0 || rd == NSAPI_ERROR_WOULD_BLOCK); diff --git a/TESTS/netsocket/udp_packet_pressure/main.cpp b/TESTS/netsocket/udp_packet_pressure/main.cpp index 9357092735..7b626476a1 100644 --- a/TESTS/netsocket/udp_packet_pressure/main.cpp +++ b/TESTS/netsocket/udp_packet_pressure/main.cpp @@ -222,7 +222,7 @@ void test_udp_packet_pressure() } } - // Prioritize recieving over sending packets to avoid flooding + // Prioritize receiving over sending packets to avoid flooding // the network while handling erronous packets while (rx_count < size) { int rd = sock.recvfrom(NULL, buffer, buffer_size); diff --git a/TESTS/netsocket/udp_packet_pressure_parallel/main.cpp b/TESTS/netsocket/udp_packet_pressure_parallel/main.cpp index 9a899bb293..c281cee42f 100644 --- a/TESTS/netsocket/udp_packet_pressure_parallel/main.cpp +++ b/TESTS/netsocket/udp_packet_pressure_parallel/main.cpp @@ -229,7 +229,7 @@ public: } } - // Prioritize recieving over sending packets to avoid flooding + // Prioritize receiving over sending packets to avoid flooding // the network while handling erronous packets while (rx_count < size) { int rd = sock.recvfrom(NULL, buffer, buffer_size); diff --git a/drivers/Ethernet.h b/drivers/Ethernet.h index ae4e999589..06aa99a76a 100644 --- a/drivers/Ethernet.h +++ b/drivers/Ethernet.h @@ -98,7 +98,7 @@ public: */ int send(); - /** Recevies an arrived ethernet packet. + /** Receives an arrived ethernet packet. * * Receiving an ethernet packet will drop the last received ethernet packet * and make a new ethernet packet ready to read. @@ -110,7 +110,7 @@ public: */ int receive(); - /** Read from an recevied ethernet packet. + /** Read from an received ethernet packet. * * After receive returned a number bigger than 0 it is * possible to read bytes from this packet. @@ -131,11 +131,11 @@ public: */ void address(char *mac); - /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up. + /** Returns if an ethernet link is present or not. It takes a while after Ethernet initialization to show up. * * @returns - * 0 if no ethernet link is pressent, - * 1 if an ethernet link is pressent. + * 0 if no ethernet link is present, + * 1 if an ethernet link is present. * * Example: * @code diff --git a/drivers/I2C.cpp b/drivers/I2C.cpp index 8be7a529fc..148d48ee38 100644 --- a/drivers/I2C.cpp +++ b/drivers/I2C.cpp @@ -81,7 +81,7 @@ int I2C::write(int data) { return ret; } -// read - Master Reciever Mode +// read - Master Receiver Mode int I2C::read(int address, char* data, int length, bool repeated) { lock(); aquire(); diff --git a/drivers/I2C.h b/drivers/I2C.h index 920a506eb7..a4b0598d29 100644 --- a/drivers/I2C.h +++ b/drivers/I2C.h @@ -159,9 +159,9 @@ public: /** Start non-blocking I2C transfer. * - * This function locks the deep sleep until any event has occured + * This function locks the deep sleep until any event has occurred * - * @param address 8/10 bit I2c slave address + * @param address 8/10 bit I2C slave address * @param tx_buffer The TX buffer with data to be transfered * @param tx_length The length of TX buffer in bytes * @param rx_buffer The RX buffer which is used for received data diff --git a/drivers/RawSerial.h b/drivers/RawSerial.h index b39fac73bf..1ede0c8a33 100644 --- a/drivers/RawSerial.h +++ b/drivers/RawSerial.h @@ -68,7 +68,7 @@ public: * * @param c The char to write * - * @returns The written char or -1 if an error occured + * @returns The written char or -1 if an error occurred */ int putc(int c); diff --git a/drivers/SPI.cpp b/drivers/SPI.cpp index 7bb94018d1..cdc1170228 100644 --- a/drivers/SPI.cpp +++ b/drivers/SPI.cpp @@ -49,8 +49,8 @@ void SPI::format(int bits, int mode) { lock(); _bits = bits; _mode = mode; - // If changing format while you are the owner than just - // update format, but if owner is changed than even frequency should be + // If changing format while you are the owner then just + // update format, but if owner is changed then even frequency should be // updated which is done by acquire. if (_owner == this) { spi_format(&_spi, _bits, _mode, 0); @@ -63,8 +63,8 @@ void SPI::format(int bits, int mode) { void SPI::frequency(int hz) { lock(); _hz = hz; - // If changing format while you are the owner than just - // update frequency, but if owner is changed than even frequency should be + // If changing format while you are the owner then just + // update frequency, but if owner is changed then even frequency should be // updated which is done by acquire. if (_owner == this) { spi_frequency(&_spi, _hz); @@ -77,7 +77,7 @@ void SPI::frequency(int hz) { SPI* SPI::_owner = NULL; SingletonPtr SPI::_mutex; -// ignore the fact there are multiple physical spis, and always update if it wasnt us last +// ignore the fact there are multiple physical spis, and always update if it wasn't us last void SPI::aquire() { lock(); if (_owner != this) { @@ -252,7 +252,7 @@ void SPI::irq_handler_asynch(void) } #if TRANSACTION_QUEUE_SIZE_SPI if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) { - // SPI peripheral is free (event happend), dequeue transaction + // SPI peripheral is free (event happened), dequeue transaction dequeue_transaction(); } #endif diff --git a/drivers/SPI.h b/drivers/SPI.h index af102dc07c..144191902c 100644 --- a/drivers/SPI.h +++ b/drivers/SPI.h @@ -79,7 +79,7 @@ public: /** Create a SPI master connected to the specified pins * - * mosi or miso can be specfied as NC if not used + * mosi or miso can be specified as NC if not used * * @param mosi SPI Master Out, Slave In pin * @param miso SPI Master In, Slave Out pin @@ -121,7 +121,7 @@ public: /** Write to the SPI Slave and obtain the response * - * The total number of bytes sent and recieved will be the maximum of + * The total number of bytes sent and received will be the maximum of * tx_length and rx_length. The bytes written will be padded with the * value 0xff. * @@ -156,7 +156,7 @@ public: /** Start non-blocking SPI transfer using 8bit buffers. * - * This function locks the deep sleep until any event has occured + * This function locks the deep sleep until any event has occurred * * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed, * the default SPI value is sent diff --git a/drivers/SPISlave.h b/drivers/SPISlave.h index c6226b2c3d..ec8456cb75 100644 --- a/drivers/SPISlave.h +++ b/drivers/SPISlave.h @@ -59,7 +59,7 @@ public: /** Create a SPI slave connected to the specified pins * - * mosi or miso can be specfied as NC if not used + * mosi or miso can be specified as NC if not used * * @param mosi SPI Master Out, Slave In pin * @param miso SPI Master In, Slave Out pin diff --git a/drivers/SerialBase.h b/drivers/SerialBase.h index faf29a0699..970cf4d19c 100644 --- a/drivers/SerialBase.h +++ b/drivers/SerialBase.h @@ -167,7 +167,7 @@ public: /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback * - * This function locks the deep sleep until any event has occured + * This function locks the deep sleep until any event has occurred * * @param buffer The buffer where received data will be stored * @param length The buffer length in bytes @@ -178,7 +178,7 @@ public: /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback * - * This function locks the deep sleep until any event has occured + * This function locks the deep sleep until any event has occurred * * @param buffer The buffer where received data will be stored * @param length The buffer length in bytes @@ -193,7 +193,7 @@ public: /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback. * - * This function locks the deep sleep until any event has occured + * This function locks the deep sleep until any event has occurred * * @param buffer The buffer where received data will be stored * @param length The buffer length in bytes @@ -205,7 +205,7 @@ public: /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback. * - * This function locks the deep sleep until any event has occured + * This function locks the deep sleep until any event has occurred * * @param buffer The buffer where received data will be stored * @param length The buffer length in bytes diff --git a/events/Event.h b/events/Event.h index 2e2d8f6906..a704409bf8 100644 --- a/events/Event.h +++ b/events/Event.h @@ -172,7 +172,7 @@ public: * The cancel function is irq safe. * * If called while the event queue's dispatch loop is active, the cancel - * function does not garuntee that the event will not execute after it + * function does not guarantee that the event will not execute after it * returns, as the event may have already begun executing. */ void cancel() const { @@ -590,7 +590,7 @@ public: * The cancel function is irq safe. * * If called while the event queue's dispatch loop is active, the cancel - * function does not garuntee that the event will not execute after it + * function does not guarantee that the event will not execute after it * returns, as the event may have already begun executing. */ void cancel() const { @@ -1008,7 +1008,7 @@ public: * The cancel function is irq safe. * * If called while the event queue's dispatch loop is active, the cancel - * function does not garuntee that the event will not execute after it + * function does not guarantee that the event will not execute after it * returns, as the event may have already begun executing. */ void cancel() const { @@ -1426,7 +1426,7 @@ public: * The cancel function is irq safe. * * If called while the event queue's dispatch loop is active, the cancel - * function does not garuntee that the event will not execute after it + * function does not guarantee that the event will not execute after it * returns, as the event may have already begun executing. */ void cancel() const { @@ -1844,7 +1844,7 @@ public: * The cancel function is irq safe. * * If called while the event queue's dispatch loop is active, the cancel - * function does not garuntee that the event will not execute after it + * function does not guarantee that the event will not execute after it * returns, as the event may have already begun executing. */ void cancel() const { @@ -2262,7 +2262,7 @@ public: * The cancel function is irq safe. * * If called while the event queue's dispatch loop is active, the cancel - * function does not garuntee that the event will not execute after it + * function does not guarantee that the event will not execute after it * returns, as the event may have already begun executing. */ void cancel() const { diff --git a/events/EventQueue.h b/events/EventQueue.h index 4ec28203a1..17ccfa4fa5 100644 --- a/events/EventQueue.h +++ b/events/EventQueue.h @@ -117,7 +117,7 @@ public: * The cancel function is irq safe. * * If called while the event queue's dispatch loop is active, the cancel - * function does not garuntee that the event will not execute after it + * function does not guarantee that the event will not execute after it * returns, as the event may have already begun executing. * * @param id Unique id of the event diff --git a/features/FEATURE_BLE/ble/BLEInstanceBase.h b/features/FEATURE_BLE/ble/BLEInstanceBase.h index d7ff34cb71..6f080c45d3 100644 --- a/features/FEATURE_BLE/ble/BLEInstanceBase.h +++ b/features/FEATURE_BLE/ble/BLEInstanceBase.h @@ -246,7 +246,7 @@ public: private: // this class is not a value type. - // prohibit copy construction and copy assignement + // prohibit copy construction and copy assignment BLEInstanceBase(const BLEInstanceBase&); BLEInstanceBase &operator=(const BLEInstanceBase&); }; diff --git a/features/FEATURE_BLE/ble/pal/AttClient.h b/features/FEATURE_BLE/ble/pal/AttClient.h index 56bd1a2f06..678f99562c 100644 --- a/features/FEATURE_BLE/ble/pal/AttClient.h +++ b/features/FEATURE_BLE/ble/pal/AttClient.h @@ -75,7 +75,7 @@ struct AttClient { * The mtu choosen for the connection is the minimum of the client Rx mtu * and server Rx mtu values. * - * If an error occured then the mtu used remains the default value. + * If an error occurred then the mtu used remains the default value. * * @param connection The handle of the connection to send this request to. * diff --git a/features/FEATURE_BLE/ble/pal/GapEvents.h b/features/FEATURE_BLE/ble/pal/GapEvents.h index a406d6cdcc..47cc2423dc 100644 --- a/features/FEATURE_BLE/ble/pal/GapEvents.h +++ b/features/FEATURE_BLE/ble/pal/GapEvents.h @@ -75,7 +75,7 @@ struct GapEvent { protected: GapEvent(GapEventType type) : type(type) { } - // Disable copy construction and copy assignement operations. + // Disable copy construction and copy assignment operations. GapEvent(const GapEvent&); GapEvent& operator=(const GapEvent&); }; diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/include/wsf_buf.h b/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/include/wsf_buf.h index e15476ed4b..6b27ca73b3 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/include/wsf_buf.h +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/include/wsf_buf.h @@ -63,7 +63,7 @@ typedef struct /*! WSF buffer diagnostics - buffer allocation failure */ typedef struct { - uint8_t taskId; /*! Task handler ID where failure occured */ + uint8_t taskId; /*! Task handler ID where failure occurred */ uint16_t len; /*! Length of buffer being allocated */ } wsfBufDiagAllocFail_t; diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c index aec280a0fb..b810e4effd 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c @@ -57,7 +57,7 @@ void hal_sleep(void) return; } else { // next event will wakeup the CPU - // If an interrupt occured between the test of SCB->ICSR and this + // If an interrupt occurred between the test of SCB->ICSR and this // instruction, WFE will just not put the CPU to sleep __WFE(); } diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/ble/peer_manager/id_manager.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/ble/peer_manager/id_manager.c index c2942c84cd..436fc783d1 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/ble/peer_manager/id_manager.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/ble/peer_manager/id_manager.c @@ -359,7 +359,7 @@ bool is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1, /**@brief Event handler for events from the peer_database module. * - * @param[in] p_event The event that has happend with peer id and flags. + * @param[in] p_event The event that has happened with peer id and flags. */ static void pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/libraries/bootloader_dfu/dfu_types.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/libraries/bootloader_dfu/dfu_types.h index d26b72f7b6..f8e8c40b6f 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/libraries/bootloader_dfu/dfu_types.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/libraries/bootloader_dfu/dfu_types.h @@ -152,10 +152,10 @@ typedef enum typedef struct { dfu_update_status_code_t status_code; /**< Device Firmware Update status. */ - uint16_t app_crc; /**< CRC of the recieved application. */ - uint32_t sd_size; /**< Size of the recieved SoftDevice. */ - uint32_t bl_size; /**< Size of the recieved BootLoader. */ - uint32_t app_size; /**< Size of the recieved Application. */ + uint16_t app_crc; /**< CRC of the received application. */ + uint32_t sd_size; /**< Size of the received SoftDevice. */ + uint32_t bl_size; /**< Size of the received BootLoader. */ + uint32_t app_size; /**< Size of the received Application. */ uint32_t sd_image_start; /**< Location in flash where the received SoftDevice image is stored. */ } dfu_update_status_t; diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gap.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gap.h index be91c1df8e..d5943b8ee5 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gap.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gap.h @@ -721,7 +721,7 @@ typedef struct /**@brief GAP event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occured. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ union /**< union alternative identified by evt_id in enclosing struct. */ { ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ @@ -1153,7 +1153,7 @@ SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::NRF_ERROR_TIMEOUT A SMP timout has occured, and further SMP operations on this link is prohibited. + * @retval ::NRF_ERROR_TIMEOUT A SMP timout has occurred, and further SMP operations on this link is prohibited. */ SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params)); diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gattc.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gattc.h index bb074ce5cb..994ea2035e 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gattc.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gattc.h @@ -239,7 +239,7 @@ typedef struct /**@brief GATTC event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occured. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ union diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_l2cap.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_l2cap.h index 6e37a39560..f8e1e9258d 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_l2cap.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_l2cap.h @@ -107,7 +107,7 @@ typedef struct /**@brief L2CAP event callback event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occured. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ union { ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ diff --git a/features/FEATURE_LWIP/lwip-interface/EthernetInterface.h b/features/FEATURE_LWIP/lwip-interface/EthernetInterface.h index 61fba64cd2..5ef6843adb 100644 --- a/features/FEATURE_LWIP/lwip-interface/EthernetInterface.h +++ b/features/FEATURE_LWIP/lwip-interface/EthernetInterface.h @@ -82,21 +82,21 @@ public: /** Get the local IP address * * @return Null-terminated representation of the local IP address - * or null if no IP address has been recieved + * or null if no IP address has been received */ virtual const char *get_ip_address(); /** Get the local network mask * * @return Null-terminated representation of the local network mask - * or null if no network mask has been recieved + * or null if no network mask has been received */ virtual const char *get_netmask(); /** Get the local gateways * * @return Null-terminated representation of the local gateway - * or null if no network mask has been recieved + * or null if no network mask has been received */ virtual const char *get_gateway(); diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17xx_emac.h b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17xx_emac.h index 9979a2560c..6e35c668a0 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17xx_emac.h +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17xx_emac.h @@ -249,7 +249,7 @@ extern "C" #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */ #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */ #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */ -#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */ +#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occurred */ #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */ #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */ #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */ @@ -373,7 +373,7 @@ extern "C" #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */ #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */ #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */ -#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ +#define EMAC_RINFO_ERR 0x80000000 /**< Error Occurred (OR of all errors) */ #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) @@ -395,10 +395,10 @@ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */ #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */ #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */ -#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */ +#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occurred */ #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */ #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */ -#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ +#define EMAC_TINFO_ERR 0x80000000 /**< Error Occurred (OR of all errors) */ #ifdef MCB_LPC_1768 /* DP83848C PHY definition ------------------------------------------------------------ */ @@ -417,7 +417,7 @@ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ -#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ +#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Ability */ #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ #define EMAC_PHY_REG_LPNPA 0x08 @@ -504,7 +504,7 @@ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ -#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ +#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Ability */ #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */ diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/CHANGELOG b/features/FEATURE_LWIP/lwip-interface/lwip/CHANGELOG index 1a5e27ba8b..bb10408c0f 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/CHANGELOG +++ b/features/FEATURE_LWIP/lwip-interface/lwip/CHANGELOG @@ -3918,7 +3918,7 @@ HISTORY ++ Bug fixes: * Fixed pool pbuf memory leak in pbuf_alloc(). - Occured if not enough PBUF_POOL pbufs for a packet pbuf chain. + Occurred if not enough PBUF_POOL pbufs for a packet pbuf chain. Reported by Savin Zlobec. * PBUF_POOL chains had their tot_len field not set for non-first diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/snmp/lwip_snmp_msg.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/snmp/lwip_snmp_msg.c index 0cb7ca997c..f95c3b38f8 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/snmp/lwip_snmp_msg.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/snmp/lwip_snmp_msg.c @@ -1469,7 +1469,7 @@ snmp_complete_outbound_frame(struct snmp_request *request) if (request->error_status == SNMP_ERR_TOOBIG) { request->error_index = 0; /* defined by RFC 1157 */ } else if (request->error_index == 0) { - /* set index to varbind where error occured (if not already set before, e.g. during GetBulk processing) */ + /* set index to varbind where error occurred (if not already set before, e.g. during GetBulk processing) */ request->error_index = request->inbound_varbind_enumerator.varbind_count; } } else { diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/tftp/lwip_tftp_server.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/tftp/lwip_tftp_server.c index 243b0924bd..a9d98b8cc1 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/tftp/lwip_tftp_server.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/tftp/lwip_tftp_server.c @@ -191,7 +191,7 @@ send_data(void) ret = tftp_state.ctx->read(tftp_state.handle, &payload[2], TFTP_MAX_PAYLOAD_SIZE); if (ret < 0) { - send_error(&tftp_state.addr, tftp_state.port, TFTP_ERROR_ACCESS_VIOLATION, "Error occured while reading the file."); + send_error(&tftp_state.addr, tftp_state.port, TFTP_ERROR_ACCESS_VIOLATION, "Error occurred while reading the file."); close_handle(); return; } diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipcp.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipcp.c index 05108a0628..cce0ae3d7d 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipcp.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipcp.c @@ -1744,7 +1744,7 @@ static int ipcp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree) { } endswitch: if (orc == CONFACK && /* Good CI */ - rc != CONFACK) /* but prior CI wasnt? */ + rc != CONFACK) /* but prior CI wasn't? */ continue; /* Don't send this one */ if (orc == CONFNAK) { /* Nak this CI? */ diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipv6cp.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipv6cp.c index f1592c6faf..f34375b498 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipv6cp.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipv6cp.c @@ -1011,7 +1011,7 @@ endswitch: IPV6CPDEBUG((" (%s)\n", CODENAME(orc))); if (orc == CONFACK && /* Good CI */ - rc != CONFACK) /* but prior CI wasnt? */ + rc != CONFACK) /* but prior CI wasn't? */ continue; /* Don't send this one */ if (orc == CONFNAK) { /* Nak this CI? */ diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_lcp.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_lcp.c index 90ed183b75..fe050b4bc1 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_lcp.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_lcp.c @@ -2232,7 +2232,7 @@ static int lcp_reqci(fsm *f, u_char *inp, int *lenp, int reject_if_disagree) { endswitch: if (orc == CONFACK && /* Good CI */ - rc != CONFACK) /* but prior CI wasnt? */ + rc != CONFACK) /* but prior CI wasn't? */ continue; /* Don't send this one */ if (orc == CONFNAK) { /* Nak this CI? */ diff --git a/features/filesystem/bd/BlockDevice.h b/features/filesystem/bd/BlockDevice.h index 81159b90ac..51118d7941 100644 --- a/features/filesystem/bd/BlockDevice.h +++ b/features/filesystem/bd/BlockDevice.h @@ -128,9 +128,9 @@ public: */ virtual bd_size_t get_read_size() const = 0; - /** Get the size of a programable block + /** Get the size of a programmable block * - * @return Size of a programable block in bytes + * @return Size of a programmable block in bytes * @note Must be a multiple of the read size */ virtual bd_size_t get_program_size() const = 0; diff --git a/features/filesystem/bd/ChainingBlockDevice.h b/features/filesystem/bd/ChainingBlockDevice.h index b6b7936591..c3b79e6b58 100644 --- a/features/filesystem/bd/ChainingBlockDevice.h +++ b/features/filesystem/bd/ChainingBlockDevice.h @@ -128,9 +128,9 @@ public: */ virtual bd_size_t get_read_size() const; - /** Get the size of a programable block + /** Get the size of a programmable block * - * @return Size of a programable block in bytes + * @return Size of a programmable block in bytes * @note Must be a multiple of the read size */ virtual bd_size_t get_program_size() const; diff --git a/features/filesystem/bd/HeapBlockDevice.h b/features/filesystem/bd/HeapBlockDevice.h index afdaeef744..8fc31cee46 100644 --- a/features/filesystem/bd/HeapBlockDevice.h +++ b/features/filesystem/bd/HeapBlockDevice.h @@ -118,9 +118,9 @@ public: */ virtual bd_size_t get_read_size() const; - /** Get the size of a programable block + /** Get the size of a programmable block * - * @return Size of a programable block in bytes + * @return Size of a programmable block in bytes */ virtual bd_size_t get_program_size() const; diff --git a/features/filesystem/bd/MBRBlockDevice.h b/features/filesystem/bd/MBRBlockDevice.h index c44e5f854a..bfb43d607c 100644 --- a/features/filesystem/bd/MBRBlockDevice.h +++ b/features/filesystem/bd/MBRBlockDevice.h @@ -187,9 +187,9 @@ public: */ virtual bd_size_t get_read_size() const; - /** Get the size of a programable block + /** Get the size of a programmable block * - * @return Size of a programable block in bytes + * @return Size of a programmable block in bytes * @note Must be a multiple of the read size */ virtual bd_size_t get_program_size() const; diff --git a/features/filesystem/bd/ProfilingBlockDevice.h b/features/filesystem/bd/ProfilingBlockDevice.h index bed93f14f9..d8196ea45b 100644 --- a/features/filesystem/bd/ProfilingBlockDevice.h +++ b/features/filesystem/bd/ProfilingBlockDevice.h @@ -114,9 +114,9 @@ public: */ virtual bd_size_t get_read_size() const; - /** Get the size of a programable block + /** Get the size of a programmable block * - * @return Size of a programable block in bytes + * @return Size of a programmable block in bytes * @note Must be a multiple of the read size */ virtual bd_size_t get_program_size() const; diff --git a/features/filesystem/bd/SlicingBlockDevice.h b/features/filesystem/bd/SlicingBlockDevice.h index 90482ed719..0278413389 100644 --- a/features/filesystem/bd/SlicingBlockDevice.h +++ b/features/filesystem/bd/SlicingBlockDevice.h @@ -120,9 +120,9 @@ public: */ virtual bd_size_t get_read_size() const; - /** Get the size of a programable block + /** Get the size of a programmable block * - * @return Size of a programable block in bytes + * @return Size of a programmable block in bytes * @note Must be a multiple of the read size */ virtual bd_size_t get_program_size() const; diff --git a/features/filesystem/fat/ChaN/ff.cpp b/features/filesystem/fat/ChaN/ff.cpp index cc04154a30..ea827af866 100644 --- a/features/filesystem/fat/ChaN/ff.cpp +++ b/features/filesystem/fat/ChaN/ff.cpp @@ -3299,7 +3299,7 @@ FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */ fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */ } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4); } - if (fmt == 4) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ + if (fmt == 4) return FR_DISK_ERR; /* An error occurred in the disk I/O layer */ if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ /* An FAT volume is found (bsect). Following code initializes the filesystem object */ diff --git a/features/filesystem/littlefs/littlefs/lfs.h b/features/filesystem/littlefs/littlefs/lfs.h index ad379852b7..f20a1d4f00 100644 --- a/features/filesystem/littlefs/littlefs/lfs.h +++ b/features/filesystem/littlefs/littlefs/lfs.h @@ -94,7 +94,7 @@ enum lfs_open_flags { LFS_F_DIRTY = 0x10000, // File does not match storage LFS_F_WRITING = 0x20000, // File has been written since last flush LFS_F_READING = 0x40000, // File has been read since last flush - LFS_F_ERRED = 0x80000, // An error occured during write + LFS_F_ERRED = 0x80000, // An error occurred during write }; // File seek flags @@ -465,7 +465,7 @@ int lfs_dir_rewind(lfs_t *lfs, lfs_dir_t *dir); // Returns a negative error code on failure. int lfs_traverse(lfs_t *lfs, int (*cb)(void*, lfs_block_t), void *data); -// Prunes any recoverable errors that may have occured in the filesystem +// Prunes any recoverable errors that may have occurred in the filesystem // // Not needed to be called by user unless an operation is interrupted // but the filesystem is still mounted. This is already called on first diff --git a/features/lorawan/LoRaWANStack.cpp b/features/lorawan/LoRaWANStack.cpp index 418322ed14..f2c4be02f7 100644 --- a/features/lorawan/LoRaWANStack.cpp +++ b/features/lorawan/LoRaWANStack.cpp @@ -860,7 +860,7 @@ void LoRaWANStack::mcps_confirm_handler(loramac_mcps_confirm_t *mcps_confirm) } if (mcps_confirm->status != LORAMAC_EVENT_INFO_STATUS_OK) { - // Couldn't schedule packet, ack not recieved in CONFIRMED case + // Couldn't schedule packet, ack not received in CONFIRMED case // or some other error happened. Discard buffer, unset the tx-ongoing // flag and let the application know _tx_msg.tx_ongoing = false; diff --git a/features/mbedtls/inc/mbedtls/bignum.h b/features/mbedtls/inc/mbedtls/bignum.h index 3bf02a7ee1..c5730db628 100644 --- a/features/mbedtls/inc/mbedtls/bignum.h +++ b/features/mbedtls/inc/mbedtls/bignum.h @@ -243,7 +243,7 @@ int mbedtls_mpi_copy( mbedtls_mpi *X, const mbedtls_mpi *Y ); void mbedtls_mpi_swap( mbedtls_mpi *X, mbedtls_mpi *Y ); /** - * \brief Safe conditional assignement X = Y if assign is 1 + * \brief Safe conditional assignment X = Y if assign is 1 * * \param X MPI to conditionally assign to * \param Y Value to be assigned diff --git a/features/mbedtls/inc/mbedtls/x509.h b/features/mbedtls/inc/mbedtls/x509.h index d6db9c6e37..2a3d7eca9a 100644 --- a/features/mbedtls/inc/mbedtls/x509.h +++ b/features/mbedtls/inc/mbedtls/x509.h @@ -77,7 +77,7 @@ #define MBEDTLS_ERR_X509_ALLOC_FAILED -0x2880 /**< Allocation of memory failed. */ #define MBEDTLS_ERR_X509_FILE_IO_ERROR -0x2900 /**< Read/write of file failed. */ #define MBEDTLS_ERR_X509_BUFFER_TOO_SMALL -0x2980 /**< Destination buffer is too small. */ -#define MBEDTLS_ERR_X509_FATAL_ERROR -0x3000 /**< A fatal error occured, eg the chain is too long or the vrfy callback failed. */ +#define MBEDTLS_ERR_X509_FATAL_ERROR -0x3000 /**< A fatal error occurred, eg the chain is too long or the vrfy callback failed. */ /* \} name */ /** @@ -250,7 +250,7 @@ int mbedtls_x509_serial_gets( char *buf, size_t size, const mbedtls_x509_buf *se * * \param to mbedtls_x509_time to check * - * \return 1 if the given time is in the past or an error occured, + * \return 1 if the given time is in the past or an error occurred, * 0 otherwise. */ int mbedtls_x509_time_is_past( const mbedtls_x509_time *to ); @@ -264,7 +264,7 @@ int mbedtls_x509_time_is_past( const mbedtls_x509_time *to ); * * \param from mbedtls_x509_time to check * - * \return 1 if the given time is in the future or an error occured, + * \return 1 if the given time is in the future or an error occurred, * 0 otherwise. */ int mbedtls_x509_time_is_future( const mbedtls_x509_time *from ); diff --git a/features/mbedtls/src/ecp.c b/features/mbedtls/src/ecp.c index b41baef27a..40e52591b9 100644 --- a/features/mbedtls/src/ecp.c +++ b/features/mbedtls/src/ecp.c @@ -1470,7 +1470,7 @@ cleanup: /* * For Montgomery curves, we do all the internal arithmetic in projective * coordinates. Import/export of points uses only the x coordinates, which is - * internaly represented as X / Z. + * internally represented as X / Z. * * For scalar multiplication, we'll use a Montgomery ladder. */ diff --git a/features/mbedtls/src/error.c b/features/mbedtls/src/error.c index 0292480aee..5a18477627 100644 --- a/features/mbedtls/src/error.c +++ b/features/mbedtls/src/error.c @@ -533,7 +533,7 @@ void mbedtls_strerror( int ret, char *buf, size_t buflen ) if( use_ret == -(MBEDTLS_ERR_X509_BUFFER_TOO_SMALL) ) mbedtls_snprintf( buf, buflen, "X509 - Destination buffer is too small" ); if( use_ret == -(MBEDTLS_ERR_X509_FATAL_ERROR) ) - mbedtls_snprintf( buf, buflen, "X509 - A fatal error occured, eg the chain is too long or the vrfy callback failed" ); + mbedtls_snprintf( buf, buflen, "X509 - A fatal error occurred, eg the chain is too long or the vrfy callback failed" ); #endif /* MBEDTLS_X509_USE_C || MBEDTLS_X509_CREATE_C */ // END generated code diff --git a/features/mbedtls/targets/TARGET_STM/aes_alt.h b/features/mbedtls/targets/TARGET_STM/aes_alt.h index 120c9af5f1..7eadcb1e6a 100644 --- a/features/mbedtls/targets/TARGET_STM/aes_alt.h +++ b/features/mbedtls/targets/TARGET_STM/aes_alt.h @@ -32,7 +32,7 @@ extern "C" { #endif #define ST_AES_TIMEOUT ((uint32_t) 0xFF) /* 255 ms timeout for the crypto processor */ -#define ST_ERR_AES_BUSY (-0x0023) /* Crypto processor is busy, timeout occured */ +#define ST_ERR_AES_BUSY (-0x0023) /* Crypto processor is busy, timeout occurred */ /** * \brief AES context structure * diff --git a/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.h b/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.h index 453efa14ae..8259984cab 100644 --- a/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.h +++ b/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.h @@ -68,7 +68,7 @@ protected: /** Bind a specific address to a socket * - * Binding a socket specifies the address and port on which to recieve + * Binding a socket specifies the address and port on which to receive * data. If the IP address is zeroed, only the port is bound. * * @param handle Socket handle diff --git a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_dhcpv6_client.c b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_dhcpv6_client.c index 7005b52336..dd83e45c50 100644 --- a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_dhcpv6_client.c +++ b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_dhcpv6_client.c @@ -60,7 +60,7 @@ void thread_dhcpv6_client_set_address(int8_t interface_id, dhcpv6_client_server_ void thread_dhcp_client_init(int8_t interface) { - // No support for multible thread instances yet. + // No support for multiple thread instances yet. dhcp_client.service_instance = dhcp_service_init(interface, DHCP_INSTANCE_CLIENT, NULL); dhcp_client.interface = interface; dhcp_client.libDhcp_instance = libdhcpv6_nonTemporal_entry_get_unique_instance_id(); diff --git a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_management_server.c b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_management_server.c index 329c26c14a..d98ab2f4a4 100644 --- a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_management_server.c +++ b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_management_server.c @@ -552,7 +552,7 @@ static uint32_t reverse_bits(uint32_t num) } static void thread_panid_scan_response(int8_t if_id, const mlme_scan_conf_t* conf) { - bool conflict_occured = false; + bool conflict_occurred = false; nwk_scan_params_t *scan_parameters_ptr; nwk_pan_descriptor_t *result; protocol_interface_info_entry_t *interface; @@ -599,12 +599,12 @@ static void thread_panid_scan_response(int8_t if_id, const mlme_scan_conf_t* con if(result->pan_descriptor->CoordPANId == this->scan_ptr->panid) { //if pan id matches then send a conflict message tr_debug("Same pan id was found on channel %d", result->pan_descriptor->LogicalChannel); set_channel_mask(this->scan_ptr->channel_mask,result->pan_descriptor->LogicalChannel,0); - conflict_occured = true; + conflict_occurred = true; } result = result->next; } while (result); - if (conflict_occured){ - tr_debug("conflict occured"); + if (conflict_occurred){ + tr_debug("conflict occurred"); this->scan_ptr->timer = eventOS_timeout_ms(thread_panid_conflict_timeout_cb, 2000, this); } thread_start_mac_with_link_configuration(interface,linkConfiguration); diff --git a/features/netsocket/NetworkInterface.h b/features/netsocket/NetworkInterface.h index 3d5d825370..486e2cf877 100644 --- a/features/netsocket/NetworkInterface.h +++ b/features/netsocket/NetworkInterface.h @@ -51,21 +51,21 @@ public: /** Get the local IP address * * @return Null-terminated representation of the local IP address - * or null if no IP address has been recieved + * or null if no IP address has been received */ virtual const char *get_ip_address(); /** Get the local network mask * * @return Null-terminated representation of the local network mask - * or null if no network mask has been recieved + * or null if no network mask has been received */ virtual const char *get_netmask(); /** Get the local gateway * * @return Null-terminated representation of the local gateway - * or null if no network mask has been recieved + * or null if no network mask has been received */ virtual const char *get_gateway(); diff --git a/features/netsocket/NetworkStack.h b/features/netsocket/NetworkStack.h index 27b9cc1f97..8688d0e833 100644 --- a/features/netsocket/NetworkStack.h +++ b/features/netsocket/NetworkStack.h @@ -130,7 +130,7 @@ protected: /** Bind a specific address to a socket * - * Binding a socket specifies the address and port on which to recieve + * Binding a socket specifies the address and port on which to receive * data. If the IP address is zeroed, only the port is bound. * * @param handle Socket handle diff --git a/features/netsocket/Socket.h b/features/netsocket/Socket.h index 4040abe5be..8c74a9e60c 100644 --- a/features/netsocket/Socket.h +++ b/features/netsocket/Socket.h @@ -78,7 +78,7 @@ public: /** Bind a specific address to a socket * - * Binding a socket specifies the address and port on which to recieve + * Binding a socket specifies the address and port on which to receive * data. * * @param port Local port to bind @@ -88,7 +88,7 @@ public: /** Bind a specific address to a socket * - * Binding a socket specifies the address and port on which to recieve + * Binding a socket specifies the address and port on which to receive * data. If the IP address is zeroed, only the port is bound. * * @param address Null-terminated local address to bind @@ -99,7 +99,7 @@ public: /** Bind a specific address to a socket * - * Binding a socket specifies the address and port on which to recieve + * Binding a socket specifies the address and port on which to receive * data. If the IP address is zeroed, only the port is bound. * * @param address Local address to bind diff --git a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h index 80cee234b3..a649c82f69 100644 --- a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h +++ b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h @@ -211,21 +211,21 @@ public: /** Get the local IP address * * @return Null-terminated representation of the local IP address - * or null if no IP address has been recieved + * or null if no IP address has been received */ virtual const char *get_ip_address(); /** Get the local network mask * * @return Null-terminated representation of the local network mask - * or null if no network mask has been recieved + * or null if no network mask has been received */ virtual const char *get_netmask(); /** Get the local gateways * * @return Null-terminated representation of the local gateway - * or null if no network mask has been recieved + * or null if no network mask has been received */ virtual const char *get_gateway(); diff --git a/features/netsocket/nsapi_types.h b/features/netsocket/nsapi_types.h index b6b789d04c..cbf2e3f075 100644 --- a/features/netsocket/nsapi_types.h +++ b/features/netsocket/nsapi_types.h @@ -403,7 +403,7 @@ typedef struct nsapi_stack_api /** Bind a specific address to a socket * - * Binding a socket specifies the address and port on which to recieve + * Binding a socket specifies the address and port on which to receive * data. If the IP address is zeroed, only the port is bound. * * @param stack Stack handle diff --git a/features/storage/FEATURE_STORAGE/cfstore/doc/design/configuration_store_hld.md b/features/storage/FEATURE_STORAGE/cfstore/doc/design/configuration_store_hld.md index 001cd8a1cb..5bb93bdbad 100644 --- a/features/storage/FEATURE_STORAGE/cfstore/doc/design/configuration_store_hld.md +++ b/features/storage/FEATURE_STORAGE/cfstore/doc/design/configuration_store_hld.md @@ -936,7 +936,7 @@ The following provides general notes on the handling of errors: - Supported backends may include non-volatile storage (flash) and SRAM. - For example. if a non-volatile storage (flash) backend is supported, then the flushing of data to the NV store must be atomic. This may require that flushing of data to flash is commited using an atomic write operation e.g. of a CRC32 value for the - commit data. If power loss occured during the atomic write then the CRC32 would be invalid, the previously written data would + commit data. If power loss occurred during the atomic write then the CRC32 would be invalid, the previously written data would not be valid, and the system would have to revert to a previous version of the data that has successfully commited the correct CRC32 value. @@ -1080,7 +1080,7 @@ split the writing of the value into M writes, where N/M is smaller than availabl In the case the the Write() call fails with return code `ARM_CFSTORE_DRIVER_ERROR_OUT_OF_MEMORY` then the client may retry the write transaction with a smaller length (less bytes). -Further, a client of the Write() function should alway check the returned value of the +Further, a client of the Write() function should always check the returned value of the len argment as this records the actual number of bytes written. CFSTORE may be able to write a number of bytes less that the total number in the data buffer supplied by the client. The unwritten bytes should be supplied to a second call to Write(). diff --git a/features/storage/FEATURE_STORAGE/cfstore/source/configuration_store.c b/features/storage/FEATURE_STORAGE/cfstore/source/configuration_store.c index a988de6ebc..3edc14c4be 100644 --- a/features/storage/FEATURE_STORAGE/cfstore/source/configuration_store.c +++ b/features/storage/FEATURE_STORAGE/cfstore/source/configuration_store.c @@ -1555,7 +1555,7 @@ static int32_t cfstore_flash_map_error(int32_t flash_journal_status_code) * In flash journal async mode, when: * - a FlashJournal_xxx() function has been invoked, and * - before the async completion has been received and processed - * the application context code should alway co-ordinate access to + * the application context code should always coordinate access to * context variables modified by interrupt and application context * by use of the critical_section_xxx. */ @@ -3497,7 +3497,7 @@ static int32_t cfstore_create(const char* key_name, ARM_CFSTORE_SIZE value_len, ret = cfstore_recreate(key_name, value_len, hkey, &hkvt); goto out1; } - /* not a valid hkvt implying the key_name wasnt found */ + /* not a valid hkvt implying the key_name wasn't found */ /* create new key */ ret = cfstore_validate_key_desc(kdesc); diff --git a/features/unsupported/USBDevice/USBMSD/USBMSD.cpp b/features/unsupported/USBDevice/USBMSD/USBMSD.cpp index 21d50f9b9f..a45c893c52 100644 --- a/features/unsupported/USBDevice/USBMSD/USBMSD.cpp +++ b/features/unsupported/USBDevice/USBMSD/USBMSD.cpp @@ -170,7 +170,7 @@ bool USBMSD::EPBULK_OUT_callback() { } break; - // an error has occured: stall endpoint and send CSW + // an error has occurred: stall endpoint and send CSW default: stallEndpoint(EPBULK_OUT); csw.Status = CSW_ERROR; @@ -207,7 +207,7 @@ bool USBMSD::EPBULK_IN_callback() { stage = READ_CBW; break; - // an error has occured + // an error has occurred default: stallEndpoint(EPBULK_IN); sendCSW(); diff --git a/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdep.c b/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdep.c index 2017edaf97..3846eb3d20 100644 --- a/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdep.c +++ b/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdep.c @@ -40,7 +40,7 @@ static const char *epStatusStr[] = { /* * USBDEP_Ep0Handler() is called each time a packet has been transmitted - * or recieved on the default endpoint. + * or received on the default endpoint. * A state machine navigate us through the phases of a control transfer * according to "chapter 9" in the USB spec. */ @@ -417,7 +417,7 @@ void USBDEP_Ep0Handler( USBD_Device_TypeDef *device ) /* * USBDEP_EpHandler() is called each time a packet has been transmitted - * or recieved on an endpoint other than the default endpoint. + * or received on an endpoint other than the default endpoint. */ void USBDEP_EpHandler( uint8_t epAddr ) { diff --git a/features/unsupported/tests/libs/SPIHalfDuplex/SPIHalfDuplex.h b/features/unsupported/tests/libs/SPIHalfDuplex/SPIHalfDuplex.h index 14633b8555..d012d7b946 100644 --- a/features/unsupported/tests/libs/SPIHalfDuplex/SPIHalfDuplex.h +++ b/features/unsupported/tests/libs/SPIHalfDuplex/SPIHalfDuplex.h @@ -48,7 +48,7 @@ public: * Pin Options: * (5, 6, 7) or (11, 12, 13) * - * mosi or miso can be specfied as NC if not used + * mosi or miso can be specified as NC if not used * * @param mosi SPI Master Out, Slave In pin * @param miso SPI Master In, Slave Out pin diff --git a/hal/ethernet_api.h b/hal/ethernet_api.h index 817f1f2f5b..1802db955e 100644 --- a/hal/ethernet_api.h +++ b/hal/ethernet_api.h @@ -40,7 +40,7 @@ int ethernet_write(const char *data, int size); // send ethernet write buffer, returning the packet size sent int ethernet_send(void); -// recieve from ethernet buffer, returning packet size, or 0 if no packet +// receive from ethernet buffer, returning packet size, or 0 if no packet int ethernet_receive(void); // read size bytes in to data, return actual num bytes read (0..size) diff --git a/hal/spi_api.h b/hal/spi_api.h index 7fbcf223e4..90117c822b 100644 --- a/hal/spi_api.h +++ b/hal/spi_api.h @@ -119,7 +119,7 @@ int spi_master_write(spi_t *obj, int value); /** Write a block out in master mode and receive a value * - * The total number of bytes sent and recieved will be the maximum of + * The total number of bytes sent and received will be the maximum of * tx_length and rx_length. The bytes written will be padded with the * value 0xff. * diff --git a/platform/ATCmdParser.cpp b/platform/ATCmdParser.cpp index 50478c2c49..30a4b8fa2b 100644 --- a/platform/ATCmdParser.cpp +++ b/platform/ATCmdParser.cpp @@ -158,7 +158,7 @@ int ATCmdParser::vscanf(const char *format, va_list args) if (j+1 >= _buffer_size - offset) { return false; } - // Recieve next character + // Receive next character int c = getc(); if (c < 0) { return -1; diff --git a/platform/Callback.h b/platform/Callback.h index b300afefad..b2f06e42fd 100644 --- a/platform/Callback.h +++ b/platform/Callback.h @@ -565,7 +565,7 @@ public: private: // Stored as pointer to function and pointer to optional object // Function pointer is stored as union of possible function types - // to garuntee proper size and alignment + // to guarantee proper size and alignment struct _class; union { void (*_staticfunc)(); @@ -1140,7 +1140,7 @@ public: private: // Stored as pointer to function and pointer to optional object // Function pointer is stored as union of possible function types - // to garuntee proper size and alignment + // to guarantee proper size and alignment struct _class; union { void (*_staticfunc)(A0); @@ -1716,7 +1716,7 @@ public: private: // Stored as pointer to function and pointer to optional object // Function pointer is stored as union of possible function types - // to garuntee proper size and alignment + // to guarantee proper size and alignment struct _class; union { void (*_staticfunc)(A0, A1); @@ -2293,7 +2293,7 @@ public: private: // Stored as pointer to function and pointer to optional object // Function pointer is stored as union of possible function types - // to garuntee proper size and alignment + // to guarantee proper size and alignment struct _class; union { void (*_staticfunc)(A0, A1, A2); @@ -2871,7 +2871,7 @@ public: private: // Stored as pointer to function and pointer to optional object // Function pointer is stored as union of possible function types - // to garuntee proper size and alignment + // to guarantee proper size and alignment struct _class; union { void (*_staticfunc)(A0, A1, A2, A3); @@ -3450,7 +3450,7 @@ public: private: // Stored as pointer to function and pointer to optional object // Function pointer is stored as union of possible function types - // to garuntee proper size and alignment + // to guarantee proper size and alignment struct _class; union { void (*_staticfunc)(A0, A1, A2, A3, A4); diff --git a/platform/NonCopyable.h b/platform/NonCopyable.h index 70444d1933..195a82cbd5 100644 --- a/platform/NonCopyable.h +++ b/platform/NonCopyable.h @@ -25,11 +25,11 @@ namespace mbed { /** * Inheriting from this class autogeneration of copy construction and copy - * assignement operations. + * assignment operations. * * Classes which are not value type should inherit privately from this class - * to avoid generation of invalid copy constructor or copy assignement operator - * which can lead to unoticeable programming errors. + * to avoid generation of invalid copy constructor or copy assignment operator + * which can lead to unnoticeable programming errors. * * As an example consider the following signature: * @@ -50,7 +50,7 @@ namespace mbed { * @endcode * * There is a bug in this function, it returns a temporary value which will be - * byte copied into foo then destroyed. Unfortunately, internaly the Foo class + * byte copied into foo then destroyed. Unfortunately, internally the Foo class * manage a pointer to a Resource object. This pointer will be released when the * temporary is destroyed and foo will manage a pointer to an already released * Resource. @@ -71,9 +71,9 @@ namespace mbed { * Foo* m = make_foo(); * @endcode * - * - Copy constructor and copy assignement operator has to be made private + * - Copy constructor and copy assignment operator has to be made private * in the Foo class. It prevents unwanted copy of Foo objects. This can be - * done by declaring copy constructor and copy assignement in the private + * done by declaring copy constructor and copy assignment in the private * section of the Foo class. * * @code @@ -92,7 +92,7 @@ namespace mbed { * * Another solution is to inherit privately from the NonCopyable class. * It reduces the boiler plate needed to avoid copy operations but more - * importantly it clarifies the programer intent and the object semantic. + * importantly it clarifies the programmer intent and the object semantic. * * class Foo : private NonCopyable { * public: @@ -121,7 +121,7 @@ namespace mbed { * }; * * // empty base optimization cannot be applied here because A from C and A from - * // B shall have a different address. In that case, with the alignement + * // B shall have a different address. In that case, with the alignment * // sizeof(C) == 2* sizeof(int) * @endcode * @@ -150,11 +150,11 @@ template class NonCopyable { protected: /** - * Disalow construction of NonCopyable objects from outside of its hierarchy. + * Disallow construction of NonCopyable objects from outside of its hierarchy. */ NonCopyable() { } /** - * Disalow destruction of NonCopyable objects from outside of its hierarchy. + * Disallow destruction of NonCopyable objects from outside of its hierarchy. */ ~NonCopyable() { } @@ -199,7 +199,7 @@ private: NonCopyable(const NonCopyable&); /** - * Declare copy assignement operator as private, any attempt to copy assign + * Declare copy assignment operator as private, any attempt to copy assign * a NonCopyable will fail at compile time. */ NonCopyable& operator=(const NonCopyable&); diff --git a/platform/mbed_retarget.h b/platform/mbed_retarget.h index e4837a7bfb..b3c6e6d502 100644 --- a/platform/mbed_retarget.h +++ b/platform/mbed_retarget.h @@ -422,7 +422,7 @@ typedef struct Dir DIR; #define S_IXUSR 0000100 ///< execute/search permission, owner #define S_IRWXG (S_IRGRP | S_IWGRP | S_IXGRP) #define S_IRGRP 0000040 ///< read permission, group -#define S_IWGRP 0000020 ///< write permission, grougroup +#define S_IWGRP 0000020 ///< write permission, group #define S_IXGRP 0000010 ///< execute/search permission, group #define S_IRWXO (S_IROTH | S_IWOTH | S_IXOTH) #define S_IROTH 0000004 ///< read permission, other @@ -461,7 +461,7 @@ struct statvfs { unsigned long f_namemax; ///< Maximum filename length }; -/* The following are dirent.h definitions are declared here to garuntee +/* The following are dirent.h definitions are declared here to guarantee * consistency where structure may be different with different toolchains */ struct dirent { diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c index d9755dfb33..2460a3741a 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c @@ -58,11 +58,11 @@ int ethernet_receive() return smsc9220_peek_next_packet_size(); } -/* Read from an recevied ethernet packet.*/ -/* After receive returnd a number bigger than 0 it is*/ +/* Read from an received ethernet packet.*/ +/* After receive returned a number bigger than 0 it is*/ /* possible to read bytes from this packet.*/ /* Read will write up to size bytes into data.*/ -/* It is possible to use read multible times.*/ +/* It is possible to use read multiple times.*/ /* Each time read will start reading after the last read byte before. */ int ethernet_read(char *data, int dlen) { diff --git a/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c b/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c index 2e20cb7113..036ee32578 100644 --- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c +++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c @@ -375,7 +375,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index) if(rxfifo_stat != 0) { // Fetch status of this packet pktsize = ((rxfifo_stat >> 16) & 0x3FFF); if(rxfifo_stat & (1 << 15)) { - printf("Error occured during receiving of packets on the bus.\n"); + printf("Error occurred during receiving of packets on the bus.\n"); return 1; } else { /* Below formula (recommended by SMSC9220 code) diff --git a/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h b/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h index 2a15b24a6c..913191435d 100644 --- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h +++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h @@ -30,7 +30,7 @@ extern "C" { // send ethernet write buffer, returning the packet size sent int ethernet_transmission(unsigned char * pkt, unsigned int length); -// recieve from ethernet buffer, returning packet size, or 0 if no packet +// receive from ethernet buffer, returning packet size, or 0 if no packet int ethernet_reception(unsigned int *recvbuf, unsigned int *index); // get the ethernet address diff --git a/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c b/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c index 78469a645f..360997c5dd 100644 --- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c @@ -136,11 +136,11 @@ int ethernet_receive() return 0; } -// Read from an recevied ethernet packet. -// After receive returnd a number bigger than 0 it is +// Read from an received ethernet packet. +// After receive returned a number bigger than 0 it is // possible to read bytes from this packet. // Read will write up to size bytes into data. -// It is possible to use read multible times. +// It is possible to use read multiple times. // Each time read will start reading after the last read byte before. int ethernet_read(char *data, int dlen) diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c b/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c index 3910871cd9..045cc07bc4 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c @@ -375,7 +375,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index) if(rxfifo_stat != 0) { // Fetch status of this packet pktsize = ((rxfifo_stat >> 16) & 0x3FFF); if(rxfifo_stat & (1 << 15)) { - printf("Error occured during receiving of packets on the bus.\n"); + printf("Error occurred during receiving of packets on the bus.\n"); return 1; } else { /* Below formula (recommended by SMSC9220 code) diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h b/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h index 2a15b24a6c..913191435d 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h @@ -30,7 +30,7 @@ extern "C" { // send ethernet write buffer, returning the packet size sent int ethernet_transmission(unsigned char * pkt, unsigned int length); -// recieve from ethernet buffer, returning packet size, or 0 if no packet +// receive from ethernet buffer, returning packet size, or 0 if no packet int ethernet_reception(unsigned int *recvbuf, unsigned int *index); // get the ethernet address diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c b/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c index 78469a645f..360997c5dd 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c @@ -136,11 +136,11 @@ int ethernet_receive() return 0; } -// Read from an recevied ethernet packet. -// After receive returnd a number bigger than 0 it is +// Read from an received ethernet packet. +// After receive returned a number bigger than 0 it is // possible to read bytes from this packet. // Read will write up to size bytes into data. -// It is possible to use read multible times. +// It is possible to use read multiple times. // Each time read will start reading after the last read byte before. int ethernet_read(char *data, int dlen) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c index dbecf7a149..17411e72f8 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c @@ -327,7 +327,7 @@ int spi_master_write(spi_t *obj, int value) /** Write a block out in master mode and receive a value * - * The total number of bytes sent and recieved will be the maximum of + * The total number of bytes sent and received will be the maximum of * tx_length and rx_length. The bytes written will be padded with the * value 0xff. * diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c index 9e889131ca..0882cbae8b 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c @@ -303,7 +303,7 @@ ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG* * * @details The timer can be configured to capture the timer value when a specific event occurs. The * list of events can be found in the hardware reference manual. The callback function specified - * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The + * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occurred. The * user can then read the captured value by calling #adi_tmr_GetCaptureCount. * * @note This function can only be called when the timer is disabled. diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c index f0dc346bfa..5c7a020447 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c @@ -1814,7 +1814,7 @@ ADI_UART_RESULT adi_uart_GetBaudRate( #endif /* ADI_DEBUG */ - /* If an error occured during autobaud this value will be set to a + /* If an error occurred during autobaud this value will be set to a non-zero value. The specific error can be found by checking against #ADI_UART_EVENT. */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c index 7f9fd048c5..74ef22135a 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c @@ -302,7 +302,7 @@ int spi_master_write(spi_t *obj, int value) /** Write a block out in master mode and receive a value * - * The total number of bytes sent and recieved will be the maximum of + * The total number of bytes sent and received will be the maximum of * tx_length and rx_length. The bytes written will be padded with the * value 0xff. * diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c index b7153b79a8..505daff976 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c @@ -284,7 +284,7 @@ ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG * * @details The timer can be configured to capture the timer value when a specific event occurs. The * list of events can be found in the hardware reference manual. The callback function specified - * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The + * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occurred. The * user can then read the captured value by calling #adi_tmr_GetCaptureCount. * * @note This function can only be called when the timer is disabled. diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c index d1f72d6048..a511985c6c 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c @@ -1808,7 +1808,7 @@ ADI_UART_RESULT adi_uart_GetBaudRate( #endif /* ADI_DEBUG */ - /* If an error occured during autobaud this value will be set to a + /* If an error occurred during autobaud this value will be set to a non-zero value. The specific error can be found by checking against #ADI_UART_EVENT. */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c index 68e9defcc3..1038c22038 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c @@ -1354,10 +1354,10 @@ enum status_code tcc_set_pattern( * * \return Bitmask of \c TCC_STATUS_* flags. * - * \retval TCC_STATUS_CHANNEL_MATCH_CAPTURE(n) Channel n match/capture has occured + * \retval TCC_STATUS_CHANNEL_MATCH_CAPTURE(n) Channel n match/capture has occurred * \retval TCC_STATUS_CHANNEL_OUTPUT(n) Channel n match/capture output state - * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) Non-recoverable fault x has occured - * \retval TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) Recoverable fault n has occured + * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) Non-recoverable fault x has occurred + * \retval TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) Recoverable fault n has occurred * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) Non-recoverable fault x input present * \retval TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n) Recoverable fault n input present * \retval TCC_STATUS_SYNC_READY None of register is syncing diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h index ec409a340d..7a53cc60a5 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h @@ -852,7 +852,7 @@ enum tcc_callback { #define TCC_STATUS_CHANNEL_OUTPUT(ch) (1UL << ((ch)+8)) /** A Non-Recoverable Fault \c x (0 ~ 1) has occurred. */ #define TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) (1UL << ((x)+16)) -/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) has occured. */ +/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) has occurred. */ #define TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) (1UL << ((n)+18)) /** The Non-Recoverable Fault \c x (0 ~ 1) input is present. */ #define TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) (1UL << ((x)+20)) diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c index 2ca86a6b63..8fed98d48d 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c @@ -1024,7 +1024,7 @@ int serial_rx_irq_handler_asynch(serial_t *obj) event |= SERIAL_EVENT_RX_CHARACTER_MATCH; } - /* Return to the call back if character match occured */ + /* Return to the call back if character match occurred */ if(event != 0) { serial_rx_abort_asynch(obj); return event & obj->serial.events; diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h index 987762aa64..f076cf2073 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h @@ -75,7 +75,7 @@ typedef struct { #define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ #define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ #define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ -#define RSTC_SR_RSTTYP_SLCK_XTAL_RST (0x7u << 8) /**< \brief (RSTC_SR) Slow Crystal Failure Detection fault occured */ +#define RSTC_SR_RSTTYP_SLCK_XTAL_RST (0x7u << 8) /**< \brief (RSTC_SR) Slow Crystal Failure Detection fault occurred */ #define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ #define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c index 73ea64fa4e..57b8dbb499 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ + kSAI_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c index 748a1e7167..db7a8e891a 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c @@ -37,7 +37,7 @@ enum _qspi_transfer_state { kQSPI_TxBusy = 0x0U, /*!< QSPI is busy */ kQSPI_TxIdle, /*!< Transfer is done. */ - kQSPI_TxError /*!< Transfer error occured. */ + kQSPI_TxError /*!< Transfer error occurred. */ }; #define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index)) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sai.c index 0d19d09e7a..97620fb6ad 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ + kSAI_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c index 959fb6050c..99f67b36a7 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c @@ -1173,7 +1173,7 @@ typedef enum _trng_statistical_check * TRNG access mode in the SA-TRNG Miscellaneous Control Register. * * Values: - * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous + * - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous * Control Register's access mode bit. * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * TRNG register programming. diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai.c index c38165ec04..9c8aab085d 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ + kSAI_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai_dma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai_dma.h index 9606afcfdf..d5f55559f0 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai_dma.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai_dma.h @@ -56,7 +56,7 @@ struct _sai_dma_handle uint8_t bytesPerFrame; /*!< Bytes in a frame */ uint8_t channel; /*!< Which Data channel SAI use */ uint32_t state; /*!< SAI DMA transfer internal state */ - sai_dma_callback_t callback; /*!< Callback for users while transfer finish or error occured */ + sai_dma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */ void *userData; /*!< User callback parameter */ sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c index 00f511cd73..2b23c1a11a 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c @@ -37,7 +37,7 @@ enum _qspi_transfer_state { kQSPI_TxBusy = 0x0U, /*!< QSPI is busy */ kQSPI_TxIdle, /*!< Transfer is done. */ - kQSPI_TxError /*!< Transfer error occured. */ + kQSPI_TxError /*!< Transfer error occurred. */ }; #define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index)) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_trng.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_trng.c index a5fd937dcd..d084fc1a58 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_trng.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_trng.c @@ -1173,7 +1173,7 @@ typedef enum _trng_statistical_check * TRNG access mode in the SA-TRNG Miscellaneous Control Register. * * Values: - * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous + * - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous * Control Register's access mode bit. * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * TRNG register programming. diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c index c38165ec04..9c8aab085d 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ + kSAI_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_trng.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_trng.c index a5fd937dcd..d084fc1a58 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_trng.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_trng.c @@ -1173,7 +1173,7 @@ typedef enum _trng_statistical_check * TRNG access mode in the SA-TRNG Miscellaneous Control Register. * * Values: - * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous + * - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous * Control Register's access mode bit. * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * TRNG register programming. diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_sai.c index c38165ec04..9c8aab085d 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ + kSAI_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c index 73ea64fa4e..57b8dbb499 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ + kSAI_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c index 0d19d09e7a..97620fb6ad 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ + kSAI_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/mxc/tmr_utils.h b/targets/TARGET_Maxim/TARGET_MAX32625/mxc/tmr_utils.h index a6712372ba..14f1aab224 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/mxc/tmr_utils.h +++ b/targets/TARGET_Maxim/TARGET_MAX32625/mxc/tmr_utils.h @@ -75,7 +75,7 @@ void TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us); void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us); /** - * @brief Check if the timeout has occured. + * @brief Check if the timeout has occurred. * @param tmr TMR module to operate on * @returns E_NO_ERROR if the timeout has not occurred, E_TIME_OUT if it has. */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h index 70e452d1ca..f81510af91 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h @@ -129,7 +129,7 @@ int AES_SetKey(const uint8_t *key, mxc_aes_mode_t mode); * @param dir Operation to perform, see #mxc_aes_dir_t for supported operations. * * @return #E_SUCCESS Operation completed successfully, output data is stored in @a *out. - * @return ErrorCode An @ref MXC_Error_Codes "Error Code" if an error occured. + * @return ErrorCode An @ref MXC_Error_Codes "Error Code" if an error occurred. */ int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_t dir); @@ -143,7 +143,7 @@ int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_ * @return #E_SUCCESS Output data was written to the location pointed * to by @a *out. * @return A @ref MXC_Error_Codes "Error Code" indicating the error that - * occured. + * occurred. */ int AES_GetOutput(uint8_t *out); diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h index c401ff04ed..19c92ae994 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h @@ -83,7 +83,7 @@ void TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us); void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us); /** - * @brief Check if the timeout has occured. + * @brief Check if the timeout has occurred. * @param tmr TMR module to operate on * @return #E_NO_ERROR if the timeout has not occurred, #E_TIME_OUT if it has. */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h index 5aa20fe430..634da43bcb 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h @@ -283,7 +283,7 @@ typedef struct /**@brief GATTC event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occured. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ union diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h index 57d3592969..e3fb2177cf 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h @@ -119,7 +119,7 @@ typedef struct /**@brief L2CAP event callback event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occured. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ union { ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h index 5aa20fe430..634da43bcb 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h @@ -283,7 +283,7 @@ typedef struct /**@brief GATTC event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occured. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ union diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h index 57d3592969..e3fb2177cf 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h @@ -119,7 +119,7 @@ typedef struct /**@brief L2CAP event callback event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occured. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ union { ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h index eb1f7753d7..62175952d5 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h @@ -301,7 +301,7 @@ typedef struct /**@brief GATTC event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occured. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ union diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h index d3cc747b10..bb980764d9 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h @@ -118,7 +118,7 @@ typedef struct /**@brief L2CAP event callback event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occured. */ + uint16_t conn_handle; /**< Connection Handle on which event occurred. */ union { ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h index ab121c2b3c..a685ad163e 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h @@ -62,7 +62,7 @@ /**@brief Error Log Data structure. * * @details The structure contains the error, message/filename, line number as well as the current - * stack, at the time where an error occured. + * stack, at the time where an error occurred. */ typedef struct { @@ -82,8 +82,8 @@ typedef struct * * @param[in] err_code Error code to be logged. * @param[in] p_message Message to be written to the flash together with stack dump, usually - * the file name where the error occured. - * @param[in] line_number Line number where the error occured. + * the file name where the error occurred. + * @param[in] line_number Line number where the error occurred. * * @return NRF_SUCCESS on successful writing of the error log. * diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c index e6b5469b41..d02d0a350f 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c @@ -67,7 +67,7 @@ static void internal_state_reset(gccm_t * gccm) /**@brief Event handler for events from the peer_database module. * - * @param[in] p_event The event that has happend with peer id and flags. + * @param[in] p_event The event that has happened with peer id and flags. */ static void pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c index 8cbca8e3f1..25e5e7f402 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c @@ -116,7 +116,7 @@ static void service_changed_pending_set(void) /**@brief Event handler for events from the peer_database module. * - * @param[in] p_event The event that has happend with peer id and flags. + * @param[in] p_event The event that has happened with peer id and flags. */ static void pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c index 94bc363ef6..38f20660a3 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c @@ -351,7 +351,7 @@ bool is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1, /**@brief Event handler for events from the peer_database module. * - * @param[in] p_event The event that has happend with peer id and flags. + * @param[in] p_event The event that has happened with peer id and flags. */ static void pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h index c7802c46a3..6c4287f595 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h @@ -13385,8 +13385,8 @@ /* Bit 0 : Overrun error */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ -#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occurred */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occurred */ /* Register: TWI_ENABLE */ /* Description: Enable TWI */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h index 7a7421d878..e78723e739 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h @@ -180,10 +180,10 @@ typedef enum typedef struct { dfu_update_status_code_t status_code; /**< Device Firmware Update status. */ - uint16_t app_crc; /**< CRC of the recieved application. */ - uint32_t sd_size; /**< Size of the recieved SoftDevice. */ - uint32_t bl_size; /**< Size of the recieved BootLoader. */ - uint32_t app_size; /**< Size of the recieved Application. */ + uint16_t app_crc; /**< CRC of the received application. */ + uint32_t sd_size; /**< Size of the received SoftDevice. */ + uint32_t bl_size; /**< Size of the received BootLoader. */ + uint32_t app_size; /**< Size of the received Application. */ uint32_t sd_image_start; /**< Location in flash where the received SoftDevice image is stored. */ } dfu_update_status_t; diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h index 9a7556f983..0b8e540d59 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h @@ -65,7 +65,7 @@ extern "C" { /**@brief Error Log Data structure. * * @details The structure contains the error, message/filename, line number as well as the current - * stack, at the time where an error occured. + * stack, at the time where an error occurred. */ typedef struct { @@ -85,8 +85,8 @@ typedef struct * * @param[in] err_code Error code to be logged. * @param[in] p_message Message to be written to the flash together with stack dump, usually - * the file name where the error occured. - * @param[in] line_number Line number where the error occured. + * the file name where the error occurred. + * @param[in] line_number Line number where the error occurred. * * @return NRF_SUCCESS on successful writing of the error log. * diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c index 3f4ac47060..3aba5f7a76 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c @@ -126,7 +126,7 @@ static void service_changed_pending_set(void) /**@brief Event handler for events from the Peer Database module. * This function is extern in Peer Database. * - * @param[in] p_event The event that has happend with peer id and flags. + * @param[in] p_event The event that has happened with peer id and flags. */ void gscm_pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c index 03cf432591..fa565c8520 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c @@ -365,7 +365,7 @@ bool im_is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1 /**@brief Event handler for events from the Peer Database module. * This function is extern in Peer Database. * - * @param[in] p_event The event that has happend with peer id and flags. + * @param[in] p_event The event that has happened with peer id and flags. */ void im_pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h index 3c71d50578..ac856b8628 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h @@ -11762,8 +11762,8 @@ /* Bit 0 : Overrun error */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ -#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occurred */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occurred */ /* Register: TWI_ENABLE */ /* Description: Enable TWI */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h index 9debbb6a26..c6fa759ecb 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h @@ -11114,8 +11114,8 @@ /* Bit 0 : Overrun error */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ -#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occurred */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occurred */ #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Register: TWI_ENABLE */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c index 0835c51765..38dea91aa1 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c @@ -112,7 +112,7 @@ typedef struct { void (*tx_asynch_handler)(); uint32_t events_wanted; - uint32_t events_occured; + uint32_t events_occurred; #define UART_IRQ_TX 1 #define UART_IRQ_RX 2 @@ -165,13 +165,13 @@ void UART_IRQ_HANDLER(void) if (UART_CB.char_match != SERIAL_RESERVED_CHAR_MATCH && rx_data == UART_CB.char_match) { // If it does, report the match and abort further receiving. - UART_CB.events_occured |= SERIAL_EVENT_RX_CHARACTER_MATCH; + UART_CB.events_occurred |= SERIAL_EVENT_RX_CHARACTER_MATCH; if (UART_CB.events_wanted & SERIAL_EVENT_RX_CHARACTER_MATCH) { end_rx = true; } } if (++UART_CB.rx_pos >= UART_CB.rx_length) { - UART_CB.events_occured |= SERIAL_EVENT_RX_COMPLETE; + UART_CB.events_occurred |= SERIAL_EVENT_RX_COMPLETE; end_rx = true; } if (end_rx) { @@ -215,7 +215,7 @@ void UART_IRQ_HANDLER(void) // 'serial_writable' function to work properly. end_asynch_tx(); - UART_CB.events_occured |= SERIAL_EVENT_TX_COMPLETE; + UART_CB.events_occurred |= SERIAL_EVENT_TX_COMPLETE; if (UART_CB.tx_asynch_handler) { // Use local variable to make it possible to start a next // transfer from callback routine. @@ -239,15 +239,15 @@ void UART_IRQ_HANDLER(void) uint8_t errorsrc = nrf_uart_errorsrc_get_and_clear(UART_INSTANCE); if (UART_CB.rx_asynch_handler) { - UART_CB.events_occured |= SERIAL_EVENT_ERROR; + UART_CB.events_occurred |= SERIAL_EVENT_ERROR; if (errorsrc & NRF_UART_ERROR_PARITY_MASK) { - UART_CB.events_occured |= SERIAL_EVENT_RX_PARITY_ERROR; + UART_CB.events_occurred |= SERIAL_EVENT_RX_PARITY_ERROR; } if (errorsrc & NRF_UART_ERROR_FRAMING_MASK) { - UART_CB.events_occured |= SERIAL_EVENT_RX_FRAMING_ERROR; + UART_CB.events_occurred |= SERIAL_EVENT_RX_FRAMING_ERROR; } if (errorsrc & NRF_UART_ERROR_OVERRUN_MASK) { - UART_CB.events_occured |= SERIAL_EVENT_RX_OVERRUN_ERROR; + UART_CB.events_occurred |= SERIAL_EVENT_RX_OVERRUN_ERROR; } UART_CB.rx_asynch_handler(); } @@ -641,8 +641,8 @@ uint8_t serial_rx_active(serial_t *obj) int serial_irq_handler_asynch(serial_t *obj) { (void)obj; - uint32_t events_to_report = UART_CB.events_wanted & UART_CB.events_occured; - UART_CB.events_occured &= (~events_to_report); + uint32_t events_to_report = UART_CB.events_wanted & UART_CB.events_occurred; + UART_CB.events_occurred &= (~events_to_report); return events_to_report; } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c b/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c index f806e7a0a6..7bb2d85f4c 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c @@ -66,7 +66,7 @@ void hal_sleep(void) return; } else { // next event will wakeup the CPU - // If an interrupt occured between the test of SCB->ICSR and this + // If an interrupt occurred between the test of SCB->ICSR and this // instruction, WFE will just not put the CPU to sleep __WFE(); } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h index 00af9638de..5ae86a9c14 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h @@ -20502,7 +20502,7 @@ typedef struct { * | | |Note: This bit is only cleared by writing 1 to it. * |[2] |OVUNF |QEI Counter Overflow Or Underflow Flag * | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_MAXCNT value to zero in compare-counting mode. - * | | |Similarly, the flag is set wile QEI counter underflows from zero to 0xFFFF_FFFF or QEI_MAXCNT. + * | | |Similarly, the flag is set while QEI counter underflows from zero to 0xFFFF_FFFF or QEI_MAXCNT. * | | |0 = No overflow or underflow occurs in QEI counter. * | | |1 = QEI counter occurs counting overflow or underflow. * | | |Note: This bit is only cleared by writing 1 to it. diff --git a/targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c index 84eeed8f93..f0e53c483e 100644 --- a/targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c @@ -204,7 +204,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically +// because something is setup wrong (e.g. wiring), and we don't need to programmatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c index 4c5202d6bc..5bfd6433e1 100644 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c @@ -187,7 +187,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically +// because something is setup wrong (e.g. wiring), and we don't need to programmatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c index 52f6f4486e..21976fb217 100644 --- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c @@ -197,7 +197,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically +// because something is setup wrong (e.g. wiring), and we don't need to programmatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c index 415ef071af..97fbb29018 100644 --- a/targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c @@ -197,7 +197,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically +// because something is setup wrong (e.g. wiring), and we don't need to programmatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c index 0b4b7a8312..d98ca77a69 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c +++ b/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c @@ -172,7 +172,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occurred */ #define TSV0_GIANT 0x00000400 /* Giant Frame */ #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ @@ -268,7 +268,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ +#define RINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ @@ -289,10 +289,10 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occurred */ #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ +#define TINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ /* ENET Device Revision ID */ #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ @@ -303,7 +303,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ @@ -540,8 +540,8 @@ void ethernet_free() { // if(TxProduceIndex == TxConsumeIndex) buffer array is empty // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill -// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment -// TxConsumeIndex - The buffer that will/is beign sent by hardware +// TxProduceIndex - The buffer that will be / is being fileld by driver, s/w increment +// TxConsumeIndex - The buffer that will be / is being sent by hardware int ethernet_write(const char *data, int slen) { @@ -651,22 +651,22 @@ int ethernet_send() { #endif } -// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read -// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd +// RxConsmeIndex - The index of buffer the driver will read / is reading from. Driver should inc once read +// RxProduceIndex - The index of buffer that will be / is being filled by MAC. H/w will inc once rxd // // if(RxConsumeIndex == RxProduceIndex) buffer array is empty // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full -// Recevies an arrived ethernet packet. +// Receives an arrived ethernet packet. // Receiving an ethernet packet will drop the last received ethernet packet // and make a new ethernet packet ready to read. // Returns size of packet, else 0 if nothing to receive // We read from RxConsumeIndex from position rx_consume_offset -// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading +// if rx_consume_offset < 0, then we have not received the RxConsumeIndex packet for reading // rx_consume_offset = -1 // no frame // rx_consume_offset = 0 // start of frame -// Assumption: A fragment should alway be a whole frame +// Assumption: A fragment should always be a whole frame int ethernet_receive() { #if NEW_LOGIC @@ -722,11 +722,11 @@ int ethernet_receive() { #endif } -// Read from an recevied ethernet packet. -// After receive returnd a number bigger than 0 it is +// Read from an received ethernet packet. +// After receive returned a number bigger than 0 it is // possible to read bytes from this packet. // Read will write up to size bytes into data. -// It is possible to use read multible times. +// It is possible to use read multiple times. // Each time read will start reading after the last read byte before. int ethernet_read(char *data, int dlen) { diff --git a/targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c index fb2ed1656a..fde4e8e746 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c @@ -204,7 +204,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically +// because something is setup wrong (e.g. wiring), and we don't need to programmatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c index 7ea6885fbf..3583096b06 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c @@ -100,7 +100,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ -#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Pressure / No Backoff */ #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ /* Back-to-Back Inter-Packet-Gap Register */ @@ -166,19 +166,19 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TSV0_CRC_ERR 0x00000001 /* CRC error */ #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ -#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_DONE 0x00000008 /* Transmission Completed */ #define TSV0_MCAST 0x00000010 /* Multicast Destination */ #define TSV0_BCAST 0x00000020 /* Broadcast Destination */ #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occurred */ #define TSV0_GIANT 0x00000400 /* Giant Frame */ #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ #define TSV0_PAUSE 0x20000000 /* Pause Frame */ -#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_BACK_PRESS 0x40000000 /* Back pressure Method Applied */ #define TSV0_VLAN 0x80000000 /* VLAN Frame */ /* Transmit Status Vector 1 Register */ @@ -268,7 +268,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ +#define RINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ @@ -289,10 +289,10 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occurred */ #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ +#define TINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ /* ENET Device Revision ID */ #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ @@ -303,7 +303,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ @@ -565,8 +565,8 @@ void ethernet_free() { // if(TxProduceIndex == TxConsumeIndex) buffer array is empty // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill -// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment -// TxConsumeIndex - The buffer that will/is beign sent by hardware +// TxProduceIndex - The buffer that will be / is being filled by driver, s/w increment +// TxConsumeIndex - The buffer that will be / is being sent by hardware int ethernet_write(const char *data, int slen) { @@ -676,22 +676,22 @@ int ethernet_send() { #endif } -// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read -// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd +// RxConsmeIndex - The index of buffer the driver will read / is reading from. Driver should inc once read +// RxProduceIndex - The index of buffer that will be / is being filled by MAC. H/w will inc once rxd // // if(RxConsumeIndex == RxProduceIndex) buffer array is empty // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full -// Recevies an arrived ethernet packet. +// Receives an arrived ethernet packet. // Receiving an ethernet packet will drop the last received ethernet packet // and make a new ethernet packet ready to read. // Returns size of packet, else 0 if nothing to receive // We read from RxConsumeIndex from position rx_consume_offset -// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading +// if rx_consume_offset < 0, then we have not received the RxConsumeIndex packet for reading // rx_consume_offset = -1 // no frame // rx_consume_offset = 0 // start of frame -// Assumption: A fragment should alway be a whole frame +// Assumption: A fragment should always be a whole frame int ethernet_receive() { #if NEW_LOGIC @@ -747,11 +747,11 @@ int ethernet_receive() { #endif } -// Read from an recevied ethernet packet. -// After receive returnd a number bigger than 0 it is +// Read from an received ethernet packet. +// After receive returned a number bigger than 0 it is // possible to read bytes from this packet. // Read will write up to size bytes into data. -// It is possible to use read multible times. +// It is possible to use read multiple times. // Each time read will start reading after the last read byte before. int ethernet_read(char *data, int dlen) { diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c index 730e51eb49..8a1cd29e8d 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c @@ -224,7 +224,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically +// because something is setup wrong (e.g. wiring), and we don't need to programmatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int count, status; diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c index 67d344aa4e..6477094954 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c @@ -172,7 +172,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occurred */ #define TSV0_GIANT 0x00000400 /* Giant Frame */ #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ @@ -268,7 +268,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ +#define RINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ @@ -289,10 +289,10 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occurred */ #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ +#define TINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ /* ENET Device Revision ID */ #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ @@ -303,7 +303,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ @@ -565,8 +565,8 @@ void ethernet_free() { // if(TxProduceIndex == TxConsumeIndex) buffer array is empty // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill -// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment -// TxConsumeIndex - The buffer that will/is beign sent by hardware +// TxProduceIndex - The buffer that will be / is being fileld by driver, s/w increment +// TxConsumeIndex - The buffer that will be / is being sent by hardware int ethernet_write(const char *data, int slen) { @@ -676,22 +676,22 @@ int ethernet_send() { #endif } -// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read -// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd +// RxConsmeIndex - The index of buffer the driver will read / is reading from. Driver should inc once read +// RxProduceIndex - The index of buffer that will be / is being filled by MAC. H/w will inc once rxd // // if(RxConsumeIndex == RxProduceIndex) buffer array is empty // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full -// Recevies an arrived ethernet packet. +// Receives an arrived ethernet packet. // Receiving an ethernet packet will drop the last received ethernet packet // and make a new ethernet packet ready to read. // Returns size of packet, else 0 if nothing to receive // We read from RxConsumeIndex from position rx_consume_offset -// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading +// if rx_consume_offset < 0, then we have not received the RxConsumeIndex packet for reading // rx_consume_offset = -1 // no frame // rx_consume_offset = 0 // start of frame -// Assumption: A fragment should alway be a whole frame +// Assumption: A fragment should always be a whole frame int ethernet_receive() { #if NEW_LOGIC @@ -747,11 +747,11 @@ int ethernet_receive() { #endif } -// Read from an recevied ethernet packet. -// After receive returnd a number bigger than 0 it is +// Read from an received ethernet packet. +// After receive returned a number bigger than 0 it is // possible to read bytes from this packet. // Read will write up to size bytes into data. -// It is possible to use read multible times. +// It is possible to use read multiple times. // Each time read will start reading after the last read byte before. int ethernet_read(char *data, int dlen) { diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c index 64ebe3cc1c..5093dfc6ea 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c @@ -210,7 +210,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically +// because something is setup wrong (e.g. wiring), and we don't need to programmatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int count, status; diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c index b947155941..6845904c69 100644 --- a/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c +++ b/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c @@ -148,7 +148,7 @@ typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c index 0e26102c91..fe1791fbc4 100644 --- a/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c @@ -205,7 +205,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically +// because something is setup wrong (e.g. wiring), and we don't need to programmatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c index 916242f3bd..df5979754a 100644 --- a/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c @@ -151,7 +151,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically +// because something is setup wrong (e.g. wiring), and we don't need to programmatically // check for that //New version WH, Tested OK for Start and Repeated Start diff --git a/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c index 91044d4ab3..a8d662da33 100644 --- a/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c @@ -242,7 +242,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically +// because something is setup wrong (e.g. wiring), and we don't need to programmatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int count, status; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h index 07c17b8d98..36f33a526a 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h @@ -548,7 +548,7 @@ void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config * @brief Configures an MCAN receive fifo 0 buffer. * * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 0. + * and datafield size of the receive fifo 0. * * @param base MCAN peripheral base address. * @param config The receive fifo 0 configuration structure. @@ -559,7 +559,7 @@ void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); * @brief Configures an MCAN receive fifo 1 buffer. * * This function sets start address, element size, watermark, operation mode - * and datafield size of the recieve fifo 1. + * and datafield size of the receive fifo 1. * * @param base MCAN peripheral base address. * @param config The receive fifo 1 configuration structure. @@ -569,7 +569,7 @@ void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); /*! * @brief Configures an MCAN receive buffer. * - * This function sets start address and datafield size of the recieve buffer. + * This function sets start address and datafield size of the receive buffer. * * @param base MCAN peripheral base address. * @param config The receive buffer configuration structure. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h index e2602c6211..ece101ad2e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h @@ -317,7 +317,7 @@ typedef struct _sdif_data size_t blockSize; /*!< Block size, take care when config this parameter */ uint32_t blockCount; /*!< Block count */ - uint32_t *rxData; /*!< data buffer to recieve */ + uint32_t *rxData; /*!< data buffer to receive */ const uint32_t *txData; /*!< data buffer to transfer */ } sdif_data_t; @@ -335,7 +335,7 @@ typedef struct _sdif_command uint32_t responseType; /*!< Command response type */ uint32_t flags; /*!< Cmd flags */ uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when - recieve the cmd response */ + receive the cmd response */ } sdif_command_t; /*! @brief Transfer state */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h index e5b6b8c16f..2f1871ba7d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h @@ -52,7 +52,7 @@ typedef enum _adc_status_flags kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */ kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */ kADC_AsynchronousWakeupInterruptFlag = - ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */ + ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occurred, support w1c. */ } adc_status_flags_t; /*! diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c index 31fd061e4c..6e6a5e30ce 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occured. */ + kSAI_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c index b0e70c0358..31f7691b72 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c @@ -37,7 +37,7 @@ enum _spdif_transfer_state { kSPDIF_Busy = 0x0U, /*!< SPDIF is busy */ kSPDIF_Idle, /*!< Transfer is done. */ - kSPDIF_Error /*!< Transfer error occured. */ + kSPDIF_Error /*!< Transfer error occurred. */ }; /*! @brief Typedef for spdif tx interrupt handler. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c index 0aafb78d8e..46190dc159 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c @@ -1176,7 +1176,7 @@ typedef enum _trng_statistical_check * TRNG access mode in the SA-TRNG Miscellaneous Control Register. * * Values: - * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous + * - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous * Control Register's access mode bit. * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * TRNG register programming. diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h index 0f6ab4489d..61a08ec6f3 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h @@ -26,7 +26,7 @@ * * @details * The character driver is intended for devices that allow read and write - * operations with "streams" of data, such as UART devices, SPI or I2c, etc. + * operations with "streams" of data, such as UART devices, SPI or I2C, etc. * * The character driver derives from the generic driver template (see driver.h). * It does so by including an element of the generic driver_t type. diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c index 8ae4a9b935..593ddf48a7 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c @@ -145,7 +145,7 @@ int32_t fI2cStop(i2c_t *obj) if (obj->membase->STATUS.WORD & (I2C_STATUS_CMD_FIFO_FULL_BIT | I2C_STATUS_CMD_FIFO_OFL_BIT | I2C_STATUS_BUS_ERR_BIT)) { - /* I2c error occured */ + /* I2C error occurred */ return I2C_ERROR_BUS_BUSY; } return I2C_API_STATUS_SUCCESS; @@ -164,7 +164,7 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len) SEND_COMMAND(I2C_CMD_RDAT8); while(!RD_DATA_READY) { if (I2C_BUS_ERR_CHECK) { - /* Bus error occured */ + /* Bus error occurred */ return I2C_ERROR_BUS_BUSY; } } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c index 227ac68f4e..ac37ba5cb5 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c @@ -442,7 +442,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } - /* Recieve the data */ + /* Receive the data */ if (count == (length - 2)) { value = i2c_do_read(obj, 1); } else if ((length >= 3) && (count == (length - 3))) { diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h index f221efc744..8b25da958a 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h @@ -125,21 +125,21 @@ public: /** Get the local IP address * * @return Null-terminated representation of the local IP address - * or null if no IP address has been recieved + * or null if no IP address has been received */ virtual const char *get_ip_address(); /** Get the local network mask * * @return Null-terminated representation of the local network mask - * or null if no network mask has been recieved + * or null if no network mask has been received */ virtual const char *get_netmask(); /** Get the local gateways * * @return Null-terminated representation of the local gateway - * or null if no network mask has been recieved + * or null if no network mask has been received */ virtual const char *get_gateway(); diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h index ac988590c4..660258bd4d 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h @@ -145,7 +145,7 @@ * * V11 to V12 * ---------- - * - Add SIOCSIWSTATS to get /proc/net/wireless programatically + * - Add SIOCSIWSTATS to get /proc/net/wireless programmatically * - Add DEV PRIVATE IOCTL to avoid collisions in SIOCDEVPRIVATE space * - Add new statistics (frag, retry, beacon) * - Add average quality (for user space calibration) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h index 315db89171..183f8c20f9 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h @@ -1000,7 +1000,7 @@ #define REG_SPIC_FLUSH_FIFO 0x0128//O VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); // spi-flash controller initialization -VOID SpicRxCmdRtl8195A(u8); // recieve command +VOID SpicRxCmdRtl8195A(u8); // receive command VOID SpicTxCmdRtl8195A(u8 cmd, SPIC_INIT_PARA SpicInitPara); // transfer command u8 SpicGetFlashStatusRtl8195A(SPIC_INIT_PARA SpicInitPara); // RDSR, read spi-flash status register VOID SpicSetFlashStatusRtl8195A(u32 data, SPIC_INIT_PARA SpicInitPara); // WRSR, write spi-flash status register diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c index 167bb4bb66..fa656f6a09 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c @@ -170,7 +170,7 @@ extern void FLASH_PageErase(uint32_t PageAddress); * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @note FLASH should be previously erased before new programmation (only exception to this + * @note FLASH should be previously erased before new programming (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram Indicate the way to program at a specified address. @@ -223,7 +223,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - /* In case of error, stop programation procedure */ + /* In case of error, stop programming procedure */ if (status != HAL_OK) { break; diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c index d0fe3dada4..ec0de43d9c 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c @@ -1040,7 +1040,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) return; } - /* I2S Overrun error interrupt occured ---------------------------------*/ + /* I2S Overrun error interrupt occurred --------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -1054,7 +1054,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) HAL_I2S_ErrorCallback(hi2s); } - /* I2S Underrun error interrupt occured --------------------------------*/ + /* I2S Underrun error interrupt occurred -------------------------------*/ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c index eaf1697a91..2297a402a0 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c @@ -703,14 +703,14 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - /* Check if the end of acquisition occured */ + /* Check if the end of acquisition occurred */ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET) { /* Clear EOA flag */ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA); } - /* Check if max count error occured */ + /* Check if max count error occurred */ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET) { /* Clear MCE flag */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c index 3aa2e4c37b..57fc036b67 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c @@ -143,7 +143,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_clock.c index 40ccdaf31b..7f53e68078 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_clock.c @@ -142,7 +142,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c index 2bbb626f14..4d83c9a258 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c @@ -173,7 +173,7 @@ extern void FLASH_PageErase(uint32_t PageAddress); * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @note FLASH should be previously erased before new programmation (only exception to this + * @note FLASH should be previously erased before new programming (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram: Indicate the way to program at a specified address. @@ -253,7 +253,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ - /* In case of error, stop programation procedure */ + /* In case of error, stop programming procedure */ if (status != HAL_OK) { break; diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c index 332717572f..828cd30823 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c @@ -1363,7 +1363,7 @@ static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_Receive_IT(hi2s); } - /* I2S Overrun error interrupt occured -------------------------------------*/ + /* I2S Overrun error interrupt occurred -------------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h index 98081ddc45..6c3810db2a 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h @@ -1203,7 +1203,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of 10-bit header sent (master mode). - * @note RESET: When no ADD10 event occured. + * @note RESET: When no ADD10 event occurred. * SET: When the master has sent the first address byte (header). * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 * @param I2Cx I2C Instance. diff --git a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_i2c.h index a3b261e85c..514829d48c 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_i2c.h @@ -1203,7 +1203,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of 10-bit header sent (master mode). - * @note RESET: When no ADD10 event occured. + * @note RESET: When no ADD10 event occurred. * SET: When the master has sent the first address byte (header). * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 * @param I2Cx I2C Instance. diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c index eaebd5682b..98908e1ee3 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c @@ -173,7 +173,7 @@ extern void FLASH_PageErase(uint32_t PageAddress); * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @note FLASH should be previously erased before new programmation (only exception to this + * @note FLASH should be previously erased before new programming (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram Indicate the way to program at a specified address. @@ -226,7 +226,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - /* In case of error, stop programation procedure */ + /* In case of error, stop programming procedure */ if (status != HAL_OK) { break; diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.c index 497a85c936..7549d7c58f 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.c @@ -5978,7 +5978,7 @@ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, } /** - * @brief Callback function invoked when a fault 1 interrupt occured + * @brief Callback function invoked when a fault 1 interrupt occurred * @param hhrtim: pointer to HAL HRTIM handle * @retval None * @retval None */ @@ -5993,7 +5993,7 @@ __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief Callback function invoked when a fault 2 interrupt occured + * @brief Callback function invoked when a fault 2 interrupt occurred * @param hhrtim: pointer to HAL HRTIM handle * @retval None */ @@ -6008,7 +6008,7 @@ __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief Callback function invoked when a fault 3 interrupt occured + * @brief Callback function invoked when a fault 3 interrupt occurred * @param hhrtim: pointer to HAL HRTIM handle * @retval None */ @@ -6023,7 +6023,7 @@ __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief Callback function invoked when a fault 4 interrupt occured + * @brief Callback function invoked when a fault 4 interrupt occurred * @param hhrtim: pointer to HAL HRTIM handle * @retval None */ @@ -6038,7 +6038,7 @@ __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief Callback function invoked when a fault 5 interrupt occured + * @brief Callback function invoked when a fault 5 interrupt occurred * @param hhrtim: pointer to HAL HRTIM handle * @retval None */ @@ -6053,7 +6053,7 @@ __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief Callback function invoked when a system fault interrupt occured + * @brief Callback function invoked when a system fault interrupt occurred * @param hhrtim: pointer to HAL HRTIM handle * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c index 0a9abba63f..d1844d77ba 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c @@ -945,7 +945,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_Receive_IT(hi2s); } - /* I2S Overrun error interrupt occured -------------------------------------*/ + /* I2S Overrun error interrupt occurred ------------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -967,7 +967,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_Transmit_IT(hi2s); } - /* I2S Underrun error interrupt occured ------------------------------------*/ + /* I2S Underrun error interrupt occurred -----------------------------------*/ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c index 37a3adbe27..338b9acd7a 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c @@ -435,7 +435,7 @@ void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT); } - /* I2Sext Overrun error interrupt occured --------------------------------*/ + /* I2Sext Overrun error interrupt occurred -------------------------------*/ if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -452,7 +452,7 @@ void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) HAL_I2S_ErrorCallback(hi2s); } - /* I2S Underrun error interrupt occured ----------------------------------*/ + /* I2S Underrun error interrupt occurred ---------------------------------*/ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ @@ -488,7 +488,7 @@ void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2S); } - /* I2S Overrun error interrupt occured -------------------------------------*/ + /* I2S Overrun error interrupt occurred ------------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -505,7 +505,7 @@ void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) HAL_I2S_ErrorCallback(hi2s); } - /* I2Sext Underrun error interrupt occured -------------------------------*/ + /* I2Sext Underrun error interrupt occurred ------------------------------*/ if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c index 77ba4ecd78..0e4df04945 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c @@ -1811,7 +1811,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) /* Wait until REACK flag is set */ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) { - /* Timeout Occured */ + /* Timeout Occurred */ return HAL_TIMEOUT; } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.c index f691e7f2f8..20f6c81007 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.c @@ -2296,7 +2296,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until TEACK flag is set */ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { - /* Timeout Occured */ + /* Timeout Occurred */ return HAL_TIMEOUT; } } @@ -2306,7 +2306,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until REACK flag is set */ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { - /* Timeout Occured */ + /* Timeout Occurred */ return HAL_TIMEOUT; } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c index a2caa0ddc4..9c2afcc7ee 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c @@ -2128,7 +2128,7 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) /* Wait until TEACK flag is set */ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) { - /* Timeout Occured */ + /* Timeout Occurred */ return HAL_TIMEOUT; } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c index 6ae08aac48..f1f150016f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c @@ -124,7 +124,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c index 6ae08aac48..f1f150016f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c @@ -124,7 +124,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c index 13d92ef57a..7d64108a6a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c @@ -130,7 +130,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c index f42278ce2c..c96b51c08c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c @@ -121,7 +121,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c index 9c33be421e..425580bc01 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c @@ -121,7 +121,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h index 23c09610e9..abb008c413 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h @@ -13604,7 +13604,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c index bffa88a663..698f92ec57 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c @@ -125,7 +125,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h index 5feb7667c5..1bc9d75b7d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h @@ -15156,7 +15156,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h index a7df3124bc..9302e9b082 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h @@ -15096,7 +15096,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h index 24be80d57a..f01a8b1f38 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h @@ -115,7 +115,7 @@ public: /** Get the local IP address * * @return Null-terminated representation of the local IP address - * or null if no IP address has been recieved + * or null if no IP address has been received */ virtual const char *get_ip_address(); @@ -129,7 +129,7 @@ public: /** Get the local gateway * * @return Null-terminated representation of the local gateway - * or null if no network mask has been recieved + * or null if no network mask has been received */ virtual const char *get_gateway(); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h index 16eb383e44..80634c63ee 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h @@ -15444,7 +15444,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c index ed57a5fa5d..6d1bdc97ad 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c @@ -124,7 +124,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h index d054b8fb07..b8893dae93 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h @@ -18175,7 +18175,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c index f80478f6ad..606c22dc8b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c @@ -1443,7 +1443,7 @@ static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_Receive_IT(hi2s); } - /* I2S Overrun error interrupt occured -------------------------------------*/ + /* I2S Overrun error interrupt occurred ------------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c index aae1ac401a..978c7ea753 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c @@ -784,7 +784,7 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT); } - /* I2Sext Overrun error interrupt occured --------------------------------*/ + /* I2Sext Overrun error interrupt occurred -------------------------------*/ if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -804,7 +804,7 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) HAL_I2S_ErrorCallback(hi2s); } - /* I2S Underrun error interrupt occured ----------------------------------*/ + /* I2S Underrun error interrupt occurred ---------------------------------*/ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ @@ -843,7 +843,7 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2S); } - /* I2S Overrun error interrupt occured -------------------------------------*/ + /* I2S Overrun error interrupt occurred ------------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -860,7 +860,7 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) HAL_I2S_ErrorCallback(hi2s); } - /* I2Sext Underrun error interrupt occured -------------------------------*/ + /* I2Sext Underrun error interrupt occurred ------------------------------*/ if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c index 0fba5e62c1..6d8daf6933 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c @@ -1310,7 +1310,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) uint32_t cr1config = hsai->Instance->CR1; uint32_t tmperror; - /* SAI Fifo request interrupt occured ------------------------------------*/ + /* SAI Fifo request interrupt occurred -----------------------------------*/ if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h index 69f44ce05b..1db3dba380 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h @@ -1309,7 +1309,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of 10-bit header sent (master mode). - * @note RESET: When no ADD10 event occured. + * @note RESET: When no ADD10 event occurred. * SET: When the master has sent the first address byte (header). * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 * @param I2Cx I2C Instance. diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h index 6ca83de287..f5a79948dc 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h @@ -976,7 +976,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) } /** - * @brief Inform application whether a autoreload match interrupt has occured. + * @brief Inform application whether a autoreload match interrupt has occurred. * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h index ca9deeebf4..4a6350c6f9 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h @@ -15398,7 +15398,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h index 1a19a08cfb..6c29b80fa9 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h @@ -15685,7 +15685,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h index 4e7911cf69..083f43e419 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h @@ -16074,7 +16074,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h index 5cde08e3a0..59e29e1b0c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h @@ -16169,7 +16169,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c index acc8a6bbc4..b5e8263498 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c @@ -577,7 +577,7 @@ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) [..] This subsection provides a set of functions allowing to control the MDIOS. (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state. - (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer. + (+) HAL_MDIOS_GetError() API, returns the errors occurred during data transfer. @endverbatim * @{ @@ -586,7 +586,7 @@ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) /** * @brief Gets MDIOS error flags * @param hmdios mdios handle - * @retval bit map of occured errors + * @retval bit map of occurred errors */ uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) { diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c index 15cf097456..5b9f5e4730 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c @@ -1358,7 +1358,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) uint32_t cr1config = hsai->Instance->CR1; uint32_t tmperror; - /* SAI Fifo request interrupt occured ------------------------------------*/ + /* SAI Fifo request interrupt occurred -----------------------------------*/ if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h index 007656613e..c69eb8b4a7 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h @@ -981,7 +981,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) } /** - * @brief Inform application whether a autoreload match interrupt has occured. + * @brief Inform application whether a autoreload match interrupt has occurred. * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c index c1c3fad6fc..d9d0873531 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c @@ -1069,7 +1069,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /* I2S interrupt error -------------------------------------------------*/ if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET) { - /* I2S Overrun error interrupt occured ---------------------------------*/ + /* I2S Overrun error interrupt occurred --------------------------------*/ if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) { /* Disable RXNE and ERR interrupt */ @@ -1079,7 +1079,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); } - /* I2S Underrun error interrupt occured --------------------------------*/ + /* I2S Underrun error interrupt occurred -------------------------------*/ if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c index 06bd6981c2..ad0fd57f14 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c @@ -896,7 +896,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) */ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) { - /* IRDA parity error interrupt occurred -------------------------------------*/ + /* IRDA parity error interrupt occurred ------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET)) { __HAL_IRDA_CLEAR_PEFLAG(hirda); @@ -906,7 +906,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) hirda->State = HAL_IRDA_STATE_READY; } - /* IRDA frame error interrupt occured --------------------------------------*/ + /* IRDA frame error interrupt occurred -------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) { __HAL_IRDA_CLEAR_FEFLAG(hirda); @@ -916,7 +916,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) hirda->State = HAL_IRDA_STATE_READY; } - /* IRDA noise error interrupt occured --------------------------------------*/ + /* IRDA noise error interrupt occurred -------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) { __HAL_IRDA_CLEAR_NEFLAG(hirda); @@ -926,7 +926,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) hirda->State = HAL_IRDA_STATE_READY; } - /* IRDA Over-Run interrupt occured -----------------------------------------*/ + /* IRDA Over-Run interrupt occurred -----------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) { __HAL_IRDA_CLEAR_OREFLAG(hirda); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c index a33f92310c..492bff6bd2 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c @@ -724,7 +724,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) hsc->State = HAL_SMARTCARD_STATE_READY; } - /* SMARTCARD frame error interrupt occured ---------------------------------*/ + /* SMARTCARD frame error interrupt occurred --------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) { __HAL_SMARTCARD_CLEAR_FEFLAG(hsc); @@ -733,7 +733,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) hsc->State = HAL_SMARTCARD_STATE_READY; } - /* SMARTCARD noise error interrupt occured ---------------------------------*/ + /* SMARTCARD noise error interrupt occurred --------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) { __HAL_SMARTCARD_CLEAR_NEFLAG(hsc); @@ -742,7 +742,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) hsc->State = HAL_SMARTCARD_STATE_READY; } - /* SMARTCARD Over-Run interrupt occured ------------------------------------*/ + /* SMARTCARD Over-Run interrupt occurred -----------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) { __HAL_SMARTCARD_CLEAR_OREFLAG(hsc); @@ -751,7 +751,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) hsc->State = HAL_SMARTCARD_STATE_READY; } - /* SMARTCARD receiver timeout interrupt occured ----------------------------*/ + /* SMARTCARD receiver timeout interrupt occurred ---------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RTO) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_RTOF); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c index daf265ddd3..fe51945c15 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c @@ -709,14 +709,14 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - /* Check if the end of acquisition occured */ + /* Check if the end of acquisition occurred */ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET) { /* Clear EOA flag */ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA); } - /* Check if max count error occured */ + /* Check if max count error occurred */ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET) { /* Clear MCE flag */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c index 98470850f3..694e8baea0 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c @@ -1083,7 +1083,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { - /* UART parity error interrupt occurred ------------------------------------*/ + /* UART parity error interrupt occurred -----------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET)) { @@ -1095,7 +1095,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxState = HAL_UART_STATE_READY; } - /* UART frame error interrupt occured --------------------------------------*/ + /* UART frame error interrupt occurred -------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); @@ -1106,7 +1106,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxState = HAL_UART_STATE_READY; } - /* UART noise error interrupt occured --------------------------------------*/ + /* UART noise error interrupt occurred -------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); @@ -1117,7 +1117,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxState = HAL_UART_STATE_READY; } - /* UART Over-Run interrupt occurred -----------------------------------------*/ + /* UART Over-Run interrupt occurred ----------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); @@ -1128,7 +1128,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxState = HAL_UART_STATE_READY; } - /* Call UART Error Call back function if need be --------------------------*/ + /* Call UART Error Call back function if need be ---------------------------*/ if(huart->ErrorCode != HAL_UART_ERROR_NONE) { /* Set the UART state ready to be able to start again the process */ @@ -1138,7 +1138,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UART_ErrorCallback(huart); } - /* UART Wake Up interrupt occured ------------------------------------------*/ + /* UART Wake Up interrupt occurred -----------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET)) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c index 3fc35648d2..32e34e5fda 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c @@ -1040,7 +1040,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { - /* USART parity error interrupt occured ------------------------------------*/ + /* USART parity error interrupt occurred ------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET)) { __HAL_USART_CLEAR_PEFLAG(husart); @@ -1049,7 +1049,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_READY; } - /* USART frame error interrupt occured -------------------------------------*/ + /* USART frame error interrupt occurred -------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) { __HAL_USART_CLEAR_FEFLAG(husart); @@ -1058,7 +1058,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_READY; } - /* USART noise error interrupt occured -------------------------------------*/ + /* USART noise error interrupt occurred -------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) { __HAL_USART_CLEAR_NEFLAG(husart); @@ -1067,7 +1067,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_READY; } - /* USART Over-Run interrupt occured ----------------------------------------*/ + /* USART Over-Run interrupt occurred ----------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) { __HAL_USART_CLEAR_OREFLAG(husart); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_lptim.h index 42c6916ca1..57c89976ab 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_lptim.h @@ -983,7 +983,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) } /** - * @brief Inform application whether a autoreload match interrupt has occured. + * @brief Inform application whether a autoreload match interrupt has occurred. * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c index bd4a411cb0..1a232bb2f5 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c @@ -158,7 +158,7 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { } uint32_t flash_get_page_size(const flash_t *obj) { - /* Page size is the minimum programable size, which 4 bytes */ + /* Page size is the minimum programmable size, which 4 bytes */ return 4; } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_clock.c index d14cbc4bc6..944956c5da 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_clock.c @@ -117,7 +117,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c index 6d1889d50a..f776950cf6 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c @@ -133,7 +133,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c index df762686ea..d6cf4416dc 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c @@ -117,7 +117,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c index 6d1889d50a..f776950cf6 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c @@ -133,7 +133,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occured... + // [TODO] Put something here to tell the user that a problem occurred... } } } diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.c index 63d8b991c4..c8aa093cb7 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.c @@ -1056,7 +1056,7 @@ static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } - /* Return the Option Byte BOR programmation Status */ + /* Return the Option Byte BOR programming Status */ return status; } diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.c index 9e4151e1a7..73f83e2e8b 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.c @@ -1033,7 +1033,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /* I2S interrupt error -------------------------------------------------*/ if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET) { - /* I2S Overrun error interrupt occured ---------------------------------*/ + /* I2S Overrun error interrupt occurred --------------------------------*/ if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) { /* Disable RXNE and ERR interrupt */ @@ -1043,7 +1043,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); } - /* I2S Underrun error interrupt occured --------------------------------*/ + /* I2S Underrun error interrupt occurred -------------------------------*/ if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) { /* Disable TXE and ERR interrupt */ @@ -1053,7 +1053,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); } - /* I2S Frame format error interrupt occured --------------------------*/ + /* I2S Frame format error interrupt occurred --------------------------*/ if((i2ssr & I2S_FLAG_FRE) == I2S_FLAG_FRE) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.c index 31b144ac60..e45d6b1151 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.c @@ -1781,7 +1781,7 @@ HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32 } else { - /* An error occured while enabling/disabling the wide bus*/ + /* An error occurred while enabling/disabling the wide bus*/ } } else diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h index dbe82c30be..84a2057411 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h @@ -1205,7 +1205,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of 10-bit header sent (master mode). - * @note RESET: When no ADD10 event occured. + * @note RESET: When no ADD10 event occurred. * SET: When the master has sent the first address byte (header). * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 * @param I2Cx I2C Instance. diff --git a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c index 5e6932071f..d4b1b44203 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c @@ -157,7 +157,7 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) uint32_t flash_get_page_size(const flash_t *obj) { - /* Page size is the minimum programable size, which 4 bytes */ + /* Page size is the minimum programmable size, which 4 bytes */ return 4; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c index 02f941c970..74f81be2ce 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c @@ -1469,7 +1469,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) uint32_t cr1config = hsai->Instance->CR1; uint32_t tmperror; - /* SAI Fifo request interrupt occured ------------------------------------*/ + /* SAI Fifo request interrupt occurred -----------------------------------*/ if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h index fc04402a39..4b8c1dc129 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h @@ -1030,7 +1030,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) } /** - * @brief Inform application whether a autoreload match interrupt has occured. + * @brief Inform application whether a autoreload match interrupt has occurred. * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c index 4904e93317..45444bee0e 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c @@ -254,7 +254,7 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { * @return The size of a page */ uint32_t flash_get_page_size(const flash_t *obj) { - /* Page size is the minimum programable size, which 8 bytes */ + /* Page size is the minimum programmable size, which 8 bytes */ return 8; } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c index 3c4bc21945..973d30dd7d 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c @@ -1910,7 +1910,7 @@ uint8_t serial_rx_active(serial_t *obj) } /** The asynchronous TX handler. Writes to the TX FIFO and checks for events. - * If any TX event has occured, the TX abort function is called. + * If any TX event has occurred, the TX abort function is called. * * @param obj The serial object * @return Returns event flags if a TX transfer termination condition was met or 0 otherwise @@ -1961,7 +1961,7 @@ int serial_tx_irq_handler_asynch(serial_t *obj) } /** The asynchronous RX handler. Reads from the RX FIFOF and checks for events. - * If any RX event has occured, the RX abort function is called. + * If any RX event has occurred, the RX abort function is called. * * @param obj The serial object * @return Returns event flags if a RX transfer termination condition was met or 0 otherwise diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h index 8f5df68ef2..e92becba4d 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h @@ -59,7 +59,7 @@ extern "C" { uint32_t TIDLE; /*!< The status of TXDx pin after output of the last bit */ uint32_t TXDEMP; /*!< The status of TXDx pin when an under run error - is occured in SCLK input mode */ + is occurred in SCLK input mode */ uint32_t EHOLDTime; /*!< The last bit hold time of TXDx pin in SCLK input mode */ uint32_t IntervalTime; /*!< Setting interval time of continuous transmission which diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c index 2a90f4a30f..a6c993cc29 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c @@ -246,7 +246,7 @@ void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx) } /** - * @brief Set I2c bus to Master mode and Generate start condition in I2C mode. + * @brief Set I2C bus to Master mode and Generate start condition in I2C mode. * @param I2Cx: Select the I2C channel. * This parameter can be one of the following values: * TSB_I2C0,TSB_I2C1 @@ -262,7 +262,7 @@ void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx) } /** - * @brief Set I2c bus to Master mode and Generate stop condition in I2C mode. + * @brief Set I2C bus to Master mode and Generate stop condition in I2C mode. * @param I2Cx: Select the I2C channel. * This parameter can be one of the following values: * TSB_I2C0,TSB_I2C1 diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c index 2dd7cc1b8c..adaac5a604 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c @@ -1121,7 +1121,7 @@ void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitSt tmp &= (CR_IOC_MASK & CR_SCLKS_MASK & CR_TIDLE_MASK); tmp |= (IOClkSel | InitStruct->InputClkEdge | InitStruct->TIDLE); - /* Set status of TXDx pin when an under run error is occured + /* Set status of TXDx pin when an under run error is occurred and The last bit hold time of TXDx pin in SCLK input mode */ if (IOClkSel == SIO_CLK_SCLKINPUT) { tmp &= (CR_TXDEMP_MASK & CR_EHOLD_MASK); diff --git a/tools/debug_tools/crash_log_parser/crash_log_parser.py b/tools/debug_tools/crash_log_parser/crash_log_parser.py index 96bf0ad786..33b1d9c8c8 100644 --- a/tools/debug_tools/crash_log_parser/crash_log_parser.py +++ b/tools/debug_tools/crash_log_parser/crash_log_parser.py @@ -48,7 +48,7 @@ class ElfHelper(object): def print_HFSR_info(hfsr): if int(hfsr, 16) & 0x80000000: - print("\t\tDebug Event Occured") + print("\t\tDebug Event Occurred") if int(hfsr, 16) & 0x40000000: print("\t\tForced exception, a fault with configurable priority has been escalated to HardFault") if int(hfsr, 16) & 0x2: From 43db7b32582406be87e2ead2936ad501a09779ce Mon Sep 17 00:00:00 2001 From: Brendan McDonnell Date: Tue, 20 Feb 2018 20:33:53 -0500 Subject: [PATCH 044/118] a few grammar corrections --- .../fnet/fnet_stack/services/dns/fnet_dns.h | 4 +- .../TARGET_K66F/drivers/fsl_flexcan.h | 2 +- .../TARGET_MCU_K24F/drivers/fsl_flexcan.h | 2 +- .../TARGET_MCU_K64F/drivers/fsl_flexcan.h | 2 +- .../TARGET_NUVOTON/TARGET_M480/device/M480.h | 40 +++++++++---------- .../TARGET_NANO100/device/Nano100Series.h | 6 +-- .../TARGET_NUC472/device/NUC472_442.h | 38 +++++++++--------- .../TARGET_LPC546XX/drivers/fsl_mcan.h | 2 +- .../TARGET_MIMXRT1050/drivers/fsl_flexcan.h | 2 +- .../Periph_Driver/inc/tmpm066_uart.h | 2 +- .../Periph_Driver/src/tmpm066_uart.c | 2 +- 11 files changed, 51 insertions(+), 51 deletions(-) diff --git a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h index d037c6b83d..c154f6295b 100644 --- a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h +++ b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h @@ -122,7 +122,7 @@ struct fnet_dns_params fnet_address_family_t addr_family; /**< @brief Family of the IP Address which is queried.*/ fnet_dns_callback_resolved_t callback; /**< @brief Pointer to the callback function defined by * @ref fnet_dns_callback_resolved_t. It is called when the - * DNS-client resolving is finished or an error is occurred. */ + * DNS-client resolving is finished or an error has occurred. */ fnet_uint32_t cookie; /**< @brief Optional application-specific parameter. @n * It's passed to the @c callback * function as input parameter. */ @@ -155,7 +155,7 @@ extern "C" { * The resolved IP-address will be passed to the @ref fnet_dns_callback_resolved_t callback function, * which is set in @c params. @n * The DNS service is released automatically as soon as the - * resolving is finished or an error is occurred. + * resolving is finished or an error has occurred. * ******************************************************************************/ fnet_return_t fnet_dns_init( struct fnet_dns_params *params ); diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h index 118badf58f..1d19e01f72 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h @@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable * * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to - * read FlEXCAN_ErrorFlag and distinguish which error is occur using + * read FlEXCAN_ErrorFlag and distinguish which error has occurred using * @ref _flexcan_error_flags enumerations. */ enum _flexcan_flags diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h index 118badf58f..1d19e01f72 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h @@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable * * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to - * read FlEXCAN_ErrorFlag and distinguish which error is occur using + * read FlEXCAN_ErrorFlag and distinguish which error has occurred using * @ref _flexcan_error_flags enumerations. */ enum _flexcan_flags diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h index bafc4450ac..1b060f31ef 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h @@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable * * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to - * read FlEXCAN_ErrorFlag and distinguish which error is occur using + * read FlEXCAN_ErrorFlag and distinguish which error has occurred using * @ref _flexcan_error_flags enumerations. */ enum _flexcan_flags diff --git a/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h b/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h index d3e5669df7..24e169925f 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h @@ -3469,7 +3469,7 @@ typedef struct { * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. - * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. + * | | |The flag is set if any wake-up source has occurred. Refer Power Modes and Wake-up Sources chapter. * | | |Note1: Write 1 to clear the bit to 0. * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. * |[7] |PDEN |System Power-down Enable (Write Protect) @@ -25914,7 +25914,7 @@ typedef struct { * | | |0 = DMA Disabled. * | | |1 = DMA Enabled. * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. - * | | |Note: If target abort is occurred, DMAEN will be cleared. + * | | |Note: If target abort has occurred, DMAEN will be cleared. * |[1] |DMARST |Software Engine Reset * | | |0 = No effect. * | | |1 = Reset internal state machine and pointers @@ -26006,7 +26006,7 @@ typedef struct { * | :----: | :----: | :---- | * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation - * | | |When Target Abort is occurred, please reset all engine. + * | | |When Target Abort has occurred, please reset all engine. * | | |0 = No bus ERROR response received. * | | |1 = Bus ERROR response received. * | | |Note: This bit is read only, but can be cleared by writing '1' to it. @@ -26119,12 +26119,12 @@ typedef struct { * | | |Note: This bit is read only, but can be cleared by writing '1' to it. * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer - * | | |When CRC error is occurred, software should reset SD engine + * | | |When CRC error has occurred, software should reset SD engine * | | |Some response (ex * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag * | | |In this condition, software should ignore CRC error and clears this bit manually. - * | | |0 = No CRC error is occurred. - * | | |1 = CRC error is occurred. + * | | |0 = No CRC error has occurred. + * | | |1 = CRC error has occurred. * | | |Note: This bit is read only, but can be cleared by writing '1' to it. * |[2] |CRC7 |CRC7 Check Status (Read Only) * | | |SD host will check CRC7 correctness during each response in @@ -27705,60 +27705,60 @@ typedef struct { * | | |This bit conveys the interrupt status for USB specific events endpoint * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[1] |CEPIF |Control Endpoint Interrupt * | | |This bit conveys the interrupt status for control endpoint * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[2] |EPAIF |Endpoint a Interrupt * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[3] |EPBIF |Endpoint B Interrupt * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[4] |EPCIF |Endpoint C Interrupt * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[5] |EPDIF |Endpoint D Interrupt * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[6] |EPEIF |Endpoint E Interrupt * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[7] |EPFIF |Endpoint F Interrupt * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[8] |EPGIF |Endpoint G Interrupt * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[9] |EPHIF |Endpoint H Interrupt * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[10] |EPIIF |Endpoint I Interrupt * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[11] |EPJIF |Endpoint J Interrupt * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[12] |EPKIF |Endpoint K Interrupt * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[13] |EPLIF |Endpoint L Interrupt * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * @var HSUSBD_T::GINTEN * Offset: 0x08 Global Interrupt Enable Register * --------------------------------------------------------------------------------------------------- diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h b/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h index 6a6520e57c..f661a3c4b5 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h @@ -10976,18 +10976,18 @@ typedef struct { * |[0] |BUS_STS |BUS Interrupt Status * | | |The BUS event means there is bus suspense or bus resume in the bus. * | | |This bit is used to indicate that there is one of events in the bus. - * | | |0 = No BUS event is occurred. + * | | |0 = No BUS event has occurred. * | | |1 = BUS event occurred; check USB_BUSSTS [3:0] to know which kind of bus event was occurred, cleared by write "1" to USB_INTSTS [0]. * |[1] |USB_STS |USB Interrupt Status * | | |The USB event means that there is Setup Token, IN token, OUT ACK, ISO IN, or ISO OUT event in the bus. * | | |This bit is used to indicate that there is one of events in the bus. - * | | |0 = No USB event is occurred. + * | | |0 = No USB event has occurred. * | | |1 = USB event occurred, check EPSTS0~7[3:0] in USB_EPSTS [31:8] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [1] or USB_INTSTS[31] or EPEVT0~7. * |[2] |FLD_STS |Floating Interrupt Status * | | |0 = There is not attached event in the USB. * | | |1 = There is attached event in the USB and it is cleared by write "1" to USB_INTSTS [2]. * |[3] |WKEUP_STS |Wake-Up Interrupt Status - * | | |0 = No wake-up event is occurred. + * | | |0 = No wake-up event has occurred. * | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS [3]. * |[16] |EPEVT0 |USB Event Status On EP0 * | | |0 = No event occurred in Endpoint 0. diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h index 5ae86a9c14..762f35c936 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h @@ -22305,7 +22305,7 @@ typedef struct { * | | |0 = DMA Disabled. * | | |1 = DMA Enabled. * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. - * | | |Note: If target abort is occurred, DMAEN will be cleared. + * | | |Note: If target abort has occurred, DMAEN will be cleared. * |[1] |DMARST |Software Engine Reset * | | |0 = No effect. * | | |1 = Reset internal state machine and pointers. @@ -22432,7 +22432,7 @@ typedef struct { * | :----: | :----: | :---- | * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation. - * | | |When Target Abort is occurred, please reset all engine. + * | | |When Target Abort has occurred, please reset all engine. * | | |0 = No bus ERROR response received. * | | |1 = Bus ERROR response received. * | | |Note: This bit is read only, but can be cleared by writing '1' to it. @@ -22583,12 +22583,12 @@ typedef struct { * | | |Note: This bit is read only, but can be cleared by writing '1' to it. * |[1] |CRCIF |CRC7, CRC16 And CRC Status Error Interrupt Flag (Read Only) * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer. - * | | |When CRC error is occurred, software should reset SD engine. + * | | |When CRC error has occurred, software should reset SD engine. * | | |Some response (ex. * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag. * | | |In this condition, software should ignore CRC error and clears this bit manually. - * | | |0 = No CRC error is occurred. - * | | |1 = CRC error is occurred. + * | | |0 = No CRC error has occurred. + * | | |1 = CRC error has occurred. * | | |Note: This bit is read only, but can be cleared by writing '1' to it. * |[2] |CRC7 |CRC7 Check Status (Read Only) * | | |SD host will check CRC7 correctness during each response in. @@ -27165,60 +27165,60 @@ typedef struct { * | | |This bit conveys the interrupt status for USB specific events endpoint. * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[1] |CEPIF |Control Endpoint Interrupt * | | |This bit conveys the interrupt status for control endpoint. * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[2] |EPAIF |Endpoints A Interrupt * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[3] |EPBIF |Endpoints B Interrupt * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[4] |EPCIF |Endpoints C Interrupt * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[5] |EPDIF |Endpoints D Interrupt * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[6] |EPEIF |Endpoints E Interrupt * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[7] |EPFIF |Endpoints F Interrupt * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[8] |EPGIF |Endpoints G Interrupt * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[9] |EPHIF |Endpoints H Interrupt * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[10] |EPIIF |Endpoints I Interrupt * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[11] |EPJIF |Endpoints J Interrupt * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[12] |EPKIF |Endpoints K Interrupt * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. * |[13] |EPLIF |Endpoints L Interrupt * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event is occurred. + * | | |1 = The related interrupt event has occurred. */ __I uint32_t GINTSTS; uint32_t RESERVE0[1]; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h index 36f33a526a..cd45a4e7f5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h @@ -79,7 +79,7 @@ enum _mcan_status * * This provides constants for the MCAN status flags for use in the MCAN functions. * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to - * read MCAN_ErrorFlag and distinguish which error is occur using + * read MCAN_ErrorFlag and distinguish which error has occurred using * @ref _mcan_error_flags enumerations. */ enum _mcan_flags diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h index 3ae7598f00..335c41b591 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h @@ -240,7 +240,7 @@ enum _flexcan_interrupt_enable * * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to - * read FlEXCAN_ErrorFlag and distinguish which error is occur using + * read FlEXCAN_ErrorFlag and distinguish which error has occurred using * @ref _flexcan_error_flags enumerations. */ enum _flexcan_flags diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h index e92becba4d..f49d91b38a 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h @@ -59,7 +59,7 @@ extern "C" { uint32_t TIDLE; /*!< The status of TXDx pin after output of the last bit */ uint32_t TXDEMP; /*!< The status of TXDx pin when an under run error - is occurred in SCLK input mode */ + has occurred in SCLK input mode */ uint32_t EHOLDTime; /*!< The last bit hold time of TXDx pin in SCLK input mode */ uint32_t IntervalTime; /*!< Setting interval time of continuous transmission which diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c index adaac5a604..0f1dd33ec9 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c @@ -1121,7 +1121,7 @@ void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitSt tmp &= (CR_IOC_MASK & CR_SCLKS_MASK & CR_TIDLE_MASK); tmp |= (IOClkSel | InitStruct->InputClkEdge | InitStruct->TIDLE); - /* Set status of TXDx pin when an under run error is occurred + /* Set status of TXDx pin when an under run error has occurred and The last bit hold time of TXDx pin in SCLK input mode */ if (IOClkSel == SIO_CLK_SCLKINPUT) { tmp &= (CR_TXDEMP_MASK & CR_EHOLD_MASK); From c59380dc82157fe2c1c4ad0b5b922c28be583bf4 Mon Sep 17 00:00:00 2001 From: Brendan McDonnell Date: Wed, 21 Feb 2018 19:08:28 -0500 Subject: [PATCH 045/118] revert typos in external sources --- features/FEATURE_BLE/ble/BLEInstanceBase.h | 2 +- features/FEATURE_BLE/ble/pal/AttClient.h | 2 +- features/FEATURE_BLE/ble/pal/GapEvents.h | 2 +- .../ws-core/sw/wsf/include/wsf_buf.h | 2 +- .../TARGET_MCU_NRF51822/hal_patch/sleep.c | 2 +- .../sdk/source/ble/peer_manager/id_manager.c | 2 +- .../libraries/bootloader_dfu/dfu_types.h | 8 ++-- .../source/softdevice/s130/headers/ble_gap.h | 4 +- .../softdevice/s130/headers/ble_gattc.h | 2 +- .../softdevice/s130/headers/ble_l2cap.h | 2 +- .../lwip-interface/EthernetInterface.h | 6 +-- .../TARGET_LPCTarget/lpc17xx_emac.h | 12 +++--- .../lwip-interface/lwip/CHANGELOG | 2 +- .../lwip/src/apps/snmp/lwip_snmp_msg.c | 2 +- .../lwip/src/apps/tftp/lwip_tftp_server.c | 2 +- .../lwip/src/netif/ppp/lwip_ipcp.c | 2 +- .../lwip/src/netif/ppp/lwip_ipv6cp.c | 2 +- .../lwip/src/netif/ppp/lwip_lcp.c | 2 +- features/filesystem/fat/ChaN/ff.cpp | 2 +- features/lorawan/LoRaWANStack.cpp | 2 +- features/mbedtls/inc/mbedtls/bignum.h | 2 +- features/mbedtls/inc/mbedtls/x509.h | 6 +-- features/mbedtls/src/ecp.c | 2 +- features/mbedtls/src/error.c | 2 +- features/mbedtls/targets/TARGET_STM/aes_alt.h | 2 +- .../nanostack-interface/NanostackInterface.h | 2 +- .../6LoWPAN/Thread/thread_dhcpv6_client.c | 2 +- .../6LoWPAN/Thread/thread_management_server.c | 8 ++-- .../fnet/fnet_stack/services/dns/fnet_dns.h | 4 +- .../unsupported/USBDevice/USBMSD/USBMSD.cpp | 4 +- .../TARGET_Silicon_Labs/src/em_usbdep.c | 4 +- .../tests/libs/SPIHalfDuplex/SPIHalfDuplex.h | 2 +- .../TARGET_CM3DS_MPS2/ethernet_api.c | 6 +-- .../TARGET_IOTSS/SDK/ETH_MPS2.c | 2 +- .../TARGET_IOTSS/SDK/mps2_ethernet_api.h | 2 +- .../TARGET_IOTSS/ethernet_api.c | 6 +-- .../TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c | 2 +- .../TARGET_MPS2/SDK/mps2_ethernet_api.h | 2 +- .../TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c | 6 +-- .../TARGET_ADUCM3029/api/spi_api.c | 2 +- .../TARGET_ADUCM3029/bsp/tmr/adi_tmr.c | 2 +- .../TARGET_ADUCM3029/bsp/uart/adi_uart.c | 2 +- .../TARGET_ADUCM4050/api/spi_api.c | 2 +- .../TARGET_ADUCM4050/bsp/tmr/adi_tmr.c | 2 +- .../TARGET_ADUCM4050/bsp/uart/adi_uart.c | 2 +- .../TARGET_SAM_CortexM0P/drivers/tcc/tcc.c | 6 +-- .../TARGET_SAM_CortexM0P/drivers/tcc/tcc.h | 2 +- .../TARGET_SAM_CortexM0P/serial_api.c | 2 +- .../include/component/comp_rstc.h | 2 +- .../TARGET_K66F/drivers/fsl_flexcan.h | 2 +- .../TARGET_K66F/drivers/fsl_sai.c | 2 +- .../TARGET_K82F/drivers/fsl_qspi.c | 2 +- .../TARGET_K82F/drivers/fsl_sai.c | 2 +- .../TARGET_K82F/drivers/fsl_trng.c | 2 +- .../TARGET_KL43Z/drivers/fsl_sai.c | 2 +- .../TARGET_KL43Z/drivers/fsl_sai_dma.h | 2 +- .../TARGET_KL82Z/drivers/fsl_qspi.c | 2 +- .../TARGET_KL82Z/drivers/fsl_trng.c | 2 +- .../TARGET_KW24D/drivers/fsl_sai.c | 2 +- .../TARGET_KW41Z/drivers/fsl_trng.c | 2 +- .../TARGET_MCU_K22F/drivers/fsl_sai.c | 2 +- .../TARGET_MCU_K24F/drivers/fsl_flexcan.h | 2 +- .../TARGET_MCU_K24F/drivers/fsl_sai.c | 2 +- .../TARGET_MCU_K64F/drivers/fsl_flexcan.h | 2 +- .../TARGET_MCU_K64F/drivers/fsl_sai.c | 2 +- .../TARGET_MAX32625/mxc/tmr_utils.h | 2 +- .../TARGET_Maxim/TARGET_MAX32630/mxc/aes.h | 4 +- .../TARGET_MAX32630/mxc/tmr_utils.h | 2 +- .../softdevice/s130/headers/nrf_ble_gattc.h | 2 +- .../softdevice/s130/headers/nrf_ble_l2cap.h | 2 +- .../softdevice/s132/headers/nrf_ble_gattc.h | 2 +- .../softdevice/s132/headers/nrf_ble_l2cap.h | 2 +- .../softdevice/s140/headers/nrf_ble_gattc.h | 2 +- .../softdevice/s140/headers/nrf_ble_l2cap.h | 2 +- .../ble/ble_error_log/ble_error_log.h | 6 +-- .../ble/peer_manager/gattc_cache_manager.c | 2 +- .../ble/peer_manager/gatts_cache_manager.c | 2 +- .../ble/peer_manager/id_manager.c | 2 +- .../TARGET_SDK11/device/nrf52_bitfields.h | 4 +- .../libraries/bootloader_dfu/dfu_types.h | 8 ++-- .../ble/ble_error_log/ble_error_log.h | 6 +-- .../ble/peer_manager/gatts_cache_manager.c | 2 +- .../ble/peer_manager/id_manager.c | 2 +- .../TARGET_SDK13/device/nrf52840_bitfields.h | 4 +- .../TARGET_SDK13/device/nrf52_bitfields.h | 4 +- .../TARGET_NORDIC/TARGET_NRF5/serial_api.c | 20 +++++----- targets/TARGET_NORDIC/TARGET_NRF5/sleep.c | 2 +- .../TARGET_NUVOTON/TARGET_M480/device/M480.h | 40 +++++++++---------- .../TARGET_NANO100/device/Nano100Series.h | 6 +-- .../TARGET_NUC472/device/NUC472_442.h | 40 +++++++++---------- targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c | 2 +- targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c | 2 +- .../TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c | 2 +- targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c | 2 +- .../TARGET_NXP/TARGET_LPC176X/ethernet_api.c | 30 +++++++------- targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c | 2 +- .../TARGET_LPC4088/ethernet_api.c | 36 ++++++++--------- .../TARGET_LPC408X/TARGET_LPC4088/i2c_api.c | 2 +- .../TARGET_LPC4088_DM/ethernet_api.c | 30 +++++++------- .../TARGET_LPC4088_DM/i2c_api.c | 2 +- .../device/system_LPC407x_8x_177x_8x.c | 3 +- .../TARGET_NXP/TARGET_LPC43XX/ethernet_api.c | 2 +- targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c | 2 +- targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c | 2 +- targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c | 2 +- .../TARGET_LPC546XX/drivers/fsl_mcan.h | 8 ++-- .../TARGET_LPC546XX/drivers/fsl_sdif.h | 4 +- .../TARGET_MIMXRT1050/drivers/fsl_adc.h | 2 +- .../TARGET_MIMXRT1050/drivers/fsl_flexcan.h | 2 +- .../TARGET_MIMXRT1050/drivers/fsl_sai.c | 2 +- .../TARGET_MIMXRT1050/drivers/fsl_spdif.c | 2 +- .../TARGET_MIMXRT1050/drivers/fsl_trng.c | 2 +- .../TARGET_NCS36510/char_driver.h | 2 +- .../TARGET_NCS36510/ncs36510_i2c.c | 4 +- .../TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c | 2 +- .../TARGET_AMEBA/RTWInterface.h | 6 +-- .../drivers/wlan/realtek/src/osdep/wireless.h | 2 +- .../8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h | 2 +- .../device/stm32f0xx_hal_flash.c | 4 +- .../TARGET_STM32F0/device/stm32f0xx_hal_i2s.c | 4 +- .../TARGET_STM32F0/device/stm32f0xx_hal_tsc.c | 4 +- .../device/system_clock.c | 2 +- .../TARGET_DISCO_F100RB/device/system_clock.c | 2 +- .../device/stm32f1xx_hal_flash.c | 4 +- .../TARGET_STM32F1/device/stm32f1xx_hal_i2s.c | 2 +- .../TARGET_STM32F1/device/stm32f1xx_ll_i2c.h | 2 +- .../TARGET_STM32F2/device/stm32f2xx_ll_i2c.h | 2 +- .../device/stm32f3xx_hal_flash.c | 4 +- .../device/stm32f3xx_hal_hrtim.c | 12 +++--- .../TARGET_STM32F3/device/stm32f3xx_hal_i2s.c | 4 +- .../device/stm32f3xx_hal_i2s_ex.c | 8 ++-- .../device/stm32f3xx_hal_irda.c | 2 +- .../device/stm32f3xx_hal_uart.c | 4 +- .../device/stm32f3xx_hal_usart.c | 2 +- .../device/system_clock.c | 2 +- .../device/system_clock.c | 2 +- .../device/system_clock.c | 2 +- .../TARGET_DISCO_F401VC/system_clock.c | 2 +- .../TARGET_ARCH_MAX/system_clock.c | 2 +- .../TARGET_STM32F407xG/device/stm32f407xx.h | 2 +- .../TARGET_ELMO_F411RE/system_clock.c | 2 +- .../TARGET_STM32F429xI/device/stm32f429xx.h | 2 +- .../TARGET_STM32F437xG/device/stm32f437xx.h | 2 +- .../ublox-odin-w2-drivers/OdinWiFiInterface.h | 4 +- .../TARGET_STM32F439xI/device/stm32f439xx.h | 2 +- .../TARGET_B96B_F446VE/system_clock.c | 2 +- .../TARGET_STM32F469xI/device/stm32f469xx.h | 2 +- .../TARGET_STM32F4/device/stm32f4xx_hal_i2s.c | 2 +- .../device/stm32f4xx_hal_i2s_ex.c | 8 ++-- .../TARGET_STM32F4/device/stm32f4xx_hal_sai.c | 2 +- .../TARGET_STM32F4/device/stm32f4xx_ll_i2c.h | 2 +- .../device/stm32f4xx_ll_lptim.h | 2 +- .../TARGET_STM32F746xG/device/stm32f746xx.h | 2 +- .../TARGET_STM32F756xG/device/stm32f756xx.h | 2 +- .../TARGET_STM32F767xI/device/stm32f767xx.h | 2 +- .../TARGET_STM32F769xI/device/stm32f769xx.h | 2 +- .../device/stm32f7xx_hal_mdios.c | 4 +- .../TARGET_STM32F7/device/stm32f7xx_hal_sai.c | 2 +- .../device/stm32f7xx_ll_lptim.h | 2 +- .../TARGET_STM32L0/device/stm32l0xx_hal_i2s.c | 4 +- .../device/stm32l0xx_hal_irda.c | 8 ++-- .../device/stm32l0xx_hal_smartcard.c | 8 ++-- .../TARGET_STM32L0/device/stm32l0xx_hal_tsc.c | 4 +- .../device/stm32l0xx_hal_uart.c | 12 +++--- .../device/stm32l0xx_hal_usart.c | 8 ++-- .../device/stm32l0xx_ll_lptim.h | 2 +- targets/TARGET_STM/TARGET_STM32L0/flash_api.c | 2 +- .../TARGET_MOTE_L152RC/device/system_clock.c | 2 +- .../TARGET_MTB_MTS_XDOT/device/system_clock.c | 2 +- .../TARGET_NZ32_SC151/device/system_clock.c | 2 +- .../TARGET_XDOT_L151CC/device/system_clock.c | 2 +- .../device/stm32l1xx_hal_flash_ex.c | 2 +- .../TARGET_STM32L1/device/stm32l1xx_hal_i2s.c | 6 +-- .../TARGET_STM32L1/device/stm32l1xx_hal_sd.c | 2 +- .../TARGET_STM32L1/device/stm32l1xx_ll_i2c.h | 2 +- targets/TARGET_STM/TARGET_STM32L1/flash_api.c | 2 +- .../TARGET_STM32L4/device/stm32l4xx_hal_sai.c | 2 +- .../device/stm32l4xx_ll_lptim.h | 2 +- targets/TARGET_STM/TARGET_STM32L4/flash_api.c | 2 +- .../TARGET_EFM32/serial_api.c | 4 +- .../Periph_Driver/inc/tmpm066_uart.h | 2 +- .../Periph_Driver/src/tmpm066_i2c.c | 4 +- .../Periph_Driver/src/tmpm066_uart.c | 2 +- 183 files changed, 363 insertions(+), 362 deletions(-) diff --git a/features/FEATURE_BLE/ble/BLEInstanceBase.h b/features/FEATURE_BLE/ble/BLEInstanceBase.h index 6f080c45d3..d7ff34cb71 100644 --- a/features/FEATURE_BLE/ble/BLEInstanceBase.h +++ b/features/FEATURE_BLE/ble/BLEInstanceBase.h @@ -246,7 +246,7 @@ public: private: // this class is not a value type. - // prohibit copy construction and copy assignment + // prohibit copy construction and copy assignement BLEInstanceBase(const BLEInstanceBase&); BLEInstanceBase &operator=(const BLEInstanceBase&); }; diff --git a/features/FEATURE_BLE/ble/pal/AttClient.h b/features/FEATURE_BLE/ble/pal/AttClient.h index 678f99562c..56bd1a2f06 100644 --- a/features/FEATURE_BLE/ble/pal/AttClient.h +++ b/features/FEATURE_BLE/ble/pal/AttClient.h @@ -75,7 +75,7 @@ struct AttClient { * The mtu choosen for the connection is the minimum of the client Rx mtu * and server Rx mtu values. * - * If an error occurred then the mtu used remains the default value. + * If an error occured then the mtu used remains the default value. * * @param connection The handle of the connection to send this request to. * diff --git a/features/FEATURE_BLE/ble/pal/GapEvents.h b/features/FEATURE_BLE/ble/pal/GapEvents.h index 47cc2423dc..a406d6cdcc 100644 --- a/features/FEATURE_BLE/ble/pal/GapEvents.h +++ b/features/FEATURE_BLE/ble/pal/GapEvents.h @@ -75,7 +75,7 @@ struct GapEvent { protected: GapEvent(GapEventType type) : type(type) { } - // Disable copy construction and copy assignment operations. + // Disable copy construction and copy assignement operations. GapEvent(const GapEvent&); GapEvent& operator=(const GapEvent&); }; diff --git a/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/include/wsf_buf.h b/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/include/wsf_buf.h index 6b27ca73b3..e15476ed4b 100644 --- a/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/include/wsf_buf.h +++ b/features/FEATURE_BLE/targets/TARGET_CORDIO/stack/cordio_stack/ws-core/sw/wsf/include/wsf_buf.h @@ -63,7 +63,7 @@ typedef struct /*! WSF buffer diagnostics - buffer allocation failure */ typedef struct { - uint8_t taskId; /*! Task handler ID where failure occurred */ + uint8_t taskId; /*! Task handler ID where failure occured */ uint16_t len; /*! Length of buffer being allocated */ } wsfBufDiagAllocFail_t; diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c index b810e4effd..aec280a0fb 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/hal_patch/sleep.c @@ -57,7 +57,7 @@ void hal_sleep(void) return; } else { // next event will wakeup the CPU - // If an interrupt occurred between the test of SCB->ICSR and this + // If an interrupt occured between the test of SCB->ICSR and this // instruction, WFE will just not put the CPU to sleep __WFE(); } diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/ble/peer_manager/id_manager.c b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/ble/peer_manager/id_manager.c index 436fc783d1..c2942c84cd 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/ble/peer_manager/id_manager.c +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/ble/peer_manager/id_manager.c @@ -359,7 +359,7 @@ bool is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1, /**@brief Event handler for events from the peer_database module. * - * @param[in] p_event The event that has happened with peer id and flags. + * @param[in] p_event The event that has happend with peer id and flags. */ static void pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/libraries/bootloader_dfu/dfu_types.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/libraries/bootloader_dfu/dfu_types.h index f8e8c40b6f..d26b72f7b6 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/libraries/bootloader_dfu/dfu_types.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/libraries/bootloader_dfu/dfu_types.h @@ -152,10 +152,10 @@ typedef enum typedef struct { dfu_update_status_code_t status_code; /**< Device Firmware Update status. */ - uint16_t app_crc; /**< CRC of the received application. */ - uint32_t sd_size; /**< Size of the received SoftDevice. */ - uint32_t bl_size; /**< Size of the received BootLoader. */ - uint32_t app_size; /**< Size of the received Application. */ + uint16_t app_crc; /**< CRC of the recieved application. */ + uint32_t sd_size; /**< Size of the recieved SoftDevice. */ + uint32_t bl_size; /**< Size of the recieved BootLoader. */ + uint32_t app_size; /**< Size of the recieved Application. */ uint32_t sd_image_start; /**< Location in flash where the received SoftDevice image is stored. */ } dfu_update_status_t; diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gap.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gap.h index d5943b8ee5..be91c1df8e 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gap.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gap.h @@ -721,7 +721,7 @@ typedef struct /**@brief GAP event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t conn_handle; /**< Connection Handle on which event occured. */ union /**< union alternative identified by evt_id in enclosing struct. */ { ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ @@ -1153,7 +1153,7 @@ SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::NRF_ERROR_TIMEOUT A SMP timout has occurred, and further SMP operations on this link is prohibited. + * @retval ::NRF_ERROR_TIMEOUT A SMP timout has occured, and further SMP operations on this link is prohibited. */ SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params)); diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gattc.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gattc.h index 994ea2035e..bb074ce5cb 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gattc.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_gattc.h @@ -239,7 +239,7 @@ typedef struct /**@brief GATTC event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t conn_handle; /**< Connection Handle on which event occured. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ union diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_l2cap.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_l2cap.h index f8e1e9258d..6e37a39560 100644 --- a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_l2cap.h +++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sdk/source/softdevice/s130/headers/ble_l2cap.h @@ -107,7 +107,7 @@ typedef struct /**@brief L2CAP event callback event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t conn_handle; /**< Connection Handle on which event occured. */ union { ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ diff --git a/features/FEATURE_LWIP/lwip-interface/EthernetInterface.h b/features/FEATURE_LWIP/lwip-interface/EthernetInterface.h index 5ef6843adb..61fba64cd2 100644 --- a/features/FEATURE_LWIP/lwip-interface/EthernetInterface.h +++ b/features/FEATURE_LWIP/lwip-interface/EthernetInterface.h @@ -82,21 +82,21 @@ public: /** Get the local IP address * * @return Null-terminated representation of the local IP address - * or null if no IP address has been received + * or null if no IP address has been recieved */ virtual const char *get_ip_address(); /** Get the local network mask * * @return Null-terminated representation of the local network mask - * or null if no network mask has been received + * or null if no network mask has been recieved */ virtual const char *get_netmask(); /** Get the local gateways * * @return Null-terminated representation of the local gateway - * or null if no network mask has been received + * or null if no network mask has been recieved */ virtual const char *get_gateway(); diff --git a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17xx_emac.h b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17xx_emac.h index 6e35c668a0..9979a2560c 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17xx_emac.h +++ b/features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NXP/TARGET_LPCTarget/lpc17xx_emac.h @@ -249,7 +249,7 @@ extern "C" #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */ #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */ #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */ -#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occurred */ +#define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */ #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */ #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */ #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */ @@ -373,7 +373,7 @@ extern "C" #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */ #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */ #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */ -#define EMAC_RINFO_ERR 0x80000000 /**< Error Occurred (OR of all errors) */ +#define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) @@ -395,10 +395,10 @@ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */ #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */ #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */ -#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occurred */ +#define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */ #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */ #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */ -#define EMAC_TINFO_ERR 0x80000000 /**< Error Occurred (OR of all errors) */ +#define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ #ifdef MCB_LPC_1768 /* DP83848C PHY definition ------------------------------------------------------------ */ @@ -417,7 +417,7 @@ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ -#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Ability */ +#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ #define EMAC_PHY_REG_LPNPA 0x08 @@ -504,7 +504,7 @@ EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ -#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Ability */ +#define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */ diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/CHANGELOG b/features/FEATURE_LWIP/lwip-interface/lwip/CHANGELOG index bb10408c0f..1a5e27ba8b 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/CHANGELOG +++ b/features/FEATURE_LWIP/lwip-interface/lwip/CHANGELOG @@ -3918,7 +3918,7 @@ HISTORY ++ Bug fixes: * Fixed pool pbuf memory leak in pbuf_alloc(). - Occurred if not enough PBUF_POOL pbufs for a packet pbuf chain. + Occured if not enough PBUF_POOL pbufs for a packet pbuf chain. Reported by Savin Zlobec. * PBUF_POOL chains had their tot_len field not set for non-first diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/snmp/lwip_snmp_msg.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/snmp/lwip_snmp_msg.c index f95c3b38f8..0cb7ca997c 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/snmp/lwip_snmp_msg.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/snmp/lwip_snmp_msg.c @@ -1469,7 +1469,7 @@ snmp_complete_outbound_frame(struct snmp_request *request) if (request->error_status == SNMP_ERR_TOOBIG) { request->error_index = 0; /* defined by RFC 1157 */ } else if (request->error_index == 0) { - /* set index to varbind where error occurred (if not already set before, e.g. during GetBulk processing) */ + /* set index to varbind where error occured (if not already set before, e.g. during GetBulk processing) */ request->error_index = request->inbound_varbind_enumerator.varbind_count; } } else { diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/tftp/lwip_tftp_server.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/tftp/lwip_tftp_server.c index a9d98b8cc1..243b0924bd 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/tftp/lwip_tftp_server.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/apps/tftp/lwip_tftp_server.c @@ -191,7 +191,7 @@ send_data(void) ret = tftp_state.ctx->read(tftp_state.handle, &payload[2], TFTP_MAX_PAYLOAD_SIZE); if (ret < 0) { - send_error(&tftp_state.addr, tftp_state.port, TFTP_ERROR_ACCESS_VIOLATION, "Error occurred while reading the file."); + send_error(&tftp_state.addr, tftp_state.port, TFTP_ERROR_ACCESS_VIOLATION, "Error occured while reading the file."); close_handle(); return; } diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipcp.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipcp.c index cce0ae3d7d..05108a0628 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipcp.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipcp.c @@ -1744,7 +1744,7 @@ static int ipcp_reqci(fsm *f, u_char *inp, int *len, int reject_if_disagree) { } endswitch: if (orc == CONFACK && /* Good CI */ - rc != CONFACK) /* but prior CI wasn't? */ + rc != CONFACK) /* but prior CI wasnt? */ continue; /* Don't send this one */ if (orc == CONFNAK) { /* Nak this CI? */ diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipv6cp.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipv6cp.c index f34375b498..f1592c6faf 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipv6cp.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_ipv6cp.c @@ -1011,7 +1011,7 @@ endswitch: IPV6CPDEBUG((" (%s)\n", CODENAME(orc))); if (orc == CONFACK && /* Good CI */ - rc != CONFACK) /* but prior CI wasn't? */ + rc != CONFACK) /* but prior CI wasnt? */ continue; /* Don't send this one */ if (orc == CONFNAK) { /* Nak this CI? */ diff --git a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_lcp.c b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_lcp.c index fe050b4bc1..90ed183b75 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_lcp.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip/src/netif/ppp/lwip_lcp.c @@ -2232,7 +2232,7 @@ static int lcp_reqci(fsm *f, u_char *inp, int *lenp, int reject_if_disagree) { endswitch: if (orc == CONFACK && /* Good CI */ - rc != CONFACK) /* but prior CI wasn't? */ + rc != CONFACK) /* but prior CI wasnt? */ continue; /* Don't send this one */ if (orc == CONFNAK) { /* Nak this CI? */ diff --git a/features/filesystem/fat/ChaN/ff.cpp b/features/filesystem/fat/ChaN/ff.cpp index ea827af866..cc04154a30 100644 --- a/features/filesystem/fat/ChaN/ff.cpp +++ b/features/filesystem/fat/ChaN/ff.cpp @@ -3299,7 +3299,7 @@ FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */ fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */ } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4); } - if (fmt == 4) return FR_DISK_ERR; /* An error occurred in the disk I/O layer */ + if (fmt == 4) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */ /* An FAT volume is found (bsect). Following code initializes the filesystem object */ diff --git a/features/lorawan/LoRaWANStack.cpp b/features/lorawan/LoRaWANStack.cpp index f2c4be02f7..418322ed14 100644 --- a/features/lorawan/LoRaWANStack.cpp +++ b/features/lorawan/LoRaWANStack.cpp @@ -860,7 +860,7 @@ void LoRaWANStack::mcps_confirm_handler(loramac_mcps_confirm_t *mcps_confirm) } if (mcps_confirm->status != LORAMAC_EVENT_INFO_STATUS_OK) { - // Couldn't schedule packet, ack not received in CONFIRMED case + // Couldn't schedule packet, ack not recieved in CONFIRMED case // or some other error happened. Discard buffer, unset the tx-ongoing // flag and let the application know _tx_msg.tx_ongoing = false; diff --git a/features/mbedtls/inc/mbedtls/bignum.h b/features/mbedtls/inc/mbedtls/bignum.h index c5730db628..3bf02a7ee1 100644 --- a/features/mbedtls/inc/mbedtls/bignum.h +++ b/features/mbedtls/inc/mbedtls/bignum.h @@ -243,7 +243,7 @@ int mbedtls_mpi_copy( mbedtls_mpi *X, const mbedtls_mpi *Y ); void mbedtls_mpi_swap( mbedtls_mpi *X, mbedtls_mpi *Y ); /** - * \brief Safe conditional assignment X = Y if assign is 1 + * \brief Safe conditional assignement X = Y if assign is 1 * * \param X MPI to conditionally assign to * \param Y Value to be assigned diff --git a/features/mbedtls/inc/mbedtls/x509.h b/features/mbedtls/inc/mbedtls/x509.h index 2a3d7eca9a..d6db9c6e37 100644 --- a/features/mbedtls/inc/mbedtls/x509.h +++ b/features/mbedtls/inc/mbedtls/x509.h @@ -77,7 +77,7 @@ #define MBEDTLS_ERR_X509_ALLOC_FAILED -0x2880 /**< Allocation of memory failed. */ #define MBEDTLS_ERR_X509_FILE_IO_ERROR -0x2900 /**< Read/write of file failed. */ #define MBEDTLS_ERR_X509_BUFFER_TOO_SMALL -0x2980 /**< Destination buffer is too small. */ -#define MBEDTLS_ERR_X509_FATAL_ERROR -0x3000 /**< A fatal error occurred, eg the chain is too long or the vrfy callback failed. */ +#define MBEDTLS_ERR_X509_FATAL_ERROR -0x3000 /**< A fatal error occured, eg the chain is too long or the vrfy callback failed. */ /* \} name */ /** @@ -250,7 +250,7 @@ int mbedtls_x509_serial_gets( char *buf, size_t size, const mbedtls_x509_buf *se * * \param to mbedtls_x509_time to check * - * \return 1 if the given time is in the past or an error occurred, + * \return 1 if the given time is in the past or an error occured, * 0 otherwise. */ int mbedtls_x509_time_is_past( const mbedtls_x509_time *to ); @@ -264,7 +264,7 @@ int mbedtls_x509_time_is_past( const mbedtls_x509_time *to ); * * \param from mbedtls_x509_time to check * - * \return 1 if the given time is in the future or an error occurred, + * \return 1 if the given time is in the future or an error occured, * 0 otherwise. */ int mbedtls_x509_time_is_future( const mbedtls_x509_time *from ); diff --git a/features/mbedtls/src/ecp.c b/features/mbedtls/src/ecp.c index 40e52591b9..b41baef27a 100644 --- a/features/mbedtls/src/ecp.c +++ b/features/mbedtls/src/ecp.c @@ -1470,7 +1470,7 @@ cleanup: /* * For Montgomery curves, we do all the internal arithmetic in projective * coordinates. Import/export of points uses only the x coordinates, which is - * internally represented as X / Z. + * internaly represented as X / Z. * * For scalar multiplication, we'll use a Montgomery ladder. */ diff --git a/features/mbedtls/src/error.c b/features/mbedtls/src/error.c index 5a18477627..0292480aee 100644 --- a/features/mbedtls/src/error.c +++ b/features/mbedtls/src/error.c @@ -533,7 +533,7 @@ void mbedtls_strerror( int ret, char *buf, size_t buflen ) if( use_ret == -(MBEDTLS_ERR_X509_BUFFER_TOO_SMALL) ) mbedtls_snprintf( buf, buflen, "X509 - Destination buffer is too small" ); if( use_ret == -(MBEDTLS_ERR_X509_FATAL_ERROR) ) - mbedtls_snprintf( buf, buflen, "X509 - A fatal error occurred, eg the chain is too long or the vrfy callback failed" ); + mbedtls_snprintf( buf, buflen, "X509 - A fatal error occured, eg the chain is too long or the vrfy callback failed" ); #endif /* MBEDTLS_X509_USE_C || MBEDTLS_X509_CREATE_C */ // END generated code diff --git a/features/mbedtls/targets/TARGET_STM/aes_alt.h b/features/mbedtls/targets/TARGET_STM/aes_alt.h index 7eadcb1e6a..120c9af5f1 100644 --- a/features/mbedtls/targets/TARGET_STM/aes_alt.h +++ b/features/mbedtls/targets/TARGET_STM/aes_alt.h @@ -32,7 +32,7 @@ extern "C" { #endif #define ST_AES_TIMEOUT ((uint32_t) 0xFF) /* 255 ms timeout for the crypto processor */ -#define ST_ERR_AES_BUSY (-0x0023) /* Crypto processor is busy, timeout occurred */ +#define ST_ERR_AES_BUSY (-0x0023) /* Crypto processor is busy, timeout occured */ /** * \brief AES context structure * diff --git a/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.h b/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.h index 8259984cab..453efa14ae 100644 --- a/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.h +++ b/features/nanostack/FEATURE_NANOSTACK/nanostack-interface/NanostackInterface.h @@ -68,7 +68,7 @@ protected: /** Bind a specific address to a socket * - * Binding a socket specifies the address and port on which to receive + * Binding a socket specifies the address and port on which to recieve * data. If the IP address is zeroed, only the port is bound. * * @param handle Socket handle diff --git a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_dhcpv6_client.c b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_dhcpv6_client.c index dd83e45c50..7005b52336 100644 --- a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_dhcpv6_client.c +++ b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_dhcpv6_client.c @@ -60,7 +60,7 @@ void thread_dhcpv6_client_set_address(int8_t interface_id, dhcpv6_client_server_ void thread_dhcp_client_init(int8_t interface) { - // No support for multiple thread instances yet. + // No support for multible thread instances yet. dhcp_client.service_instance = dhcp_service_init(interface, DHCP_INSTANCE_CLIENT, NULL); dhcp_client.interface = interface; dhcp_client.libDhcp_instance = libdhcpv6_nonTemporal_entry_get_unique_instance_id(); diff --git a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_management_server.c b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_management_server.c index d98ab2f4a4..329c26c14a 100644 --- a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_management_server.c +++ b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/6LoWPAN/Thread/thread_management_server.c @@ -552,7 +552,7 @@ static uint32_t reverse_bits(uint32_t num) } static void thread_panid_scan_response(int8_t if_id, const mlme_scan_conf_t* conf) { - bool conflict_occurred = false; + bool conflict_occured = false; nwk_scan_params_t *scan_parameters_ptr; nwk_pan_descriptor_t *result; protocol_interface_info_entry_t *interface; @@ -599,12 +599,12 @@ static void thread_panid_scan_response(int8_t if_id, const mlme_scan_conf_t* con if(result->pan_descriptor->CoordPANId == this->scan_ptr->panid) { //if pan id matches then send a conflict message tr_debug("Same pan id was found on channel %d", result->pan_descriptor->LogicalChannel); set_channel_mask(this->scan_ptr->channel_mask,result->pan_descriptor->LogicalChannel,0); - conflict_occurred = true; + conflict_occured = true; } result = result->next; } while (result); - if (conflict_occurred){ - tr_debug("conflict occurred"); + if (conflict_occured){ + tr_debug("conflict occured"); this->scan_ptr->timer = eventOS_timeout_ms(thread_panid_conflict_timeout_cb, 2000, this); } thread_start_mac_with_link_configuration(interface,linkConfiguration); diff --git a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h index c154f6295b..d037c6b83d 100644 --- a/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h +++ b/features/nanostack/FEATURE_NANOSTACK/sal-stack-nanostack/source/Service_Libs/mdns/fnet/fnet_stack/services/dns/fnet_dns.h @@ -122,7 +122,7 @@ struct fnet_dns_params fnet_address_family_t addr_family; /**< @brief Family of the IP Address which is queried.*/ fnet_dns_callback_resolved_t callback; /**< @brief Pointer to the callback function defined by * @ref fnet_dns_callback_resolved_t. It is called when the - * DNS-client resolving is finished or an error has occurred. */ + * DNS-client resolving is finished or an error is occurred. */ fnet_uint32_t cookie; /**< @brief Optional application-specific parameter. @n * It's passed to the @c callback * function as input parameter. */ @@ -155,7 +155,7 @@ extern "C" { * The resolved IP-address will be passed to the @ref fnet_dns_callback_resolved_t callback function, * which is set in @c params. @n * The DNS service is released automatically as soon as the - * resolving is finished or an error has occurred. + * resolving is finished or an error is occurred. * ******************************************************************************/ fnet_return_t fnet_dns_init( struct fnet_dns_params *params ); diff --git a/features/unsupported/USBDevice/USBMSD/USBMSD.cpp b/features/unsupported/USBDevice/USBMSD/USBMSD.cpp index a45c893c52..21d50f9b9f 100644 --- a/features/unsupported/USBDevice/USBMSD/USBMSD.cpp +++ b/features/unsupported/USBDevice/USBMSD/USBMSD.cpp @@ -170,7 +170,7 @@ bool USBMSD::EPBULK_OUT_callback() { } break; - // an error has occurred: stall endpoint and send CSW + // an error has occured: stall endpoint and send CSW default: stallEndpoint(EPBULK_OUT); csw.Status = CSW_ERROR; @@ -207,7 +207,7 @@ bool USBMSD::EPBULK_IN_callback() { stage = READ_CBW; break; - // an error has occurred + // an error has occured default: stallEndpoint(EPBULK_IN); sendCSW(); diff --git a/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdep.c b/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdep.c index 3846eb3d20..2017edaf97 100644 --- a/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdep.c +++ b/features/unsupported/USBDevice/targets/TARGET_Silicon_Labs/src/em_usbdep.c @@ -40,7 +40,7 @@ static const char *epStatusStr[] = { /* * USBDEP_Ep0Handler() is called each time a packet has been transmitted - * or received on the default endpoint. + * or recieved on the default endpoint. * A state machine navigate us through the phases of a control transfer * according to "chapter 9" in the USB spec. */ @@ -417,7 +417,7 @@ void USBDEP_Ep0Handler( USBD_Device_TypeDef *device ) /* * USBDEP_EpHandler() is called each time a packet has been transmitted - * or received on an endpoint other than the default endpoint. + * or recieved on an endpoint other than the default endpoint. */ void USBDEP_EpHandler( uint8_t epAddr ) { diff --git a/features/unsupported/tests/libs/SPIHalfDuplex/SPIHalfDuplex.h b/features/unsupported/tests/libs/SPIHalfDuplex/SPIHalfDuplex.h index d012d7b946..14633b8555 100644 --- a/features/unsupported/tests/libs/SPIHalfDuplex/SPIHalfDuplex.h +++ b/features/unsupported/tests/libs/SPIHalfDuplex/SPIHalfDuplex.h @@ -48,7 +48,7 @@ public: * Pin Options: * (5, 6, 7) or (11, 12, 13) * - * mosi or miso can be specified as NC if not used + * mosi or miso can be specfied as NC if not used * * @param mosi SPI Master Out, Slave In pin * @param miso SPI Master In, Slave Out pin diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c index 2460a3741a..d9755dfb33 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/ethernet_api.c @@ -58,11 +58,11 @@ int ethernet_receive() return smsc9220_peek_next_packet_size(); } -/* Read from an received ethernet packet.*/ -/* After receive returned a number bigger than 0 it is*/ +/* Read from an recevied ethernet packet.*/ +/* After receive returnd a number bigger than 0 it is*/ /* possible to read bytes from this packet.*/ /* Read will write up to size bytes into data.*/ -/* It is possible to use read multiple times.*/ +/* It is possible to use read multible times.*/ /* Each time read will start reading after the last read byte before. */ int ethernet_read(char *data, int dlen) { diff --git a/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c b/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c index 036ee32578..2e20cb7113 100644 --- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c +++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/ETH_MPS2.c @@ -375,7 +375,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index) if(rxfifo_stat != 0) { // Fetch status of this packet pktsize = ((rxfifo_stat >> 16) & 0x3FFF); if(rxfifo_stat & (1 << 15)) { - printf("Error occurred during receiving of packets on the bus.\n"); + printf("Error occured during receiving of packets on the bus.\n"); return 1; } else { /* Below formula (recommended by SMSC9220 code) diff --git a/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h b/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h index 913191435d..2a15b24a6c 100644 --- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h +++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/SDK/mps2_ethernet_api.h @@ -30,7 +30,7 @@ extern "C" { // send ethernet write buffer, returning the packet size sent int ethernet_transmission(unsigned char * pkt, unsigned int length); -// receive from ethernet buffer, returning packet size, or 0 if no packet +// recieve from ethernet buffer, returning packet size, or 0 if no packet int ethernet_reception(unsigned int *recvbuf, unsigned int *index); // get the ethernet address diff --git a/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c b/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c index 360997c5dd..78469a645f 100644 --- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/ethernet_api.c @@ -136,11 +136,11 @@ int ethernet_receive() return 0; } -// Read from an received ethernet packet. -// After receive returned a number bigger than 0 it is +// Read from an recevied ethernet packet. +// After receive returnd a number bigger than 0 it is // possible to read bytes from this packet. // Read will write up to size bytes into data. -// It is possible to use read multiple times. +// It is possible to use read multible times. // Each time read will start reading after the last read byte before. int ethernet_read(char *data, int dlen) diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c b/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c index 045cc07bc4..3910871cd9 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/ETH_MPS2.c @@ -375,7 +375,7 @@ unsigned int smsc9220_recv_packet(unsigned int *recvbuf, unsigned int *index) if(rxfifo_stat != 0) { // Fetch status of this packet pktsize = ((rxfifo_stat >> 16) & 0x3FFF); if(rxfifo_stat & (1 << 15)) { - printf("Error occurred during receiving of packets on the bus.\n"); + printf("Error occured during receiving of packets on the bus.\n"); return 1; } else { /* Below formula (recommended by SMSC9220 code) diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h b/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h index 913191435d..2a15b24a6c 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/SDK/mps2_ethernet_api.h @@ -30,7 +30,7 @@ extern "C" { // send ethernet write buffer, returning the packet size sent int ethernet_transmission(unsigned char * pkt, unsigned int length); -// receive from ethernet buffer, returning packet size, or 0 if no packet +// recieve from ethernet buffer, returning packet size, or 0 if no packet int ethernet_reception(unsigned int *recvbuf, unsigned int *index); // get the ethernet address diff --git a/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c b/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c index 360997c5dd..78469a645f 100644 --- a/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/ethernet_api.c @@ -136,11 +136,11 @@ int ethernet_receive() return 0; } -// Read from an received ethernet packet. -// After receive returned a number bigger than 0 it is +// Read from an recevied ethernet packet. +// After receive returnd a number bigger than 0 it is // possible to read bytes from this packet. // Read will write up to size bytes into data. -// It is possible to use read multiple times. +// It is possible to use read multible times. // Each time read will start reading after the last read byte before. int ethernet_read(char *data, int dlen) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c index 17411e72f8..dbecf7a149 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/spi_api.c @@ -327,7 +327,7 @@ int spi_master_write(spi_t *obj, int value) /** Write a block out in master mode and receive a value * - * The total number of bytes sent and received will be the maximum of + * The total number of bytes sent and recieved will be the maximum of * tx_length and rx_length. The bytes written will be padded with the * value 0xff. * diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c index 0882cbae8b..9e889131ca 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/tmr/adi_tmr.c @@ -303,7 +303,7 @@ ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG* * * @details The timer can be configured to capture the timer value when a specific event occurs. The * list of events can be found in the hardware reference manual. The callback function specified - * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occurred. The + * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The * user can then read the captured value by calling #adi_tmr_GetCaptureCount. * * @note This function can only be called when the timer is disabled. diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c index 5c7a020447..f0dc346bfa 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/bsp/uart/adi_uart.c @@ -1814,7 +1814,7 @@ ADI_UART_RESULT adi_uart_GetBaudRate( #endif /* ADI_DEBUG */ - /* If an error occurred during autobaud this value will be set to a + /* If an error occured during autobaud this value will be set to a non-zero value. The specific error can be found by checking against #ADI_UART_EVENT. */ diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c index 74ef22135a..7f9fd048c5 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/spi_api.c @@ -302,7 +302,7 @@ int spi_master_write(spi_t *obj, int value) /** Write a block out in master mode and receive a value * - * The total number of bytes sent and received will be the maximum of + * The total number of bytes sent and recieved will be the maximum of * tx_length and rx_length. The bytes written will be padded with the * value 0xff. * diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c index 505daff976..b7153b79a8 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr.c @@ -284,7 +284,7 @@ ADI_TMR_RESULT adi_tmr_ConfigTimer(ADI_TMR_DEVICE const eDevice, ADI_TMR_CONFIG * * @details The timer can be configured to capture the timer value when a specific event occurs. The * list of events can be found in the hardware reference manual. The callback function specified - * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occurred. The + * in #adi_tmr_Init will be supplied #ADI_TMR_EVENT_CAPTURE to indicate the event occured. The * user can then read the captured value by calling #adi_tmr_GetCaptureCount. * * @note This function can only be called when the timer is disabled. diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c index a511985c6c..d1f72d6048 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/uart/adi_uart.c @@ -1808,7 +1808,7 @@ ADI_UART_RESULT adi_uart_GetBaudRate( #endif /* ADI_DEBUG */ - /* If an error occurred during autobaud this value will be set to a + /* If an error occured during autobaud this value will be set to a non-zero value. The specific error can be found by checking against #ADI_UART_EVENT. */ diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c index 1038c22038..68e9defcc3 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.c @@ -1354,10 +1354,10 @@ enum status_code tcc_set_pattern( * * \return Bitmask of \c TCC_STATUS_* flags. * - * \retval TCC_STATUS_CHANNEL_MATCH_CAPTURE(n) Channel n match/capture has occurred + * \retval TCC_STATUS_CHANNEL_MATCH_CAPTURE(n) Channel n match/capture has occured * \retval TCC_STATUS_CHANNEL_OUTPUT(n) Channel n match/capture output state - * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) Non-recoverable fault x has occurred - * \retval TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) Recoverable fault n has occurred + * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) Non-recoverable fault x has occured + * \retval TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) Recoverable fault n has occured * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) Non-recoverable fault x input present * \retval TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n) Recoverable fault n input present * \retval TCC_STATUS_SYNC_READY None of register is syncing diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h index 7a53cc60a5..ec409a340d 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/tcc/tcc.h @@ -852,7 +852,7 @@ enum tcc_callback { #define TCC_STATUS_CHANNEL_OUTPUT(ch) (1UL << ((ch)+8)) /** A Non-Recoverable Fault \c x (0 ~ 1) has occurred. */ #define TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) (1UL << ((x)+16)) -/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) has occurred. */ +/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) has occured. */ #define TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) (1UL << ((n)+18)) /** The Non-Recoverable Fault \c x (0 ~ 1) input is present. */ #define TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) (1UL << ((x)+20)) diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c index 8fed98d48d..2ca86a6b63 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/serial_api.c @@ -1024,7 +1024,7 @@ int serial_rx_irq_handler_asynch(serial_t *obj) event |= SERIAL_EVENT_RX_CHARACTER_MATCH; } - /* Return to the call back if character match occurred */ + /* Return to the call back if character match occured */ if(event != 0) { serial_rx_abort_asynch(obj); return event & obj->serial.events; diff --git a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h index f076cf2073..987762aa64 100644 --- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/utils/cmsis/TARGET_SAMG55/include/component/comp_rstc.h @@ -75,7 +75,7 @@ typedef struct { #define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ #define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ #define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ -#define RSTC_SR_RSTTYP_SLCK_XTAL_RST (0x7u << 8) /**< \brief (RSTC_SR) Slow Crystal Failure Detection fault occurred */ +#define RSTC_SR_RSTTYP_SLCK_XTAL_RST (0x7u << 8) /**< \brief (RSTC_SR) Slow Crystal Failure Detection fault occured */ #define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ #define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h index 1d19e01f72..118badf58f 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_flexcan.h @@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable * * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to - * read FlEXCAN_ErrorFlag and distinguish which error has occurred using + * read FlEXCAN_ErrorFlag and distinguish which error is occur using * @ref _flexcan_error_flags enumerations. */ enum _flexcan_flags diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c index 57b8dbb499..73ea64fa4e 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occurred. */ + kSAI_Error /*!< Transfer error occured. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c index db7a8e891a..748a1e7167 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_qspi.c @@ -37,7 +37,7 @@ enum _qspi_transfer_state { kQSPI_TxBusy = 0x0U, /*!< QSPI is busy */ kQSPI_TxIdle, /*!< Transfer is done. */ - kQSPI_TxError /*!< Transfer error occurred. */ + kQSPI_TxError /*!< Transfer error occured. */ }; #define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index)) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sai.c index 97620fb6ad..0d19d09e7a 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occurred. */ + kSAI_Error /*!< Transfer error occured. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c index 99f67b36a7..959fb6050c 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/drivers/fsl_trng.c @@ -1173,7 +1173,7 @@ typedef enum _trng_statistical_check * TRNG access mode in the SA-TRNG Miscellaneous Control Register. * * Values: - * - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous + * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous * Control Register's access mode bit. * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * TRNG register programming. diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai.c index 9c8aab085d..c38165ec04 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occurred. */ + kSAI_Error /*!< Transfer error occured. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai_dma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai_dma.h index d5f55559f0..9606afcfdf 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai_dma.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/drivers/fsl_sai_dma.h @@ -56,7 +56,7 @@ struct _sai_dma_handle uint8_t bytesPerFrame; /*!< Bytes in a frame */ uint8_t channel; /*!< Which Data channel SAI use */ uint32_t state; /*!< SAI DMA transfer internal state */ - sai_dma_callback_t callback; /*!< Callback for users while transfer finish or error occurred */ + sai_dma_callback_t callback; /*!< Callback for users while transfer finish or error occured */ void *userData; /*!< User callback parameter */ sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */ size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c index 2b23c1a11a..00f511cd73 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_qspi.c @@ -37,7 +37,7 @@ enum _qspi_transfer_state { kQSPI_TxBusy = 0x0U, /*!< QSPI is busy */ kQSPI_TxIdle, /*!< Transfer is done. */ - kQSPI_TxError /*!< Transfer error occurred. */ + kQSPI_TxError /*!< Transfer error occured. */ }; #define QSPI_AHB_BUFFER_REG(base, index) (*((uint32_t *)&(base->BUF0CR) + index)) diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_trng.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_trng.c index d084fc1a58..a5fd937dcd 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_trng.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_trng.c @@ -1173,7 +1173,7 @@ typedef enum _trng_statistical_check * TRNG access mode in the SA-TRNG Miscellaneous Control Register. * * Values: - * - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous + * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous * Control Register's access mode bit. * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * TRNG register programming. diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c index 9c8aab085d..c38165ec04 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occurred. */ + kSAI_Error /*!< Transfer error occured. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_trng.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_trng.c index d084fc1a58..a5fd937dcd 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_trng.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/drivers/fsl_trng.c @@ -1173,7 +1173,7 @@ typedef enum _trng_statistical_check * TRNG access mode in the SA-TRNG Miscellaneous Control Register. * * Values: - * - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous + * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous * Control Register's access mode bit. * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * TRNG register programming. diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_sai.c index 9c8aab085d..c38165ec04 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occurred. */ + kSAI_Error /*!< Transfer error occured. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h index 1d19e01f72..118badf58f 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_flexcan.h @@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable * * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to - * read FlEXCAN_ErrorFlag and distinguish which error has occurred using + * read FlEXCAN_ErrorFlag and distinguish which error is occur using * @ref _flexcan_error_flags enumerations. */ enum _flexcan_flags diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c index 57b8dbb499..73ea64fa4e 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occurred. */ + kSAI_Error /*!< Transfer error occured. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h index 1b060f31ef..bafc4450ac 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_flexcan.h @@ -227,7 +227,7 @@ enum _flexcan_interrupt_enable * * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to - * read FlEXCAN_ErrorFlag and distinguish which error has occurred using + * read FlEXCAN_ErrorFlag and distinguish which error is occur using * @ref _flexcan_error_flags enumerations. */ enum _flexcan_flags diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c index 97620fb6ad..0d19d09e7a 100644 --- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occurred. */ + kSAI_Error /*!< Transfer error occured. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32625/mxc/tmr_utils.h b/targets/TARGET_Maxim/TARGET_MAX32625/mxc/tmr_utils.h index 14f1aab224..a6712372ba 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32625/mxc/tmr_utils.h +++ b/targets/TARGET_Maxim/TARGET_MAX32625/mxc/tmr_utils.h @@ -75,7 +75,7 @@ void TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us); void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us); /** - * @brief Check if the timeout has occurred. + * @brief Check if the timeout has occured. * @param tmr TMR module to operate on * @returns E_NO_ERROR if the timeout has not occurred, E_TIME_OUT if it has. */ diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h index f81510af91..70e452d1ca 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/aes.h @@ -129,7 +129,7 @@ int AES_SetKey(const uint8_t *key, mxc_aes_mode_t mode); * @param dir Operation to perform, see #mxc_aes_dir_t for supported operations. * * @return #E_SUCCESS Operation completed successfully, output data is stored in @a *out. - * @return ErrorCode An @ref MXC_Error_Codes "Error Code" if an error occurred. + * @return ErrorCode An @ref MXC_Error_Codes "Error Code" if an error occured. */ int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_t dir); @@ -143,7 +143,7 @@ int AES_ECBOp(const uint8_t *in, uint8_t *out, mxc_aes_mode_t mode, mxc_aes_dir_ * @return #E_SUCCESS Output data was written to the location pointed * to by @a *out. * @return A @ref MXC_Error_Codes "Error Code" indicating the error that - * occurred. + * occured. */ int AES_GetOutput(uint8_t *out); diff --git a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h index 19c92ae994..c401ff04ed 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h +++ b/targets/TARGET_Maxim/TARGET_MAX32630/mxc/tmr_utils.h @@ -83,7 +83,7 @@ void TMR_Delay(mxc_tmr_regs_t* tmr, unsigned long us); void TMR_TO_Start(mxc_tmr_regs_t* tmr, unsigned long us); /** - * @brief Check if the timeout has occurred. + * @brief Check if the timeout has occured. * @param tmr TMR module to operate on * @return #E_NO_ERROR if the timeout has not occurred, #E_TIME_OUT if it has. */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h index 634da43bcb..5aa20fe430 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h @@ -283,7 +283,7 @@ typedef struct /**@brief GATTC event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t conn_handle; /**< Connection Handle on which event occured. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ union diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h index e3fb2177cf..57d3592969 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h @@ -119,7 +119,7 @@ typedef struct /**@brief L2CAP event callback event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t conn_handle; /**< Connection Handle on which event occured. */ union { ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h index 634da43bcb..5aa20fe430 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h @@ -283,7 +283,7 @@ typedef struct /**@brief GATTC event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t conn_handle; /**< Connection Handle on which event occured. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ union diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h index e3fb2177cf..57d3592969 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h @@ -119,7 +119,7 @@ typedef struct /**@brief L2CAP event callback event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t conn_handle; /**< Connection Handle on which event occured. */ union { ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h index 62175952d5..eb1f7753d7 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_gattc.h @@ -301,7 +301,7 @@ typedef struct /**@brief GATTC event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t conn_handle; /**< Connection Handle on which event occured. */ uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ union diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h index bb980764d9..d3cc747b10 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/sdk/softdevice/s140/headers/nrf_ble_l2cap.h @@ -118,7 +118,7 @@ typedef struct /**@brief L2CAP event callback event structure. */ typedef struct { - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ + uint16_t conn_handle; /**< Connection Handle on which event occured. */ union { ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h index a685ad163e..ab121c2b3c 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/ble_error_log/ble_error_log.h @@ -62,7 +62,7 @@ /**@brief Error Log Data structure. * * @details The structure contains the error, message/filename, line number as well as the current - * stack, at the time where an error occurred. + * stack, at the time where an error occured. */ typedef struct { @@ -82,8 +82,8 @@ typedef struct * * @param[in] err_code Error code to be logged. * @param[in] p_message Message to be written to the flash together with stack dump, usually - * the file name where the error occurred. - * @param[in] line_number Line number where the error occurred. + * the file name where the error occured. + * @param[in] line_number Line number where the error occured. * * @return NRF_SUCCESS on successful writing of the error log. * diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c index d02d0a350f..e6b5469b41 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gattc_cache_manager.c @@ -67,7 +67,7 @@ static void internal_state_reset(gccm_t * gccm) /**@brief Event handler for events from the peer_database module. * - * @param[in] p_event The event that has happened with peer id and flags. + * @param[in] p_event The event that has happend with peer id and flags. */ static void pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c index 25e5e7f402..8cbca8e3f1 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/gatts_cache_manager.c @@ -116,7 +116,7 @@ static void service_changed_pending_set(void) /**@brief Event handler for events from the peer_database module. * - * @param[in] p_event The event that has happened with peer id and flags. + * @param[in] p_event The event that has happend with peer id and flags. */ static void pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c index 38f20660a3..94bc363ef6 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/ble/peer_manager/id_manager.c @@ -351,7 +351,7 @@ bool is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1, /**@brief Event handler for events from the peer_database module. * - * @param[in] p_event The event that has happened with peer id and flags. + * @param[in] p_event The event that has happend with peer id and flags. */ static void pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h index 6c4287f595..c7802c46a3 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/device/nrf52_bitfields.h @@ -13385,8 +13385,8 @@ /* Bit 0 : Overrun error */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occurred */ -#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occurred */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ /* Register: TWI_ENABLE */ /* Description: Enable TWI */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h index e78723e739..7a7421d878 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/libraries/bootloader_dfu/dfu_types.h @@ -180,10 +180,10 @@ typedef enum typedef struct { dfu_update_status_code_t status_code; /**< Device Firmware Update status. */ - uint16_t app_crc; /**< CRC of the received application. */ - uint32_t sd_size; /**< Size of the received SoftDevice. */ - uint32_t bl_size; /**< Size of the received BootLoader. */ - uint32_t app_size; /**< Size of the received Application. */ + uint16_t app_crc; /**< CRC of the recieved application. */ + uint32_t sd_size; /**< Size of the recieved SoftDevice. */ + uint32_t bl_size; /**< Size of the recieved BootLoader. */ + uint32_t app_size; /**< Size of the recieved Application. */ uint32_t sd_image_start; /**< Location in flash where the received SoftDevice image is stored. */ } dfu_update_status_t; diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h index 0b8e540d59..9a7556f983 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/ble_error_log/ble_error_log.h @@ -65,7 +65,7 @@ extern "C" { /**@brief Error Log Data structure. * * @details The structure contains the error, message/filename, line number as well as the current - * stack, at the time where an error occurred. + * stack, at the time where an error occured. */ typedef struct { @@ -85,8 +85,8 @@ typedef struct * * @param[in] err_code Error code to be logged. * @param[in] p_message Message to be written to the flash together with stack dump, usually - * the file name where the error occurred. - * @param[in] line_number Line number where the error occurred. + * the file name where the error occured. + * @param[in] line_number Line number where the error occured. * * @return NRF_SUCCESS on successful writing of the error log. * diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c index 3aba5f7a76..3f4ac47060 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/gatts_cache_manager.c @@ -126,7 +126,7 @@ static void service_changed_pending_set(void) /**@brief Event handler for events from the Peer Database module. * This function is extern in Peer Database. * - * @param[in] p_event The event that has happened with peer id and flags. + * @param[in] p_event The event that has happend with peer id and flags. */ void gscm_pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c index fa565c8520..03cf432591 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/ble/peer_manager/id_manager.c @@ -365,7 +365,7 @@ bool im_is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1 /**@brief Event handler for events from the Peer Database module. * This function is extern in Peer Database. * - * @param[in] p_event The event that has happened with peer id and flags. + * @param[in] p_event The event that has happend with peer id and flags. */ void im_pdb_evt_handler(pdb_evt_t const * p_event) { diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h index ac856b8628..3c71d50578 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52840_bitfields.h @@ -11762,8 +11762,8 @@ /* Bit 0 : Overrun error */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occurred */ -#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occurred */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ /* Register: TWI_ENABLE */ /* Description: Enable TWI */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h index c6fa759ecb..9debbb6a26 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK13/device/nrf52_bitfields.h @@ -11114,8 +11114,8 @@ /* Bit 0 : Overrun error */ #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occurred */ -#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occurred */ +#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ +#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */ /* Register: TWI_ENABLE */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c b/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c index 38dea91aa1..0835c51765 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/serial_api.c @@ -112,7 +112,7 @@ typedef struct { void (*tx_asynch_handler)(); uint32_t events_wanted; - uint32_t events_occurred; + uint32_t events_occured; #define UART_IRQ_TX 1 #define UART_IRQ_RX 2 @@ -165,13 +165,13 @@ void UART_IRQ_HANDLER(void) if (UART_CB.char_match != SERIAL_RESERVED_CHAR_MATCH && rx_data == UART_CB.char_match) { // If it does, report the match and abort further receiving. - UART_CB.events_occurred |= SERIAL_EVENT_RX_CHARACTER_MATCH; + UART_CB.events_occured |= SERIAL_EVENT_RX_CHARACTER_MATCH; if (UART_CB.events_wanted & SERIAL_EVENT_RX_CHARACTER_MATCH) { end_rx = true; } } if (++UART_CB.rx_pos >= UART_CB.rx_length) { - UART_CB.events_occurred |= SERIAL_EVENT_RX_COMPLETE; + UART_CB.events_occured |= SERIAL_EVENT_RX_COMPLETE; end_rx = true; } if (end_rx) { @@ -215,7 +215,7 @@ void UART_IRQ_HANDLER(void) // 'serial_writable' function to work properly. end_asynch_tx(); - UART_CB.events_occurred |= SERIAL_EVENT_TX_COMPLETE; + UART_CB.events_occured |= SERIAL_EVENT_TX_COMPLETE; if (UART_CB.tx_asynch_handler) { // Use local variable to make it possible to start a next // transfer from callback routine. @@ -239,15 +239,15 @@ void UART_IRQ_HANDLER(void) uint8_t errorsrc = nrf_uart_errorsrc_get_and_clear(UART_INSTANCE); if (UART_CB.rx_asynch_handler) { - UART_CB.events_occurred |= SERIAL_EVENT_ERROR; + UART_CB.events_occured |= SERIAL_EVENT_ERROR; if (errorsrc & NRF_UART_ERROR_PARITY_MASK) { - UART_CB.events_occurred |= SERIAL_EVENT_RX_PARITY_ERROR; + UART_CB.events_occured |= SERIAL_EVENT_RX_PARITY_ERROR; } if (errorsrc & NRF_UART_ERROR_FRAMING_MASK) { - UART_CB.events_occurred |= SERIAL_EVENT_RX_FRAMING_ERROR; + UART_CB.events_occured |= SERIAL_EVENT_RX_FRAMING_ERROR; } if (errorsrc & NRF_UART_ERROR_OVERRUN_MASK) { - UART_CB.events_occurred |= SERIAL_EVENT_RX_OVERRUN_ERROR; + UART_CB.events_occured |= SERIAL_EVENT_RX_OVERRUN_ERROR; } UART_CB.rx_asynch_handler(); } @@ -641,8 +641,8 @@ uint8_t serial_rx_active(serial_t *obj) int serial_irq_handler_asynch(serial_t *obj) { (void)obj; - uint32_t events_to_report = UART_CB.events_wanted & UART_CB.events_occurred; - UART_CB.events_occurred &= (~events_to_report); + uint32_t events_to_report = UART_CB.events_wanted & UART_CB.events_occured; + UART_CB.events_occured &= (~events_to_report); return events_to_report; } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c b/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c index 7bb2d85f4c..f806e7a0a6 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c +++ b/targets/TARGET_NORDIC/TARGET_NRF5/sleep.c @@ -66,7 +66,7 @@ void hal_sleep(void) return; } else { // next event will wakeup the CPU - // If an interrupt occurred between the test of SCB->ICSR and this + // If an interrupt occured between the test of SCB->ICSR and this // instruction, WFE will just not put the CPU to sleep __WFE(); } diff --git a/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h b/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h index 24e169925f..d3e5669df7 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/M480.h @@ -3469,7 +3469,7 @@ typedef struct { * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode. - * | | |The flag is set if any wake-up source has occurred. Refer Power Modes and Wake-up Sources chapter. + * | | |The flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter. * | | |Note1: Write 1 to clear the bit to 0. * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. * |[7] |PDEN |System Power-down Enable (Write Protect) @@ -25914,7 +25914,7 @@ typedef struct { * | | |0 = DMA Disabled. * | | |1 = DMA Enabled. * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. - * | | |Note: If target abort has occurred, DMAEN will be cleared. + * | | |Note: If target abort is occurred, DMAEN will be cleared. * |[1] |DMARST |Software Engine Reset * | | |0 = No effect. * | | |1 = Reset internal state machine and pointers @@ -26006,7 +26006,7 @@ typedef struct { * | :----: | :----: | :---- | * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation - * | | |When Target Abort has occurred, please reset all engine. + * | | |When Target Abort is occurred, please reset all engine. * | | |0 = No bus ERROR response received. * | | |1 = Bus ERROR response received. * | | |Note: This bit is read only, but can be cleared by writing '1' to it. @@ -26119,12 +26119,12 @@ typedef struct { * | | |Note: This bit is read only, but can be cleared by writing '1' to it. * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer - * | | |When CRC error has occurred, software should reset SD engine + * | | |When CRC error is occurred, software should reset SD engine * | | |Some response (ex * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag * | | |In this condition, software should ignore CRC error and clears this bit manually. - * | | |0 = No CRC error has occurred. - * | | |1 = CRC error has occurred. + * | | |0 = No CRC error is occurred. + * | | |1 = CRC error is occurred. * | | |Note: This bit is read only, but can be cleared by writing '1' to it. * |[2] |CRC7 |CRC7 Check Status (Read Only) * | | |SD host will check CRC7 correctness during each response in @@ -27705,60 +27705,60 @@ typedef struct { * | | |This bit conveys the interrupt status for USB specific events endpoint * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[1] |CEPIF |Control Endpoint Interrupt * | | |This bit conveys the interrupt status for control endpoint * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[2] |EPAIF |Endpoint a Interrupt * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[3] |EPBIF |Endpoint B Interrupt * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[4] |EPCIF |Endpoint C Interrupt * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[5] |EPDIF |Endpoint D Interrupt * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[6] |EPEIF |Endpoint E Interrupt * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[7] |EPFIF |Endpoint F Interrupt * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[8] |EPGIF |Endpoint G Interrupt * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[9] |EPHIF |Endpoint H Interrupt * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[10] |EPIIF |Endpoint I Interrupt * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[11] |EPJIF |Endpoint J Interrupt * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[12] |EPKIF |Endpoint K Interrupt * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[13] |EPLIF |Endpoint L Interrupt * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * @var HSUSBD_T::GINTEN * Offset: 0x08 Global Interrupt Enable Register * --------------------------------------------------------------------------------------------------- diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h b/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h index f661a3c4b5..6a6520e57c 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/device/Nano100Series.h @@ -10976,18 +10976,18 @@ typedef struct { * |[0] |BUS_STS |BUS Interrupt Status * | | |The BUS event means there is bus suspense or bus resume in the bus. * | | |This bit is used to indicate that there is one of events in the bus. - * | | |0 = No BUS event has occurred. + * | | |0 = No BUS event is occurred. * | | |1 = BUS event occurred; check USB_BUSSTS [3:0] to know which kind of bus event was occurred, cleared by write "1" to USB_INTSTS [0]. * |[1] |USB_STS |USB Interrupt Status * | | |The USB event means that there is Setup Token, IN token, OUT ACK, ISO IN, or ISO OUT event in the bus. * | | |This bit is used to indicate that there is one of events in the bus. - * | | |0 = No USB event has occurred. + * | | |0 = No USB event is occurred. * | | |1 = USB event occurred, check EPSTS0~7[3:0] in USB_EPSTS [31:8] to know which kind of USB event was occurred, cleared by write "1" to USB_INTSTS [1] or USB_INTSTS[31] or EPEVT0~7. * |[2] |FLD_STS |Floating Interrupt Status * | | |0 = There is not attached event in the USB. * | | |1 = There is attached event in the USB and it is cleared by write "1" to USB_INTSTS [2]. * |[3] |WKEUP_STS |Wake-Up Interrupt Status - * | | |0 = No wake-up event has occurred. + * | | |0 = No wake-up event is occurred. * | | |1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS [3]. * |[16] |EPEVT0 |USB Event Status On EP0 * | | |0 = No event occurred in Endpoint 0. diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h b/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h index 762f35c936..00af9638de 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h @@ -20502,7 +20502,7 @@ typedef struct { * | | |Note: This bit is only cleared by writing 1 to it. * |[2] |OVUNF |QEI Counter Overflow Or Underflow Flag * | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_MAXCNT value to zero in compare-counting mode. - * | | |Similarly, the flag is set while QEI counter underflows from zero to 0xFFFF_FFFF or QEI_MAXCNT. + * | | |Similarly, the flag is set wile QEI counter underflows from zero to 0xFFFF_FFFF or QEI_MAXCNT. * | | |0 = No overflow or underflow occurs in QEI counter. * | | |1 = QEI counter occurs counting overflow or underflow. * | | |Note: This bit is only cleared by writing 1 to it. @@ -22305,7 +22305,7 @@ typedef struct { * | | |0 = DMA Disabled. * | | |1 = DMA Enabled. * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. - * | | |Note: If target abort has occurred, DMAEN will be cleared. + * | | |Note: If target abort is occurred, DMAEN will be cleared. * |[1] |DMARST |Software Engine Reset * | | |0 = No effect. * | | |1 = Reset internal state machine and pointers. @@ -22432,7 +22432,7 @@ typedef struct { * | :----: | :----: | :---- | * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation. - * | | |When Target Abort has occurred, please reset all engine. + * | | |When Target Abort is occurred, please reset all engine. * | | |0 = No bus ERROR response received. * | | |1 = Bus ERROR response received. * | | |Note: This bit is read only, but can be cleared by writing '1' to it. @@ -22583,12 +22583,12 @@ typedef struct { * | | |Note: This bit is read only, but can be cleared by writing '1' to it. * |[1] |CRCIF |CRC7, CRC16 And CRC Status Error Interrupt Flag (Read Only) * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer. - * | | |When CRC error has occurred, software should reset SD engine. + * | | |When CRC error is occurred, software should reset SD engine. * | | |Some response (ex. * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag. * | | |In this condition, software should ignore CRC error and clears this bit manually. - * | | |0 = No CRC error has occurred. - * | | |1 = CRC error has occurred. + * | | |0 = No CRC error is occurred. + * | | |1 = CRC error is occurred. * | | |Note: This bit is read only, but can be cleared by writing '1' to it. * |[2] |CRC7 |CRC7 Check Status (Read Only) * | | |SD host will check CRC7 correctness during each response in. @@ -27165,60 +27165,60 @@ typedef struct { * | | |This bit conveys the interrupt status for USB specific events endpoint. * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[1] |CEPIF |Control Endpoint Interrupt * | | |This bit conveys the interrupt status for control endpoint. * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[2] |EPAIF |Endpoints A Interrupt * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[3] |EPBIF |Endpoints B Interrupt * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[4] |EPCIF |Endpoints C Interrupt * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[5] |EPDIF |Endpoints D Interrupt * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[6] |EPEIF |Endpoints E Interrupt * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[7] |EPFIF |Endpoints F Interrupt * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[8] |EPGIF |Endpoints G Interrupt * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[9] |EPHIF |Endpoints H Interrupt * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[10] |EPIIF |Endpoints I Interrupt * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[11] |EPJIF |Endpoints J Interrupt * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[12] |EPKIF |Endpoints K Interrupt * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. * |[13] |EPLIF |Endpoints L Interrupt * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt. * | | |0 = No interrupt event occurred. - * | | |1 = The related interrupt event has occurred. + * | | |1 = The related interrupt event is occurred. */ __I uint32_t GINTSTS; uint32_t RESERVE0[1]; diff --git a/targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c index f0e53c483e..84eeed8f93 100644 --- a/targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC11U6X/i2c_api.c @@ -204,7 +204,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programmatically +// because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c index 5bfd6433e1..4c5202d6bc 100644 --- a/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC11UXX/i2c_api.c @@ -187,7 +187,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programmatically +// because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c index 21976fb217..52f6f4486e 100644 --- a/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC11XX_11CXX/i2c_api.c @@ -197,7 +197,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programmatically +// because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c index 97fbb29018..415ef071af 100644 --- a/targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC13XX/i2c_api.c @@ -197,7 +197,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programmatically +// because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c index d98ca77a69..0b4b7a8312 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c +++ b/targets/TARGET_NXP/TARGET_LPC176X/ethernet_api.c @@ -172,7 +172,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occurred */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ #define TSV0_GIANT 0x00000400 /* Giant Frame */ #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ @@ -268,7 +268,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ @@ -289,10 +289,10 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occurred */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ /* ENET Device Revision ID */ #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ @@ -303,7 +303,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ @@ -540,8 +540,8 @@ void ethernet_free() { // if(TxProduceIndex == TxConsumeIndex) buffer array is empty // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill -// TxProduceIndex - The buffer that will be / is being fileld by driver, s/w increment -// TxConsumeIndex - The buffer that will be / is being sent by hardware +// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment +// TxConsumeIndex - The buffer that will/is beign sent by hardware int ethernet_write(const char *data, int slen) { @@ -651,22 +651,22 @@ int ethernet_send() { #endif } -// RxConsmeIndex - The index of buffer the driver will read / is reading from. Driver should inc once read -// RxProduceIndex - The index of buffer that will be / is being filled by MAC. H/w will inc once rxd +// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read +// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd // // if(RxConsumeIndex == RxProduceIndex) buffer array is empty // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full -// Receives an arrived ethernet packet. +// Recevies an arrived ethernet packet. // Receiving an ethernet packet will drop the last received ethernet packet // and make a new ethernet packet ready to read. // Returns size of packet, else 0 if nothing to receive // We read from RxConsumeIndex from position rx_consume_offset -// if rx_consume_offset < 0, then we have not received the RxConsumeIndex packet for reading +// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading // rx_consume_offset = -1 // no frame // rx_consume_offset = 0 // start of frame -// Assumption: A fragment should always be a whole frame +// Assumption: A fragment should alway be a whole frame int ethernet_receive() { #if NEW_LOGIC @@ -722,11 +722,11 @@ int ethernet_receive() { #endif } -// Read from an received ethernet packet. -// After receive returned a number bigger than 0 it is +// Read from an recevied ethernet packet. +// After receive returnd a number bigger than 0 it is // possible to read bytes from this packet. // Read will write up to size bytes into data. -// It is possible to use read multiple times. +// It is possible to use read multible times. // Each time read will start reading after the last read byte before. int ethernet_read(char *data, int dlen) { diff --git a/targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c index fde4e8e746..fb2ed1656a 100644 --- a/targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC176X/i2c_api.c @@ -204,7 +204,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programmatically +// because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c index 3583096b06..7ea6885fbf 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/ethernet_api.c @@ -100,7 +100,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ -#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Pressure / No Backoff */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ /* Back-to-Back Inter-Packet-Gap Register */ @@ -166,19 +166,19 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TSV0_CRC_ERR 0x00000001 /* CRC error */ #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ -#define TSV0_DONE 0x00000008 /* Transmission Completed */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ #define TSV0_MCAST 0x00000010 /* Multicast Destination */ #define TSV0_BCAST 0x00000020 /* Broadcast Destination */ #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occurred */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ #define TSV0_GIANT 0x00000400 /* Giant Frame */ #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ #define TSV0_PAUSE 0x20000000 /* Pause Frame */ -#define TSV0_BACK_PRESS 0x40000000 /* Back pressure Method Applied */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ #define TSV0_VLAN 0x80000000 /* VLAN Frame */ /* Transmit Status Vector 1 Register */ @@ -268,7 +268,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ @@ -289,10 +289,10 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occurred */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ /* ENET Device Revision ID */ #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ @@ -303,7 +303,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ @@ -565,8 +565,8 @@ void ethernet_free() { // if(TxProduceIndex == TxConsumeIndex) buffer array is empty // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill -// TxProduceIndex - The buffer that will be / is being filled by driver, s/w increment -// TxConsumeIndex - The buffer that will be / is being sent by hardware +// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment +// TxConsumeIndex - The buffer that will/is beign sent by hardware int ethernet_write(const char *data, int slen) { @@ -676,22 +676,22 @@ int ethernet_send() { #endif } -// RxConsmeIndex - The index of buffer the driver will read / is reading from. Driver should inc once read -// RxProduceIndex - The index of buffer that will be / is being filled by MAC. H/w will inc once rxd +// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read +// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd // // if(RxConsumeIndex == RxProduceIndex) buffer array is empty // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full -// Receives an arrived ethernet packet. +// Recevies an arrived ethernet packet. // Receiving an ethernet packet will drop the last received ethernet packet // and make a new ethernet packet ready to read. // Returns size of packet, else 0 if nothing to receive // We read from RxConsumeIndex from position rx_consume_offset -// if rx_consume_offset < 0, then we have not received the RxConsumeIndex packet for reading +// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading // rx_consume_offset = -1 // no frame // rx_consume_offset = 0 // start of frame -// Assumption: A fragment should always be a whole frame +// Assumption: A fragment should alway be a whole frame int ethernet_receive() { #if NEW_LOGIC @@ -747,11 +747,11 @@ int ethernet_receive() { #endif } -// Read from an received ethernet packet. -// After receive returned a number bigger than 0 it is +// Read from an recevied ethernet packet. +// After receive returnd a number bigger than 0 it is // possible to read bytes from this packet. // Read will write up to size bytes into data. -// It is possible to use read multiple times. +// It is possible to use read multible times. // Each time read will start reading after the last read byte before. int ethernet_read(char *data, int dlen) { diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c index 8a1cd29e8d..730e51eb49 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088/i2c_api.c @@ -224,7 +224,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programmatically +// because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int count, status; diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c index 6477094954..67d344aa4e 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c @@ -172,7 +172,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occurred */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ #define TSV0_GIANT 0x00000400 /* Giant Frame */ #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ @@ -268,7 +268,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define RINFO_OVERRUN 0x10000000 /* Receive overrun */ #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \ @@ -289,10 +289,10 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occurred */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occurred (OR of all errors) */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ /* ENET Device Revision ID */ #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ @@ -303,7 +303,7 @@ typedef struct TX_STAT_TypeDef TX_STAT_TypeDef; #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ @@ -565,8 +565,8 @@ void ethernet_free() { // if(TxProduceIndex == TxConsumeIndex) buffer array is empty // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill -// TxProduceIndex - The buffer that will be / is being fileld by driver, s/w increment -// TxConsumeIndex - The buffer that will be / is being sent by hardware +// TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment +// TxConsumeIndex - The buffer that will/is beign sent by hardware int ethernet_write(const char *data, int slen) { @@ -676,22 +676,22 @@ int ethernet_send() { #endif } -// RxConsmeIndex - The index of buffer the driver will read / is reading from. Driver should inc once read -// RxProduceIndex - The index of buffer that will be / is being filled by MAC. H/w will inc once rxd +// RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read +// RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd // // if(RxConsumeIndex == RxProduceIndex) buffer array is empty // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full -// Receives an arrived ethernet packet. +// Recevies an arrived ethernet packet. // Receiving an ethernet packet will drop the last received ethernet packet // and make a new ethernet packet ready to read. // Returns size of packet, else 0 if nothing to receive // We read from RxConsumeIndex from position rx_consume_offset -// if rx_consume_offset < 0, then we have not received the RxConsumeIndex packet for reading +// if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading // rx_consume_offset = -1 // no frame // rx_consume_offset = 0 // start of frame -// Assumption: A fragment should always be a whole frame +// Assumption: A fragment should alway be a whole frame int ethernet_receive() { #if NEW_LOGIC @@ -747,11 +747,11 @@ int ethernet_receive() { #endif } -// Read from an received ethernet packet. -// After receive returned a number bigger than 0 it is +// Read from an recevied ethernet packet. +// After receive returnd a number bigger than 0 it is // possible to read bytes from this packet. // Read will write up to size bytes into data. -// It is possible to use read multiple times. +// It is possible to use read multible times. // Each time read will start reading after the last read byte before. int ethernet_read(char *data, int dlen) { diff --git a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c index 5093dfc6ea..64ebe3cc1c 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/i2c_api.c @@ -210,7 +210,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programmatically +// because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int count, status; diff --git a/targets/TARGET_NXP/TARGET_LPC408X/device/system_LPC407x_8x_177x_8x.c b/targets/TARGET_NXP/TARGET_LPC408X/device/system_LPC407x_8x_177x_8x.c index 835d31b4a5..9978362559 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/device/system_LPC407x_8x_177x_8x.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/device/system_LPC407x_8x_177x_8x.c @@ -555,7 +555,8 @@ fpu_init(); LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ #endif - LPC_SC->PBOOST |= 0x03; /* Power Boost control */ + //TODO: verify correct operation w/ this setting. Refer to Table 18 in UM10562.pdf. + LPC_SC->PBOOST |= 0x00; /* Power Boost control */ #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A; diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c index 6845904c69..b947155941 100644 --- a/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c +++ b/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c @@ -148,7 +148,7 @@ typedef struct TX_DESC_TypeDef TX_DESC_TypeDef; #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Ability */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ diff --git a/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c index fe1791fbc4..0e26102c91 100644 --- a/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC43XX/i2c_api.c @@ -205,7 +205,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programmatically +// because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { diff --git a/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c index df5979754a..916242f3bd 100644 --- a/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c @@ -151,7 +151,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programmatically +// because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that //New version WH, Tested OK for Start and Repeated Start diff --git a/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c index a8d662da33..91044d4ab3 100644 --- a/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c +++ b/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c @@ -242,7 +242,7 @@ void i2c_frequency(i2c_t *obj, int hz) { // 2) on error, we use the standard error mechanisms to report/debug // // Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programmatically +// because something is setup wrong (e.g. wiring), and we don't need to programatically // check for that int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { int count, status; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h index cd45a4e7f5..07c17b8d98 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h @@ -79,7 +79,7 @@ enum _mcan_status * * This provides constants for the MCAN status flags for use in the MCAN functions. * Note: The CPU read action clears MCAN_ErrorFlag, therefore user need to - * read MCAN_ErrorFlag and distinguish which error has occurred using + * read MCAN_ErrorFlag and distinguish which error is occur using * @ref _mcan_error_flags enumerations. */ enum _mcan_flags @@ -548,7 +548,7 @@ void MCAN_SetDataTimingConfig(CAN_Type *base, const mcan_timing_config_t *config * @brief Configures an MCAN receive fifo 0 buffer. * * This function sets start address, element size, watermark, operation mode - * and datafield size of the receive fifo 0. + * and datafield size of the recieve fifo 0. * * @param base MCAN peripheral base address. * @param config The receive fifo 0 configuration structure. @@ -559,7 +559,7 @@ void MCAN_SetRxFifo0Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); * @brief Configures an MCAN receive fifo 1 buffer. * * This function sets start address, element size, watermark, operation mode - * and datafield size of the receive fifo 1. + * and datafield size of the recieve fifo 1. * * @param base MCAN peripheral base address. * @param config The receive fifo 1 configuration structure. @@ -569,7 +569,7 @@ void MCAN_SetRxFifo1Config(CAN_Type *base, const mcan_rx_fifo_config_t *config); /*! * @brief Configures an MCAN receive buffer. * - * This function sets start address and datafield size of the receive buffer. + * This function sets start address and datafield size of the recieve buffer. * * @param base MCAN peripheral base address. * @param config The receive buffer configuration structure. diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h index ece101ad2e..e2602c6211 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h @@ -317,7 +317,7 @@ typedef struct _sdif_data size_t blockSize; /*!< Block size, take care when config this parameter */ uint32_t blockCount; /*!< Block count */ - uint32_t *rxData; /*!< data buffer to receive */ + uint32_t *rxData; /*!< data buffer to recieve */ const uint32_t *txData; /*!< data buffer to transfer */ } sdif_data_t; @@ -335,7 +335,7 @@ typedef struct _sdif_command uint32_t responseType; /*!< Command response type */ uint32_t flags; /*!< Cmd flags */ uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when - receive the cmd response */ + recieve the cmd response */ } sdif_command_t; /*! @brief Transfer state */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h index 2f1871ba7d..e5b6b8c16f 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_adc.h @@ -52,7 +52,7 @@ typedef enum _adc_status_flags kADC_ConversionActiveFlag = ADC_GS_ADACT_MASK, /*!< Conversion is active,not support w1c. */ kADC_CalibrationFailedFlag = ADC_GS_CALF_MASK, /*!< Calibration is failed,support w1c. */ kADC_AsynchronousWakeupInterruptFlag = - ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occurred, support w1c. */ + ADC_GS_AWKST_MASK, /*!< Asynchronous wakeup interrupt occured, support w1c. */ } adc_status_flags_t; /*! diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h index 335c41b591..3ae7598f00 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_flexcan.h @@ -240,7 +240,7 @@ enum _flexcan_interrupt_enable * * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to - * read FlEXCAN_ErrorFlag and distinguish which error has occurred using + * read FlEXCAN_ErrorFlag and distinguish which error is occur using * @ref _flexcan_error_flags enumerations. */ enum _flexcan_flags diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c index 6e6a5e30ce..31fd061e4c 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_sai.c @@ -37,7 +37,7 @@ enum _sai_transfer_state { kSAI_Busy = 0x0U, /*!< SAI is busy */ kSAI_Idle, /*!< Transfer is done. */ - kSAI_Error /*!< Transfer error occurred. */ + kSAI_Error /*!< Transfer error occured. */ }; /*! @brief Typedef for sai tx interrupt handler. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c index 31f7691b72..b0e70c0358 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_spdif.c @@ -37,7 +37,7 @@ enum _spdif_transfer_state { kSPDIF_Busy = 0x0U, /*!< SPDIF is busy */ kSPDIF_Idle, /*!< Transfer is done. */ - kSPDIF_Error /*!< Transfer error occurred. */ + kSPDIF_Error /*!< Transfer error occured. */ }; /*! @brief Typedef for spdif tx interrupt handler. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c index 46190dc159..0aafb78d8e 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_trng.c @@ -1176,7 +1176,7 @@ typedef enum _trng_statistical_check * TRNG access mode in the SA-TRNG Miscellaneous Control Register. * * Values: - * - 0b0 - Programmability of registers controlled only by the RNG Miscellaneous + * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous * Control Register's access mode bit. * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents * TRNG register programming. diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h b/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h index 61a08ec6f3..0f6ab4489d 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h @@ -26,7 +26,7 @@ * * @details * The character driver is intended for devices that allow read and write - * operations with "streams" of data, such as UART devices, SPI or I2C, etc. + * operations with "streams" of data, such as UART devices, SPI or I2c, etc. * * The character driver derives from the generic driver template (see driver.h). * It does so by including an element of the generic driver_t type. diff --git a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c index 593ddf48a7..8ae4a9b935 100644 --- a/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/ncs36510_i2c.c @@ -145,7 +145,7 @@ int32_t fI2cStop(i2c_t *obj) if (obj->membase->STATUS.WORD & (I2C_STATUS_CMD_FIFO_FULL_BIT | I2C_STATUS_CMD_FIFO_OFL_BIT | I2C_STATUS_BUS_ERR_BIT)) { - /* I2C error occurred */ + /* I2c error occured */ return I2C_ERROR_BUS_BUSY; } return I2C_API_STATUS_SUCCESS; @@ -164,7 +164,7 @@ int32_t fI2cReadB(i2c_t *obj, char *buf, int len) SEND_COMMAND(I2C_CMD_RDAT8); while(!RD_DATA_READY) { if (I2C_BUS_ERR_CHECK) { - /* Bus error occurred */ + /* Bus error occured */ return I2C_ERROR_BUS_BUSY; } } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c index ac37ba5cb5..227ac68f4e 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c @@ -442,7 +442,7 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { i2c_set_err_noslave(obj); return I2C_ERROR_NO_SLAVE; } - /* Receive the data */ + /* Recieve the data */ if (count == (length - 2)) { value = i2c_do_read(obj, 1); } else if ((length >= 3) && (count == (length - 3))) { diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h index 8b25da958a..f221efc744 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.h @@ -125,21 +125,21 @@ public: /** Get the local IP address * * @return Null-terminated representation of the local IP address - * or null if no IP address has been received + * or null if no IP address has been recieved */ virtual const char *get_ip_address(); /** Get the local network mask * * @return Null-terminated representation of the local network mask - * or null if no network mask has been received + * or null if no network mask has been recieved */ virtual const char *get_netmask(); /** Get the local gateways * * @return Null-terminated representation of the local gateway - * or null if no network mask has been received + * or null if no network mask has been recieved */ virtual const char *get_gateway(); diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h index 660258bd4d..ac988590c4 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/drivers/wlan/realtek/src/osdep/wireless.h @@ -145,7 +145,7 @@ * * V11 to V12 * ---------- - * - Add SIOCSIWSTATS to get /proc/net/wireless programmatically + * - Add SIOCSIWSTATS to get /proc/net/wireless programatically * - Add DEV PRIVATE IOCTL to avoid collisions in SIOCDEVPRIVATE space * - Add new statistics (frag, retry, beacon) * - Add average quality (for user space calibration) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h index 183f8c20f9..315db89171 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h @@ -1000,7 +1000,7 @@ #define REG_SPIC_FLUSH_FIFO 0x0128//O VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); // spi-flash controller initialization -VOID SpicRxCmdRtl8195A(u8); // receive command +VOID SpicRxCmdRtl8195A(u8); // recieve command VOID SpicTxCmdRtl8195A(u8 cmd, SPIC_INIT_PARA SpicInitPara); // transfer command u8 SpicGetFlashStatusRtl8195A(SPIC_INIT_PARA SpicInitPara); // RDSR, read spi-flash status register VOID SpicSetFlashStatusRtl8195A(u32 data, SPIC_INIT_PARA SpicInitPara); // WRSR, write spi-flash status register diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c index fa656f6a09..167bb4bb66 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_flash.c @@ -170,7 +170,7 @@ extern void FLASH_PageErase(uint32_t PageAddress); * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @note FLASH should be previously erased before new programming (only exception to this + * @note FLASH should be previously erased before new programmation (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram Indicate the way to program at a specified address. @@ -223,7 +223,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - /* In case of error, stop programming procedure */ + /* In case of error, stop programation procedure */ if (status != HAL_OK) { break; diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c index ec0de43d9c..d0fe3dada4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.c @@ -1040,7 +1040,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) return; } - /* I2S Overrun error interrupt occurred --------------------------------*/ + /* I2S Overrun error interrupt occured ---------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -1054,7 +1054,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) HAL_I2S_ErrorCallback(hi2s); } - /* I2S Underrun error interrupt occurred -------------------------------*/ + /* I2S Underrun error interrupt occured --------------------------------*/ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c index 2297a402a0..eaf1697a91 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tsc.c @@ -703,14 +703,14 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - /* Check if the end of acquisition occurred */ + /* Check if the end of acquisition occured */ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET) { /* Clear EOA flag */ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA); } - /* Check if max count error occurred */ + /* Check if max count error occured */ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET) { /* Clear MCE flag */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c index 57fc036b67..3aa2e4c37b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c @@ -143,7 +143,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_clock.c index 7f53e68078..40ccdaf31b 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/system_clock.c @@ -142,7 +142,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c index 4d83c9a258..2bbb626f14 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_flash.c @@ -173,7 +173,7 @@ extern void FLASH_PageErase(uint32_t PageAddress); * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @note FLASH should be previously erased before new programming (only exception to this + * @note FLASH should be previously erased before new programmation (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram: Indicate the way to program at a specified address. @@ -253,7 +253,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint CLEAR_BIT(FLASH->CR2, FLASH_CR2_PG); } #endif /* FLASH_BANK2_END */ - /* In case of error, stop programming procedure */ + /* In case of error, stop programation procedure */ if (status != HAL_OK) { break; diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c index 828cd30823..332717572f 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2s.c @@ -1363,7 +1363,7 @@ static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_Receive_IT(hi2s); } - /* I2S Overrun error interrupt occurred -------------------------------------*/ + /* I2S Overrun error interrupt occured -------------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h index 6c3810db2a..98081ddc45 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h @@ -1203,7 +1203,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of 10-bit header sent (master mode). - * @note RESET: When no ADD10 event occurred. + * @note RESET: When no ADD10 event occured. * SET: When the master has sent the first address byte (header). * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 * @param I2Cx I2C Instance. diff --git a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_i2c.h index 514829d48c..a3b261e85c 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_i2c.h @@ -1203,7 +1203,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of 10-bit header sent (master mode). - * @note RESET: When no ADD10 event occurred. + * @note RESET: When no ADD10 event occured. * SET: When the master has sent the first address byte (header). * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 * @param I2Cx I2C Instance. diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c index 98908e1ee3..eaebd5682b 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c @@ -173,7 +173,7 @@ extern void FLASH_PageErase(uint32_t PageAddress); * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. * - * @note FLASH should be previously erased before new programming (only exception to this + * @note FLASH should be previously erased before new programmation (only exception to this * is when 0x0000 is programmed) * * @param TypeProgram Indicate the way to program at a specified address. @@ -226,7 +226,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint /* If the program operation is completed, disable the PG Bit */ CLEAR_BIT(FLASH->CR, FLASH_CR_PG); - /* In case of error, stop programming procedure */ + /* In case of error, stop programation procedure */ if (status != HAL_OK) { break; diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.c index 7549d7c58f..497a85c936 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.c @@ -5978,7 +5978,7 @@ void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim, } /** - * @brief Callback function invoked when a fault 1 interrupt occurred + * @brief Callback function invoked when a fault 1 interrupt occured * @param hhrtim: pointer to HAL HRTIM handle * @retval None * @retval None */ @@ -5993,7 +5993,7 @@ __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief Callback function invoked when a fault 2 interrupt occurred + * @brief Callback function invoked when a fault 2 interrupt occured * @param hhrtim: pointer to HAL HRTIM handle * @retval None */ @@ -6008,7 +6008,7 @@ __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief Callback function invoked when a fault 3 interrupt occurred + * @brief Callback function invoked when a fault 3 interrupt occured * @param hhrtim: pointer to HAL HRTIM handle * @retval None */ @@ -6023,7 +6023,7 @@ __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief Callback function invoked when a fault 4 interrupt occurred + * @brief Callback function invoked when a fault 4 interrupt occured * @param hhrtim: pointer to HAL HRTIM handle * @retval None */ @@ -6038,7 +6038,7 @@ __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief Callback function invoked when a fault 5 interrupt occurred + * @brief Callback function invoked when a fault 5 interrupt occured * @param hhrtim: pointer to HAL HRTIM handle * @retval None */ @@ -6053,7 +6053,7 @@ __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim) } /** - * @brief Callback function invoked when a system fault interrupt occurred + * @brief Callback function invoked when a system fault interrupt occured * @param hhrtim: pointer to HAL HRTIM handle * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c index d1844d77ba..0a9abba63f 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c @@ -945,7 +945,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_Receive_IT(hi2s); } - /* I2S Overrun error interrupt occurred ------------------------------------*/ + /* I2S Overrun error interrupt occured -------------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -967,7 +967,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_Transmit_IT(hi2s); } - /* I2S Underrun error interrupt occurred -----------------------------------*/ + /* I2S Underrun error interrupt occured ------------------------------------*/ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c index 338b9acd7a..37a3adbe27 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c @@ -435,7 +435,7 @@ void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT); } - /* I2Sext Overrun error interrupt occurred -------------------------------*/ + /* I2Sext Overrun error interrupt occured --------------------------------*/ if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -452,7 +452,7 @@ void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) HAL_I2S_ErrorCallback(hi2s); } - /* I2S Underrun error interrupt occurred ---------------------------------*/ + /* I2S Underrun error interrupt occured ----------------------------------*/ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ @@ -488,7 +488,7 @@ void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_FullDuplexRx_IT(hi2s, I2S_USE_I2S); } - /* I2S Overrun error interrupt occurred ------------------------------------*/ + /* I2S Overrun error interrupt occured -------------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -505,7 +505,7 @@ void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) HAL_I2S_ErrorCallback(hi2s); } - /* I2Sext Underrun error interrupt occurred ------------------------------*/ + /* I2Sext Underrun error interrupt occured -------------------------------*/ if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c index 0e4df04945..77ba4ecd78 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c @@ -1811,7 +1811,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) /* Wait until REACK flag is set */ if(IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) { - /* Timeout Occurred */ + /* Timeout Occured */ return HAL_TIMEOUT; } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.c index 20f6c81007..f691e7f2f8 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_uart.c @@ -2296,7 +2296,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until TEACK flag is set */ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { - /* Timeout Occurred */ + /* Timeout Occured */ return HAL_TIMEOUT; } } @@ -2306,7 +2306,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until REACK flag is set */ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { - /* Timeout Occurred */ + /* Timeout Occured */ return HAL_TIMEOUT; } } diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c index 9c2afcc7ee..a2caa0ddc4 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.c @@ -2128,7 +2128,7 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) /* Wait until TEACK flag is set */ if(USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) { - /* Timeout Occurred */ + /* Timeout Occured */ return HAL_TIMEOUT; } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c index f1f150016f..6ae08aac48 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c @@ -124,7 +124,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c index f1f150016f..6ae08aac48 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c @@ -124,7 +124,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c index 7d64108a6a..13d92ef57a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c @@ -130,7 +130,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c index c96b51c08c..f42278ce2c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c @@ -121,7 +121,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c index 425580bc01..9c33be421e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c @@ -121,7 +121,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h index abb008c413..23c09610e9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h @@ -13604,7 +13604,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c index 698f92ec57..bffa88a663 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c @@ -125,7 +125,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h index 1bc9d75b7d..5feb7667c5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h @@ -15156,7 +15156,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h index 9302e9b082..a7df3124bc 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h @@ -15096,7 +15096,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h index f01a8b1f38..24be80d57a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/ublox-odin-w2-drivers/OdinWiFiInterface.h @@ -115,7 +115,7 @@ public: /** Get the local IP address * * @return Null-terminated representation of the local IP address - * or null if no IP address has been received + * or null if no IP address has been recieved */ virtual const char *get_ip_address(); @@ -129,7 +129,7 @@ public: /** Get the local gateway * * @return Null-terminated representation of the local gateway - * or null if no network mask has been received + * or null if no network mask has been recieved */ virtual const char *get_gateway(); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h index 80634c63ee..16eb383e44 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h @@ -15444,7 +15444,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c index 6d1bdc97ad..ed57a5fa5d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c @@ -124,7 +124,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h index b8893dae93..d054b8fb07 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h @@ -18175,7 +18175,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c index 606c22dc8b..f80478f6ad 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c @@ -1443,7 +1443,7 @@ static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s) I2S_Receive_IT(hi2s); } - /* I2S Overrun error interrupt occurred ------------------------------------*/ + /* I2S Overrun error interrupt occured -------------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c index 978c7ea753..aae1ac401a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c @@ -784,7 +784,7 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2SEXT); } - /* I2Sext Overrun error interrupt occurred -------------------------------*/ + /* I2Sext Overrun error interrupt occured --------------------------------*/ if(((i2sextsr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -804,7 +804,7 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) HAL_I2S_ErrorCallback(hi2s); } - /* I2S Underrun error interrupt occurred ---------------------------------*/ + /* I2S Underrun error interrupt occured ----------------------------------*/ if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ @@ -843,7 +843,7 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) I2SEx_FullDuplexRx_IT(hi2s, I2S_USE_I2S); } - /* I2S Overrun error interrupt occurred ------------------------------------*/ + /* I2S Overrun error interrupt occured -------------------------------------*/ if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable RXNE and ERR interrupt */ @@ -860,7 +860,7 @@ void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s) HAL_I2S_ErrorCallback(hi2s); } - /* I2Sext Underrun error interrupt occurred ------------------------------*/ + /* I2Sext Underrun error interrupt occured -------------------------------*/ if(((i2sextsr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2SEXT_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c index 6d8daf6933..0fba5e62c1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c @@ -1310,7 +1310,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) uint32_t cr1config = hsai->Instance->CR1; uint32_t tmperror; - /* SAI Fifo request interrupt occurred -----------------------------------*/ + /* SAI Fifo request interrupt occured ------------------------------------*/ if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h index 1db3dba380..69f44ce05b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h @@ -1309,7 +1309,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of 10-bit header sent (master mode). - * @note RESET: When no ADD10 event occurred. + * @note RESET: When no ADD10 event occured. * SET: When the master has sent the first address byte (header). * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 * @param I2Cx I2C Instance. diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h index f5a79948dc..6ca83de287 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h @@ -976,7 +976,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) } /** - * @brief Inform application whether a autoreload match interrupt has occurred. + * @brief Inform application whether a autoreload match interrupt has occured. * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h index 4a6350c6f9..ca9deeebf4 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h @@ -15398,7 +15398,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h index 6c29b80fa9..1a19a08cfb 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h @@ -15685,7 +15685,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h index 083f43e419..4e7911cf69 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h @@ -16074,7 +16074,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h index 59e29e1b0c..5cde08e3a0 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h @@ -16169,7 +16169,7 @@ typedef struct #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ -#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ +#define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c index b5e8263498..acc8a6bbc4 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c @@ -577,7 +577,7 @@ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) [..] This subsection provides a set of functions allowing to control the MDIOS. (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state. - (+) HAL_MDIOS_GetError() API, returns the errors occurred during data transfer. + (+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer. @endverbatim * @{ @@ -586,7 +586,7 @@ __weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) /** * @brief Gets MDIOS error flags * @param hmdios mdios handle - * @retval bit map of occurred errors + * @retval bit map of occured errors */ uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) { diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c index 5b9f5e4730..15cf097456 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c @@ -1358,7 +1358,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) uint32_t cr1config = hsai->Instance->CR1; uint32_t tmperror; - /* SAI Fifo request interrupt occurred -----------------------------------*/ + /* SAI Fifo request interrupt occured ------------------------------------*/ if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h index c69eb8b4a7..007656613e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h @@ -981,7 +981,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) } /** - * @brief Inform application whether a autoreload match interrupt has occurred. + * @brief Inform application whether a autoreload match interrupt has occured. * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c index d9d0873531..c1c3fad6fc 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2s.c @@ -1069,7 +1069,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /* I2S interrupt error -------------------------------------------------*/ if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET) { - /* I2S Overrun error interrupt occurred --------------------------------*/ + /* I2S Overrun error interrupt occured ---------------------------------*/ if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) { /* Disable RXNE and ERR interrupt */ @@ -1079,7 +1079,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); } - /* I2S Underrun error interrupt occurred -------------------------------*/ + /* I2S Underrun error interrupt occured --------------------------------*/ if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c index ad0fd57f14..06bd6981c2 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_irda.c @@ -896,7 +896,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) */ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) { - /* IRDA parity error interrupt occurred ------------------------------------*/ + /* IRDA parity error interrupt occurred -------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET)) { __HAL_IRDA_CLEAR_PEFLAG(hirda); @@ -906,7 +906,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) hirda->State = HAL_IRDA_STATE_READY; } - /* IRDA frame error interrupt occurred -------------------------------------*/ + /* IRDA frame error interrupt occured --------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) { __HAL_IRDA_CLEAR_FEFLAG(hirda); @@ -916,7 +916,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) hirda->State = HAL_IRDA_STATE_READY; } - /* IRDA noise error interrupt occurred -------------------------------------*/ + /* IRDA noise error interrupt occured --------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) { __HAL_IRDA_CLEAR_NEFLAG(hirda); @@ -926,7 +926,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) hirda->State = HAL_IRDA_STATE_READY; } - /* IRDA Over-Run interrupt occurred -----------------------------------------*/ + /* IRDA Over-Run interrupt occured -----------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) { __HAL_IRDA_CLEAR_OREFLAG(hirda); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c index 492bff6bd2..a33f92310c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_smartcard.c @@ -724,7 +724,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) hsc->State = HAL_SMARTCARD_STATE_READY; } - /* SMARTCARD frame error interrupt occurred --------------------------------*/ + /* SMARTCARD frame error interrupt occured ---------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) { __HAL_SMARTCARD_CLEAR_FEFLAG(hsc); @@ -733,7 +733,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) hsc->State = HAL_SMARTCARD_STATE_READY; } - /* SMARTCARD noise error interrupt occurred --------------------------------*/ + /* SMARTCARD noise error interrupt occured ---------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) { __HAL_SMARTCARD_CLEAR_NEFLAG(hsc); @@ -742,7 +742,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) hsc->State = HAL_SMARTCARD_STATE_READY; } - /* SMARTCARD Over-Run interrupt occurred -----------------------------------*/ + /* SMARTCARD Over-Run interrupt occured ------------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) { __HAL_SMARTCARD_CLEAR_OREFLAG(hsc); @@ -751,7 +751,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) hsc->State = HAL_SMARTCARD_STATE_READY; } - /* SMARTCARD receiver timeout interrupt occurred ---------------------------*/ + /* SMARTCARD receiver timeout interrupt occured ----------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_RTO) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RTO) != RESET)) { __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_RTOF); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c index fe51945c15..daf265ddd3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tsc.c @@ -709,14 +709,14 @@ void HAL_TSC_IRQHandler(TSC_HandleTypeDef* htsc) /* Check the parameters */ assert_param(IS_TSC_ALL_INSTANCE(htsc->Instance)); - /* Check if the end of acquisition occurred */ + /* Check if the end of acquisition occured */ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_EOA) != RESET) { /* Clear EOA flag */ __HAL_TSC_CLEAR_FLAG(htsc, TSC_FLAG_EOA); } - /* Check if max count error occurred */ + /* Check if max count error occured */ if (__HAL_TSC_GET_FLAG(htsc, TSC_FLAG_MCE) != RESET) { /* Clear MCE flag */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c index 694e8baea0..98470850f3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_uart.c @@ -1083,7 +1083,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { - /* UART parity error interrupt occurred -----------------------------------*/ + /* UART parity error interrupt occurred ------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET)) { @@ -1095,7 +1095,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxState = HAL_UART_STATE_READY; } - /* UART frame error interrupt occurred -------------------------------------*/ + /* UART frame error interrupt occured --------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); @@ -1106,7 +1106,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxState = HAL_UART_STATE_READY; } - /* UART noise error interrupt occurred -------------------------------------*/ + /* UART noise error interrupt occured --------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); @@ -1117,7 +1117,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxState = HAL_UART_STATE_READY; } - /* UART Over-Run interrupt occurred ----------------------------------------*/ + /* UART Over-Run interrupt occurred -----------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); @@ -1128,7 +1128,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) huart->RxState = HAL_UART_STATE_READY; } - /* Call UART Error Call back function if need be ---------------------------*/ + /* Call UART Error Call back function if need be --------------------------*/ if(huart->ErrorCode != HAL_UART_ERROR_NONE) { /* Set the UART state ready to be able to start again the process */ @@ -1138,7 +1138,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UART_ErrorCallback(huart); } - /* UART Wake Up interrupt occurred -----------------------------------------*/ + /* UART Wake Up interrupt occured ------------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_WUF) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_WUF) != RESET)) { __HAL_UART_CLEAR_IT(huart, UART_CLEAR_WUF); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c index 32e34e5fda..3fc35648d2 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_usart.c @@ -1040,7 +1040,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) { - /* USART parity error interrupt occurred ------------------------------------*/ + /* USART parity error interrupt occured ------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET)) { __HAL_USART_CLEAR_PEFLAG(husart); @@ -1049,7 +1049,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_READY; } - /* USART frame error interrupt occurred -------------------------------------*/ + /* USART frame error interrupt occured -------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) { __HAL_USART_CLEAR_FEFLAG(husart); @@ -1058,7 +1058,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_READY; } - /* USART noise error interrupt occurred -------------------------------------*/ + /* USART noise error interrupt occured -------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) { __HAL_USART_CLEAR_NEFLAG(husart); @@ -1067,7 +1067,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) husart->State = HAL_USART_STATE_READY; } - /* USART Over-Run interrupt occurred ----------------------------------------*/ + /* USART Over-Run interrupt occured ----------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) { __HAL_USART_CLEAR_OREFLAG(husart); diff --git a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_lptim.h index 57c89976ab..42c6916ca1 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_ll_lptim.h @@ -983,7 +983,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) } /** - * @brief Inform application whether a autoreload match interrupt has occurred. + * @brief Inform application whether a autoreload match interrupt has occured. * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c index 1a232bb2f5..bd4a411cb0 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L0/flash_api.c @@ -158,7 +158,7 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { } uint32_t flash_get_page_size(const flash_t *obj) { - /* Page size is the minimum programmable size, which 4 bytes */ + /* Page size is the minimum programable size, which 4 bytes */ return 4; } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_clock.c index 944956c5da..d14cbc4bc6 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_clock.c @@ -117,7 +117,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c index f776950cf6..6d1889d50a 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c @@ -133,7 +133,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c index d6cf4416dc..df762686ea 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_clock.c @@ -117,7 +117,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c index f776950cf6..6d1889d50a 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c @@ -133,7 +133,7 @@ void SetSysClock(void) /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { while(1) { - // [TODO] Put something here to tell the user that a problem occurred... + // [TODO] Put something here to tell the user that a problem occured... } } } diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.c index c8aa093cb7..63d8b991c4 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.c @@ -1056,7 +1056,7 @@ static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } - /* Return the Option Byte BOR programming Status */ + /* Return the Option Byte BOR programmation Status */ return status; } diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.c index 73f83e2e8b..9e4151e1a7 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.c @@ -1033,7 +1033,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) /* I2S interrupt error -------------------------------------------------*/ if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET) { - /* I2S Overrun error interrupt occurred --------------------------------*/ + /* I2S Overrun error interrupt occured ---------------------------------*/ if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) { /* Disable RXNE and ERR interrupt */ @@ -1043,7 +1043,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); } - /* I2S Underrun error interrupt occurred -------------------------------*/ + /* I2S Underrun error interrupt occured --------------------------------*/ if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) { /* Disable TXE and ERR interrupt */ @@ -1053,7 +1053,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); } - /* I2S Frame format error interrupt occurred --------------------------*/ + /* I2S Frame format error interrupt occured --------------------------*/ if((i2ssr & I2S_FLAG_FRE) == I2S_FLAG_FRE) { /* Disable TXE and ERR interrupt */ diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.c index e45d6b1151..31b144ac60 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.c @@ -1781,7 +1781,7 @@ HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32 } else { - /* An error occurred while enabling/disabling the wide bus*/ + /* An error occured while enabling/disabling the wide bus*/ } } else diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h index 84a2057411..dbe82c30be 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h @@ -1205,7 +1205,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of 10-bit header sent (master mode). - * @note RESET: When no ADD10 event occurred. + * @note RESET: When no ADD10 event occured. * SET: When the master has sent the first address byte (header). * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 * @param I2Cx I2C Instance. diff --git a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c index d4b1b44203..5e6932071f 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L1/flash_api.c @@ -157,7 +157,7 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) uint32_t flash_get_page_size(const flash_t *obj) { - /* Page size is the minimum programmable size, which 4 bytes */ + /* Page size is the minimum programable size, which 4 bytes */ return 4; } diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c index 74f81be2ce..02f941c970 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_sai.c @@ -1469,7 +1469,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) uint32_t cr1config = hsai->Instance->CR1; uint32_t tmperror; - /* SAI Fifo request interrupt occurred -----------------------------------*/ + /* SAI Fifo request interrupt occured ------------------------------------*/ if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h index 4b8c1dc129..fc04402a39 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_lptim.h @@ -1030,7 +1030,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) } /** - * @brief Inform application whether a autoreload match interrupt has occurred. + * @brief Inform application whether a autoreload match interrupt has occured. * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c index 45444bee0e..4904e93317 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32L4/flash_api.c @@ -254,7 +254,7 @@ uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { * @return The size of a page */ uint32_t flash_get_page_size(const flash_t *obj) { - /* Page size is the minimum programmable size, which 8 bytes */ + /* Page size is the minimum programable size, which 8 bytes */ return 8; } diff --git a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c index 973d30dd7d..3c4bc21945 100644 --- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c @@ -1910,7 +1910,7 @@ uint8_t serial_rx_active(serial_t *obj) } /** The asynchronous TX handler. Writes to the TX FIFO and checks for events. - * If any TX event has occurred, the TX abort function is called. + * If any TX event has occured, the TX abort function is called. * * @param obj The serial object * @return Returns event flags if a TX transfer termination condition was met or 0 otherwise @@ -1961,7 +1961,7 @@ int serial_tx_irq_handler_asynch(serial_t *obj) } /** The asynchronous RX handler. Reads from the RX FIFOF and checks for events. - * If any RX event has occurred, the RX abort function is called. + * If any RX event has occured, the RX abort function is called. * * @param obj The serial object * @return Returns event flags if a RX transfer termination condition was met or 0 otherwise diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h index f49d91b38a..8f5df68ef2 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/inc/tmpm066_uart.h @@ -59,7 +59,7 @@ extern "C" { uint32_t TIDLE; /*!< The status of TXDx pin after output of the last bit */ uint32_t TXDEMP; /*!< The status of TXDx pin when an under run error - has occurred in SCLK input mode */ + is occured in SCLK input mode */ uint32_t EHOLDTime; /*!< The last bit hold time of TXDx pin in SCLK input mode */ uint32_t IntervalTime; /*!< Setting interval time of continuous transmission which diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c index a6c993cc29..2a90f4a30f 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_i2c.c @@ -246,7 +246,7 @@ void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx) } /** - * @brief Set I2C bus to Master mode and Generate start condition in I2C mode. + * @brief Set I2c bus to Master mode and Generate start condition in I2C mode. * @param I2Cx: Select the I2C channel. * This parameter can be one of the following values: * TSB_I2C0,TSB_I2C1 @@ -262,7 +262,7 @@ void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx) } /** - * @brief Set I2C bus to Master mode and Generate stop condition in I2C mode. + * @brief Set I2c bus to Master mode and Generate stop condition in I2C mode. * @param I2Cx: Select the I2C channel. * This parameter can be one of the following values: * TSB_I2C0,TSB_I2C1 diff --git a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c index 0f1dd33ec9..2dd7cc1b8c 100644 --- a/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c +++ b/targets/TARGET_TOSHIBA/TARGET_TMPM066/Periph_Driver/src/tmpm066_uart.c @@ -1121,7 +1121,7 @@ void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitSt tmp &= (CR_IOC_MASK & CR_SCLKS_MASK & CR_TIDLE_MASK); tmp |= (IOClkSel | InitStruct->InputClkEdge | InitStruct->TIDLE); - /* Set status of TXDx pin when an under run error has occurred + /* Set status of TXDx pin when an under run error is occured and The last bit hold time of TXDx pin in SCLK input mode */ if (IOClkSel == SIO_CLK_SCLKINPUT) { tmp &= (CR_TXDEMP_MASK & CR_EHOLD_MASK); From 1d979213261c92d2c858fbb060281321efd00e7b Mon Sep 17 00:00:00 2001 From: Brendan McDonnell Date: Thu, 8 Mar 2018 11:56:47 -0500 Subject: [PATCH 046/118] revert accidentally-included change from 7094e13891cde91b0ddccda562638dd17e0a2b22 --- .../TARGET_LPC408X/device/system_LPC407x_8x_177x_8x.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/targets/TARGET_NXP/TARGET_LPC408X/device/system_LPC407x_8x_177x_8x.c b/targets/TARGET_NXP/TARGET_LPC408X/device/system_LPC407x_8x_177x_8x.c index 9978362559..835d31b4a5 100644 --- a/targets/TARGET_NXP/TARGET_LPC408X/device/system_LPC407x_8x_177x_8x.c +++ b/targets/TARGET_NXP/TARGET_LPC408X/device/system_LPC407x_8x_177x_8x.c @@ -555,8 +555,7 @@ fpu_init(); LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */ #endif - //TODO: verify correct operation w/ this setting. Refer to Table 18 in UM10562.pdf. - LPC_SC->PBOOST |= 0x00; /* Power Boost control */ + LPC_SC->PBOOST |= 0x03; /* Power Boost control */ #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */ LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A; From f003b98e97266a4b49c50f71887c6bbe3b766dab Mon Sep 17 00:00:00 2001 From: Filip Jagodzinski Date: Tue, 12 Sep 2017 16:41:01 +0200 Subject: [PATCH 047/118] Tests: Drivers: Timeout: Update unit tests Added unit tests for Timeout API. Added unit tests for LowPowerTimeout API. Moved all existing test cases to a header file. --- TESTS/mbed_drivers/lp_timeout/main.cpp | 165 +++----- TESTS/mbed_drivers/timeout/main.cpp | 108 +++--- TESTS/mbed_drivers/timeout/timeout_tests.h | 415 +++++++++++++++++++++ 3 files changed, 518 insertions(+), 170 deletions(-) create mode 100644 TESTS/mbed_drivers/timeout/timeout_tests.h diff --git a/TESTS/mbed_drivers/lp_timeout/main.cpp b/TESTS/mbed_drivers/lp_timeout/main.cpp index 9a16d6bdfb..eaccab90c9 100644 --- a/TESTS/mbed_drivers/lp_timeout/main.cpp +++ b/TESTS/mbed_drivers/lp_timeout/main.cpp @@ -15,138 +15,79 @@ */ #if !DEVICE_LOWPOWERTIMER - #error [NOT_SUPPORTED] Low power timer not supported for this target +#error [NOT_SUPPORTED] Low power timer not supported for this target #endif +#include "mbed.h" +#include "greentea-client/test_env.h" #include "utest/utest.h" #include "unity/unity.h" -#include "greentea-client/test_env.h" - -#include "mbed.h" +#include "../timeout/timeout_tests.h" using namespace utest::v1; -volatile static bool complete; -static LowPowerTimeout lpt; - -/* Timeouts are quite arbitrary due to large number of boards with varying level of accuracy */ -#define LONG_TIMEOUT (100000) -#define SHORT_TIMEOUT (600) - -void cb_done() { - complete = true; -} - -#if DEVICE_SLEEP -void lp_timeout_1s_deepsleep(void) +utest::v1::status_t greentea_failure_handler(const Case * const source, const failure_t reason) { - complete = false; - LowPowerTimer timer; - - /* - * Since deepsleep() may shut down the UART peripheral, we wait for 10ms - * to allow for hardware serial buffers to completely flush. - - * This should be replaced with a better function that checks if the - * hardware buffers are empty. However, such an API does not exist now, - * so we'll use the wait_ms() function for now. - */ - wait_ms(10); - - /* - * We use here the low power timer instead of microsecond timer for start and - * end because the microseconds timer might be disable during deepsleep. - */ - timer.start(); - lpt.attach(&cb_done, 1); - /* Make sure deepsleep is allowed, to go to deepsleep */ - bool deep_sleep_allowed = sleep_manager_can_deep_sleep(); - TEST_ASSERT_TRUE_MESSAGE(deep_sleep_allowed, "Deep sleep should be allowed"); - sleep(); - while (!complete); - - /* It takes longer to wake up from deep sleep */ - TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, timer.read_us()); - TEST_ASSERT_TRUE(complete); -} - -void lp_timeout_1s_sleep(void) -{ - complete = false; - Timer timer; - timer.start(); - - sleep_manager_lock_deep_sleep(); - lpt.attach(&cb_done, 1); - bool deep_sleep_allowed = sleep_manager_can_deep_sleep(); - TEST_ASSERT_FALSE_MESSAGE(deep_sleep_allowed, "Deep sleep should be disallowed"); - sleep(); - while (!complete); - sleep_manager_unlock_deep_sleep(); - - TEST_ASSERT_UINT32_WITHIN(LONG_TIMEOUT, 1000000, timer.read_us()); - TEST_ASSERT_TRUE(complete); -} -#endif /* DEVICE_SLEEP */ - -void lp_timeout_us(uint32_t delay_us, uint32_t tolerance) -{ - complete = false; - Timer timer; - timer.start(); - - lpt.attach_us(&cb_done, delay_us); - while (!complete); - - /* Using RTC which is less accurate */ - TEST_ASSERT_UINT32_WITHIN(tolerance, delay_us, timer.read_us()); - TEST_ASSERT_TRUE(complete); -} - -void lp_timeout_5s(void) -{ - lp_timeout_us(5000000, LONG_TIMEOUT); -} - -void lp_timeout_1s(void) -{ - lp_timeout_us(1000000, LONG_TIMEOUT); -} - -void lp_timeout_1ms(void) -{ - lp_timeout_us(1000, SHORT_TIMEOUT); -} - -void lp_timeout_500us(void) -{ - lp_timeout_us(500, SHORT_TIMEOUT); - -} - -utest::v1::status_t greentea_failure_handler(const Case *const source, const failure_t reason) { greentea_case_failure_abort_handler(source, reason); return STATUS_CONTINUE; } Case cases[] = { - Case("500us LowPowerTimeout", lp_timeout_500us, greentea_failure_handler), - Case("1ms LowPowerTimeout", lp_timeout_1ms, greentea_failure_handler), - Case("1sec LowPowerTimeout", lp_timeout_1s, greentea_failure_handler), - Case("5sec LowPowerTimeout", lp_timeout_5s, greentea_failure_handler), + Case("Callback called once (attach)", test_single_call >), + Case("Callback called once (attach_us)", test_single_call >), + + Case("Callback not called when cancelled (attach)", test_cancel >), + Case("Callback not called when cancelled (attach_us)", test_cancel >), + + Case("Callback override (attach)", test_override >), + Case("Callback override (attach_us)", test_override >), + + Case("Multiple timeouts running in parallel (attach)", test_multiple >), + Case("Multiple timeouts running in parallel (attach_us)", test_multiple >), + + Case("Zero delay (attach)", test_no_wait >), + Case("Zero delay (attach_us)", test_no_wait >), + + Case("10 ms delay accuracy (attach)", test_delay_accuracy, 10000, SHORT_DELTA_US>, + greentea_failure_handler), + Case("10 ms delay accuracy (attach_us)", test_delay_accuracy, 10000, SHORT_DELTA_US>, + greentea_failure_handler), + + Case("1 s delay accuracy (attach)", test_delay_accuracy, 1000000, LONG_DELTA_US>, + greentea_failure_handler), + Case("1 s delay accuracy (attach_us)", test_delay_accuracy, 1000000, LONG_DELTA_US>, + greentea_failure_handler), + + Case("5 s delay accuracy (attach)", test_delay_accuracy, 5000000, LONG_DELTA_US>, + greentea_failure_handler), + Case("5 s delay accuracy (attach_us)", test_delay_accuracy, 5000000, LONG_DELTA_US>, + greentea_failure_handler), + #if DEVICE_SLEEP - Case("1sec LowPowerTimeout from sleep", lp_timeout_1s_sleep, greentea_failure_handler), - Case("1sec LowPowerTimeout from deepsleep", lp_timeout_1s_deepsleep, greentea_failure_handler), -#endif /* DEVICE_SLEEP */ + Case("1 s delay during sleep (attach)", test_sleep, 1000000, LONG_DELTA_US>, + greentea_failure_handler), + Case("1 s delay during sleep (attach_us)", test_sleep, 1000000, LONG_DELTA_US>, + greentea_failure_handler), + + Case("1 s delay during deepsleep (attach)", test_deepsleep, 1000000, LONG_DELTA_US>, + greentea_failure_handler), + Case("1 s delay during deepsleep (attach_us)", test_deepsleep, 1000000, LONG_DELTA_US>, + greentea_failure_handler), +#endif + + Case("Timing drift (attach)", test_drift >), + Case("Timing drift (attach_us)", test_drift >), }; -utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(20, "default_auto"); +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(240, "timing_drift_auto"); return greentea_test_setup_handler(number_of_cases); } Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); -int main() { +int main() +{ Harness::run(specification); } diff --git a/TESTS/mbed_drivers/timeout/main.cpp b/TESTS/mbed_drivers/timeout/main.cpp index 851b947020..acab4fda5c 100644 --- a/TESTS/mbed_drivers/timeout/main.cpp +++ b/TESTS/mbed_drivers/timeout/main.cpp @@ -1,91 +1,83 @@ -/* - * Copyright (c) 2013-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ - - -/* - * Tests is to measure the accuracy of Timeout over a period of time - * - * - * 1) DUT would start to update callback_trigger_count every milli sec - * 2) Host would query what is current count base_time, Device responds by the callback_trigger_count - * 3) Host after waiting for measurement stretch. It will query for device time again final_time. - * 4) Host computes the drift considering base_time, final_time, transport delay and measurement stretch - * 5) Finally host send the results back to device pass/fail based on tolerance. - * 6) More details on tests can be found in timing_drift_auto.py - * - */ - #include "mbed.h" #include "greentea-client/test_env.h" #include "utest/utest.h" #include "unity/unity.h" +#include "timeout_tests.h" using namespace utest::v1; -#define PERIOD_US 10000 - -volatile int ticker_count = 0; -volatile uint32_t callback_trigger_count = 0; -static const int test_timeout = 240; -Timeout timeout; - -void set_incremeant_count() { - timeout.attach_us(set_incremeant_count, PERIOD_US); - ++callback_trigger_count; +utest::v1::status_t greentea_failure_handler(const Case * const source, const failure_t reason) +{ + greentea_case_failure_abort_handler(source, reason); + return STATUS_CONTINUE; } -void test_case_timeout() { +Case cases[] = { + Case("Callback called once (attach)", test_single_call >), + Case("Callback called once (attach_us)", test_single_call >), - char _key[11] = { }; - char _value[128] = { }; - int expected_key = 1; - uint8_t results_size = 0; + Case("Callback not called when cancelled (attach)", test_cancel >), + Case("Callback not called when cancelled (attach_us)", test_cancel >), - greentea_send_kv("timing_drift_check_start", 0); - timeout.attach_us(set_incremeant_count, PERIOD_US); + Case("Callback override (attach)", test_override >), + Case("Callback override (attach_us)", test_override >), - // wait for 1st signal from host - do { - greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); - expected_key = strcmp(_key, "base_time"); - } while (expected_key); + Case("Multiple timeouts running in parallel (attach)", test_multiple >), + Case("Multiple timeouts running in parallel (attach_us)", test_multiple >), - greentea_send_kv(_key, callback_trigger_count * PERIOD_US); + Case("Zero delay (attach)", test_no_wait >), + Case("Zero delay (attach_us)", test_no_wait >), - // wait for 2nd signal from host - greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); - greentea_send_kv(_key, callback_trigger_count * PERIOD_US); + Case("10 ms delay accuracy (attach)", test_delay_accuracy, 10000, SHORT_DELTA_US>, + greentea_failure_handler), + Case("10 ms delay accuracy (attach_us)", test_delay_accuracy, 10000, SHORT_DELTA_US>, + greentea_failure_handler), - //get the results from host - greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); + Case("1 s delay accuracy (attach)", test_delay_accuracy, 1000000, LONG_DELTA_US>, + greentea_failure_handler), + Case("1 s delay accuracy (attach_us)", test_delay_accuracy, 1000000, LONG_DELTA_US>, + greentea_failure_handler), - TEST_ASSERT_EQUAL_STRING_MESSAGE("pass", _key,"Host side script reported a fail..."); -} + Case("5 s delay accuracy (attach)", test_delay_accuracy, 5000000, LONG_DELTA_US>, + greentea_failure_handler), + Case("5 s delay accuracy (attach_us)", test_delay_accuracy, 5000000, LONG_DELTA_US>, + greentea_failure_handler), -// Test casess -Case cases[] = { Case("Timers: toggle on/off", test_case_timeout), }; +#if DEVICE_SLEEP + Case("1 s delay during sleep (attach)", test_sleep, 1000000, LONG_DELTA_US>, + greentea_failure_handler), + Case("1 s delay during sleep (attach_us)", test_sleep, 1000000, LONG_DELTA_US>, + greentea_failure_handler), +#endif -utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { - GREENTEA_SETUP(test_timeout, "timing_drift_auto"); + Case("Timing drift (attach)", test_drift >), + Case("Timing drift (attach_us)", test_drift >), +}; + +utest::v1::status_t greentea_test_setup(const size_t number_of_cases) +{ + GREENTEA_SETUP(240, "timing_drift_auto"); return greentea_test_setup_handler(number_of_cases); } Specification specification(greentea_test_setup, cases, greentea_test_teardown_handler); -int main() { +int main() +{ Harness::run(specification); } diff --git a/TESTS/mbed_drivers/timeout/timeout_tests.h b/TESTS/mbed_drivers/timeout/timeout_tests.h new file mode 100644 index 0000000000..2920e8c243 --- /dev/null +++ b/TESTS/mbed_drivers/timeout/timeout_tests.h @@ -0,0 +1,415 @@ +/* mbed Microcontroller Library + * Copyright (c) 2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_TIMEOUT_TESTS_H +#define MBED_TIMEOUT_TESTS_H + +#include "mbed.h" +#include "unity/unity.h" + +#define NUM_TIMEOUTS 16 +#define DRIFT_TEST_PERIOD_US 10000 + +const float TEST_DELAY_S = 0.01; +const uint32_t TEST_DELAY_MS = 1000.0F * TEST_DELAY_S; +const us_timestamp_t TEST_DELAY_US = 1000000.0F * TEST_DELAY_S; + +/* Timeouts are quite arbitrary due to large number of boards with varying level of accuracy */ +#define LONG_DELTA_US (100000) +#define SHORT_DELTA_US (2000) + +void sem_callback(Semaphore *sem) +{ + sem->release(); +} + +void cnt_callback(volatile uint32_t *cnt) +{ + (*cnt)++; +} + +template +class AttachTester: public TimeoutType { +public: + void attach_callback(Callback func, us_timestamp_t delay_us) + { + TimeoutType::attach(func, (float) delay_us / 1000000.0f); + } +}; + +template +class AttachUSTester: public TimeoutType { +public: + void attach_callback(Callback func, us_timestamp_t delay_us) + { + TimeoutType::attach_us(func, delay_us); + } +}; + +/** Template for tests: callback called once + * + * Test callback called once + * Given a Timeout object with a callback attached with @a attach() + * When given time elapses + * Then the callback is called exactly one time + * + * Test callback called once + * Given a Timeout object with a callback attached with @a attach_us() + * When given time elapses + * Then the callback is called exactly one time + */ +template +void test_single_call(void) +{ + Semaphore sem(0, 1); + T timeout; + + timeout.attach_callback(mbed::callback(sem_callback, &sem), TEST_DELAY_US); + + int32_t sem_slots = sem.wait(0); + TEST_ASSERT_EQUAL(0, sem_slots); + + sem_slots = sem.wait(TEST_DELAY_MS + 1); + TEST_ASSERT_EQUAL(1, sem_slots); + + sem_slots = sem.wait(TEST_DELAY_MS + 1); + TEST_ASSERT_EQUAL(0, sem_slots); + + timeout.detach(); +} + +/** Template for tests: callback not called when cancelled + * + * Test callback not called when cancelled + * Given a Timeout object with a callback attached with @a attach() + * When the callback is detached before being called + * Then the callback is never called + * + * Test callback not called when cancelled + * Given a Timeout object with a callback attached with @a attach_us() + * When the callback is detached before being called + * Then the callback is never called + */ +template +void test_cancel(void) +{ + Semaphore sem(0, 1); + T timeout; + + timeout.attach_callback(mbed::callback(sem_callback, &sem), 2.0f * TEST_DELAY_US); + + int32_t sem_slots = sem.wait(TEST_DELAY_MS); + TEST_ASSERT_EQUAL(0, sem_slots); + timeout.detach(); + + sem_slots = sem.wait(TEST_DELAY_MS + 1); + TEST_ASSERT_EQUAL(0, sem_slots); +} + +/** Template for tests: callback override + * + * Test callback override + * Given a Timeout object with a callback attached with @a attach() + * When another callback is attached before first one is called + * and second callback's delay elapses + * Then the second callback is called + * and the first callback is never called + * + * Test callback override + * Given a Timeout object with a callback attached with @a attach_us() + * When another callback is attached before first one is called + * and second callback's delay elapses + * Then the second callback is called + * and the first callback is never called + */ +template +void test_override(void) +{ + Semaphore sem1(0, 1); + Semaphore sem2(0, 1); + T timeout; + + timeout.attach_callback(mbed::callback(sem_callback, &sem1), 2.0f * TEST_DELAY_US); + + int32_t sem_slots = sem1.wait(TEST_DELAY_MS); + TEST_ASSERT_EQUAL(0, sem_slots); + timeout.attach_callback(mbed::callback(sem_callback, &sem2), 2.0f * TEST_DELAY_US); + + sem_slots = sem2.wait(2 * TEST_DELAY_MS + 1); + TEST_ASSERT_EQUAL(1, sem_slots); + sem_slots = sem1.wait(0); + TEST_ASSERT_EQUAL(0, sem_slots); + + timeout.detach(); +} + +/** Template for tests: multiple Timeouts + * + * Test multiple Timeouts + * Given multiple separate Timeout objects + * When a callback is attached to all of these Timeout objects with @a attach() + * and delay for every Timeout elapses + * Then all callbacks are called + * + * Test multiple Timeouts + * Given multiple separate Timeout objects + * When a callback is attached to all of these Timeout objects with @a attach_us() + * and delay for every Timeout elapses + * Then all callbacks are called + */ +template +void test_multiple(void) +{ + volatile uint32_t callback_count = 0; + T timeouts[NUM_TIMEOUTS]; + for (size_t i = 0; i < NUM_TIMEOUTS; i++) { + timeouts[i].attach_callback(mbed::callback(cnt_callback, &callback_count), TEST_DELAY_US); + } + Thread::wait(TEST_DELAY_MS + 1); + TEST_ASSERT_EQUAL(NUM_TIMEOUTS, callback_count); +} + +/** Template for tests: zero delay + * + * Test zero delay + * Given a Timeout object + * When a callback is attached with 0.0 s delay, with @a attach() + * Then the callback is called instantly + * + * Test zero delay + * Given a Timeout object + * When a callback is attached with 0.0 s delay, with @a attach_us() + * Then the callback is called instantly + */ +template +void test_no_wait(void) +{ + Semaphore sem(0, 1); + T timeout; + timeout.attach_callback(mbed::callback(sem_callback, &sem), 0ULL); + + int32_t sem_slots = sem.wait(0); + TEST_ASSERT_EQUAL(1, sem_slots); + timeout.detach(); +} + +/** Template for tests: accuracy of timeout delay + * + * Test delay accuracy + * Given a Timeout object with a callback attached with @a attach() + * When the callback is called + * Then elapsed time matches given delay + * + * Test delay accuracy + * Given a Timeout object with a callback attached with @a attach_us() + * When the callback is called + * Then elapsed time matches given delay + */ +template +void test_delay_accuracy(void) +{ + Semaphore sem(0, 1); + T timeout; + Timer timer; + + timer.start(); + timeout.attach_callback(mbed::callback(sem_callback, &sem), delay_us); + + int32_t sem_slots = sem.wait(osWaitForever); + timer.stop(); + TEST_ASSERT_EQUAL(1, sem_slots); + TEST_ASSERT_UINT64_WITHIN(delta_us, delay_us, timer.read_high_resolution_us()); + + timeout.detach(); +} + +#if DEVICE_SLEEP +/** Template for tests: timeout during sleep + * + * Test timeout during sleep + * Given a Timeout object with a callback attached with @a attach() + * and the uC in a sleep mode + * When given delay elapses + * Then the callback is called + * and elapsed time matches given delay + * + * Test timeout during sleep + * Given a Timeout object with a callback attached with @a attach_us() + * and the uC in a sleep mode + * When given delay elapses + * Then the callback is called + * and elapsed time matches given delay + */ +template +void test_sleep(void) +{ + Semaphore sem(0, 1); + T timeout; + Timer timer; + + sleep_manager_lock_deep_sleep(); + timer.start(); + timeout.attach_callback(mbed::callback(sem_callback, &sem), delay_us); + + bool deep_sleep_allowed = sleep_manager_can_deep_sleep(); + TEST_ASSERT_FALSE_MESSAGE(deep_sleep_allowed, "Deep sleep should be disallowed"); + while (sem.wait(0) != 1) { + sleep(); + } + timer.stop(); + + sleep_manager_unlock_deep_sleep(); + TEST_ASSERT_UINT64_WITHIN(delta_us, delay_us, timer.read_high_resolution_us()); + + timeout.detach(); +} + +#if DEVICE_LOWPOWERTIMER +/** Template for tests: timeout during deepsleep + * + * Test timeout during deepsleep + * Given a LowPowerTimeout object with a callback attached with @a attach() + * and the uC in a deepsleep mode + * When given delay elapses + * Then the callback is called + * and elapsed time matches given delay + * + * Test timeout during deepsleep + * Given a LowPowerTimeout object with a callback attached with @a attach_us() + * and the uC in a deepsleep mode + * When given delay elapses + * Then the callback is called + * and elapsed time matches given delay + */ +template +void test_deepsleep(void) +{ + Semaphore sem(0, 1); + T timeout; + /* + * We use here the low power timer instead of microsecond timer for start and + * end because the microseconds timer might be disabled during deepsleep. + */ + LowPowerTimer timer; + + /* + * Since deepsleep() may shut down the UART peripheral, we wait for 10ms + * to allow for hardware serial buffers to completely flush. + + * This should be replaced with a better function that checks if the + * hardware buffers are empty. However, such an API does not exist now, + * so we'll use the wait_ms() function for now. + */ + wait_ms(10); + + timer.start(); + timeout.attach_callback(mbed::callback(sem_callback, &sem), delay_us); + + bool deep_sleep_allowed = sleep_manager_can_deep_sleep(); + TEST_ASSERT_TRUE_MESSAGE(deep_sleep_allowed, "Deep sleep should be allowed"); + while (sem.wait(0) != 1) { + sleep(); + } + timer.stop(); + + TEST_ASSERT_UINT64_WITHIN(delta_us, delay_us, timer.read_high_resolution_us()); + + timeout.detach(); +} +#endif +#endif + +template +class TimeoutDriftTester { +public: + TimeoutDriftTester(us_timestamp_t period = 1000) : + _callback_count(0), _period(period), _timeout() + { + } + + void reschedule_callback(void) + { + _timeout.attach_callback(mbed::callback(this, &TimeoutDriftTester::reschedule_callback), _period); + _callback_count++; + } + + void detach_callback(void) + { + _timeout.detach(); + } + + uint32_t get_callback_count(void) + { + return _callback_count; + } + +private: + volatile uint32_t _callback_count; + us_timestamp_t _period; + TimeoutTesterType _timeout; +}; + +/** Template for tests: accuracy of timeout delay scheduled repeatedly + * + * Test time drift -- device part + * Given a Timeout object with a callback repeatedly attached with @a attach() + * When the testing host computes test duration based on values received from uC + * Then computed time and actual time measured by host are equal within given tolerance + * + * Test time drift -- device part + * Given a Timeout object with a callback repeatedly attached with @a attach_us() + * When the testing host computes test duration based on values received from uC + * Then computed time and actual time measured by host are equal within given tolerance + * + * Original description: + * 1) DUT would start to update callback_trigger_count every milli sec + * 2) Host would query what is current count base_time, Device responds by the callback_trigger_count + * 3) Host after waiting for measurement stretch. It will query for device time again final_time. + * 4) Host computes the drift considering base_time, final_time, transport delay and measurement stretch + * 5) Finally host send the results back to device pass/fail based on tolerance. + * 6) More details on tests can be found in timing_drift_auto.py + */ +template +void test_drift(void) +{ + char _key[11] = { }; + char _value[128] = { }; + int expected_key = 1; + TimeoutDriftTester timeout(DRIFT_TEST_PERIOD_US); + + greentea_send_kv("timing_drift_check_start", 0); + timeout.reschedule_callback(); + + // wait for 1st signal from host + do { + greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); + expected_key = strcmp(_key, "base_time"); + } while (expected_key); + + greentea_send_kv(_key, timeout.get_callback_count() * DRIFT_TEST_PERIOD_US); + + // wait for 2nd signal from host + greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); + greentea_send_kv(_key, timeout.get_callback_count() * DRIFT_TEST_PERIOD_US); + + timeout.detach_callback(); + + //get the results from host + greentea_parse_kv(_key, _value, sizeof(_key), sizeof(_value)); + + TEST_ASSERT_EQUAL_STRING_MESSAGE("pass", _key, "Host script reported a failure"); +} + +#endif From d63f07bd6f70f09ab386e3f645daa95cfbe882b5 Mon Sep 17 00:00:00 2001 From: Kevin Bracey Date: Wed, 14 Feb 2018 14:28:44 +0200 Subject: [PATCH 048/118] mbed-mesh-api: add JSON help --- .../mbed-mesh-api/mbed_lib.json | 125 ++++++++++++++---- 1 file changed, 100 insertions(+), 25 deletions(-) diff --git a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json index f3a1cd359c..532a5b902a 100644 --- a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json +++ b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json @@ -1,30 +1,105 @@ { "name": "mbed-mesh-api", "config": { - "heap-size": 32500, - "use-malloc-for-heap": false, - "6lowpan-nd-channel-mask": "0x7fff800", - "6lowpan-nd-channel-page": 0, - "6lowpan-nd-channel": 0, - "6lowpan-nd-panid-filter": "0xffff", - "6lowpan-nd-security-mode": "NONE", - "6lowpan-nd-psk-key-id": 1, - "6lowpan-nd-psk-key": "{0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf}", - "6lowpan-nd-sec-level": 5, - "6lowpan-nd-device-type": "NET_6LOWPAN_ROUTER", - "thread-pskd": "\"ABCDEFGH\"", - "thread-use-static-link-config": true, - "thread-config-channel-mask": "0x7fff800", - "thread-config-channel-page": 0, - "thread-config-channel": 22, - "thread-config-panid": "0x0700", - "thread-config-network-name": "\"Thread Network\"", - "thread-config-commissioning-dataset-timestamp": "0x10000", - "thread-config-extended-panid": "{0xf1, 0xb5, 0xa1, 0xb2,0xc4, 0xd5, 0xa1, 0xbd }", - "thread-master-key": "{0x10, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff}", - "thread-config-ml-prefix": "{0xfd, 0x0, 0x0d, 0xb8, 0x0, 0x0, 0x0, 0x0}", - "thread-config-pskc": "{0xc8, 0xa6, 0x2e, 0xae, 0xf3, 0x68, 0xf3, 0x46, 0xa9, 0x9e, 0x57, 0x85, 0x98, 0x9d, 0x1c, 0xd0}", - "thread-device-type": "MESH_DEVICE_TYPE_THREAD_ROUTER", - "thread-security-policy": 255 + "heap-size": { + "help": "Nanostack's heap size (bytes: 0-65534)", + "value": 32500 + }, + "use-malloc-for-heap": { + "help": "Use `malloc()` for reserving the internal heap.", + "value": false + }, + "6lowpan-nd-channel-mask": { + "help": "Channel mask, bit mask of channels to use.", + "value": "0x7fff800" + }, + "6lowpan-nd-channel-page": { + "help": "0 for 2.4 GHz and 2 for sub-GHz radios.", + "value": 0 + }, + "6lowpan-nd-channel": { + "help": "RF channel to use when `channel_mask` is not defined (0-26).", + "value": 0 + }, + "6lowpan-nd-panid-filter": { + "help": "Beacon PAN ID filter, 0xffff means no filtering.", + "value": "0xffff" + }, + "6lowpan-nd-security-mode": { + "help": "NONE or PSK to use either no security, or pre-shared network key.", + "value": "NONE" + }, + "6lowpan-nd-psk-key-id": { + "help": "PSK key ID when PSK is enabled.", + "value": 1 + }, + "6lowpan-nd-psk-key": { + "help": "Pre-shared network key.", + "value": "{0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf}" + }, + "6lowpan-nd-sec-level": { + "help": "Network security level (1-7). Use default `5`.", + "value": 5 + }, + "6lowpan-nd-device-type": { + "help": "Device mode (NET_6LOWPAN_ROUTER or NET_6LOWPAN_HOST). Router is routing packets from other device, creating a mesh network.", + "value": "NET_6LOWPAN_ROUTER" + }, + "thread-pskd": { + "help": "Human-scaled commissioning credentials (string 6-255 chars).", + "value": "\"ABCDEFGH\"" + }, + "thread-use-static-link-config": { + "help": "True: Use the below link config, False: Use commissioning, ignore the below link config.", + "value": true + }, + "thread-config-channel-mask": { + "help": "Channel mask, 0x7ffff800 scans all channels.", + "value": "0x7fff800" + }, + "thread-config-channel-page": { + "help": "Channel page, 0 for 2.4 GHz radio.", + "value": 0 + }, + "thread-config-channel": { + "help": "RF channel to use. (11-26)", + "value": 22 + }, + "thread-config-panid": { + "help": "Network identifier (0-0xFFFF)", + "value": "0x0700" + }, + "thread-config-network-name": { + "help": "Network name", + "value": "\"Thread Network\"" + }, + "thread-config-commissioning-dataset-timestamp": { + "help": "[48 bit timestamp seconds]-[15 bit timestamp ticks]-[U bit] (0-0xFFFFFFFFFFFFFFFF)", + "value": "0x10000" + }, + "thread-config-extended-panid": { + "help": "Extended PAN ID.", + "value": "{0xf1, 0xb5, 0xa1, 0xb2,0xc4, 0xd5, 0xa1, 0xbd }" + }, + "thread-master-key": { + "help": "Network master key.", + "value": "{0x10, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff}" + }, + "thread-config-ml-prefix": { + "help": "Mesh Local prefix.", + "value": "{0xfd, 0x0, 0x0d, 0xb8, 0x0, 0x0, 0x0, 0x0}" + }, + "thread-config-pskc": { + "help": "Pre-Shared Key for the Commissioner.", + "value": "{0xc8, 0xa6, 0x2e, 0xae, 0xf3, 0x68, 0xf3, 0x46, 0xa9, 0x9e, 0x57, 0x85, 0x98, 0x9d, 0x1c, 0xd0}" + }, + "thread-device-type": { + "help": "Supported device operating modes: MESH_DEVICE_TYPE_THREAD_ROUTER, MESH_DEVICE_TYPE_THREAD_SLEEPY_END_DEVICE, MESH_DEVICE_TYPE_THREAD_MINIMAL_END_DEVICE", + "value": "MESH_DEVICE_TYPE_THREAD_ROUTER" + }, + "thread-security-policy": { + "help": "Commissioning security policy bits (0-0xFF)", + "value": 255 + } } } From 2df1f47ed2afd61b8676da58a9ca2f496d5ceb16 Mon Sep 17 00:00:00 2001 From: Kevin Bracey Date: Tue, 6 Mar 2018 10:58:34 +0200 Subject: [PATCH 049/118] mbed-mesh-api: revise some Thread JSON help --- .../nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json index 532a5b902a..5ccb713378 100644 --- a/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json +++ b/features/nanostack/FEATURE_NANOSTACK/mbed-mesh-api/mbed_lib.json @@ -46,7 +46,7 @@ "value": "NET_6LOWPAN_ROUTER" }, "thread-pskd": { - "help": "Human-scaled commissioning credentials (string 6-255 chars).", + "help": "Human-scaled commissioning credentials. Uppercase alphanumeric string (0-9, A-Y excluding I, O, Q and Z), 6-32 characters.", "value": "\"ABCDEFGH\"" }, "thread-use-static-link-config": { @@ -70,7 +70,7 @@ "value": "0x0700" }, "thread-config-network-name": { - "help": "Network name", + "help": "Network name (max 16 characters)", "value": "\"Thread Network\"" }, "thread-config-commissioning-dataset-timestamp": { From 3508c200e08eb444bc69282db478efa577ad9565 Mon Sep 17 00:00:00 2001 From: Juha Ylinen Date: Wed, 7 Mar 2018 14:14:35 +0200 Subject: [PATCH 050/118] rtl8195am - improve credentials handling Add checks for empty strings set_channel() not supported for STA mode wifi driver --- .../TARGET_AMEBA/RTWInterface.cpp | 30 ++++++++++++------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp index 92b3a91b56..6b64f8609b 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp +++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp @@ -86,7 +86,7 @@ static rtw_result_t scan_result_handler( rtw_scan_handler_result_t* malloced_sca } RTWInterface::RTWInterface(bool debug) - : _dhcp(true), _ip_address(), _netmask(), _gateway() + : _dhcp(true), _ssid(), _pass(), _ip_address(), _netmask(), _gateway() { emac_interface_t *emac; int ret; @@ -135,7 +135,7 @@ nsapi_error_t RTWInterface::set_dhcp(bool dhcp) */ nsapi_error_t RTWInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) { - if(!ssid) { + if(!ssid || (strlen(ssid) == 0)) { return NSAPI_ERROR_PARAMETER; } @@ -149,6 +149,9 @@ nsapi_error_t RTWInterface::set_credentials(const char *ssid, const char *pass, } break; case NSAPI_SECURITY_NONE: + if(pass && strlen(pass) > 0) { + return NSAPI_ERROR_PARAMETER; + } break; default: return NSAPI_ERROR_PARAMETER; @@ -166,7 +169,8 @@ nsapi_error_t RTWInterface::connect() int ret; rtw_security_t sec; - if (!_ssid || (!_pass && _security != NSAPI_SECURITY_NONE)) { + if (!_ssid || (strlen(_ssid) == 0) || + (!_pass && _security != NSAPI_SECURITY_NONE)) { printf("Invalid credentials\r\n"); return NSAPI_ERROR_PARAMETER; } @@ -187,11 +191,6 @@ nsapi_error_t RTWInterface::connect() return NSAPI_ERROR_PARAMETER; } - if(_channel > 0 && _channel < 14){ - uint8_t pscan_config = PSCAN_ENABLE; - wifi_set_pscan_chan(&_channel, &pscan_config, 1); - } - ret = wifi_connect(_ssid, sec, _pass, strlen(_ssid), strlen(_pass), 0, (void *)NULL); if (ret != RTW_SUCCESS) { printf("failed: %d\r\n", ret); @@ -229,7 +228,10 @@ nsapi_error_t RTWInterface::scan(WiFiAccessPoint *res, unsigned count) nsapi_error_t RTWInterface::set_channel(uint8_t channel) { - _channel = channel; + // Not supported for STA mode wifi driver + if (channel != 0) + return NSAPI_ERROR_UNSUPPORTED; + return NSAPI_ERROR_OK; } @@ -244,8 +246,14 @@ int8_t RTWInterface::get_rssi() nsapi_error_t RTWInterface::connect(const char *ssid, const char *pass, nsapi_security_t security, uint8_t channel) { - set_credentials(ssid, pass, security); - set_channel(channel); + nsapi_error_t ret; + + ret = set_credentials(ssid, pass, security); + if(ret != NSAPI_ERROR_OK) return ret; + + ret = set_channel(channel); + if(ret != NSAPI_ERROR_OK) return ret; + return connect(); } From 20cefbf462ef25a8f9647187015c3851b87ec8b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Tue, 13 Mar 2018 13:52:05 +0200 Subject: [PATCH 051/118] Cellular: Fixed sms unit tests. --- .../at/at_cellularsms/test_at_cellularsms.cpp | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/features/cellular/UNITTESTS/at/at_cellularsms/test_at_cellularsms.cpp b/features/cellular/UNITTESTS/at/at_cellularsms/test_at_cellularsms.cpp index f505be0db1..9faac21d67 100644 --- a/features/cellular/UNITTESTS/at/at_cellularsms/test_at_cellularsms.cpp +++ b/features/cellular/UNITTESTS/at/at_cellularsms/test_at_cellularsms.cpp @@ -68,38 +68,37 @@ void Test_AT_CellularSMS::test_AT_CellularSMS_send_sms() ATHandler at(&fh1, que, 0, ","); AT_CellularSMS sms(at); - CHECK(NSAPI_ERROR_PARAMETER == sms.send_sms(NULL, "2", 1)); + LONGS_EQUAL(NSAPI_ERROR_PARAMETER, sms.send_sms(NULL, "2", 1)); sms.initialize(CellularSMS::CellularSMSMmodeText); ATHandler_stub::size_value = 1; - CHECK(1 == sms.send_sms("1", "22", 2)); + LONGS_EQUAL(1, sms.send_sms("1", "22", 2)); ATHandler_stub::size_value = 2; - CHECK(2 == sms.send_sms("1", "22", 2)); + LONGS_EQUAL(2, sms.send_sms("1", "22", 2)); + ATHandler_stub::return_given_size = true; // PDU mode write is much longer than than msg len sms.initialize(CellularSMS::CellularSMSMmodePDU); - CHECK(2 == sms.send_sms("1", "23", 2)); + LONGS_EQUAL(2, sms.send_sms("1", "23", 2));; ATHandler_stub::nsapi_error_ok_counter = 1; ATHandler_stub::size_value = 32; ATHandler_stub::nsapi_error_value = NSAPI_ERROR_AUTH_FAILURE; - CHECK(NSAPI_ERROR_AUTH_FAILURE == sms.send_sms("1", "23232323", 8)); + LONGS_EQUAL(NSAPI_ERROR_AUTH_FAILURE, sms.send_sms("1", "23232323", 8)); ATHandler_stub::nsapi_error_ok_counter = 2; ATHandler_stub::size_value = 32; ATHandler_stub::nsapi_error_value = NSAPI_ERROR_AUTH_FAILURE; - CHECK(NSAPI_ERROR_AUTH_FAILURE == sms.send_sms("1", "23232323", 8)); + LONGS_EQUAL(NSAPI_ERROR_AUTH_FAILURE, sms.send_sms("1", "23232323", 8)); ATHandler_stub::nsapi_error_value = NSAPI_ERROR_OK; char table[] = "232323232323232323232323232323232323232323232323232323\ 232323232323232323232323232323232323232323232323232323\ 232323232323232323232323232323232323232323232323232323\ 23232323232323232323232323232323232323\0"; - ATHandler_stub::size_value = 0; - ATHandler_stub::return_given_size = true; - CHECK(218 == sms.send_sms("1", table, strlen(table))); - CHECK(218 == sms.send_sms("12", table, strlen(table))); + LONGS_EQUAL(strlen(table), sms.send_sms("1", table, strlen(table))); + LONGS_EQUAL(strlen(table), sms.send_sms("12", table, strlen(table))); } From 2af9b5cf8ba115fe3d9464ad491aaaf87f37d69a Mon Sep 17 00:00:00 2001 From: Teemu Kultala Date: Mon, 12 Mar 2018 11:51:27 +0200 Subject: [PATCH 052/118] callback API added --- .../cellular/framework/API/CellularNetwork.h | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/features/cellular/framework/API/CellularNetwork.h b/features/cellular/framework/API/CellularNetwork.h index 672b08b9f1..c85df16e8d 100644 --- a/features/cellular/framework/API/CellularNetwork.h +++ b/features/cellular/framework/API/CellularNetwork.h @@ -381,6 +381,30 @@ public: * @return NSAPI_ERROR_OK on success, negative error code on failure */ virtual nsapi_error_t get_operator_params(int &format, operator_t &operator_params) = 0; + + /** Register callback for status reporting + * + * The specified status callback function will be called on status changes + * on the network. The parameters on the callback are the event type and + * event-type dependent reason parameter. + * + * @param status_cb The callback for status changes + */ + virtual void attach(mbed::Callback status_cb) = 0; + + /** Get the connection status + * + * @return The connection status according to ConnectionStatusType + */ + virtual nsapi_connection_status_t get_connection_status() const = 0; + + /** Set blocking status of connect() which by default should be blocking + * + * @param blocking true if connect is blocking + * @return 0 on success, negative error code on failure + */ + virtual nsapi_error_t set_blocking(bool blocking) = 0; + }; } // namespace mbed From 90da5a50372e177733dd3757142876d02f38fa69 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Wed, 14 Mar 2018 11:03:39 -0500 Subject: [PATCH 053/118] Convert option list to unicode --- tools/utils.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/utils.py b/tools/utils.py index 1d4f7ef9c8..640403fe00 100644 --- a/tools/utils.py +++ b/tools/utils.py @@ -393,6 +393,8 @@ def argparse_force_type(case): """ def middle(lst, type_name): """ The parser type generator""" + if not isinstance(lst[0], unicode): + lst = [o.decode() for o in lst] def parse_type(string): """ The parser type""" if not isinstance(string, unicode): From 1525bc0f2b3300bddab49b24d46cebfa3079a008 Mon Sep 17 00:00:00 2001 From: David Saada Date: Wed, 14 Mar 2018 16:15:48 +0200 Subject: [PATCH 054/118] NVStore: add comments in header file for Doxygen formatting sake. --- features/nvstore/source/nvstore.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/features/nvstore/source/nvstore.h b/features/nvstore/source/nvstore.h index 4272579402..8d2f7d26d1 100644 --- a/features/nvstore/source/nvstore.h +++ b/features/nvstore/source/nvstore.h @@ -50,6 +50,11 @@ typedef enum { // defines 2 areas - active and nonactive, not configurable #define NVSTORE_NUM_AREAS 2 +/** NVStore class + * + * Class for storing data by keys in the internal flash + */ + class NVStore : private mbed::NonCopyable { public: @@ -399,6 +404,7 @@ private: int do_set(uint16_t key, uint16_t buf_size, const void *buf, uint16_t flags); }; +/** @}*/ #endif // NVSTORE_ENABLED From abb9c74d1385d3cccca87f1b1536b7a09f5f74cf Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Tue, 13 Mar 2018 12:01:20 +0000 Subject: [PATCH 055/118] STM32L486: fix two ram region define for GCC ARM Based on the changes for other targets, these 2 were left. --- targets/targets.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/targets.json b/targets/targets.json index c67a0c338c..9af741146f 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1609,7 +1609,7 @@ } }, "detect_code": ["0827"], - "macros_add": ["USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"], + "macros_add": ["USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT", "TWO_RAM_REGIONS"], "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["2", "5"], "device_name": "STM32L486RG" @@ -1626,7 +1626,7 @@ } }, "detect_code": ["0460"], - "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "WISE_1570"], + "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "WISE_1570", "TWO_RAM_REGIONS"], "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["5"], "device_name": "STM32L486RG" From 4b31413f9cf8046bd12ff16f91b29242f04241ee Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Tue, 13 Mar 2018 13:52:11 +0000 Subject: [PATCH 056/118] WISE_1570: use hex as output Fixes #6252. Use hex rather than binary - use the hex format validation. --- targets/targets.json | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 9af741146f..96961d38d6 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1629,7 +1629,8 @@ "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "WISE_1570", "TWO_RAM_REGIONS"], "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], "release_versions": ["5"], - "device_name": "STM32L486RG" + "device_name": "STM32L486RG", + "OUTPUT_EXT": "hex" }, "ARCH_MAX": { "inherits": ["FAMILY_STM32"], From 322fe964405eab7687a8398c10b2894c59e93e09 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 14 Mar 2018 11:12:29 +0100 Subject: [PATCH 057/118] STM32 RTC init When LSE is configured for RTC, LSI is not affected --- targets/TARGET_STM/rtc_api.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 1d04db7b88..34559869bf 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -58,10 +58,9 @@ void rtc_init(void) } #if MBED_CONF_TARGET_LSE_AVAILABLE - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! RCC_OscInitStruct.LSEState = RCC_LSE_ON; - RCC_OscInitStruct.LSIState = RCC_LSI_OFF; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { error("Cannot initialize RTC with LSE\n"); @@ -81,9 +80,8 @@ void rtc_init(void) __HAL_RCC_BACKUPRESET_RELEASE(); // Enable LSI clock - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured! - RCC_OscInitStruct.LSEState = RCC_LSE_OFF; RCC_OscInitStruct.LSIState = RCC_LSI_ON; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { error("Cannot initialize RTC with LSI\n"); From 941dccac1448c8d5d70f6a11e45c5b439ffc814f Mon Sep 17 00:00:00 2001 From: Alan Chuang Date: Wed, 14 Mar 2018 19:07:42 +0800 Subject: [PATCH 058/118] Enable iar export option for MTB_ADV_WISE_1510 --- tools/export/iar/iar_definitions.json | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index a4c29003f9..748c6a909d 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -1,4 +1,7 @@ { + "STM32L443RC": { + "OGChipSelectEditMenu": "STM32L443RC\tST STM32L443RC" + }, "STM32L496ZG": { "OGChipSelectEditMenu": "STM32L496ZG\tST STM32L496ZG" }, From c2b61e5472d3fe3ef4560620182577636772129d Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Thu, 15 Feb 2018 16:44:51 -0600 Subject: [PATCH 059/118] Removed mbed 2 builds from Travis --- .travis.yml | 34 ---------------------------------- 1 file changed, 34 deletions(-) diff --git a/.travis.yml b/.travis.yml index 9de3678080..ff8445a5fa 100644 --- a/.travis.yml +++ b/.travis.yml @@ -187,37 +187,3 @@ matrix: STATUSM="$STATUSM ($(python -c "print '%+.2f' % (100*($CURR-$PREV)/$PREV.0)")%)" fi - bash -c "$STATUS" success "$STATUSM" - - - &mbed-2 - env: NAME=mbed2-NXP - install: - # Install dependencies - - export GCC_DIR=$HOME/gcc-arm-none-eabi-6-2017-q2-update - - export GCC_ARCHIVE=$HOME/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 - - export GCC_URL=https://developer.arm.com/-/media/Files/downloads/gnu-rm/6-2017q2/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2?revision=2cc92fb5-3e0e-402d-9197-bdfc8224d8a5?product=GNU%20Arm%20Embedded%20Toolchain,64-bit,,Linux,6-2017-q2-update - - if [ ! -e $GCC_DIR/bin/arm-none-eabi-gcc ]; then wget $GCC_URL -O $GCC_ARCHIVE; tar xfj $GCC_ARCHIVE -C $HOME; fi - - export PATH=$PATH:$GCC_DIR/bin - - pip install -r requirements.txt - # Print versions we use - - arm-none-eabi-gcc --version - - python --version - before_script: - # Create BUILD directory for tests - - mkdir BUILD - script: - # Run local mbed 2 testing - - python -u tools/build_travis.py --vendor "${NAME#mbed2-}" - - <<: *mbed-2 - env: NAME=mbed2-STM - - <<: *mbed-2 - env: NAME=mbed2-NORDIC - - <<: *mbed-2 - env: NAME=mbed2-SILICON_LABS - - <<: *mbed-2 - env: NAME=mbed2-MAXIM - - <<: *mbed-2 - env: NAME=mbed2-ATMEL - - <<: *mbed-2 - env: NAME=mbed2-NUVOTON - - <<: *mbed-2 - env: NAME=mbed2-RENESAS From 8b557f2317fbd3ab3562eb65d0f7382c31c7c4ca Mon Sep 17 00:00:00 2001 From: zzw Date: Mon, 12 Mar 2018 14:10:40 +0800 Subject: [PATCH 060/118] rtl8195am : fix gpio toggle slow Ameba has two memory blocks: SDRAM(2M) and SRAM(512KB). SRAM has better access performance than SDRAM. So some timing critical codes must be moved to SRAM. fix for mbed-os issue #5778 rebase for #6289 --- .../device/TOOLCHAIN_ARM_STD/rtl8195a.sct | 20 ++++++++++++------- .../device/TOOLCHAIN_GCC_ARM/rtl8195a.ld | 19 +++++++++--------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct index 1485827255..1b9ee2aeb0 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct @@ -22,17 +22,23 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { *(i.mbedtls*) *libc.a (+RO) *rtx_*.o (+RO) + *main*.o (+RO) + *lib_peripheral_mbed_arm.ar (+RO) + *_api*.o (+RO) } RW_IRAM1 +0 UNINIT FIXED { *rtl8195a_crypto*.o(+RW) *libc.a (+RW) - *(.sdram.data*) + *main*.o (+RW) *lib_peripheral_mbed_arm.ar (+RW) - *rtl8195a_crypto*.o(+ZI, COMMON) - *libc.a (+ZI, COMMON) - *(.bss.thread_stack_main) - *lib_peripheral_mbed_arm.ar (+ZI, COMMON) + *_api*.o (+RW) + *rtl8195a_crypto*.o(+ZI) + *libc.a (+ZI) + *main*.o (+ZI) + *lib_peripheral_mbed_arm.ar (+ZI) + *_api*.o (+ZI) + *mbed_boot*.o (+ZI) } ARM_LIB_STACK (0x10070000 - 0x1000) EMPTY 0x1000 { @@ -41,8 +47,8 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { LR_TCM 0x1FFF0000 0x10000 { TCM_OVERLAY 0x1FFF0000 0x10000 { - *lwip_mem*.o(.bss*) - *lwip_memp*.o(.bss*) + *lwip_mem*.o(+ZI) + *lwip_memp*.o(+ZI) *.o(.tcm.heap*) } } diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld index ed3661c6af..a82398e380 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld @@ -67,18 +67,17 @@ SECTIONS .text.sram1 : { . = ALIGN(4); - *rtl8195a_crypto.o (.text* .rodata*) + *rtl8195a_crypto*.o (.text* .rodata*) *mbedtls*.o (.text* .rodata*) *libc.a: (.text* .rodata*) + *lib_peripheral_mbed_gcc.a: (.text* .rodata*) + *_api*.o (.text* .rodata*) + *main*.o (.text* .rodata*) } > SRAM1 .text.sram2 : { . = ALIGN(4); - *(.mon.ram.text*) - *(.hal.flash.text*) - *(.hal.sdrc.text*) - *(.hal.gpio.text*) *(.text*) KEEP(*(.init)) @@ -165,9 +164,11 @@ SECTIONS .bss.sram1 (NOLOAD) : { __bss_sram_start__ = .; - *rtl8195a_crypto.o (.bss* COMMON) + *rtl8195a_crypto*.o (.bss* COMMON) *mbedtls*.o (.bss* COMMON) *(.bss.thread_stack_main) + *lib_peripheral_mbed_gcc.a: (.bss* COMMON) + *mbed_boot*.o (.bss* COMMON) __bss_sram_end__ = .; } > SRAM1 @@ -198,11 +199,11 @@ SECTIONS __HeapLimit = .; } > SRAM1 - .TCM_overlay : + .TCM_overlay (NOLOAD): { __bss_dtcm_start__ = .; - *lwip_mem.o (.bss*) - *lwip_memp.o (.bss*) + *lwip_mem*.o (.bss* COMMON) + *lwip_memp*.o (.bss* COMMON) *(.tcm.heap*) __bss_dtcm_end__ = .; } > TCM From e97939e95f992c7d97e940180a933bc44ad12274 Mon Sep 17 00:00:00 2001 From: zzw Date: Thu, 15 Mar 2018 11:01:09 +0800 Subject: [PATCH 061/118] fix mbed-ci build error L6216E fix mbed-ci build error L6216E * (.ARM.exidx) and *(.init_array) must be placed explicitly, otherwise it is shared between two regions, and the linker is unable to decide where to place it. --- .../TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct | 2 ++ 1 file changed, 2 insertions(+) diff --git a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct index 1b9ee2aeb0..6080041b2f 100644 --- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct @@ -18,6 +18,8 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) { } ER_IRAM +0 FIXED { + *(.ARM.exidx) + *(.init_array) *rtl8195a_crypto*.o (+RO) *(i.mbedtls*) *libc.a (+RO) From dbaa387a316bece0e3d87287f84c0ac1b9b31111 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Tue, 27 Feb 2018 14:19:09 +0200 Subject: [PATCH 062/118] Added deprecation notes to old cellular interfaces. --- features/netsocket/CellularInterface.h | 2 ++ .../generic_modem_driver/OnboardCellularInterface.cpp | 2 ++ .../cellular/generic_modem_driver/OnboardCellularInterface.h | 2 ++ .../cellular/generic_modem_driver/PPPCellularInterface.cpp | 4 ++++ .../cellular/generic_modem_driver/PPPCellularInterface.h | 2 ++ .../cellular/generic_modem_driver/UARTCellularInterface.cpp | 3 +++ .../cellular/generic_modem_driver/UARTCellularInterface.h | 2 ++ 7 files changed, 17 insertions(+) diff --git a/features/netsocket/CellularInterface.h b/features/netsocket/CellularInterface.h index 8851a2ac6c..de0a0e533d 100644 --- a/features/netsocket/CellularInterface.h +++ b/features/netsocket/CellularInterface.h @@ -24,6 +24,8 @@ * * Common interface that is shared between ethernet hardware * @addtogroup netsocket + * + * @attention CellularInterface API will be deprecated, use mbed-os/features/cellular/framework/API instead. */ class CellularInterface : public NetworkInterface { diff --git a/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.cpp b/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.cpp index fbd111eff7..8aca57c76b 100644 --- a/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.cpp +++ b/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.cpp @@ -23,6 +23,8 @@ /** * OnboardCellularInterface is an on-board specific implementation. + * + * @attention This API will be deprecated, use mbed-os/features/cellular/framework/API instead. */ OnboardCellularInterface::OnboardCellularInterface(bool debug) : UARTCellularInterface(MDMTXD, MDMRXD, MDMDCD, MDMRTS, diff --git a/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h b/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h index 379ece87ec..482ccb5bbf 100644 --- a/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h +++ b/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h @@ -31,6 +31,8 @@ typedef mbed::EasyCellularConnection OnboardCellularInterface; * Depending on the type of on-board modem, OnboardCellularInterface * could be derived from different implementation classes. * Portable applications should only rely on it being a CellularBase. + * + * @attention This API will be deprecated, use mbed-os/features/cellular/framework/API instead. */ class OnboardCellularInterface : public UARTCellularInterface { diff --git a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp index 4d22eb2b8b..b07199e360 100644 --- a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp +++ b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp @@ -14,6 +14,10 @@ */ #include "PPPCellularInterface.h" +/** + * @attention This API will be deprecated, use mbed-os/features/cellular/framework/API instead. + */ + #if NSAPI_PPP_AVAILABLE #include diff --git a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h index a649c82f69..ff57f6a582 100644 --- a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h +++ b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h @@ -98,6 +98,8 @@ typedef struct { * The driver will work with any generic FileHandle, and can be * derived from in order to provide forms for specific interfaces, as well as * adding extra power and reset controls alongside the FileHandle. + * + * @attention This API will be deprecated, use mbed-os/features/cellular/framework/API instead. */ class PPPCellularInterface : public CellularBase { diff --git a/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.cpp b/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.cpp index e1ee638876..eace5a8d96 100644 --- a/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.cpp +++ b/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.cpp @@ -14,6 +14,9 @@ */ #include "UARTCellularInterface.h" +/** + * @attention UARTCellularInterface API will be deprecated, use mbed-os/features/cellular/framework/API instead. + */ #if NSAPI_PPP_AVAILABLE UARTCellularInterface::UARTCellularInterface(PinName txd, PinName rxd, PinName dcd, PinName rts, PinName cts, PinName ri, diff --git a/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h b/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h index e86d5862c6..ea6b8dc346 100644 --- a/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h +++ b/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h @@ -28,6 +28,8 @@ * * It constructs a FileHandle and passes it back to its base class as well as overrides * enable_hup() in the base class. + * + * @attention UARTCellularInterface API will be deprecated, use mbed-os/features/cellular/framework/API instead. */ class UARTCellularInterface : public PPPCellularInterface { From 51558781afa1644244977bbb8d597a6c3fc036bb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Mon, 5 Mar 2018 10:56:05 +0200 Subject: [PATCH 063/118] Moved APN_db.h under new cellular. --- .../cellular/utils => cellular/easy_cellular}/APN_db.h | 0 .../generic_modem_driver/PPPCellularInterface.cpp | 8 ++++---- 2 files changed, 4 insertions(+), 4 deletions(-) rename features/{netsocket/cellular/utils => cellular/easy_cellular}/APN_db.h (100%) diff --git a/features/netsocket/cellular/utils/APN_db.h b/features/cellular/easy_cellular/APN_db.h similarity index 100% rename from features/netsocket/cellular/utils/APN_db.h rename to features/cellular/easy_cellular/APN_db.h diff --git a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp index b07199e360..0d8e39f2f2 100644 --- a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp +++ b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp @@ -23,7 +23,7 @@ #include #include "nsapi_ppp.h" #if MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP -#include "utils/APN_db.h" +#include "APN_db.h" #endif //MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP #if defined(FEATURE_COMMON_PAL) #include "mbed_trace.h" @@ -574,12 +574,12 @@ nsapi_error_t PPPCellularInterface::connect() user_specified_apn = true; #endif } - + if (is_connected()) { return NSAPI_ERROR_IS_CONNECTED; } else if (_connect_status == NSAPI_STATUS_CONNECTING) { return NSAPI_ERROR_ALREADY; - } + } _connect_status = NSAPI_STATUS_CONNECTING; if (_connection_status_cb) { @@ -681,7 +681,7 @@ nsapi_error_t PPPCellularInterface::connect() } tr_info("The APN being used is %s.\n", _apn); - + /* Attempt to enter data mode */ success = set_atd(_at); //enter into Data mode with the modem if (!success) { From 6dd0a79e397debcc63c9fb0db60aa99c06716f86 Mon Sep 17 00:00:00 2001 From: Antti Kauppila Date: Mon, 12 Mar 2018 19:38:58 +0200 Subject: [PATCH 064/118] MBED_DEPRECATED_SINCE taken into use --- features/netsocket/CellularInterface.h | 8 ++++--- .../OnboardCellularInterface.cpp | 2 +- .../OnboardCellularInterface.h | 9 ++++++-- .../PPPCellularInterface.cpp | 4 ---- .../PPPCellularInterface.h | 22 ++++++++++++++++--- .../UARTCellularInterface.cpp | 4 +--- .../UARTCellularInterface.h | 6 +++-- 7 files changed, 37 insertions(+), 18 deletions(-) diff --git a/features/netsocket/CellularInterface.h b/features/netsocket/CellularInterface.h index de0a0e533d..cfcf2dd4c5 100644 --- a/features/netsocket/CellularInterface.h +++ b/features/netsocket/CellularInterface.h @@ -19,19 +19,17 @@ #include "netsocket/NetworkInterface.h" - /** CellularInterface class * * Common interface that is shared between ethernet hardware * @addtogroup netsocket - * - * @attention CellularInterface API will be deprecated, use mbed-os/features/cellular/framework/API instead. */ class CellularInterface : public NetworkInterface { public: /** CellularInterface lifetime */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual ~CellularInterface() {}; /** Set the cellular network APN and credentials @@ -41,6 +39,7 @@ public: * @param password Optional password fot the APN * @return 0 on success, negative error code on failure */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual nsapi_error_t set_credentials(const char *apn, const char *username = 0, const char *password = 0) = 0; @@ -51,6 +50,7 @@ public: * @param password Optional password for your APN * @return 0 on success, negative error code on failure */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual nsapi_error_t connect(const char *apn, const char *username = 0, const char *password = 0) = 0; @@ -60,12 +60,14 @@ public: * * @return 0 on success, negative error code on failure */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual nsapi_error_t connect() = 0; /** Stop the interface * * @return 0 on success, negative error code on failure */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual nsapi_error_t disconnect() = 0; }; diff --git a/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.cpp b/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.cpp index 8aca57c76b..4857dc1a85 100644 --- a/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.cpp +++ b/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.cpp @@ -24,8 +24,8 @@ /** * OnboardCellularInterface is an on-board specific implementation. * - * @attention This API will be deprecated, use mbed-os/features/cellular/framework/API instead. */ + OnboardCellularInterface::OnboardCellularInterface(bool debug) : UARTCellularInterface(MDMTXD, MDMRXD, MDMDCD, MDMRTS, MDMCTS, MDMRI, MDMDTR, MDMDSR, diff --git a/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h b/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h index 482ccb5bbf..140ef02440 100644 --- a/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h +++ b/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h @@ -31,15 +31,16 @@ typedef mbed::EasyCellularConnection OnboardCellularInterface; * Depending on the type of on-board modem, OnboardCellularInterface * could be derived from different implementation classes. * Portable applications should only rely on it being a CellularBase. - * - * @attention This API will be deprecated, use mbed-os/features/cellular/framework/API instead. */ + class OnboardCellularInterface : public UARTCellularInterface { public: + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") OnboardCellularInterface(bool debug = false); + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual ~OnboardCellularInterface(); protected: @@ -48,6 +49,7 @@ protected: * modem_init() is equivalent to plugging in the device, for example, attaching power and serial port. * Uses onboard_modem_api.h where the target provides the implementation of onboard_modem_api. */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual void modem_init(); /** Sets the modem in unplugged state @@ -56,6 +58,7 @@ protected: * and serial port. This puts the modem in lowest power state. * Uses onboard_modem_api.h where the target provides the implementation of onboard_modem_api. */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual void modem_deinit(); /** Powers up the modem @@ -64,6 +67,7 @@ protected: * The driver may repeat this if the modem is not responsive to AT commands. * Uses onboard_modem_api.h where the target provides the implementation of onboard_modem_api. */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual void modem_power_up(); /** Powers down the modem @@ -71,6 +75,7 @@ protected: * modem_power_down() is equivalent to turning off the modem by button press. * Uses onboard_modem_api.h where the target provides the implementation of onboard_modem_api. */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual void modem_power_down(); }; diff --git a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp index 0d8e39f2f2..76a5ed288f 100644 --- a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp +++ b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.cpp @@ -14,10 +14,6 @@ */ #include "PPPCellularInterface.h" -/** - * @attention This API will be deprecated, use mbed-os/features/cellular/framework/API instead. - */ - #if NSAPI_PPP_AVAILABLE #include diff --git a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h index ff57f6a582..6f40f58e95 100644 --- a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h +++ b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h @@ -98,9 +98,8 @@ typedef struct { * The driver will work with any generic FileHandle, and can be * derived from in order to provide forms for specific interfaces, as well as * adding extra power and reset controls alongside the FileHandle. - * - * @attention This API will be deprecated, use mbed-os/features/cellular/framework/API instead. */ + class PPPCellularInterface : public CellularBase { public: @@ -110,8 +109,10 @@ public: * The file handle pointer is not accessed within the constructor, only recorded for later * use - this permits a derived class to pass a pointer to a not-yet-constructed member object. */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") PPPCellularInterface(FileHandle *fh, bool debug = false); + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual ~PPPCellularInterface(); /** Set the Cellular network credentials @@ -122,6 +123,7 @@ public: * @param uname optionally, Username * @param pwd optionally, password */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual void set_credentials(const char *apn, const char *uname = 0, const char *pwd = 0); @@ -129,6 +131,7 @@ public: * * @param sim_pin PIN for the SIM card */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual void set_sim_pin(const char *sim_pin); /** Start the interface @@ -146,6 +149,7 @@ public: * @param pwd optionally, password * @return NSAPI_ERROR_OK on success, or negative error code on failure */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual nsapi_error_t connect(const char *sim_pin, const char *apn = 0, const char *uname = 0, const char *pwd = 0); @@ -169,6 +173,7 @@ public: * Preferred method is to setup APN using 'set_credentials()' API. * @return 0 on success, negative error code on failure */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual nsapi_error_t connect(); /** Attempt to disconnect from the network @@ -178,6 +183,7 @@ public: * * @return 0 on success, negative error code on failure */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual nsapi_error_t disconnect(); /** Adds or removes a SIM facility lock @@ -190,6 +196,7 @@ public: * @param set can be set to true if the SIM pin check is supposed to be enabled * and vice versa. */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") void set_sim_pin_check(bool set); /** Change the pin for the SIM card @@ -200,6 +207,7 @@ public: * * @param new_pin new pin to be used in string format */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") void set_new_sim_pin(const char *new_pin); /** Check if the connection is currently established or not @@ -208,6 +216,7 @@ public: * connected to an external packet data network using PPP, isConnected() * API returns true and false otherwise. */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual bool is_connected(); /** Get the local IP address @@ -215,6 +224,7 @@ public: * @return Null-terminated representation of the local IP address * or null if no IP address has been received */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual const char *get_ip_address(); /** Get the local network mask @@ -222,6 +232,7 @@ public: * @return Null-terminated representation of the local network mask * or null if no network mask has been received */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual const char *get_netmask(); /** Get the local gateways @@ -229,6 +240,7 @@ public: * @return Null-terminated representation of the local gateway * or null if no network mask has been received */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual const char *get_gateway(); @@ -236,18 +248,21 @@ public: * * @param on set true to enable debug traces */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") void modem_debug_on(bool on); /** Register callback for status reporting * * @param status_cb The callback for status changes */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual void attach(Callback status_cb); /** Get the connection status * * @return The connection status according to nsapi_connection_status_t */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual nsapi_connection_status_t get_connection_status() const; /** Set blocking status of connect() which by default should be blocking @@ -255,6 +270,7 @@ public: * @param blocking true if connect is blocking * @return 0 on success, negative error code on failure */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual nsapi_error_t set_blocking(bool blocking); private: @@ -276,7 +292,7 @@ private: nsapi_error_t initialize_sim_card(); nsapi_error_t setup_context_and_credentials(); bool power_up(); - void power_down(); + void power_down(); void ppp_status_cb(nsapi_event_t, intptr_t); protected: diff --git a/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.cpp b/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.cpp index eace5a8d96..87ee0f3349 100644 --- a/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.cpp +++ b/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.cpp @@ -14,9 +14,7 @@ */ #include "UARTCellularInterface.h" -/** - * @attention UARTCellularInterface API will be deprecated, use mbed-os/features/cellular/framework/API instead. - */ + #if NSAPI_PPP_AVAILABLE UARTCellularInterface::UARTCellularInterface(PinName txd, PinName rxd, PinName dcd, PinName rts, PinName cts, PinName ri, diff --git a/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h b/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h index ea6b8dc346..b1f4748e61 100644 --- a/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h +++ b/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h @@ -28,18 +28,19 @@ * * It constructs a FileHandle and passes it back to its base class as well as overrides * enable_hup() in the base class. - * - * @attention UARTCellularInterface API will be deprecated, use mbed-os/features/cellular/framework/API instead. */ + class UARTCellularInterface : public PPPCellularInterface { public: + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") UARTCellularInterface(PinName tx, PinName rx, PinName dcd = NC, PinName rts = NC, PinName cts = NC, PinName ri = NC, PinName dtr = NC, PinName dsr = NC, int baud = MBED_CONF_PPP_CELL_IFACE_BAUD_RATE, bool active_high = false, bool debug = false); + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual ~UARTCellularInterface(); private: @@ -55,6 +56,7 @@ protected: * signaling is not desired. enable_hup() controls whether this function should be * active. */ + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") virtual void enable_hup(bool enable); }; From 08d681a82a92a9786bf5aa261fcd475a1fabd0ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Tue, 13 Mar 2018 13:09:36 +0200 Subject: [PATCH 065/118] PR review findings, updated deprecated comments. --- features/netsocket/CellularInterface.h | 10 +++--- .../OnboardCellularInterface.h | 12 +++---- .../PPPCellularInterface.h | 34 +++++++++---------- .../UARTCellularInterface.h | 6 ++-- 4 files changed, 31 insertions(+), 31 deletions(-) diff --git a/features/netsocket/CellularInterface.h b/features/netsocket/CellularInterface.h index cfcf2dd4c5..3905530f19 100644 --- a/features/netsocket/CellularInterface.h +++ b/features/netsocket/CellularInterface.h @@ -29,7 +29,7 @@ class CellularInterface : public NetworkInterface public: /** CellularInterface lifetime */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularNetwork.h instead.") virtual ~CellularInterface() {}; /** Set the cellular network APN and credentials @@ -39,7 +39,7 @@ public: * @param password Optional password fot the APN * @return 0 on success, negative error code on failure */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularNetwork.h instead.") virtual nsapi_error_t set_credentials(const char *apn, const char *username = 0, const char *password = 0) = 0; @@ -50,7 +50,7 @@ public: * @param password Optional password for your APN * @return 0 on success, negative error code on failure */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularNetwork.h instead.") virtual nsapi_error_t connect(const char *apn, const char *username = 0, const char *password = 0) = 0; @@ -60,14 +60,14 @@ public: * * @return 0 on success, negative error code on failure */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularNetwork.h instead.") virtual nsapi_error_t connect() = 0; /** Stop the interface * * @return 0 on success, negative error code on failure */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularNetwork.h instead.") virtual nsapi_error_t disconnect() = 0; }; diff --git a/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h b/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h index 140ef02440..1bc30b4bc7 100644 --- a/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h +++ b/features/netsocket/cellular/generic_modem_driver/OnboardCellularInterface.h @@ -37,10 +37,10 @@ class OnboardCellularInterface : public UARTCellularInterface { public: - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularPower.h instead.") OnboardCellularInterface(bool debug = false); - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularPower.h instead.") virtual ~OnboardCellularInterface(); protected: @@ -49,7 +49,7 @@ protected: * modem_init() is equivalent to plugging in the device, for example, attaching power and serial port. * Uses onboard_modem_api.h where the target provides the implementation of onboard_modem_api. */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularPower.h instead.") virtual void modem_init(); /** Sets the modem in unplugged state @@ -58,7 +58,7 @@ protected: * and serial port. This puts the modem in lowest power state. * Uses onboard_modem_api.h where the target provides the implementation of onboard_modem_api. */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularPower.h instead.") virtual void modem_deinit(); /** Powers up the modem @@ -67,7 +67,7 @@ protected: * The driver may repeat this if the modem is not responsive to AT commands. * Uses onboard_modem_api.h where the target provides the implementation of onboard_modem_api. */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularPower.h instead.") virtual void modem_power_up(); /** Powers down the modem @@ -75,7 +75,7 @@ protected: * modem_power_down() is equivalent to turning off the modem by button press. * Uses onboard_modem_api.h where the target provides the implementation of onboard_modem_api. */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API/CellularPower.h instead.") virtual void modem_power_down(); }; diff --git a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h index 6f40f58e95..4502f7b476 100644 --- a/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h +++ b/features/netsocket/cellular/generic_modem_driver/PPPCellularInterface.h @@ -109,10 +109,10 @@ public: * The file handle pointer is not accessed within the constructor, only recorded for later * use - this permits a derived class to pass a pointer to a not-yet-constructed member object. */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") PPPCellularInterface(FileHandle *fh, bool debug = false); - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual ~PPPCellularInterface(); /** Set the Cellular network credentials @@ -123,7 +123,7 @@ public: * @param uname optionally, Username * @param pwd optionally, password */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual void set_credentials(const char *apn, const char *uname = 0, const char *pwd = 0); @@ -131,7 +131,7 @@ public: * * @param sim_pin PIN for the SIM card */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual void set_sim_pin(const char *sim_pin); /** Start the interface @@ -149,7 +149,7 @@ public: * @param pwd optionally, password * @return NSAPI_ERROR_OK on success, or negative error code on failure */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual nsapi_error_t connect(const char *sim_pin, const char *apn = 0, const char *uname = 0, const char *pwd = 0); @@ -173,7 +173,7 @@ public: * Preferred method is to setup APN using 'set_credentials()' API. * @return 0 on success, negative error code on failure */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual nsapi_error_t connect(); /** Attempt to disconnect from the network @@ -183,7 +183,7 @@ public: * * @return 0 on success, negative error code on failure */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual nsapi_error_t disconnect(); /** Adds or removes a SIM facility lock @@ -196,7 +196,7 @@ public: * @param set can be set to true if the SIM pin check is supposed to be enabled * and vice versa. */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") void set_sim_pin_check(bool set); /** Change the pin for the SIM card @@ -207,7 +207,7 @@ public: * * @param new_pin new pin to be used in string format */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") void set_new_sim_pin(const char *new_pin); /** Check if the connection is currently established or not @@ -216,7 +216,7 @@ public: * connected to an external packet data network using PPP, isConnected() * API returns true and false otherwise. */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual bool is_connected(); /** Get the local IP address @@ -224,7 +224,7 @@ public: * @return Null-terminated representation of the local IP address * or null if no IP address has been received */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual const char *get_ip_address(); /** Get the local network mask @@ -232,7 +232,7 @@ public: * @return Null-terminated representation of the local network mask * or null if no network mask has been received */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual const char *get_netmask(); /** Get the local gateways @@ -240,7 +240,7 @@ public: * @return Null-terminated representation of the local gateway * or null if no network mask has been received */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual const char *get_gateway(); @@ -248,21 +248,21 @@ public: * * @param on set true to enable debug traces */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") void modem_debug_on(bool on); /** Register callback for status reporting * * @param status_cb The callback for status changes */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual void attach(Callback status_cb); /** Get the connection status * * @return The connection status according to nsapi_connection_status_t */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual nsapi_connection_status_t get_connection_status() const; /** Set blocking status of connect() which by default should be blocking @@ -270,7 +270,7 @@ public: * @param blocking true if connect is blocking * @return 0 on success, negative error code on failure */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual nsapi_error_t set_blocking(bool blocking); private: diff --git a/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h b/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h index b1f4748e61..0d5e611be8 100644 --- a/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h +++ b/features/netsocket/cellular/generic_modem_driver/UARTCellularInterface.h @@ -34,13 +34,13 @@ class UARTCellularInterface : public PPPCellularInterface { public: - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") UARTCellularInterface(PinName tx, PinName rx, PinName dcd = NC, PinName rts = NC, PinName cts = NC, PinName ri = NC, PinName dtr = NC, PinName dsr = NC, int baud = MBED_CONF_PPP_CELL_IFACE_BAUD_RATE, bool active_high = false, bool debug = false); - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual ~UARTCellularInterface(); private: @@ -56,7 +56,7 @@ protected: * signaling is not desired. enable_hup() controls whether this function should be * active. */ - MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/framework/API instead.") + MBED_DEPRECATED_SINCE("mbed-os-5.9", "This API will be deprecated, use mbed-os/features/cellular/easy_cellular/EasyCellularConnection.h instead.") virtual void enable_hup(bool enable); }; From b7526edf68d3ee0f6dc41cfe43c2a3e4d0d93018 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Teppo=20J=C3=A4rvelin?= Date: Tue, 13 Mar 2018 16:23:15 +0200 Subject: [PATCH 066/118] Fixed correct includes so that compile log is not polluted. --- features/cellular/framework/API/CellularNetwork.h | 1 - features/netsocket/nsapi.h | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/features/cellular/framework/API/CellularNetwork.h b/features/cellular/framework/API/CellularNetwork.h index c85df16e8d..46934770c5 100644 --- a/features/cellular/framework/API/CellularNetwork.h +++ b/features/cellular/framework/API/CellularNetwork.h @@ -18,7 +18,6 @@ #ifndef CELLULAR_NETWORK_H_ #define CELLULAR_NETWORK_H_ -#include "CellularInterface.h" #include "NetworkInterface.h" #include "CellularList.h" diff --git a/features/netsocket/nsapi.h b/features/netsocket/nsapi.h index c9ed8bd6e4..21047dad73 100644 --- a/features/netsocket/nsapi.h +++ b/features/netsocket/nsapi.h @@ -33,7 +33,7 @@ #include "netsocket/NetworkInterface.h" #include "netsocket/EthInterface.h" #include "netsocket/WiFiInterface.h" -#include "netsocket/CellularInterface.h" +#include "netsocket/CellularBase.h" #include "netsocket/MeshInterface.h" #include "netsocket/Socket.h" From b4ac1a5a037cb8b3a54ec2516e98ac2d3cf6ea10 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 5 Mar 2018 14:36:51 +0100 Subject: [PATCH 067/118] DISCO_L496AG: add PeripheralPins.c --- .../TARGET_DISCO_L496AG/PeripheralPins.c | 476 ++++++++++++++++++ 1 file changed, 476 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c new file mode 100644 index 0000000000..872be10e3d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c @@ -0,0 +1,476 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: some pins are connected to the default STDIO_UART_TX and STDIO_UART_RX pins. +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +//============================================================================== + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 + {PA_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - ARDUINO_A4 + {PA_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO_A4 +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - Connected to STDIO_UART_TX + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 - Connected to STDIO_UART_TX +#endif + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - ARDUINO_D13 + {PA_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 - ARDUINO_D13 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12 + {PA_7_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15 + {PB_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - ARDUINO_A5 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - ARDUINO_A5 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 - ARDUINO_A5 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - ARDUINO_A1 + {PC_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 - ARDUINO_A1 + {PC_1_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 - ARDUINO_A1 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 + {PC_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3 + {PC_2_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - ARDUINO_A2 + {PC_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - ARDUINO_A2 + {PC_3_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 - ARDUINO_A2 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - ARDUINO_A0 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 - ARDUINO_A0 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14 + {PC_5_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 - ARDUINO_A3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - ARDUINO_D13 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO_D12 + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO_D14 + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, // ARDUINO_D14 + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO_D5 + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_11_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO_A1 + {PC_1_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)}, // ARDUINO_A1 + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO_D0 + {PG_13, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO_D2 + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO_D15 + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PB_10_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)}, + {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to LED1 + {PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO_A5 + {PC_0_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)}, // ARDUINO_A5 + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PG_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO_D1 + {PG_14, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {NC, NC, 0} +}; + +//*** PWM *** +// Warning: Pins using PWM_5 cannot be used as TIMER5 is already used by the ticker. +MBED_WEAK const PinMap PinMap_PWM[] = { + {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - already used by the ticker + {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO_A4 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - already used by the ticker + {PA_1_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N - ARDUINO_A4 +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - Connected to STDIO_UART_TX +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - already used by the ticker + {PA_2_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 - Connected to STDIO_UART_TX +#endif + {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - already used by the ticker + {PA_3_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - ARDUINO_D13 + {PA_5_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - ARDUINO_D13 + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - ARDUINO_D10 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO_D12 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO_D11 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - ARDUINO_D14 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N - ARDUINO_D14 + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - ARDUINO_D15 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 - ARDUINO_D15 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - ARDUINO_D5 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 - ARDUINO_D5 + {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - Connected to LED1 + {PB_13_ALT0, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N - Connected to LED1 + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 + {PE_1, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 + {PE_3, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PE_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PE_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PE_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PF_10, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 - ARDUINO_A3 + {PG_9, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N + {PG_10, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 + {PG_11, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 +// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - already used by the ticker +// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - already used by the ticker +// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - already used by the ticker + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - ARDUINO_D9 + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - ARDUINO_D3 +// {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - already used by the ticker + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - ARDUINO_D6 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX (default) + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO_A1 + {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO_A0 + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO_D1 + {PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // ARDUINO_A4 + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, // ARDUINO_D10 + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // ARDUINO_D14 + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO_A5 + {PC_5, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX (default) + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_8, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO_D0 + {PG_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ARDUINO_A4 + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO_D10 + {PA_15_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // ARDUINO_D10 + {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_1_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // ARDUINO_D12 + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_2, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO_D7 + {PG_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PA_6_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // ARDUINO_D12 + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // ARDUINO_D11 + {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // ARDUINO_D14 + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED1 + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LED1 + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PG_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PG_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO_D11 + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // ARDUINO_D11 + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, // ARDUINO_A1 + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO_A2 + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO_D12 + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // ARDUINO_D12 + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO_A4 + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO_D13 + {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Connected to LED1 + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, + {PE_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_2, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_9, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PA_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO_D10 + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // ARDUINO_D10 + {PB_0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO_D5 + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {PE_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, + {PG_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, + {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_CAN2)}, // ARDUINO_D11 + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO_D15 + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to JOYSTICK_LEFT + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO_D5 + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)}, // Connected to LED1 + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, + {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO_D9 + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // Connected to STDIO_UART_TX +#endif + {PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PC_1, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A1 + {PC_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PC_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A2 + {PC_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A0 + {PC_11, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, + {PD_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PD_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PD_5, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + {PD_6, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // Connected to STDIO_UART_RX + {PD_6_ALT0, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // Connected to STDIO_UART_RX +#endif + {PD_7, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PH_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)}, // ARDUINO_A3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // Connected to STDIO_UART_TX +#endif + {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PC_11, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, + {PD_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, + {NC, NC, 0} +}; From 615ac588a44af0244a51953ddfd6a1d857f3f179 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 5 Mar 2018 15:57:12 +0100 Subject: [PATCH 068/118] DISCO_L496AG: remove QSPI2 Base adress not found in registers map file but found in CubeMX xml file. --- .../TARGET_DISCO_L496AG/PeripheralPins.c | 28 +++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c index 872be10e3d..8077e146e3 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c @@ -434,25 +434,25 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA[] = { {PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, - {PC_1, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A1 - {PC_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, - {PC_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A2 - {PC_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A0 - {PC_11, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, - {PD_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, - {PD_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, - {PD_5, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, +// {PC_1, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A1 +// {PC_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, +// {PC_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A2 +// {PC_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A0 +// {PC_11, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, +// {PD_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, +// {PD_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, +// {PD_5, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, #ifdef MBED_CONF_TARGET_STDIO_UART_RX - {PD_6, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // Connected to STDIO_UART_RX - {PD_6_ALT0, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // Connected to STDIO_UART_RX +// {PD_6, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // Connected to STDIO_UART_RX +// {PD_6_ALT0, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // Connected to STDIO_UART_RX #endif - {PD_7, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, +// {PD_7, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, {PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, {PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, {PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, {PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, - {PH_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)}, +// {PH_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)}, {NC, NC, 0} }; @@ -469,8 +469,8 @@ MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // Connected to STDIO_UART_TX #endif {PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, - {PC_11, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, - {PD_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, +// {PC_11, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, +// {PD_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, {PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, {NC, NC, 0} }; From 1bbcd08dc3127182b937c3ec487fd226438274aa Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 5 Mar 2018 15:59:29 +0100 Subject: [PATCH 069/118] DISCO_L496AG: add other pins related files --- .../TARGET_DISCO_L496AG/PeripheralNames.h | 96 ++++++ .../TARGET_DISCO_L496AG/PinNames.h | 313 ++++++++++++++++++ 2 files changed, 409 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralNames.h create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralNames.h new file mode 100644 index 0000000000..a2d80f0942 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralNames.h @@ -0,0 +1,96 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ADC_1 = (int)ADC1_BASE, + ADC_2 = (int)ADC2_BASE, + ADC_3 = (int)ADC3_BASE +} ADCName; + +typedef enum { + DAC_1 = (int)DAC_BASE +} DACName; + +typedef enum { + UART_1 = (int)USART1_BASE, + UART_2 = (int)USART2_BASE, + UART_3 = (int)USART3_BASE, + UART_4 = (int)UART4_BASE, + UART_5 = (int)UART5_BASE, + LPUART_1 = (int)LPUART1_BASE +} UARTName; + +typedef enum { + SPI_1 = (int)SPI1_BASE, + SPI_2 = (int)SPI2_BASE, + SPI_3 = (int)SPI3_BASE +} SPIName; + +typedef enum { + I2C_1 = (int)I2C1_BASE, + I2C_2 = (int)I2C2_BASE, + I2C_3 = (int)I2C3_BASE, + I2C_4 = (int)I2C4_BASE +} I2CName; + +typedef enum { + PWM_1 = (int)TIM1_BASE, + PWM_2 = (int)TIM2_BASE, + PWM_3 = (int)TIM3_BASE, + PWM_4 = (int)TIM4_BASE, + PWM_5 = (int)TIM5_BASE, + PWM_8 = (int)TIM8_BASE, + PWM_15 = (int)TIM15_BASE, + PWM_16 = (int)TIM16_BASE, + PWM_17 = (int)TIM17_BASE +} PWMName; + +typedef enum { + CAN_1 = (int)CAN1_BASE, + CAN_2 = (int)CAN2_BASE +} CANName; + +typedef enum { + QSPI_1 = (int)QSPI_BASE +} QSPIName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h new file mode 100644 index 0000000000..1ec0545782 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h @@ -0,0 +1,313 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400 +} ALTx; + +typedef enum { + PA_0 = 0x00, + PA_0_ALT0 = PA_0|ALT0, + PA_1 = 0x01, + PA_1_ALT0 = PA_1|ALT0, + PA_1_ALT1 = PA_1|ALT1, + PA_2 = 0x02, + PA_2_ALT0 = PA_2|ALT0, + PA_2_ALT1 = PA_2|ALT1, + PA_3 = 0x03, + PA_3_ALT0 = PA_3|ALT0, + PA_3_ALT1 = PA_3|ALT1, + PA_4 = 0x04, + PA_4_ALT0 = PA_4|ALT0, + PA_5 = 0x05, + PA_5_ALT0 = PA_5|ALT0, + PA_6 = 0x06, + PA_6_ALT0 = PA_6|ALT0, + PA_7 = 0x07, + PA_7_ALT0 = PA_7|ALT0, + PA_7_ALT1 = PA_7|ALT1, + PA_7_ALT2 = PA_7|ALT2, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15|ALT0, + + PB_0 = 0x10, + PB_0_ALT0 = PB_0|ALT0, + PB_0_ALT1 = PB_0|ALT1, + PB_1 = 0x11, + PB_1_ALT0 = PB_1|ALT0, + PB_1_ALT1 = PB_1|ALT1, + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3|ALT0, + PB_4 = 0x14, + PB_4_ALT0 = PB_4|ALT0, + PB_5 = 0x15, + PB_5_ALT0 = PB_5|ALT0, + PB_6 = 0x16, + PB_6_ALT0 = PB_6|ALT0, + PB_7 = 0x17, + PB_7_ALT0 = PB_7|ALT0, + PB_8 = 0x18, + PB_8_ALT0 = PB_8|ALT0, + PB_9 = 0x19, + PB_9_ALT0 = PB_9|ALT0, + PB_10 = 0x1A, + PB_10_ALT0 = PB_10|ALT0, + PB_11 = 0x1B, + PB_11_ALT0 = PB_11|ALT0, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_13_ALT0 = PB_13|ALT0, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14|ALT0, + PB_14_ALT1 = PB_14|ALT1, + PB_15 = 0x1F, + PB_15_ALT0 = PB_15|ALT0, + PB_15_ALT1 = PB_15|ALT1, + + PC_0 = 0x20, + PC_0_ALT0 = PC_0|ALT0, + PC_0_ALT1 = PC_0|ALT1, + PC_1 = 0x21, + PC_1_ALT0 = PC_1|ALT0, + PC_1_ALT1 = PC_1|ALT1, + PC_2 = 0x22, + PC_2_ALT0 = PC_2|ALT0, + PC_2_ALT1 = PC_2|ALT1, + PC_3 = 0x23, + PC_3_ALT0 = PC_3|ALT0, + PC_3_ALT1 = PC_3|ALT1, + PC_4 = 0x24, + PC_4_ALT0 = PC_4|ALT0, + PC_5 = 0x25, + PC_5_ALT0 = PC_5|ALT0, + PC_6 = 0x26, + PC_6_ALT0 = PC_6|ALT0, + PC_7 = 0x27, + PC_7_ALT0 = PC_7|ALT0, + PC_8 = 0x28, + PC_8_ALT0 = PC_8|ALT0, + PC_9 = 0x29, + PC_9_ALT0 = PC_9|ALT0, + PC_10 = 0x2A, + PC_10_ALT0 = PC_10|ALT0, + PC_11 = 0x2B, + PC_11_ALT0 = PC_11|ALT0, + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_5 = 0x55, + PF_10 = 0x5A, + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_15 = 0x5F, + + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_4 = 0x74, + PH_5 = 0x75, + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // Arduino connector + A0 = PC_4, + A1 = PC_1, + A2 = PC_3, + A3 = PF_10, + A4 = PA_1, + A5 = PC_0, + D0 = PG_8, + D1 = PG_7, + D2 = PG_13, + D3 = PH_15, + D4 = PI_11, + D5 = PB_9, + D6 = PI_6, + D7 = PG_6, + D8 = PG_15, + D9 = PH_13, + D10 = PA_15, + D11 = PB_5, + D12 = PB_4, + D13 = PA_5, + D14 = PB_7, + D15 = PB_8, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_2, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PD_6, +#endif + + // Generic signals + LED1 = PB_13, // Green LD2 on board + LED2 = LED1, + LED3 = LED1, + LED4 = LED1, + USER_BUTTON = PC_13, // Joystick Center + BUTTON1 = USER_BUTTON, + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port + I2C_SCL = D15, + I2C_SDA = D14, + SPI_MOSI = D11, + SPI_MISO = D12, + SPI_SCK = D13, + SPI_CS = D10, + PWM_OUT = D9, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif From e9a2373ae2cd22896cdb4adb61c6e6cdaf49bcfd Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 5 Mar 2018 16:01:05 +0100 Subject: [PATCH 070/118] DISCO_L496AG: add platform in targets.json file --- targets/targets.json | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/targets/targets.json b/targets/targets.json index 96961d38d6..22e943ccd5 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3840,6 +3840,27 @@ "release_versions": ["2"], "device_name": "nRF51822_xxAC" }, + "DISCO_L496AG": { + "inherits": ["FAMILY_STM32"], + "supported_form_factors": ["ARDUINO", "MORPHO"], + "core": "Cortex-M4F", + "extra_labels_add": ["STM32L4", "STM32L496AG", "STM32L496xG"], + "config": { + "clock_source": { + "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI", + "value": "USE_PLL_MSI", + "macro_name": "CLOCK_SOURCE" + }, + "lowpowertimer_lptim": { + "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer", + "value": 1 + } + }, + "detect_code": ["0822"], + "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"], + "release_versions": ["2", "5"], + "device_name": "STM32L496AG" + }, "NUCLEO_L496ZG": { "inherits": ["FAMILY_STM32"], "supported_form_factors": ["ARDUINO", "MORPHO"], From ed63943fc43b84ec69292fbd5fc8c2cb699a5491 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 5 Mar 2018 16:05:02 +0100 Subject: [PATCH 071/118] DISCO_L496AG: add system clock file (same as Nucleo) --- .../TARGET_DISCO_L496AG/system_clock.c | 382 ++++++++++++++++++ 1 file changed, 382 insertions(+) create mode 100644 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c new file mode 100644 index 0000000000..e8d5be0049 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c @@ -0,0 +1,382 @@ +/* mbed Microcontroller Library +* Copyright (c) 2006-2017 ARM Limited +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*/ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 16 MHz) + * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 80 + * AHBCLK (MHz) | 80 + * APB1CLK (MHz) | 80 + * APB2CLK (MHz) | 80 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32l4xx.h" +#include "nvic_addr.h" +#include "mbed_assert.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock +#define USE_PLL_MSI 0x1 // Use MSI internal clock + +#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +uint8_t SetSysClock_PLL_MSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ + + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= (uint32_t)0xEAF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock */ + if (SetSysClock_PLL_HSE(1) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI()==0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_MSI) + /* 4- If fail start with MSI clock */ + if (SetSysClock_PLL_MSI() == 0) +#endif + { + while(1) { + MBED_ASSERT(1); + } + } + } + } + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 1 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); +#endif +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Used to gain time after DeepSleep in case HSI is used + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { + return 0; + } + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSE oscillator and activate PLL with HSE as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; + if (bypass == 0) { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN + } + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select HSI as clock source for LPUART1 */ + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 2 + if (bypass == 0) + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz + else + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; + + // Select MSI as system clock source to allow modification of the PLL configuration + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz + RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) + RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) + RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; + RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Disable MSI Oscillator + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Select HSI as clock source for LPUART1 */ + RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; + if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 3 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if ((CLOCK_SOURCE) & USE_PLL_MSI) +/******************************************************************************/ +/* PLL (clocked by MSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_MSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // Enable LSE Oscillator to automatically calibrate the MSI clock + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update + RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { + RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode + } + + HAL_RCCEx_DisableLSECSS(); + /* Enable MSI Oscillator and activate PLL with MSI as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; + RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ + RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ + RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ + RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ + RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + /* Enable MSI Auto-calibration through LSE */ + HAL_RCCEx_EnableMSIPLLMode(); + /* Select MSI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + /* Select LSE as clock source for LPUART1 */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + // Output clock on MCO1 pin(PA8) for debugging purpose +#if DEBUG_MCO == 4 + HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz +#endif + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ From b33c5240a6d2ceeaf54eaae87a79380e99957e5a Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 6 Mar 2018 10:36:15 +0100 Subject: [PATCH 072/118] DISCO_L496AG: add entry in mbed_rtx.h --- targets/TARGET_STM/mbed_rtx.h | 1 + 1 file changed, 1 insertion(+) diff --git a/targets/TARGET_STM/mbed_rtx.h b/targets/TARGET_STM/mbed_rtx.h index f4935483be..2c24d0a4db 100644 --- a/targets/TARGET_STM/mbed_rtx.h +++ b/targets/TARGET_STM/mbed_rtx.h @@ -108,6 +108,7 @@ defined(TARGET_STM32F746NG) ||\ defined(TARGET_STM32F746ZG) ||\ defined(TARGET_STM32F756ZG) ||\ + defined(TARGET_STM32L496AG) ||\ defined(TARGET_STM32L496ZG)) #define INITIAL_SP (0x20050000UL) From 42e3be8bfe5bcf1462f6f57f520960250fd53f3c Mon Sep 17 00:00:00 2001 From: bcostm Date: Tue, 6 Mar 2018 10:39:15 +0100 Subject: [PATCH 073/118] DISCO_L496AG: remove morpho connector in targets.json --- targets/targets.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targets/targets.json b/targets/targets.json index 22e943ccd5..a685eb4d80 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -3842,7 +3842,7 @@ }, "DISCO_L496AG": { "inherits": ["FAMILY_STM32"], - "supported_form_factors": ["ARDUINO", "MORPHO"], + "supported_form_factors": ["ARDUINO"], "core": "Cortex-M4F", "extra_labels_add": ["STM32L4", "STM32L496AG", "STM32L496xG"], "config": { From 5e2977f25650926f5724dfd790aa2e2b3acec189 Mon Sep 17 00:00:00 2001 From: Bartek Szatkowski Date: Thu, 15 Mar 2018 10:43:48 +0000 Subject: [PATCH 074/118] Fix doxygen for ITM HAL --- doxyfile_options | 1 + doxygen_options.json | 2 +- hal/itm_api.h | 14 +++++--------- 3 files changed, 7 insertions(+), 10 deletions(-) diff --git a/doxyfile_options b/doxyfile_options index c97e13de78..ad9497fc1d 100644 --- a/doxyfile_options +++ b/doxyfile_options @@ -2070,6 +2070,7 @@ PREDEFINED = DOXYGEN_ONLY \ DEVICE_I2CSLAVE \ DEVICE_I2C_ASYNCH \ DEVICE_INTERRUPTIN \ + DEVICE_ITM \ DEVICE_LOWPOWERTIMER \ DEVICE_PORTIN \ DEVICE_PORTINOUT \ diff --git a/doxygen_options.json b/doxygen_options.json index eed31ad6cb..f25f70ce43 100644 --- a/doxygen_options.json +++ b/doxygen_options.json @@ -6,7 +6,7 @@ "SEARCH_INCLUDES": "YES", "INCLUDE_PATH": "", "INCLUDE_FILE_PATTERNS": "", - "PREDEFINED": "DOXYGEN_ONLY DEVICE_ANALOGIN DEVICE_ANALOGOUT DEVICE_CAN DEVICE_ETHERNET DEVICE_EMAC DEVICE_FLASH DEVICE_I2C DEVICE_I2CSLAVE DEVICE_I2C_ASYNCH DEVICE_INTERRUPTIN DEVICE_LOWPOWERTIMER DEVICE_PORTIN DEVICE_PORTINOUT DEVICE_PORTOUT DEVICE_PWMOUT DEVICE_RTC DEVICE_TRNG DEVICE_SERIAL DEVICE_SERIAL_ASYNCH DEVICE_SERIAL_FC DEVICE_SLEEP DEVICE_SPI DEVICE_SPI_ASYNCH DEVICE_SPISLAVE DEVICE_STORAGE \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\" \"MBED_DEPRECATED(s)=\"", + "PREDEFINED": "DOXYGEN_ONLY DEVICE_ANALOGIN DEVICE_ANALOGOUT DEVICE_CAN DEVICE_ETHERNET DEVICE_EMAC DEVICE_FLASH DEVICE_I2C DEVICE_I2CSLAVE DEVICE_I2C_ASYNCH DEVICE_INTERRUPTIN DEVICE_ITM DEVICE_LOWPOWERTIMER DEVICE_PORTIN DEVICE_PORTINOUT DEVICE_PORTOUT DEVICE_PWMOUT DEVICE_RTC DEVICE_TRNG DEVICE_SERIAL DEVICE_SERIAL_ASYNCH DEVICE_SERIAL_FC DEVICE_SLEEP DEVICE_SPI DEVICE_SPI_ASYNCH DEVICE_SPISLAVE DEVICE_STORAGE \"MBED_DEPRECATED_SINCE(f, g)=\" \"MBED_ENABLE_IF_CALLBACK_COMPATIBLE(F, M)=\" \"MBED_DEPRECATED(s)=\"", "EXPAND_AS_DEFINED": "", "SKIP_FUNCTION_MACROS": "NO", "EXCLUDE_PATTERNS": "*/tools/* */targets/* */features/mbedtls/* */features/storage/* */features/unsupported/* */BUILD/* */rtos/TARGET_CORTEX/rtx*/* */cmsis/* */features/FEATURE_COMMON_PAL/* */features/FEATURE_LWIP/* */features/FEATURE_UVISOR/* */features/nanostack/* */ble/generic/* */ble/pal/*" diff --git a/hal/itm_api.h b/hal/itm_api.h index 0c5a739c43..c773963fd2 100644 --- a/hal/itm_api.h +++ b/hal/itm_api.h @@ -1,3 +1,5 @@ +/** \addtogroup hal */ +/** @{*/ /* mbed Microcontroller Library * Copyright (c) 2017 ARM Limited * @@ -26,8 +28,7 @@ extern "C" { #endif /** - * @defgroup hal_itm_port ITM Stimulus Ports - * + * \defgroup itm_hal Instrumented Trace Macrocell HAL API * @{ */ @@ -35,13 +36,6 @@ enum { ITM_PORT_SWO = 0 }; -/**@}*/ - -/** - * \defgroup itm_hal Instrumented Trace Macrocell HAL API - * @{ - */ - /** * @brief Target specific initialization function. * This function is responsible for initializing and configuring @@ -89,3 +83,5 @@ uint32_t mbed_itm_send(uint32_t port, uint32_t data); #endif #endif /* MBED_ITM_API_H */ + +/**@}*/ From 84c1aee5698cecd745effc84bfc11860e393562a Mon Sep 17 00:00:00 2001 From: li-ho Date: Thu, 15 Mar 2018 16:50:06 +1100 Subject: [PATCH 075/118] Fix on chip flash minimal programmable unit size - sector size is 0x800 bytes - writeable unit size is 0x8 bytes - flash start address is 0x0 - total ADuCM3029 on chip flash size is 0x40000 bytes - total ADuCM4050 on chip flash size is 0x7F000 bytes --- .../TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c | 2 +- .../TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c index feae0e3d98..304219e8af 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c @@ -76,7 +76,7 @@ static const sector_info_t sectors_info[] = { }; static const flash_target_config_t flash_target_config = { - .page_size = 0x800, + .page_size = 0x8, // minimal programmable unit size .flash_start = 0x0, .flash_size = 0x00040000, .sectors = sectors_info, diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c index 25afcc193f..2779c4cb5a 100755 --- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c +++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c @@ -74,7 +74,7 @@ static const sector_info_t sectors_info[] = { }; static const flash_target_config_t flash_target_config = { - .page_size = 0x800, + .page_size = 0x8, // minimal programmable unit size .flash_start = 0x0, .flash_size = 0x0007F000, .sectors = sectors_info, From 2df7de25dcc48bc31400f19216d8f3fe109f44b4 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Mon, 26 Feb 2018 10:03:49 -0600 Subject: [PATCH 076/118] Correct Realtek post-build script to work in the online compiler --- tools/targets/REALTEK_RTL8195AM.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/targets/REALTEK_RTL8195AM.py b/tools/targets/REALTEK_RTL8195AM.py index c5670df482..0333b29dc1 100644 --- a/tools/targets/REALTEK_RTL8195AM.py +++ b/tools/targets/REALTEK_RTL8195AM.py @@ -273,11 +273,11 @@ def create_daplink(image_bin, ram1_bin, ram2_bin): # ---------------------------- def rtl8195a_elf2bin(t_self, image_elf, image_bin): - image_name = os.path.splitext(image_elf)[0] - image_map = image_name + '.map' + image_name = list(os.path.splitext(image_elf))[:-1] + image_map = ".".join(image_name + ['map']) ram1_bin = os.path.join(TOOLS_BOOTLOADERS, "REALTEK_RTL8195AM", "ram_1.bin") - ram2_bin = image_name + '-payload.bin' + ram2_bin = ".".join(image_name) + '-payload.bin' entry = find_symbol(t_self.name, image_map, "PLAT_Start") segment = parse_load_segment(t_self.name, image_elf) From 40d9b3eef8cb4974d8c5b99a0a3e9f3c7bfd179f Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Fri, 23 Feb 2018 09:57:02 -0600 Subject: [PATCH 077/118] Correct syntax for mbed export in Py3 --- tools/export/cmake/__init__.py | 5 ++- tools/export/gnuarmeclipse/__init__.py | 52 ++------------------------ tools/export/iar/__init__.py | 5 ++- tools/export/makefile/__init__.py | 5 ++- tools/export/mcuxpresso/__init__.py | 47 +++-------------------- tools/export/nb/__init__.py | 30 +++------------ tools/export/sw4stm32/__init__.py | 27 +++++-------- tools/export/uvision/__init__.py | 14 +++---- tools/export/vscode/__init__.py | 5 ++- tools/project.py | 8 ++-- tools/toolchains/arm.py | 7 +++- 11 files changed, 56 insertions(+), 149 deletions(-) diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py index a83f773abf..e1f3e0b749 100644 --- a/tools/export/cmake/__init__.py +++ b/tools/export/cmake/__init__.py @@ -14,6 +14,9 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. """ +from __future__ import print_function, absolute_import +from builtins import str + import re import shutil from os import remove, getcwd, chdir, mkdir @@ -162,7 +165,7 @@ class CMake(Exporter): else: out_string += "FAILURE" - print out_string + print(out_string) if log_name: # Write the output to the log file diff --git a/tools/export/gnuarmeclipse/__init__.py b/tools/export/gnuarmeclipse/__init__.py index 99860dcd36..a1f8d7cddc 100644 --- a/tools/export/gnuarmeclipse/__init__.py +++ b/tools/export/gnuarmeclipse/__init__.py @@ -21,6 +21,8 @@ the GNU ARM Eclipse plug-ins. Author: Liviu Ionescu """ +from __future__ import print_function, absolute_import +from builtins import str import os import copy @@ -139,8 +141,6 @@ class GNUARMEclipse(Exporter): # TODO: use some logger to display additional info if verbose libraries = [] - # print 'libraries' - # print self.resources.libraries for lib in self.resources.libraries: l, _ = splitext(basename(lib)) libraries.append(l[3:]) @@ -158,28 +158,22 @@ class GNUARMEclipse(Exporter): # TODO: get the list from existing .cproject build_folders = [s.capitalize() for s in profile_ids] build_folders.append('BUILD') - # print build_folders objects = [self.filter_dot(s) for s in self.resources.objects] for bf in build_folders: objects = [o for o in objects if not o.startswith(bf + '/')] - # print 'objects' - # print objects self.compute_exclusions() self.include_path = [ self.filter_dot(s) for s in self.resources.inc_dirs] - print 'Include folders: {0}'.format(len(self.include_path)) self.as_defines = self.toolchain.get_symbols(True) self.c_defines = self.toolchain.get_symbols() self.cpp_defines = self.c_defines - print 'Symbols: {0}'.format(len(self.c_defines)) self.ld_script = self.filter_dot( self.resources.linker_script) - print 'Linker script: {0}'.format(self.ld_script) self.options = {} for id in profile_ids: @@ -196,8 +190,6 @@ class GNUARMEclipse(Exporter): opts['id'] = id opts['name'] = opts['id'].capitalize() - print - print 'Build configuration: {0}'.format(opts['name']) profile = profiles[id] @@ -215,12 +207,6 @@ class GNUARMEclipse(Exporter): flags = self.toolchain_flags(toolchain) - print 'Common flags:', ' '.join(flags['common_flags']) - print 'C++ flags:', ' '.join(flags['cxx_flags']) - print 'C flags:', ' '.join(flags['c_flags']) - print 'ASM flags:', ' '.join(flags['asm_flags']) - print 'Linker flags:', ' '.join(flags['ld_flags']) - # Most GNU ARM Eclipse options have a parent, # either debug or release. if '-O0' in flags['common_flags'] or '-Og' in flags['common_flags']: @@ -281,11 +267,6 @@ class GNUARMEclipse(Exporter): """ jinja_ctx = self.create_jinja_ctx() - print - print 'Create a GNU ARM Eclipse C++ managed project' - print 'Project name: {0}'.format(self.project_name) - print 'Target: {0}'.format(self.toolchain.target.name) - print 'Toolchain: {0}'.format(self.TOOLCHAIN) self.gen_file('gnuarmeclipse/.project.tmpl', jinja_ctx, '.project', trim_blocks=True, lstrip_blocks=True) @@ -296,8 +277,7 @@ class GNUARMEclipse(Exporter): self.gen_file_nonoverwrite('gnuarmeclipse/mbedignore.tmpl', jinja_ctx, '.mbedignore') - print - print 'Done. Import the \'{0}\' project in Eclipse.'.format(self.project_name) + print('Done. Import the \'{0}\' project in Eclipse.'.format(self.project_name)) @staticmethod def clean(_): @@ -363,7 +343,7 @@ class GNUARMEclipse(Exporter): if ret_code != 0: ret_string += "FAILURE\n" - print "%s\n%s\n%s\n%s" % (stdout_string, out, err_string, ret_string) + print("%s\n%s\n%s\n%s" % (stdout_string, out, err_string, ret_string)) if log_name: # Write the output to the log file @@ -397,11 +377,9 @@ class GNUARMEclipse(Exporter): file_names = [join(tools_path, "profiles", fn) for fn in os.listdir( join(tools_path, "profiles")) if fn.endswith(".json")] - # print file_names profile_names = [basename(fn).replace(".json", "") for fn in file_names] - # print profile_names profiles = {} @@ -435,7 +413,6 @@ class GNUARMEclipse(Exporter): src) for src in self.resources.c_sources + self.resources.cpp_sources + self.resources.s_sources)] self.excluded_folders = set(self.resources.ignored_dirs) - set(self.resources.inc_dirs) - print 'Source folders: {0}, with {1} exclusions'.format(len(source_folders), len(self.excluded_folders)) # ------------------------------------------------------------------------- @@ -460,7 +437,6 @@ class GNUARMEclipse(Exporter): node = nodes[k] parent_name = node['parent'][ 'name'] if 'parent' in node.keys() else '' - print ' ' * depth, node['name'], node['is_used'], parent_name if len(node['children'].keys()) != 0: self.dump_tree(node['children'], depth + 1) @@ -474,7 +450,6 @@ class GNUARMEclipse(Exporter): break node = node['parent'] path = '/'.join(parts) - print path, nodes[k]['is_used'] self.dump_paths(nodes[k]['children'], depth + 1) # ------------------------------------------------------------------------- @@ -504,14 +479,6 @@ class GNUARMEclipse(Exporter): # Make a copy of the flags, to be one by one removed after processing. flags = copy.deepcopy(flags_in) - if False: - print - print 'common_flags', flags['common_flags'] - print 'asm_flags', flags['asm_flags'] - print 'c_flags', flags['c_flags'] - print 'cxx_flags', flags['cxx_flags'] - print 'ld_flags', flags['ld_flags'] - # Initialise the 'last resort' options where all unrecognised # options will be collected. opts['as']['other'] = '' @@ -944,17 +911,6 @@ class GNUARMEclipse(Exporter): opts['cpp']['other'] = opts['cpp']['other'].strip() opts['ld']['other'] = opts['ld']['other'].strip() - if False: - print - print opts - - print - print 'common_flags', flags['common_flags'] - print 'asm_flags', flags['asm_flags'] - print 'c_flags', flags['c_flags'] - print 'cxx_flags', flags['cxx_flags'] - print 'ld_flags', flags['ld_flags'] - @staticmethod def find_options(lst, option): tmp = [str for str in lst if str.startswith(option)] diff --git a/tools/export/iar/__init__.py b/tools/export/iar/__init__.py index 69b53dbb96..e3fa360afd 100644 --- a/tools/export/iar/__init__.py +++ b/tools/export/iar/__init__.py @@ -1,3 +1,6 @@ +from __future__ import print_function, absolute_import +from builtins import str + import os from os.path import sep, join, exists from collections import namedtuple @@ -181,7 +184,7 @@ class IAR(Exporter): else: out_string += "FAILURE" - print out_string + print(out_string) if log_name: # Write the output to the log file diff --git a/tools/export/makefile/__init__.py b/tools/export/makefile/__init__.py index 3c0fc2a857..683ecd08fa 100644 --- a/tools/export/makefile/__init__.py +++ b/tools/export/makefile/__init__.py @@ -14,6 +14,9 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. """ +from __future__ import print_function, absolute_import +from builtins import str + from os.path import splitext, basename, relpath, join, abspath, dirname,\ exists from os import remove @@ -178,7 +181,7 @@ class Makefile(Exporter): else: out_string += "FAILURE" - print out_string + print(out_string) if log_name: # Write the output to the log file diff --git a/tools/export/mcuxpresso/__init__.py b/tools/export/mcuxpresso/__init__.py index 8768d8537d..6c2789f1ae 100644 --- a/tools/export/mcuxpresso/__init__.py +++ b/tools/export/mcuxpresso/__init__.py @@ -22,6 +22,8 @@ the MCUXpresso IDE from NXP Based on GNU ARM Eclipse Exporter from Liviu Ionescu modified for MCUXpresso by Johannes Stratmann """ +from __future__ import print_function, absolute_import +from builtins import str import copy import tempfile @@ -39,9 +41,6 @@ from tools.utils import NotSupportedException from tools.build_api import prepare_toolchain -# ============================================================================= - - POST_BINARY_WHITELIST = set([ "TEENSY3_1Code.binary_hook", "MCU_NRF51Code.binary_hook", @@ -73,12 +72,6 @@ class MCUXpresso(GNUARMEclipse): if not self.resources.linker_script: raise NotSupportedException("No linker script found.") - print - print 'Create a GNU ARM Eclipse C++ managed project' - print 'Project name: {0}'.format(self.project_name) - print 'Target: {0}'.format(self.toolchain.target.name) - print 'Toolchain: {0}'.format(self.TOOLCHAIN) - self.resources.win_to_unix() # TODO: use some logger to display additional info if verbose @@ -115,16 +108,13 @@ class MCUXpresso(GNUARMEclipse): self.include_path = [ self.filter_dot(s) for s in self.resources.inc_dirs] - print 'Include folders: {0}'.format(len(self.include_path)) self.as_defines = self.toolchain.get_symbols(True) self.c_defines = self.toolchain.get_symbols() self.cpp_defines = self.c_defines - print 'Symbols: {0}'.format(len(self.c_defines)) self.ld_script = self.filter_dot( self.resources.linker_script) - print 'Linker script: {0}'.format(self.ld_script) self.options = {} profile_ids.remove('develop') @@ -143,7 +133,6 @@ class MCUXpresso(GNUARMEclipse): opts['name'] = opts['id'].capitalize() print - print 'Build configuration: {0}'.format(opts['name']) profile = profiles[id] @@ -159,12 +148,6 @@ class MCUXpresso(GNUARMEclipse): flags = self.toolchain_flags(toolchain) - print 'Common flags:', ' '.join(flags['common_flags']) - print 'C++ flags:', ' '.join(flags['cxx_flags']) - print 'C flags:', ' '.join(flags['c_flags']) - print 'ASM flags:', ' '.join(flags['asm_flags']) - print 'Linker flags:', ' '.join(flags['ld_flags']) - # Most GNU ARM Eclipse options have a parent, # either debug or release. if '-O0' in flags['common_flags'] or '-Og' in flags['common_flags']: @@ -227,8 +210,8 @@ class MCUXpresso(GNUARMEclipse): self.gen_file_nonoverwrite('mcuxpresso/mbedignore.tmpl', jinja_ctx, '.mbedignore') - print - print 'Done. Import the \'{0}\' project in Eclipse.'.format(self.project_name) + print('Done. Import the \'{0}\' project in MCUXpresso.'.format( + self.project_name)) @staticmethod def clean(_): @@ -296,7 +279,7 @@ class MCUXpresso(GNUARMEclipse): else: ret_string = "FAILURE: build returned %s \n" % ret_code - print "%s\n%s\n%s\n%s" % (stdout_string, out, err_string, ret_string) + print("%s\n%s\n%s\n%s" % (stdout_string, out, err_string, ret_string)) if log_name: # Write the output to the log file @@ -346,14 +329,6 @@ class MCUXpresso(GNUARMEclipse): # Make a copy of the flags, to be one by one removed after processing. flags = copy.deepcopy(flags_in) - if False: - print - print 'common_flags', flags['common_flags'] - print 'asm_flags', flags['asm_flags'] - print 'c_flags', flags['c_flags'] - print 'cxx_flags', flags['cxx_flags'] - print 'ld_flags', flags['ld_flags'] - # Initialise the 'last resort' options where all unrecognised # options will be collected. opts['as']['other'] = '' @@ -733,15 +708,3 @@ class MCUXpresso(GNUARMEclipse): opts['c']['other'] = opts['c']['other'].strip() opts['cpp']['other'] = opts['cpp']['other'].strip() opts['ld']['other'] = opts['ld']['other'].strip() - - if False: - print - print opts - - print - print 'common_flags', flags['common_flags'] - print 'asm_flags', flags['asm_flags'] - print 'c_flags', flags['c_flags'] - print 'cxx_flags', flags['cxx_flags'] - print 'ld_flags', flags['ld_flags'] - diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index 47a815f1d7..3ae81d0c51 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -1,9 +1,12 @@ +from __future__ import print_function, absolute_import +from builtins import str + import os import copy import shutil from os.path import relpath, join, exists, dirname, basename -from os import makedirs +from os import makedirs, remove from json import load from tools.export.exporters import Exporter, apply_supported_whitelist @@ -49,7 +52,7 @@ class GNUARMNetbeans(Exporter): config_header = self.toolchain.get_config_header() flags = {key + "_flags": copy.deepcopy(value) for key, value - in toolchain.flags.iteritems()} + in toolchain.flags.items()} if config_header: config_header = relpath(config_header, self.resources.file_basepath[config_header]) @@ -130,13 +133,8 @@ class GNUARMNetbeans(Exporter): # Convert all Backslashes to Forward Slashes self.resources.win_to_unix() - print 'Include folders: {0}'.format(len(self.resources.inc_dirs)) - - print 'Symbols: {0}'.format(len(self.toolchain.get_symbols())) - self.ld_script = self.filter_dot( self.resources.linker_script) - print 'Linker script: {0}'.format(self.ld_script) # Read in all profiles, we'll extract compiler options. profiles = self.get_all_profiles() @@ -157,9 +155,6 @@ class GNUARMNetbeans(Exporter): opts['id'] = prof_id opts['name'] = opts['id'].capitalize() - print - print 'Build configuration: {0}'.format(opts['name']) - profile = profiles[prof_id] # A small hack, do not bother with src_path again, @@ -172,12 +167,6 @@ class GNUARMNetbeans(Exporter): flags = self.toolchain_flags(toolchain) - print 'Common flags:', ' '.join(flags['common_flags']) - print 'C++ flags:', ' '.join(flags['cxx_flags']) - print 'C flags:', ' '.join(flags['c_flags']) - print 'ASM flags:', ' '.join(flags['asm_flags']) - print 'Linker flags:', ' '.join(flags['ld_flags']) - opts['defines'] = self.get_defines_and_remove_from_flags(flags, 'common_flags') opts['forced_includes'] = self.get_includes_and_remove_from_flags(flags, 'common_flags') opts['common'] = flags['common_flags'] @@ -258,12 +247,6 @@ class GNUARMNetbeans(Exporter): """ jinja_ctx = self.create_jinja_ctx() - print - print 'Create a GNU ARM Netbeans C++ managed project' - print 'Project name: {0}'.format(self.project_name) - print 'Target: {0}'.format(self.toolchain.target.name) - print 'Toolchain: {0}'.format(self.TOOLCHAIN) - if not exists(join(self.export_dir, 'nbproject')): makedirs(join(self.export_dir, 'nbproject')) @@ -273,8 +256,7 @@ class GNUARMNetbeans(Exporter): '.mbedignore') self.gen_file('nb/Makefile.tmpl', jinja_ctx, 'Makefile') - print - print 'Done. Import the \'{0}\' project in Netbeans.'.format(self.project_name) + print('Done. Import the \'{0}\' project in Netbeans.'.format(self.project_name)) @staticmethod def clean(_): diff --git a/tools/export/sw4stm32/__init__.py b/tools/export/sw4stm32/__init__.py index 607840fa48..1d24fb91c7 100644 --- a/tools/export/sw4stm32/__init__.py +++ b/tools/export/sw4stm32/__init__.py @@ -14,6 +14,8 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. """ +from __future__ import print_function, absolute_import +from builtins import str from os.path import splitext, basename, join import shutil @@ -420,10 +422,10 @@ class Sw4STM32(GNUARMEclipse): if not self.resources.linker_script: raise NotSupportedException("No linker script found.") - print ('\nCreate a System Workbench for STM32 managed project') - print ('Project name: {0}'.format(self.project_name)) - print ('Target: {0}'.format(self.toolchain.target.name)) - print ('Toolchain: {0}'.format(self.TOOLCHAIN) + '\n') + print('\nCreate a System Workbench for STM32 managed project') + print('Project name: {0}'.format(self.project_name)) + print('Target: {0}'.format(self.toolchain.target.name)) + print('Toolchain: {0}'.format(self.TOOLCHAIN) + '\n') self.resources.win_to_unix() @@ -444,19 +446,18 @@ class Sw4STM32(GNUARMEclipse): self.c_defines = [s.replace('"', '"') for s in self.toolchain.get_symbols()] self.cpp_defines = self.c_defines - print 'Symbols: {0}'.format(len(self.c_defines)) self.include_path = [] for s in self.resources.inc_dirs: self.include_path.append("../" + self.filter_dot(s)) - print ('Include folders: {0}'.format(len(self.include_path))) + print('Include folders: {0}'.format(len(self.include_path))) self.compute_exclusions() - print ('Exclude folders: {0}'.format(len(self.excluded_folders))) + print('Exclude folders: {0}'.format(len(self.excluded_folders))) ld_script = self.filter_dot(self.resources.linker_script) - print ('Linker script: {0}'.format(ld_script)) + print('Linker script: {0}'.format(ld_script)) lib_dirs = [self.filter_dot(s) for s in self.resources.lib_dirs] @@ -473,9 +474,6 @@ class Sw4STM32(GNUARMEclipse): opts['id'] = id opts['name'] = opts['id'].capitalize() - # TODO: Add prints to log or console in verbose mode. - #print ('\nBuild configuration: {0}'.format(opts['name'])) - profile = profiles[id] # A small hack, do not bother with src_path again, @@ -489,13 +487,6 @@ class Sw4STM32(GNUARMEclipse): flags = self.toolchain_flags(toolchain) - # TODO: Add prints to log or console in verbose mode. - # print 'Common flags:', ' '.join(flags['common_flags']) - # print 'C++ flags:', ' '.join(flags['cxx_flags']) - # print 'C flags:', ' '.join(flags['c_flags']) - # print 'ASM flags:', ' '.join(flags['asm_flags']) - # print 'Linker flags:', ' '.join(flags['ld_flags']) - # Most GNU ARM Eclipse options have a parent, # either debug or release. if '-O0' in flags['common_flags'] or '-Og' in flags['common_flags']: diff --git a/tools/export/uvision/__init__.py b/tools/export/uvision/__init__.py index 749dffa6cd..38ff88dfb6 100644 --- a/tools/export/uvision/__init__.py +++ b/tools/export/uvision/__init__.py @@ -1,3 +1,6 @@ +from __future__ import print_function, absolute_import +from builtins import str + import os from os.path import sep, normpath, join, exists import ntpath @@ -12,9 +15,6 @@ from tools.targets import TARGET_MAP from tools.export.exporters import Exporter, apply_supported_whitelist from tools.export.cmsis import DeviceCMSIS -cache_d = False - - class DeviceUvision(DeviceCMSIS): """Uvision Device class, inherits CMSIS Device class @@ -189,7 +189,7 @@ class Uvision(Exporter): grouped = self.group_project_files(srcs) for group, files in grouped.items(): grouped[group] = sorted(list(self.uv_files(files)), - key=lambda (_, __, name): name.lower()) + key=lambda tuple: tuple[2].lower()) return grouped @staticmethod @@ -205,8 +205,6 @@ class Uvision(Exporter): def generate(self): """Generate the .uvproj file""" cache = Cache(True, False) - if cache_d: - cache.cache_descriptors() srcs = self.resources.headers + self.resources.s_sources + \ self.resources.c_sources + self.resources.cpp_sources + \ @@ -216,7 +214,7 @@ class Uvision(Exporter): # project_files => dict of generators - file group to generator of # UVFile tuples defined above 'project_files': sorted(list(self.format_src(srcs).items()), - key=lambda (group, _): group.lower()), + key=lambda tuple: tuple[0].lower()), 'include_paths': '; '.join(self.resources.inc_dirs).encode('utf-8'), 'device': DeviceUvision(self.target), } @@ -262,7 +260,7 @@ class Uvision(Exporter): # Print the log file to stdout with open(log_name, 'r') as f: - print f.read() + print(f.read()) # Cleanup the exported and built files if cleanup: diff --git a/tools/export/vscode/__init__.py b/tools/export/vscode/__init__.py index 450e04537f..9cfa1f4836 100644 --- a/tools/export/vscode/__init__.py +++ b/tools/export/vscode/__init__.py @@ -12,6 +12,9 @@ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. +from __future__ import print_function, absolute_import +from builtins import str + from os.path import join, exists, realpath, relpath, basename, isfile, splitext from os import makedirs, listdir, remove, rmdir @@ -46,7 +49,7 @@ class VSCode(Makefile): self.gen_file('vscode/%s.tmpl' % file, ctx, '.vscode/%s.json' % file) else: - print 'Keeping existing %s.json' % file + print('Keeping existing %s.json' % file) # So.... I want all .h and .hpp files in self.resources.inc_dirs all_directories = [] diff --git a/tools/project.py b/tools/project.py index e1fbae5136..c413aa150f 100644 --- a/tools/project.py +++ b/tools/project.py @@ -1,7 +1,9 @@ """ The CLI entry point for exporting projects from the mbed tools to any of the supported IDEs or project structures. """ -from __future__ import absolute_import, print_function +from __future__ import print_function, absolute_import +from builtins import str + import sys from os.path import (join, abspath, dirname, exists, basename, normpath, realpath, relpath, basename) @@ -105,7 +107,7 @@ def main(): targetnames = TARGET_NAMES targetnames.sort() - toolchainlist = EXPORTERS.keys() + toolchainlist = list(EXPORTERS.keys()) toolchainlist.sort() parser.add_argument("-m", "--mcu", @@ -259,7 +261,7 @@ def main(): cls.clean(basename(abspath(options.source_dir[0]))) except (NotImplementedError, IOError, OSError): pass - for f in EXPORTERS.values()[0].CLEAN_FILES: + for f in list(EXPORTERS.values())[0].CLEAN_FILES: try: remove(f) except (IOError, OSError): diff --git a/tools/toolchains/arm.py b/tools/toolchains/arm.py index 2df0bfac10..5d36c37d44 100644 --- a/tools/toolchains/arm.py +++ b/tools/toolchains/arm.py @@ -14,6 +14,9 @@ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. """ +from __future__ import print_function, absolute_import +from builtins import str + import re from copy import copy from os.path import join, dirname, splitext, basename, exists, relpath @@ -196,7 +199,7 @@ class ARM(mbedToolchain): Side Effects: This method MAY write a new scatter file to disk """ - with open(scatter_file, "rb") as input: + with open(scatter_file, "r") as input: lines = input.readlines() if (lines[0].startswith(self.SHEBANG) or not lines[0].startswith("#!")): @@ -206,7 +209,7 @@ class ARM(mbedToolchain): self.SHEBANG += " -I %s" % relpath(dirname(scatter_file), base_path) if self.need_update(new_scatter, [scatter_file]): - with open(new_scatter, "wb") as out: + with open(new_scatter, "w") as out: out.write(self.SHEBANG) out.write("\n") out.write("".join(lines[1:])) From 4611bb699e3d85dc60e08e2be2a8f4d140421ab3 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Fri, 16 Mar 2018 13:18:04 -0500 Subject: [PATCH 078/118] Correct type issue in export arg parsing --- tools/project.py | 1 - 1 file changed, 1 deletion(-) diff --git a/tools/project.py b/tools/project.py index c413aa150f..a8654c1963 100644 --- a/tools/project.py +++ b/tools/project.py @@ -112,7 +112,6 @@ def main(): parser.add_argument("-m", "--mcu", metavar="MCU", - type=str.upper, help="generate project for the given MCU ({})".format( ', '.join(targetnames))) From cd8f5834c3514552fd098874ebaec75de1619d38 Mon Sep 17 00:00:00 2001 From: Hugues de Valon Date: Tue, 13 Mar 2018 15:17:53 +0000 Subject: [PATCH 079/118] Add ASM flags virtual path for make export When exporting a mbed project to make_armc5, the include options (-I) of the ASM flags are not pointing to the good folder. It should be pointing to the root mbed-os folder and not the one in BUILD. This issue was found in the pull request ARMmbed/mbed-os#6168. Signed-off-by: Hugues de Valon --- tools/export/makefile/__init__.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/export/makefile/__init__.py b/tools/export/makefile/__init__.py index 683ecd08fa..3002b66a79 100644 --- a/tools/export/makefile/__init__.py +++ b/tools/export/makefile/__init__.py @@ -124,6 +124,10 @@ class Makefile(Exporter): 'to_be_compiled']: ctx[key] = sorted(ctx[key]) ctx.update(self.format_flags()) + # Add the virtual path the the include option in the ASM flags + for index, flag in enumerate(ctx['asm_flags']): + if flag.startswith('-I'): + ctx['asm_flags'][index] = "-I" + ctx['vpath'][0] + "/" + ctx['asm_flags'][index][2:] for templatefile in \ ['makefile/%s_%s.tmpl' % (self.TEMPLATE, From f2dcff5e4afd4f071bcd86ccb7b1ef7c8215d80d Mon Sep 17 00:00:00 2001 From: Hugues de Valon Date: Tue, 13 Mar 2018 15:22:43 +0000 Subject: [PATCH 080/118] Add ASM include flags in uvision export When exporting to a uvision project, the include flags are not put in the assembly compilation line. When assembling the files containing includes, the search path will then fail. This patch adds the include paths to the Assembly sequence, as it is done for compilation. This issue was found in the pull request ARMmbed/mbed-os#6168. Signed-off-by: Hugues de Valon --- tools/export/uvision/uvision.tmpl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/export/uvision/uvision.tmpl b/tools/export/uvision/uvision.tmpl index f49c79659d..49c708c3bb 100644 --- a/tools/export/uvision/uvision.tmpl +++ b/tools/export/uvision/uvision.tmpl @@ -394,7 +394,7 @@ {{asm_flags}} - + {{include_paths}} From 95ca5de41d632c2b29f7efe72ae047927f809a6c Mon Sep 17 00:00:00 2001 From: Cruz Monrreal II Date: Mon, 19 Mar 2018 11:13:22 -0500 Subject: [PATCH 081/118] Disabled flash clock and cache test for NRF52 MCUs. This is meant to be a temporary fix until the issue has been root caused, and Jenkins CI is no longer intermittently failing. --- TESTS/mbed_hal/flash/functional_tests/main.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/TESTS/mbed_hal/flash/functional_tests/main.cpp b/TESTS/mbed_hal/flash/functional_tests/main.cpp index af101b7232..4b28510c68 100644 --- a/TESTS/mbed_hal/flash/functional_tests/main.cpp +++ b/TESTS/mbed_hal/flash/functional_tests/main.cpp @@ -279,7 +279,9 @@ Case cases[] = { Case("Flash - erase sector", flash_erase_sector_test), Case("Flash - program page", flash_program_page_test), Case("Flash - buffer alignment test", flash_buffer_alignment_test), +#ifndef MCU_NRF52 Case("Flash - clock and cache test", flash_clock_and_cache_test), +#endif }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) { From 5cb29a7ea491630abf22657b16135d6628caa96f Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Thu, 8 Mar 2018 12:46:44 +0200 Subject: [PATCH 082/118] Own SIM state retrieval for Quectel BC95 --- .../targets/QUECTEL/BC95/QUECTEL_BC95.cpp | 31 +++++++++++- .../targets/QUECTEL/BC95/QUECTEL_BC95.h | 1 + .../QUECTEL/BC95/QUECTEL_BC95_CellularSIM.cpp | 49 +++++++++++++++++++ .../QUECTEL/BC95/QUECTEL_BC95_CellularSIM.h | 37 ++++++++++++++ 4 files changed, 116 insertions(+), 2 deletions(-) create mode 100644 features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularSIM.cpp create mode 100644 features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularSIM.h diff --git a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.cpp b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.cpp index 30736b4549..84f446542f 100644 --- a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.cpp +++ b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.cpp @@ -17,6 +17,7 @@ #include "QUECTEL_BC95_CellularNetwork.h" #include "QUECTEL_BC95_CellularPower.h" +#include "QUECTEL_BC95_CellularSIM.h" #include "QUECTEL_BC95.h" @@ -41,7 +42,13 @@ QUECTEL_BC95::~QUECTEL_BC95() CellularNetwork *QUECTEL_BC95::open_network(FileHandle *fh) { if (!_network) { - _network = new QUECTEL_BC95_CellularNetwork(*get_at_handler(fh)); + ATHandler *atHandler = get_at_handler(fh); + if (atHandler) { + _network = new QUECTEL_BC95_CellularNetwork(*atHandler); + if (!_network) { + release_at_handler(atHandler); + } + } } return _network; } @@ -49,7 +56,27 @@ CellularNetwork *QUECTEL_BC95::open_network(FileHandle *fh) CellularPower *QUECTEL_BC95::open_power(FileHandle *fh) { if (!_power) { - _power = new QUECTEL_BC95_CellularPower(*get_at_handler(fh)); + ATHandler *atHandler = get_at_handler(fh); + if (atHandler) { + _power = new QUECTEL_BC95_CellularPower(*atHandler); + if (!_power) { + release_at_handler(atHandler); + } + } } return _power; } + +CellularSIM *QUECTEL_BC95::open_sim(FileHandle *fh) +{ + if (!_sim) { + ATHandler *atHandler = get_at_handler(fh); + if (atHandler) { + _sim = new QUECTEL_BC95_CellularSIM(*atHandler); + if (!_sim) { + release_at_handler(atHandler); + } + } + } + return _sim; +} diff --git a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.h b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.h index 9dbce43544..adfa1ccc61 100644 --- a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.h +++ b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95.h @@ -32,6 +32,7 @@ public: public: // CellularDevice virtual CellularNetwork *open_network(FileHandle *fh); virtual CellularPower *open_power(FileHandle *fh); + virtual CellularSIM *open_sim(FileHandle *fh); public: // NetworkInterface void handle_urc(FileHandle *fh); diff --git a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularSIM.cpp b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularSIM.cpp new file mode 100644 index 0000000000..a3cd04d06a --- /dev/null +++ b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularSIM.cpp @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2017, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "QUECTEL_BC95_CellularSIM.h" +#include "CellularLog.h" + +using namespace mbed; + +QUECTEL_BC95_CellularSIM::QUECTEL_BC95_CellularSIM(ATHandler &atHandler) : AT_CellularSIM(atHandler) +{ + +} + +QUECTEL_BC95_CellularSIM::~QUECTEL_BC95_CellularSIM() +{ + +} + +nsapi_error_t QUECTEL_BC95_CellularSIM::get_sim_state(SimState &state) +{ + _at.lock(); + _at.flush(); + _at.cmd_start("AT+NCCID?"); + _at.cmd_stop(); + _at.resp_start("+NCCID:"); + if (_at.info_resp()) { + state = SimStateReady; + } else { + tr_warn("SIM not readable."); + state = SimStateUnknown; // SIM may not be ready yet + } + _at.resp_stop(); + return _at.unlock_return_error(); +} + diff --git a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularSIM.h b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularSIM.h new file mode 100644 index 0000000000..26798857f5 --- /dev/null +++ b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularSIM.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2017, Arm Limited and affiliates. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef QUECTEL_BC95_CELLULAR_SIM_H_ +#define QUECTEL_BC95_CELLULAR_SIM_H_ + +#include "AT_CellularSIM.h" + +namespace mbed { + +class QUECTEL_BC95_CellularSIM : public AT_CellularSIM +{ +public: + QUECTEL_BC95_CellularSIM(ATHandler &atHandler); + virtual ~QUECTEL_BC95_CellularSIM(); + +public: //from CellularSIM + virtual nsapi_error_t get_sim_state(SimState &state); +}; + +} // namespace mbed + +#endif // QUECTEL_BC95_CELLULAR_SIM_H_ From a708296f29b6656fbfa68cc31b137eb1391067d1 Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Thu, 8 Mar 2018 12:50:14 +0200 Subject: [PATCH 083/118] Release AT handler if network not created --- .../framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp index 5fd746d48e..59b090ccc6 100644 --- a/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp +++ b/features/cellular/framework/targets/QUECTEL/BG96/QUECTEL_BG96.cpp @@ -40,7 +40,13 @@ QUECTEL_BG96::~QUECTEL_BG96() CellularNetwork *QUECTEL_BG96::open_network(FileHandle *fh) { if (!_network) { - _network = new QUECTEL_BG96_CellularNetwork(*get_at_handler(fh)); + ATHandler *atHandler = get_at_handler(fh); + if (atHandler) { + _network = new QUECTEL_BG96_CellularNetwork(*atHandler); + if (!_network) { + release_at_handler(atHandler); + } + } } return _network; } From 79fa5775b4ac7d3e75e0c28a1d4f44c11c44b8f7 Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Thu, 8 Mar 2018 12:53:52 +0200 Subject: [PATCH 084/118] Fix wrong header define name --- .../targets/QUECTEL/BC95/QUECTEL_BC95_CellularPower.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularPower.h b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularPower.h index c51a12d3d5..1f0bfee809 100644 --- a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularPower.h +++ b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularPower.h @@ -15,8 +15,8 @@ * limitations under the License. */ -#ifndef TELIT_HE910_CELLULAR_POWER_H_ -#define TELIT_HE910_CELLULAR_POWER_H_ +#ifndef QUECTEL_BC95_CELLULAR_POWER_H_ +#define QUECTEL_BC95_CELLULAR_POWER_H_ #include "AT_CellularPower.h" @@ -36,4 +36,4 @@ public: //from CellularPower } // namespace mbed -#endif // TELIT_HE910_CELLULAR_POWER_H_ +#endif // QUECTEL_BC95_CELLULAR_POWER_H_ From b620a35ed37bcc09b1efa5bb2890b93fe995ce0d Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Thu, 8 Mar 2018 12:58:12 +0200 Subject: [PATCH 085/118] Use of APN lookup decision logic fixed --- .../easy_cellular/EasyCellularConnection.cpp | 20 +++++++++---------- .../easy_cellular/EasyCellularConnection.h | 6 ++++-- .../framework/AT/AT_CellularNetwork.cpp | 14 +++++++++++-- 3 files changed, 26 insertions(+), 14 deletions(-) diff --git a/features/cellular/easy_cellular/EasyCellularConnection.cpp b/features/cellular/easy_cellular/EasyCellularConnection.cpp index 733490ee90..7be4c8207e 100644 --- a/features/cellular/easy_cellular/EasyCellularConnection.cpp +++ b/features/cellular/easy_cellular/EasyCellularConnection.cpp @@ -29,9 +29,9 @@ #include "CellularLog.h" #include "mbed_wait_api.h" -#if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#if USE_APN_LOOKUP #include "APN_db.h" -#endif //MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#endif //USE_APN_LOOKUP namespace mbed { @@ -59,9 +59,9 @@ EasyCellularConnection::EasyCellularConnection(bool debug) : NSAPI_ERROR_OK) { tr_info("EasyCellularConnection()"); -#if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#if USE_APN_LOOKUP _credentials_set = false; -#endif // #if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#endif // #if USE_APN_LOOKUP modem_debug_on(debug); } @@ -102,11 +102,11 @@ void EasyCellularConnection::set_credentials(const char *apn, const char *uname, CellularNetwork * network = _cellularConnectionFSM.get_network(); if (network) { _credentials_err = network->set_credentials(apn, uname, pwd); -#if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#if USE_APN_LOOKUP if (_credentials_err == NSAPI_ERROR_OK) { _credentials_set = true; } -#endif // #if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#endif // #if USE_APN_LOOKUP } else { tr_error("NO Network..."); } @@ -163,7 +163,7 @@ nsapi_error_t EasyCellularConnection::connect() if (err) { return err; } -#if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#if USE_APN_LOOKUP if (!_credentials_set) { _target_state = CellularConnectionFSM::STATE_SIM_PIN; err = _cellularConnectionFSM.continue_to_state(_target_state); @@ -193,7 +193,7 @@ nsapi_error_t EasyCellularConnection::connect() return err; } } -#endif // MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#endif // USE_APN_LOOKUP _target_state = CellularConnectionFSM::STATE_CONNECTED; err = _cellularConnectionFSM.continue_to_state(_target_state); @@ -212,9 +212,9 @@ nsapi_error_t EasyCellularConnection::disconnect() { _credentials_err = NSAPI_ERROR_OK; _is_connected = false; -#if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#if USE_APN_LOOKUP _credentials_set = false; -#endif // #if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#endif // #if USE_APN_LOOKUP if (!_cellularConnectionFSM.get_network()) { return NSAPI_ERROR_NO_CONNECTION; } diff --git a/features/cellular/easy_cellular/EasyCellularConnection.h b/features/cellular/easy_cellular/EasyCellularConnection.h index 37d231f72d..d16784a012 100644 --- a/features/cellular/easy_cellular/EasyCellularConnection.h +++ b/features/cellular/easy_cellular/EasyCellularConnection.h @@ -24,6 +24,8 @@ #include "netsocket/CellularBase.h" +#define USE_APN_LOOKUP (MBED_CONF_CELLULAR_USE_APN_LOOKUP || (NSAPI_PPP_AVAILABLE && MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP)) + namespace mbed { @@ -145,9 +147,9 @@ private: bool _is_connected; bool _is_initialized; -#if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#if USE_APN_LOOKUP bool _credentials_set; -#endif // #if MBED_CONF_CELLULAR_USE_APN_LOOKUP || MBED_CONF_PPP_CELL_IFACE_APN_LOOKUP +#endif // #if USE_APN_LOOKUP CellularConnectionFSM::CellularState _target_state; UARTSerial _cellularSerial; diff --git a/features/cellular/framework/AT/AT_CellularNetwork.cpp b/features/cellular/framework/AT/AT_CellularNetwork.cpp index 5c05d35e1f..6799e98cbf 100644 --- a/features/cellular/framework/AT/AT_CellularNetwork.cpp +++ b/features/cellular/framework/AT/AT_CellularNetwork.cpp @@ -133,6 +133,7 @@ nsapi_error_t AT_CellularNetwork::connect(const char *apn, nsapi_error_t AT_CellularNetwork::delete_current_context() { + tr_info("Delete context %d", _cid); _at.clear_error(); _at.cmd_start("AT+CGDCONT="); _at.write_int(_cid); @@ -236,12 +237,14 @@ nsapi_error_t AT_CellularNetwork::open_data_channel() int context_activation_state = _at.read_int(); if (context_id == _cid && context_activation_state == 1) { is_context_active = true; + tr_debug("PDP context %d is active.", _cid); + break; } } _at.resp_stop(); if (!is_context_active) { - tr_info("Activate PDP context"); + tr_info("Activate PDP context %d", _cid); _at.cmd_start("AT+CGACT=1,"); _at.write_int(_cid); _at.cmd_stop(); @@ -401,6 +404,7 @@ bool AT_CellularNetwork::set_new_context(int cid) _ip_stack_type = tmp_stack; _cid = cid; _new_context_set = true; + tr_info("New PDP context id %d was created", _cid); } return success; @@ -408,6 +412,12 @@ bool AT_CellularNetwork::set_new_context(int cid) bool AT_CellularNetwork::get_context() { + if (_apn) { + tr_debug("APN in use: %s", _apn); + } else { + tr_debug("NO APN"); + } + _at.cmd_start("AT+CGDCONT?"); _at.cmd_stop(); _at.resp_start("+CGDCONT:"); @@ -429,7 +439,7 @@ bool AT_CellularNetwork::get_context() if (pdp_type_len > 0) { apn_len = _at.read_string(apn, sizeof(apn) - 1); if (apn_len >= 0) { - if (_apn && strcmp(apn, _apn) != 0 ) { + if (_apn && (strcmp(apn, _apn) != 0) ) { continue; } nsapi_ip_stack_t pdp_stack = string_to_stack_type(pdp_type_from_context); From 3cbfd3faadac5116b6faedd545e74fff42bc4a6c Mon Sep 17 00:00:00 2001 From: Mirela Chirica Date: Thu, 8 Mar 2018 13:00:14 +0200 Subject: [PATCH 086/118] Quectel BC95 echo test fixes Fixing get host by name and iterate send/recv socket operations. --- .../targets/QUECTEL/BC95/QUECTEL_BC95_CellularStack.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularStack.cpp b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularStack.cpp index 4b77532f34..a63806f7d0 100644 --- a/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularStack.cpp +++ b/features/cellular/framework/targets/QUECTEL/BC95/QUECTEL_BC95_CellularStack.cpp @@ -150,7 +150,8 @@ nsapi_size_or_error_t QUECTEL_BC95_CellularStack::socket_sendto_impl(CellularSoc _at.write_string(hexstr, false); _at.cmd_stop(); _at.resp_start(); - socket->id = _at.read_int(); + // skip socket id + _at.skip_param(); sent_len = _at.read_int(); _at.resp_stop(); @@ -182,6 +183,7 @@ nsapi_size_or_error_t QUECTEL_BC95_CellularStack::socket_recvfrom_impl(CellularS _at.read_string(hexstr, sizeof(hexstr)); // remaining length _at.skip_param(); + _at.resp_stop(); if (!recv_len || (recv_len == -1) || (_at.get_last_error() != NSAPI_ERROR_OK)) { return NSAPI_ERROR_WOULD_BLOCK; From f2db21f71db11bc24b6db10d0b7e905462931b47 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Thu, 15 Mar 2018 11:12:09 +0100 Subject: [PATCH 087/118] STM32 LPTICKER : optimize RTC wake up timer init Division in a while loop is removed --- targets/TARGET_STM/rtc_api.c | 37 +++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/targets/TARGET_STM/rtc_api.c b/targets/TARGET_STM/rtc_api.c index 34559869bf..28bcde11dd 100644 --- a/targets/TARGET_STM/rtc_api.c +++ b/targets/TARGET_STM/rtc_api.c @@ -330,6 +330,11 @@ uint32_t rtc_read_us(void) void rtc_set_wake_up_timer(uint32_t delta) { +#define RTC_CLOCK_US (((uint64_t)RTC_CLOCK << 32 ) / 1000000) + + uint32_t WakeUpCounter; + uint32_t WakeUpClock; + /* Ex for Wakeup period resolution with RTCCLK=32768 Hz : * RTCCLK_DIV2: ~122us < wakeup period < ~4s * RTCCLK_DIV4: ~244us < wakeup period < ~8s @@ -338,19 +343,21 @@ void rtc_set_wake_up_timer(uint32_t delta) * CK_SPRE_16BITS: 1s < wakeup period < (0xFFFF+ 1) x 1 s = 65536 s (18 hours) * CK_SPRE_17BITS: 18h+1s < wakeup period < (0x1FFFF+ 1) x 1 s = 131072 s (36 hours) */ - uint32_t WakeUpClock[6] = {RTC_WAKEUPCLOCK_RTCCLK_DIV2, RTC_WAKEUPCLOCK_RTCCLK_DIV4, RTC_WAKEUPCLOCK_RTCCLK_DIV8, RTC_WAKEUPCLOCK_RTCCLK_DIV16, RTC_WAKEUPCLOCK_CK_SPRE_16BITS, RTC_WAKEUPCLOCK_CK_SPRE_17BITS}; - uint8_t ClockDiv[4] = {2, 4, 8, 16}; - uint32_t WakeUpCounter; - uint8_t DivIndex = 0; - - do { - WakeUpCounter = delta / (ClockDiv[DivIndex] * 1000000 / RTC_CLOCK); - DivIndex++; - } while ( (WakeUpCounter > 0xFFFF) && (DivIndex < 4) ); - - if (WakeUpCounter > 0xFFFF) { - WakeUpCounter = delta / 1000000; - DivIndex++; + if (delta < (0x10000 * 2 / RTC_CLOCK * 1000000) ) { // (0xFFFF + 1) * RTCCLK_DIV2 / RTC_CLOCK * 1s + WakeUpCounter = (((uint64_t)delta * RTC_CLOCK_US) >> 32) >> 1 ; + WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV2; + } else if (delta < (0x10000 * 4 / RTC_CLOCK * 1000000) ) { + WakeUpCounter = (((uint64_t)delta * RTC_CLOCK_US) >> 32) >> 2 ; + WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV4; + } else if (delta < (0x10000 * 8 / RTC_CLOCK * 1000000) ) { + WakeUpCounter = (((uint64_t)delta * RTC_CLOCK_US) >> 32) >> 3 ; + WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV8; + } else if (delta < (0x10000 * 16 / RTC_CLOCK * 1000000) ) { + WakeUpCounter = (((uint64_t)delta * RTC_CLOCK_US) >> 32) >> 4 ; + WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV16; + } else { + WakeUpCounter = (delta / 1000000) ; + WakeUpClock = RTC_WAKEUPCLOCK_CK_SPRE_16BITS; } irq_handler = (void (*)(void))lp_ticker_irq_handler; @@ -358,8 +365,8 @@ void rtc_set_wake_up_timer(uint32_t delta) NVIC_EnableIRQ(RTC_WKUP_IRQn); RtcHandle.Instance = RTC; - if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, 0xFFFF & WakeUpCounter, WakeUpClock[DivIndex - 1]) != HAL_OK) { - error("rtc_set_wake_up_timer init error (%d)\n", DivIndex); + if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, (uint32_t)WakeUpCounter, WakeUpClock) != HAL_OK) { + error("rtc_set_wake_up_timer init error\n"); } } From aad97a6d34308c6580844d695527b7a4e04fce69 Mon Sep 17 00:00:00 2001 From: Deepika Date: Wed, 14 Mar 2018 13:58:20 -0500 Subject: [PATCH 088/118] dir seek fixed - dptr was not updated before checking --- features/filesystem/fat/FATFileSystem.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/features/filesystem/fat/FATFileSystem.cpp b/features/filesystem/fat/FATFileSystem.cpp index 05e4849609..70cd2ffb53 100644 --- a/features/filesystem/fat/FATFileSystem.cpp +++ b/features/filesystem/fat/FATFileSystem.cpp @@ -724,6 +724,7 @@ void FATFileSystem::dir_seek(fs_dir_t dir, off_t offset) FRESULT res; res = f_readdir(dh, &finfo); + dptr = dh->dptr; if (res != FR_OK) { break; } else if (finfo.fname[0] == 0) { From 6d4e280160ab02c02dcc80b3de35bfedb559c776 Mon Sep 17 00:00:00 2001 From: Mudassar Hussain Date: Tue, 13 Mar 2018 20:49:31 +0500 Subject: [PATCH 089/118] Cellular: update attach test --- .../cellular/framework/AT/AT_CellularNetwork.cpp | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/features/cellular/framework/AT/AT_CellularNetwork.cpp b/features/cellular/framework/AT/AT_CellularNetwork.cpp index 6799e98cbf..23f389ff22 100644 --- a/features/cellular/framework/AT/AT_CellularNetwork.cpp +++ b/features/cellular/framework/AT/AT_CellularNetwork.cpp @@ -556,10 +556,20 @@ nsapi_error_t AT_CellularNetwork::set_registration(const char *plmn) if (!plmn) { tr_debug("Automatic network registration"); - _at.cmd_start("AT+COPS=0"); + uint8_t len=8; + uint8_t buf[8]; + _at.cmd_start("AT+COPS?"); _at.cmd_stop(); _at.resp_start(); + _at.read_bytes(buf,len); _at.resp_stop(); + if (strncmp((char*)buf,"+COPS: 0",len) != 0) { + _at.clear_error(); + _at.cmd_start("AT+COPS=0"); + _at.cmd_stop(); + _at.resp_start(); + _at.resp_stop(); + } } else { tr_debug("Manual network registration to %s", plmn); _at.cmd_start("AT+COPS=4,2,"); From a8cde30c2d0d38d2242250671fe132445f878aa5 Mon Sep 17 00:00:00 2001 From: Mudassar Hussain Date: Thu, 15 Mar 2018 10:41:00 +0500 Subject: [PATCH 090/118] Removed strncmp --- features/cellular/framework/AT/AT_CellularNetwork.cpp | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/features/cellular/framework/AT/AT_CellularNetwork.cpp b/features/cellular/framework/AT/AT_CellularNetwork.cpp index 23f389ff22..f9306fe206 100644 --- a/features/cellular/framework/AT/AT_CellularNetwork.cpp +++ b/features/cellular/framework/AT/AT_CellularNetwork.cpp @@ -556,14 +556,12 @@ nsapi_error_t AT_CellularNetwork::set_registration(const char *plmn) if (!plmn) { tr_debug("Automatic network registration"); - uint8_t len=8; - uint8_t buf[8]; _at.cmd_start("AT+COPS?"); _at.cmd_stop(); - _at.resp_start(); - _at.read_bytes(buf,len); + _at.resp_start("AT+COPS:"); + int mode = _at.read_int(); _at.resp_stop(); - if (strncmp((char*)buf,"+COPS: 0",len) != 0) { + if (mode != 0) { _at.clear_error(); _at.cmd_start("AT+COPS=0"); _at.cmd_stop(); From 4c93aa262ec3bf1e7a18aede50cdab0e49626448 Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Mon, 12 Mar 2018 15:51:52 -0500 Subject: [PATCH 091/118] littlefs: Fixed issue updating dir struct when extended dir chain Like most of the lfs_dir_t functions, lfs_dir_append is responsible for updating the lfs_dir_t struct if the underlying directory block is moved. This property makes handling worn out blocks much easier by removing the amount of state that needs to be considered during a directory update. However, extending the dir chain is a bit of a corner case. It's not changing the old block, but callers of lfs_dir_append do assume the "entry" will reside in "dir" after lfs_dir_append completes. This issue only occurs when creating files, since mkdir does not use the entry after lfs_dir_append. Unfortunately, the tests against extending the directory chain were all made using mkdir. Found by schouleu --- features/filesystem/littlefs/littlefs/lfs.c | 20 +++--- .../littlefs/littlefs/tests/test_dirs.sh | 66 +++++++++++++++++++ .../littlefs/littlefs/tests/test_files.sh | 19 ++++++ 3 files changed, 95 insertions(+), 10 deletions(-) diff --git a/features/filesystem/littlefs/littlefs/lfs.c b/features/filesystem/littlefs/littlefs/lfs.c index fb167c2c0e..3ba8b3b708 100644 --- a/features/filesystem/littlefs/littlefs/lfs.c +++ b/features/filesystem/littlefs/littlefs/lfs.c @@ -658,17 +658,17 @@ static int lfs_dir_append(lfs_t *lfs, lfs_dir_t *dir, // we need to allocate a new dir block if (!(0x80000000 & dir->d.size)) { - lfs_dir_t newdir; - int err = lfs_dir_alloc(lfs, &newdir); + lfs_dir_t olddir = *dir; + int err = lfs_dir_alloc(lfs, dir); if (err) { return err; } - newdir.d.tail[0] = dir->d.tail[0]; - newdir.d.tail[1] = dir->d.tail[1]; - entry->off = newdir.d.size - 4; + dir->d.tail[0] = olddir.d.tail[0]; + dir->d.tail[1] = olddir.d.tail[1]; + entry->off = dir->d.size - 4; lfs_entry_tole32(&entry->d); - err = lfs_dir_commit(lfs, &newdir, (struct lfs_region[]){ + err = lfs_dir_commit(lfs, dir, (struct lfs_region[]){ {entry->off, 0, &entry->d, sizeof(entry->d)}, {entry->off, 0, data, entry->d.nlen} }, 2); @@ -677,10 +677,10 @@ static int lfs_dir_append(lfs_t *lfs, lfs_dir_t *dir, return err; } - dir->d.size |= 0x80000000; - dir->d.tail[0] = newdir.pair[0]; - dir->d.tail[1] = newdir.pair[1]; - return lfs_dir_commit(lfs, dir, NULL, 0); + olddir.d.size |= 0x80000000; + olddir.d.tail[0] = dir->pair[0]; + olddir.d.tail[1] = dir->pair[1]; + return lfs_dir_commit(lfs, &olddir, NULL, 0); } int err = lfs_dir_fetch(lfs, dir, dir->d.tail); diff --git a/features/filesystem/littlefs/littlefs/tests/test_dirs.sh b/features/filesystem/littlefs/littlefs/tests/test_dirs.sh index 9f9733dd71..53d76f7a8d 100755 --- a/features/filesystem/littlefs/littlefs/tests/test_dirs.sh +++ b/features/filesystem/littlefs/littlefs/tests/test_dirs.sh @@ -118,6 +118,7 @@ tests/test.py << TEST sprintf((char*)buffer, "test%d", i); lfs_dir_read(&lfs, &dir[0], &info) => 1; strcmp(info.name, (char*)buffer) => 0; + info.type => LFS_TYPE_DIR; } lfs_dir_read(&lfs, &dir[0], &info) => 0; lfs_unmount(&lfs) => 0; @@ -355,5 +356,70 @@ tests/test.py << TEST lfs_unmount(&lfs) => 0; TEST +echo "--- Multi-block directory with files ---" +tests/test.py << TEST + lfs_mount(&lfs, &cfg) => 0; + lfs_mkdir(&lfs, "prickly-pear") => 0; + for (int i = 0; i < $LARGESIZE; i++) { + sprintf((char*)buffer, "prickly-pear/test%d", i); + lfs_file_open(&lfs, &file[0], (char*)buffer, + LFS_O_WRONLY | LFS_O_CREAT) => 0; + size = 6; + memcpy(wbuffer, "Hello", size); + lfs_file_write(&lfs, &file[0], wbuffer, size) => size; + lfs_file_close(&lfs, &file[0]) => 0; + } + lfs_unmount(&lfs) => 0; +TEST +tests/test.py << TEST + lfs_mount(&lfs, &cfg) => 0; + lfs_dir_open(&lfs, &dir[0], "prickly-pear") => 0; + lfs_dir_read(&lfs, &dir[0], &info) => 1; + strcmp(info.name, ".") => 0; + info.type => LFS_TYPE_DIR; + lfs_dir_read(&lfs, &dir[0], &info) => 1; + strcmp(info.name, "..") => 0; + info.type => LFS_TYPE_DIR; + for (int i = 0; i < $LARGESIZE; i++) { + sprintf((char*)buffer, "test%d", i); + lfs_dir_read(&lfs, &dir[0], &info) => 1; + strcmp(info.name, (char*)buffer) => 0; + info.type => LFS_TYPE_REG; + info.size => 6; + } + lfs_dir_read(&lfs, &dir[0], &info) => 0; + lfs_unmount(&lfs) => 0; +TEST + +echo "--- Multi-block remove with files ---" +tests/test.py << TEST + lfs_mount(&lfs, &cfg) => 0; + lfs_remove(&lfs, "prickly-pear") => LFS_ERR_NOTEMPTY; + + for (int i = 0; i < $LARGESIZE; i++) { + sprintf((char*)buffer, "prickly-pear/test%d", i); + lfs_remove(&lfs, (char*)buffer) => 0; + } + + lfs_remove(&lfs, "prickly-pear") => 0; + lfs_unmount(&lfs) => 0; +TEST +tests/test.py << TEST + lfs_mount(&lfs, &cfg) => 0; + lfs_dir_open(&lfs, &dir[0], "/") => 0; + lfs_dir_read(&lfs, &dir[0], &info) => 1; + strcmp(info.name, ".") => 0; + info.type => LFS_TYPE_DIR; + lfs_dir_read(&lfs, &dir[0], &info) => 1; + strcmp(info.name, "..") => 0; + info.type => LFS_TYPE_DIR; + lfs_dir_read(&lfs, &dir[0], &info) => 1; + strcmp(info.name, "burito") => 0; + info.type => LFS_TYPE_REG; + lfs_dir_read(&lfs, &dir[0], &info) => 0; + lfs_dir_close(&lfs, &dir[0]) => 0; + lfs_unmount(&lfs) => 0; +TEST + echo "--- Results ---" tests/stats.py diff --git a/features/filesystem/littlefs/littlefs/tests/test_files.sh b/features/filesystem/littlefs/littlefs/tests/test_files.sh index 444346371b..b2039a7b1e 100755 --- a/features/filesystem/littlefs/littlefs/tests/test_files.sh +++ b/features/filesystem/littlefs/littlefs/tests/test_files.sh @@ -135,5 +135,24 @@ tests/test.py << TEST lfs_unmount(&lfs) => 0; TEST +echo "--- Many file test ---" +tests/test.py << TEST + lfs_format(&lfs, &cfg) => 0; +TEST +tests/test.py << TEST + // Create 300 files of 6 bytes + lfs_mount(&lfs, &cfg) => 0; + lfs_mkdir(&lfs, "directory") => 0; + for (unsigned i = 0; i < 300; i++) { + snprintf((char*)buffer, sizeof(buffer), "file_%03d", i); + lfs_file_open(&lfs, &file[0], (char*)buffer, LFS_O_WRONLY | LFS_O_CREAT) => 0; + size = 6; + memcpy(wbuffer, "Hello", size); + lfs_file_write(&lfs, &file[0], wbuffer, size) => size; + lfs_file_close(&lfs, &file[0]) => 0; + } + lfs_unmount(&lfs) => 0; +TEST + echo "--- Results ---" tests/stats.py From 9d5908695b040046d9187fd2e2d95b966d222642 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mika=20Lepp=C3=A4nen?= Date: Mon, 12 Mar 2018 16:15:46 +0200 Subject: [PATCH 092/118] Corrected lwip adaptation TCP flagging --- features/FEATURE_LWIP/lwip-interface/lwip_stack.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c index f1e2c7b9cf..061a8706e1 100644 --- a/features/FEATURE_LWIP/lwip-interface/lwip_stack.c +++ b/features/FEATURE_LWIP/lwip-interface/lwip_stack.c @@ -1145,6 +1145,7 @@ static nsapi_error_t mbed_lwip_socket_bind(nsapi_stack_t *stack, nsapi_socket_t static nsapi_error_t mbed_lwip_socket_listen(nsapi_stack_t *stack, nsapi_socket_t handle, int backlog) { +#if LWIP_TCP struct lwip_socket *s = (struct lwip_socket *)handle; if (s->conn->pcb.tcp->local_port == 0) { @@ -1153,6 +1154,9 @@ static nsapi_error_t mbed_lwip_socket_listen(nsapi_stack_t *stack, nsapi_socket_ err_t err = netconn_listen_with_backlog(s->conn, backlog); return mbed_lwip_err_remap(err); +#else + return NSAPI_ERROR_UNSUPPORTED; +#endif } static nsapi_error_t mbed_lwip_socket_connect(nsapi_stack_t *stack, nsapi_socket_t handle, nsapi_addr_t addr, uint16_t port) @@ -1173,6 +1177,7 @@ static nsapi_error_t mbed_lwip_socket_connect(nsapi_stack_t *stack, nsapi_socket static nsapi_error_t mbed_lwip_socket_accept(nsapi_stack_t *stack, nsapi_socket_t server, nsapi_socket_t *handle, nsapi_addr_t *addr, uint16_t *port) { +#if LWIP_TCP struct lwip_socket *s = (struct lwip_socket *)server; struct lwip_socket *ns = mbed_lwip_arena_alloc(); if (!ns) { @@ -1199,6 +1204,9 @@ static nsapi_error_t mbed_lwip_socket_accept(nsapi_stack_t *stack, nsapi_socket_ netconn_set_nonblocking(ns->conn, true); return 0; +#else + return NSAPI_ERROR_UNSUPPORTED; +#endif } static nsapi_size_or_error_t mbed_lwip_socket_send(nsapi_stack_t *stack, nsapi_socket_t handle, const void *data, nsapi_size_t size) From c5650d847ac01afbc50166fe1ecabbb2f46ec273 Mon Sep 17 00:00:00 2001 From: bcostm Date: Mon, 12 Mar 2018 11:30:52 +0100 Subject: [PATCH 093/118] NUCLEO_L433RC_P: fix LEDs pin assignment --- .../TARGET_NUCLEO_L433RC_P/PinNames.h | 21 ++++++++----------- 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h index 8f74a691fc..c9656069e0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h @@ -111,7 +111,6 @@ typedef enum { PC_14 = 0x2E, PC_15 = 0x2F, - PD_2 = 0x32, #ifdef STM32L433_100PINS // LQFP100 or UFBGA100 versions PD_0 = 0x30, @@ -165,10 +164,6 @@ typedef enum { A3 = PC_2, A4 = PC_1, A5 = PC_0, - - A6 = PA_7, - A7 = PA_2, - D0 = PA_2, D1 = PA_3, D2 = PA_12, @@ -183,8 +178,10 @@ typedef enum { D11 = PB_15, D12 = PB_14, D13 = PB_13, + D14 = PB_7, + D15 = PB_8, - // STDIO for console print + // STDIO for console print #ifdef MBED_CONF_TARGET_STDIO_UART_TX STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, #else @@ -197,12 +194,12 @@ typedef enum { #endif // Generic signals namings - LED1 = PA_5, - LED2 = PA_5, - LED3 = PA_5, - LED4 = PA_5, + LED1 = PB_13, + LED2 = PB_13, + LED3 = PB_13, + LED4 = PB_13, USER_BUTTON = PC_13, - BUTTON1 = USER_BUTTON, + BUTTON1 = USER_BUTTON, SERIAL_TX = STDIO_UART_TX, SERIAL_RX = STDIO_UART_RX, USBTX = STDIO_UART_TX, @@ -215,7 +212,7 @@ typedef enum { SPI_CS = D10, PWM_OUT = D9, - //USB pins + // USB pins USB_DM = PA_11, USB_DP = PA_12, USB_NOE = PA_13, From 5db8a42e0b2de8aebd1ad477134fab3c3f67f1bf Mon Sep 17 00:00:00 2001 From: mbedNoobNinja Date: Thu, 1 Mar 2018 16:06:18 +0200 Subject: [PATCH 094/118] Enabled os5 support for VK_RZ_A1H & synced with rest Renesas targets ! Mbed-os 5.4.7 was the last unofficial working support for this target. Since Mbed-os 5.6.0, the support is now official and VK_RZ_A1H is now "codebase aligned" with GR_PEACH (RZ_A1H) & GR_LYCHEE (RZ_A1LU) ! --- .../TARGET_MBED_VKRZA1H/reserved_pins.h | 16 + .../TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h | 15 +- .../TARGET_VK_RZ_A1H/device/RZ_A1_Init.c | 2 + .../device/TOOLCHAIN_ARM_STD/VKRZA1H.sct | 64 +- .../device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h | 95 + .../TOOLCHAIN_ARM_STD/startup_VKRZA1H.S | 454 - .../TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c | 162 + .../device/TOOLCHAIN_ARM_STD/sys.cpp | 61 + .../device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld | 78 +- .../TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S | 326 +- .../device/TOOLCHAIN_IAR/VKRZA1H.icf | 5 +- .../device/TOOLCHAIN_IAR/startup_VKRZA1H.S | 339 +- .../TARGET_VK_RZ_A1H/device/VKRZA1H.h | 1076 +- .../TARGET_VK_RZ_A1H/device/cmsis.h | 1 + .../TARGET_VK_RZ_A1H/device/cmsis_nvic.c | 11 +- .../TARGET_VK_RZ_A1H/device/gic.c | 305 - .../TARGET_VK_RZ_A1H/device/gic.h | 316 - .../TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h | 922 + .../TARGET_VK_RZ_A1H/device/inc/iodefine.h | 151 +- .../device/inc/iodefines/adc_iodefine.h | 79 +- .../device/inc/iodefines/bsc_iodefine.h | 88 +- .../device/inc/iodefines/ceu_iodefine.h | 198 +- .../device/inc/iodefines/cpg_iodefine.h | 252 +- .../device/inc/iodefines/disc_iodefine.h | 107 +- .../device/inc/iodefines/dmac_iodefine.h | 1384 +- .../device/inc/iodefines/dvdec_iodefine.h | 532 +- .../device/inc/iodefines/ether_iodefine.h | 424 +- .../device/inc/iodefines/flctl_iodefine.h | 52 +- .../device/inc/iodefines/gpio_iodefine.h | 2011 +- .../device/inc/iodefines/ieb_iodefine.h | 77 +- .../device/inc/iodefines/inb_iodefine.h | 92 +- .../device/inc/iodefines/intc_iodefine.h | 1022 +- .../device/inc/iodefines/iodefine_typedef.h | 118 + .../device/inc/iodefines/irda_iodefine.h | 29 +- .../device/inc/iodefines/jcu_iodefine.h | 162 +- .../device/inc/iodefines/l2c_iodefine.h | 188 +- .../device/inc/iodefines/lin_iodefine.h | 205 +- .../device/inc/iodefines/lvds_iodefine.h | 35 +- .../device/inc/iodefines/mlb_iodefine.h | 913 +- .../device/inc/iodefines/mmc_iodefine.h | 74 +- .../device/inc/iodefines/mtu2_iodefine.h | 183 +- .../device/inc/iodefines/ostm_iodefine.h | 83 +- .../device/inc/iodefines/pfv_iodefine.h | 188 +- .../device/inc/iodefines/pwm_iodefine.h | 176 +- .../device/inc/iodefines/riic_iodefine.h | 1050 +- .../device/inc/iodefines/romdec_iodefine.h | 168 +- .../device/inc/iodefines/rscan0_iodefine.h | 17794 ++++++++-------- .../device/inc/iodefines/rspi_iodefine.h | 312 +- .../device/inc/iodefines/rtc_iodefine.h | 67 +- .../device/inc/iodefines/scif_iodefine.h | 254 +- .../device/inc/iodefines/scim_iodefine.h | 99 +- .../device/inc/iodefines/scux_iodefine.h | 829 +- .../device/inc/iodefines/sdg_iodefine.h | 103 +- .../device/inc/iodefines/spdif_iodefine.h | 55 +- .../device/inc/iodefines/spibsc_iodefine.h | 252 +- .../device/inc/iodefines/ssif_iodefine.h | 187 +- .../device/inc/iodefines/usb20_iodefine.h | 770 +- .../device/inc/iodefines/vdc5_iodefine.h | 2172 +- .../device/inc/iodefines/wdt_iodefine.h | 37 +- .../device/mmu_Renesas_RZ_A1.c | 243 - .../TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c | 281 + .../TARGET_VK_RZ_A1H/device/nvic_wrapper.c | 9 +- .../TARGET_VK_RZ_A1H/device/os_tick_ostm.c | 201 + .../TARGET_VK_RZ_A1H/device/pl310.c | 128 - .../TARGET_VK_RZ_A1H/device/pl310.h | 114 - .../TARGET_VK_RZ_A1H/device/system_VKRZA1H.c | 521 - .../TARGET_VK_RZ_A1H/device/system_VKRZA1H.h | 67 - .../device/system_VK_RZ_A1H.c | 157 + .../device/system_VK_RZ_A1H.h | 81 + targets/TARGET_RENESAS/mbed_rtx.h | 2 +- targets/targets.json | 4 +- 71 files changed, 19583 insertions(+), 19445 deletions(-) create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h index 10d094ce32..201e6fb008 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h @@ -1,3 +1,19 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + #ifndef RESERVED_PINS_H #define RESERVED_PINS_H diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h index 76739b32c4..20024dad86 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h @@ -26,23 +26,12 @@ #endif /* <-Take measures about optimization problems of web compiler */ - - - - - - - - - +#define TRANSACTION_QUEUE_SIZE_SPI 16 #define DEVICE_ID_LENGTH 32 #define DEVICE_MAC_OFFSET 20 - - - - #include "objects.h" +#include "dma_api.h" #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c index 69364aaee7..ff7b5d66e2 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c @@ -47,7 +47,9 @@ Macro definitions #define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu) +#if (defined(TARGET_DEBUG) || !defined(RUN_FROM_SDRAM)) #define CS2_SDRAM +#endif /****************************************************************************** Imported global variables and functions (from other files) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct index 71b59832d6..fafb1bae33 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct @@ -1,42 +1,62 @@ +#! armcc -E -I"../" +;************************************************** +; Copyright (c) 2017 ARM Ltd. All rights reserved. +;************************************************** +; Scatter-file for RTX Example on Versatile Express -LOAD_TTB 0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +#include "mbed_config.h" +#include "mem_VK_RZ_A1H.h" + +LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM { TTB +0 EMPTY 0x4000 { } ; Level-1 Translation Table for MMU } -SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region +SFLASH __ROM_BASE __ROM_SIZE ; load region size_region { -} + VECTORS __VECTOR_BASE FIXED + { + * (RESET, +FIRST) ; Vector table and other startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + } -SFLASH_DUAL 0x18020000 (32*1024*1024-2*64*1024) -{ - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; S-Flash ROM : Executable cached region - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) - VECTORS 0x18020000 FIXED - { - * (RESET, +FIRST) ; Vector table and other (assembler) startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - } + RW_DATA __DATA_BASE + { * (+RW) } ; Application RW data (.data) - RO_DATA +0 - { * (+RO-DATA) } ; Application RO data (.constdata) + RW_IRAM1 +0 ALIGN 0x10 + { * (+ZI) } ; Application ZI data (.bss) - RW_DATA 0x20020000 - { * (+RW) } ; Application RW data (.data) + ARM_LIB_HEAP +0 + { * (HEAP) } ; Application heap area (HEAP) - ZI_DATA +0 ALIGN 0x400 - { * (+ZI) } ; Application ZI data (.bss) + ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down + { } - RW_DATA_NC 0x60900000 0x00100000 + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; RAM-NC : Internal non-cached RAM region + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE { * (NC_DATA) } ; Application RW data Non cached area ZI_DATA_NC +0 { * (NC_BSS) } ; Application ZI data Non cached area } - +#ifndef RUN_FROM_SDRAM +SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region +{ +} +#else +SRAM 0x200A0000 0x00960000 ; 9.5MB Internal SRAM region (0.5MB SDCARD Bootloader !!!) +{ +} +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h new file mode 100644 index 0000000000..63feb75a7a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h @@ -0,0 +1,95 @@ +/**************************************************************************//** + * @file mem_VK_RZ_A1H.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_VK_RZ_A1H_H +#define __MEM_VK_RZ_A1H_H + +/*---------------------------------------------------------------------------- + User Stack & Heap size definition + *----------------------------------------------------------------------------*/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- ROM Configuration ------------------------------------ +// +// ROM Configuration +// ROM Base Address <0x0-0xFFFFFFFF:8> +// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#ifdef RUN_FROM_SDRAM + #define __ROM_BASE 0x08000000 + #define __ROM_SIZE 0x02000000 + #define __VECTOR_BASE 0x08000000 + #define __DATA_BASE +0 ALIGN 0x100000 +#elif defined (RUN_FROM_SRAM) + #define __ROM_BASE 0x200A0000 + #define __ROM_SIZE 0x00960000 + #define __VECTOR_BASE 0x200A0000 + #define __DATA_BASE +0 ALIGN 0x100000 NOCOMPRESS +#else + #define __ROM_BASE 0x18020000 + #define __ROM_SIZE 0x01FE0000 + #define __VECTOR_BASE 0x18020000 + #define __DATA_BASE 0x20020000 +#endif + +/*--------------------- RAM Configuration ----------------------------------- + *----------------------------------------------------------------------------*/ +#ifdef RUN_FROM_SDRAM +#define __RAM_BASE 0x08000000 +#define __RAM_SIZE 0x02000000 +#define __NC_RAM_SIZE 0x00200000 +#else +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00A00000 +#define __NC_RAM_SIZE 0x00100000 +#endif +#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE) +#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000) + +#define __UND_STACK_SIZE 0x00000100 +#define __SVC_STACK_SIZE 0x00008000 +#define __ABT_STACK_SIZE 0x00000100 +#define __FIQ_STACK_SIZE 0x00000100 +#define __IRQ_STACK_SIZE 0x0000F000 +#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE) + +/*----------------------------------------------------------------------------*/ + +/*--------------------- TTB Configuration ------------------------------------ +// +// TTB Configuration +// TTB Base Address <0x0-0xFFFFFFFF:8> +// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __TTB_BASE 0x20000000 +#define __TTB_SIZE 0x00004000 + +#endif /* __MEM_VK_RZ_A1H_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S deleted file mode 100644 index 3f4776384e..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S +++ /dev/null @@ -1,454 +0,0 @@ -;/***************************************************************************** -; * @file: startup_VKRZA1H.s -; * @purpose: CMSIS Cortex-A9 Core Device Startup File -; * for the Renesas RZA1H Device Series -; * @version: V1.02, modified for mbed -; * @date: 27. July 2009, modified 3rd Aug 2009 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2009 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - -GICI_BASE EQU 0xe8202000 -ICCIAR_OFFSET EQU 0x0000000C -ICCEOIR_OFFSET EQU 0x00000010 -ICCHPIR_OFFSET EQU 0x00000018 - -GICD_BASE EQU 0xe8201000 -ICDISER0_OFFSET EQU 0x00000100 -ICDICER0_OFFSET EQU 0x00000180 -ICDISPR0_OFFSET EQU 0x00000200 -ICDABR0_OFFSET EQU 0x00000300 -ICDIPR0_OFFSET EQU 0x00000400 - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled -T_Bit EQU 0x20 ; when T bit is set, core is in Thumb state - -GIC_ERRATA_CHECK_1 EQU 0x000003FE -GIC_ERRATA_CHECK_2 EQU 0x000003FF - - -Sect_Normal EQU 0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -Sect_Normal_Cod EQU 0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -Sect_Normal_RO EQU 0x0000dc16 ;as Sect_Normal_Cod, but not executable -Sect_Normal_RW EQU 0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable -Sect_SO EQU 0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 -Sect_Device_RO EQU 0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0 -Sect_Device_RW EQU 0x00000c12 ;as Sect_Device_RO, but writeable -Sect_Fault EQU 0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored) - -RAM_BASE EQU 0x80000000 -VRAM_BASE EQU 0x18000000 -SRAM_BASE EQU 0x2e000000 -ETHERNET EQU 0x1a000000 -CS3_PERIPHERAL_BASE EQU 0x1c000000 - -; Stack Configuration -; Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8> -; - -UND_Stack_Size EQU 0x00000100 -SVC_Stack_Size EQU 0x00008000 -ABT_Stack_Size EQU 0x00000100 -FIQ_Stack_Size EQU 0x00000100 -IRQ_Stack_Size EQU 0x00008000 -USR_Stack_Size EQU 0x00004000 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size - -Stack_Top - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00080000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - ARM - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, CODE, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors LDR PC, Reset_Addr ; Address of Reset Handler - LDR PC, Undef_Addr ; Address of Undef Handler - LDR PC, SVC_Addr ; Address of SVC Handler - LDR PC, PAbt_Addr ; Address of Prefetch Abort Handler - LDR PC, DAbt_Addr ; Address of Data Abort Handler - NOP ; Reserved Vector - LDR PC, IRQ_Addr ; Address of IRQ Handler - LDR PC, FIQ_Addr ; Address of FIQ Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SVC_Addr DCD SVC_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - - AREA |.text|, CODE, READONLY - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT InitMemorySubsystem - IMPORT __main - IMPORT RZ_A1_SetSramWriteEnable - - ; Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - -; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -; Enables Full Access i.e. in both privileged and non privileged modes - MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR) - ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11 - MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR) - ISB - -; Switch on the VFP and NEON hardware - MOV r0, #0x40000000 - VMSR FPEXC, r0 ; Write FPEXC register, EN bit set - - MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register - ISB - -; Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =__Vectors - MCR p15, 0, R0, c12, c0, 0 - -; Setup Stack for each exceptional mode - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - -; Enter System Mode to complete initialization and enter kernel - MSR CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit - MOV SP, R0 - - ISB - - LDR R0, =RZ_A1_SetSramWriteEnable - BLX R0 - - IMPORT create_translation_table - BL create_translation_table - -; USR/SYS stack pointer will be set during kernel init - - LDR R0, =SystemInit - BLX R0 - LDR R0, =InitMemorySubsystem - BLX R0 - LDR R0, =__main - BLX R0 - - ENDP - -Undef_Handler\ - PROC - EXPORT Undef_Handler [WEAK] - IMPORT CUndefHandler - SRSFD SP!, #Mode_UND - PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack - - MRS R0, SPSR - TST R0, #T_Bit ; Check mode - MOVEQ R1, #4 ; R1 = 4 ARM mode - MOVNE R1, #2 ; R1 = 2 Thumb mode - SUB R0, LR, R1 - LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction - BEQ undef_cont - - ;Thumb instruction - ;Determine if it is a 32-bit Thumb instruction - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont ;16-bit Thumb instruction - - ;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont - MOV R2, LR ; Set LR to third argument - -; AND R12, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R12, R3, #4 - SUB SP, SP, R12 ; Adjust stack - PUSH {R12, LR} ; Store stack adjustment and dummy LR - - ;R0 Offending instruction - ;R1 =2 (Thumb) or =4 (ARM) - BL CUndefHandler - - POP {R12, LR} ; Get stack adjustment & discard dummy LR - ADD SP, SP, R12 ; Unadjust stack - - LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry - SUB LR, LR, R0 - LDR R0, [SP, #28] ; Restore stacked SPSR - MSR SPSR_CXSF, R0 - POP {R0-R4, R12} ; Restore stacked APCS registers - ADD SP, SP, #8 ; Adjust SP for already-restored banked registers - MOVS PC, LR - ENDP - -PAbt_Handler\ - PROC - EXPORT PAbt_Handler [WEAK] - IMPORT CPAbtHandler - SUB LR, LR, #4 ; Pre-adjust LR - SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack - PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack - MRC p15, 0, R0, c5, c0, 1 ; IFSR - MRC p15, 0, R1, c6, c0, 2 ; IFAR - - MOV R2, LR ; Set LR to third argument - -; AND R12, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R12, R3, #4 - SUB SP, SP, R12 ; Adjust stack - PUSH {R12, LR} ; Store stack adjustment and dummy LR - - BL CPAbtHandler - - POP {R12, LR} ; Get stack adjustment & discard dummy LR - ADD SP, SP, R12 ; Unadjust stack - - POP {R0-R4, R12} ; Restore stack APCS registers - RFEFD SP! ; Return from exception - ENDP - - -DAbt_Handler\ - PROC - EXPORT DAbt_Handler [WEAK] - IMPORT CDAbtHandler - SUB LR, LR, #8 ; Pre-adjust LR - SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack - PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack - CLREX ; State of exclusive monitors unknown after taken data abort - MRC p15, 0, R0, c5, c0, 0 ; DFSR - MRC p15, 0, R1, c6, c0, 0 ; DFAR - - MOV R2, LR ; Set LR to third argument - -; AND R12, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R12, R3, #4 - SUB SP, SP, R12 ; Adjust stack - PUSH {R12, LR} ; Store stack adjustment and dummy LR - - BL CDAbtHandler - - POP {R12, LR} ; Get stack adjustment & discard dummy LR - ADD SP, SP, R12 ; Unadjust stack - - POP {R0-R4, R12} ; Restore stacked APCS registers - RFEFD SP! ; Return from exception - ENDP - -FIQ_Handler\ - PROC - EXPORT FIQ_Handler [WEAK] - ;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - ;; so if a real FIQ Handler is implemented, this will be needed before returning: - ;; LDR R1, =GICI_BASE - ;; LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - B . - ENDP - -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -IRQ_Handler\ - PROC - EXPORT IRQ_Handler [WEAK] - IMPORT IRQCount - IMPORT IRQTable - IMPORT IRQNestLevel - - ;prologue - SUB LR, LR, #4 ; Pre-adjust LR - SRSFD SP!, #Mode_SVC ; Save LR_IRQ and SPRS_IRQ to SVC mode stack - CPS #Mode_SVC ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL - PUSH {R0-R3, R12} ; Save remaining APCS corruptible registers to SVC stack - -; AND R1, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R1, R3, #4 - SUB SP, SP, R1 ; Adjust stack - PUSH {R1, LR} ; Store stack adjustment and LR_SVC to SVC stack - - LDR R0, =IRQNestLevel ; Get address of nesting counter - LDR R1, [R0] - ADD R1, R1, #1 ; Increment nesting counter - STR R1, [R0] - - ;identify and acknowledge interrupt - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - LDR R0, [R1, #ICCIAR_OFFSET] ; Read ICCIAR (GIC CPU Interface register) - DSB ; Ensure that interrupt acknowledge completes before re-enabling interrupts - - ; Workaround GIC 390 errata 733075 - ; If the ID is not 0, then service the interrupt as normal. - ; If the ID is 0 and active, then service interrupt ID 0 as normal. - ; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - ; with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - ; - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active ; If the ID is not 0, then service the interrupt - LDR R3, [R2, #ICDABR0_OFFSET] ; Get the interrupt state - TST R3, #1 - BNE int_active ; If active, then service the interrupt -unlock_cpu - LDR R3, [R2, #ICDIPR0_OFFSET] ; Not active, so unlock the CPU interface - STR R3, [R2, #ICDIPR0_OFFSET] ; with a dummy write - DSB ; Ensure the write completes before continuing - B ret_irq ; Do not service the spurious interrupt - ; End workaround - -int_active - LDR R2, =IRQCount ; Read number of IRQs - LDR R2, [R2] - CMP R0, R2 ; Clean up and return if no handler - BHS ret_irq ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling - LDR R2, =IRQTable ; Get address of handler - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 ; Clean up and return if handler address is 0 - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i ; Now safe to re-enable interrupts - BLX R2 ; Call handler. R0 will be IRQ number - CPSID i ; Disable interrupts again - - ;write EOIR (GIC CPU Interface register) - POP {R0,R1} - DSB ; Ensure that interrupt source is cleared before we write the EOIR -ret_irq - ;epilogue - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel ; Get address of nesting counter - LDR R1, [R0] - SUB R1, R1, #1 ; Decrement nesting counter - STR R1, [R0] - - POP {R1, LR} ; Get stack adjustment and restore LR_SVC - ADD SP, SP, R1 ; Unadjust stack - - POP {R0-R3,R12} ; Restore stacked APCS registers - RFEFD SP! ; Return from exception - ENDP - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ENDIF - - - END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c new file mode 100644 index 0000000000..a83d7a235e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c @@ -0,0 +1,162 @@ +/****************************************************************************** + * @file startup_RZ_A1H_H.c + * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "VKRZA1H.h" +#include "mem_VK_RZ_A1H.h" + +/*---------------------------------------------------------------------------- + Definitions + *----------------------------------------------------------------------------*/ +#define USR_MODE 0x10 // User mode +#define FIQ_MODE 0x11 // Fast Interrupt Request mode +#define IRQ_MODE 0x12 // Interrupt Request mode +#define SVC_MODE 0x13 // Supervisor mode +#define ABT_MODE 0x17 // Abort mode +#define UND_MODE 0x1B // Undefined Instruction mode +#define SYS_MODE 0x1F // System mode + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Vectors (void) __attribute__ ((section("RESET"))); +void Reset_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector Table + *----------------------------------------------------------------------------*/ +__ASM void Vectors(void) { + IMPORT Undef_Handler + IMPORT SVC_Handler + IMPORT PAbt_Handler + IMPORT DAbt_Handler + IMPORT IRQ_Handler + IMPORT FIQ_Handler + LDR PC, =Reset_Handler + LDR PC, =Undef_Handler + LDR PC, =SVC_Handler + LDR PC, =PAbt_Handler + LDR PC, =DAbt_Handler + NOP + LDR PC, =IRQ_Handler + LDR PC, =FIQ_Handler +} + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__ASM void Reset_Handler(void) { + + // Mask interrupts + CPSID if + + // Put any cores other than 0 to sleep + MRC p15, 0, R0, c0, c0, 5 // Read MPIDR + ANDS R0, R0, #3 +goToSleep + WFINE + BNE goToSleep + + // Reset SCTLR Settings + MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register + BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU + BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction + BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs + MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register + ISB + + // Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register + + // Set Vector Base Address Register (VBAR) to point to this application's vector table + LDR R0, =Vectors + MCR p15, 0, R0, c12, c0, 0 + + // Setup Stack for each exceptional mode + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| + + //Enter Undefined Instruction Mode and set its Stack Pointer + CPS #UND_MODE + MOV SP, R0 + SUB R0, R0, #__UND_STACK_SIZE + + // Enter Abort Mode and set its Stack Pointer + CPS #ABT_MODE + MOV SP, R0 + SUB R0, R0, #__ABT_STACK_SIZE + + // Enter FIQ Mode and set its Stack Pointer + CPS #FIQ_MODE + MOV SP, R0 + SUB R0, R0, #__FIQ_STACK_SIZE + + // Enter IRQ Mode and set its Stack Pointer + CPS #IRQ_MODE + MOV SP, R0 + SUB R0, R0, #__IRQ_STACK_SIZE + + // Enter Supervisor Mode and set its Stack Pointer + CPS #SVC_MODE + MOV SP, R0 + SUB R0, R0, #__SVC_STACK_SIZE + + // Enter System Mode to complete initialization and enter kernel + CPS #SYS_MODE + MOV SP, R0 + + // Call SystemInit + IMPORT SystemInit + BL SystemInit + + // Unmask interrupts + CPSIE if + + // Call __main + IMPORT __main + BL __main +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + while(1); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..dfa0bc6f1f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2017 ARM Limited. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#include +#endif + +#include +#include + +extern char Image$$ARM_LIB_HEAP$$Base[]; +extern char Image$$ARM_LIB_STACK$$Base[]; + +extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$ARM_LIB_HEAP$$Base; + uint32_t sp_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base; + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld index 12afcc6c7a..b2a7fa5caa 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld @@ -1,15 +1,40 @@ /* Linker script for mbed VK_RZ_A1H */ /* Linker script to configure memory regions. */ +/* +#ifdef RUN_FROM_SDRAM +MEMORY +{ + L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 + RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x01E00000 + RAM_NC (rwx) : ORIGIN = 0x49E00000, LENGTH = 0x00200000 + SRAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00960000 +} +REGION_ALIAS("SFLASH", RAM); +TTBOFFSET = 1M; + +#elif defined (RUN_FROM_SRAM) +MEMORY +{ + L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 + RAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00860000 + RAM_NC (rwx) : ORIGIN = 0x60900000, LENGTH = 0x00100000 + SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000 +} +REGION_ALIAS("SFLASH", RAM); +TTBOFFSET = 1M; +#else +*/ MEMORY { ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000000 - SFLASH_DUAL (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000 + SFLASH (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000 L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 - RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000 + RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x008E0000 RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000 SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000 } +/*#endif*/ /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. @@ -45,8 +70,7 @@ SECTIONS { Image$$VECTORS$$Base = .; - *(.isr_vector) - Image$$VECTORS$$Limit = .; + KEEP(*(.isr_vector)) *(SVC_TABLE) *(.text*) @@ -66,24 +90,25 @@ SECTIONS *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) + Image$$VECTORS$$Limit = .; Image$$RO_DATA$$Base = .; *(.rodata*) Image$$RO_DATA$$Limit = .; KEEP(*(.eh_frame*)) - } > SFLASH_DUAL + } > SFLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } > SFLASH_DUAL + } > SFLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > SFLASH_DUAL + } > SFLASH __exidx_end = .; @@ -98,7 +123,7 @@ SECTIONS LONG (__nc_data_start) LONG (__nc_data_end - __nc_data_start) __copy_table_end__ = .; - } > SFLASH_DUAL + } > SFLASH .zero.table : { @@ -109,7 +134,7 @@ SECTIONS LONG (__nc_bss_start) LONG (__nc_bss_end - __nc_bss_start) __zero_table_end__ = .; - } > SFLASH_DUAL + } > SFLASH __etext = .; @@ -155,34 +180,42 @@ SECTIONS } > RAM - - .bss ALIGN(0x400): + .bss ALIGN(0x10): { - Image$$ZI_DATA$$Base = .; + Image$$RW_IRAM1$$Base = .; __bss_start__ = .; *(.bss*) *(COMMON) __bss_end__ = .; - Image$$ZI_DATA$$Limit = .; + Image$$RW_IRAM1$$Limit = .; } > RAM - .heap : { __end__ = .; end = __end__; *(.heap*) - __HeapLimit = .; } > RAM /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ - .stack_dummy : + .stack_dummy (COPY): { - *(.stack) + *(.stack*) } > RAM + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + __HeapLimit = __StackLimit; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + __etext2 = __etext + SIZEOF(.data); .nc_data : AT (__etext2) { @@ -205,15 +238,4 @@ SECTIONS __nc_bss_end = .; Image$$ZI_DATA_NC$$Limit = .; } > RAM_NC - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S index c74cccba81..0506dd8c68 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S @@ -19,26 +19,6 @@ .extern _start @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs - .equ USR_MODE , 0x10 - .equ FIQ_MODE , 0x11 - .equ IRQ_MODE , 0x12 - .equ SVC_MODE , 0x13 - .equ ABT_MODE , 0x17 - .equ UND_MODE , 0x1b - .equ SYS_MODE , 0x1f - .equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit - - .equ GICI_BASE , 0xe8202000 - .equ ICCIAR_OFFSET , 0x0000000C - .equ ICCEOIR_OFFSET , 0x00000010 - .equ ICCHPIR_OFFSET , 0x00000018 - .equ GICD_BASE , 0xe8201000 - .equ ICDISER0_OFFSET , 0x00000100 - .equ ICDICER0_OFFSET , 0x00000180 - .equ ICDISPR0_OFFSET , 0x00000200 - .equ ICDABR0_OFFSET , 0x00000300 - .equ ICDIPR0_OFFSET , 0x00000400 - .equ Mode_USR , 0x10 .equ Mode_FIQ , 0x11 .equ Mode_IRQ , 0x12 @@ -51,33 +31,13 @@ .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state - .equ GIC_ERRATA_CHECK_1, 0x000003FE - .equ GIC_ERRATA_CHECK_2, 0x000003FF - - .equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 - .equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 - .equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable - .equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable - .equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 - .equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0 - .equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable - .equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored) - - .equ RAM_BASE , 0x80000000 - .equ VRAM_BASE , 0x18000000 - .equ SRAM_BASE , 0x2e000000 - .equ ETHERNET , 0x1a000000 - .equ CS3_PERIPHERAL_BASE, 0x1c000000 - - @ Stack Configuration .EQU UND_Stack_Size , 0x00000100 .EQU SVC_Stack_Size , 0x00008000 .EQU ABT_Stack_Size , 0x00000100 .EQU FIQ_Stack_Size , 0x00000100 - .EQU IRQ_Stack_Size , 0x00008000 - .EQU USR_Stack_Size , 0x00004000 + .EQU IRQ_Stack_Size , 0x0000F000 .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) @@ -88,7 +48,6 @@ __StackLimit: .space ISR_Stack_Size __initial_sp: - .space USR_Stack_Size .size __StackLimit, . - __StackLimit __StackTop: .size __StackTop, . - __StackTop @@ -139,25 +98,17 @@ __isr_vector: .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: + @ Mask interrupts + CPSID if + @ Put any cores other than 0 to sleep mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR ands r0, r0, #3 - goToSleep: wfine bne goToSleep -@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -@ Enables Full Access i.e. in both privileged and non privileged modes - mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR) - orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11 - mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR) - isb - -@ Switch on the VFP and NEON hardware - mov r0, #0x40000000 - vmsr fpexc, r0 @ Write FPEXC register, EN bit set - + @ Reset SCTLR Settings mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache @@ -167,13 +118,17 @@ goToSleep: mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register isb + @ Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register + @ Set Vector Base Address Register (VBAR) to point to this application's vector table ldr r0, =__isr_vector mcr p15, 0, r0, c12, c0, 0 @ Setup Stack for each exceptional mode -/* ldr r0, =__StackTop */ - ldr r0, =(__StackTop - USR_Stack_Size) + ldr r0, =__StackTop @ Enter Undefined Instruction Mode and set its Stack Pointer msr cpsr_c, #(Mode_UND | I_Bit | F_Bit) @@ -203,23 +158,12 @@ goToSleep: msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit) mov sp, r0 - isb - ldr r0, =RZ_A1_SetSramWriteEnable - blx r0 - - .extern create_translation_table - bl create_translation_table - @ USR/SYS stack pointer will be set during kernel init ldr r0, =SystemInit blx r0 - ldr r0, =InitMemorySubsystem - blx r0 - -@ fp_init - mov r0, #0x3000000 - vmsr fpscr, r0 + @ Unmask interrupts + CPSIE if @ data sections copy ldr r4, =__copy_table_start__ @@ -269,227 +213,12 @@ goToSleep: ldr r0, =_start bx r0 - ldr r0, sf_boot @ dummy to keep boot loader area -loop_here: - b loop_here - -sf_boot: - .word 0x18020000 - .pool .size Reset_Handler, . - Reset_Handler .text -Undef_Handler: - .global Undef_Handler - .func Undef_Handler - .extern CUndefHandler - SRSDB SP!, #Mode_UND - PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ - - MRS R0, SPSR - TST R0, #T_Bit /* Check mode */ - MOVEQ R1, #4 /* R1 = 4 ARM mode */ - MOVNE R1, #2 /* R1 = 2 Thumb mode */ - SUB R0, LR, R1 - LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ - BEQ undef_cont - - /* Thumb instruction */ - /* Determine if it is a 32-bit Thumb instruction */ - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont /* 16-bit Thumb instruction */ - - /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont: - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - /* R0 Offending instruction */ - /* R1 =2 (Thumb) or =4 (ARM) */ - BL CUndefHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ - SUB LR, LR, R0 - LDR R0, [SP, #28] /* Restore stacked SPSR */ - MSR SPSR_cxsf, R0 - POP {R0-R4, R12} /* Restore stacked APCS registers */ - ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ - MOVS PC, LR - .endfunc - -PAbt_Handler: - .global PAbt_Handler - .func PAbt_Handler - .extern CPAbtHandler - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - MRC p15, 0, R0, c5, c0, 1 /* IFSR */ - MRC p15, 0, R1, c6, c0, 2 /* IFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CPAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stack APCS registers */ - RFEFD SP! /* Return from exception */ - .endfunc - -DAbt_Handler: - .global DAbt_Handler - .func DAbt_Handler - .extern CDAbtHandler - SUB LR, LR, #8 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - CLREX /* State of exclusive monitors unknown after taken data abort */ - MRC p15, 0, R0, c5, c0, 0 /* DFSR */ - MRC p15, 0, R1, c6, c0, 0 /* DFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CDAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ - .endfunc - -FIQ_Handler: - .global FIQ_Handler - .func FIQ_Handler - /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - * so if a real FIQ Handler is implemented, this will be needed before returning: - */ - /* LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - */ - B . - .endfunc - - .extern SVC_Handler /* refer RTX function */ - -IRQ_Handler: - .global IRQ_Handler - .func IRQ_Handler - .extern IRQCount - .extern IRQTable - .extern IRQNestLevel - - /* prologue */ - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ - CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ - PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ - -/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R1, R3, #4 - SUB SP, SP, R1 /* Adjust stack */ - PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - ADD R1, R1, #1 /* Increment nesting counter */ - STR R1, [R0] - - /* identify and acknowledge interrupt */ - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ - LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ - DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ - - /* Workaround GIC 390 errata 733075 - * If the ID is not 0, then service the interrupt as normal. - * If the ID is 0 and active, then service interrupt ID 0 as normal. - * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - */ - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active /* If the ID is not 0, then service the interrupt */ - LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ - TST R3, #1 - BNE int_active /* If active, then service the interrupt */ -unlock_cpu: - LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ - STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ - DSB /* Ensure the write completes before continuing */ - B ret_irq /* Do not service the spurious interrupt */ - /* End workaround */ - -int_active: - LDR R2, =IRQCount /* Read number of IRQs */ - LDR R2, [R2] - CMP R0, R2 /* Clean up and return if no handler */ - BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ - LDR R2, =IRQTable /* Get address of handler */ - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 /* Clean up and return if handler address is 0 */ - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i /* Now safe to re-enable interrupts */ - BLX R2 /* Call handler. R0 will be IRQ number */ - CPSID i /* Disable interrupts again */ - - /* write EOIR (GIC CPU Interface register) */ - POP {R0,R1} - DSB /* Ensure that interrupt source is cleared before we write the EOIR */ -ret_irq: - /* epilogue */ - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - SUB R1, R1, #1 /* Decrement nesting counter */ - STR R1, [R0] - - POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ - ADD SP, SP, R1 /* Unadjust stack */ - - POP {R0-R3,R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ - .endfunc - /* Macro to define default handlers. Default handler * will be weak symbol and just dead loops. They can be * overwritten by other handlers */ @@ -503,30 +232,11 @@ ret_irq: .size \handler_name, . - \handler_name .endm + def_default_handler Undef_Handler def_default_handler SVC_Handler - - -/* User Initial Stack & Heap */ - - .ifdef __MICROLIB - - .global __initial_sp - .global __heap_base - .global __heap_limit - - .else - - .extern __use_two_region_memory - .global __user_initial_stackheap -__user_initial_stackheap: - - LDR R0, = __HeapBase - LDR R1, =(__StackTop) - LDR R2, = (__HeapBase + Heap_Size) - LDR R3, = (__StackTop - USR_Stack_Size) - BX LR - - .endif - + def_default_handler PAbt_Handler + def_default_handler DAbt_Handler + def_default_handler IRQ_Handler + def_default_handler FIQ_Handler .END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf index 30addf8e44..d00e9df287 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf @@ -41,6 +41,7 @@ define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__]; define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__]; +define block ROM_FIXED_ORDER with fixed order { ro code, ro data }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; @@ -51,11 +52,11 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; -do not initialize { section MMU_TT }; +do not initialize { section .retram }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; +place in ROM_region { readonly, block ROM_FIXED_ORDER }; place in RAM_region { readwrite, block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, block UND_STACK, block ABT_STACK, block HEAP }; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S index 94f605c124..521dc5f116 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S @@ -29,30 +29,21 @@ SECTION .intvec:CODE:NOROOT(2) - PUBLIC __vector_core_a9 - PUBWEAK __iar_program_start - PUBLIC Undefined_Handler - EXTERN SWI_Handler - PUBLIC Prefetch_Handler - PUBLIC Abort_Handler - PUBLIC IRQ_Handler + PUBLIC __vector_table + PUBLIC __RST_Handler + EXTERN Undef_Handler + EXTERN SVC_Handler + EXTERN PAbt_Handler + EXTERN DAbt_Handler + EXTERN IRQ_Handler PUBLIC FIQ_Handler - EXTERN VbarInit - EXTERN SetLowVectors - EXTERN init_TTB - EXTERN enable_mmu - EXTERN Peripheral_BasicInit - EXTERN initsct - EXTERN PowerON_Reset - PUBLIC FPUEnable - DATA __iar_init$$done: ; The vector table is not needed ; until after copy initialization is done -__vector_core_a9: ; Make this a DATA label, so that stack usage +__vector_table: ; Make this a DATA label, so that stack usage ; analysis doesn't consider it an uncalled fun ARM @@ -71,11 +62,11 @@ __vector_core_a9: ; Make this a DATA label, so that stack usage DATA -Reset_Addr: DCD __iar_program_start -Undefined_Addr: DCD Undefined_Handler -SWI_Addr: DCD SWI_Handler -Prefetch_Addr: DCD Prefetch_Handler -Abort_Addr: DCD Abort_Handler +Reset_Addr: DCD __RST_Handler +Undefined_Addr: DCD Undef_Handler +SWI_Addr: DCD SVC_Handler +Prefetch_Addr: DCD PAbt_Handler +Abort_Addr: DCD DAbt_Handler IRQ_Addr: DCD IRQ_Handler FIQ_Addr: DCD FIQ_Handler @@ -90,21 +81,20 @@ FIQ_Addr: DCD FIQ_Handler SECTION .text:CODE:NOROOT(2) - EXTERN RZ_A1_SetSramWriteEnable - EXTERN create_translation_table EXTERN SystemInit - EXTERN InitMemorySubsystem - EXTERN __cmain - REQUIRE __vector_core_a9 + EXTERN __iar_program_start + REQUIRE __vector_table EXTWEAK __iar_init_core EXTWEAK __iar_init_vfp ARM -__iar_program_start: +__RST_Handler: ?cstartup: +;;; @ Mask interrupts + CPSID if ;;; @ Put any cores other than 0 to sleep mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR @@ -114,19 +104,7 @@ goToSleep: wfine bne goToSleep - -//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -//@ Enables Full Access i.e. in both privileged and non privileged modes - mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR) - orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11 - mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR) - isb - - -;; Switch on the VFP and NEON hardware - mov r0, #0x40000000 - vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set - +;;; @ Reset SCTLR Settings mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache @@ -136,9 +114,13 @@ goToSleep: mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register isb +;;; @ Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 ;@ Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) ;@ Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 ;@ Write CP15 Auxiliary Control Register ;; Set Vector Base Address Register (VBAR) to point to this application's vector table - ldr r0, =__vector_core_a9 + ldr r0, =__vector_table mcr p15, 0, r0, c12, c0, 0 @@ -169,20 +151,6 @@ goToSleep: #define UND_MODE 0x1B ; Undefined Instruction mode #define SYS_MODE 0x1F ; System mode -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define GICI_BASE 0xe8202000 -#define ICCIAR_OFFSET 0x0000000C -#define ICCEOIR_OFFSET 0x00000010 -#define ICCHPIR_OFFSET 0x00000018 -#define GICD_BASE 0xe8201000 -#define GIC_ERRATA_CHECK_1 0x000003FE -#define GIC_ERRATA_CHECK_2 0x000003FF -#define ICDABR0_OFFSET 0x00000300 -#define ICDIPR0_OFFSET 0x00000400 -#define T_Bit 0x20 ; when T bit is set, core is in Thumb state - MRS r0, cpsr ; Original PSR value ;; Set up the SVC stack pointer. @@ -235,271 +203,16 @@ goToSleep: BIC sp,sp,#0x7 ; Make sure SP is 8 aligned ;;; - - isb - ldr r0, =RZ_A1_SetSramWriteEnable - blx r0 - - bl create_translation_table - ; USR/SYS stack pointer will be set during kernel init ldr r0, =SystemInit blx r0 - ldr r0, =InitMemorySubsystem - blx r0 - -; fp_init - mov r0, #0x3000000 - vmsr fpscr, r0 - - ;;; Continue to __cmain for C-level initialization. - FUNCALL __iar_program_start, __cmain - B __cmain - - - ldr r0, sf_boot ;@ dummy to keep boot loader area -loop_here: - b loop_here - -sf_boot: - DC32 0x00000001 - -Undefined_Handler: - EXTERN CUndefHandler - SRSDB SP!, #Mode_UND - PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ - - MRS R0, SPSR - TST R0, #T_Bit /* Check mode */ - MOVEQ R1, #4 /* R1 = 4 ARM mode */ - MOVNE R1, #2 /* R1 = 2 Thumb mode */ - SUB R0, LR, R1 - LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ - BEQ undef_cont - - /* Thumb instruction */ - /* Determine if it is a 32-bit Thumb instruction */ - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont /* 16-bit Thumb instruction */ - - /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont: - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - /* R0 Offending instruction */ - /* R1 =2 (Thumb) or =4 (ARM) */ - BL CUndefHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ - SUB LR, LR, R0 - LDR R0, [SP, #28] /* Restore stacked SPSR */ - MSR SPSR_cxsf, R0 - POP {R0-R4, R12} /* Restore stacked APCS registers */ - ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ - MOVS PC, LR - -Prefetch_Handler: - EXTERN CPAbtHandler - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - MRC p15, 0, R0, c5, c0, 1 /* IFSR */ - MRC p15, 0, R1, c6, c0, 2 /* IFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CPAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stack APCS registers */ - RFEFD SP! /* Return from exception */ - -Abort_Handler: - EXTERN CDAbtHandler - SUB LR, LR, #8 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - CLREX /* State of exclusive monitors unknown after taken data abort */ - MRC p15, 0, R0, c5, c0, 0 /* DFSR */ - MRC p15, 0, R1, c6, c0, 0 /* DFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CDAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ + FUNCALL __RST_Handler, __iar_program_start + B __iar_program_start FIQ_Handler: - /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - * so if a real FIQ Handler is implemented, this will be needed before returning: - */ - /* LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - */ B . - EXTERN SVC_Handler /* refer RTX function */ - -IRQ_Handler: - EXTERN IRQCount - EXTERN IRQTable - EXTERN IRQNestLevel - - /* prologue */ - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ - CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ - PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ - -/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R1, R3, #4 - SUB SP, SP, R1 /* Adjust stack */ - PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - ADD R1, R1, #1 /* Increment nesting counter */ - STR R1, [R0] - - /* identify and acknowledge interrupt */ - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ - LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ - DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ - - /* Workaround GIC 390 errata 733075 - * If the ID is not 0, then service the interrupt as normal. - * If the ID is 0 and active, then service interrupt ID 0 as normal. - * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - */ - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active /* If the ID is not 0, then service the interrupt */ - LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ - TST R3, #1 - BNE int_active /* If active, then service the interrupt */ -unlock_cpu: - LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ - STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ - DSB /* Ensure the write completes before continuing */ - B ret_irq /* Do not service the spurious interrupt */ - /* End workaround */ - -int_active: - LDR R2, =IRQCount /* Read number of IRQs */ - LDR R2, [R2] - CMP R0, R2 /* Clean up and return if no handler */ - BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ - LDR R2, =IRQTable /* Get address of handler */ - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 /* Clean up and return if handler address is 0 */ - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i /* Now safe to re-enable interrupts */ - BLX R2 /* Call handler. R0 will be IRQ number */ - CPSID i /* Disable interrupts again */ - - /* write EOIR (GIC CPU Interface register) */ - POP {R0,R1} - DSB /* Ensure that interrupt source is cleared before we write the EOIR */ -ret_irq: - /* epilogue */ - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - SUB R1, R1, #1 /* Decrement nesting counter */ - STR R1, [R0] - - POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ - ADD SP, SP, R1 /* Unadjust stack */ - - POP {R0-R3,R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ -;;; -;;; Add more initialization here -;;; -FPUEnable: - ARM - - //Permit access to VFP registers by modifying CPACR - MRC p15,0,R1,c1,c0,2 - ORR R1,R1,#0x00F00000 - MCR p15,0,R1,c1,c0,2 - - //Enable VFP - VMRS R1,FPEXC - ORR R1,R1,#0x40000000 - VMSR FPEXC,R1 - - //Initialise VFP registers to 0 - MOV R2,#0 - VMOV D0, R2,R2 - VMOV D1, R2,R2 - VMOV D2, R2,R2 - VMOV D3, R2,R2 - VMOV D4, R2,R2 - VMOV D5, R2,R2 - VMOV D6, R2,R2 - VMOV D7, R2,R2 - VMOV D8, R2,R2 - VMOV D9, R2,R2 - VMOV D10,R2,R2 - VMOV D11,R2,R2 - VMOV D12,R2,R2 - VMOV D13,R2,R2 - VMOV D14,R2,R2 - VMOV D15,R2,R2 - - //Initialise FPSCR to a known state - VMRS R2,FPSCR - LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - AND R2,R2,R3 - VMSR FPSCR,R2 - - BX LR - END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h index 0a79f4c8e8..089284dc1c 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h @@ -1,1075 +1 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/**************************************************************************//** - * @file VKRZA1H.h - * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for - * Renesas RZA1H Device Series - * @version - * @date 19 Sept 2013 - * - * @note - * - ******************************************************************************/ - -#ifndef __VKRZA1H_H__ -#define __VKRZA1H_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/****** SGI Interrupts Numbers ****************************************/ - SGI0_IRQn = 0, - SGI1_IRQn = 1, - SGI2_IRQn = 2, - SGI3_IRQn = 3, - SGI4_IRQn = 4, - SGI5_IRQn = 5, - SGI6_IRQn = 6, - SGI7_IRQn = 7, - SGI8_IRQn = 8, - SGI9_IRQn = 9, - SGI10_IRQn = 10, - SGI11_IRQn = 11, - SGI12_IRQn = 12, - SGI13_IRQn = 13, - SGI14_IRQn = 14, - SGI15_IRQn = 15, - -/****** Cortex-A9 Processor Exceptions Numbers ****************************************/ - /* 16 - 578 */ - PMUIRQ0_IRQn = 16, - COMMRX0_IRQn = 17, - COMMTX0_IRQn = 18, - CTIIRQ0_IRQn = 19, - - IRQ0_IRQn = 32, - IRQ1_IRQn = 33, - IRQ2_IRQn = 34, - IRQ3_IRQn = 35, - IRQ4_IRQn = 36, - IRQ5_IRQn = 37, - IRQ6_IRQn = 38, - IRQ7_IRQn = 39, - - PL310ERR_IRQn = 40, - - DMAINT0_IRQn = 41, /*!< DMAC Interrupt */ - DMAINT1_IRQn = 42, /*!< DMAC Interrupt */ - DMAINT2_IRQn = 43, /*!< DMAC Interrupt */ - DMAINT3_IRQn = 44, /*!< DMAC Interrupt */ - DMAINT4_IRQn = 45, /*!< DMAC Interrupt */ - DMAINT5_IRQn = 46, /*!< DMAC Interrupt */ - DMAINT6_IRQn = 47, /*!< DMAC Interrupt */ - DMAINT7_IRQn = 48, /*!< DMAC Interrupt */ - DMAINT8_IRQn = 49, /*!< DMAC Interrupt */ - DMAINT9_IRQn = 50, /*!< DMAC Interrupt */ - DMAINT10_IRQn = 51, /*!< DMAC Interrupt */ - DMAINT11_IRQn = 52, /*!< DMAC Interrupt */ - DMAINT12_IRQn = 53, /*!< DMAC Interrupt */ - DMAINT13_IRQn = 54, /*!< DMAC Interrupt */ - DMAINT14_IRQn = 55, /*!< DMAC Interrupt */ - DMAINT15_IRQn = 56, /*!< DMAC Interrupt */ - DMAERR_IRQn = 57, /*!< DMAC Interrupt */ - - /* 58-72 Reserved */ - - USBI0_IRQn = 73, - USBI1_IRQn = 74, - - S0_VI_VSYNC0_IRQn = 75, - S0_LO_VSYNC0_IRQn = 76, - S0_VSYNCERR0_IRQn = 77, - GR3_VLINE0_IRQn = 78, - S0_VFIELD0_IRQn = 79, - IV1_VBUFERR0_IRQn = 80, - IV3_VBUFERR0_IRQn = 81, - IV5_VBUFERR0_IRQn = 82, - IV6_VBUFERR0_IRQn = 83, - S0_WLINE0_IRQn = 84, - S1_VI_VSYNC0_IRQn = 85, - S1_LO_VSYNC0_IRQn = 86, - S1_VSYNCERR0_IRQn = 87, - S1_VFIELD0_IRQn = 88, - IV2_VBUFERR0_IRQn = 89, - IV4_VBUFERR0_IRQn = 90, - S1_WLINE0_IRQn = 91, - OIR_VI_VSYNC0_IRQn = 92, - OIR_LO_VSYNC0_IRQn = 93, - OIR_VSYNCERR0_IRQn = 94, - OIR_VFIELD0_IRQn = 95, - IV7_VBUFERR0_IRQn = 96, - IV8_VBUFERR0_IRQn = 97, - /* 98 Reserved */ - S0_VI_VSYNC1_IRQn = 99, - S0_LO_VSYNC1_IRQn = 100, - S0_VSYNCERR1_IRQn = 101, - GR3_VLINE1_IRQn = 102, - S0_VFIELD1_IRQn = 103, - IV1_VBUFERR1_IRQn = 104, - IV3_VBUFERR1_IRQn = 105, - IV5_VBUFERR1_IRQn = 106, - IV6_VBUFERR1_IRQn = 107, - S0_WLINE1_IRQn = 108, - S1_VI_VSYNC1_IRQn = 109, - S1_LO_VSYNC1_IRQn = 110, - S1_VSYNCERR1_IRQn = 111, - S1_VFIELD1_IRQn = 112, - IV2_VBUFERR1_IRQn = 113, - IV4_VBUFERR1_IRQn = 114, - S1_WLINE1_IRQn = 115, - OIR_VI_VSYNC1_IRQn = 116, - OIR_LO_VSYNC1_IRQn = 117, - OIR_VSYNCERR1_IRQn = 118, - OIR_VFIELD1_IRQn = 119, - IV7_VBUFERR1_IRQn = 120, - IV8_VBUFERR1_IRQn = 121, - /* Reserved = 122 */ - - IMRDI_IRQn = 123, - IMR2I0_IRQn = 124, - IMR2I1_IRQn = 125, - - JEDI_IRQn = 126, - JDTI_IRQn = 127, - - CMP0_IRQn = 128, - CMP1_IRQn = 129, - - INT0_IRQn = 130, - INT1_IRQn = 131, - INT2_IRQn = 132, - INT3_IRQn = 133, - - OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */ - OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */ - - CMI_IRQn = 136, - WTOUT_IRQn = 137, - - ITI_IRQn = 138, - - TGI0A_IRQn = 139, - TGI0B_IRQn = 140, - TGI0C_IRQn = 141, - TGI0D_IRQn = 142, - TGI0V_IRQn = 143, - TGI0E_IRQn = 144, - TGI0F_IRQn = 145, - TGI1A_IRQn = 146, - TGI1B_IRQn = 147, - TGI1V_IRQn = 148, - TGI1U_IRQn = 149, - TGI2A_IRQn = 150, - TGI2B_IRQn = 151, - TGI2V_IRQn = 152, - TGI2U_IRQn = 153, - TGI3A_IRQn = 154, - TGI3B_IRQn = 155, - TGI3C_IRQn = 156, - TGI3D_IRQn = 157, - TGI3V_IRQn = 158, - TGI4A_IRQn = 159, - TGI4B_IRQn = 160, - TGI4C_IRQn = 161, - TGI4D_IRQn = 162, - TGI4V_IRQn = 163, - - CMI1_IRQn = 164, - CMI2_IRQn = 165, - - SGDEI0_IRQn = 166, - SGDEI1_IRQn = 167, - SGDEI2_IRQn = 168, - SGDEI3_IRQn = 169, - - ADI_IRQn = 170, - LMTI_IRQn = 171, - - SSII0_IRQn = 172, /*!< SSIF Interrupt */ - SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */ - SSITXI0_IRQn = 174, /*!< SSIF Interrupt */ - SSII1_IRQn = 175, /*!< SSIF Interrupt */ - SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */ - SSITXI1_IRQn = 177, /*!< SSIF Interrupt */ - SSII2_IRQn = 178, /*!< SSIF Interrupt */ - SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */ - SSII3_IRQn = 180, /*!< SSIF Interrupt */ - SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */ - SSITXI3_IRQn = 182, /*!< SSIF Interrupt */ - SSII4_IRQn = 183, /*!< SSIF Interrupt */ - SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */ - SSII5_IRQn = 185, /*!< SSIF Interrupt */ - SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */ - SSITXI5_IRQn = 187, /*!< SSIF Interrupt */ - - SPDIFI_IRQn = 188, - - INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */ - INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */ - INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */ - INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */ - INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */ - INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */ - INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */ - INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */ - INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */ - INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */ - INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */ - INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */ - INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */ - INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */ - INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */ - INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */ - INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */ - INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */ - INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */ - INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */ - INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */ - INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */ - INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */ - INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */ - INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */ - INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */ - INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */ - INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */ - INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */ - INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */ - INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */ - INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */ - - SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */ - SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */ - SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */ - SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */ - SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */ - SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */ - SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */ - SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */ - SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */ - SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */ - SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */ - SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */ - SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */ - SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */ - SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */ - SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */ - SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */ - SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */ - SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */ - SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */ - SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */ - SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */ - SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */ - SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */ - SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */ - SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */ - SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */ - SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */ - SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */ - SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */ - SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */ - SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */ - - INTRCANGERR_IRQn = 253, - INTRCANGRECC_IRQn = 254, - INTRCAN0REC_IRQn = 255, - INTRCAN0ERR_IRQn = 256, - INTRCAN0TRX_IRQn = 257, - INTRCAN1REC_IRQn = 258, - INTRCAN1ERR_IRQn = 259, - INTRCAN1TRX_IRQn = 260, - INTRCAN2REC_IRQn = 261, - INTRCAN2ERR_IRQn = 262, - INTRCAN2TRX_IRQn = 263, - INTRCAN3REC_IRQn = 264, - INTRCAN3ERR_IRQn = 265, - INTRCAN3TRX_IRQn = 266, - INTRCAN4REC_IRQn = 267, - INTRCAN4ERR_IRQn = 268, - INTRCAN4TRX_IRQn = 269, - - RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */ - RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */ - RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */ - RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */ - RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */ - RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */ - RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */ - RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */ - RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */ - RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */ - RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */ - RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */ - RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */ - RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */ - RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */ - - IEBBTD_IRQn = 285, - IEBBTERR_IRQn = 286, - IEBBTSTA_IRQn = 287, - IEBBTV_IRQn = 288, - - ISY_IRQn = 289, - IERR_IRQn = 290, - ITARG_IRQn = 291, - ISEC_IRQn = 292, - IBUF_IRQn = 293, - IREADY_IRQn = 294, - - STERB_IRQn = 295, - FLTENDI_IRQn = 296, - FLTREQ0I_IRQn = 297, - FLTREQ1I_IRQn = 298, - - MMC0_IRQn = 299, - MMC1_IRQn = 300, - MMC2_IRQn = 301, - - SCHI0_3_IRQn = 302, - SDHI0_0_IRQn = 303, - SDHI0_1_IRQn = 304, - SCHI1_3_IRQn = 305, - SDHI1_0_IRQn = 306, - SDHI1_1_IRQn = 307, - - ARM_IRQn = 308, - PRD_IRQn = 309, - CUP_IRQn = 310, - - SCUAI0_IRQn = 311, - SCUAI1_IRQn = 312, - SCUFDI0_IRQn = 313, - SCUFDI1_IRQn = 314, - SCUFDI2_IRQn = 315, - SCUFDI3_IRQn = 316, - SCUFUI0_IRQn = 317, - SCUFUI1_IRQn = 318, - SCUFUI2_IRQn = 319, - SCUFUI3_IRQn = 320, - SCUDVI0_IRQn = 321, - SCUDVI1_IRQn = 322, - SCUDVI2_IRQn = 323, - SCUDVI3_IRQn = 324, - - MLB_CINT_IRQn = 325, - MLB_SINT_IRQn = 326, - - DRC10_IRQn = 327, - DRC11_IRQn = 328, - - /* 329-330 Reserved */ - - LINI0_INT_T_IRQn = 331, - LINI0_INT_R_IRQn = 332, - LINI0_INT_S_IRQn = 333, - LINI0_INT_M_IRQn = 334, - LINI1_INT_T_IRQn = 335, - LINI1_INT_R_IRQn = 336, - LINI1_INT_S_IRQn = 337, - LINI1_INT_M_IRQn = 338, - - /* 339-346 Reserved */ - - SCIERI0_IRQn = 347, - SCIRXI0_IRQn = 348, - SCITXI0_IRQn = 349, - SCITEI0_IRQn = 350, - SCIERI1_IRQn = 351, - SCIRXI1_IRQn = 352, - SCITXI1_IRQn = 353, - SCITEI1_IRQn = 354, - - AVBI_DATA = 355, - AVBI_ERROR = 356, - AVBI_MANAGE = 357, - AVBI_MAC = 358, - - ETHERI_IRQn = 359, - - /* 360-363 Reserved */ - - CEUI_IRQn = 364, - - /* 365-380 Reserved */ - - - H2XMLB_ERRINT_IRQn = 381, - H2XIC1_ERRINT_IRQn = 382, - X2HPERI1_ERRINT_IRQn = 383, - X2HPERR2_ERRINT_IRQn = 384, - X2HPERR34_ERRINT_IRQn= 385, - X2HPERR5_ERRINT_IRQn = 386, - X2HPERR67_ERRINT_IRQn= 387, - X2HDBGR_ERRINT_IRQn = 388, - X2HBSC_ERRINT_IRQn = 389, - X2HSPI1_ERRINT_IRQn = 390, - X2HSPI2_ERRINT_IRQn = 391, - PRRI_IRQn = 392, - - IFEI0_IRQn = 393, - OFFI0_IRQn = 394, - PFVEI0_IRQn = 395, - IFEI1_IRQn = 396, - OFFI1_IRQn = 397, - PFVEI1_IRQn = 398, - - /* 399-415 Reserved */ - TINT0_IRQn = 416, - TINT1_IRQn = 417, - TINT2_IRQn = 418, - TINT3_IRQn = 419, - TINT4_IRQn = 420, - TINT5_IRQn = 421, - TINT6_IRQn = 422, - TINT7_IRQn = 423, - TINT8_IRQn = 424, - TINT9_IRQn = 425, - TINT10_IRQn = 426, - TINT11_IRQn = 427, - TINT12_IRQn = 428, - TINT13_IRQn = 429, - TINT14_IRQn = 430, - TINT15_IRQn = 431, - TINT16_IRQn = 432, - TINT17_IRQn = 433, - TINT18_IRQn = 434, - TINT19_IRQn = 435, - TINT20_IRQn = 436, - TINT21_IRQn = 437, - TINT22_IRQn = 438, - TINT23_IRQn = 439, - TINT24_IRQn = 440, - TINT25_IRQn = 441, - TINT26_IRQn = 442, - TINT27_IRQn = 443, - TINT28_IRQn = 444, - TINT29_IRQn = 445, - TINT30_IRQn = 446, - TINT31_IRQn = 447, - TINT32_IRQn = 448, - TINT33_IRQn = 449, - TINT34_IRQn = 450, - TINT35_IRQn = 451, - TINT36_IRQn = 452, - TINT37_IRQn = 453, - TINT38_IRQn = 454, - TINT39_IRQn = 455, - TINT40_IRQn = 456, - TINT41_IRQn = 457, - TINT42_IRQn = 458, - TINT43_IRQn = 459, - TINT44_IRQn = 460, - TINT45_IRQn = 461, - TINT46_IRQn = 462, - TINT47_IRQn = 463, - TINT48_IRQn = 464, - TINT49_IRQn = 465, - TINT50_IRQn = 466, - TINT51_IRQn = 467, - TINT52_IRQn = 468, - TINT53_IRQn = 469, - TINT54_IRQn = 470, - TINT55_IRQn = 471, - TINT56_IRQn = 472, - TINT57_IRQn = 473, - TINT58_IRQn = 474, - TINT59_IRQn = 475, - TINT60_IRQn = 476, - TINT61_IRQn = 477, - TINT62_IRQn = 478, - TINT63_IRQn = 479, - TINT64_IRQn = 480, - TINT65_IRQn = 481, - TINT66_IRQn = 482, - TINT67_IRQn = 483, - TINT68_IRQn = 484, - TINT69_IRQn = 485, - TINT70_IRQn = 486, - TINT71_IRQn = 487, - TINT72_IRQn = 488, - TINT73_IRQn = 489, - TINT74_IRQn = 490, - TINT75_IRQn = 491, - TINT76_IRQn = 492, - TINT77_IRQn = 493, - TINT78_IRQn = 494, - TINT79_IRQn = 495, - TINT80_IRQn = 496, - TINT81_IRQn = 497, - TINT82_IRQn = 498, - TINT83_IRQn = 499, - TINT84_IRQn = 500, - TINT85_IRQn = 501, - TINT86_IRQn = 502, - TINT87_IRQn = 503, - TINT88_IRQn = 504, - TINT89_IRQn = 505, - TINT90_IRQn = 506, - TINT91_IRQn = 507, - TINT92_IRQn = 508, - TINT93_IRQn = 509, - TINT94_IRQn = 510, - TINT95_IRQn = 511, - TINT96_IRQn = 512, - TINT97_IRQn = 513, - TINT98_IRQn = 514, - TINT99_IRQn = 515, - TINT100_IRQn = 516, - TINT101_IRQn = 517, - TINT102_IRQn = 518, - TINT103_IRQn = 519, - TINT104_IRQn = 520, - TINT105_IRQn = 521, - TINT106_IRQn = 522, - TINT107_IRQn = 523, - TINT108_IRQn = 524, - TINT109_IRQn = 525, - TINT110_IRQn = 526, - TINT111_IRQn = 527, - TINT112_IRQn = 528, - TINT113_IRQn = 529, - TINT114_IRQn = 530, - TINT115_IRQn = 531, - TINT116_IRQn = 532, - TINT117_IRQn = 533, - TINT118_IRQn = 534, - TINT119_IRQn = 535, - TINT120_IRQn = 536, - TINT121_IRQn = 537, - TINT122_IRQn = 538, - TINT123_IRQn = 539, - TINT124_IRQn = 540, - TINT125_IRQn = 541, - TINT126_IRQn = 542, - TINT127_IRQn = 543, - TINT128_IRQn = 544, - TINT129_IRQn = 545, - TINT130_IRQn = 546, - TINT131_IRQn = 547, - TINT132_IRQn = 548, - TINT133_IRQn = 549, - TINT134_IRQn = 550, - TINT135_IRQn = 551, - TINT136_IRQn = 552, - TINT137_IRQn = 553, - TINT138_IRQn = 554, - TINT139_IRQn = 555, - TINT140_IRQn = 556, - TINT141_IRQn = 557, - TINT142_IRQn = 558, - TINT143_IRQn = 559, - TINT144_IRQn = 560, - TINT145_IRQn = 561, - TINT146_IRQn = 562, - TINT147_IRQn = 563, - TINT148_IRQn = 564, - TINT149_IRQn = 565, - TINT150_IRQn = 566, - TINT151_IRQn = 567, - TINT152_IRQn = 568, - TINT153_IRQn = 569, - TINT154_IRQn = 570, - TINT155_IRQn = 571, - TINT156_IRQn = 572, - TINT157_IRQn = 573, - TINT158_IRQn = 574, - TINT159_IRQn = 575, - TINT160_IRQn = 576, - TINT161_IRQn = 577, - TINT162_IRQn = 578, - TINT163_IRQn = 579, - TINT164_IRQn = 580, - TINT165_IRQn = 581, - TINT166_IRQn = 582, - TINT167_IRQn = 583, - TINT168_IRQn = 584, - TINT169_IRQn = 585, - TINT170_IRQn = 586 - -} IRQn_Type; - -#define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn - -/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ -#define __CA9_REV 0x0000 /*!< Core revision r0 */ - -#define __MPU_PRESENT 1 /*!< MPU present or not */ - -#define __FPU_PRESENT 1 /*!< FPU present or not */ - -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -#include "core_ca.h" -#include "system_VKRZA1H.h" -#include "iodefine.h" - -/******************************************************************************/ -/* Device Specific Peripheral Section */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals - Renesas_RZ_A1 Device Specific Peripheral registers structures - @{ -*/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -#include "pl310.h" -#include "gic.h" -#include "nvic_wrapper.h" -#include "cmsis_nvic.h" - -#include "ostm_iodefine.h" -#include "gpio_iodefine.h" -#include "cpg_iodefine.h" -#include "l2c_iodefine.h" - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/*@}*/ /* end of group Renesas_RZ_A1_Peripherals */ - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping - @{ -*/ - -/* R7S72100 CPU board */ -#define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ -#define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ -#define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ -#define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ -#define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ -#define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ -#define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ -#define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ -#define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ -#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ -#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ -#define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ -#define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ -#define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ -#define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ - -//Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map -//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0. -#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = NORMAL; \ - region.sec_t = SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0. -#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Normal_RO. Sect_Normal_Cod, but not executable -#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -#ifdef __RAM_DEBUG__ -//Sect_Normal_RWX. Sect_Normal_Cod, but writeable -#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); -#else -//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable -#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); -#endif - -//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 -#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 -#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Device_RW. Sect_Device_RO, but writeable -#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); -//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 -#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = SHARED_DEVICE; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); - -//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 -#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = SHARED_DEVICE; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); - -/*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */ - -/******************************************************************************/ -/* Clock Settings */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions - @{ -*/ - -/* - * Clock Mode 0 settings - * SW1-4(MD_CLK):ON - * SW1-5(MD_CLKS):ON - * FRQCR=0x1035 - * CLKEN2 = 0b - unstable - * CLKEN[1:0]=01b - Output, Low, Low - * IFC[1:0] =00b - CPU clock is 1/1 PLL clock - * FRQCR2=0x0001 - * GFC[1:0] =01b - Graphic clock is 2/3 bus clock - */ -#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u) -#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u) -#define CM0_RENESAS_RZ_A1_I_CLK (400000000u) -#define CM0_RENESAS_RZ_A1_G_CLK (266666666u) -#define CM0_RENESAS_RZ_A1_B_CLK (133333333u) -#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u) -#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) - -/* - * Clock Mode 1 settings - * SW1-4(MD_CLK):OFF - * SW1-5(MD_CLKS):ON - * FRQCR=0x1335 - * CLKEN2 = 0b - unstable - * CLKEN[1:0]=01b - Output, Low, Low - * IFC[1:0] =11b - CPU clock is 1/3 PLL clock - * FRQCR2=0x0003 - * GFC[1:0] =11b - graphic clock is 1/3 bus clock - */ -#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u) -#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u) -#define CM1_RENESAS_RZ_A1_I_CLK (128000000u) -#define CM1_RENESAS_RZ_A1_G_CLK (128000000u) -#define CM1_RENESAS_RZ_A1_B_CLK (128000000u) -#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) -#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) - -/*@}*/ /* end of group Renesas_RZ_A1_Clocks */ - -/******************************************************************************/ -/* CPG Settings */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions - @{ -*/ - -#define CPG_FRQCR_SHIFT_CKOEN2 (14) -#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) -#define CPG_FRQCR_SHIFT_CKOEN0 (12) -#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) -#define CPG_FRQCR_SHIFT_IFC (8) -#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) - -#define CPG_FRQCR2_SHIFT_GFC (0) -#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) - - -#define CPG_STBCR1_BIT_STBY (0x80u) -#define CPG_STBCR1_BIT_DEEP (0x40u) -#define CPG_STBCR2_BIT_HIZ (0x80u) -#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ -#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ -#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ -#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ -#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ -#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ -#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ -#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ -#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ -#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ -#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ -#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ -#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ -#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ -#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ -#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ -#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ -#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ -#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ -#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ -#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ -#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ -#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ -#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ -#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */ -#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ -#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ -#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ -#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */ -#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */ -#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ -#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ -#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ -#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ -#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */ -#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ -#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ -#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ -#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ -#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ -#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ -#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ -#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ -#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ -#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ -#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ -#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ -#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ -#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ -#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ -#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ -#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ -#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ -#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ -#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ -#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ -#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ -#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ -#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ -#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ -#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ -#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ -#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ -#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ -#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ -#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ -#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ -#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ -#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ -#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ -#define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */ -#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ -#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ -#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ -#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ -#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ -#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ -#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ -#define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */ -#define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */ -#define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */ -#define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */ -#define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */ -#define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */ -#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ -#define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */ -#define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */ -#define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */ -#define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */ -#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ -#define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */ -#define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */ -#define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */ -#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ -#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ -#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ -#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ -#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ -#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ -#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ -#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ -#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ -#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ -#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ -#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ -#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ -#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ - -/*@}*/ /* end of group Renesas_RZ_A1_CPG */ - -/******************************************************************************/ -/* GPIO Settings */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions - @{ -*/ - -#define GPIO_BIT_N0 (1u << 0) -#define GPIO_BIT_N1 (1u << 1) -#define GPIO_BIT_N2 (1u << 2) -#define GPIO_BIT_N3 (1u << 3) -#define GPIO_BIT_N4 (1u << 4) -#define GPIO_BIT_N5 (1u << 5) -#define GPIO_BIT_N6 (1u << 6) -#define GPIO_BIT_N7 (1u << 7) -#define GPIO_BIT_N8 (1u << 8) -#define GPIO_BIT_N9 (1u << 9) -#define GPIO_BIT_N10 (1u << 10) -#define GPIO_BIT_N11 (1u << 11) -#define GPIO_BIT_N12 (1u << 12) -#define GPIO_BIT_N13 (1u << 13) -#define GPIO_BIT_N14 (1u << 14) -#define GPIO_BIT_N15 (1u << 15) - - -#define MD_BOOT10_MASK (0x3) - -#define MD_BOOT10_BM0 (0x0) -#define MD_BOOT10_BM1 (0x2) -#define MD_BOOT10_BM3 (0x1) -#define MD_BOOT10_BM4_5 (0x3) - -#define MD_CLK (1u << 2) -#define MD_CLKS (1u << 3) - -/*@}*/ /* end of group Renesas_RZ_A1_GPIO */ - -#ifdef __cplusplus -} -#endif - -#endif // __VKRZA1H_H__ +#include "VK_RZ_A1H.h" diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h index aa64c1d768..701c856fa4 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h @@ -8,5 +8,6 @@ #define MBED_CMSIS_H #include "VKRZA1H.h" +#include "cmsis_nvic.h" #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c index ad6ac0fb8f..1fa680598c 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c @@ -29,14 +29,15 @@ ******************************************************************************* */ #include "VKRZA1H.h" +#include "irq_ctrl.h" -extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ InterruptHandlerRegister(IRQn, (IRQHandler)vector); } -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t vectors = (uint32_t)IRQTable[IRQn]; +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn); return vectors; } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c deleted file mode 100644 index 9c68da0b4f..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c +++ /dev/null @@ -1,305 +0,0 @@ -/**************************************************************************//** - * @file gic.c - * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File - * @version - * @date 19 Sept 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#include "VKRZA1H.h" - -#define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */ -#define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */ - -/* Globals for use of post-scatterloading code that must access GIC */ -const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE; -const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE; - -void GIC_EnableDistributor(void) -{ - GICDistributor->ICDDCR |= 1; //enable distributor -} - -void GIC_DisableDistributor(void) -{ - GICDistributor->ICDDCR &=~1; //disable distributor -} - -uint32_t GIC_DistributorInfo(void) -{ - return (uint32_t)(GICDistributor->ICDICTR); -} - -uint32_t GIC_DistributorImplementer(void) -{ - return (uint32_t)(GICDistributor->ICDIIDR); -} - -void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); - field += IRQn % 4; - *field = (uint8_t)cpu_target & 0xf; -} - -void GIC_SetICDICFR (const uint32_t *ICDICFRn) -{ - uint32_t i, num_irq; - - //Get the maximum number of interrupts that the GIC supports - num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); - - for (i = 0; i < (num_irq/16); i++) - { - GICDistributor->ICDISPR[i] = *ICDICFRn++; - } -} - -uint32_t GIC_GetTarget(IRQn_Type IRQn) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); - field += IRQn % 4; - return ((uint32_t)*field & 0xf); -} - -void GIC_EnableInterface(void) -{ - GICInterface->ICCICR |= 1; //enable interface -} - -void GIC_DisableInterface(void) -{ - GICInterface->ICCICR &=~1; //disable distributor -} - -IRQn_Type GIC_AcknowledgePending(void) -{ - return (IRQn_Type)(GICInterface->ICCIAR); -} - -void GIC_EndInterrupt(IRQn_Type IRQn) -{ - GICInterface->ICCEOIR = IRQn; -} - -void GIC_EnableIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_DisableIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_SetPendingIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]); - int bit_shift = (IRQn % 16)<<1; - uint8_t save_byte; - - field += (bit_shift / 8); - bit_shift %= 8; - - save_byte = *field; - save_byte &= ((uint8_t)~(3u << bit_shift)); - - *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift); -} - -void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); - field += (IRQn % 4); - *field = (uint8_t)priority; -} - -uint32_t GIC_GetPriority(IRQn_Type IRQn) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); - field += (IRQn % 4); - return (uint32_t)*field; -} - -void GIC_InterfacePriorityMask(uint32_t priority) -{ - GICInterface->ICCPMR = priority & 0xff; //set priority mask -} - -void GIC_SetBinaryPoint(uint32_t binary_point) -{ - GICInterface->ICCBPR = binary_point & 0x07; //set binary point -} - -uint32_t GIC_GetBinaryPoint(uint32_t binary_point) -{ - return (uint32_t)GICInterface->ICCBPR; -} - -uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) -{ - uint32_t pending, active; - - active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1; - pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1; - - return ((active<<1) | pending); -} - -void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) -{ - GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf); -} - -void GIC_DistInit(void) -{ - //IRQn_Type i; - uint32_t i; - uint32_t num_irq = 0; - uint32_t priority_field; - - //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, - //configuring all of the interrupts as Secure. - - //Disable interrupt forwarding - GIC_DisableDistributor(); - //Get the maximum number of interrupts that the GIC supports - num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); - - /* Priority level is implementation defined. - To determine the number of priority bits implemented write 0xFF to an ICDIPR - priority field and read back the value stored.*/ - GIC_SetPriority((IRQn_Type)0, 0xff); - priority_field = GIC_GetPriority((IRQn_Type)0); - - for (i = 32; i < num_irq; i++) - { - //Disable all SPI the interrupts - GIC_DisableIRQ((IRQn_Type)i); - //Set level-sensitive and N-N model - //GIC_SetLevelModel(i, 0, 0); - //Set priority - GIC_SetPriority((IRQn_Type)i, priority_field/2); - //Set target list to "all cpus" - GIC_SetTarget((IRQn_Type)i, 0xff); - } - /* Set level-edge and 1-N model */ - /* GICDistributor->ICDICFR[ 0] is read only */ - GICDistributor->ICDICFR[ 1] = 0x00000055; - GICDistributor->ICDICFR[ 2] = 0xFFFD5555; - GICDistributor->ICDICFR[ 3] = 0x555FFFFF; - GICDistributor->ICDICFR[ 4] = 0x55555555; - GICDistributor->ICDICFR[ 5] = 0x55555555; - GICDistributor->ICDICFR[ 6] = 0x55555555; - GICDistributor->ICDICFR[ 7] = 0x55555555; - GICDistributor->ICDICFR[ 8] = 0x5555F555; - GICDistributor->ICDICFR[ 9] = 0x55555555; - GICDistributor->ICDICFR[10] = 0x55555555; - GICDistributor->ICDICFR[11] = 0xF5555555; - GICDistributor->ICDICFR[12] = 0xF555F555; - GICDistributor->ICDICFR[13] = 0x5555F555; - GICDistributor->ICDICFR[14] = 0x55555555; - GICDistributor->ICDICFR[15] = 0x55555555; - GICDistributor->ICDICFR[16] = 0x55555555; - GICDistributor->ICDICFR[17] = 0xFD555555; - GICDistributor->ICDICFR[18] = 0x55555557; - GICDistributor->ICDICFR[19] = 0x55555555; - GICDistributor->ICDICFR[20] = 0xFFD55555; - GICDistributor->ICDICFR[21] = 0x5F55557F; - GICDistributor->ICDICFR[22] = 0xFD55555F; - GICDistributor->ICDICFR[23] = 0x55555557; - GICDistributor->ICDICFR[24] = 0x55555555; - GICDistributor->ICDICFR[25] = 0x55555555; - GICDistributor->ICDICFR[26] = 0x55555555; - GICDistributor->ICDICFR[27] = 0x55555555; - GICDistributor->ICDICFR[28] = 0x55555555; - GICDistributor->ICDICFR[29] = 0x55555555; - GICDistributor->ICDICFR[30] = 0x55555555; - GICDistributor->ICDICFR[31] = 0x55555555; - GICDistributor->ICDICFR[32] = 0x55555555; - GICDistributor->ICDICFR[33] = 0x55555555; - - //Enable distributor - GIC_EnableDistributor(); -} - -void GIC_CPUInterfaceInit(void) -{ - IRQn_Type i; - uint32_t priority_field; - - //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, - //configuring all of the interrupts as Secure. - - //Disable interrupt forwarding - GIC_DisableInterface(); - - /* Priority level is implementation defined. - To determine the number of priority bits implemented write 0xFF to an ICDIPR - priority field and read back the value stored.*/ - GIC_SetPriority((IRQn_Type)0, 0xff); - priority_field = GIC_GetPriority((IRQn_Type)0); - - //SGI and PPI - for (i = (IRQn_Type)0; i < 32; i++) - { - //Set level-sensitive and N-N model for PPI - //if(i > 15) - //GIC_SetLevelModel(i, 0, 0); - //Disable SGI and PPI interrupts - GIC_DisableIRQ(i); - //Set priority - GIC_SetPriority(i, priority_field/2); - } - //Enable interface - GIC_EnableInterface(); - //Set binary point to 0 - GIC_SetBinaryPoint(0); - //Set priority mask - GIC_InterfacePriorityMask(0xff); -} - -void GIC_Enable(void) -{ - GIC_DistInit(); - GIC_CPUInterfaceInit(); //per CPU -} - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h deleted file mode 100644 index d4cbfd81ab..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h +++ /dev/null @@ -1,316 +0,0 @@ -/**************************************************************************//** - * @file gic.h - * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File - * @version - * @date 29 August 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef GIC_H_ -#define GIC_H_ - -/* IO definitions (access restrictions to peripheral registers) */ -/** -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) - */ -typedef struct -{ - __IO uint32_t ICDDCR; - __I uint32_t ICDICTR; - __I uint32_t ICDIIDR; - uint32_t RESERVED0[29]; - __IO uint32_t ICDISR[32]; - __IO uint32_t ICDISER[32]; - __IO uint32_t ICDICER[32]; - __IO uint32_t ICDISPR[32]; - __IO uint32_t ICDICPR[32]; - __I uint32_t ICDABR[32]; - uint32_t RESERVED1[32]; - __IO uint32_t ICDIPR[256]; - __IO uint32_t ICDIPTR[256]; - __IO uint32_t ICDICFR[64]; - uint32_t RESERVED2[128]; - __IO uint32_t ICDSGIR; -} GICDistributor_Type; - -/** \brief Structure type to access the Controller Interface (GICC) - */ -typedef struct -{ - __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register - __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register - __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register - __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register - __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register - __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register - __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register - __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register - - uint32_t RESERVED[55]; - - __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register -} GICInterface_Type; - -/*@} end of GICD */ - -/* ########################## GIC functions #################################### */ -/** \brief Functions that manage interrupts via the GIC. - @{ - */ - -/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface - - Enables the forwarding of pending interrupts to the CPU interfaces. - - */ -void GIC_EnableDistributor(void); - -/** \brief Disable Distributor - - Disables the forwarding of pending interrupts to the CPU interfaces. - - */ -void GIC_DisableDistributor(void); - -/** \brief Provides information about the configuration of the GIC. - Provides information about the configuration of the GIC. - - whether the GIC implements the Security Extensions - - the maximum number of interrupt IDs that the GIC supports - - the number of CPU interfaces implemented - - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). - - \return Distributor Information. - */ -uint32_t GIC_DistributorInfo(void); - -/** \brief Distributor Implementer Identification Register. - - Distributor Implementer Identification Register - - \return Implementer Information. - */ -uint32_t GIC_DistributorImplementer(void); - -/** \brief Set list of processors that the interrupt is sent to if it is asserted. - - The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. - This field stores the list of processors that the interrupt is sent to if it is asserted. - - \param [in] IRQn Interrupt number. - \param [in] target CPU target - */ -void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target); - -/** \brief Get list of processors that the interrupt is sent to if it is asserted. - - The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. - This field stores the list of processors that the interrupt is sent to if it is asserted. - - \param [in] IRQn Interrupt number. - \param [in] target CPU target -*/ -uint32_t GIC_GetTarget(IRQn_Type IRQn); - -/** \brief Enable Interface - - Enables the signalling of interrupts to the target processors. - - */ -void GIC_EnableInterface(void); - -/** \brief Disable Interface - - Disables the signalling of interrupts to the target processors. - - */ -void GIC_DisableInterface(void); - -/** \brief Acknowledge Interrupt - - The function acknowledges the highest priority pending interrupt and returns its IRQ number. - - \return Interrupt number - */ -IRQn_Type GIC_AcknowledgePending(void); - -/** \brief End Interrupt - - The function writes the end of interrupt register, indicating that handling of the interrupt is complete. - - \param [in] IRQn Interrupt number. - */ -void GIC_EndInterrupt(IRQn_Type IRQn); - - -/** \brief Enable Interrupt - - Set-enable bit for each interrupt supported by the GIC. - - \param [in] IRQn External interrupt number. - */ -void GIC_EnableIRQ(IRQn_Type IRQn); - -/** \brief Disable Interrupt - - Clear-enable bit for each interrupt supported by the GIC. - - \param [in] IRQn Number of the external interrupt to disable - */ -void GIC_DisableIRQ(IRQn_Type IRQn); - -/** \brief Set Pending Interrupt - - Set-pending bit for each interrupt supported by the GIC. - - \param [in] IRQn Interrupt number. - */ -void GIC_SetPendingIRQ(IRQn_Type IRQn); - -/** \brief Clear Pending Interrupt - - Clear-pending bit for each interrupt supported by the GIC - - \param [in] IRQn Number of the interrupt for clear pending - */ -void GIC_ClearPendingIRQ(IRQn_Type IRQn); - -/** \brief Int_config field for each interrupt supported by the GIC. - - This field identifies whether the corresponding interrupt is: - (1) edge-triggered or (0) level-sensitive - (1) 1-N model or (0) N-N model - - \param [in] IRQn Interrupt number. - \param [in] edge_level (1) edge-triggered or (0) level-sensitive - \param [in] model (1) 1-N model or (0) N-N model - */ -void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model); - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority); - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - */ -uint32_t GIC_GetPriority(IRQn_Type IRQn); - -/** \brief CPU Interface Priority Mask Register - - The priority mask level for the CPU interface. If the priority of an interrupt is higher than the - value indicated by this field, the interface signals the interrupt to the processor. - - \param [in] Mask. - */ -void GIC_InterfacePriorityMask(uint32_t priority); - -/** \brief Set the binary point. - - Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field. - - \param [in] Mask. - */ -void GIC_SetBinaryPoint(uint32_t binary_point); - -/** \brief Get the binary point. - - Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field. - - \return Binary point. - */ -uint32_t GIC_GetBinaryPoint(uint32_t binary_point); - -/** \brief Get Interrupt state. - - Get the interrupt state, whether pending and/or active - - \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active - */ -uint32_t GIC_GetIRQStatus(IRQn_Type IRQn); - -/** \brief Send Software Generated interrupt - - Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor. -GIC_InterfacePriorityMask - \param [in] IRQn The Interrupt ID of the SGI. - \param [in] target_list CPUTargetList - \param [in] filter_list TargetListFilter - */ -void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list); - -/** \brief API call to initialise the interrupt distributor - - API call to initialise the interrupt distributor - - */ -void GIC_DistInit(void); - -/** \brief API call to initialise the CPU interface - - API call to initialise the CPU interface - - */ -void GIC_CPUInterfaceInit(void); - -/** \brief API call to set the Interrupt Configuration Registers - - API call to initialise the Interrupt Configuration Registers - - */ -void GIC_SetICDICFR (const uint32_t *ICDICFRn); - -/** \brief API call to Enable the GIC - - API call to Enable the GIC - - */ -void GIC_Enable(void); - -#endif /* GIC_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h new file mode 100644 index 0000000000..faca6ce56c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h @@ -0,0 +1,922 @@ +/****************************************************************************** + * @file VK_RZ_A1H.h + * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version V1.00 + * @data 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __VK_RZ_A1H_H__ +#define __VK_RZ_A1H_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/****** SGI Interrupts Numbers ****************************************/ + SGI0_IRQn = 0, + SGI1_IRQn = 1, + SGI2_IRQn = 2, + SGI3_IRQn = 3, + SGI4_IRQn = 4, + SGI5_IRQn = 5, + SGI6_IRQn = 6, + SGI7_IRQn = 7, + SGI8_IRQn = 8, + SGI9_IRQn = 9, + SGI10_IRQn = 10, + SGI11_IRQn = 11, + SGI12_IRQn = 12, + SGI13_IRQn = 13, + SGI14_IRQn = 14, + SGI15_IRQn = 15, + +/****** Cortex-A9 Processor Exceptions Numbers ****************************************/ + /* 16 - 578 */ + PMUIRQ0_IRQn = 16, + COMMRX0_IRQn = 17, + COMMTX0_IRQn = 18, + CTIIRQ0_IRQn = 19, + + IRQ0_IRQn = 32, + IRQ1_IRQn = 33, + IRQ2_IRQn = 34, + IRQ3_IRQn = 35, + IRQ4_IRQn = 36, + IRQ5_IRQn = 37, + IRQ6_IRQn = 38, + IRQ7_IRQn = 39, + + PL310ERR_IRQn = 40, + + DMAINT0_IRQn = 41, /*!< DMAC Interrupt */ + DMAINT1_IRQn = 42, /*!< DMAC Interrupt */ + DMAINT2_IRQn = 43, /*!< DMAC Interrupt */ + DMAINT3_IRQn = 44, /*!< DMAC Interrupt */ + DMAINT4_IRQn = 45, /*!< DMAC Interrupt */ + DMAINT5_IRQn = 46, /*!< DMAC Interrupt */ + DMAINT6_IRQn = 47, /*!< DMAC Interrupt */ + DMAINT7_IRQn = 48, /*!< DMAC Interrupt */ + DMAINT8_IRQn = 49, /*!< DMAC Interrupt */ + DMAINT9_IRQn = 50, /*!< DMAC Interrupt */ + DMAINT10_IRQn = 51, /*!< DMAC Interrupt */ + DMAINT11_IRQn = 52, /*!< DMAC Interrupt */ + DMAINT12_IRQn = 53, /*!< DMAC Interrupt */ + DMAINT13_IRQn = 54, /*!< DMAC Interrupt */ + DMAINT14_IRQn = 55, /*!< DMAC Interrupt */ + DMAINT15_IRQn = 56, /*!< DMAC Interrupt */ + DMAERR_IRQn = 57, /*!< DMAC Interrupt */ + + /* 58-72 Reserved */ + + USBI0_IRQn = 73, + USBI1_IRQn = 74, + + S0_VI_VSYNC0_IRQn = 75, + S0_LO_VSYNC0_IRQn = 76, + S0_VSYNCERR0_IRQn = 77, + GR3_VLINE0_IRQn = 78, + S0_VFIELD0_IRQn = 79, + IV1_VBUFERR0_IRQn = 80, + IV3_VBUFERR0_IRQn = 81, + IV5_VBUFERR0_IRQn = 82, + IV6_VBUFERR0_IRQn = 83, + S0_WLINE0_IRQn = 84, + S1_VI_VSYNC0_IRQn = 85, + S1_LO_VSYNC0_IRQn = 86, + S1_VSYNCERR0_IRQn = 87, + S1_VFIELD0_IRQn = 88, + IV2_VBUFERR0_IRQn = 89, + IV4_VBUFERR0_IRQn = 90, + S1_WLINE0_IRQn = 91, + OIR_VI_VSYNC0_IRQn = 92, + OIR_LO_VSYNC0_IRQn = 93, + OIR_VSYNCERR0_IRQn = 94, + OIR_VFIELD0_IRQn = 95, + IV7_VBUFERR0_IRQn = 96, + IV8_VBUFERR0_IRQn = 97, + /* 98 Reserved */ + S0_VI_VSYNC1_IRQn = 99, + S0_LO_VSYNC1_IRQn = 100, + S0_VSYNCERR1_IRQn = 101, + GR3_VLINE1_IRQn = 102, + S0_VFIELD1_IRQn = 103, + IV1_VBUFERR1_IRQn = 104, + IV3_VBUFERR1_IRQn = 105, + IV5_VBUFERR1_IRQn = 106, + IV6_VBUFERR1_IRQn = 107, + S0_WLINE1_IRQn = 108, + S1_VI_VSYNC1_IRQn = 109, + S1_LO_VSYNC1_IRQn = 110, + S1_VSYNCERR1_IRQn = 111, + S1_VFIELD1_IRQn = 112, + IV2_VBUFERR1_IRQn = 113, + IV4_VBUFERR1_IRQn = 114, + S1_WLINE1_IRQn = 115, + OIR_VI_VSYNC1_IRQn = 116, + OIR_LO_VSYNC1_IRQn = 117, + OIR_VSYNCERR1_IRQn = 118, + OIR_VFIELD1_IRQn = 119, + IV7_VBUFERR1_IRQn = 120, + IV8_VBUFERR1_IRQn = 121, + /* Reserved = 122 */ + + IMRDI_IRQn = 123, + IMR2I0_IRQn = 124, + IMR2I1_IRQn = 125, + + JEDI_IRQn = 126, + JDTI_IRQn = 127, + + CMP0_IRQn = 128, + CMP1_IRQn = 129, + + INT0_IRQn = 130, + INT1_IRQn = 131, + INT2_IRQn = 132, + INT3_IRQn = 133, + + OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */ + OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */ + + CMI_IRQn = 136, + WTOUT_IRQn = 137, + + ITI_IRQn = 138, + + TGI0A_IRQn = 139, + TGI0B_IRQn = 140, + TGI0C_IRQn = 141, + TGI0D_IRQn = 142, + TGI0V_IRQn = 143, + TGI0E_IRQn = 144, + TGI0F_IRQn = 145, + TGI1A_IRQn = 146, + TGI1B_IRQn = 147, + TGI1V_IRQn = 148, + TGI1U_IRQn = 149, + TGI2A_IRQn = 150, + TGI2B_IRQn = 151, + TGI2V_IRQn = 152, + TGI2U_IRQn = 153, + TGI3A_IRQn = 154, + TGI3B_IRQn = 155, + TGI3C_IRQn = 156, + TGI3D_IRQn = 157, + TGI3V_IRQn = 158, + TGI4A_IRQn = 159, + TGI4B_IRQn = 160, + TGI4C_IRQn = 161, + TGI4D_IRQn = 162, + TGI4V_IRQn = 163, + + CMI1_IRQn = 164, + CMI2_IRQn = 165, + + SGDEI0_IRQn = 166, + SGDEI1_IRQn = 167, + SGDEI2_IRQn = 168, + SGDEI3_IRQn = 169, + + ADI_IRQn = 170, + LMTI_IRQn = 171, + + SSII0_IRQn = 172, /*!< SSIF Interrupt */ + SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */ + SSITXI0_IRQn = 174, /*!< SSIF Interrupt */ + SSII1_IRQn = 175, /*!< SSIF Interrupt */ + SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */ + SSITXI1_IRQn = 177, /*!< SSIF Interrupt */ + SSII2_IRQn = 178, /*!< SSIF Interrupt */ + SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */ + SSII3_IRQn = 180, /*!< SSIF Interrupt */ + SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */ + SSITXI3_IRQn = 182, /*!< SSIF Interrupt */ + SSII4_IRQn = 183, /*!< SSIF Interrupt */ + SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */ + SSII5_IRQn = 185, /*!< SSIF Interrupt */ + SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */ + SSITXI5_IRQn = 187, /*!< SSIF Interrupt */ + + SPDIFI_IRQn = 188, + + INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */ + INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */ + INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */ + INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */ + INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */ + INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */ + INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */ + INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */ + INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */ + INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */ + INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */ + INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */ + INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */ + INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */ + INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */ + INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */ + INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */ + INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */ + INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */ + INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */ + INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */ + INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */ + INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */ + INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */ + INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */ + INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */ + INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */ + INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */ + INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */ + INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */ + INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */ + INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */ + + SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */ + SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */ + SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */ + SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */ + SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */ + SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */ + SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */ + SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */ + SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */ + SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */ + SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */ + SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */ + SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */ + SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */ + SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */ + SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */ + SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */ + SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */ + SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */ + SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */ + SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */ + SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */ + SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */ + SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */ + SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */ + SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */ + SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */ + SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */ + SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */ + SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */ + SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */ + SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */ + + INTRCANGERR_IRQn = 253, + INTRCANGRECC_IRQn = 254, + INTRCAN0REC_IRQn = 255, + INTRCAN0ERR_IRQn = 256, + INTRCAN0TRX_IRQn = 257, + INTRCAN1REC_IRQn = 258, + INTRCAN1ERR_IRQn = 259, + INTRCAN1TRX_IRQn = 260, + INTRCAN2REC_IRQn = 261, + INTRCAN2ERR_IRQn = 262, + INTRCAN2TRX_IRQn = 263, + INTRCAN3REC_IRQn = 264, + INTRCAN3ERR_IRQn = 265, + INTRCAN3TRX_IRQn = 266, + INTRCAN4REC_IRQn = 267, + INTRCAN4ERR_IRQn = 268, + INTRCAN4TRX_IRQn = 269, + + RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */ + RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */ + RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */ + RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */ + RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */ + RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */ + RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */ + RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */ + RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */ + RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */ + RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */ + RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */ + RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */ + RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */ + RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */ + + IEBBTD_IRQn = 285, + IEBBTERR_IRQn = 286, + IEBBTSTA_IRQn = 287, + IEBBTV_IRQn = 288, + + ISY_IRQn = 289, + IERR_IRQn = 290, + ITARG_IRQn = 291, + ISEC_IRQn = 292, + IBUF_IRQn = 293, + IREADY_IRQn = 294, + + STERB_IRQn = 295, + FLTENDI_IRQn = 296, + FLTREQ0I_IRQn = 297, + FLTREQ1I_IRQn = 298, + + MMC0_IRQn = 299, + MMC1_IRQn = 300, + MMC2_IRQn = 301, + + SCHI0_3_IRQn = 302, + SDHI0_0_IRQn = 303, + SDHI0_1_IRQn = 304, + SCHI1_3_IRQn = 305, + SDHI1_0_IRQn = 306, + SDHI1_1_IRQn = 307, + + ARM_IRQn = 308, + PRD_IRQn = 309, + CUP_IRQn = 310, + + SCUAI0_IRQn = 311, + SCUAI1_IRQn = 312, + SCUFDI0_IRQn = 313, + SCUFDI1_IRQn = 314, + SCUFDI2_IRQn = 315, + SCUFDI3_IRQn = 316, + SCUFUI0_IRQn = 317, + SCUFUI1_IRQn = 318, + SCUFUI2_IRQn = 319, + SCUFUI3_IRQn = 320, + SCUDVI0_IRQn = 321, + SCUDVI1_IRQn = 322, + SCUDVI2_IRQn = 323, + SCUDVI3_IRQn = 324, + + MLB_CINT_IRQn = 325, + MLB_SINT_IRQn = 326, + + DRC10_IRQn = 327, + DRC11_IRQn = 328, + + /* 329-330 Reserved */ + + LINI0_INT_T_IRQn = 331, + LINI0_INT_R_IRQn = 332, + LINI0_INT_S_IRQn = 333, + LINI0_INT_M_IRQn = 334, + LINI1_INT_T_IRQn = 335, + LINI1_INT_R_IRQn = 336, + LINI1_INT_S_IRQn = 337, + LINI1_INT_M_IRQn = 338, + + /* 339-346 Reserved */ + + SCIERI0_IRQn = 347, + SCIRXI0_IRQn = 348, + SCITXI0_IRQn = 349, + SCITEI0_IRQn = 350, + SCIERI1_IRQn = 351, + SCIRXI1_IRQn = 352, + SCITXI1_IRQn = 353, + SCITEI1_IRQn = 354, + + AVBI_DATA = 355, + AVBI_ERROR = 356, + AVBI_MANAGE = 357, + AVBI_MAC = 358, + + ETHERI_IRQn = 359, + + /* 360-363 Reserved */ + + CEUI_IRQn = 364, + + /* 365-380 Reserved */ + + H2XMLB_ERRINT_IRQn = 381, + H2XIC1_ERRINT_IRQn = 382, + X2HPERI1_ERRINT_IRQn = 383, + X2HPERR2_ERRINT_IRQn = 384, + X2HPERR34_ERRINT_IRQn= 385, + X2HPERR5_ERRINT_IRQn = 386, + X2HPERR67_ERRINT_IRQn= 387, + X2HDBGR_ERRINT_IRQn = 388, + X2HBSC_ERRINT_IRQn = 389, + X2HSPI1_ERRINT_IRQn = 390, + X2HSPI2_ERRINT_IRQn = 391, + PRRI_IRQn = 392, + + IFEI0_IRQn = 393, + OFFI0_IRQn = 394, + PFVEI0_IRQn = 395, + IFEI1_IRQn = 396, + OFFI1_IRQn = 397, + PFVEI1_IRQn = 398, + + /* 399-415 Reserved */ + + TINT0_IRQn = 416, + TINT1_IRQn = 417, + TINT2_IRQn = 418, + TINT3_IRQn = 419, + TINT4_IRQn = 420, + TINT5_IRQn = 421, + TINT6_IRQn = 422, + TINT7_IRQn = 423, + TINT8_IRQn = 424, + TINT9_IRQn = 425, + TINT10_IRQn = 426, + TINT11_IRQn = 427, + TINT12_IRQn = 428, + TINT13_IRQn = 429, + TINT14_IRQn = 430, + TINT15_IRQn = 431, + TINT16_IRQn = 432, + TINT17_IRQn = 433, + TINT18_IRQn = 434, + TINT19_IRQn = 435, + TINT20_IRQn = 436, + TINT21_IRQn = 437, + TINT22_IRQn = 438, + TINT23_IRQn = 439, + TINT24_IRQn = 440, + TINT25_IRQn = 441, + TINT26_IRQn = 442, + TINT27_IRQn = 443, + TINT28_IRQn = 444, + TINT29_IRQn = 445, + TINT30_IRQn = 446, + TINT31_IRQn = 447, + TINT32_IRQn = 448, + TINT33_IRQn = 449, + TINT34_IRQn = 450, + TINT35_IRQn = 451, + TINT36_IRQn = 452, + TINT37_IRQn = 453, + TINT38_IRQn = 454, + TINT39_IRQn = 455, + TINT40_IRQn = 456, + TINT41_IRQn = 457, + TINT42_IRQn = 458, + TINT43_IRQn = 459, + TINT44_IRQn = 460, + TINT45_IRQn = 461, + TINT46_IRQn = 462, + TINT47_IRQn = 463, + TINT48_IRQn = 464, + TINT49_IRQn = 465, + TINT50_IRQn = 466, + TINT51_IRQn = 467, + TINT52_IRQn = 468, + TINT53_IRQn = 469, + TINT54_IRQn = 470, + TINT55_IRQn = 471, + TINT56_IRQn = 472, + TINT57_IRQn = 473, + TINT58_IRQn = 474, + TINT59_IRQn = 475, + TINT60_IRQn = 476, + TINT61_IRQn = 477, + TINT62_IRQn = 478, + TINT63_IRQn = 479, + TINT64_IRQn = 480, + TINT65_IRQn = 481, + TINT66_IRQn = 482, + TINT67_IRQn = 483, + TINT68_IRQn = 484, + TINT69_IRQn = 485, + TINT70_IRQn = 486, + TINT71_IRQn = 487, + TINT72_IRQn = 488, + TINT73_IRQn = 489, + TINT74_IRQn = 490, + TINT75_IRQn = 491, + TINT76_IRQn = 492, + TINT77_IRQn = 493, + TINT78_IRQn = 494, + TINT79_IRQn = 495, + TINT80_IRQn = 496, + TINT81_IRQn = 497, + TINT82_IRQn = 498, + TINT83_IRQn = 499, + TINT84_IRQn = 500, + TINT85_IRQn = 501, + TINT86_IRQn = 502, + TINT87_IRQn = 503, + TINT88_IRQn = 504, + TINT89_IRQn = 505, + TINT90_IRQn = 506, + TINT91_IRQn = 507, + TINT92_IRQn = 508, + TINT93_IRQn = 509, + TINT94_IRQn = 510, + TINT95_IRQn = 511, + TINT96_IRQn = 512, + TINT97_IRQn = 513, + TINT98_IRQn = 514, + TINT99_IRQn = 515, + TINT100_IRQn = 516, + TINT101_IRQn = 517, + TINT102_IRQn = 518, + TINT103_IRQn = 519, + TINT104_IRQn = 520, + TINT105_IRQn = 521, + TINT106_IRQn = 522, + TINT107_IRQn = 523, + TINT108_IRQn = 524, + TINT109_IRQn = 525, + TINT110_IRQn = 526, + TINT111_IRQn = 527, + TINT112_IRQn = 528, + TINT113_IRQn = 529, + TINT114_IRQn = 530, + TINT115_IRQn = 531, + TINT116_IRQn = 532, + TINT117_IRQn = 533, + TINT118_IRQn = 534, + TINT119_IRQn = 535, + TINT120_IRQn = 536, + TINT121_IRQn = 537, + TINT122_IRQn = 538, + TINT123_IRQn = 539, + TINT124_IRQn = 540, + TINT125_IRQn = 541, + TINT126_IRQn = 542, + TINT127_IRQn = 543, + TINT128_IRQn = 544, + TINT129_IRQn = 545, + TINT130_IRQn = 546, + TINT131_IRQn = 547, + TINT132_IRQn = 548, + TINT133_IRQn = 549, + TINT134_IRQn = 550, + TINT135_IRQn = 551, + TINT136_IRQn = 552, + TINT137_IRQn = 553, + TINT138_IRQn = 554, + TINT139_IRQn = 555, + TINT140_IRQn = 556, + TINT141_IRQn = 557, + TINT142_IRQn = 558, + TINT143_IRQn = 559, + TINT144_IRQn = 560, + TINT145_IRQn = 561, + TINT146_IRQn = 562, + TINT147_IRQn = 563, + TINT148_IRQn = 564, + TINT149_IRQn = 565, + TINT150_IRQn = 566, + TINT151_IRQn = 567, + TINT152_IRQn = 568, + TINT153_IRQn = 569, + TINT154_IRQn = 570, + TINT155_IRQn = 571, + TINT156_IRQn = 572, + TINT157_IRQn = 573, + TINT158_IRQn = 574, + TINT159_IRQn = 575, + TINT160_IRQn = 576, + TINT161_IRQn = 577, + TINT162_IRQn = 578, + TINT163_IRQn = 579, + TINT164_IRQn = 580, + TINT165_IRQn = 581, + TINT166_IRQn = 582, + TINT167_IRQn = 583, + TINT168_IRQn = 584, + TINT169_IRQn = 585, + TINT170_IRQn = 586 + +} IRQn_Type; + +#define RZ_A1_IRQ_MAX TINT170_IRQn + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ + +#define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ +#define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ +#define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ +#define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ +#define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ +#define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ +#define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ +#define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ +#define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ +#define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ +#define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ +#define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ +#define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ +#define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ +#define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ +#define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ +#define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ +#define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */ +#define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE +#define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE +#define L2C_310_BASE RZ_A1_PL310_BASE +#define TIMER_BASE RZ_A1_PRIVATE_TIMER + +/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ +#define __CA_REV 0x0000U /*!< Core revision r0p0 */ +#define __CORTEX_A 9U /*!< Cortex-A9 Core */ +#if (__FPU_PRESENT != 1) +#undef __FPU_PRESENT +#define __FPU_PRESENT 1U /* FPU present */ +#endif +#define __GIC_PRESENT 1U /* GIC present */ +#define __TIM_PRESENT 0U /* TIM present */ +#define __L2C_PRESENT 1U /* L2C present */ + +#include "core_ca.h" +#include "nvic_wrapper.h" +#include +#include "iodefine.h" + +/******************************************************************************/ +/* Clock Settings */ +/******************************************************************************/ +/* + * Clock Mode 0 settings + * SW1-4(MD_CLK):ON + * SW1-5(MD_CLKS):ON + * FRQCR=0x1035 + * CLKEN2 = 0b - unstable + * CLKEN[1:0]=01b - Output, Low, Low + * IFC[1:0] =00b - CPU clock is 1/1 PLL clock + * FRQCR2=0x0001 + * GFC[1:0] =01b - Graphic clock is 2/3 bus clock + */ +#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u) +#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u) +#define CM0_RENESAS_RZ_A1_I_CLK (400000000u) +#define CM0_RENESAS_RZ_A1_G_CLK (266666666u) +#define CM0_RENESAS_RZ_A1_B_CLK (133333333u) +#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u) +#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) + +/* + * Clock Mode 1 settings + * SW1-4(MD_CLK):OFF + * SW1-5(MD_CLKS):ON + * FRQCR=0x1335 + * CLKEN2 = 0b - unstable + * CLKEN[1:0]=01b - Output, Low, Low + * IFC[1:0] =11b - CPU clock is 1/3 PLL clock + * FRQCR2=0x0003 + * GFC[1:0] =11b - graphic clock is 1/3 bus clock + */ +#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u) +#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u) +#define CM1_RENESAS_RZ_A1_I_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_G_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_B_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) +#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) + +/******************************************************************************/ +/* CPG Settings */ +/******************************************************************************/ +#define CPG_FRQCR_SHIFT_CKOEN2 (14) +#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) +#define CPG_FRQCR_SHIFT_CKOEN0 (12) +#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) +#define CPG_FRQCR_SHIFT_IFC (8) +#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) + +#define CPG_FRQCR2_SHIFT_GFC (0) +#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) + + +#define CPG_STBCR1_BIT_STBY (0x80u) +#define CPG_STBCR1_BIT_DEEP (0x40u) +#define CPG_STBCR2_BIT_HIZ (0x80u) +#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ +#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ +#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ +#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ +#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ +#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ +#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ +#define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */ +#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ +#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ +#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ +#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ +#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ +#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ +#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ +#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ +#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ +#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ +#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ +#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ +#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ +#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ +#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ +#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ +#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ +#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */ +#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ +#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ +#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ +#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */ +#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */ +#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ +#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ +#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ +#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ +#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */ +#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ +#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ +#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ +#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ +#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ +#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ +#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ +#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ +#define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */ +#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ +#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ +#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ +#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ +#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ +#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ +#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ +#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ +#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ +#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ +#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ +#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ +#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ +#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ +#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ +#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ +#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ +#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ +#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ +#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ +#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ +#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ +#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ +#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ +#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ +#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ +#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ +#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */ +#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */ +#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ +#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ +#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ +#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ +#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ +#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ +#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ +#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ +#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ +#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ +#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ +#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ +#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ +#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ +#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ +#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ +#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ +#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ +#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ +#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ +#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ +#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ +#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ +#define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */ +#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */ +#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */ +#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */ +#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */ +#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */ +#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */ +#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */ +#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */ +#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */ +#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */ +#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */ +#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */ +#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */ +#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */ +#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */ +#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */ +#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */ +#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */ +#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */ +#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */ +#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */ +#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */ +#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */ +#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */ +#define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */ +#define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */ +#define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */ +#define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */ +#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */ +#define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */ +#define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */ +#define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */ +#define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */ +#define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */ +#define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */ +#define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */ +#define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */ +#define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */ +#define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */ +#define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */ +#define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */ +#define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */ +#define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */ +#define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */ +#define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */ +#define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */ +#define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */ +#define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */ +#define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */ +#define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */ +#define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */ +#define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */ +#define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */ +#define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */ +#define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */ +#define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */ +#define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */ +#define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */ +#define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */ +#define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */ +#define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */ +#define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */ +#define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */ +#define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */ +#define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */ +#define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */ +#define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */ +#define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */ +#define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */ +#define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */ +#define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */ +#define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */ +#define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */ +#define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */ + +/******************************************************************************/ +/* GPIO Settings */ +/******************************************************************************/ +#define GPIO_BIT_N0 (1u << 0) +#define GPIO_BIT_N1 (1u << 1) +#define GPIO_BIT_N2 (1u << 2) +#define GPIO_BIT_N3 (1u << 3) +#define GPIO_BIT_N4 (1u << 4) +#define GPIO_BIT_N5 (1u << 5) +#define GPIO_BIT_N6 (1u << 6) +#define GPIO_BIT_N7 (1u << 7) +#define GPIO_BIT_N8 (1u << 8) +#define GPIO_BIT_N9 (1u << 9) +#define GPIO_BIT_N10 (1u << 10) +#define GPIO_BIT_N11 (1u << 11) +#define GPIO_BIT_N12 (1u << 12) +#define GPIO_BIT_N13 (1u << 13) +#define GPIO_BIT_N14 (1u << 14) +#define GPIO_BIT_N15 (1u << 15) + +#define MD_BOOT10_MASK (0x3) + +#define MD_BOOT10_BM0 (0x0) +#define MD_BOOT10_BM1 (0x2) +#define MD_BOOT10_BM3 (0x1) +#define MD_BOOT10_BM4_5 (0x3) + +#define MD_CLK (1u << 2) +#define MD_CLKS (1u << 3) + + +#ifdef __cplusplus +} +#endif + +#endif // __VK_RZ_A1H_H__ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h index 2d18559982..d01d74b0e6 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h @@ -18,119 +18,56 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ -#ifndef R7S72100_IODEFINE_H -#define R7S72100_IODEFINE_H -#define IODEFINE_H_VERSION 100 +#ifndef R7S721000_IODEFINE_H +#define R7S721000_IODEFINE_H -enum iodefine_byte_select_t -{ - L = 0, H = 1, - LL= 0, LH = 1, HL = 2, HH = 3 -}; +#include "iodefines/iodefine_typedef.h" /* (V2.00h) */ -/*********************************************************************** - <<< [iodefine_reg32_t] >>> -- Padding : sizeof(iodefine_reg32_t) == 4 -- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 -- &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3 -- Endian : Independent (Same as CPU endian as register endian) -- Bit-Order : Independent -************************************************************************/ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ -union iodefine_reg32_t -{ - volatile uint32_t UINT32; /* 32-bit Access */ - volatile uint16_t UINT16[2]; /* 16-bit Access */ - volatile uint8_t UINT8[4]; /* 8-bit Access */ -}; -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ - -/*********************************************************************** - <<< [iodefine_reg32_16_t] >>> -- Padding : sizeof(iodefine_reg32_16_t) == 4 -- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 -- Endian : Independent (Same as CPU endian as register endian) -- Bit-Order : Independent -************************************************************************/ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ -union iodefine_reg32_16_t -{ - volatile uint32_t UINT32; /* 32-bit Access */ - volatile uint16_t UINT16[2]; /* 16-bit Access */ -}; -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ - -/*********************************************************************** - <<< [iodefine_reg16_8_t] >>> -- Padding : sizeof(iodefine_reg16_8_t) == 2 -- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1 -- Endian : Independent (Same as CPU endian as register endian) -- Bit-Order : Independent -************************************************************************/ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ -union iodefine_reg16_8_t -{ - volatile uint16_t UINT16; /* 16-bit Access */ - volatile uint8_t UINT8[2]; /* 8-bit Access */ -}; -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ - - - - - - -#include "adc_iodefine.h" /* (V1.00a) */ -#include "bsc_iodefine.h" /* (V1.00a) */ -#include "ceu_iodefine.h" /* (V1.00a) */ -#include "cpg_iodefine.h" /* (V1.00a) */ -#include "disc_iodefine.h" /* (V1.00a) */ -#include "dmac_iodefine.h" /* (V1.00a) */ -#include "dvdec_iodefine.h" /* (V1.00a) */ -#include "ether_iodefine.h" /* (V1.00a) */ -#include "flctl_iodefine.h" /* (V1.00a) */ -#include "gpio_iodefine.h" /* (V1.00a) */ -#include "ieb_iodefine.h" /* (V1.00a) */ -#include "inb_iodefine.h" /* (V1.00a) */ -#include "intc_iodefine.h" /* (V1.00a) */ -#include "irda_iodefine.h" /* (V1.00a) */ -#include "jcu_iodefine.h" /* (V1.00a) */ -#include "l2c_iodefine.h" /* (V1.00a) */ -#include "lin_iodefine.h" /* (V1.00a) */ -#include "lvds_iodefine.h" /* (V1.00a) */ -#include "mlb_iodefine.h" /* (V1.00a) */ -#include "mmc_iodefine.h" /* (V1.00a) */ -#include "mtu2_iodefine.h" /* (V1.00a) */ -#include "ostm_iodefine.h" /* (V1.00a) */ -#include "pfv_iodefine.h" /* (V1.00a) */ -#include "pwm_iodefine.h" /* (V1.00a) */ -#include "riic_iodefine.h" /* (V1.00a) */ -#include "romdec_iodefine.h" /* (V1.00a) */ -#include "rscan0_iodefine.h" /* (V1.00a) */ -#include "rspi_iodefine.h" /* (V1.00a) */ -#include "rtc_iodefine.h" /* (V1.00a) */ -#include "scif_iodefine.h" /* (V1.00a) */ -#include "scim_iodefine.h" /* (V1.00a) */ -#include "scux_iodefine.h" /* (V1.00a) */ -#include "sdg_iodefine.h" /* (V1.00a) */ -#include "spdif_iodefine.h" /* (V1.00a) */ -#include "spibsc_iodefine.h" /* (V1.00a) */ -#include "ssif_iodefine.h" /* (V1.00a) */ -#include "usb20_iodefine.h" /* (V1.00a) */ -#include "vdc5_iodefine.h" /* (V1.00a) */ -#include "wdt_iodefine.h" /* (V1.00a) */ +#include "iodefines/adc_iodefine.h" /* (V2.00h) */ +#include "iodefines/bsc_iodefine.h" /* (V2.00h) */ +#include "iodefines/ceu_iodefine.h" /* (V2.00h) */ +#include "iodefines/cpg_iodefine.h" /* (V2.00h) */ +#include "iodefines/disc_iodefine.h" /* (V2.00h) */ +#include "iodefines/dmac_iodefine.h" /* (V2.00h) */ +#include "iodefines/dvdec_iodefine.h" /* (V2.00h) */ +#include "iodefines/ether_iodefine.h" /* (V2.00h) */ +#include "iodefines/flctl_iodefine.h" /* (V2.00h) */ +#include "iodefines/gpio_iodefine.h" /* (V2.00h) */ +#include "iodefines/ieb_iodefine.h" /* (V2.00h) */ +#include "iodefines/inb_iodefine.h" /* (V2.00h) */ +#include "iodefines/intc_iodefine.h" /* (V2.00h) */ +#include "iodefines/irda_iodefine.h" /* (V2.00h) */ +#include "iodefines/jcu_iodefine.h" /* (V2.00h) */ +#include "iodefines/l2c_iodefine.h" /* (V2.00h) */ +#include "iodefines/lin_iodefine.h" /* (V2.00h) */ +#include "iodefines/lvds_iodefine.h" /* (V2.00h) */ +#include "iodefines/mlb_iodefine.h" /* (V2.00h) */ +#include "iodefines/mmc_iodefine.h" /* (V2.00h) */ +#include "iodefines/mtu2_iodefine.h" /* (V2.00h) */ +#include "iodefines/ostm_iodefine.h" /* (V2.00h) */ +#include "iodefines/pfv_iodefine.h" /* (V2.00h) */ +#include "iodefines/pwm_iodefine.h" /* (V2.00h) */ +#include "iodefines/riic_iodefine.h" /* (V2.00h) */ +#include "iodefines/romdec_iodefine.h" /* (V2.00h) */ +#include "iodefines/rscan0_iodefine.h" /* (V2.00h) */ +#include "iodefines/rspi_iodefine.h" /* (V2.00h) */ +#include "iodefines/rtc_iodefine.h" /* (V2.00h) */ +#include "iodefines/scif_iodefine.h" /* (V2.00h) */ +#include "iodefines/scim_iodefine.h" /* (V2.00h) */ +#include "iodefines/scux_iodefine.h" /* (V2.00h) */ +#include "iodefines/sdg_iodefine.h" /* (V2.00h) */ +#include "iodefines/spdif_iodefine.h" /* (V2.00h) */ +#include "iodefines/spibsc_iodefine.h" /* (V2.00h) */ +#include "iodefines/ssif_iodefine.h" /* (V2.00h) */ +#include "iodefines/usb20_iodefine.h" /* (V2.00h) */ +#include "iodefines/vdc5_iodefine.h" /* (V2.00h) */ +#include "iodefines/wdt_iodefine.h" /* (V2.00h) */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h index 55bc7ddd26..a16183efcc 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h @@ -18,20 +18,56 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : adc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef ADC_IODEFINE_H #define ADC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_adc -{ /* ADC */ +#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */ + + +#define ADCADDRA (ADC.ADDRA) +#define ADCADDRB (ADC.ADDRB) +#define ADCADDRC (ADC.ADDRC) +#define ADCADDRD (ADC.ADDRD) +#define ADCADDRE (ADC.ADDRE) +#define ADCADDRF (ADC.ADDRF) +#define ADCADDRG (ADC.ADDRG) +#define ADCADDRH (ADC.ADDRH) +#define ADCADCMPHA (ADC.ADCMPHA) +#define ADCADCMPLA (ADC.ADCMPLA) +#define ADCADCMPHB (ADC.ADCMPHB) +#define ADCADCMPLB (ADC.ADCMPLB) +#define ADCADCMPHC (ADC.ADCMPHC) +#define ADCADCMPLC (ADC.ADCMPLC) +#define ADCADCMPHD (ADC.ADCMPHD) +#define ADCADCMPLD (ADC.ADCMPLD) +#define ADCADCMPHE (ADC.ADCMPHE) +#define ADCADCMPLE (ADC.ADCMPLE) +#define ADCADCMPHF (ADC.ADCMPHF) +#define ADCADCMPLF (ADC.ADCMPLF) +#define ADCADCMPHG (ADC.ADCMPHG) +#define ADCADCMPLG (ADC.ADCMPLG) +#define ADCADCMPHH (ADC.ADCMPHH) +#define ADCADCMPLH (ADC.ADCMPLH) +#define ADCADCSR (ADC.ADCSR) +#define ADCADCMPER (ADC.ADCMPER) +#define ADCADCMPSR (ADC.ADCMPSR) + + +typedef struct st_adc +{ + /* ADC */ volatile uint16_t ADDRA; /* ADDRA */ volatile uint16_t ADDRB; /* ADDRB */ volatile uint16_t ADDRC; /* ADDRC */ @@ -61,38 +97,11 @@ struct st_adc volatile uint16_t ADCSR; /* ADCSR */ volatile uint16_t ADCMPER; /* ADCMPER */ volatile uint16_t ADCMPSR; /* ADCMPSR */ -}; +} r_io_adc_t; -#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */ - - -#define ADCADDRA ADC.ADDRA -#define ADCADDRB ADC.ADDRB -#define ADCADDRC ADC.ADDRC -#define ADCADDRD ADC.ADDRD -#define ADCADDRE ADC.ADDRE -#define ADCADDRF ADC.ADDRF -#define ADCADDRG ADC.ADDRG -#define ADCADDRH ADC.ADDRH -#define ADCADCMPHA ADC.ADCMPHA -#define ADCADCMPLA ADC.ADCMPLA -#define ADCADCMPHB ADC.ADCMPHB -#define ADCADCMPLB ADC.ADCMPLB -#define ADCADCMPHC ADC.ADCMPHC -#define ADCADCMPLC ADC.ADCMPLC -#define ADCADCMPHD ADC.ADCMPHD -#define ADCADCMPLD ADC.ADCMPLD -#define ADCADCMPHE ADC.ADCMPHE -#define ADCADCMPLE ADC.ADCMPLE -#define ADCADCMPHF ADC.ADCMPHF -#define ADCADCMPLF ADC.ADCMPLF -#define ADCADCMPHG ADC.ADCMPHG -#define ADCADCMPLG ADC.ADCMPLG -#define ADCADCMPHH ADC.ADCMPHH -#define ADCADCMPLH ADC.ADCMPLH -#define ADCADCSR ADC.ADCSR -#define ADCADCMPER ADC.ADCMPER -#define ADCADCMPSR ADC.ADCMPSR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h index 0d327ac760..6665787ee7 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h @@ -18,22 +18,61 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : bsc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef BSC_IODEFINE_H #define BSC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_bsc -{ /* BSC */ +#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ + + +#define BSCCMNCR (BSC.CMNCR) +#define BSCCS0BCR (BSC.CS0BCR) +#define BSCCS1BCR (BSC.CS1BCR) +#define BSCCS2BCR (BSC.CS2BCR) +#define BSCCS3BCR (BSC.CS3BCR) +#define BSCCS4BCR (BSC.CS4BCR) +#define BSCCS5BCR (BSC.CS5BCR) +#define BSCCS0WCR (BSC.CS0WCR) +#define BSCCS1WCR (BSC.CS1WCR) +#define BSCCS2WCR (BSC.CS2WCR) +#define BSCCS3WCR (BSC.CS3WCR) +#define BSCCS4WCR (BSC.CS4WCR) +#define BSCCS5WCR (BSC.CS5WCR) +#define BSCSDCR (BSC.SDCR) +#define BSCRTCSR (BSC.RTCSR) +#define BSCRTCNT (BSC.RTCNT) +#define BSCRTCOR (BSC.RTCOR) +#define BSCTOSCOR0 (BSC.TOSCOR0) +#define BSCTOSCOR1 (BSC.TOSCOR1) +#define BSCTOSCOR2 (BSC.TOSCOR2) +#define BSCTOSCOR3 (BSC.TOSCOR3) +#define BSCTOSCOR4 (BSC.TOSCOR4) +#define BSCTOSCOR5 (BSC.TOSCOR5) +#define BSCTOSTR (BSC.TOSTR) +#define BSCTOENR (BSC.TOENR) + +#define BSC_CSnBCR_COUNT (6) +#define BSC_CSnWCR_COUNT (6) +#define BSC_TOSCORn_COUNT (6) + + +typedef struct st_bsc +{ + /* BSC */ volatile uint32_t CMNCR; /* CMNCR */ -#define BSC_CSnBCR_COUNT 6 + +/* #define BSC_CSnBCR_COUNT (6) */ volatile uint32_t CS0BCR; /* CS0BCR */ volatile uint32_t CS1BCR; /* CS1BCR */ volatile uint32_t CS2BCR; /* CS2BCR */ @@ -41,7 +80,8 @@ struct st_bsc volatile uint32_t CS4BCR; /* CS4BCR */ volatile uint32_t CS5BCR; /* CS5BCR */ volatile uint8_t dummy4[12]; /* */ -#define BSC_CSnWCR_COUNT 6 + +/* #define BSC_CSnWCR_COUNT (6) */ volatile uint32_t CS0WCR; /* CS0WCR */ volatile uint32_t CS1WCR; /* CS1WCR */ volatile uint32_t CS2WCR; /* CS2WCR */ @@ -54,7 +94,8 @@ struct st_bsc volatile uint32_t RTCNT; /* RTCNT */ volatile uint32_t RTCOR; /* RTCOR */ volatile uint8_t dummy6[4]; /* */ -#define BSC_TOSCORn_COUNT 6 + +/* #define BSC_TOSCORn_COUNT (6) */ volatile uint32_t TOSCOR0; /* TOSCOR0 */ volatile uint32_t TOSCOR1; /* TOSCOR1 */ volatile uint32_t TOSCOR2; /* TOSCOR2 */ @@ -64,36 +105,11 @@ struct st_bsc volatile uint8_t dummy7[8]; /* */ volatile uint32_t TOSTR; /* TOSTR */ volatile uint32_t TOENR; /* TOENR */ -}; +} r_io_bsc_t; -#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ - - -#define BSCCMNCR BSC.CMNCR -#define BSCCS0BCR BSC.CS0BCR -#define BSCCS1BCR BSC.CS1BCR -#define BSCCS2BCR BSC.CS2BCR -#define BSCCS3BCR BSC.CS3BCR -#define BSCCS4BCR BSC.CS4BCR -#define BSCCS5BCR BSC.CS5BCR -#define BSCCS0WCR BSC.CS0WCR -#define BSCCS1WCR BSC.CS1WCR -#define BSCCS2WCR BSC.CS2WCR -#define BSCCS3WCR BSC.CS3WCR -#define BSCCS4WCR BSC.CS4WCR -#define BSCCS5WCR BSC.CS5WCR -#define BSCSDCR BSC.SDCR -#define BSCRTCSR BSC.RTCSR -#define BSCRTCNT BSC.RTCNT -#define BSCRTCOR BSC.RTCOR -#define BSCTOSCOR0 BSC.TOSCOR0 -#define BSCTOSCOR1 BSC.TOSCOR1 -#define BSCTOSCOR2 BSC.TOSCOR2 -#define BSCTOSCOR3 BSC.TOSCOR3 -#define BSCTOSCOR4 BSC.TOSCOR4 -#define BSCTOSCOR5 BSC.TOSCOR5 -#define BSCTOSTR BSC.TOSTR -#define BSCTOENR BSC.TOENR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h index 535b18bed0..a970bfd807 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h @@ -18,20 +18,108 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ceu_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef CEU_IODEFINE_H #define CEU_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ceu -{ /* CEU */ +#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ + + +/* Start of channel array defines of CEU */ + +/* Channel array defines of CEUn */ +/*(Sample) value = CEUn[ channel ]->CAMOR; */ +#define CEUn_COUNT (3) +#define CEUn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + (volatile struct st_ceu_n*)&CEU_A, \ + (volatile struct st_ceu_n*)&CEU_B, \ + (volatile struct st_ceu_n*)&CEU_M \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ +#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ +#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ + +/* End of channel array defines of CEU */ + + +#define CEUCAPSR (CEU.CAPSR) +#define CEUCAPCR (CEU.CAPCR) +#define CEUCAMCR (CEU.CAMCR) +#define CEUCMCYR (CEU.CMCYR) +#define CEUCAMOR_A (CEU.CAMOR_A) +#define CEUCAPWR_A (CEU.CAPWR_A) +#define CEUCAIFR (CEU.CAIFR) +#define CEUCRCNTR (CEU.CRCNTR) +#define CEUCRCMPR (CEU.CRCMPR) +#define CEUCFLCR_A (CEU.CFLCR_A) +#define CEUCFSZR_A (CEU.CFSZR_A) +#define CEUCDWDR_A (CEU.CDWDR_A) +#define CEUCDAYR_A (CEU.CDAYR_A) +#define CEUCDACR_A (CEU.CDACR_A) +#define CEUCDBYR_A (CEU.CDBYR_A) +#define CEUCDBCR_A (CEU.CDBCR_A) +#define CEUCBDSR_A (CEU.CBDSR_A) +#define CEUCFWCR (CEU.CFWCR) +#define CEUCLFCR_A (CEU.CLFCR_A) +#define CEUCDOCR_A (CEU.CDOCR_A) +#define CEUCEIER (CEU.CEIER) +#define CEUCETCR (CEU.CETCR) +#define CEUCSTSR (CEU.CSTSR) +#define CEUCDSSR (CEU.CDSSR) +#define CEUCDAYR2_A (CEU.CDAYR2_A) +#define CEUCDACR2_A (CEU.CDACR2_A) +#define CEUCDBYR2_A (CEU.CDBYR2_A) +#define CEUCDBCR2_A (CEU.CDBCR2_A) +#define CEUCAMOR_B (CEU.CAMOR_B) +#define CEUCAPWR_B (CEU.CAPWR_B) +#define CEUCFLCR_B (CEU.CFLCR_B) +#define CEUCFSZR_B (CEU.CFSZR_B) +#define CEUCDWDR_B (CEU.CDWDR_B) +#define CEUCDAYR_B (CEU.CDAYR_B) +#define CEUCDACR_B (CEU.CDACR_B) +#define CEUCDBYR_B (CEU.CDBYR_B) +#define CEUCDBCR_B (CEU.CDBCR_B) +#define CEUCBDSR_B (CEU.CBDSR_B) +#define CEUCLFCR_B (CEU.CLFCR_B) +#define CEUCDOCR_B (CEU.CDOCR_B) +#define CEUCDAYR2_B (CEU.CDAYR2_B) +#define CEUCDACR2_B (CEU.CDACR2_B) +#define CEUCDBYR2_B (CEU.CDBYR2_B) +#define CEUCDBCR2_B (CEU.CDBCR2_B) +#define CEUCAMOR_M (CEU.CAMOR_M) +#define CEUCAPWR_M (CEU.CAPWR_M) +#define CEUCFLCR_M (CEU.CFLCR_M) +#define CEUCFSZR_M (CEU.CFSZR_M) +#define CEUCDWDR_M (CEU.CDWDR_M) +#define CEUCDAYR_M (CEU.CDAYR_M) +#define CEUCDACR_M (CEU.CDACR_M) +#define CEUCDBYR_M (CEU.CDBYR_M) +#define CEUCDBCR_M (CEU.CDBCR_M) +#define CEUCBDSR_M (CEU.CBDSR_M) +#define CEUCLFCR_M (CEU.CLFCR_M) +#define CEUCDOCR_M (CEU.CDOCR_M) +#define CEUCDAYR2_M (CEU.CDAYR2_M) +#define CEUCDACR2_M (CEU.CDACR2_M) +#define CEUCDBYR2_M (CEU.CDBYR2_M) +#define CEUCDBCR2_M (CEU.CDBCR2_M) + + +typedef struct st_ceu +{ + /* CEU */ + /* start of struct st_ceu_n */ volatile uint32_t CAPSR; /* CAPSR */ volatile uint32_t CAPCR; /* CAPCR */ @@ -67,8 +155,10 @@ struct st_ceu volatile uint32_t CDACR2_A; /* CDACR2_A */ volatile uint32_t CDBYR2_A; /* CDBYR2_A */ volatile uint32_t CDBCR2_A; /* CDBCR2_A */ + /* end of struct st_ceu_n */ volatile uint8_t dummy3110[3936]; /* */ + /* start of struct st_ceu_n */ volatile uint8_t dummy3111[4]; /* */ volatile uint8_t dummy3112[4]; /* */ @@ -104,8 +194,10 @@ struct st_ceu volatile uint32_t CDACR2_B; /* CDACR2_B */ volatile uint32_t CDBYR2_B; /* CDBYR2_B */ volatile uint32_t CDBCR2_B; /* CDBCR2_B */ + /* end of struct st_ceu_n */ volatile uint8_t dummy3150[3936]; /* */ + /* start of struct st_ceu_n */ volatile uint8_t dummy3151[4]; /* */ volatile uint8_t dummy3152[4]; /* */ @@ -141,12 +233,14 @@ struct st_ceu volatile uint32_t CDACR2_M; /* CDACR2_M */ volatile uint32_t CDBYR2_M; /* CDBYR2_M */ volatile uint32_t CDBCR2_M; /* CDBCR2_M */ + /* end of struct st_ceu_n */ -}; +} r_io_ceu_t; -struct st_ceu_n +typedef struct st_ceu_n { + volatile uint32_t not_common1; /* */ volatile uint32_t not_common2; /* */ volatile uint32_t not_common3; /* */ @@ -181,89 +275,21 @@ struct st_ceu_n volatile uint32_t CDACR2; /* CDACR2 */ volatile uint32_t CDBYR2; /* CDBYR2 */ volatile uint32_t CDBCR2; /* CDBCR2 */ -}; +} r_io_ceu_n_t; -#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ +/* Channel array defines of CEUn (2)*/ +#ifdef DECLARE_CEUn_CHANNELS +volatile struct st_ceu_n* CEUn[ CEUn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CEUn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CEUn_CHANNELS */ +/* End of channel array defines of CEUn (2)*/ -/* Start of channnel array defines of CEU */ - -/* Channnel array defines of CEUn */ -/*(Sample) value = CEUn[ channel ]->CAMOR; */ -#define CEUn_COUNT 3 -#define CEUn_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - (volatile struct st_ceu_n*)&CEU_A, \ - (volatile struct st_ceu_n*)&CEU_B, \ - (volatile struct st_ceu_n*)&CEU_M \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ -#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ -#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ - -/* End of channnel array defines of CEU */ - - -#define CEUCAPSR CEU.CAPSR -#define CEUCAPCR CEU.CAPCR -#define CEUCAMCR CEU.CAMCR -#define CEUCMCYR CEU.CMCYR -#define CEUCAMOR_A CEU.CAMOR_A -#define CEUCAPWR_A CEU.CAPWR_A -#define CEUCAIFR CEU.CAIFR -#define CEUCRCNTR CEU.CRCNTR -#define CEUCRCMPR CEU.CRCMPR -#define CEUCFLCR_A CEU.CFLCR_A -#define CEUCFSZR_A CEU.CFSZR_A -#define CEUCDWDR_A CEU.CDWDR_A -#define CEUCDAYR_A CEU.CDAYR_A -#define CEUCDACR_A CEU.CDACR_A -#define CEUCDBYR_A CEU.CDBYR_A -#define CEUCDBCR_A CEU.CDBCR_A -#define CEUCBDSR_A CEU.CBDSR_A -#define CEUCFWCR CEU.CFWCR -#define CEUCLFCR_A CEU.CLFCR_A -#define CEUCDOCR_A CEU.CDOCR_A -#define CEUCEIER CEU.CEIER -#define CEUCETCR CEU.CETCR -#define CEUCSTSR CEU.CSTSR -#define CEUCDSSR CEU.CDSSR -#define CEUCDAYR2_A CEU.CDAYR2_A -#define CEUCDACR2_A CEU.CDACR2_A -#define CEUCDBYR2_A CEU.CDBYR2_A -#define CEUCDBCR2_A CEU.CDBCR2_A -#define CEUCAMOR_B CEU.CAMOR_B -#define CEUCAPWR_B CEU.CAPWR_B -#define CEUCFLCR_B CEU.CFLCR_B -#define CEUCFSZR_B CEU.CFSZR_B -#define CEUCDWDR_B CEU.CDWDR_B -#define CEUCDAYR_B CEU.CDAYR_B -#define CEUCDACR_B CEU.CDACR_B -#define CEUCDBYR_B CEU.CDBYR_B -#define CEUCDBCR_B CEU.CDBCR_B -#define CEUCBDSR_B CEU.CBDSR_B -#define CEUCLFCR_B CEU.CLFCR_B -#define CEUCDOCR_B CEU.CDOCR_B -#define CEUCDAYR2_B CEU.CDAYR2_B -#define CEUCDACR2_B CEU.CDACR2_B -#define CEUCDBYR2_B CEU.CDBYR2_B -#define CEUCDBCR2_B CEU.CDBCR2_B -#define CEUCAMOR_M CEU.CAMOR_M -#define CEUCAPWR_M CEU.CAPWR_M -#define CEUCFLCR_M CEU.CFLCR_M -#define CEUCFSZR_M CEU.CFSZR_M -#define CEUCDWDR_M CEU.CDWDR_M -#define CEUCDAYR_M CEU.CDAYR_M -#define CEUCDACR_M CEU.CDACR_M -#define CEUCDBYR_M CEU.CDBYR_M -#define CEUCDBCR_M CEU.CDBCR_M -#define CEUCBDSR_M CEU.CBDSR_M -#define CEUCLFCR_M CEU.CLFCR_M -#define CEUCDOCR_M CEU.CDOCR_M -#define CEUCDAYR2_M CEU.CDAYR2_M -#define CEUCDACR2_M CEU.CDACR2_M -#define CEUCDBYR2_M CEU.CDBYR2_M -#define CEUCDBCR2_M CEU.CDBCR2_M /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h index 5fc9890ff5..6260ad010e 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h @@ -18,20 +18,109 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : cpg_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef CPG_IODEFINE_H #define CPG_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_cpg -{ /* CPG */ +#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */ + + +/* Start of channel array defines of CPG */ + +/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */ +#define CPG_FROM_SWRSTCR1_ARRAY_COUNT (3) +#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */ +#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */ +#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */ + + +/* Channel array defines of CPG_FROM_STBCR3_ARRAY */ +/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */ +#define CPG_FROM_STBCR3_ARRAY_COUNT (10) +#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \ + &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */ +#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */ +#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */ +#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */ +#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */ +#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */ +#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */ +#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */ +#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */ +#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */ + + +/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */ +#define CPG_FROM_SYSCR1_ARRAY_COUNT (3) +#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */ +#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */ +#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */ + +/* End of channel array defines of CPG */ + + +#define CPGFRQCR (CPG.FRQCR) +#define CPGFRQCR2 (CPG.FRQCR2) +#define CPGCPUSTS (CPG.CPUSTS) +#define CPGSTBCR1 (CPG.STBCR1) +#define CPGSTBCR2 (CPG.STBCR2) +#define CPGSTBREQ1 (CPG.STBREQ1) +#define CPGSTBREQ2 (CPG.STBREQ2) +#define CPGSTBACK1 (CPG.STBACK1) +#define CPGSTBACK2 (CPG.STBACK2) +#define CPGSYSCR1 (CPG.SYSCR1) +#define CPGSYSCR2 (CPG.SYSCR2) +#define CPGSYSCR3 (CPG.SYSCR3) +#define CPGSTBCR3 (CPG.STBCR3) +#define CPGSTBCR4 (CPG.STBCR4) +#define CPGSTBCR5 (CPG.STBCR5) +#define CPGSTBCR6 (CPG.STBCR6) +#define CPGSTBCR7 (CPG.STBCR7) +#define CPGSTBCR8 (CPG.STBCR8) +#define CPGSTBCR9 (CPG.STBCR9) +#define CPGSTBCR10 (CPG.STBCR10) +#define CPGSTBCR11 (CPG.STBCR11) +#define CPGSTBCR12 (CPG.STBCR12) +#define CPGSWRSTCR1 (CPG.SWRSTCR1) +#define CPGSWRSTCR2 (CPG.SWRSTCR2) +#define CPGSWRSTCR3 (CPG.SWRSTCR3) +#define CPGSTBCR13 (CPG.STBCR13) +#define CPGRRAMKP (CPG.RRAMKP) +#define CPGDSCTR (CPG.DSCTR) +#define CPGDSSSR (CPG.DSSSR) +#define CPGDSESR (CPG.DSESR) +#define CPGDSFR (CPG.DSFR) +#define CPGXTALCTR (CPG.XTALCTR) + + +typedef struct st_cpg +{ + /* CPG */ volatile uint16_t FRQCR; /* FRQCR */ volatile uint8_t dummy319[2]; /* */ volatile uint16_t FRQCR2; /* FRQCR2 */ @@ -50,71 +139,103 @@ struct st_cpg volatile uint8_t dummy326[3]; /* */ volatile uint8_t STBACK2; /* STBACK2 */ volatile uint8_t dummy327[955]; /* */ + /* start of struct st_cpg_from_syscr1 */ volatile uint8_t SYSCR1; /* SYSCR1 */ volatile uint8_t dummy328[3]; /* */ + /* end of struct st_cpg_from_syscr1 */ + /* start of struct st_cpg_from_syscr1 */ volatile uint8_t SYSCR2; /* SYSCR2 */ volatile uint8_t dummy329[3]; /* */ + /* end of struct st_cpg_from_syscr1 */ + /* start of struct st_cpg_from_syscr1 */ volatile uint8_t SYSCR3; /* SYSCR3 */ volatile uint8_t dummy3300[3]; /* */ + /* end of struct st_cpg_from_syscr1 */ volatile uint8_t dummy3301[20]; /* */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR3; /* STBCR3 */ volatile uint8_t dummy331[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR4; /* STBCR4 */ volatile uint8_t dummy332[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR5; /* STBCR5 */ volatile uint8_t dummy333[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR6; /* STBCR6 */ volatile uint8_t dummy334[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR7; /* STBCR7 */ volatile uint8_t dummy335[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR8; /* STBCR8 */ volatile uint8_t dummy336[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR9; /* STBCR9 */ volatile uint8_t dummy337[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR10; /* STBCR10 */ volatile uint8_t dummy338[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR11; /* STBCR11 */ volatile uint8_t dummy339[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR12; /* STBCR12 */ volatile uint8_t dummy3400[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ volatile uint8_t dummy3401[24]; /* */ + /* start of struct st_cpg_from_swrstcr1 */ volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ volatile uint8_t dummy341[3]; /* */ + /* end of struct st_cpg_from_swrstcr1 */ + /* start of struct st_cpg_from_swrstcr1 */ volatile uint8_t SWRSTCR2; /* SWRSTCR2 */ volatile uint8_t dummy342[3]; /* */ + /* end of struct st_cpg_from_swrstcr1 */ + /* start of struct st_cpg_from_swrstcr1 */ volatile uint8_t SWRSTCR3; /* SWRSTCR3 */ volatile uint8_t dummy3430[3]; /* */ + /* end of struct st_cpg_from_swrstcr1 */ volatile uint8_t dummy3431[4]; /* */ volatile uint8_t STBCR13; /* STBCR13 */ @@ -128,112 +249,59 @@ struct st_cpg volatile uint16_t DSFR; /* DSFR */ volatile uint8_t dummy347[6]; /* */ volatile uint8_t XTALCTR; /* XTALCTR */ -}; +} r_io_cpg_t; -struct st_cpg_from_syscr1 +typedef struct st_cpg_from_syscr1 { + volatile uint8_t SYSCR1; /* SYSCR1 */ volatile uint8_t dummy1[3]; /* */ -}; +} r_io_cpg_from_syscr1_t; -struct st_cpg_from_stbcr3 +typedef struct st_cpg_from_stbcr3 { + volatile uint8_t STBCR3; /* STBCR3 */ volatile uint8_t dummy1[3]; /* */ -}; +} r_io_cpg_from_stbcr3_t; -struct st_cpg_from_swrstcr1 +typedef struct st_cpg_from_swrstcr1 { + volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ volatile uint8_t dummy1[3]; /* */ -}; +} r_io_cpg_from_swrstcr1_t; -#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */ +/* Channel array defines of CPG (2)*/ +#ifdef DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS +volatile struct st_cpg_from_swrstcr1* CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */ + +#ifdef DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS +volatile struct st_cpg_from_stbcr3* CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */ + +#ifdef DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS +volatile struct st_cpg_from_syscr1* CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */ +/* End of channel array defines of CPG (2)*/ -/* Start of channnel array defines of CPG */ - -/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */ -/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */ -#define CPG_FROM_SWRSTCR1_ARRAY_COUNT 3 -#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */ -#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */ -#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */ - - -/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */ -/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */ -#define CPG_FROM_STBCR3_ARRAY_COUNT 10 -#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \ - &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */ -#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */ -#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */ -#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */ -#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */ -#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */ -#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */ -#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */ -#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */ -#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */ - - -/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */ -/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */ -#define CPG_FROM_SYSCR1_ARRAY_COUNT 3 -#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */ -#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */ -#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */ - -/* End of channnel array defines of CPG */ - - -#define CPGFRQCR CPG.FRQCR -#define CPGFRQCR2 CPG.FRQCR2 -#define CPGCPUSTS CPG.CPUSTS -#define CPGSTBCR1 CPG.STBCR1 -#define CPGSTBCR2 CPG.STBCR2 -#define CPGSTBREQ1 CPG.STBREQ1 -#define CPGSTBREQ2 CPG.STBREQ2 -#define CPGSTBACK1 CPG.STBACK1 -#define CPGSTBACK2 CPG.STBACK2 -#define CPGSYSCR1 CPG.SYSCR1 -#define CPGSYSCR2 CPG.SYSCR2 -#define CPGSYSCR3 CPG.SYSCR3 -#define CPGSTBCR3 CPG.STBCR3 -#define CPGSTBCR4 CPG.STBCR4 -#define CPGSTBCR5 CPG.STBCR5 -#define CPGSTBCR6 CPG.STBCR6 -#define CPGSTBCR7 CPG.STBCR7 -#define CPGSTBCR8 CPG.STBCR8 -#define CPGSTBCR9 CPG.STBCR9 -#define CPGSTBCR10 CPG.STBCR10 -#define CPGSTBCR11 CPG.STBCR11 -#define CPGSTBCR12 CPG.STBCR12 -#define CPGSWRSTCR1 CPG.SWRSTCR1 -#define CPGSWRSTCR2 CPG.SWRSTCR2 -#define CPGSWRSTCR3 CPG.SWRSTCR3 -#define CPGSTBCR13 CPG.STBCR13 -#define CPGRRAMKP CPG.RRAMKP -#define CPGDSCTR CPG.DSCTR -#define CPGDSSSR CPG.DSSSR -#define CPGDSESR CPG.DSESR -#define CPGDSFR CPG.DSFR -#define CPGXTALCTR CPG.XTALCTR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h index 8844fa2afb..dd2abd5e75 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h @@ -18,20 +18,67 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : disc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef DISC_IODEFINE_H #define DISC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_disc -{ /* DISC */ +#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */ +#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */ + + +/* Start of channel array defines of DISC */ + +/* Channel array defines of DISC */ +/*(Sample) value = DISC[ channel ]->DOCMCR; */ +#define DISC_COUNT (2) +#define DISC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DISC0, &DISC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of DISC */ + + +#define DISC0DOCMCR (DISC0.DOCMCR) +#define DISC0DOCMSTR (DISC0.DOCMSTR) +#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR) +#define DISC0DOCMIENR (DISC0.DOCMIENR) +#define DISC0DOCMPMR (DISC0.DOCMPMR) +#define DISC0DOCMECRCR (DISC0.DOCMECRCR) +#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR) +#define DISC0DOCMSPXR (DISC0.DOCMSPXR) +#define DISC0DOCMSPYR (DISC0.DOCMSPYR) +#define DISC0DOCMSZXR (DISC0.DOCMSZXR) +#define DISC0DOCMSZYR (DISC0.DOCMSZYR) +#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR) +#define DISC1DOCMCR (DISC1.DOCMCR) +#define DISC1DOCMSTR (DISC1.DOCMSTR) +#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR) +#define DISC1DOCMIENR (DISC1.DOCMIENR) +#define DISC1DOCMPMR (DISC1.DOCMPMR) +#define DISC1DOCMECRCR (DISC1.DOCMECRCR) +#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR) +#define DISC1DOCMSPXR (DISC1.DOCMSPXR) +#define DISC1DOCMSPYR (DISC1.DOCMSPYR) +#define DISC1DOCMSZXR (DISC1.DOCMSZXR) +#define DISC1DOCMSZYR (DISC1.DOCMSZYR) +#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR) + + +typedef struct st_disc +{ + /* DISC */ volatile uint32_t DOCMCR; /* DOCMCR */ volatile uint32_t DOCMSTR; /* DOCMSTR */ volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */ @@ -45,49 +92,21 @@ struct st_disc volatile uint32_t DOCMSZXR; /* DOCMSZXR */ volatile uint32_t DOCMSZYR; /* DOCMSZYR */ volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */ -}; +} r_io_disc_t; -#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */ -#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */ +/* Channel array defines of DISC (2)*/ +#ifdef DECLARE_DISC_CHANNELS +volatile struct st_disc* DISC[ DISC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DISC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DISC_CHANNELS */ +/* End of channel array defines of DISC (2)*/ -/* Start of channnel array defines of DISC */ - -/* Channnel array defines of DISC */ -/*(Sample) value = DISC[ channel ]->DOCMCR; */ -#define DISC_COUNT 2 -#define DISC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DISC0, &DISC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of DISC */ - - -#define DISC0DOCMCR DISC0.DOCMCR -#define DISC0DOCMSTR DISC0.DOCMSTR -#define DISC0DOCMCLSTR DISC0.DOCMCLSTR -#define DISC0DOCMIENR DISC0.DOCMIENR -#define DISC0DOCMPMR DISC0.DOCMPMR -#define DISC0DOCMECRCR DISC0.DOCMECRCR -#define DISC0DOCMCCRCR DISC0.DOCMCCRCR -#define DISC0DOCMSPXR DISC0.DOCMSPXR -#define DISC0DOCMSPYR DISC0.DOCMSPYR -#define DISC0DOCMSZXR DISC0.DOCMSZXR -#define DISC0DOCMSZYR DISC0.DOCMSZYR -#define DISC0DOCMCRCIR DISC0.DOCMCRCIR -#define DISC1DOCMCR DISC1.DOCMCR -#define DISC1DOCMSTR DISC1.DOCMSTR -#define DISC1DOCMCLSTR DISC1.DOCMCLSTR -#define DISC1DOCMIENR DISC1.DOCMIENR -#define DISC1DOCMPMR DISC1.DOCMPMR -#define DISC1DOCMECRCR DISC1.DOCMECRCR -#define DISC1DOCMCCRCR DISC1.DOCMCCRCR -#define DISC1DOCMSPXR DISC1.DOCMSPXR -#define DISC1DOCMSPYR DISC1.DOCMSPYR -#define DISC1DOCMSZXR DISC1.DOCMSZXR -#define DISC1DOCMSZYR DISC1.DOCMSZYR -#define DISC1DOCMCRCIR DISC1.DOCMCRCIR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h index 0faf27fbe0..a6d6865f86 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h @@ -18,383 +18,48 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : dmac_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef DMAC_IODEFINE_H #define DMAC_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_dmac -{ /* DMAC */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_0; /* N0SA_0 */ - volatile uint32_t N0DA_0; /* N0DA_0 */ - volatile uint32_t N0TB_0; /* N0TB_0 */ - volatile uint32_t N1SA_0; /* N1SA_0 */ - volatile uint32_t N1DA_0; /* N1DA_0 */ - volatile uint32_t N1TB_0; /* N1TB_0 */ - volatile uint32_t CRSA_0; /* CRSA_0 */ - volatile uint32_t CRDA_0; /* CRDA_0 */ - volatile uint32_t CRTB_0; /* CRTB_0 */ - volatile uint32_t CHSTAT_0; /* CHSTAT_0 */ - volatile uint32_t CHCTRL_0; /* CHCTRL_0 */ - volatile uint32_t CHCFG_0; /* CHCFG_0 */ - volatile uint32_t CHITVL_0; /* CHITVL_0 */ - volatile uint32_t CHEXT_0; /* CHEXT_0 */ - volatile uint32_t NXLA_0; /* NXLA_0 */ - volatile uint32_t CRLA_0; /* CRLA_0 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_1; /* N0SA_1 */ - volatile uint32_t N0DA_1; /* N0DA_1 */ - volatile uint32_t N0TB_1; /* N0TB_1 */ - volatile uint32_t N1SA_1; /* N1SA_1 */ - volatile uint32_t N1DA_1; /* N1DA_1 */ - volatile uint32_t N1TB_1; /* N1TB_1 */ - volatile uint32_t CRSA_1; /* CRSA_1 */ - volatile uint32_t CRDA_1; /* CRDA_1 */ - volatile uint32_t CRTB_1; /* CRTB_1 */ - volatile uint32_t CHSTAT_1; /* CHSTAT_1 */ - volatile uint32_t CHCTRL_1; /* CHCTRL_1 */ - volatile uint32_t CHCFG_1; /* CHCFG_1 */ - volatile uint32_t CHITVL_1; /* CHITVL_1 */ - volatile uint32_t CHEXT_1; /* CHEXT_1 */ - volatile uint32_t NXLA_1; /* NXLA_1 */ - volatile uint32_t CRLA_1; /* CRLA_1 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_2; /* N0SA_2 */ - volatile uint32_t N0DA_2; /* N0DA_2 */ - volatile uint32_t N0TB_2; /* N0TB_2 */ - volatile uint32_t N1SA_2; /* N1SA_2 */ - volatile uint32_t N1DA_2; /* N1DA_2 */ - volatile uint32_t N1TB_2; /* N1TB_2 */ - volatile uint32_t CRSA_2; /* CRSA_2 */ - volatile uint32_t CRDA_2; /* CRDA_2 */ - volatile uint32_t CRTB_2; /* CRTB_2 */ - volatile uint32_t CHSTAT_2; /* CHSTAT_2 */ - volatile uint32_t CHCTRL_2; /* CHCTRL_2 */ - volatile uint32_t CHCFG_2; /* CHCFG_2 */ - volatile uint32_t CHITVL_2; /* CHITVL_2 */ - volatile uint32_t CHEXT_2; /* CHEXT_2 */ - volatile uint32_t NXLA_2; /* NXLA_2 */ - volatile uint32_t CRLA_2; /* CRLA_2 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_3; /* N0SA_3 */ - volatile uint32_t N0DA_3; /* N0DA_3 */ - volatile uint32_t N0TB_3; /* N0TB_3 */ - volatile uint32_t N1SA_3; /* N1SA_3 */ - volatile uint32_t N1DA_3; /* N1DA_3 */ - volatile uint32_t N1TB_3; /* N1TB_3 */ - volatile uint32_t CRSA_3; /* CRSA_3 */ - volatile uint32_t CRDA_3; /* CRDA_3 */ - volatile uint32_t CRTB_3; /* CRTB_3 */ - volatile uint32_t CHSTAT_3; /* CHSTAT_3 */ - volatile uint32_t CHCTRL_3; /* CHCTRL_3 */ - volatile uint32_t CHCFG_3; /* CHCFG_3 */ - volatile uint32_t CHITVL_3; /* CHITVL_3 */ - volatile uint32_t CHEXT_3; /* CHEXT_3 */ - volatile uint32_t NXLA_3; /* NXLA_3 */ - volatile uint32_t CRLA_3; /* CRLA_3 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_4; /* N0SA_4 */ - volatile uint32_t N0DA_4; /* N0DA_4 */ - volatile uint32_t N0TB_4; /* N0TB_4 */ - volatile uint32_t N1SA_4; /* N1SA_4 */ - volatile uint32_t N1DA_4; /* N1DA_4 */ - volatile uint32_t N1TB_4; /* N1TB_4 */ - volatile uint32_t CRSA_4; /* CRSA_4 */ - volatile uint32_t CRDA_4; /* CRDA_4 */ - volatile uint32_t CRTB_4; /* CRTB_4 */ - volatile uint32_t CHSTAT_4; /* CHSTAT_4 */ - volatile uint32_t CHCTRL_4; /* CHCTRL_4 */ - volatile uint32_t CHCFG_4; /* CHCFG_4 */ - volatile uint32_t CHITVL_4; /* CHITVL_4 */ - volatile uint32_t CHEXT_4; /* CHEXT_4 */ - volatile uint32_t NXLA_4; /* NXLA_4 */ - volatile uint32_t CRLA_4; /* CRLA_4 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_5; /* N0SA_5 */ - volatile uint32_t N0DA_5; /* N0DA_5 */ - volatile uint32_t N0TB_5; /* N0TB_5 */ - volatile uint32_t N1SA_5; /* N1SA_5 */ - volatile uint32_t N1DA_5; /* N1DA_5 */ - volatile uint32_t N1TB_5; /* N1TB_5 */ - volatile uint32_t CRSA_5; /* CRSA_5 */ - volatile uint32_t CRDA_5; /* CRDA_5 */ - volatile uint32_t CRTB_5; /* CRTB_5 */ - volatile uint32_t CHSTAT_5; /* CHSTAT_5 */ - volatile uint32_t CHCTRL_5; /* CHCTRL_5 */ - volatile uint32_t CHCFG_5; /* CHCFG_5 */ - volatile uint32_t CHITVL_5; /* CHITVL_5 */ - volatile uint32_t CHEXT_5; /* CHEXT_5 */ - volatile uint32_t NXLA_5; /* NXLA_5 */ - volatile uint32_t CRLA_5; /* CRLA_5 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_6; /* N0SA_6 */ - volatile uint32_t N0DA_6; /* N0DA_6 */ - volatile uint32_t N0TB_6; /* N0TB_6 */ - volatile uint32_t N1SA_6; /* N1SA_6 */ - volatile uint32_t N1DA_6; /* N1DA_6 */ - volatile uint32_t N1TB_6; /* N1TB_6 */ - volatile uint32_t CRSA_6; /* CRSA_6 */ - volatile uint32_t CRDA_6; /* CRDA_6 */ - volatile uint32_t CRTB_6; /* CRTB_6 */ - volatile uint32_t CHSTAT_6; /* CHSTAT_6 */ - volatile uint32_t CHCTRL_6; /* CHCTRL_6 */ - volatile uint32_t CHCFG_6; /* CHCFG_6 */ - volatile uint32_t CHITVL_6; /* CHITVL_6 */ - volatile uint32_t CHEXT_6; /* CHEXT_6 */ - volatile uint32_t NXLA_6; /* NXLA_6 */ - volatile uint32_t CRLA_6; /* CRLA_6 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_7; /* N0SA_7 */ - volatile uint32_t N0DA_7; /* N0DA_7 */ - volatile uint32_t N0TB_7; /* N0TB_7 */ - volatile uint32_t N1SA_7; /* N1SA_7 */ - volatile uint32_t N1DA_7; /* N1DA_7 */ - volatile uint32_t N1TB_7; /* N1TB_7 */ - volatile uint32_t CRSA_7; /* CRSA_7 */ - volatile uint32_t CRDA_7; /* CRDA_7 */ - volatile uint32_t CRTB_7; /* CRTB_7 */ - volatile uint32_t CHSTAT_7; /* CHSTAT_7 */ - volatile uint32_t CHCTRL_7; /* CHCTRL_7 */ - volatile uint32_t CHCFG_7; /* CHCFG_7 */ - volatile uint32_t CHITVL_7; /* CHITVL_7 */ - volatile uint32_t CHEXT_7; /* CHEXT_7 */ - volatile uint32_t NXLA_7; /* NXLA_7 */ - volatile uint32_t CRLA_7; /* CRLA_7 */ -/* end of struct st_dmac_n */ - volatile uint8_t dummy187[256]; /* */ -/* start of struct st_dmaccommon_n */ - volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ - volatile uint8_t dummy188[12]; /* */ - volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ - volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ - volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ - volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ - volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ -/* end of struct st_dmaccommon_n */ - volatile uint8_t dummy189[220]; /* */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_8; /* N0SA_8 */ - volatile uint32_t N0DA_8; /* N0DA_8 */ - volatile uint32_t N0TB_8; /* N0TB_8 */ - volatile uint32_t N1SA_8; /* N1SA_8 */ - volatile uint32_t N1DA_8; /* N1DA_8 */ - volatile uint32_t N1TB_8; /* N1TB_8 */ - volatile uint32_t CRSA_8; /* CRSA_8 */ - volatile uint32_t CRDA_8; /* CRDA_8 */ - volatile uint32_t CRTB_8; /* CRTB_8 */ - volatile uint32_t CHSTAT_8; /* CHSTAT_8 */ - volatile uint32_t CHCTRL_8; /* CHCTRL_8 */ - volatile uint32_t CHCFG_8; /* CHCFG_8 */ - volatile uint32_t CHITVL_8; /* CHITVL_8 */ - volatile uint32_t CHEXT_8; /* CHEXT_8 */ - volatile uint32_t NXLA_8; /* NXLA_8 */ - volatile uint32_t CRLA_8; /* CRLA_8 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_9; /* N0SA_9 */ - volatile uint32_t N0DA_9; /* N0DA_9 */ - volatile uint32_t N0TB_9; /* N0TB_9 */ - volatile uint32_t N1SA_9; /* N1SA_9 */ - volatile uint32_t N1DA_9; /* N1DA_9 */ - volatile uint32_t N1TB_9; /* N1TB_9 */ - volatile uint32_t CRSA_9; /* CRSA_9 */ - volatile uint32_t CRDA_9; /* CRDA_9 */ - volatile uint32_t CRTB_9; /* CRTB_9 */ - volatile uint32_t CHSTAT_9; /* CHSTAT_9 */ - volatile uint32_t CHCTRL_9; /* CHCTRL_9 */ - volatile uint32_t CHCFG_9; /* CHCFG_9 */ - volatile uint32_t CHITVL_9; /* CHITVL_9 */ - volatile uint32_t CHEXT_9; /* CHEXT_9 */ - volatile uint32_t NXLA_9; /* NXLA_9 */ - volatile uint32_t CRLA_9; /* CRLA_9 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_10; /* N0SA_10 */ - volatile uint32_t N0DA_10; /* N0DA_10 */ - volatile uint32_t N0TB_10; /* N0TB_10 */ - volatile uint32_t N1SA_10; /* N1SA_10 */ - volatile uint32_t N1DA_10; /* N1DA_10 */ - volatile uint32_t N1TB_10; /* N1TB_10 */ - volatile uint32_t CRSA_10; /* CRSA_10 */ - volatile uint32_t CRDA_10; /* CRDA_10 */ - volatile uint32_t CRTB_10; /* CRTB_10 */ - volatile uint32_t CHSTAT_10; /* CHSTAT_10 */ - volatile uint32_t CHCTRL_10; /* CHCTRL_10 */ - volatile uint32_t CHCFG_10; /* CHCFG_10 */ - volatile uint32_t CHITVL_10; /* CHITVL_10 */ - volatile uint32_t CHEXT_10; /* CHEXT_10 */ - volatile uint32_t NXLA_10; /* NXLA_10 */ - volatile uint32_t CRLA_10; /* CRLA_10 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_11; /* N0SA_11 */ - volatile uint32_t N0DA_11; /* N0DA_11 */ - volatile uint32_t N0TB_11; /* N0TB_11 */ - volatile uint32_t N1SA_11; /* N1SA_11 */ - volatile uint32_t N1DA_11; /* N1DA_11 */ - volatile uint32_t N1TB_11; /* N1TB_11 */ - volatile uint32_t CRSA_11; /* CRSA_11 */ - volatile uint32_t CRDA_11; /* CRDA_11 */ - volatile uint32_t CRTB_11; /* CRTB_11 */ - volatile uint32_t CHSTAT_11; /* CHSTAT_11 */ - volatile uint32_t CHCTRL_11; /* CHCTRL_11 */ - volatile uint32_t CHCFG_11; /* CHCFG_11 */ - volatile uint32_t CHITVL_11; /* CHITVL_11 */ - volatile uint32_t CHEXT_11; /* CHEXT_11 */ - volatile uint32_t NXLA_11; /* NXLA_11 */ - volatile uint32_t CRLA_11; /* CRLA_11 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_12; /* N0SA_12 */ - volatile uint32_t N0DA_12; /* N0DA_12 */ - volatile uint32_t N0TB_12; /* N0TB_12 */ - volatile uint32_t N1SA_12; /* N1SA_12 */ - volatile uint32_t N1DA_12; /* N1DA_12 */ - volatile uint32_t N1TB_12; /* N1TB_12 */ - volatile uint32_t CRSA_12; /* CRSA_12 */ - volatile uint32_t CRDA_12; /* CRDA_12 */ - volatile uint32_t CRTB_12; /* CRTB_12 */ - volatile uint32_t CHSTAT_12; /* CHSTAT_12 */ - volatile uint32_t CHCTRL_12; /* CHCTRL_12 */ - volatile uint32_t CHCFG_12; /* CHCFG_12 */ - volatile uint32_t CHITVL_12; /* CHITVL_12 */ - volatile uint32_t CHEXT_12; /* CHEXT_12 */ - volatile uint32_t NXLA_12; /* NXLA_12 */ - volatile uint32_t CRLA_12; /* CRLA_12 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_13; /* N0SA_13 */ - volatile uint32_t N0DA_13; /* N0DA_13 */ - volatile uint32_t N0TB_13; /* N0TB_13 */ - volatile uint32_t N1SA_13; /* N1SA_13 */ - volatile uint32_t N1DA_13; /* N1DA_13 */ - volatile uint32_t N1TB_13; /* N1TB_13 */ - volatile uint32_t CRSA_13; /* CRSA_13 */ - volatile uint32_t CRDA_13; /* CRDA_13 */ - volatile uint32_t CRTB_13; /* CRTB_13 */ - volatile uint32_t CHSTAT_13; /* CHSTAT_13 */ - volatile uint32_t CHCTRL_13; /* CHCTRL_13 */ - volatile uint32_t CHCFG_13; /* CHCFG_13 */ - volatile uint32_t CHITVL_13; /* CHITVL_13 */ - volatile uint32_t CHEXT_13; /* CHEXT_13 */ - volatile uint32_t NXLA_13; /* NXLA_13 */ - volatile uint32_t CRLA_13; /* CRLA_13 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_14; /* N0SA_14 */ - volatile uint32_t N0DA_14; /* N0DA_14 */ - volatile uint32_t N0TB_14; /* N0TB_14 */ - volatile uint32_t N1SA_14; /* N1SA_14 */ - volatile uint32_t N1DA_14; /* N1DA_14 */ - volatile uint32_t N1TB_14; /* N1TB_14 */ - volatile uint32_t CRSA_14; /* CRSA_14 */ - volatile uint32_t CRDA_14; /* CRDA_14 */ - volatile uint32_t CRTB_14; /* CRTB_14 */ - volatile uint32_t CHSTAT_14; /* CHSTAT_14 */ - volatile uint32_t CHCTRL_14; /* CHCTRL_14 */ - volatile uint32_t CHCFG_14; /* CHCFG_14 */ - volatile uint32_t CHITVL_14; /* CHITVL_14 */ - volatile uint32_t CHEXT_14; /* CHEXT_14 */ - volatile uint32_t NXLA_14; /* NXLA_14 */ - volatile uint32_t CRLA_14; /* CRLA_14 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_15; /* N0SA_15 */ - volatile uint32_t N0DA_15; /* N0DA_15 */ - volatile uint32_t N0TB_15; /* N0TB_15 */ - volatile uint32_t N1SA_15; /* N1SA_15 */ - volatile uint32_t N1DA_15; /* N1DA_15 */ - volatile uint32_t N1TB_15; /* N1TB_15 */ - volatile uint32_t CRSA_15; /* CRSA_15 */ - volatile uint32_t CRDA_15; /* CRDA_15 */ - volatile uint32_t CRTB_15; /* CRTB_15 */ - volatile uint32_t CHSTAT_15; /* CHSTAT_15 */ - volatile uint32_t CHCTRL_15; /* CHCTRL_15 */ - volatile uint32_t CHCFG_15; /* CHCFG_15 */ - volatile uint32_t CHITVL_15; /* CHITVL_15 */ - volatile uint32_t CHEXT_15; /* CHEXT_15 */ - volatile uint32_t NXLA_15; /* NXLA_15 */ - volatile uint32_t CRLA_15; /* CRLA_15 */ -/* end of struct st_dmac_n */ - volatile uint8_t dummy190[256]; /* */ -/* start of struct st_dmaccommon_n */ - volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */ - volatile uint8_t dummy191[12]; /* */ - volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */ - volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */ - volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */ - volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */ - volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */ -/* end of struct st_dmaccommon_n */ - volatile uint8_t dummy192[350095580]; /* */ - volatile uint32_t DMARS0; /* DMARS0 */ - volatile uint32_t DMARS1; /* DMARS1 */ - volatile uint32_t DMARS2; /* DMARS2 */ - volatile uint32_t DMARS3; /* DMARS3 */ - volatile uint32_t DMARS4; /* DMARS4 */ - volatile uint32_t DMARS5; /* DMARS5 */ - volatile uint32_t DMARS6; /* DMARS6 */ - volatile uint32_t DMARS7; /* DMARS7 */ -}; -struct st_dmaccommon_n -{ - volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ - volatile uint8_t dummy1[12]; /* */ - volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ - volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ - volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ - volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ - volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ -}; - - -struct st_dmac_n -{ - volatile uint32_t N0SA_n; /* N0SA_n */ - volatile uint32_t N0DA_n; /* N0DA_n */ - volatile uint32_t N0TB_n; /* N0TB_n */ - volatile uint32_t N1SA_n; /* N1SA_n */ - volatile uint32_t N1DA_n; /* N1DA_n */ - volatile uint32_t N1TB_n; /* N1TB_n */ - volatile uint32_t CRSA_n; /* CRSA_n */ - volatile uint32_t CRDA_n; /* CRDA_n */ - volatile uint32_t CRTB_n; /* CRTB_n */ - volatile uint32_t CHSTAT_n; /* CHSTAT_n */ - volatile uint32_t CHCTRL_n; /* CHCTRL_n */ - volatile uint32_t CHCFG_n; /* CHCFG_n */ - volatile uint32_t CHITVL_n; /* CHITVL_n */ - volatile uint32_t CHEXT_n; /* CHEXT_n */ - volatile uint32_t NXLA_n; /* NXLA_n */ - volatile uint32_t CRLA_n; /* CRLA_n */ -}; +/* Channel array defines of DMACmm */ +#define DMACmm_COUNT (8) +#define DMACmm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */ +#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */ +#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */ +#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */ +#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */ +#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */ +#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */ +#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */ +/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */ #define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */ -/* Start of channnel array defines of DMAC */ +/* Start of channel array defines of DMAC */ -/* Channnel array defines of DMACn */ +/* Channel array defines of DMACn */ /*(Sample) value = DMACn[ channel ]->N0SA_n; */ -#define DMACn_COUNT 16 +#define DMACn_COUNT (16) #define DMACn_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \ @@ -418,9 +83,9 @@ struct st_dmac_n #define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */ -/* Channnel array defines of DMACnn */ +/* Channel array defines of DMACnn */ /*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */ -#define DMACnn_COUNT 2 +#define DMACnn_COUNT (2) #define DMACnn_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &DMAC07, &DMAC815 \ @@ -428,306 +93,715 @@ struct st_dmac_n #define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */ #define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */ +/* End of channel array defines of DMAC */ -/* Channnel array defines of DMACmm */ -/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */ -struct st_dmars_mm + +#define DMACN0SA_0 (DMAC.N0SA_0) +#define DMACN0DA_0 (DMAC.N0DA_0) +#define DMACN0TB_0 (DMAC.N0TB_0) +#define DMACN1SA_0 (DMAC.N1SA_0) +#define DMACN1DA_0 (DMAC.N1DA_0) +#define DMACN1TB_0 (DMAC.N1TB_0) +#define DMACCRSA_0 (DMAC.CRSA_0) +#define DMACCRDA_0 (DMAC.CRDA_0) +#define DMACCRTB_0 (DMAC.CRTB_0) +#define DMACCHSTAT_0 (DMAC.CHSTAT_0) +#define DMACCHCTRL_0 (DMAC.CHCTRL_0) +#define DMACCHCFG_0 (DMAC.CHCFG_0) +#define DMACCHITVL_0 (DMAC.CHITVL_0) +#define DMACCHEXT_0 (DMAC.CHEXT_0) +#define DMACNXLA_0 (DMAC.NXLA_0) +#define DMACCRLA_0 (DMAC.CRLA_0) +#define DMACN0SA_1 (DMAC.N0SA_1) +#define DMACN0DA_1 (DMAC.N0DA_1) +#define DMACN0TB_1 (DMAC.N0TB_1) +#define DMACN1SA_1 (DMAC.N1SA_1) +#define DMACN1DA_1 (DMAC.N1DA_1) +#define DMACN1TB_1 (DMAC.N1TB_1) +#define DMACCRSA_1 (DMAC.CRSA_1) +#define DMACCRDA_1 (DMAC.CRDA_1) +#define DMACCRTB_1 (DMAC.CRTB_1) +#define DMACCHSTAT_1 (DMAC.CHSTAT_1) +#define DMACCHCTRL_1 (DMAC.CHCTRL_1) +#define DMACCHCFG_1 (DMAC.CHCFG_1) +#define DMACCHITVL_1 (DMAC.CHITVL_1) +#define DMACCHEXT_1 (DMAC.CHEXT_1) +#define DMACNXLA_1 (DMAC.NXLA_1) +#define DMACCRLA_1 (DMAC.CRLA_1) +#define DMACN0SA_2 (DMAC.N0SA_2) +#define DMACN0DA_2 (DMAC.N0DA_2) +#define DMACN0TB_2 (DMAC.N0TB_2) +#define DMACN1SA_2 (DMAC.N1SA_2) +#define DMACN1DA_2 (DMAC.N1DA_2) +#define DMACN1TB_2 (DMAC.N1TB_2) +#define DMACCRSA_2 (DMAC.CRSA_2) +#define DMACCRDA_2 (DMAC.CRDA_2) +#define DMACCRTB_2 (DMAC.CRTB_2) +#define DMACCHSTAT_2 (DMAC.CHSTAT_2) +#define DMACCHCTRL_2 (DMAC.CHCTRL_2) +#define DMACCHCFG_2 (DMAC.CHCFG_2) +#define DMACCHITVL_2 (DMAC.CHITVL_2) +#define DMACCHEXT_2 (DMAC.CHEXT_2) +#define DMACNXLA_2 (DMAC.NXLA_2) +#define DMACCRLA_2 (DMAC.CRLA_2) +#define DMACN0SA_3 (DMAC.N0SA_3) +#define DMACN0DA_3 (DMAC.N0DA_3) +#define DMACN0TB_3 (DMAC.N0TB_3) +#define DMACN1SA_3 (DMAC.N1SA_3) +#define DMACN1DA_3 (DMAC.N1DA_3) +#define DMACN1TB_3 (DMAC.N1TB_3) +#define DMACCRSA_3 (DMAC.CRSA_3) +#define DMACCRDA_3 (DMAC.CRDA_3) +#define DMACCRTB_3 (DMAC.CRTB_3) +#define DMACCHSTAT_3 (DMAC.CHSTAT_3) +#define DMACCHCTRL_3 (DMAC.CHCTRL_3) +#define DMACCHCFG_3 (DMAC.CHCFG_3) +#define DMACCHITVL_3 (DMAC.CHITVL_3) +#define DMACCHEXT_3 (DMAC.CHEXT_3) +#define DMACNXLA_3 (DMAC.NXLA_3) +#define DMACCRLA_3 (DMAC.CRLA_3) +#define DMACN0SA_4 (DMAC.N0SA_4) +#define DMACN0DA_4 (DMAC.N0DA_4) +#define DMACN0TB_4 (DMAC.N0TB_4) +#define DMACN1SA_4 (DMAC.N1SA_4) +#define DMACN1DA_4 (DMAC.N1DA_4) +#define DMACN1TB_4 (DMAC.N1TB_4) +#define DMACCRSA_4 (DMAC.CRSA_4) +#define DMACCRDA_4 (DMAC.CRDA_4) +#define DMACCRTB_4 (DMAC.CRTB_4) +#define DMACCHSTAT_4 (DMAC.CHSTAT_4) +#define DMACCHCTRL_4 (DMAC.CHCTRL_4) +#define DMACCHCFG_4 (DMAC.CHCFG_4) +#define DMACCHITVL_4 (DMAC.CHITVL_4) +#define DMACCHEXT_4 (DMAC.CHEXT_4) +#define DMACNXLA_4 (DMAC.NXLA_4) +#define DMACCRLA_4 (DMAC.CRLA_4) +#define DMACN0SA_5 (DMAC.N0SA_5) +#define DMACN0DA_5 (DMAC.N0DA_5) +#define DMACN0TB_5 (DMAC.N0TB_5) +#define DMACN1SA_5 (DMAC.N1SA_5) +#define DMACN1DA_5 (DMAC.N1DA_5) +#define DMACN1TB_5 (DMAC.N1TB_5) +#define DMACCRSA_5 (DMAC.CRSA_5) +#define DMACCRDA_5 (DMAC.CRDA_5) +#define DMACCRTB_5 (DMAC.CRTB_5) +#define DMACCHSTAT_5 (DMAC.CHSTAT_5) +#define DMACCHCTRL_5 (DMAC.CHCTRL_5) +#define DMACCHCFG_5 (DMAC.CHCFG_5) +#define DMACCHITVL_5 (DMAC.CHITVL_5) +#define DMACCHEXT_5 (DMAC.CHEXT_5) +#define DMACNXLA_5 (DMAC.NXLA_5) +#define DMACCRLA_5 (DMAC.CRLA_5) +#define DMACN0SA_6 (DMAC.N0SA_6) +#define DMACN0DA_6 (DMAC.N0DA_6) +#define DMACN0TB_6 (DMAC.N0TB_6) +#define DMACN1SA_6 (DMAC.N1SA_6) +#define DMACN1DA_6 (DMAC.N1DA_6) +#define DMACN1TB_6 (DMAC.N1TB_6) +#define DMACCRSA_6 (DMAC.CRSA_6) +#define DMACCRDA_6 (DMAC.CRDA_6) +#define DMACCRTB_6 (DMAC.CRTB_6) +#define DMACCHSTAT_6 (DMAC.CHSTAT_6) +#define DMACCHCTRL_6 (DMAC.CHCTRL_6) +#define DMACCHCFG_6 (DMAC.CHCFG_6) +#define DMACCHITVL_6 (DMAC.CHITVL_6) +#define DMACCHEXT_6 (DMAC.CHEXT_6) +#define DMACNXLA_6 (DMAC.NXLA_6) +#define DMACCRLA_6 (DMAC.CRLA_6) +#define DMACN0SA_7 (DMAC.N0SA_7) +#define DMACN0DA_7 (DMAC.N0DA_7) +#define DMACN0TB_7 (DMAC.N0TB_7) +#define DMACN1SA_7 (DMAC.N1SA_7) +#define DMACN1DA_7 (DMAC.N1DA_7) +#define DMACN1TB_7 (DMAC.N1TB_7) +#define DMACCRSA_7 (DMAC.CRSA_7) +#define DMACCRDA_7 (DMAC.CRDA_7) +#define DMACCRTB_7 (DMAC.CRTB_7) +#define DMACCHSTAT_7 (DMAC.CHSTAT_7) +#define DMACCHCTRL_7 (DMAC.CHCTRL_7) +#define DMACCHCFG_7 (DMAC.CHCFG_7) +#define DMACCHITVL_7 (DMAC.CHITVL_7) +#define DMACCHEXT_7 (DMAC.CHEXT_7) +#define DMACNXLA_7 (DMAC.NXLA_7) +#define DMACCRLA_7 (DMAC.CRLA_7) +#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7) +#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7) +#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7) +#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7) +#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7) +#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7) +#define DMACN0SA_8 (DMAC.N0SA_8) +#define DMACN0DA_8 (DMAC.N0DA_8) +#define DMACN0TB_8 (DMAC.N0TB_8) +#define DMACN1SA_8 (DMAC.N1SA_8) +#define DMACN1DA_8 (DMAC.N1DA_8) +#define DMACN1TB_8 (DMAC.N1TB_8) +#define DMACCRSA_8 (DMAC.CRSA_8) +#define DMACCRDA_8 (DMAC.CRDA_8) +#define DMACCRTB_8 (DMAC.CRTB_8) +#define DMACCHSTAT_8 (DMAC.CHSTAT_8) +#define DMACCHCTRL_8 (DMAC.CHCTRL_8) +#define DMACCHCFG_8 (DMAC.CHCFG_8) +#define DMACCHITVL_8 (DMAC.CHITVL_8) +#define DMACCHEXT_8 (DMAC.CHEXT_8) +#define DMACNXLA_8 (DMAC.NXLA_8) +#define DMACCRLA_8 (DMAC.CRLA_8) +#define DMACN0SA_9 (DMAC.N0SA_9) +#define DMACN0DA_9 (DMAC.N0DA_9) +#define DMACN0TB_9 (DMAC.N0TB_9) +#define DMACN1SA_9 (DMAC.N1SA_9) +#define DMACN1DA_9 (DMAC.N1DA_9) +#define DMACN1TB_9 (DMAC.N1TB_9) +#define DMACCRSA_9 (DMAC.CRSA_9) +#define DMACCRDA_9 (DMAC.CRDA_9) +#define DMACCRTB_9 (DMAC.CRTB_9) +#define DMACCHSTAT_9 (DMAC.CHSTAT_9) +#define DMACCHCTRL_9 (DMAC.CHCTRL_9) +#define DMACCHCFG_9 (DMAC.CHCFG_9) +#define DMACCHITVL_9 (DMAC.CHITVL_9) +#define DMACCHEXT_9 (DMAC.CHEXT_9) +#define DMACNXLA_9 (DMAC.NXLA_9) +#define DMACCRLA_9 (DMAC.CRLA_9) +#define DMACN0SA_10 (DMAC.N0SA_10) +#define DMACN0DA_10 (DMAC.N0DA_10) +#define DMACN0TB_10 (DMAC.N0TB_10) +#define DMACN1SA_10 (DMAC.N1SA_10) +#define DMACN1DA_10 (DMAC.N1DA_10) +#define DMACN1TB_10 (DMAC.N1TB_10) +#define DMACCRSA_10 (DMAC.CRSA_10) +#define DMACCRDA_10 (DMAC.CRDA_10) +#define DMACCRTB_10 (DMAC.CRTB_10) +#define DMACCHSTAT_10 (DMAC.CHSTAT_10) +#define DMACCHCTRL_10 (DMAC.CHCTRL_10) +#define DMACCHCFG_10 (DMAC.CHCFG_10) +#define DMACCHITVL_10 (DMAC.CHITVL_10) +#define DMACCHEXT_10 (DMAC.CHEXT_10) +#define DMACNXLA_10 (DMAC.NXLA_10) +#define DMACCRLA_10 (DMAC.CRLA_10) +#define DMACN0SA_11 (DMAC.N0SA_11) +#define DMACN0DA_11 (DMAC.N0DA_11) +#define DMACN0TB_11 (DMAC.N0TB_11) +#define DMACN1SA_11 (DMAC.N1SA_11) +#define DMACN1DA_11 (DMAC.N1DA_11) +#define DMACN1TB_11 (DMAC.N1TB_11) +#define DMACCRSA_11 (DMAC.CRSA_11) +#define DMACCRDA_11 (DMAC.CRDA_11) +#define DMACCRTB_11 (DMAC.CRTB_11) +#define DMACCHSTAT_11 (DMAC.CHSTAT_11) +#define DMACCHCTRL_11 (DMAC.CHCTRL_11) +#define DMACCHCFG_11 (DMAC.CHCFG_11) +#define DMACCHITVL_11 (DMAC.CHITVL_11) +#define DMACCHEXT_11 (DMAC.CHEXT_11) +#define DMACNXLA_11 (DMAC.NXLA_11) +#define DMACCRLA_11 (DMAC.CRLA_11) +#define DMACN0SA_12 (DMAC.N0SA_12) +#define DMACN0DA_12 (DMAC.N0DA_12) +#define DMACN0TB_12 (DMAC.N0TB_12) +#define DMACN1SA_12 (DMAC.N1SA_12) +#define DMACN1DA_12 (DMAC.N1DA_12) +#define DMACN1TB_12 (DMAC.N1TB_12) +#define DMACCRSA_12 (DMAC.CRSA_12) +#define DMACCRDA_12 (DMAC.CRDA_12) +#define DMACCRTB_12 (DMAC.CRTB_12) +#define DMACCHSTAT_12 (DMAC.CHSTAT_12) +#define DMACCHCTRL_12 (DMAC.CHCTRL_12) +#define DMACCHCFG_12 (DMAC.CHCFG_12) +#define DMACCHITVL_12 (DMAC.CHITVL_12) +#define DMACCHEXT_12 (DMAC.CHEXT_12) +#define DMACNXLA_12 (DMAC.NXLA_12) +#define DMACCRLA_12 (DMAC.CRLA_12) +#define DMACN0SA_13 (DMAC.N0SA_13) +#define DMACN0DA_13 (DMAC.N0DA_13) +#define DMACN0TB_13 (DMAC.N0TB_13) +#define DMACN1SA_13 (DMAC.N1SA_13) +#define DMACN1DA_13 (DMAC.N1DA_13) +#define DMACN1TB_13 (DMAC.N1TB_13) +#define DMACCRSA_13 (DMAC.CRSA_13) +#define DMACCRDA_13 (DMAC.CRDA_13) +#define DMACCRTB_13 (DMAC.CRTB_13) +#define DMACCHSTAT_13 (DMAC.CHSTAT_13) +#define DMACCHCTRL_13 (DMAC.CHCTRL_13) +#define DMACCHCFG_13 (DMAC.CHCFG_13) +#define DMACCHITVL_13 (DMAC.CHITVL_13) +#define DMACCHEXT_13 (DMAC.CHEXT_13) +#define DMACNXLA_13 (DMAC.NXLA_13) +#define DMACCRLA_13 (DMAC.CRLA_13) +#define DMACN0SA_14 (DMAC.N0SA_14) +#define DMACN0DA_14 (DMAC.N0DA_14) +#define DMACN0TB_14 (DMAC.N0TB_14) +#define DMACN1SA_14 (DMAC.N1SA_14) +#define DMACN1DA_14 (DMAC.N1DA_14) +#define DMACN1TB_14 (DMAC.N1TB_14) +#define DMACCRSA_14 (DMAC.CRSA_14) +#define DMACCRDA_14 (DMAC.CRDA_14) +#define DMACCRTB_14 (DMAC.CRTB_14) +#define DMACCHSTAT_14 (DMAC.CHSTAT_14) +#define DMACCHCTRL_14 (DMAC.CHCTRL_14) +#define DMACCHCFG_14 (DMAC.CHCFG_14) +#define DMACCHITVL_14 (DMAC.CHITVL_14) +#define DMACCHEXT_14 (DMAC.CHEXT_14) +#define DMACNXLA_14 (DMAC.NXLA_14) +#define DMACCRLA_14 (DMAC.CRLA_14) +#define DMACN0SA_15 (DMAC.N0SA_15) +#define DMACN0DA_15 (DMAC.N0DA_15) +#define DMACN0TB_15 (DMAC.N0TB_15) +#define DMACN1SA_15 (DMAC.N1SA_15) +#define DMACN1DA_15 (DMAC.N1DA_15) +#define DMACN1TB_15 (DMAC.N1TB_15) +#define DMACCRSA_15 (DMAC.CRSA_15) +#define DMACCRDA_15 (DMAC.CRDA_15) +#define DMACCRTB_15 (DMAC.CRTB_15) +#define DMACCHSTAT_15 (DMAC.CHSTAT_15) +#define DMACCHCTRL_15 (DMAC.CHCTRL_15) +#define DMACCHCFG_15 (DMAC.CHCFG_15) +#define DMACCHITVL_15 (DMAC.CHITVL_15) +#define DMACCHEXT_15 (DMAC.CHEXT_15) +#define DMACNXLA_15 (DMAC.NXLA_15) +#define DMACCRLA_15 (DMAC.CRLA_15) +#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15) +#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15) +#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15) +#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15) +#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15) +#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15) +#define DMACDMARS0 (DMAC.DMARS0) +#define DMACDMARS1 (DMAC.DMARS1) +#define DMACDMARS2 (DMAC.DMARS2) +#define DMACDMARS3 (DMAC.DMARS3) +#define DMACDMARS4 (DMAC.DMARS4) +#define DMACDMARS5 (DMAC.DMARS5) +#define DMACDMARS6 (DMAC.DMARS6) +#define DMACDMARS7 (DMAC.DMARS7) + + +typedef struct st_dmars_mm { - uint32_t DMARS; /* DMARS */ -}; -#define DMACmm_COUNT 8 -#define DMACmm_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */ -#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */ -#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */ -#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */ -#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */ -#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */ -#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */ -#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */ - -/* End of channnel array defines of DMAC */ + + volatile uint32_t DMARS; /* DMARS */ +} r_io_dmars_mm_t; + + +typedef struct st_dmac +{ + /* DMAC */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_0; /* N0SA_0 */ + volatile uint32_t N0DA_0; /* N0DA_0 */ + volatile uint32_t N0TB_0; /* N0TB_0 */ + volatile uint32_t N1SA_0; /* N1SA_0 */ + volatile uint32_t N1DA_0; /* N1DA_0 */ + volatile uint32_t N1TB_0; /* N1TB_0 */ + volatile uint32_t CRSA_0; /* CRSA_0 */ + volatile uint32_t CRDA_0; /* CRDA_0 */ + volatile uint32_t CRTB_0; /* CRTB_0 */ + volatile uint32_t CHSTAT_0; /* CHSTAT_0 */ + volatile uint32_t CHCTRL_0; /* CHCTRL_0 */ + volatile uint32_t CHCFG_0; /* CHCFG_0 */ + volatile uint32_t CHITVL_0; /* CHITVL_0 */ + volatile uint32_t CHEXT_0; /* CHEXT_0 */ + volatile uint32_t NXLA_0; /* NXLA_0 */ + volatile uint32_t CRLA_0; /* CRLA_0 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_1; /* N0SA_1 */ + volatile uint32_t N0DA_1; /* N0DA_1 */ + volatile uint32_t N0TB_1; /* N0TB_1 */ + volatile uint32_t N1SA_1; /* N1SA_1 */ + volatile uint32_t N1DA_1; /* N1DA_1 */ + volatile uint32_t N1TB_1; /* N1TB_1 */ + volatile uint32_t CRSA_1; /* CRSA_1 */ + volatile uint32_t CRDA_1; /* CRDA_1 */ + volatile uint32_t CRTB_1; /* CRTB_1 */ + volatile uint32_t CHSTAT_1; /* CHSTAT_1 */ + volatile uint32_t CHCTRL_1; /* CHCTRL_1 */ + volatile uint32_t CHCFG_1; /* CHCFG_1 */ + volatile uint32_t CHITVL_1; /* CHITVL_1 */ + volatile uint32_t CHEXT_1; /* CHEXT_1 */ + volatile uint32_t NXLA_1; /* NXLA_1 */ + volatile uint32_t CRLA_1; /* CRLA_1 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_2; /* N0SA_2 */ + volatile uint32_t N0DA_2; /* N0DA_2 */ + volatile uint32_t N0TB_2; /* N0TB_2 */ + volatile uint32_t N1SA_2; /* N1SA_2 */ + volatile uint32_t N1DA_2; /* N1DA_2 */ + volatile uint32_t N1TB_2; /* N1TB_2 */ + volatile uint32_t CRSA_2; /* CRSA_2 */ + volatile uint32_t CRDA_2; /* CRDA_2 */ + volatile uint32_t CRTB_2; /* CRTB_2 */ + volatile uint32_t CHSTAT_2; /* CHSTAT_2 */ + volatile uint32_t CHCTRL_2; /* CHCTRL_2 */ + volatile uint32_t CHCFG_2; /* CHCFG_2 */ + volatile uint32_t CHITVL_2; /* CHITVL_2 */ + volatile uint32_t CHEXT_2; /* CHEXT_2 */ + volatile uint32_t NXLA_2; /* NXLA_2 */ + volatile uint32_t CRLA_2; /* CRLA_2 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_3; /* N0SA_3 */ + volatile uint32_t N0DA_3; /* N0DA_3 */ + volatile uint32_t N0TB_3; /* N0TB_3 */ + volatile uint32_t N1SA_3; /* N1SA_3 */ + volatile uint32_t N1DA_3; /* N1DA_3 */ + volatile uint32_t N1TB_3; /* N1TB_3 */ + volatile uint32_t CRSA_3; /* CRSA_3 */ + volatile uint32_t CRDA_3; /* CRDA_3 */ + volatile uint32_t CRTB_3; /* CRTB_3 */ + volatile uint32_t CHSTAT_3; /* CHSTAT_3 */ + volatile uint32_t CHCTRL_3; /* CHCTRL_3 */ + volatile uint32_t CHCFG_3; /* CHCFG_3 */ + volatile uint32_t CHITVL_3; /* CHITVL_3 */ + volatile uint32_t CHEXT_3; /* CHEXT_3 */ + volatile uint32_t NXLA_3; /* NXLA_3 */ + volatile uint32_t CRLA_3; /* CRLA_3 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_4; /* N0SA_4 */ + volatile uint32_t N0DA_4; /* N0DA_4 */ + volatile uint32_t N0TB_4; /* N0TB_4 */ + volatile uint32_t N1SA_4; /* N1SA_4 */ + volatile uint32_t N1DA_4; /* N1DA_4 */ + volatile uint32_t N1TB_4; /* N1TB_4 */ + volatile uint32_t CRSA_4; /* CRSA_4 */ + volatile uint32_t CRDA_4; /* CRDA_4 */ + volatile uint32_t CRTB_4; /* CRTB_4 */ + volatile uint32_t CHSTAT_4; /* CHSTAT_4 */ + volatile uint32_t CHCTRL_4; /* CHCTRL_4 */ + volatile uint32_t CHCFG_4; /* CHCFG_4 */ + volatile uint32_t CHITVL_4; /* CHITVL_4 */ + volatile uint32_t CHEXT_4; /* CHEXT_4 */ + volatile uint32_t NXLA_4; /* NXLA_4 */ + volatile uint32_t CRLA_4; /* CRLA_4 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_5; /* N0SA_5 */ + volatile uint32_t N0DA_5; /* N0DA_5 */ + volatile uint32_t N0TB_5; /* N0TB_5 */ + volatile uint32_t N1SA_5; /* N1SA_5 */ + volatile uint32_t N1DA_5; /* N1DA_5 */ + volatile uint32_t N1TB_5; /* N1TB_5 */ + volatile uint32_t CRSA_5; /* CRSA_5 */ + volatile uint32_t CRDA_5; /* CRDA_5 */ + volatile uint32_t CRTB_5; /* CRTB_5 */ + volatile uint32_t CHSTAT_5; /* CHSTAT_5 */ + volatile uint32_t CHCTRL_5; /* CHCTRL_5 */ + volatile uint32_t CHCFG_5; /* CHCFG_5 */ + volatile uint32_t CHITVL_5; /* CHITVL_5 */ + volatile uint32_t CHEXT_5; /* CHEXT_5 */ + volatile uint32_t NXLA_5; /* NXLA_5 */ + volatile uint32_t CRLA_5; /* CRLA_5 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_6; /* N0SA_6 */ + volatile uint32_t N0DA_6; /* N0DA_6 */ + volatile uint32_t N0TB_6; /* N0TB_6 */ + volatile uint32_t N1SA_6; /* N1SA_6 */ + volatile uint32_t N1DA_6; /* N1DA_6 */ + volatile uint32_t N1TB_6; /* N1TB_6 */ + volatile uint32_t CRSA_6; /* CRSA_6 */ + volatile uint32_t CRDA_6; /* CRDA_6 */ + volatile uint32_t CRTB_6; /* CRTB_6 */ + volatile uint32_t CHSTAT_6; /* CHSTAT_6 */ + volatile uint32_t CHCTRL_6; /* CHCTRL_6 */ + volatile uint32_t CHCFG_6; /* CHCFG_6 */ + volatile uint32_t CHITVL_6; /* CHITVL_6 */ + volatile uint32_t CHEXT_6; /* CHEXT_6 */ + volatile uint32_t NXLA_6; /* NXLA_6 */ + volatile uint32_t CRLA_6; /* CRLA_6 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_7; /* N0SA_7 */ + volatile uint32_t N0DA_7; /* N0DA_7 */ + volatile uint32_t N0TB_7; /* N0TB_7 */ + volatile uint32_t N1SA_7; /* N1SA_7 */ + volatile uint32_t N1DA_7; /* N1DA_7 */ + volatile uint32_t N1TB_7; /* N1TB_7 */ + volatile uint32_t CRSA_7; /* CRSA_7 */ + volatile uint32_t CRDA_7; /* CRDA_7 */ + volatile uint32_t CRTB_7; /* CRTB_7 */ + volatile uint32_t CHSTAT_7; /* CHSTAT_7 */ + volatile uint32_t CHCTRL_7; /* CHCTRL_7 */ + volatile uint32_t CHCFG_7; /* CHCFG_7 */ + volatile uint32_t CHITVL_7; /* CHITVL_7 */ + volatile uint32_t CHEXT_7; /* CHEXT_7 */ + volatile uint32_t NXLA_7; /* NXLA_7 */ + volatile uint32_t CRLA_7; /* CRLA_7 */ + +/* end of struct st_dmac_n */ + volatile uint8_t dummy187[256]; /* */ + +/* start of struct st_dmaccommon_n */ + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ + volatile uint8_t dummy188[12]; /* */ + volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ + volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ + volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ + volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ + volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ + +/* end of struct st_dmaccommon_n */ + volatile uint8_t dummy189[220]; /* */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_8; /* N0SA_8 */ + volatile uint32_t N0DA_8; /* N0DA_8 */ + volatile uint32_t N0TB_8; /* N0TB_8 */ + volatile uint32_t N1SA_8; /* N1SA_8 */ + volatile uint32_t N1DA_8; /* N1DA_8 */ + volatile uint32_t N1TB_8; /* N1TB_8 */ + volatile uint32_t CRSA_8; /* CRSA_8 */ + volatile uint32_t CRDA_8; /* CRDA_8 */ + volatile uint32_t CRTB_8; /* CRTB_8 */ + volatile uint32_t CHSTAT_8; /* CHSTAT_8 */ + volatile uint32_t CHCTRL_8; /* CHCTRL_8 */ + volatile uint32_t CHCFG_8; /* CHCFG_8 */ + volatile uint32_t CHITVL_8; /* CHITVL_8 */ + volatile uint32_t CHEXT_8; /* CHEXT_8 */ + volatile uint32_t NXLA_8; /* NXLA_8 */ + volatile uint32_t CRLA_8; /* CRLA_8 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_9; /* N0SA_9 */ + volatile uint32_t N0DA_9; /* N0DA_9 */ + volatile uint32_t N0TB_9; /* N0TB_9 */ + volatile uint32_t N1SA_9; /* N1SA_9 */ + volatile uint32_t N1DA_9; /* N1DA_9 */ + volatile uint32_t N1TB_9; /* N1TB_9 */ + volatile uint32_t CRSA_9; /* CRSA_9 */ + volatile uint32_t CRDA_9; /* CRDA_9 */ + volatile uint32_t CRTB_9; /* CRTB_9 */ + volatile uint32_t CHSTAT_9; /* CHSTAT_9 */ + volatile uint32_t CHCTRL_9; /* CHCTRL_9 */ + volatile uint32_t CHCFG_9; /* CHCFG_9 */ + volatile uint32_t CHITVL_9; /* CHITVL_9 */ + volatile uint32_t CHEXT_9; /* CHEXT_9 */ + volatile uint32_t NXLA_9; /* NXLA_9 */ + volatile uint32_t CRLA_9; /* CRLA_9 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_10; /* N0SA_10 */ + volatile uint32_t N0DA_10; /* N0DA_10 */ + volatile uint32_t N0TB_10; /* N0TB_10 */ + volatile uint32_t N1SA_10; /* N1SA_10 */ + volatile uint32_t N1DA_10; /* N1DA_10 */ + volatile uint32_t N1TB_10; /* N1TB_10 */ + volatile uint32_t CRSA_10; /* CRSA_10 */ + volatile uint32_t CRDA_10; /* CRDA_10 */ + volatile uint32_t CRTB_10; /* CRTB_10 */ + volatile uint32_t CHSTAT_10; /* CHSTAT_10 */ + volatile uint32_t CHCTRL_10; /* CHCTRL_10 */ + volatile uint32_t CHCFG_10; /* CHCFG_10 */ + volatile uint32_t CHITVL_10; /* CHITVL_10 */ + volatile uint32_t CHEXT_10; /* CHEXT_10 */ + volatile uint32_t NXLA_10; /* NXLA_10 */ + volatile uint32_t CRLA_10; /* CRLA_10 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_11; /* N0SA_11 */ + volatile uint32_t N0DA_11; /* N0DA_11 */ + volatile uint32_t N0TB_11; /* N0TB_11 */ + volatile uint32_t N1SA_11; /* N1SA_11 */ + volatile uint32_t N1DA_11; /* N1DA_11 */ + volatile uint32_t N1TB_11; /* N1TB_11 */ + volatile uint32_t CRSA_11; /* CRSA_11 */ + volatile uint32_t CRDA_11; /* CRDA_11 */ + volatile uint32_t CRTB_11; /* CRTB_11 */ + volatile uint32_t CHSTAT_11; /* CHSTAT_11 */ + volatile uint32_t CHCTRL_11; /* CHCTRL_11 */ + volatile uint32_t CHCFG_11; /* CHCFG_11 */ + volatile uint32_t CHITVL_11; /* CHITVL_11 */ + volatile uint32_t CHEXT_11; /* CHEXT_11 */ + volatile uint32_t NXLA_11; /* NXLA_11 */ + volatile uint32_t CRLA_11; /* CRLA_11 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_12; /* N0SA_12 */ + volatile uint32_t N0DA_12; /* N0DA_12 */ + volatile uint32_t N0TB_12; /* N0TB_12 */ + volatile uint32_t N1SA_12; /* N1SA_12 */ + volatile uint32_t N1DA_12; /* N1DA_12 */ + volatile uint32_t N1TB_12; /* N1TB_12 */ + volatile uint32_t CRSA_12; /* CRSA_12 */ + volatile uint32_t CRDA_12; /* CRDA_12 */ + volatile uint32_t CRTB_12; /* CRTB_12 */ + volatile uint32_t CHSTAT_12; /* CHSTAT_12 */ + volatile uint32_t CHCTRL_12; /* CHCTRL_12 */ + volatile uint32_t CHCFG_12; /* CHCFG_12 */ + volatile uint32_t CHITVL_12; /* CHITVL_12 */ + volatile uint32_t CHEXT_12; /* CHEXT_12 */ + volatile uint32_t NXLA_12; /* NXLA_12 */ + volatile uint32_t CRLA_12; /* CRLA_12 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_13; /* N0SA_13 */ + volatile uint32_t N0DA_13; /* N0DA_13 */ + volatile uint32_t N0TB_13; /* N0TB_13 */ + volatile uint32_t N1SA_13; /* N1SA_13 */ + volatile uint32_t N1DA_13; /* N1DA_13 */ + volatile uint32_t N1TB_13; /* N1TB_13 */ + volatile uint32_t CRSA_13; /* CRSA_13 */ + volatile uint32_t CRDA_13; /* CRDA_13 */ + volatile uint32_t CRTB_13; /* CRTB_13 */ + volatile uint32_t CHSTAT_13; /* CHSTAT_13 */ + volatile uint32_t CHCTRL_13; /* CHCTRL_13 */ + volatile uint32_t CHCFG_13; /* CHCFG_13 */ + volatile uint32_t CHITVL_13; /* CHITVL_13 */ + volatile uint32_t CHEXT_13; /* CHEXT_13 */ + volatile uint32_t NXLA_13; /* NXLA_13 */ + volatile uint32_t CRLA_13; /* CRLA_13 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_14; /* N0SA_14 */ + volatile uint32_t N0DA_14; /* N0DA_14 */ + volatile uint32_t N0TB_14; /* N0TB_14 */ + volatile uint32_t N1SA_14; /* N1SA_14 */ + volatile uint32_t N1DA_14; /* N1DA_14 */ + volatile uint32_t N1TB_14; /* N1TB_14 */ + volatile uint32_t CRSA_14; /* CRSA_14 */ + volatile uint32_t CRDA_14; /* CRDA_14 */ + volatile uint32_t CRTB_14; /* CRTB_14 */ + volatile uint32_t CHSTAT_14; /* CHSTAT_14 */ + volatile uint32_t CHCTRL_14; /* CHCTRL_14 */ + volatile uint32_t CHCFG_14; /* CHCFG_14 */ + volatile uint32_t CHITVL_14; /* CHITVL_14 */ + volatile uint32_t CHEXT_14; /* CHEXT_14 */ + volatile uint32_t NXLA_14; /* NXLA_14 */ + volatile uint32_t CRLA_14; /* CRLA_14 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_15; /* N0SA_15 */ + volatile uint32_t N0DA_15; /* N0DA_15 */ + volatile uint32_t N0TB_15; /* N0TB_15 */ + volatile uint32_t N1SA_15; /* N1SA_15 */ + volatile uint32_t N1DA_15; /* N1DA_15 */ + volatile uint32_t N1TB_15; /* N1TB_15 */ + volatile uint32_t CRSA_15; /* CRSA_15 */ + volatile uint32_t CRDA_15; /* CRDA_15 */ + volatile uint32_t CRTB_15; /* CRTB_15 */ + volatile uint32_t CHSTAT_15; /* CHSTAT_15 */ + volatile uint32_t CHCTRL_15; /* CHCTRL_15 */ + volatile uint32_t CHCFG_15; /* CHCFG_15 */ + volatile uint32_t CHITVL_15; /* CHITVL_15 */ + volatile uint32_t CHEXT_15; /* CHEXT_15 */ + volatile uint32_t NXLA_15; /* NXLA_15 */ + volatile uint32_t CRLA_15; /* CRLA_15 */ + +/* end of struct st_dmac_n */ + volatile uint8_t dummy190[256]; /* */ + +/* start of struct st_dmaccommon_n */ + volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */ + volatile uint8_t dummy191[12]; /* */ + volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */ + volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */ + volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */ + volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */ + volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */ + +/* end of struct st_dmaccommon_n */ + volatile uint8_t dummy192[350095580]; /* */ + volatile uint32_t DMARS0; /* DMARS0 */ + volatile uint32_t DMARS1; /* DMARS1 */ + volatile uint32_t DMARS2; /* DMARS2 */ + volatile uint32_t DMARS3; /* DMARS3 */ + volatile uint32_t DMARS4; /* DMARS4 */ + volatile uint32_t DMARS5; /* DMARS5 */ + volatile uint32_t DMARS6; /* DMARS6 */ + volatile uint32_t DMARS7; /* DMARS7 */ +} r_io_dmac_t; + + +typedef struct st_dmaccommon_n +{ + + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ + volatile uint8_t dummy1[12]; /* */ + volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ + volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ + volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ + volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ + volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ +} r_io_dmaccommon_n_t; + + +typedef struct st_dmac_n +{ + + volatile uint32_t N0SA_n; /* N0SA_n */ + volatile uint32_t N0DA_n; /* N0DA_n */ + volatile uint32_t N0TB_n; /* N0TB_n */ + volatile uint32_t N1SA_n; /* N1SA_n */ + volatile uint32_t N1DA_n; /* N1DA_n */ + volatile uint32_t N1TB_n; /* N1TB_n */ + volatile uint32_t CRSA_n; /* CRSA_n */ + volatile uint32_t CRDA_n; /* CRDA_n */ + volatile uint32_t CRTB_n; /* CRTB_n */ + volatile uint32_t CHSTAT_n; /* CHSTAT_n */ + volatile uint32_t CHCTRL_n; /* CHCTRL_n */ + volatile uint32_t CHCFG_n; /* CHCFG_n */ + volatile uint32_t CHITVL_n; /* CHITVL_n */ + volatile uint32_t CHEXT_n; /* CHEXT_n */ + volatile uint32_t NXLA_n; /* NXLA_n */ + volatile uint32_t CRLA_n; /* CRLA_n */ +} r_io_dmac_n_t; + + +/* Channel array defines of DMAC (2)*/ +#ifdef DECLARE_DMACmm_CHANNELS +volatile struct st_dmars_mm* DMACmm[ DMACmm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACmm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACmm_CHANNELS */ + +#ifdef DECLARE_DMACn_CHANNELS +volatile struct st_dmac_n* DMACn[ DMACn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACn_CHANNELS */ + +#ifdef DECLARE_DMACnn_CHANNELS +volatile struct st_dmaccommon_n* DMACnn[ DMACnn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACnn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACnn_CHANNELS */ +/* End of channel array defines of DMAC (2)*/ -#define DMACN0SA_0 DMAC.N0SA_0 -#define DMACN0DA_0 DMAC.N0DA_0 -#define DMACN0TB_0 DMAC.N0TB_0 -#define DMACN1SA_0 DMAC.N1SA_0 -#define DMACN1DA_0 DMAC.N1DA_0 -#define DMACN1TB_0 DMAC.N1TB_0 -#define DMACCRSA_0 DMAC.CRSA_0 -#define DMACCRDA_0 DMAC.CRDA_0 -#define DMACCRTB_0 DMAC.CRTB_0 -#define DMACCHSTAT_0 DMAC.CHSTAT_0 -#define DMACCHCTRL_0 DMAC.CHCTRL_0 -#define DMACCHCFG_0 DMAC.CHCFG_0 -#define DMACCHITVL_0 DMAC.CHITVL_0 -#define DMACCHEXT_0 DMAC.CHEXT_0 -#define DMACNXLA_0 DMAC.NXLA_0 -#define DMACCRLA_0 DMAC.CRLA_0 -#define DMACN0SA_1 DMAC.N0SA_1 -#define DMACN0DA_1 DMAC.N0DA_1 -#define DMACN0TB_1 DMAC.N0TB_1 -#define DMACN1SA_1 DMAC.N1SA_1 -#define DMACN1DA_1 DMAC.N1DA_1 -#define DMACN1TB_1 DMAC.N1TB_1 -#define DMACCRSA_1 DMAC.CRSA_1 -#define DMACCRDA_1 DMAC.CRDA_1 -#define DMACCRTB_1 DMAC.CRTB_1 -#define DMACCHSTAT_1 DMAC.CHSTAT_1 -#define DMACCHCTRL_1 DMAC.CHCTRL_1 -#define DMACCHCFG_1 DMAC.CHCFG_1 -#define DMACCHITVL_1 DMAC.CHITVL_1 -#define DMACCHEXT_1 DMAC.CHEXT_1 -#define DMACNXLA_1 DMAC.NXLA_1 -#define DMACCRLA_1 DMAC.CRLA_1 -#define DMACN0SA_2 DMAC.N0SA_2 -#define DMACN0DA_2 DMAC.N0DA_2 -#define DMACN0TB_2 DMAC.N0TB_2 -#define DMACN1SA_2 DMAC.N1SA_2 -#define DMACN1DA_2 DMAC.N1DA_2 -#define DMACN1TB_2 DMAC.N1TB_2 -#define DMACCRSA_2 DMAC.CRSA_2 -#define DMACCRDA_2 DMAC.CRDA_2 -#define DMACCRTB_2 DMAC.CRTB_2 -#define DMACCHSTAT_2 DMAC.CHSTAT_2 -#define DMACCHCTRL_2 DMAC.CHCTRL_2 -#define DMACCHCFG_2 DMAC.CHCFG_2 -#define DMACCHITVL_2 DMAC.CHITVL_2 -#define DMACCHEXT_2 DMAC.CHEXT_2 -#define DMACNXLA_2 DMAC.NXLA_2 -#define DMACCRLA_2 DMAC.CRLA_2 -#define DMACN0SA_3 DMAC.N0SA_3 -#define DMACN0DA_3 DMAC.N0DA_3 -#define DMACN0TB_3 DMAC.N0TB_3 -#define DMACN1SA_3 DMAC.N1SA_3 -#define DMACN1DA_3 DMAC.N1DA_3 -#define DMACN1TB_3 DMAC.N1TB_3 -#define DMACCRSA_3 DMAC.CRSA_3 -#define DMACCRDA_3 DMAC.CRDA_3 -#define DMACCRTB_3 DMAC.CRTB_3 -#define DMACCHSTAT_3 DMAC.CHSTAT_3 -#define DMACCHCTRL_3 DMAC.CHCTRL_3 -#define DMACCHCFG_3 DMAC.CHCFG_3 -#define DMACCHITVL_3 DMAC.CHITVL_3 -#define DMACCHEXT_3 DMAC.CHEXT_3 -#define DMACNXLA_3 DMAC.NXLA_3 -#define DMACCRLA_3 DMAC.CRLA_3 -#define DMACN0SA_4 DMAC.N0SA_4 -#define DMACN0DA_4 DMAC.N0DA_4 -#define DMACN0TB_4 DMAC.N0TB_4 -#define DMACN1SA_4 DMAC.N1SA_4 -#define DMACN1DA_4 DMAC.N1DA_4 -#define DMACN1TB_4 DMAC.N1TB_4 -#define DMACCRSA_4 DMAC.CRSA_4 -#define DMACCRDA_4 DMAC.CRDA_4 -#define DMACCRTB_4 DMAC.CRTB_4 -#define DMACCHSTAT_4 DMAC.CHSTAT_4 -#define DMACCHCTRL_4 DMAC.CHCTRL_4 -#define DMACCHCFG_4 DMAC.CHCFG_4 -#define DMACCHITVL_4 DMAC.CHITVL_4 -#define DMACCHEXT_4 DMAC.CHEXT_4 -#define DMACNXLA_4 DMAC.NXLA_4 -#define DMACCRLA_4 DMAC.CRLA_4 -#define DMACN0SA_5 DMAC.N0SA_5 -#define DMACN0DA_5 DMAC.N0DA_5 -#define DMACN0TB_5 DMAC.N0TB_5 -#define DMACN1SA_5 DMAC.N1SA_5 -#define DMACN1DA_5 DMAC.N1DA_5 -#define DMACN1TB_5 DMAC.N1TB_5 -#define DMACCRSA_5 DMAC.CRSA_5 -#define DMACCRDA_5 DMAC.CRDA_5 -#define DMACCRTB_5 DMAC.CRTB_5 -#define DMACCHSTAT_5 DMAC.CHSTAT_5 -#define DMACCHCTRL_5 DMAC.CHCTRL_5 -#define DMACCHCFG_5 DMAC.CHCFG_5 -#define DMACCHITVL_5 DMAC.CHITVL_5 -#define DMACCHEXT_5 DMAC.CHEXT_5 -#define DMACNXLA_5 DMAC.NXLA_5 -#define DMACCRLA_5 DMAC.CRLA_5 -#define DMACN0SA_6 DMAC.N0SA_6 -#define DMACN0DA_6 DMAC.N0DA_6 -#define DMACN0TB_6 DMAC.N0TB_6 -#define DMACN1SA_6 DMAC.N1SA_6 -#define DMACN1DA_6 DMAC.N1DA_6 -#define DMACN1TB_6 DMAC.N1TB_6 -#define DMACCRSA_6 DMAC.CRSA_6 -#define DMACCRDA_6 DMAC.CRDA_6 -#define DMACCRTB_6 DMAC.CRTB_6 -#define DMACCHSTAT_6 DMAC.CHSTAT_6 -#define DMACCHCTRL_6 DMAC.CHCTRL_6 -#define DMACCHCFG_6 DMAC.CHCFG_6 -#define DMACCHITVL_6 DMAC.CHITVL_6 -#define DMACCHEXT_6 DMAC.CHEXT_6 -#define DMACNXLA_6 DMAC.NXLA_6 -#define DMACCRLA_6 DMAC.CRLA_6 -#define DMACN0SA_7 DMAC.N0SA_7 -#define DMACN0DA_7 DMAC.N0DA_7 -#define DMACN0TB_7 DMAC.N0TB_7 -#define DMACN1SA_7 DMAC.N1SA_7 -#define DMACN1DA_7 DMAC.N1DA_7 -#define DMACN1TB_7 DMAC.N1TB_7 -#define DMACCRSA_7 DMAC.CRSA_7 -#define DMACCRDA_7 DMAC.CRDA_7 -#define DMACCRTB_7 DMAC.CRTB_7 -#define DMACCHSTAT_7 DMAC.CHSTAT_7 -#define DMACCHCTRL_7 DMAC.CHCTRL_7 -#define DMACCHCFG_7 DMAC.CHCFG_7 -#define DMACCHITVL_7 DMAC.CHITVL_7 -#define DMACCHEXT_7 DMAC.CHEXT_7 -#define DMACNXLA_7 DMAC.NXLA_7 -#define DMACCRLA_7 DMAC.CRLA_7 -#define DMACDCTRL_0_7 DMAC.DCTRL_0_7 -#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7 -#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7 -#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7 -#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7 -#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7 -#define DMACN0SA_8 DMAC.N0SA_8 -#define DMACN0DA_8 DMAC.N0DA_8 -#define DMACN0TB_8 DMAC.N0TB_8 -#define DMACN1SA_8 DMAC.N1SA_8 -#define DMACN1DA_8 DMAC.N1DA_8 -#define DMACN1TB_8 DMAC.N1TB_8 -#define DMACCRSA_8 DMAC.CRSA_8 -#define DMACCRDA_8 DMAC.CRDA_8 -#define DMACCRTB_8 DMAC.CRTB_8 -#define DMACCHSTAT_8 DMAC.CHSTAT_8 -#define DMACCHCTRL_8 DMAC.CHCTRL_8 -#define DMACCHCFG_8 DMAC.CHCFG_8 -#define DMACCHITVL_8 DMAC.CHITVL_8 -#define DMACCHEXT_8 DMAC.CHEXT_8 -#define DMACNXLA_8 DMAC.NXLA_8 -#define DMACCRLA_8 DMAC.CRLA_8 -#define DMACN0SA_9 DMAC.N0SA_9 -#define DMACN0DA_9 DMAC.N0DA_9 -#define DMACN0TB_9 DMAC.N0TB_9 -#define DMACN1SA_9 DMAC.N1SA_9 -#define DMACN1DA_9 DMAC.N1DA_9 -#define DMACN1TB_9 DMAC.N1TB_9 -#define DMACCRSA_9 DMAC.CRSA_9 -#define DMACCRDA_9 DMAC.CRDA_9 -#define DMACCRTB_9 DMAC.CRTB_9 -#define DMACCHSTAT_9 DMAC.CHSTAT_9 -#define DMACCHCTRL_9 DMAC.CHCTRL_9 -#define DMACCHCFG_9 DMAC.CHCFG_9 -#define DMACCHITVL_9 DMAC.CHITVL_9 -#define DMACCHEXT_9 DMAC.CHEXT_9 -#define DMACNXLA_9 DMAC.NXLA_9 -#define DMACCRLA_9 DMAC.CRLA_9 -#define DMACN0SA_10 DMAC.N0SA_10 -#define DMACN0DA_10 DMAC.N0DA_10 -#define DMACN0TB_10 DMAC.N0TB_10 -#define DMACN1SA_10 DMAC.N1SA_10 -#define DMACN1DA_10 DMAC.N1DA_10 -#define DMACN1TB_10 DMAC.N1TB_10 -#define DMACCRSA_10 DMAC.CRSA_10 -#define DMACCRDA_10 DMAC.CRDA_10 -#define DMACCRTB_10 DMAC.CRTB_10 -#define DMACCHSTAT_10 DMAC.CHSTAT_10 -#define DMACCHCTRL_10 DMAC.CHCTRL_10 -#define DMACCHCFG_10 DMAC.CHCFG_10 -#define DMACCHITVL_10 DMAC.CHITVL_10 -#define DMACCHEXT_10 DMAC.CHEXT_10 -#define DMACNXLA_10 DMAC.NXLA_10 -#define DMACCRLA_10 DMAC.CRLA_10 -#define DMACN0SA_11 DMAC.N0SA_11 -#define DMACN0DA_11 DMAC.N0DA_11 -#define DMACN0TB_11 DMAC.N0TB_11 -#define DMACN1SA_11 DMAC.N1SA_11 -#define DMACN1DA_11 DMAC.N1DA_11 -#define DMACN1TB_11 DMAC.N1TB_11 -#define DMACCRSA_11 DMAC.CRSA_11 -#define DMACCRDA_11 DMAC.CRDA_11 -#define DMACCRTB_11 DMAC.CRTB_11 -#define DMACCHSTAT_11 DMAC.CHSTAT_11 -#define DMACCHCTRL_11 DMAC.CHCTRL_11 -#define DMACCHCFG_11 DMAC.CHCFG_11 -#define DMACCHITVL_11 DMAC.CHITVL_11 -#define DMACCHEXT_11 DMAC.CHEXT_11 -#define DMACNXLA_11 DMAC.NXLA_11 -#define DMACCRLA_11 DMAC.CRLA_11 -#define DMACN0SA_12 DMAC.N0SA_12 -#define DMACN0DA_12 DMAC.N0DA_12 -#define DMACN0TB_12 DMAC.N0TB_12 -#define DMACN1SA_12 DMAC.N1SA_12 -#define DMACN1DA_12 DMAC.N1DA_12 -#define DMACN1TB_12 DMAC.N1TB_12 -#define DMACCRSA_12 DMAC.CRSA_12 -#define DMACCRDA_12 DMAC.CRDA_12 -#define DMACCRTB_12 DMAC.CRTB_12 -#define DMACCHSTAT_12 DMAC.CHSTAT_12 -#define DMACCHCTRL_12 DMAC.CHCTRL_12 -#define DMACCHCFG_12 DMAC.CHCFG_12 -#define DMACCHITVL_12 DMAC.CHITVL_12 -#define DMACCHEXT_12 DMAC.CHEXT_12 -#define DMACNXLA_12 DMAC.NXLA_12 -#define DMACCRLA_12 DMAC.CRLA_12 -#define DMACN0SA_13 DMAC.N0SA_13 -#define DMACN0DA_13 DMAC.N0DA_13 -#define DMACN0TB_13 DMAC.N0TB_13 -#define DMACN1SA_13 DMAC.N1SA_13 -#define DMACN1DA_13 DMAC.N1DA_13 -#define DMACN1TB_13 DMAC.N1TB_13 -#define DMACCRSA_13 DMAC.CRSA_13 -#define DMACCRDA_13 DMAC.CRDA_13 -#define DMACCRTB_13 DMAC.CRTB_13 -#define DMACCHSTAT_13 DMAC.CHSTAT_13 -#define DMACCHCTRL_13 DMAC.CHCTRL_13 -#define DMACCHCFG_13 DMAC.CHCFG_13 -#define DMACCHITVL_13 DMAC.CHITVL_13 -#define DMACCHEXT_13 DMAC.CHEXT_13 -#define DMACNXLA_13 DMAC.NXLA_13 -#define DMACCRLA_13 DMAC.CRLA_13 -#define DMACN0SA_14 DMAC.N0SA_14 -#define DMACN0DA_14 DMAC.N0DA_14 -#define DMACN0TB_14 DMAC.N0TB_14 -#define DMACN1SA_14 DMAC.N1SA_14 -#define DMACN1DA_14 DMAC.N1DA_14 -#define DMACN1TB_14 DMAC.N1TB_14 -#define DMACCRSA_14 DMAC.CRSA_14 -#define DMACCRDA_14 DMAC.CRDA_14 -#define DMACCRTB_14 DMAC.CRTB_14 -#define DMACCHSTAT_14 DMAC.CHSTAT_14 -#define DMACCHCTRL_14 DMAC.CHCTRL_14 -#define DMACCHCFG_14 DMAC.CHCFG_14 -#define DMACCHITVL_14 DMAC.CHITVL_14 -#define DMACCHEXT_14 DMAC.CHEXT_14 -#define DMACNXLA_14 DMAC.NXLA_14 -#define DMACCRLA_14 DMAC.CRLA_14 -#define DMACN0SA_15 DMAC.N0SA_15 -#define DMACN0DA_15 DMAC.N0DA_15 -#define DMACN0TB_15 DMAC.N0TB_15 -#define DMACN1SA_15 DMAC.N1SA_15 -#define DMACN1DA_15 DMAC.N1DA_15 -#define DMACN1TB_15 DMAC.N1TB_15 -#define DMACCRSA_15 DMAC.CRSA_15 -#define DMACCRDA_15 DMAC.CRDA_15 -#define DMACCRTB_15 DMAC.CRTB_15 -#define DMACCHSTAT_15 DMAC.CHSTAT_15 -#define DMACCHCTRL_15 DMAC.CHCTRL_15 -#define DMACCHCFG_15 DMAC.CHCFG_15 -#define DMACCHITVL_15 DMAC.CHITVL_15 -#define DMACCHEXT_15 DMAC.CHEXT_15 -#define DMACNXLA_15 DMAC.NXLA_15 -#define DMACCRLA_15 DMAC.CRLA_15 -#define DMACDCTRL_8_15 DMAC.DCTRL_8_15 -#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15 -#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15 -#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15 -#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15 -#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15 -#define DMACDMARS0 DMAC.DMARS0 -#define DMACDMARS1 DMAC.DMARS1 -#define DMACDMARS2 DMAC.DMARS2 -#define DMACDMARS3 DMAC.DMARS3 -#define DMACDMARS4 DMAC.DMARS4 -#define DMACDMARS5 DMAC.DMARS5 -#define DMACDMARS6 DMAC.DMARS6 -#define DMACDMARS7 DMAC.DMARS7 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h index 6c28acb009..54bd656227 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h @@ -18,40 +18,289 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : dvdec_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef DVDEC_IODEFINE_H #define DVDEC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_dvdec -{ /* DVDEC */ +#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */ +#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */ + + +/* Start of channel array defines of DVDEC */ + +/* Channel array defines of DVDEC */ +/*(Sample) value = DVDEC[ channel ]->ADCCR1; */ +#define DVDEC_COUNT (2) +#define DVDEC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DVDEC0, &DVDEC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of DVDEC */ + + +#define ADCCR1_1 (DVDEC1.ADCCR1) +#define TGCR1_1 (DVDEC1.TGCR1) +#define TGCR2_1 (DVDEC1.TGCR2) +#define TGCR3_1 (DVDEC1.TGCR3) +#define SYNSCR1_1 (DVDEC1.SYNSCR1) +#define SYNSCR2_1 (DVDEC1.SYNSCR2) +#define SYNSCR3_1 (DVDEC1.SYNSCR3) +#define SYNSCR4_1 (DVDEC1.SYNSCR4) +#define SYNSCR5_1 (DVDEC1.SYNSCR5) +#define HAFCCR1_1 (DVDEC1.HAFCCR1) +#define HAFCCR2_1 (DVDEC1.HAFCCR2) +#define HAFCCR3_1 (DVDEC1.HAFCCR3) +#define VCDWCR1_1 (DVDEC1.VCDWCR1) +#define DCPCR1_1 (DVDEC1.DCPCR1) +#define DCPCR2_1 (DVDEC1.DCPCR2) +#define DCPCR3_1 (DVDEC1.DCPCR3) +#define DCPCR4_1 (DVDEC1.DCPCR4) +#define DCPCR5_1 (DVDEC1.DCPCR5) +#define DCPCR6_1 (DVDEC1.DCPCR6) +#define DCPCR7_1 (DVDEC1.DCPCR7) +#define DCPCR8_1 (DVDEC1.DCPCR8) +#define NSDCR_1 (DVDEC1.NSDCR) +#define BTLCR_1 (DVDEC1.BTLCR) +#define BTGPCR_1 (DVDEC1.BTGPCR) +#define ACCCR1_1 (DVDEC1.ACCCR1) +#define ACCCR2_1 (DVDEC1.ACCCR2) +#define ACCCR3_1 (DVDEC1.ACCCR3) +#define TINTCR_1 (DVDEC1.TINTCR) +#define YCDCR_1 (DVDEC1.YCDCR) +#define AGCCR1_1 (DVDEC1.AGCCR1) +#define AGCCR2_1 (DVDEC1.AGCCR2) +#define PKLIMITCR_1 (DVDEC1.PKLIMITCR) +#define RGORCR1_1 (DVDEC1.RGORCR1) +#define RGORCR2_1 (DVDEC1.RGORCR2) +#define RGORCR3_1 (DVDEC1.RGORCR3) +#define RGORCR4_1 (DVDEC1.RGORCR4) +#define RGORCR5_1 (DVDEC1.RGORCR5) +#define RGORCR6_1 (DVDEC1.RGORCR6) +#define RGORCR7_1 (DVDEC1.RGORCR7) +#define AFCPFCR_1 (DVDEC1.AFCPFCR) +#define RUPDCR_1 (DVDEC1.RUPDCR) +#define VSYNCSR_1 (DVDEC1.VSYNCSR) +#define HSYNCSR_1 (DVDEC1.HSYNCSR) +#define DCPSR1_1 (DVDEC1.DCPSR1) +#define DCPSR2_1 (DVDEC1.DCPSR2) +#define NSDSR_1 (DVDEC1.NSDSR) +#define CROMASR1_1 (DVDEC1.CROMASR1) +#define CROMASR2_1 (DVDEC1.CROMASR2) +#define SYNCSSR_1 (DVDEC1.SYNCSSR) +#define AGCCSR1_1 (DVDEC1.AGCCSR1) +#define AGCCSR2_1 (DVDEC1.AGCCSR2) +#define YCSCR3_1 (DVDEC1.YCSCR3) +#define YCSCR4_1 (DVDEC1.YCSCR4) +#define YCSCR5_1 (DVDEC1.YCSCR5) +#define YCSCR6_1 (DVDEC1.YCSCR6) +#define YCSCR7_1 (DVDEC1.YCSCR7) +#define YCSCR8_1 (DVDEC1.YCSCR8) +#define YCSCR9_1 (DVDEC1.YCSCR9) +#define YCSCR11_1 (DVDEC1.YCSCR11) +#define YCSCR12_1 (DVDEC1.YCSCR12) +#define DCPCR9_1 (DVDEC1.DCPCR9) +#define YCTWA_F0_1 (DVDEC1.YCTWA_F0) +#define YCTWA_F1_1 (DVDEC1.YCTWA_F1) +#define YCTWA_F2_1 (DVDEC1.YCTWA_F2) +#define YCTWA_F3_1 (DVDEC1.YCTWA_F3) +#define YCTWA_F4_1 (DVDEC1.YCTWA_F4) +#define YCTWA_F5_1 (DVDEC1.YCTWA_F5) +#define YCTWA_F6_1 (DVDEC1.YCTWA_F6) +#define YCTWA_F7_1 (DVDEC1.YCTWA_F7) +#define YCTWA_F8_1 (DVDEC1.YCTWA_F8) +#define YCTWB_F0_1 (DVDEC1.YCTWB_F0) +#define YCTWB_F1_1 (DVDEC1.YCTWB_F1) +#define YCTWB_F2_1 (DVDEC1.YCTWB_F2) +#define YCTWB_F3_1 (DVDEC1.YCTWB_F3) +#define YCTWB_F4_1 (DVDEC1.YCTWB_F4) +#define YCTWB_F5_1 (DVDEC1.YCTWB_F5) +#define YCTWB_F6_1 (DVDEC1.YCTWB_F6) +#define YCTWB_F7_1 (DVDEC1.YCTWB_F7) +#define YCTWB_F8_1 (DVDEC1.YCTWB_F8) +#define YCTNA_F0_1 (DVDEC1.YCTNA_F0) +#define YCTNA_F1_1 (DVDEC1.YCTNA_F1) +#define YCTNA_F2_1 (DVDEC1.YCTNA_F2) +#define YCTNA_F3_1 (DVDEC1.YCTNA_F3) +#define YCTNA_F4_1 (DVDEC1.YCTNA_F4) +#define YCTNA_F5_1 (DVDEC1.YCTNA_F5) +#define YCTNA_F6_1 (DVDEC1.YCTNA_F6) +#define YCTNA_F7_1 (DVDEC1.YCTNA_F7) +#define YCTNA_F8_1 (DVDEC1.YCTNA_F8) +#define YCTNB_F0_1 (DVDEC1.YCTNB_F0) +#define YCTNB_F1_1 (DVDEC1.YCTNB_F1) +#define YCTNB_F2_1 (DVDEC1.YCTNB_F2) +#define YCTNB_F3_1 (DVDEC1.YCTNB_F3) +#define YCTNB_F4_1 (DVDEC1.YCTNB_F4) +#define YCTNB_F5_1 (DVDEC1.YCTNB_F5) +#define YCTNB_F6_1 (DVDEC1.YCTNB_F6) +#define YCTNB_F7_1 (DVDEC1.YCTNB_F7) +#define YCTNB_F8_1 (DVDEC1.YCTNB_F8) +#define YGAINCR_1 (DVDEC1.YGAINCR) +#define CBGAINCR_1 (DVDEC1.CBGAINCR) +#define CRGAINCR_1 (DVDEC1.CRGAINCR) +#define PGA_UPDATE_1 (DVDEC1.PGA_UPDATE) +#define PGACR_1 (DVDEC1.PGACR) +#define ADCCR2_1 (DVDEC1.ADCCR2) +#define ADCCR1_0 (DVDEC0.ADCCR1) +#define TGCR1_0 (DVDEC0.TGCR1) +#define TGCR2_0 (DVDEC0.TGCR2) +#define TGCR3_0 (DVDEC0.TGCR3) +#define SYNSCR1_0 (DVDEC0.SYNSCR1) +#define SYNSCR2_0 (DVDEC0.SYNSCR2) +#define SYNSCR3_0 (DVDEC0.SYNSCR3) +#define SYNSCR4_0 (DVDEC0.SYNSCR4) +#define SYNSCR5_0 (DVDEC0.SYNSCR5) +#define HAFCCR1_0 (DVDEC0.HAFCCR1) +#define HAFCCR2_0 (DVDEC0.HAFCCR2) +#define HAFCCR3_0 (DVDEC0.HAFCCR3) +#define VCDWCR1_0 (DVDEC0.VCDWCR1) +#define DCPCR1_0 (DVDEC0.DCPCR1) +#define DCPCR2_0 (DVDEC0.DCPCR2) +#define DCPCR3_0 (DVDEC0.DCPCR3) +#define DCPCR4_0 (DVDEC0.DCPCR4) +#define DCPCR5_0 (DVDEC0.DCPCR5) +#define DCPCR6_0 (DVDEC0.DCPCR6) +#define DCPCR7_0 (DVDEC0.DCPCR7) +#define DCPCR8_0 (DVDEC0.DCPCR8) +#define NSDCR_0 (DVDEC0.NSDCR) +#define BTLCR_0 (DVDEC0.BTLCR) +#define BTGPCR_0 (DVDEC0.BTGPCR) +#define ACCCR1_0 (DVDEC0.ACCCR1) +#define ACCCR2_0 (DVDEC0.ACCCR2) +#define ACCCR3_0 (DVDEC0.ACCCR3) +#define TINTCR_0 (DVDEC0.TINTCR) +#define YCDCR_0 (DVDEC0.YCDCR) +#define AGCCR1_0 (DVDEC0.AGCCR1) +#define AGCCR2_0 (DVDEC0.AGCCR2) +#define PKLIMITCR_0 (DVDEC0.PKLIMITCR) +#define RGORCR1_0 (DVDEC0.RGORCR1) +#define RGORCR2_0 (DVDEC0.RGORCR2) +#define RGORCR3_0 (DVDEC0.RGORCR3) +#define RGORCR4_0 (DVDEC0.RGORCR4) +#define RGORCR5_0 (DVDEC0.RGORCR5) +#define RGORCR6_0 (DVDEC0.RGORCR6) +#define RGORCR7_0 (DVDEC0.RGORCR7) +#define AFCPFCR_0 (DVDEC0.AFCPFCR) +#define RUPDCR_0 (DVDEC0.RUPDCR) +#define VSYNCSR_0 (DVDEC0.VSYNCSR) +#define HSYNCSR_0 (DVDEC0.HSYNCSR) +#define DCPSR1_0 (DVDEC0.DCPSR1) +#define DCPSR2_0 (DVDEC0.DCPSR2) +#define NSDSR_0 (DVDEC0.NSDSR) +#define CROMASR1_0 (DVDEC0.CROMASR1) +#define CROMASR2_0 (DVDEC0.CROMASR2) +#define SYNCSSR_0 (DVDEC0.SYNCSSR) +#define AGCCSR1_0 (DVDEC0.AGCCSR1) +#define AGCCSR2_0 (DVDEC0.AGCCSR2) +#define YCSCR3_0 (DVDEC0.YCSCR3) +#define YCSCR4_0 (DVDEC0.YCSCR4) +#define YCSCR5_0 (DVDEC0.YCSCR5) +#define YCSCR6_0 (DVDEC0.YCSCR6) +#define YCSCR7_0 (DVDEC0.YCSCR7) +#define YCSCR8_0 (DVDEC0.YCSCR8) +#define YCSCR9_0 (DVDEC0.YCSCR9) +#define YCSCR11_0 (DVDEC0.YCSCR11) +#define YCSCR12_0 (DVDEC0.YCSCR12) +#define DCPCR9_0 (DVDEC0.DCPCR9) +#define YCTWA_F0_0 (DVDEC0.YCTWA_F0) +#define YCTWA_F1_0 (DVDEC0.YCTWA_F1) +#define YCTWA_F2_0 (DVDEC0.YCTWA_F2) +#define YCTWA_F3_0 (DVDEC0.YCTWA_F3) +#define YCTWA_F4_0 (DVDEC0.YCTWA_F4) +#define YCTWA_F5_0 (DVDEC0.YCTWA_F5) +#define YCTWA_F6_0 (DVDEC0.YCTWA_F6) +#define YCTWA_F7_0 (DVDEC0.YCTWA_F7) +#define YCTWA_F8_0 (DVDEC0.YCTWA_F8) +#define YCTWB_F0_0 (DVDEC0.YCTWB_F0) +#define YCTWB_F1_0 (DVDEC0.YCTWB_F1) +#define YCTWB_F2_0 (DVDEC0.YCTWB_F2) +#define YCTWB_F3_0 (DVDEC0.YCTWB_F3) +#define YCTWB_F4_0 (DVDEC0.YCTWB_F4) +#define YCTWB_F5_0 (DVDEC0.YCTWB_F5) +#define YCTWB_F6_0 (DVDEC0.YCTWB_F6) +#define YCTWB_F7_0 (DVDEC0.YCTWB_F7) +#define YCTWB_F8_0 (DVDEC0.YCTWB_F8) +#define YCTNA_F0_0 (DVDEC0.YCTNA_F0) +#define YCTNA_F1_0 (DVDEC0.YCTNA_F1) +#define YCTNA_F2_0 (DVDEC0.YCTNA_F2) +#define YCTNA_F3_0 (DVDEC0.YCTNA_F3) +#define YCTNA_F4_0 (DVDEC0.YCTNA_F4) +#define YCTNA_F5_0 (DVDEC0.YCTNA_F5) +#define YCTNA_F6_0 (DVDEC0.YCTNA_F6) +#define YCTNA_F7_0 (DVDEC0.YCTNA_F7) +#define YCTNA_F8_0 (DVDEC0.YCTNA_F8) +#define YCTNB_F0_0 (DVDEC0.YCTNB_F0) +#define YCTNB_F1_0 (DVDEC0.YCTNB_F1) +#define YCTNB_F2_0 (DVDEC0.YCTNB_F2) +#define YCTNB_F3_0 (DVDEC0.YCTNB_F3) +#define YCTNB_F4_0 (DVDEC0.YCTNB_F4) +#define YCTNB_F5_0 (DVDEC0.YCTNB_F5) +#define YCTNB_F6_0 (DVDEC0.YCTNB_F6) +#define YCTNB_F7_0 (DVDEC0.YCTNB_F7) +#define YCTNB_F8_0 (DVDEC0.YCTNB_F8) +#define YGAINCR_0 (DVDEC0.YGAINCR) +#define CBGAINCR_0 (DVDEC0.CBGAINCR) +#define CRGAINCR_0 (DVDEC0.CRGAINCR) +#define PGA_UPDATE_0 (DVDEC0.PGA_UPDATE) +#define PGACR_0 (DVDEC0.PGACR) +#define ADCCR2_0 (DVDEC0.ADCCR2) + +#define DVDEC_TGCRn_COUNT (3) +#define DVDEC_SYNSCRn_COUNT (5) +#define DVDEC_HAFCCRn_COUNT (3) +#define DVDEC_DCPCRn_COUNT (8) +#define DVDEC_ACCCRn_COUNT (3) +#define DVDEC_AGCCRn_COUNT (2) +#define DVDEC_RGORCRn_COUNT (7) +#define DVDEC_DCPSRn_COUNT (2) +#define DVDEC_CROMASRn_COUNT (2) +#define DVDEC_AGCCSRn_COUNT (2) +#define DVDEC_YCSCRn_COUNT (7) +#define DVDEC_YCTWA_Fn_COUNT (9) +#define DVDEC_YCTWB_Fn_COUNT (9) +#define DVDEC_YCTNA_Fn_COUNT (9) +#define DVDEC_YCTNB_Fn_COUNT (9) + + +typedef struct st_dvdec +{ + /* DVDEC */ volatile uint16_t ADCCR1; /* ADCCR1 */ volatile uint8_t dummy1[4]; /* */ -#define DVDEC_TGCRn_COUNT 3 + +/* #define DVDEC_TGCRn_COUNT (3) */ volatile uint16_t TGCR1; /* TGCR1 */ volatile uint16_t TGCR2; /* TGCR2 */ volatile uint16_t TGCR3; /* TGCR3 */ volatile uint8_t dummy2[6]; /* */ -#define DVDEC_SYNSCRn_COUNT 5 + +/* #define DVDEC_SYNSCRn_COUNT (5) */ volatile uint16_t SYNSCR1; /* SYNSCR1 */ volatile uint16_t SYNSCR2; /* SYNSCR2 */ volatile uint16_t SYNSCR3; /* SYNSCR3 */ volatile uint16_t SYNSCR4; /* SYNSCR4 */ volatile uint16_t SYNSCR5; /* SYNSCR5 */ -#define DVDEC_HAFCCRn_COUNT 3 + +/* #define DVDEC_HAFCCRn_COUNT (3) */ volatile uint16_t HAFCCR1; /* HAFCCR1 */ volatile uint16_t HAFCCR2; /* HAFCCR2 */ volatile uint16_t HAFCCR3; /* HAFCCR3 */ volatile uint16_t VCDWCR1; /* VCDWCR1 */ volatile uint8_t dummy3[4]; /* */ -#define DVDEC_DCPCRn_COUNT 8 + +/* #define DVDEC_DCPCRn_COUNT (8) */ volatile uint16_t DCPCR1; /* DCPCR1 */ volatile uint16_t DCPCR2; /* DCPCR2 */ volatile uint16_t DCPCR3; /* DCPCR3 */ @@ -63,17 +312,20 @@ struct st_dvdec volatile uint16_t NSDCR; /* NSDCR */ volatile uint16_t BTLCR; /* BTLCR */ volatile uint16_t BTGPCR; /* BTGPCR */ -#define DVDEC_ACCCRn_COUNT 3 + +/* #define DVDEC_ACCCRn_COUNT (3) */ volatile uint16_t ACCCR1; /* ACCCR1 */ volatile uint16_t ACCCR2; /* ACCCR2 */ volatile uint16_t ACCCR3; /* ACCCR3 */ volatile uint16_t TINTCR; /* TINTCR */ volatile uint16_t YCDCR; /* YCDCR */ -#define DVDEC_AGCCRn_COUNT 2 + +/* #define DVDEC_AGCCRn_COUNT (2) */ volatile uint16_t AGCCR1; /* AGCCR1 */ volatile uint16_t AGCCR2; /* AGCCR2 */ volatile uint16_t PKLIMITCR; /* PKLIMITCR */ -#define DVDEC_RGORCRn_COUNT 7 + +/* #define DVDEC_RGORCRn_COUNT (7) */ volatile uint16_t RGORCR1; /* RGORCR1 */ volatile uint16_t RGORCR2; /* RGORCR2 */ volatile uint16_t RGORCR3; /* RGORCR3 */ @@ -86,20 +338,24 @@ struct st_dvdec volatile uint16_t RUPDCR; /* RUPDCR */ volatile uint16_t VSYNCSR; /* VSYNCSR */ volatile uint16_t HSYNCSR; /* HSYNCSR */ -#define DVDEC_DCPSRn_COUNT 2 + +/* #define DVDEC_DCPSRn_COUNT (2) */ volatile uint16_t DCPSR1; /* DCPSR1 */ volatile uint16_t DCPSR2; /* DCPSR2 */ volatile uint8_t dummy5[4]; /* */ volatile uint16_t NSDSR; /* NSDSR */ -#define DVDEC_CROMASRn_COUNT 2 + +/* #define DVDEC_CROMASRn_COUNT (2) */ volatile uint16_t CROMASR1; /* CROMASR1 */ volatile uint16_t CROMASR2; /* CROMASR2 */ volatile uint16_t SYNCSSR; /* SYNCSSR */ -#define DVDEC_AGCCSRn_COUNT 2 + +/* #define DVDEC_AGCCSRn_COUNT (2) */ volatile uint16_t AGCCSR1; /* AGCCSR1 */ volatile uint16_t AGCCSR2; /* AGCCSR2 */ volatile uint8_t dummy6[108]; /* */ -#define DVDEC_YCSCRn_COUNT 7 + +/* #define DVDEC_YCSCRn_COUNT (7) */ volatile uint16_t YCSCR3; /* YCSCR3 */ volatile uint16_t YCSCR4; /* YCSCR4 */ volatile uint16_t YCSCR5; /* YCSCR5 */ @@ -113,7 +369,8 @@ struct st_dvdec volatile uint8_t dummy8[104]; /* */ volatile uint16_t DCPCR9; /* DCPCR9 */ volatile uint8_t dummy9[16]; /* */ -#define DVDEC_YCTWA_Fn_COUNT 9 + +/* #define DVDEC_YCTWA_Fn_COUNT (9) */ volatile uint16_t YCTWA_F0; /* YCTWA_F0 */ volatile uint16_t YCTWA_F1; /* YCTWA_F1 */ volatile uint16_t YCTWA_F2; /* YCTWA_F2 */ @@ -123,7 +380,8 @@ struct st_dvdec volatile uint16_t YCTWA_F6; /* YCTWA_F6 */ volatile uint16_t YCTWA_F7; /* YCTWA_F7 */ volatile uint16_t YCTWA_F8; /* YCTWA_F8 */ -#define DVDEC_YCTWB_Fn_COUNT 9 + +/* #define DVDEC_YCTWB_Fn_COUNT (9) */ volatile uint16_t YCTWB_F0; /* YCTWB_F0 */ volatile uint16_t YCTWB_F1; /* YCTWB_F1 */ volatile uint16_t YCTWB_F2; /* YCTWB_F2 */ @@ -133,7 +391,8 @@ struct st_dvdec volatile uint16_t YCTWB_F6; /* YCTWB_F6 */ volatile uint16_t YCTWB_F7; /* YCTWB_F7 */ volatile uint16_t YCTWB_F8; /* YCTWB_F8 */ -#define DVDEC_YCTNA_Fn_COUNT 9 + +/* #define DVDEC_YCTNA_Fn_COUNT (9) */ volatile uint16_t YCTNA_F0; /* YCTNA_F0 */ volatile uint16_t YCTNA_F1; /* YCTNA_F1 */ volatile uint16_t YCTNA_F2; /* YCTNA_F2 */ @@ -143,7 +402,8 @@ struct st_dvdec volatile uint16_t YCTNA_F6; /* YCTNA_F6 */ volatile uint16_t YCTNA_F7; /* YCTNA_F7 */ volatile uint16_t YCTNA_F8; /* YCTNA_F8 */ -#define DVDEC_YCTNB_Fn_COUNT 9 + +/* #define DVDEC_YCTNB_Fn_COUNT (9) */ volatile uint16_t YCTNB_F0; /* YCTNB_F0 */ volatile uint16_t YCTNB_F1; /* YCTNB_F1 */ volatile uint16_t YCTNB_F2; /* YCTNB_F2 */ @@ -161,231 +421,21 @@ struct st_dvdec volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */ volatile uint16_t PGACR; /* PGACR */ volatile uint16_t ADCCR2; /* ADCCR2 */ -}; +} r_io_dvdec_t; -#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */ -#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */ +/* Channel array defines of DVDEC (2)*/ +#ifdef DECLARE_DVDEC_CHANNELS +volatile struct st_dvdec* DVDEC[ DVDEC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DVDEC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DVDEC_CHANNELS */ +/* End of channel array defines of DVDEC (2)*/ -/* Start of channnel array defines of DVDEC */ - -/* Channnel array defines of DVDEC */ -/*(Sample) value = DVDEC[ channel ]->ADCCR1; */ -#define DVDEC_COUNT 2 -#define DVDEC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DVDEC0, &DVDEC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of DVDEC */ - - -#define ADCCR1_1 DVDEC1.ADCCR1 -#define TGCR1_1 DVDEC1.TGCR1 -#define TGCR2_1 DVDEC1.TGCR2 -#define TGCR3_1 DVDEC1.TGCR3 -#define SYNSCR1_1 DVDEC1.SYNSCR1 -#define SYNSCR2_1 DVDEC1.SYNSCR2 -#define SYNSCR3_1 DVDEC1.SYNSCR3 -#define SYNSCR4_1 DVDEC1.SYNSCR4 -#define SYNSCR5_1 DVDEC1.SYNSCR5 -#define HAFCCR1_1 DVDEC1.HAFCCR1 -#define HAFCCR2_1 DVDEC1.HAFCCR2 -#define HAFCCR3_1 DVDEC1.HAFCCR3 -#define VCDWCR1_1 DVDEC1.VCDWCR1 -#define DCPCR1_1 DVDEC1.DCPCR1 -#define DCPCR2_1 DVDEC1.DCPCR2 -#define DCPCR3_1 DVDEC1.DCPCR3 -#define DCPCR4_1 DVDEC1.DCPCR4 -#define DCPCR5_1 DVDEC1.DCPCR5 -#define DCPCR6_1 DVDEC1.DCPCR6 -#define DCPCR7_1 DVDEC1.DCPCR7 -#define DCPCR8_1 DVDEC1.DCPCR8 -#define NSDCR_1 DVDEC1.NSDCR -#define BTLCR_1 DVDEC1.BTLCR -#define BTGPCR_1 DVDEC1.BTGPCR -#define ACCCR1_1 DVDEC1.ACCCR1 -#define ACCCR2_1 DVDEC1.ACCCR2 -#define ACCCR3_1 DVDEC1.ACCCR3 -#define TINTCR_1 DVDEC1.TINTCR -#define YCDCR_1 DVDEC1.YCDCR -#define AGCCR1_1 DVDEC1.AGCCR1 -#define AGCCR2_1 DVDEC1.AGCCR2 -#define PKLIMITCR_1 DVDEC1.PKLIMITCR -#define RGORCR1_1 DVDEC1.RGORCR1 -#define RGORCR2_1 DVDEC1.RGORCR2 -#define RGORCR3_1 DVDEC1.RGORCR3 -#define RGORCR4_1 DVDEC1.RGORCR4 -#define RGORCR5_1 DVDEC1.RGORCR5 -#define RGORCR6_1 DVDEC1.RGORCR6 -#define RGORCR7_1 DVDEC1.RGORCR7 -#define AFCPFCR_1 DVDEC1.AFCPFCR -#define RUPDCR_1 DVDEC1.RUPDCR -#define VSYNCSR_1 DVDEC1.VSYNCSR -#define HSYNCSR_1 DVDEC1.HSYNCSR -#define DCPSR1_1 DVDEC1.DCPSR1 -#define DCPSR2_1 DVDEC1.DCPSR2 -#define NSDSR_1 DVDEC1.NSDSR -#define CROMASR1_1 DVDEC1.CROMASR1 -#define CROMASR2_1 DVDEC1.CROMASR2 -#define SYNCSSR_1 DVDEC1.SYNCSSR -#define AGCCSR1_1 DVDEC1.AGCCSR1 -#define AGCCSR2_1 DVDEC1.AGCCSR2 -#define YCSCR3_1 DVDEC1.YCSCR3 -#define YCSCR4_1 DVDEC1.YCSCR4 -#define YCSCR5_1 DVDEC1.YCSCR5 -#define YCSCR6_1 DVDEC1.YCSCR6 -#define YCSCR7_1 DVDEC1.YCSCR7 -#define YCSCR8_1 DVDEC1.YCSCR8 -#define YCSCR9_1 DVDEC1.YCSCR9 -#define YCSCR11_1 DVDEC1.YCSCR11 -#define YCSCR12_1 DVDEC1.YCSCR12 -#define DCPCR9_1 DVDEC1.DCPCR9 -#define YCTWA_F0_1 DVDEC1.YCTWA_F0 -#define YCTWA_F1_1 DVDEC1.YCTWA_F1 -#define YCTWA_F2_1 DVDEC1.YCTWA_F2 -#define YCTWA_F3_1 DVDEC1.YCTWA_F3 -#define YCTWA_F4_1 DVDEC1.YCTWA_F4 -#define YCTWA_F5_1 DVDEC1.YCTWA_F5 -#define YCTWA_F6_1 DVDEC1.YCTWA_F6 -#define YCTWA_F7_1 DVDEC1.YCTWA_F7 -#define YCTWA_F8_1 DVDEC1.YCTWA_F8 -#define YCTWB_F0_1 DVDEC1.YCTWB_F0 -#define YCTWB_F1_1 DVDEC1.YCTWB_F1 -#define YCTWB_F2_1 DVDEC1.YCTWB_F2 -#define YCTWB_F3_1 DVDEC1.YCTWB_F3 -#define YCTWB_F4_1 DVDEC1.YCTWB_F4 -#define YCTWB_F5_1 DVDEC1.YCTWB_F5 -#define YCTWB_F6_1 DVDEC1.YCTWB_F6 -#define YCTWB_F7_1 DVDEC1.YCTWB_F7 -#define YCTWB_F8_1 DVDEC1.YCTWB_F8 -#define YCTNA_F0_1 DVDEC1.YCTNA_F0 -#define YCTNA_F1_1 DVDEC1.YCTNA_F1 -#define YCTNA_F2_1 DVDEC1.YCTNA_F2 -#define YCTNA_F3_1 DVDEC1.YCTNA_F3 -#define YCTNA_F4_1 DVDEC1.YCTNA_F4 -#define YCTNA_F5_1 DVDEC1.YCTNA_F5 -#define YCTNA_F6_1 DVDEC1.YCTNA_F6 -#define YCTNA_F7_1 DVDEC1.YCTNA_F7 -#define YCTNA_F8_1 DVDEC1.YCTNA_F8 -#define YCTNB_F0_1 DVDEC1.YCTNB_F0 -#define YCTNB_F1_1 DVDEC1.YCTNB_F1 -#define YCTNB_F2_1 DVDEC1.YCTNB_F2 -#define YCTNB_F3_1 DVDEC1.YCTNB_F3 -#define YCTNB_F4_1 DVDEC1.YCTNB_F4 -#define YCTNB_F5_1 DVDEC1.YCTNB_F5 -#define YCTNB_F6_1 DVDEC1.YCTNB_F6 -#define YCTNB_F7_1 DVDEC1.YCTNB_F7 -#define YCTNB_F8_1 DVDEC1.YCTNB_F8 -#define YGAINCR_1 DVDEC1.YGAINCR -#define CBGAINCR_1 DVDEC1.CBGAINCR -#define CRGAINCR_1 DVDEC1.CRGAINCR -#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE -#define PGACR_1 DVDEC1.PGACR -#define ADCCR2_1 DVDEC1.ADCCR2 -#define ADCCR1_0 DVDEC0.ADCCR1 -#define TGCR1_0 DVDEC0.TGCR1 -#define TGCR2_0 DVDEC0.TGCR2 -#define TGCR3_0 DVDEC0.TGCR3 -#define SYNSCR1_0 DVDEC0.SYNSCR1 -#define SYNSCR2_0 DVDEC0.SYNSCR2 -#define SYNSCR3_0 DVDEC0.SYNSCR3 -#define SYNSCR4_0 DVDEC0.SYNSCR4 -#define SYNSCR5_0 DVDEC0.SYNSCR5 -#define HAFCCR1_0 DVDEC0.HAFCCR1 -#define HAFCCR2_0 DVDEC0.HAFCCR2 -#define HAFCCR3_0 DVDEC0.HAFCCR3 -#define VCDWCR1_0 DVDEC0.VCDWCR1 -#define DCPCR1_0 DVDEC0.DCPCR1 -#define DCPCR2_0 DVDEC0.DCPCR2 -#define DCPCR3_0 DVDEC0.DCPCR3 -#define DCPCR4_0 DVDEC0.DCPCR4 -#define DCPCR5_0 DVDEC0.DCPCR5 -#define DCPCR6_0 DVDEC0.DCPCR6 -#define DCPCR7_0 DVDEC0.DCPCR7 -#define DCPCR8_0 DVDEC0.DCPCR8 -#define NSDCR_0 DVDEC0.NSDCR -#define BTLCR_0 DVDEC0.BTLCR -#define BTGPCR_0 DVDEC0.BTGPCR -#define ACCCR1_0 DVDEC0.ACCCR1 -#define ACCCR2_0 DVDEC0.ACCCR2 -#define ACCCR3_0 DVDEC0.ACCCR3 -#define TINTCR_0 DVDEC0.TINTCR -#define YCDCR_0 DVDEC0.YCDCR -#define AGCCR1_0 DVDEC0.AGCCR1 -#define AGCCR2_0 DVDEC0.AGCCR2 -#define PKLIMITCR_0 DVDEC0.PKLIMITCR -#define RGORCR1_0 DVDEC0.RGORCR1 -#define RGORCR2_0 DVDEC0.RGORCR2 -#define RGORCR3_0 DVDEC0.RGORCR3 -#define RGORCR4_0 DVDEC0.RGORCR4 -#define RGORCR5_0 DVDEC0.RGORCR5 -#define RGORCR6_0 DVDEC0.RGORCR6 -#define RGORCR7_0 DVDEC0.RGORCR7 -#define AFCPFCR_0 DVDEC0.AFCPFCR -#define RUPDCR_0 DVDEC0.RUPDCR -#define VSYNCSR_0 DVDEC0.VSYNCSR -#define HSYNCSR_0 DVDEC0.HSYNCSR -#define DCPSR1_0 DVDEC0.DCPSR1 -#define DCPSR2_0 DVDEC0.DCPSR2 -#define NSDSR_0 DVDEC0.NSDSR -#define CROMASR1_0 DVDEC0.CROMASR1 -#define CROMASR2_0 DVDEC0.CROMASR2 -#define SYNCSSR_0 DVDEC0.SYNCSSR -#define AGCCSR1_0 DVDEC0.AGCCSR1 -#define AGCCSR2_0 DVDEC0.AGCCSR2 -#define YCSCR3_0 DVDEC0.YCSCR3 -#define YCSCR4_0 DVDEC0.YCSCR4 -#define YCSCR5_0 DVDEC0.YCSCR5 -#define YCSCR6_0 DVDEC0.YCSCR6 -#define YCSCR7_0 DVDEC0.YCSCR7 -#define YCSCR8_0 DVDEC0.YCSCR8 -#define YCSCR9_0 DVDEC0.YCSCR9 -#define YCSCR11_0 DVDEC0.YCSCR11 -#define YCSCR12_0 DVDEC0.YCSCR12 -#define DCPCR9_0 DVDEC0.DCPCR9 -#define YCTWA_F0_0 DVDEC0.YCTWA_F0 -#define YCTWA_F1_0 DVDEC0.YCTWA_F1 -#define YCTWA_F2_0 DVDEC0.YCTWA_F2 -#define YCTWA_F3_0 DVDEC0.YCTWA_F3 -#define YCTWA_F4_0 DVDEC0.YCTWA_F4 -#define YCTWA_F5_0 DVDEC0.YCTWA_F5 -#define YCTWA_F6_0 DVDEC0.YCTWA_F6 -#define YCTWA_F7_0 DVDEC0.YCTWA_F7 -#define YCTWA_F8_0 DVDEC0.YCTWA_F8 -#define YCTWB_F0_0 DVDEC0.YCTWB_F0 -#define YCTWB_F1_0 DVDEC0.YCTWB_F1 -#define YCTWB_F2_0 DVDEC0.YCTWB_F2 -#define YCTWB_F3_0 DVDEC0.YCTWB_F3 -#define YCTWB_F4_0 DVDEC0.YCTWB_F4 -#define YCTWB_F5_0 DVDEC0.YCTWB_F5 -#define YCTWB_F6_0 DVDEC0.YCTWB_F6 -#define YCTWB_F7_0 DVDEC0.YCTWB_F7 -#define YCTWB_F8_0 DVDEC0.YCTWB_F8 -#define YCTNA_F0_0 DVDEC0.YCTNA_F0 -#define YCTNA_F1_0 DVDEC0.YCTNA_F1 -#define YCTNA_F2_0 DVDEC0.YCTNA_F2 -#define YCTNA_F3_0 DVDEC0.YCTNA_F3 -#define YCTNA_F4_0 DVDEC0.YCTNA_F4 -#define YCTNA_F5_0 DVDEC0.YCTNA_F5 -#define YCTNA_F6_0 DVDEC0.YCTNA_F6 -#define YCTNA_F7_0 DVDEC0.YCTNA_F7 -#define YCTNA_F8_0 DVDEC0.YCTNA_F8 -#define YCTNB_F0_0 DVDEC0.YCTNB_F0 -#define YCTNB_F1_0 DVDEC0.YCTNB_F1 -#define YCTNB_F2_0 DVDEC0.YCTNB_F2 -#define YCTNB_F3_0 DVDEC0.YCTNB_F3 -#define YCTNB_F4_0 DVDEC0.YCTNB_F4 -#define YCTNB_F5_0 DVDEC0.YCTNB_F5 -#define YCTNB_F6_0 DVDEC0.YCTNB_F6 -#define YCTNB_F7_0 DVDEC0.YCTNB_F7 -#define YCTNB_F8_0 DVDEC0.YCTNB_F8 -#define YGAINCR_0 DVDEC0.YGAINCR -#define CBGAINCR_0 DVDEC0.CBGAINCR -#define CRGAINCR_0 DVDEC0.CRGAINCR -#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE -#define PGACR_0 DVDEC0.PGACR -#define ADCCR2_0 DVDEC0.ADCCR2 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h index 88b268ec7d..fef3000ff9 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h @@ -18,21 +18,192 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ether_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef ETHER_IODEFINE_H #define ETHER_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ether -{ /* ETHER */ +#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */ + + +/* Start of channel array defines of ETHER */ + +/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */ +/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */ +#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT (32) +#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \ + ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \ + ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \ + ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */ +#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */ +#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */ +#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */ +#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */ +#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */ +#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */ +#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */ +#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */ +#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */ +#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */ +#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */ +#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */ +#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */ +#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */ +#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */ +#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */ +#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */ +#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */ +#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */ +#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */ +#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */ +#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */ +#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */ +#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */ +#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */ +#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */ +#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */ +#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */ +#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */ +#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */ +#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */ + +/* End of channel array defines of ETHER */ + + +#define ETHEREDSR0 (ETHER.EDSR0) +#define ETHERTDLAR0 (ETHER.TDLAR0) +#define ETHERTDFAR0 (ETHER.TDFAR0) +#define ETHERTDFXR0 (ETHER.TDFXR0) +#define ETHERTDFFR0 (ETHER.TDFFR0) +#define ETHERRDLAR0 (ETHER.RDLAR0) +#define ETHERRDFAR0 (ETHER.RDFAR0) +#define ETHERRDFXR0 (ETHER.RDFXR0) +#define ETHERRDFFR0 (ETHER.RDFFR0) +#define ETHEREDMR0 (ETHER.EDMR0) +#define ETHEREDTRR0 (ETHER.EDTRR0) +#define ETHEREDRRR0 (ETHER.EDRRR0) +#define ETHEREESR0 (ETHER.EESR0) +#define ETHEREESIPR0 (ETHER.EESIPR0) +#define ETHERTRSCER0 (ETHER.TRSCER0) +#define ETHERRMFCR0 (ETHER.RMFCR0) +#define ETHERTFTR0 (ETHER.TFTR0) +#define ETHERFDR0 (ETHER.FDR0) +#define ETHERRMCR0 (ETHER.RMCR0) +#define ETHERRPADIR0 (ETHER.RPADIR0) +#define ETHERFCFTR0 (ETHER.FCFTR0) +#define ETHERCSMR (ETHER.CSMR) +#define ETHERCSSBM (ETHER.CSSBM) +#define ETHERCSSMR (ETHER.CSSMR) +#define ETHERECMR0 (ETHER.ECMR0) +#define ETHERRFLR0 (ETHER.RFLR0) +#define ETHERECSR0 (ETHER.ECSR0) +#define ETHERECSIPR0 (ETHER.ECSIPR0) +#define ETHERPIR0 (ETHER.PIR0) +#define ETHERAPR0 (ETHER.APR0) +#define ETHERMPR0 (ETHER.MPR0) +#define ETHERPFTCR0 (ETHER.PFTCR0) +#define ETHERPFRCR0 (ETHER.PFRCR0) +#define ETHERTPAUSER0 (ETHER.TPAUSER0) +#define ETHERMAHR0 (ETHER.MAHR0) +#define ETHERMALR0 (ETHER.MALR0) +#define ETHERCEFCR0 (ETHER.CEFCR0) +#define ETHERFRECR0 (ETHER.FRECR0) +#define ETHERTSFRCR0 (ETHER.TSFRCR0) +#define ETHERTLFRCR0 (ETHER.TLFRCR0) +#define ETHERRFCR0 (ETHER.RFCR0) +#define ETHERMAFCR0 (ETHER.MAFCR0) +#define ETHERARSTR (ETHER.ARSTR) +#define ETHERTSU_CTRST (ETHER.TSU_CTRST) +#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0) +#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY) +#define ETHERTSU_TEN (ETHER.TSU_TEN) +#define ETHERTXNLCR0 (ETHER.TXNLCR0) +#define ETHERTXALCR0 (ETHER.TXALCR0) +#define ETHERRXNLCR0 (ETHER.RXNLCR0) +#define ETHERRXALCR0 (ETHER.RXALCR0) +#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0) +#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0) +#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1) +#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1) +#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2) +#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2) +#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3) +#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3) +#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4) +#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4) +#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5) +#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5) +#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6) +#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6) +#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7) +#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7) +#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8) +#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8) +#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9) +#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9) +#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10) +#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10) +#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11) +#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11) +#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12) +#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12) +#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13) +#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13) +#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14) +#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14) +#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15) +#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15) +#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16) +#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16) +#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17) +#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17) +#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18) +#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18) +#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19) +#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19) +#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20) +#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20) +#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21) +#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21) +#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22) +#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22) +#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23) +#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23) +#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24) +#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24) +#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25) +#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25) +#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26) +#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26) +#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27) +#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27) +#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28) +#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28) +#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29) +#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29) +#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30) +#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30) +#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31) +#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31) + + +typedef struct st_ether +{ + /* ETHER */ volatile uint32_t EDSR0; /* EDSR0 */ volatile uint8_t dummy207[12]; /* */ volatile uint32_t TDLAR0; /* TDLAR0 */ @@ -118,310 +289,221 @@ struct st_ether volatile uint32_t RXNLCR0; /* RXNLCR0 */ volatile uint32_t RXALCR0; /* RXALCR0 */ volatile uint8_t dummy240[112]; /* */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */ volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */ volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */ volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */ volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */ volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */ volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */ volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */ volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */ volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */ volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */ volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */ volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */ volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */ volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */ volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */ volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */ volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */ volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */ volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */ volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */ volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */ volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */ volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */ volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */ volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */ volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */ volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */ volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */ volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */ volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */ volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */ + /* end of struct st_ether_from_tsu_adrh0 */ -}; +} r_io_ether_t; -struct st_ether_from_tsu_adrh0 +typedef struct st_ether_from_tsu_adrh0 { + volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ -}; +} r_io_ether_from_tsu_adrh0_t; -#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */ +/* Channel array defines of ETHER (2)*/ +#ifdef DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS +volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */ +/* End of channel array defines of ETHER (2)*/ -/* Start of channnel array defines of ETHER */ - -/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */ -/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */ -#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT 32 -#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \ - ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \ - ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \ - ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */ -#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */ -#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */ -#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */ -#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */ -#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */ -#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */ -#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */ -#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */ -#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */ -#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */ -#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */ -#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */ -#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */ -#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */ -#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */ -#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */ -#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */ -#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */ -#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */ -#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */ -#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */ -#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */ -#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */ -#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */ -#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */ -#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */ -#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */ -#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */ -#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */ -#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */ -#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */ - -/* End of channnel array defines of ETHER */ - - -#define ETHEREDSR0 ETHER.EDSR0 -#define ETHERTDLAR0 ETHER.TDLAR0 -#define ETHERTDFAR0 ETHER.TDFAR0 -#define ETHERTDFXR0 ETHER.TDFXR0 -#define ETHERTDFFR0 ETHER.TDFFR0 -#define ETHERRDLAR0 ETHER.RDLAR0 -#define ETHERRDFAR0 ETHER.RDFAR0 -#define ETHERRDFXR0 ETHER.RDFXR0 -#define ETHERRDFFR0 ETHER.RDFFR0 -#define ETHEREDMR0 ETHER.EDMR0 -#define ETHEREDTRR0 ETHER.EDTRR0 -#define ETHEREDRRR0 ETHER.EDRRR0 -#define ETHEREESR0 ETHER.EESR0 -#define ETHEREESIPR0 ETHER.EESIPR0 -#define ETHERTRSCER0 ETHER.TRSCER0 -#define ETHERRMFCR0 ETHER.RMFCR0 -#define ETHERTFTR0 ETHER.TFTR0 -#define ETHERFDR0 ETHER.FDR0 -#define ETHERRMCR0 ETHER.RMCR0 -#define ETHERRPADIR0 ETHER.RPADIR0 -#define ETHERFCFTR0 ETHER.FCFTR0 -#define ETHERCSMR ETHER.CSMR -#define ETHERCSSBM ETHER.CSSBM -#define ETHERCSSMR ETHER.CSSMR -#define ETHERECMR0 ETHER.ECMR0 -#define ETHERRFLR0 ETHER.RFLR0 -#define ETHERECSR0 ETHER.ECSR0 -#define ETHERECSIPR0 ETHER.ECSIPR0 -#define ETHERPIR0 ETHER.PIR0 -#define ETHERAPR0 ETHER.APR0 -#define ETHERMPR0 ETHER.MPR0 -#define ETHERPFTCR0 ETHER.PFTCR0 -#define ETHERPFRCR0 ETHER.PFRCR0 -#define ETHERTPAUSER0 ETHER.TPAUSER0 -#define ETHERMAHR0 ETHER.MAHR0 -#define ETHERMALR0 ETHER.MALR0 -#define ETHERCEFCR0 ETHER.CEFCR0 -#define ETHERFRECR0 ETHER.FRECR0 -#define ETHERTSFRCR0 ETHER.TSFRCR0 -#define ETHERTLFRCR0 ETHER.TLFRCR0 -#define ETHERRFCR0 ETHER.RFCR0 -#define ETHERMAFCR0 ETHER.MAFCR0 -#define ETHERARSTR ETHER.ARSTR -#define ETHERTSU_CTRST ETHER.TSU_CTRST -#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0 -#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY -#define ETHERTSU_TEN ETHER.TSU_TEN -#define ETHERTXNLCR0 ETHER.TXNLCR0 -#define ETHERTXALCR0 ETHER.TXALCR0 -#define ETHERRXNLCR0 ETHER.RXNLCR0 -#define ETHERRXALCR0 ETHER.RXALCR0 -#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0 -#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0 -#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1 -#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1 -#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2 -#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2 -#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3 -#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3 -#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4 -#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4 -#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5 -#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5 -#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6 -#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6 -#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7 -#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7 -#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8 -#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8 -#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9 -#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9 -#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10 -#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10 -#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11 -#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11 -#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12 -#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12 -#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13 -#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13 -#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14 -#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14 -#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15 -#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15 -#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16 -#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16 -#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17 -#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17 -#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18 -#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18 -#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19 -#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19 -#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20 -#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20 -#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21 -#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21 -#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22 -#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22 -#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23 -#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23 -#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24 -#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24 -#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25 -#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25 -#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26 -#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26 -#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27 -#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27 -#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28 -#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28 -#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29 -#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29 -#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30 -#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30 -#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31 -#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h index 3f8ec183c2..0e88e0cad2 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h @@ -18,20 +18,41 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : flctl_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef FLCTL_IODEFINE_H #define FLCTL_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_flctl -{ /* FLCTL */ +#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */ + + +#define FLCTLFLCMNCR (FLCTL.FLCMNCR) +#define FLCTLFLCMDCR (FLCTL.FLCMDCR) +#define FLCTLFLCMCDR (FLCTL.FLCMCDR) +#define FLCTLFLADR (FLCTL.FLADR) +#define FLCTLFLDATAR (FLCTL.FLDATAR) +#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR) +#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR) +#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR) +#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT) +#define FLCTLFLTRCR (FLCTL.FLTRCR) +#define FLCTLFLADR2 (FLCTL.FLADR2) +#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO) + + +typedef struct st_flctl +{ + /* FLCTL */ volatile uint32_t FLCMNCR; /* FLCMNCR */ volatile uint32_t FLCMDCR; /* FLCMDCR */ volatile uint32_t FLCMCDR; /* FLCMCDR */ @@ -47,26 +68,11 @@ struct st_flctl volatile uint32_t FLADR2; /* FLADR2 */ volatile uint8_t dummy557[16]; /* */ volatile uint32_t FLDTFIFO; /* FLDTFIFO */ - volatile uint8_t dummy558[12]; /* */ - volatile uint32_t FLECFIFO; /* FLECFIFO */ -}; +} r_io_flctl_t; -#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */ - - -#define FLCTLFLCMNCR FLCTL.FLCMNCR -#define FLCTLFLCMDCR FLCTL.FLCMDCR -#define FLCTLFLCMCDR FLCTL.FLCMCDR -#define FLCTLFLADR FLCTL.FLADR -#define FLCTLFLDATAR FLCTL.FLDATAR -#define FLCTLFLDTCNTR FLCTL.FLDTCNTR -#define FLCTLFLINTDMACR FLCTL.FLINTDMACR -#define FLCTLFLBSYTMR FLCTL.FLBSYTMR -#define FLCTLFLBSYCNT FLCTL.FLBSYCNT -#define FLCTLFLTRCR FLCTL.FLTRCR -#define FLCTLFLADR2 FLCTL.FLADR2 -#define FLCTLFLDTFIFO FLCTL.FLDTFIFO -#define FLCTLFLECFIFO FLCTL.FLECFIFO /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h index 8bedb518ff..05c30ecdf5 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h @@ -18,662 +18,29 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : gpio_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef GPIO_IODEFINE_H #define GPIO_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_gpio -{ /* GPIO */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P1; /* P1 */ - volatile uint8_t dummy348[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P2; /* P2 */ - volatile uint8_t dummy349[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P3; /* P3 */ - volatile uint8_t dummy350[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P4; /* P4 */ - volatile uint8_t dummy351[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P5; /* P5 */ - volatile uint8_t dummy352[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P6; /* P6 */ - volatile uint8_t dummy353[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P7; /* P7 */ - volatile uint8_t dummy354[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P8; /* P8 */ - volatile uint8_t dummy355[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P9; /* P9 */ - volatile uint8_t dummy356[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P10; /* P10 */ - volatile uint8_t dummy357[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P11; /* P11 */ - volatile uint8_t dummy3580[2]; /* */ -/* end of struct st_gpio_from_p1 */ - volatile uint8_t dummy3581[212]; /* */ -#define GPIO_PSRn_COUNT 11 - volatile uint32_t PSR1; /* PSR1 */ - volatile uint32_t PSR2; /* PSR2 */ - volatile uint32_t PSR3; /* PSR3 */ - volatile uint32_t PSR4; /* PSR4 */ - volatile uint32_t PSR5; /* PSR5 */ - volatile uint32_t PSR6; /* PSR6 */ - volatile uint32_t PSR7; /* PSR7 */ - volatile uint32_t PSR8; /* PSR8 */ - volatile uint32_t PSR9; /* PSR9 */ - volatile uint32_t PSR10; /* PSR10 */ - volatile uint32_t PSR11; /* PSR11 */ - volatile uint8_t dummy359[208]; /* */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR0; /* PPR0 */ - volatile uint8_t dummy360[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR1; /* PPR1 */ - volatile uint8_t dummy361[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR2; /* PPR2 */ - volatile uint8_t dummy362[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR3; /* PPR3 */ - volatile uint8_t dummy363[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR4; /* PPR4 */ - volatile uint8_t dummy364[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR5; /* PPR5 */ - volatile uint8_t dummy365[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR6; /* PPR6 */ - volatile uint8_t dummy366[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR7; /* PPR7 */ - volatile uint8_t dummy367[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR8; /* PPR8 */ - volatile uint8_t dummy368[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR9; /* PPR9 */ - volatile uint8_t dummy369[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR10; /* PPR10 */ - volatile uint8_t dummy370[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR11; /* PPR11 */ - volatile uint8_t dummy3710[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ - volatile uint8_t dummy3711[212]; /* */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM1; /* PM1 */ - volatile uint8_t dummy372[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM2; /* PM2 */ - volatile uint8_t dummy373[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM3; /* PM3 */ - volatile uint8_t dummy374[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM4; /* PM4 */ - volatile uint8_t dummy375[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM5; /* PM5 */ - volatile uint8_t dummy376[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM6; /* PM6 */ - volatile uint8_t dummy377[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM7; /* PM7 */ - volatile uint8_t dummy378[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM8; /* PM8 */ - volatile uint8_t dummy379[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM9; /* PM9 */ - volatile uint8_t dummy380[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM10; /* PM10 */ - volatile uint8_t dummy381[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM11; /* PM11 */ - volatile uint8_t dummy3820[2]; /* */ -/* end of struct st_gpio_from_pm1 */ - volatile uint8_t dummy3821[208]; /* */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC0; /* PMC0 */ - volatile uint8_t dummy383[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC1; /* PMC1 */ - volatile uint8_t dummy384[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC2; /* PMC2 */ - volatile uint8_t dummy385[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC3; /* PMC3 */ - volatile uint8_t dummy386[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC4; /* PMC4 */ - volatile uint8_t dummy387[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC5; /* PMC5 */ - volatile uint8_t dummy388[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC6; /* PMC6 */ - volatile uint8_t dummy389[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC7; /* PMC7 */ - volatile uint8_t dummy390[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC8; /* PMC8 */ - volatile uint8_t dummy391[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC9; /* PMC9 */ - volatile uint8_t dummy392[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC10; /* PMC10 */ - volatile uint8_t dummy393[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC11; /* PMC11 */ - volatile uint8_t dummy3940[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ - volatile uint8_t dummy3941[212]; /* */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC1; /* PFC1 */ - volatile uint8_t dummy395[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC2; /* PFC2 */ - volatile uint8_t dummy396[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC3; /* PFC3 */ - volatile uint8_t dummy397[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC4; /* PFC4 */ - volatile uint8_t dummy398[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC5; /* PFC5 */ - volatile uint8_t dummy399[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC6; /* PFC6 */ - volatile uint8_t dummy400[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC7; /* PFC7 */ - volatile uint8_t dummy401[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC8; /* PFC8 */ - volatile uint8_t dummy402[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC9; /* PFC9 */ - volatile uint8_t dummy403[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC10; /* PFC10 */ - volatile uint8_t dummy404[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC11; /* PFC11 */ - volatile uint8_t dummy4050[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ - volatile uint8_t dummy4051[212]; /* */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE1; /* PFCE1 */ - volatile uint8_t dummy406[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE2; /* PFCE2 */ - volatile uint8_t dummy407[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE3; /* PFCE3 */ - volatile uint8_t dummy408[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE4; /* PFCE4 */ - volatile uint8_t dummy409[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE5; /* PFCE5 */ - volatile uint8_t dummy410[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE6; /* PFCE6 */ - volatile uint8_t dummy411[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE7; /* PFCE7 */ - volatile uint8_t dummy412[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE8; /* PFCE8 */ - volatile uint8_t dummy413[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE9; /* PFCE9 */ - volatile uint8_t dummy414[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE10; /* PFCE10 */ - volatile uint8_t dummy415[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE11; /* PFCE11 */ - volatile uint8_t dummy4160[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ - volatile uint8_t dummy4161[212]; /* */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT1; /* PNOT1 */ - volatile uint8_t dummy417[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT2; /* PNOT2 */ - volatile uint8_t dummy418[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT3; /* PNOT3 */ - volatile uint8_t dummy419[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT4; /* PNOT4 */ - volatile uint8_t dummy420[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT5; /* PNOT5 */ - volatile uint8_t dummy421[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT6; /* PNOT6 */ - volatile uint8_t dummy422[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT7; /* PNOT7 */ - volatile uint8_t dummy423[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT8; /* PNOT8 */ - volatile uint8_t dummy424[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT9; /* PNOT9 */ - volatile uint8_t dummy425[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT10; /* PNOT10 */ - volatile uint8_t dummy426[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT11; /* PNOT11 */ - volatile uint8_t dummy4270[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ - volatile uint8_t dummy4271[212]; /* */ -#define GPIO_PMSRn_COUNT 11 - volatile uint32_t PMSR1; /* PMSR1 */ - volatile uint32_t PMSR2; /* PMSR2 */ - volatile uint32_t PMSR3; /* PMSR3 */ - volatile uint32_t PMSR4; /* PMSR4 */ - volatile uint32_t PMSR5; /* PMSR5 */ - volatile uint32_t PMSR6; /* PMSR6 */ - volatile uint32_t PMSR7; /* PMSR7 */ - volatile uint32_t PMSR8; /* PMSR8 */ - volatile uint32_t PMSR9; /* PMSR9 */ - volatile uint32_t PMSR10; /* PMSR10 */ - volatile uint32_t PMSR11; /* PMSR11 */ - volatile uint8_t dummy428[208]; /* */ -#define GPIO_PMCSRn_COUNT 12 - volatile uint32_t PMCSR0; /* PMCSR0 */ - volatile uint32_t PMCSR1; /* PMCSR1 */ - volatile uint32_t PMCSR2; /* PMCSR2 */ - volatile uint32_t PMCSR3; /* PMCSR3 */ - volatile uint32_t PMCSR4; /* PMCSR4 */ - volatile uint32_t PMCSR5; /* PMCSR5 */ - volatile uint32_t PMCSR6; /* PMCSR6 */ - volatile uint32_t PMCSR7; /* PMCSR7 */ - volatile uint32_t PMCSR8; /* PMCSR8 */ - volatile uint32_t PMCSR9; /* PMCSR9 */ - volatile uint32_t PMCSR10; /* PMCSR10 */ - volatile uint32_t PMCSR11; /* PMCSR11 */ - volatile uint8_t dummy429[212]; /* */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE1; /* PFCAE1 */ - volatile uint8_t dummy430[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE2; /* PFCAE2 */ - volatile uint8_t dummy431[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE3; /* PFCAE3 */ - volatile uint8_t dummy432[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE4; /* PFCAE4 */ - volatile uint8_t dummy433[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE5; /* PFCAE5 */ - volatile uint8_t dummy434[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE6; /* PFCAE6 */ - volatile uint8_t dummy435[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE7; /* PFCAE7 */ - volatile uint8_t dummy436[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE8; /* PFCAE8 */ - volatile uint8_t dummy437[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE9; /* PFCAE9 */ - volatile uint8_t dummy438[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE10; /* PFCAE10 */ - volatile uint8_t dummy439[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE11; /* PFCAE11 */ - volatile uint8_t dummy4400[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ - volatile uint8_t dummy4401[464]; /* */ - volatile uint32_t SNCR; /* SNCR */ - volatile uint8_t dummy441[13308]; /* */ - volatile uint16_t PIBC0; /* PIBC0 */ - volatile uint8_t dummy442[2]; /* */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC1; /* PIBC1 */ - volatile uint8_t dummy443[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC2; /* PIBC2 */ - volatile uint8_t dummy444[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC3; /* PIBC3 */ - volatile uint8_t dummy445[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC4; /* PIBC4 */ - volatile uint8_t dummy446[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC5; /* PIBC5 */ - volatile uint8_t dummy447[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC6; /* PIBC6 */ - volatile uint8_t dummy448[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC7; /* PIBC7 */ - volatile uint8_t dummy449[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC8; /* PIBC8 */ - volatile uint8_t dummy450[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC9; /* PIBC9 */ - volatile uint8_t dummy451[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC10; /* PIBC10 */ - volatile uint8_t dummy452[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC11; /* PIBC11 */ - volatile uint8_t dummy4530[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ - volatile uint8_t dummy4531[212]; /* */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC1; /* PBDC1 */ - volatile uint8_t dummy454[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC2; /* PBDC2 */ - volatile uint8_t dummy455[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC3; /* PBDC3 */ - volatile uint8_t dummy456[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC4; /* PBDC4 */ - volatile uint8_t dummy457[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC5; /* PBDC5 */ - volatile uint8_t dummy458[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC6; /* PBDC6 */ - volatile uint8_t dummy459[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC7; /* PBDC7 */ - volatile uint8_t dummy460[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC8; /* PBDC8 */ - volatile uint8_t dummy461[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC9; /* PBDC9 */ - volatile uint8_t dummy462[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC10; /* PBDC10 */ - volatile uint8_t dummy463[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC11; /* PBDC11 */ - volatile uint8_t dummy4640[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ - volatile uint8_t dummy4641[212]; /* */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC1; /* PIPC1 */ - volatile uint8_t dummy465[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC2; /* PIPC2 */ - volatile uint8_t dummy466[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC3; /* PIPC3 */ - volatile uint8_t dummy467[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC4; /* PIPC4 */ - volatile uint8_t dummy468[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC5; /* PIPC5 */ - volatile uint8_t dummy469[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC6; /* PIPC6 */ - volatile uint8_t dummy470[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC7; /* PIPC7 */ - volatile uint8_t dummy471[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC8; /* PIPC8 */ - volatile uint8_t dummy472[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC9; /* PIPC9 */ - volatile uint8_t dummy473[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC10; /* PIPC10 */ - volatile uint8_t dummy474[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC11; /* PIPC11 */ - volatile uint8_t dummy4750[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ - volatile uint8_t dummy4751[2288]; /* */ - volatile uint16_t JPPR0; /* JPPR0 */ - volatile uint8_t dummy476[30]; /* */ - volatile uint16_t JPMC0; /* JPMC0 */ - volatile uint8_t dummy477[78]; /* */ - volatile uint32_t JPMCSR0; /* JPMCSR0 */ - volatile uint8_t dummy478[876]; /* */ - volatile uint16_t JPIBC0; /* JPIBC0 */ -}; - - -struct st_gpio_from_p1 -{ - volatile uint16_t P1; /* P1 */ - volatile uint8_t dummy1[3]; /* */ -}; - - -struct st_gpio_from_ppr0 -{ - volatile uint16_t PPR0; /* PPR0 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pm1 -{ - volatile uint16_t PM1; /* PM1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pmc0 -{ - volatile uint16_t PMC0; /* PMC0 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pfc1 -{ - volatile uint16_t PFC1; /* PFC1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pfce1 -{ - volatile uint16_t PFCE1; /* PFCE1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pnot1 -{ - volatile uint16_t PNOT1; /* PNOT1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pfcae1 -{ - volatile uint16_t PFCAE1; /* PFCAE1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pibc1 -{ - volatile uint16_t PIBC1; /* PIBC1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pbdc1 -{ - volatile uint16_t PBDC1; /* PBDC1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pipc1 -{ - volatile uint16_t PIPC1; /* PIPC1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - #define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */ -/* Start of channnel array defines of GPIO */ -/* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */ +/* Start of channel array defines of GPIO */ + +/* Channel array defines of GPIO_FROM_PIPC1_ARRAY */ /*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */ -#define GPIO_FROM_PIPC1_ARRAY_COUNT 11 +#define GPIO_FROM_PIPC1_ARRAY_COUNT (11) #define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \ @@ -692,9 +59,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */ -/* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */ +/* Channel array defines of GPIO_FROM_PBDC1_ARRAY */ /*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */ -#define GPIO_FROM_PBDC1_ARRAY_COUNT 11 +#define GPIO_FROM_PBDC1_ARRAY_COUNT (11) #define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \ @@ -713,14 +80,15 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */ -/* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */ +/* Channel array defines of GPIO_FROM_PIBC1_ARRAY */ /*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */ -#define GPIO_FROM_PIBC1_ARRAY_COUNT 11 +#define GPIO_FROM_PIBC1_ARRAY_COUNT (12) #define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \ - &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \ + &GPIO_FROM_PIBC0, &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, \ + &GPIO_FROM_PIBC8, &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PIBC0 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC0) /* GPIO_FROM_PIBC0 */ #define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */ #define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */ #define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */ @@ -734,9 +102,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */ -/* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */ +/* Channel array defines of GPIO_FROM_PFCAE1_ARRAY */ /*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */ -#define GPIO_FROM_PFCAE1_ARRAY_COUNT 11 +#define GPIO_FROM_PFCAE1_ARRAY_COUNT (11) #define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \ @@ -755,9 +123,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */ -/* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */ +/* Channel array defines of GPIO_FROM_PNOT1_ARRAY */ /*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */ -#define GPIO_FROM_PNOT1_ARRAY_COUNT 11 +#define GPIO_FROM_PNOT1_ARRAY_COUNT (11) #define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \ @@ -776,9 +144,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */ -/* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */ +/* Channel array defines of GPIO_FROM_PFCE1_ARRAY */ /*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */ -#define GPIO_FROM_PFCE1_ARRAY_COUNT 11 +#define GPIO_FROM_PFCE1_ARRAY_COUNT (11) #define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \ @@ -797,9 +165,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */ -/* Channnel array defines of GPIO_FROM_PFC1_ARRAY */ +/* Channel array defines of GPIO_FROM_PFC1_ARRAY */ /*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */ -#define GPIO_FROM_PFC1_ARRAY_COUNT 11 +#define GPIO_FROM_PFC1_ARRAY_COUNT (11) #define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \ @@ -818,9 +186,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */ -/* Channnel array defines of GPIO_FROM_PMC0_ARRAY */ +/* Channel array defines of GPIO_FROM_PMC0_ARRAY */ /*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */ -#define GPIO_FROM_PMC0_ARRAY_COUNT 12 +#define GPIO_FROM_PMC0_ARRAY_COUNT (12) #define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \ @@ -840,9 +208,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */ -/* Channnel array defines of GPIO_FROM_PM1_ARRAY */ +/* Channel array defines of GPIO_FROM_PM1_ARRAY */ /*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */ -#define GPIO_FROM_PM1_ARRAY_COUNT 11 +#define GPIO_FROM_PM1_ARRAY_COUNT (11) #define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \ @@ -861,9 +229,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11) /* GPIO_FROM_PM11 */ -/* Channnel array defines of GPIO_FROM_PPR0_ARRAY */ +/* Channel array defines of GPIO_FROM_PPR0_ARRAY */ /*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */ -#define GPIO_FROM_PPR0_ARRAY_COUNT 12 +#define GPIO_FROM_PPR0_ARRAY_COUNT (12) #define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \ @@ -883,9 +251,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */ -/* Channnel array defines of GPIO_FROM_P1_ARRAY */ +/* Channel array defines of GPIO_FROM_P1_ARRAY */ /*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */ -#define GPIO_FROM_P1_ARRAY_COUNT 11 +#define GPIO_FROM_P1_ARRAY_COUNT (11) #define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \ @@ -903,172 +271,1161 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10) /* GPIO_FROM_P10 */ #define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11) /* GPIO_FROM_P11 */ -/* End of channnel array defines of GPIO */ +/* End of channel array defines of GPIO */ + + +#define GPIOP1 (GPIO.P1) +#define GPIOP2 (GPIO.P2) +#define GPIOP3 (GPIO.P3) +#define GPIOP4 (GPIO.P4) +#define GPIOP5 (GPIO.P5) +#define GPIOP6 (GPIO.P6) +#define GPIOP7 (GPIO.P7) +#define GPIOP8 (GPIO.P8) +#define GPIOP9 (GPIO.P9) +#define GPIOP10 (GPIO.P10) +#define GPIOP11 (GPIO.P11) +#define GPIOPSR1 (GPIO.PSR1) +#define GPIOPSR2 (GPIO.PSR2) +#define GPIOPSR3 (GPIO.PSR3) +#define GPIOPSR4 (GPIO.PSR4) +#define GPIOPSR5 (GPIO.PSR5) +#define GPIOPSR6 (GPIO.PSR6) +#define GPIOPSR7 (GPIO.PSR7) +#define GPIOPSR8 (GPIO.PSR8) +#define GPIOPSR9 (GPIO.PSR9) +#define GPIOPSR10 (GPIO.PSR10) +#define GPIOPSR11 (GPIO.PSR11) +#define GPIOPPR0 (GPIO.PPR0) +#define GPIOPPR1 (GPIO.PPR1) +#define GPIOPPR2 (GPIO.PPR2) +#define GPIOPPR3 (GPIO.PPR3) +#define GPIOPPR4 (GPIO.PPR4) +#define GPIOPPR5 (GPIO.PPR5) +#define GPIOPPR6 (GPIO.PPR6) +#define GPIOPPR7 (GPIO.PPR7) +#define GPIOPPR8 (GPIO.PPR8) +#define GPIOPPR9 (GPIO.PPR9) +#define GPIOPPR10 (GPIO.PPR10) +#define GPIOPPR11 (GPIO.PPR11) +#define GPIOPM1 (GPIO.PM1) +#define GPIOPM2 (GPIO.PM2) +#define GPIOPM3 (GPIO.PM3) +#define GPIOPM4 (GPIO.PM4) +#define GPIOPM5 (GPIO.PM5) +#define GPIOPM6 (GPIO.PM6) +#define GPIOPM7 (GPIO.PM7) +#define GPIOPM8 (GPIO.PM8) +#define GPIOPM9 (GPIO.PM9) +#define GPIOPM10 (GPIO.PM10) +#define GPIOPM11 (GPIO.PM11) +#define GPIOPMC0 (GPIO.PMC0) +#define GPIOPMC1 (GPIO.PMC1) +#define GPIOPMC2 (GPIO.PMC2) +#define GPIOPMC3 (GPIO.PMC3) +#define GPIOPMC4 (GPIO.PMC4) +#define GPIOPMC5 (GPIO.PMC5) +#define GPIOPMC6 (GPIO.PMC6) +#define GPIOPMC7 (GPIO.PMC7) +#define GPIOPMC8 (GPIO.PMC8) +#define GPIOPMC9 (GPIO.PMC9) +#define GPIOPMC10 (GPIO.PMC10) +#define GPIOPMC11 (GPIO.PMC11) +#define GPIOPFC1 (GPIO.PFC1) +#define GPIOPFC2 (GPIO.PFC2) +#define GPIOPFC3 (GPIO.PFC3) +#define GPIOPFC4 (GPIO.PFC4) +#define GPIOPFC5 (GPIO.PFC5) +#define GPIOPFC6 (GPIO.PFC6) +#define GPIOPFC7 (GPIO.PFC7) +#define GPIOPFC8 (GPIO.PFC8) +#define GPIOPFC9 (GPIO.PFC9) +#define GPIOPFC10 (GPIO.PFC10) +#define GPIOPFC11 (GPIO.PFC11) +#define GPIOPFCE1 (GPIO.PFCE1) +#define GPIOPFCE2 (GPIO.PFCE2) +#define GPIOPFCE3 (GPIO.PFCE3) +#define GPIOPFCE4 (GPIO.PFCE4) +#define GPIOPFCE5 (GPIO.PFCE5) +#define GPIOPFCE6 (GPIO.PFCE6) +#define GPIOPFCE7 (GPIO.PFCE7) +#define GPIOPFCE8 (GPIO.PFCE8) +#define GPIOPFCE9 (GPIO.PFCE9) +#define GPIOPFCE10 (GPIO.PFCE10) +#define GPIOPFCE11 (GPIO.PFCE11) +#define GPIOPNOT1 (GPIO.PNOT1) +#define GPIOPNOT2 (GPIO.PNOT2) +#define GPIOPNOT3 (GPIO.PNOT3) +#define GPIOPNOT4 (GPIO.PNOT4) +#define GPIOPNOT5 (GPIO.PNOT5) +#define GPIOPNOT6 (GPIO.PNOT6) +#define GPIOPNOT7 (GPIO.PNOT7) +#define GPIOPNOT8 (GPIO.PNOT8) +#define GPIOPNOT9 (GPIO.PNOT9) +#define GPIOPNOT10 (GPIO.PNOT10) +#define GPIOPNOT11 (GPIO.PNOT11) +#define GPIOPMSR1 (GPIO.PMSR1) +#define GPIOPMSR2 (GPIO.PMSR2) +#define GPIOPMSR3 (GPIO.PMSR3) +#define GPIOPMSR4 (GPIO.PMSR4) +#define GPIOPMSR5 (GPIO.PMSR5) +#define GPIOPMSR6 (GPIO.PMSR6) +#define GPIOPMSR7 (GPIO.PMSR7) +#define GPIOPMSR8 (GPIO.PMSR8) +#define GPIOPMSR9 (GPIO.PMSR9) +#define GPIOPMSR10 (GPIO.PMSR10) +#define GPIOPMSR11 (GPIO.PMSR11) +#define GPIOPMCSR0 (GPIO.PMCSR0) +#define GPIOPMCSR1 (GPIO.PMCSR1) +#define GPIOPMCSR2 (GPIO.PMCSR2) +#define GPIOPMCSR3 (GPIO.PMCSR3) +#define GPIOPMCSR4 (GPIO.PMCSR4) +#define GPIOPMCSR5 (GPIO.PMCSR5) +#define GPIOPMCSR6 (GPIO.PMCSR6) +#define GPIOPMCSR7 (GPIO.PMCSR7) +#define GPIOPMCSR8 (GPIO.PMCSR8) +#define GPIOPMCSR9 (GPIO.PMCSR9) +#define GPIOPMCSR10 (GPIO.PMCSR10) +#define GPIOPMCSR11 (GPIO.PMCSR11) +#define GPIOPFCAE1 (GPIO.PFCAE1) +#define GPIOPFCAE2 (GPIO.PFCAE2) +#define GPIOPFCAE3 (GPIO.PFCAE3) +#define GPIOPFCAE4 (GPIO.PFCAE4) +#define GPIOPFCAE5 (GPIO.PFCAE5) +#define GPIOPFCAE6 (GPIO.PFCAE6) +#define GPIOPFCAE7 (GPIO.PFCAE7) +#define GPIOPFCAE8 (GPIO.PFCAE8) +#define GPIOPFCAE9 (GPIO.PFCAE9) +#define GPIOPFCAE10 (GPIO.PFCAE10) +#define GPIOPFCAE11 (GPIO.PFCAE11) +#define GPIOSNCR (GPIO.SNCR) +#define GPIOPIBC0 (GPIO.PIBC0) +#define GPIOPIBC1 (GPIO.PIBC1) +#define GPIOPIBC2 (GPIO.PIBC2) +#define GPIOPIBC3 (GPIO.PIBC3) +#define GPIOPIBC4 (GPIO.PIBC4) +#define GPIOPIBC5 (GPIO.PIBC5) +#define GPIOPIBC6 (GPIO.PIBC6) +#define GPIOPIBC7 (GPIO.PIBC7) +#define GPIOPIBC8 (GPIO.PIBC8) +#define GPIOPIBC9 (GPIO.PIBC9) +#define GPIOPIBC10 (GPIO.PIBC10) +#define GPIOPIBC11 (GPIO.PIBC11) +#define GPIOPBDC1 (GPIO.PBDC1) +#define GPIOPBDC2 (GPIO.PBDC2) +#define GPIOPBDC3 (GPIO.PBDC3) +#define GPIOPBDC4 (GPIO.PBDC4) +#define GPIOPBDC5 (GPIO.PBDC5) +#define GPIOPBDC6 (GPIO.PBDC6) +#define GPIOPBDC7 (GPIO.PBDC7) +#define GPIOPBDC8 (GPIO.PBDC8) +#define GPIOPBDC9 (GPIO.PBDC9) +#define GPIOPBDC10 (GPIO.PBDC10) +#define GPIOPBDC11 (GPIO.PBDC11) +#define GPIOPIPC1 (GPIO.PIPC1) +#define GPIOPIPC2 (GPIO.PIPC2) +#define GPIOPIPC3 (GPIO.PIPC3) +#define GPIOPIPC4 (GPIO.PIPC4) +#define GPIOPIPC5 (GPIO.PIPC5) +#define GPIOPIPC6 (GPIO.PIPC6) +#define GPIOPIPC7 (GPIO.PIPC7) +#define GPIOPIPC8 (GPIO.PIPC8) +#define GPIOPIPC9 (GPIO.PIPC9) +#define GPIOPIPC10 (GPIO.PIPC10) +#define GPIOPIPC11 (GPIO.PIPC11) +#define GPIOJPPR0 (GPIO.JPPR0) +#define GPIOJPMC0 (GPIO.JPMC0) +#define GPIOJPMCSR0 (GPIO.JPMCSR0) +#define GPIOJPIBC0 (GPIO.JPIBC0) + +#define GPIO_PSRn_COUNT (11) +#define GPIO_PMSRn_COUNT (11) +#define GPIO_PMCSRn_COUNT (12) + + +typedef struct st_gpio +{ + /* GPIO */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P1; /* P1 */ + volatile uint8_t dummy348[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P2; /* P2 */ + volatile uint8_t dummy349[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P3; /* P3 */ + volatile uint8_t dummy350[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P4; /* P4 */ + volatile uint8_t dummy351[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P5; /* P5 */ + volatile uint8_t dummy352[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P6; /* P6 */ + volatile uint8_t dummy353[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P7; /* P7 */ + volatile uint8_t dummy354[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P8; /* P8 */ + volatile uint8_t dummy355[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P9; /* P9 */ + volatile uint8_t dummy356[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P10; /* P10 */ + volatile uint8_t dummy357[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P11; /* P11 */ + volatile uint8_t dummy3580[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + volatile uint8_t dummy3581[212]; /* */ + +/* #define GPIO_PSRn_COUNT (11) */ + volatile uint32_t PSR1; /* PSR1 */ + volatile uint32_t PSR2; /* PSR2 */ + volatile uint32_t PSR3; /* PSR3 */ + volatile uint32_t PSR4; /* PSR4 */ + volatile uint32_t PSR5; /* PSR5 */ + volatile uint32_t PSR6; /* PSR6 */ + volatile uint32_t PSR7; /* PSR7 */ + volatile uint32_t PSR8; /* PSR8 */ + volatile uint32_t PSR9; /* PSR9 */ + volatile uint32_t PSR10; /* PSR10 */ + volatile uint32_t PSR11; /* PSR11 */ + volatile uint8_t dummy359[208]; /* */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR0; /* PPR0 */ + volatile uint8_t dummy360[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR1; /* PPR1 */ + volatile uint8_t dummy361[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR2; /* PPR2 */ + volatile uint8_t dummy362[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR3; /* PPR3 */ + volatile uint8_t dummy363[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR4; /* PPR4 */ + volatile uint8_t dummy364[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR5; /* PPR5 */ + volatile uint8_t dummy365[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR6; /* PPR6 */ + volatile uint8_t dummy366[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR7; /* PPR7 */ + volatile uint8_t dummy367[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR8; /* PPR8 */ + volatile uint8_t dummy368[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR9; /* PPR9 */ + volatile uint8_t dummy369[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR10; /* PPR10 */ + volatile uint8_t dummy370[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR11; /* PPR11 */ + volatile uint8_t dummy3710[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + volatile uint8_t dummy3711[212]; /* */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM1; /* PM1 */ + volatile uint8_t dummy372[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM2; /* PM2 */ + volatile uint8_t dummy373[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM3; /* PM3 */ + volatile uint8_t dummy374[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM4; /* PM4 */ + volatile uint8_t dummy375[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM5; /* PM5 */ + volatile uint8_t dummy376[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM6; /* PM6 */ + volatile uint8_t dummy377[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM7; /* PM7 */ + volatile uint8_t dummy378[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM8; /* PM8 */ + volatile uint8_t dummy379[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM9; /* PM9 */ + volatile uint8_t dummy380[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM10; /* PM10 */ + volatile uint8_t dummy381[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM11; /* PM11 */ + volatile uint8_t dummy3820[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + volatile uint8_t dummy3821[208]; /* */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC0; /* PMC0 */ + volatile uint8_t dummy383[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC1; /* PMC1 */ + volatile uint8_t dummy384[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC2; /* PMC2 */ + volatile uint8_t dummy385[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC3; /* PMC3 */ + volatile uint8_t dummy386[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC4; /* PMC4 */ + volatile uint8_t dummy387[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC5; /* PMC5 */ + volatile uint8_t dummy388[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC6; /* PMC6 */ + volatile uint8_t dummy389[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC7; /* PMC7 */ + volatile uint8_t dummy390[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC8; /* PMC8 */ + volatile uint8_t dummy391[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC9; /* PMC9 */ + volatile uint8_t dummy392[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC10; /* PMC10 */ + volatile uint8_t dummy393[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC11; /* PMC11 */ + volatile uint8_t dummy3940[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + volatile uint8_t dummy3941[212]; /* */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC1; /* PFC1 */ + volatile uint8_t dummy395[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC2; /* PFC2 */ + volatile uint8_t dummy396[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC3; /* PFC3 */ + volatile uint8_t dummy397[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC4; /* PFC4 */ + volatile uint8_t dummy398[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC5; /* PFC5 */ + volatile uint8_t dummy399[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC6; /* PFC6 */ + volatile uint8_t dummy400[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC7; /* PFC7 */ + volatile uint8_t dummy401[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC8; /* PFC8 */ + volatile uint8_t dummy402[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC9; /* PFC9 */ + volatile uint8_t dummy403[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC10; /* PFC10 */ + volatile uint8_t dummy404[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC11; /* PFC11 */ + volatile uint8_t dummy4050[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + volatile uint8_t dummy4051[212]; /* */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE1; /* PFCE1 */ + volatile uint8_t dummy406[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE2; /* PFCE2 */ + volatile uint8_t dummy407[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE3; /* PFCE3 */ + volatile uint8_t dummy408[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE4; /* PFCE4 */ + volatile uint8_t dummy409[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE5; /* PFCE5 */ + volatile uint8_t dummy410[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE6; /* PFCE6 */ + volatile uint8_t dummy411[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE7; /* PFCE7 */ + volatile uint8_t dummy412[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE8; /* PFCE8 */ + volatile uint8_t dummy413[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE9; /* PFCE9 */ + volatile uint8_t dummy414[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE10; /* PFCE10 */ + volatile uint8_t dummy415[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE11; /* PFCE11 */ + volatile uint8_t dummy4160[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + volatile uint8_t dummy4161[212]; /* */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT1; /* PNOT1 */ + volatile uint8_t dummy417[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT2; /* PNOT2 */ + volatile uint8_t dummy418[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT3; /* PNOT3 */ + volatile uint8_t dummy419[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT4; /* PNOT4 */ + volatile uint8_t dummy420[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT5; /* PNOT5 */ + volatile uint8_t dummy421[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT6; /* PNOT6 */ + volatile uint8_t dummy422[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT7; /* PNOT7 */ + volatile uint8_t dummy423[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT8; /* PNOT8 */ + volatile uint8_t dummy424[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT9; /* PNOT9 */ + volatile uint8_t dummy425[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT10; /* PNOT10 */ + volatile uint8_t dummy426[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT11; /* PNOT11 */ + volatile uint8_t dummy4270[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + volatile uint8_t dummy4271[212]; /* */ + +/* #define GPIO_PMSRn_COUNT (11) */ + volatile uint32_t PMSR1; /* PMSR1 */ + volatile uint32_t PMSR2; /* PMSR2 */ + volatile uint32_t PMSR3; /* PMSR3 */ + volatile uint32_t PMSR4; /* PMSR4 */ + volatile uint32_t PMSR5; /* PMSR5 */ + volatile uint32_t PMSR6; /* PMSR6 */ + volatile uint32_t PMSR7; /* PMSR7 */ + volatile uint32_t PMSR8; /* PMSR8 */ + volatile uint32_t PMSR9; /* PMSR9 */ + volatile uint32_t PMSR10; /* PMSR10 */ + volatile uint32_t PMSR11; /* PMSR11 */ + volatile uint8_t dummy428[208]; /* */ + +/* #define GPIO_PMCSRn_COUNT (12) */ + volatile uint32_t PMCSR0; /* PMCSR0 */ + volatile uint32_t PMCSR1; /* PMCSR1 */ + volatile uint32_t PMCSR2; /* PMCSR2 */ + volatile uint32_t PMCSR3; /* PMCSR3 */ + volatile uint32_t PMCSR4; /* PMCSR4 */ + volatile uint32_t PMCSR5; /* PMCSR5 */ + volatile uint32_t PMCSR6; /* PMCSR6 */ + volatile uint32_t PMCSR7; /* PMCSR7 */ + volatile uint32_t PMCSR8; /* PMCSR8 */ + volatile uint32_t PMCSR9; /* PMCSR9 */ + volatile uint32_t PMCSR10; /* PMCSR10 */ + volatile uint32_t PMCSR11; /* PMCSR11 */ + volatile uint8_t dummy429[212]; /* */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE1; /* PFCAE1 */ + volatile uint8_t dummy430[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE2; /* PFCAE2 */ + volatile uint8_t dummy431[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE3; /* PFCAE3 */ + volatile uint8_t dummy432[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE4; /* PFCAE4 */ + volatile uint8_t dummy433[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE5; /* PFCAE5 */ + volatile uint8_t dummy434[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE6; /* PFCAE6 */ + volatile uint8_t dummy435[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE7; /* PFCAE7 */ + volatile uint8_t dummy436[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE8; /* PFCAE8 */ + volatile uint8_t dummy437[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE9; /* PFCAE9 */ + volatile uint8_t dummy438[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE10; /* PFCAE10 */ + volatile uint8_t dummy439[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE11; /* PFCAE11 */ + volatile uint8_t dummy4400[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + volatile uint8_t dummy4401[464]; /* */ + volatile uint32_t SNCR; /* SNCR */ + volatile uint8_t dummy441[13308]; /* */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC0; /* PIBC0 */ + volatile uint8_t dummy442[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC1; /* PIBC1 */ + volatile uint8_t dummy443[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC2; /* PIBC2 */ + volatile uint8_t dummy444[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC3; /* PIBC3 */ + volatile uint8_t dummy445[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC4; /* PIBC4 */ + volatile uint8_t dummy446[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC5; /* PIBC5 */ + volatile uint8_t dummy447[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC6; /* PIBC6 */ + volatile uint8_t dummy448[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC7; /* PIBC7 */ + volatile uint8_t dummy449[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC8; /* PIBC8 */ + volatile uint8_t dummy450[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC9; /* PIBC9 */ + volatile uint8_t dummy451[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC10; /* PIBC10 */ + volatile uint8_t dummy452[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC11; /* PIBC11 */ + volatile uint8_t dummy4530[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + volatile uint8_t dummy4531[212]; /* */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC1; /* PBDC1 */ + volatile uint8_t dummy454[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC2; /* PBDC2 */ + volatile uint8_t dummy455[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC3; /* PBDC3 */ + volatile uint8_t dummy456[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC4; /* PBDC4 */ + volatile uint8_t dummy457[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC5; /* PBDC5 */ + volatile uint8_t dummy458[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC6; /* PBDC6 */ + volatile uint8_t dummy459[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC7; /* PBDC7 */ + volatile uint8_t dummy460[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC8; /* PBDC8 */ + volatile uint8_t dummy461[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC9; /* PBDC9 */ + volatile uint8_t dummy462[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC10; /* PBDC10 */ + volatile uint8_t dummy463[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC11; /* PBDC11 */ + volatile uint8_t dummy4640[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + volatile uint8_t dummy4641[212]; /* */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC1; /* PIPC1 */ + volatile uint8_t dummy465[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC2; /* PIPC2 */ + volatile uint8_t dummy466[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC3; /* PIPC3 */ + volatile uint8_t dummy467[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC4; /* PIPC4 */ + volatile uint8_t dummy468[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC5; /* PIPC5 */ + volatile uint8_t dummy469[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC6; /* PIPC6 */ + volatile uint8_t dummy470[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC7; /* PIPC7 */ + volatile uint8_t dummy471[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC8; /* PIPC8 */ + volatile uint8_t dummy472[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC9; /* PIPC9 */ + volatile uint8_t dummy473[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC10; /* PIPC10 */ + volatile uint8_t dummy474[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC11; /* PIPC11 */ + volatile uint8_t dummy4750[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + volatile uint8_t dummy4751[2288]; /* */ + volatile uint16_t JPPR0; /* JPPR0 */ + volatile uint8_t dummy476[30]; /* */ + volatile uint16_t JPMC0; /* JPMC0 */ + volatile uint8_t dummy477[78]; /* */ + volatile uint32_t JPMCSR0; /* JPMCSR0 */ + volatile uint8_t dummy478[876]; /* */ + volatile uint16_t JPIBC0; /* JPIBC0 */ +} r_io_gpio_t; + + +typedef struct st_gpio_from_p1 +{ + + volatile uint16_t P1; /* P1 */ + volatile uint8_t dummy1[3]; /* */ +} r_io_gpio_from_p1_t; + + +typedef struct st_gpio_from_ppr0 +{ + + volatile uint16_t PPR0; /* PPR0 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_ppr0_t; + + +typedef struct st_gpio_from_pm1 +{ + + volatile uint16_t PM1; /* PM1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pm1_t; + + +typedef struct st_gpio_from_pmc0 +{ + + volatile uint16_t PMC0; /* PMC0 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pmc0_t; + + +typedef struct st_gpio_from_pfc1 +{ + + volatile uint16_t PFC1; /* PFC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pfc1_t; + + +typedef struct st_gpio_from_pfce1 +{ + + volatile uint16_t PFCE1; /* PFCE1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pfce1_t; + + +typedef struct st_gpio_from_pnot1 +{ + + volatile uint16_t PNOT1; /* PNOT1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pnot1_t; + + +typedef struct st_gpio_from_pfcae1 +{ + + volatile uint16_t PFCAE1; /* PFCAE1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pfcae1_t; + + +typedef struct st_gpio_from_pibc1 +{ + + volatile uint16_t PIBC1; /* PIBC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pibc1_t; + + +typedef struct st_gpio_from_pbdc1 +{ + + volatile uint16_t PBDC1; /* PBDC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pbdc1_t; + + +typedef struct st_gpio_from_pipc1 +{ + + volatile uint16_t PIPC1; /* PIPC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pipc1_t; + + +/* Channel array defines of GPIO (2)*/ +#ifdef DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pipc1* GPIO_FROM_PIPC1_ARRAY[ GPIO_FROM_PIPC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pbdc1* GPIO_FROM_PBDC1_ARRAY[ GPIO_FROM_PBDC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pibc1* GPIO_FROM_PIBC1_ARRAY[ GPIO_FROM_PIBC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfcae1* GPIO_FROM_PFCAE1_ARRAY[ GPIO_FROM_PFCAE1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS +volatile struct st_gpio_from_pnot1* GPIO_FROM_PNOT1_ARRAY[ GPIO_FROM_PNOT1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfce1* GPIO_FROM_PFCE1_ARRAY[ GPIO_FROM_PFCE1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfc1* GPIO_FROM_PFC1_ARRAY[ GPIO_FROM_PFC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS +volatile struct st_gpio_from_pmc0* GPIO_FROM_PMC0_ARRAY[ GPIO_FROM_PMC0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS +volatile struct st_gpio_from_pm1* GPIO_FROM_PM1_ARRAY[ GPIO_FROM_PM1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PM1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS +volatile struct st_gpio_from_ppr0* GPIO_FROM_PPR0_ARRAY[ GPIO_FROM_PPR0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS +volatile struct st_gpio_from_p1* GPIO_FROM_P1_ARRAY[ GPIO_FROM_P1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_P1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS */ +/* End of channel array defines of GPIO (2)*/ -#define GPIOP1 GPIO.P1 -#define GPIOP2 GPIO.P2 -#define GPIOP3 GPIO.P3 -#define GPIOP4 GPIO.P4 -#define GPIOP5 GPIO.P5 -#define GPIOP6 GPIO.P6 -#define GPIOP7 GPIO.P7 -#define GPIOP8 GPIO.P8 -#define GPIOP9 GPIO.P9 -#define GPIOP10 GPIO.P10 -#define GPIOP11 GPIO.P11 -#define GPIOPSR1 GPIO.PSR1 -#define GPIOPSR2 GPIO.PSR2 -#define GPIOPSR3 GPIO.PSR3 -#define GPIOPSR4 GPIO.PSR4 -#define GPIOPSR5 GPIO.PSR5 -#define GPIOPSR6 GPIO.PSR6 -#define GPIOPSR7 GPIO.PSR7 -#define GPIOPSR8 GPIO.PSR8 -#define GPIOPSR9 GPIO.PSR9 -#define GPIOPSR10 GPIO.PSR10 -#define GPIOPSR11 GPIO.PSR11 -#define GPIOPPR0 GPIO.PPR0 -#define GPIOPPR1 GPIO.PPR1 -#define GPIOPPR2 GPIO.PPR2 -#define GPIOPPR3 GPIO.PPR3 -#define GPIOPPR4 GPIO.PPR4 -#define GPIOPPR5 GPIO.PPR5 -#define GPIOPPR6 GPIO.PPR6 -#define GPIOPPR7 GPIO.PPR7 -#define GPIOPPR8 GPIO.PPR8 -#define GPIOPPR9 GPIO.PPR9 -#define GPIOPPR10 GPIO.PPR10 -#define GPIOPPR11 GPIO.PPR11 -#define GPIOPM1 GPIO.PM1 -#define GPIOPM2 GPIO.PM2 -#define GPIOPM3 GPIO.PM3 -#define GPIOPM4 GPIO.PM4 -#define GPIOPM5 GPIO.PM5 -#define GPIOPM6 GPIO.PM6 -#define GPIOPM7 GPIO.PM7 -#define GPIOPM8 GPIO.PM8 -#define GPIOPM9 GPIO.PM9 -#define GPIOPM10 GPIO.PM10 -#define GPIOPM11 GPIO.PM11 -#define GPIOPMC0 GPIO.PMC0 -#define GPIOPMC1 GPIO.PMC1 -#define GPIOPMC2 GPIO.PMC2 -#define GPIOPMC3 GPIO.PMC3 -#define GPIOPMC4 GPIO.PMC4 -#define GPIOPMC5 GPIO.PMC5 -#define GPIOPMC6 GPIO.PMC6 -#define GPIOPMC7 GPIO.PMC7 -#define GPIOPMC8 GPIO.PMC8 -#define GPIOPMC9 GPIO.PMC9 -#define GPIOPMC10 GPIO.PMC10 -#define GPIOPMC11 GPIO.PMC11 -#define GPIOPFC1 GPIO.PFC1 -#define GPIOPFC2 GPIO.PFC2 -#define GPIOPFC3 GPIO.PFC3 -#define GPIOPFC4 GPIO.PFC4 -#define GPIOPFC5 GPIO.PFC5 -#define GPIOPFC6 GPIO.PFC6 -#define GPIOPFC7 GPIO.PFC7 -#define GPIOPFC8 GPIO.PFC8 -#define GPIOPFC9 GPIO.PFC9 -#define GPIOPFC10 GPIO.PFC10 -#define GPIOPFC11 GPIO.PFC11 -#define GPIOPFCE1 GPIO.PFCE1 -#define GPIOPFCE2 GPIO.PFCE2 -#define GPIOPFCE3 GPIO.PFCE3 -#define GPIOPFCE4 GPIO.PFCE4 -#define GPIOPFCE5 GPIO.PFCE5 -#define GPIOPFCE6 GPIO.PFCE6 -#define GPIOPFCE7 GPIO.PFCE7 -#define GPIOPFCE8 GPIO.PFCE8 -#define GPIOPFCE9 GPIO.PFCE9 -#define GPIOPFCE10 GPIO.PFCE10 -#define GPIOPFCE11 GPIO.PFCE11 -#define GPIOPNOT1 GPIO.PNOT1 -#define GPIOPNOT2 GPIO.PNOT2 -#define GPIOPNOT3 GPIO.PNOT3 -#define GPIOPNOT4 GPIO.PNOT4 -#define GPIOPNOT5 GPIO.PNOT5 -#define GPIOPNOT6 GPIO.PNOT6 -#define GPIOPNOT7 GPIO.PNOT7 -#define GPIOPNOT8 GPIO.PNOT8 -#define GPIOPNOT9 GPIO.PNOT9 -#define GPIOPNOT10 GPIO.PNOT10 -#define GPIOPNOT11 GPIO.PNOT11 -#define GPIOPMSR1 GPIO.PMSR1 -#define GPIOPMSR2 GPIO.PMSR2 -#define GPIOPMSR3 GPIO.PMSR3 -#define GPIOPMSR4 GPIO.PMSR4 -#define GPIOPMSR5 GPIO.PMSR5 -#define GPIOPMSR6 GPIO.PMSR6 -#define GPIOPMSR7 GPIO.PMSR7 -#define GPIOPMSR8 GPIO.PMSR8 -#define GPIOPMSR9 GPIO.PMSR9 -#define GPIOPMSR10 GPIO.PMSR10 -#define GPIOPMSR11 GPIO.PMSR11 -#define GPIOPMCSR0 GPIO.PMCSR0 -#define GPIOPMCSR1 GPIO.PMCSR1 -#define GPIOPMCSR2 GPIO.PMCSR2 -#define GPIOPMCSR3 GPIO.PMCSR3 -#define GPIOPMCSR4 GPIO.PMCSR4 -#define GPIOPMCSR5 GPIO.PMCSR5 -#define GPIOPMCSR6 GPIO.PMCSR6 -#define GPIOPMCSR7 GPIO.PMCSR7 -#define GPIOPMCSR8 GPIO.PMCSR8 -#define GPIOPMCSR9 GPIO.PMCSR9 -#define GPIOPMCSR10 GPIO.PMCSR10 -#define GPIOPMCSR11 GPIO.PMCSR11 -#define GPIOPFCAE1 GPIO.PFCAE1 -#define GPIOPFCAE2 GPIO.PFCAE2 -#define GPIOPFCAE3 GPIO.PFCAE3 -#define GPIOPFCAE4 GPIO.PFCAE4 -#define GPIOPFCAE5 GPIO.PFCAE5 -#define GPIOPFCAE6 GPIO.PFCAE6 -#define GPIOPFCAE7 GPIO.PFCAE7 -#define GPIOPFCAE8 GPIO.PFCAE8 -#define GPIOPFCAE9 GPIO.PFCAE9 -#define GPIOPFCAE10 GPIO.PFCAE10 -#define GPIOPFCAE11 GPIO.PFCAE11 -#define GPIOSNCR GPIO.SNCR -#define GPIOPIBC0 GPIO.PIBC0 -#define GPIOPIBC1 GPIO.PIBC1 -#define GPIOPIBC2 GPIO.PIBC2 -#define GPIOPIBC3 GPIO.PIBC3 -#define GPIOPIBC4 GPIO.PIBC4 -#define GPIOPIBC5 GPIO.PIBC5 -#define GPIOPIBC6 GPIO.PIBC6 -#define GPIOPIBC7 GPIO.PIBC7 -#define GPIOPIBC8 GPIO.PIBC8 -#define GPIOPIBC9 GPIO.PIBC9 -#define GPIOPIBC10 GPIO.PIBC10 -#define GPIOPIBC11 GPIO.PIBC11 -#define GPIOPBDC1 GPIO.PBDC1 -#define GPIOPBDC2 GPIO.PBDC2 -#define GPIOPBDC3 GPIO.PBDC3 -#define GPIOPBDC4 GPIO.PBDC4 -#define GPIOPBDC5 GPIO.PBDC5 -#define GPIOPBDC6 GPIO.PBDC6 -#define GPIOPBDC7 GPIO.PBDC7 -#define GPIOPBDC8 GPIO.PBDC8 -#define GPIOPBDC9 GPIO.PBDC9 -#define GPIOPBDC10 GPIO.PBDC10 -#define GPIOPBDC11 GPIO.PBDC11 -#define GPIOPIPC1 GPIO.PIPC1 -#define GPIOPIPC2 GPIO.PIPC2 -#define GPIOPIPC3 GPIO.PIPC3 -#define GPIOPIPC4 GPIO.PIPC4 -#define GPIOPIPC5 GPIO.PIPC5 -#define GPIOPIPC6 GPIO.PIPC6 -#define GPIOPIPC7 GPIO.PIPC7 -#define GPIOPIPC8 GPIO.PIPC8 -#define GPIOPIPC9 GPIO.PIPC9 -#define GPIOPIPC10 GPIO.PIPC10 -#define GPIOPIPC11 GPIO.PIPC11 -#define GPIOJPPR0 GPIO.JPPR0 -#define GPIOJPMC0 GPIO.JPMC0 -#define GPIOJPMCSR0 GPIO.JPMCSR0 -#define GPIOJPIBC0 GPIO.JPIBC0 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h index 8b76e23c6f..5dee5fab31 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h @@ -18,20 +18,55 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ieb_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef IEB_IODEFINE_H #define IEB_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ieb -{ /* IEB */ +#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */ + + +#define IEBB0BCR (IEB.B0BCR) +#define IEBB0PSR (IEB.B0PSR) +#define IEBB0UAR (IEB.B0UAR) +#define IEBB0SAR (IEB.B0SAR) +#define IEBB0PAR (IEB.B0PAR) +#define IEBB0RSA (IEB.B0RSA) +#define IEBB0CDR (IEB.B0CDR) +#define IEBB0TCD (IEB.B0TCD) +#define IEBB0RCD (IEB.B0RCD) +#define IEBB0DLR (IEB.B0DLR) +#define IEBB0TDL (IEB.B0TDL) +#define IEBB0RDL (IEB.B0RDL) +#define IEBB0CKS (IEB.B0CKS) +#define IEBB0TMS (IEB.B0TMS) +#define IEBB0PCR (IEB.B0PCR) +#define IEBB0BSR (IEB.B0BSR) +#define IEBB0SSR (IEB.B0SSR) +#define IEBB0USR (IEB.B0USR) +#define IEBB0ISR (IEB.B0ISR) +#define IEBB0ESR (IEB.B0ESR) +#define IEBB0FSR (IEB.B0FSR) +#define IEBB0SCR (IEB.B0SCR) +#define IEBB0CCR (IEB.B0CCR) +#define IEBB0STC0 (IEB.B0STC0) +#define IEBB0STC1 (IEB.B0STC1) +#define IEBB0DR (IEB.B0DR) + + +typedef struct st_ieb +{ + /* IEB */ volatile uint8_t B0BCR; /* B0BCR */ volatile uint8_t dummy495[3]; /* */ volatile uint8_t B0PSR; /* B0PSR */ @@ -83,37 +118,11 @@ struct st_ieb volatile uint8_t B0STC1; /* B0STC1 */ volatile uint8_t dummy519[3]; /* */ volatile uint8_t B0DR; /* B0DR */ -}; +} r_io_ieb_t; -#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */ - - -#define IEBB0BCR IEB.B0BCR -#define IEBB0PSR IEB.B0PSR -#define IEBB0UAR IEB.B0UAR -#define IEBB0SAR IEB.B0SAR -#define IEBB0PAR IEB.B0PAR -#define IEBB0RSA IEB.B0RSA -#define IEBB0CDR IEB.B0CDR -#define IEBB0TCD IEB.B0TCD -#define IEBB0RCD IEB.B0RCD -#define IEBB0DLR IEB.B0DLR -#define IEBB0TDL IEB.B0TDL -#define IEBB0RDL IEB.B0RDL -#define IEBB0CKS IEB.B0CKS -#define IEBB0TMS IEB.B0TMS -#define IEBB0PCR IEB.B0PCR -#define IEBB0BSR IEB.B0BSR -#define IEBB0SSR IEB.B0SSR -#define IEBB0USR IEB.B0USR -#define IEBB0ISR IEB.B0ISR -#define IEBB0ESR IEB.B0ESR -#define IEBB0FSR IEB.B0FSR -#define IEBB0SCR IEB.B0SCR -#define IEBB0CCR IEB.B0CCR -#define IEBB0STC0 IEB.B0STC0 -#define IEBB0STC1 IEB.B0STC1 -#define IEBB0DR IEB.B0DR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h index f8175a6978..ea148b05d4 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h @@ -18,21 +18,61 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : inb_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef INB_IODEFINE_H #define INB_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ -struct st_inb -{ /* INB */ +#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ + + +#define INBRMPR (INB.RMPR) +#define INBAXIBUSCTL0 (INB.AXIBUSCTL0) +#define INBAXIBUSCTL1 (INB.AXIBUSCTL1) +#define INBAXIBUSCTL2 (INB.AXIBUSCTL2) +#define INBAXIBUSCTL3 (INB.AXIBUSCTL3) +#define INBAXIBUSCTL4 (INB.AXIBUSCTL4) +#define INBAXIBUSCTL5 (INB.AXIBUSCTL5) +#define INBAXIBUSCTL6 (INB.AXIBUSCTL6) +#define INBAXIBUSCTL7 (INB.AXIBUSCTL7) +#define INBAXIBUSCTL8 (INB.AXIBUSCTL8) +#define INBAXIBUSCTL9 (INB.AXIBUSCTL9) +#define INBAXIBUSCTL10 (INB.AXIBUSCTL10) +#define INBAXIRERRCTL0 (INB.AXIRERRCTL0) +#define INBAXIRERRCTL1 (INB.AXIRERRCTL1) +#define INBAXIRERRCTL2 (INB.AXIRERRCTL2) +#define INBAXIRERRCTL3 (INB.AXIRERRCTL3) +#define INBAXIRERRST0 (INB.AXIRERRST0) +#define INBAXIRERRST1 (INB.AXIRERRST1) +#define INBAXIRERRST2 (INB.AXIRERRST2) +#define INBAXIRERRST3 (INB.AXIRERRST3) +#define INBAXIRERRCLR0 (INB.AXIRERRCLR0) +#define INBAXIRERRCLR1 (INB.AXIRERRCLR1) +#define INBAXIRERRCLR2 (INB.AXIRERRCLR2) +#define INBAXIRERRCLR3 (INB.AXIRERRCLR3) + +#define INB_AXIBUSCTLn_COUNT (11) +#define INB_AXIRERRCTLn_COUNT (4) +#define INB_AXIRERRSTn_COUNT (4) +#define INB_AXIRERRCLRn_COUNT (4) + + +typedef struct st_inb +{ + /* INB */ volatile uint32_t RMPR; /* RMPR */ -#define INB_AXIBUSCTLn_COUNT 11 + +/* #define INB_AXIBUSCTLn_COUNT (11) */ volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */ volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */ volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */ @@ -44,49 +84,29 @@ struct st_inb volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */ volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */ volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */ -#define INB_AXIRERRCTLn_COUNT 4 + +/* #define INB_AXIRERRCTLn_COUNT (4) */ volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */ volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */ volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */ volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */ -#define INB_AXIRERRSTn_COUNT 4 + +/* #define INB_AXIRERRSTn_COUNT (4) */ volatile uint32_t AXIRERRST0; /* AXIRERRST0 */ volatile uint32_t AXIRERRST1; /* AXIRERRST1 */ volatile uint32_t AXIRERRST2; /* AXIRERRST2 */ volatile uint32_t AXIRERRST3; /* AXIRERRST3 */ -#define INB_AXIRERRCLRn_COUNT 4 + +/* #define INB_AXIRERRCLRn_COUNT (4) */ volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */ volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */ volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */ volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */ -}; +} r_io_inb_t; -#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ - - -#define INBRMPR INB.RMPR -#define INBAXIBUSCTL0 INB.AXIBUSCTL0 -#define INBAXIBUSCTL1 INB.AXIBUSCTL1 -#define INBAXIBUSCTL2 INB.AXIBUSCTL2 -#define INBAXIBUSCTL3 INB.AXIBUSCTL3 -#define INBAXIBUSCTL4 INB.AXIBUSCTL4 -#define INBAXIBUSCTL5 INB.AXIBUSCTL5 -#define INBAXIBUSCTL6 INB.AXIBUSCTL6 -#define INBAXIBUSCTL7 INB.AXIBUSCTL7 -#define INBAXIBUSCTL8 INB.AXIBUSCTL8 -#define INBAXIBUSCTL9 INB.AXIBUSCTL9 -#define INBAXIBUSCTL10 INB.AXIBUSCTL10 -#define INBAXIRERRCTL0 INB.AXIRERRCTL0 -#define INBAXIRERRCTL1 INB.AXIRERRCTL1 -#define INBAXIRERRCTL2 INB.AXIRERRCTL2 -#define INBAXIRERRCTL3 INB.AXIRERRCTL3 -#define INBAXIRERRST0 INB.AXIRERRST0 -#define INBAXIRERRST1 INB.AXIRERRST1 -#define INBAXIRERRST2 INB.AXIRERRST2 -#define INBAXIRERRST3 INB.AXIRERRST3 -#define INBAXIRERRCLR0 INB.AXIRERRCLR0 -#define INBAXIRERRCLR1 INB.AXIRERRCLR1 -#define INBAXIRERRCLR2 INB.AXIRERRCLR2 -#define INBAXIRERRCLR3 INB.AXIRERRCLR3 +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h index 253d4b9399..6ee9ea1bab 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h @@ -18,26 +18,525 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : intc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef INTC_IODEFINE_H #define INTC_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_intc -{ /* INTC */ +#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */ + + +#define INTCICDDCR (INTC.ICDDCR) +#define INTCICDICTR (INTC.ICDICTR) +#define INTCICDIIDR (INTC.ICDIIDR) +#define INTCICDISR0 (INTC.ICDISR0) +#define INTCICDISR1 (INTC.ICDISR1) +#define INTCICDISR2 (INTC.ICDISR2) +#define INTCICDISR3 (INTC.ICDISR3) +#define INTCICDISR4 (INTC.ICDISR4) +#define INTCICDISR5 (INTC.ICDISR5) +#define INTCICDISR6 (INTC.ICDISR6) +#define INTCICDISR7 (INTC.ICDISR7) +#define INTCICDISR8 (INTC.ICDISR8) +#define INTCICDISR9 (INTC.ICDISR9) +#define INTCICDISR10 (INTC.ICDISR10) +#define INTCICDISR11 (INTC.ICDISR11) +#define INTCICDISR12 (INTC.ICDISR12) +#define INTCICDISR13 (INTC.ICDISR13) +#define INTCICDISR14 (INTC.ICDISR14) +#define INTCICDISR15 (INTC.ICDISR15) +#define INTCICDISR16 (INTC.ICDISR16) +#define INTCICDISR17 (INTC.ICDISR17) +#define INTCICDISR18 (INTC.ICDISR18) +#define INTCICDISER0 (INTC.ICDISER0) +#define INTCICDISER1 (INTC.ICDISER1) +#define INTCICDISER2 (INTC.ICDISER2) +#define INTCICDISER3 (INTC.ICDISER3) +#define INTCICDISER4 (INTC.ICDISER4) +#define INTCICDISER5 (INTC.ICDISER5) +#define INTCICDISER6 (INTC.ICDISER6) +#define INTCICDISER7 (INTC.ICDISER7) +#define INTCICDISER8 (INTC.ICDISER8) +#define INTCICDISER9 (INTC.ICDISER9) +#define INTCICDISER10 (INTC.ICDISER10) +#define INTCICDISER11 (INTC.ICDISER11) +#define INTCICDISER12 (INTC.ICDISER12) +#define INTCICDISER13 (INTC.ICDISER13) +#define INTCICDISER14 (INTC.ICDISER14) +#define INTCICDISER15 (INTC.ICDISER15) +#define INTCICDISER16 (INTC.ICDISER16) +#define INTCICDISER17 (INTC.ICDISER17) +#define INTCICDISER18 (INTC.ICDISER18) +#define INTCICDICER0 (INTC.ICDICER0) +#define INTCICDICER1 (INTC.ICDICER1) +#define INTCICDICER2 (INTC.ICDICER2) +#define INTCICDICER3 (INTC.ICDICER3) +#define INTCICDICER4 (INTC.ICDICER4) +#define INTCICDICER5 (INTC.ICDICER5) +#define INTCICDICER6 (INTC.ICDICER6) +#define INTCICDICER7 (INTC.ICDICER7) +#define INTCICDICER8 (INTC.ICDICER8) +#define INTCICDICER9 (INTC.ICDICER9) +#define INTCICDICER10 (INTC.ICDICER10) +#define INTCICDICER11 (INTC.ICDICER11) +#define INTCICDICER12 (INTC.ICDICER12) +#define INTCICDICER13 (INTC.ICDICER13) +#define INTCICDICER14 (INTC.ICDICER14) +#define INTCICDICER15 (INTC.ICDICER15) +#define INTCICDICER16 (INTC.ICDICER16) +#define INTCICDICER17 (INTC.ICDICER17) +#define INTCICDICER18 (INTC.ICDICER18) +#define INTCICDISPR0 (INTC.ICDISPR0) +#define INTCICDISPR1 (INTC.ICDISPR1) +#define INTCICDISPR2 (INTC.ICDISPR2) +#define INTCICDISPR3 (INTC.ICDISPR3) +#define INTCICDISPR4 (INTC.ICDISPR4) +#define INTCICDISPR5 (INTC.ICDISPR5) +#define INTCICDISPR6 (INTC.ICDISPR6) +#define INTCICDISPR7 (INTC.ICDISPR7) +#define INTCICDISPR8 (INTC.ICDISPR8) +#define INTCICDISPR9 (INTC.ICDISPR9) +#define INTCICDISPR10 (INTC.ICDISPR10) +#define INTCICDISPR11 (INTC.ICDISPR11) +#define INTCICDISPR12 (INTC.ICDISPR12) +#define INTCICDISPR13 (INTC.ICDISPR13) +#define INTCICDISPR14 (INTC.ICDISPR14) +#define INTCICDISPR15 (INTC.ICDISPR15) +#define INTCICDISPR16 (INTC.ICDISPR16) +#define INTCICDISPR17 (INTC.ICDISPR17) +#define INTCICDISPR18 (INTC.ICDISPR18) +#define INTCICDICPR0 (INTC.ICDICPR0) +#define INTCICDICPR1 (INTC.ICDICPR1) +#define INTCICDICPR2 (INTC.ICDICPR2) +#define INTCICDICPR3 (INTC.ICDICPR3) +#define INTCICDICPR4 (INTC.ICDICPR4) +#define INTCICDICPR5 (INTC.ICDICPR5) +#define INTCICDICPR6 (INTC.ICDICPR6) +#define INTCICDICPR7 (INTC.ICDICPR7) +#define INTCICDICPR8 (INTC.ICDICPR8) +#define INTCICDICPR9 (INTC.ICDICPR9) +#define INTCICDICPR10 (INTC.ICDICPR10) +#define INTCICDICPR11 (INTC.ICDICPR11) +#define INTCICDICPR12 (INTC.ICDICPR12) +#define INTCICDICPR13 (INTC.ICDICPR13) +#define INTCICDICPR14 (INTC.ICDICPR14) +#define INTCICDICPR15 (INTC.ICDICPR15) +#define INTCICDICPR16 (INTC.ICDICPR16) +#define INTCICDICPR17 (INTC.ICDICPR17) +#define INTCICDICPR18 (INTC.ICDICPR18) +#define INTCICDABR0 (INTC.ICDABR0) +#define INTCICDABR1 (INTC.ICDABR1) +#define INTCICDABR2 (INTC.ICDABR2) +#define INTCICDABR3 (INTC.ICDABR3) +#define INTCICDABR4 (INTC.ICDABR4) +#define INTCICDABR5 (INTC.ICDABR5) +#define INTCICDABR6 (INTC.ICDABR6) +#define INTCICDABR7 (INTC.ICDABR7) +#define INTCICDABR8 (INTC.ICDABR8) +#define INTCICDABR9 (INTC.ICDABR9) +#define INTCICDABR10 (INTC.ICDABR10) +#define INTCICDABR11 (INTC.ICDABR11) +#define INTCICDABR12 (INTC.ICDABR12) +#define INTCICDABR13 (INTC.ICDABR13) +#define INTCICDABR14 (INTC.ICDABR14) +#define INTCICDABR15 (INTC.ICDABR15) +#define INTCICDABR16 (INTC.ICDABR16) +#define INTCICDABR17 (INTC.ICDABR17) +#define INTCICDABR18 (INTC.ICDABR18) +#define INTCICDIPR0 (INTC.ICDIPR0) +#define INTCICDIPR1 (INTC.ICDIPR1) +#define INTCICDIPR2 (INTC.ICDIPR2) +#define INTCICDIPR3 (INTC.ICDIPR3) +#define INTCICDIPR4 (INTC.ICDIPR4) +#define INTCICDIPR5 (INTC.ICDIPR5) +#define INTCICDIPR6 (INTC.ICDIPR6) +#define INTCICDIPR7 (INTC.ICDIPR7) +#define INTCICDIPR8 (INTC.ICDIPR8) +#define INTCICDIPR9 (INTC.ICDIPR9) +#define INTCICDIPR10 (INTC.ICDIPR10) +#define INTCICDIPR11 (INTC.ICDIPR11) +#define INTCICDIPR12 (INTC.ICDIPR12) +#define INTCICDIPR13 (INTC.ICDIPR13) +#define INTCICDIPR14 (INTC.ICDIPR14) +#define INTCICDIPR15 (INTC.ICDIPR15) +#define INTCICDIPR16 (INTC.ICDIPR16) +#define INTCICDIPR17 (INTC.ICDIPR17) +#define INTCICDIPR18 (INTC.ICDIPR18) +#define INTCICDIPR19 (INTC.ICDIPR19) +#define INTCICDIPR20 (INTC.ICDIPR20) +#define INTCICDIPR21 (INTC.ICDIPR21) +#define INTCICDIPR22 (INTC.ICDIPR22) +#define INTCICDIPR23 (INTC.ICDIPR23) +#define INTCICDIPR24 (INTC.ICDIPR24) +#define INTCICDIPR25 (INTC.ICDIPR25) +#define INTCICDIPR26 (INTC.ICDIPR26) +#define INTCICDIPR27 (INTC.ICDIPR27) +#define INTCICDIPR28 (INTC.ICDIPR28) +#define INTCICDIPR29 (INTC.ICDIPR29) +#define INTCICDIPR30 (INTC.ICDIPR30) +#define INTCICDIPR31 (INTC.ICDIPR31) +#define INTCICDIPR32 (INTC.ICDIPR32) +#define INTCICDIPR33 (INTC.ICDIPR33) +#define INTCICDIPR34 (INTC.ICDIPR34) +#define INTCICDIPR35 (INTC.ICDIPR35) +#define INTCICDIPR36 (INTC.ICDIPR36) +#define INTCICDIPR37 (INTC.ICDIPR37) +#define INTCICDIPR38 (INTC.ICDIPR38) +#define INTCICDIPR39 (INTC.ICDIPR39) +#define INTCICDIPR40 (INTC.ICDIPR40) +#define INTCICDIPR41 (INTC.ICDIPR41) +#define INTCICDIPR42 (INTC.ICDIPR42) +#define INTCICDIPR43 (INTC.ICDIPR43) +#define INTCICDIPR44 (INTC.ICDIPR44) +#define INTCICDIPR45 (INTC.ICDIPR45) +#define INTCICDIPR46 (INTC.ICDIPR46) +#define INTCICDIPR47 (INTC.ICDIPR47) +#define INTCICDIPR48 (INTC.ICDIPR48) +#define INTCICDIPR49 (INTC.ICDIPR49) +#define INTCICDIPR50 (INTC.ICDIPR50) +#define INTCICDIPR51 (INTC.ICDIPR51) +#define INTCICDIPR52 (INTC.ICDIPR52) +#define INTCICDIPR53 (INTC.ICDIPR53) +#define INTCICDIPR54 (INTC.ICDIPR54) +#define INTCICDIPR55 (INTC.ICDIPR55) +#define INTCICDIPR56 (INTC.ICDIPR56) +#define INTCICDIPR57 (INTC.ICDIPR57) +#define INTCICDIPR58 (INTC.ICDIPR58) +#define INTCICDIPR59 (INTC.ICDIPR59) +#define INTCICDIPR60 (INTC.ICDIPR60) +#define INTCICDIPR61 (INTC.ICDIPR61) +#define INTCICDIPR62 (INTC.ICDIPR62) +#define INTCICDIPR63 (INTC.ICDIPR63) +#define INTCICDIPR64 (INTC.ICDIPR64) +#define INTCICDIPR65 (INTC.ICDIPR65) +#define INTCICDIPR66 (INTC.ICDIPR66) +#define INTCICDIPR67 (INTC.ICDIPR67) +#define INTCICDIPR68 (INTC.ICDIPR68) +#define INTCICDIPR69 (INTC.ICDIPR69) +#define INTCICDIPR70 (INTC.ICDIPR70) +#define INTCICDIPR71 (INTC.ICDIPR71) +#define INTCICDIPR72 (INTC.ICDIPR72) +#define INTCICDIPR73 (INTC.ICDIPR73) +#define INTCICDIPR74 (INTC.ICDIPR74) +#define INTCICDIPR75 (INTC.ICDIPR75) +#define INTCICDIPR76 (INTC.ICDIPR76) +#define INTCICDIPR77 (INTC.ICDIPR77) +#define INTCICDIPR78 (INTC.ICDIPR78) +#define INTCICDIPR79 (INTC.ICDIPR79) +#define INTCICDIPR80 (INTC.ICDIPR80) +#define INTCICDIPR81 (INTC.ICDIPR81) +#define INTCICDIPR82 (INTC.ICDIPR82) +#define INTCICDIPR83 (INTC.ICDIPR83) +#define INTCICDIPR84 (INTC.ICDIPR84) +#define INTCICDIPR85 (INTC.ICDIPR85) +#define INTCICDIPR86 (INTC.ICDIPR86) +#define INTCICDIPR87 (INTC.ICDIPR87) +#define INTCICDIPR88 (INTC.ICDIPR88) +#define INTCICDIPR89 (INTC.ICDIPR89) +#define INTCICDIPR90 (INTC.ICDIPR90) +#define INTCICDIPR91 (INTC.ICDIPR91) +#define INTCICDIPR92 (INTC.ICDIPR92) +#define INTCICDIPR93 (INTC.ICDIPR93) +#define INTCICDIPR94 (INTC.ICDIPR94) +#define INTCICDIPR95 (INTC.ICDIPR95) +#define INTCICDIPR96 (INTC.ICDIPR96) +#define INTCICDIPR97 (INTC.ICDIPR97) +#define INTCICDIPR98 (INTC.ICDIPR98) +#define INTCICDIPR99 (INTC.ICDIPR99) +#define INTCICDIPR100 (INTC.ICDIPR100) +#define INTCICDIPR101 (INTC.ICDIPR101) +#define INTCICDIPR102 (INTC.ICDIPR102) +#define INTCICDIPR103 (INTC.ICDIPR103) +#define INTCICDIPR104 (INTC.ICDIPR104) +#define INTCICDIPR105 (INTC.ICDIPR105) +#define INTCICDIPR106 (INTC.ICDIPR106) +#define INTCICDIPR107 (INTC.ICDIPR107) +#define INTCICDIPR108 (INTC.ICDIPR108) +#define INTCICDIPR109 (INTC.ICDIPR109) +#define INTCICDIPR110 (INTC.ICDIPR110) +#define INTCICDIPR111 (INTC.ICDIPR111) +#define INTCICDIPR112 (INTC.ICDIPR112) +#define INTCICDIPR113 (INTC.ICDIPR113) +#define INTCICDIPR114 (INTC.ICDIPR114) +#define INTCICDIPR115 (INTC.ICDIPR115) +#define INTCICDIPR116 (INTC.ICDIPR116) +#define INTCICDIPR117 (INTC.ICDIPR117) +#define INTCICDIPR118 (INTC.ICDIPR118) +#define INTCICDIPR119 (INTC.ICDIPR119) +#define INTCICDIPR120 (INTC.ICDIPR120) +#define INTCICDIPR121 (INTC.ICDIPR121) +#define INTCICDIPR122 (INTC.ICDIPR122) +#define INTCICDIPR123 (INTC.ICDIPR123) +#define INTCICDIPR124 (INTC.ICDIPR124) +#define INTCICDIPR125 (INTC.ICDIPR125) +#define INTCICDIPR126 (INTC.ICDIPR126) +#define INTCICDIPR127 (INTC.ICDIPR127) +#define INTCICDIPR128 (INTC.ICDIPR128) +#define INTCICDIPR129 (INTC.ICDIPR129) +#define INTCICDIPR130 (INTC.ICDIPR130) +#define INTCICDIPR131 (INTC.ICDIPR131) +#define INTCICDIPR132 (INTC.ICDIPR132) +#define INTCICDIPR133 (INTC.ICDIPR133) +#define INTCICDIPR134 (INTC.ICDIPR134) +#define INTCICDIPR135 (INTC.ICDIPR135) +#define INTCICDIPR136 (INTC.ICDIPR136) +#define INTCICDIPR137 (INTC.ICDIPR137) +#define INTCICDIPR138 (INTC.ICDIPR138) +#define INTCICDIPR139 (INTC.ICDIPR139) +#define INTCICDIPR140 (INTC.ICDIPR140) +#define INTCICDIPR141 (INTC.ICDIPR141) +#define INTCICDIPR142 (INTC.ICDIPR142) +#define INTCICDIPR143 (INTC.ICDIPR143) +#define INTCICDIPR144 (INTC.ICDIPR144) +#define INTCICDIPR145 (INTC.ICDIPR145) +#define INTCICDIPR146 (INTC.ICDIPR146) +#define INTCICDIPTR0 (INTC.ICDIPTR0) +#define INTCICDIPTR1 (INTC.ICDIPTR1) +#define INTCICDIPTR2 (INTC.ICDIPTR2) +#define INTCICDIPTR3 (INTC.ICDIPTR3) +#define INTCICDIPTR4 (INTC.ICDIPTR4) +#define INTCICDIPTR5 (INTC.ICDIPTR5) +#define INTCICDIPTR6 (INTC.ICDIPTR6) +#define INTCICDIPTR7 (INTC.ICDIPTR7) +#define INTCICDIPTR8 (INTC.ICDIPTR8) +#define INTCICDIPTR9 (INTC.ICDIPTR9) +#define INTCICDIPTR10 (INTC.ICDIPTR10) +#define INTCICDIPTR11 (INTC.ICDIPTR11) +#define INTCICDIPTR12 (INTC.ICDIPTR12) +#define INTCICDIPTR13 (INTC.ICDIPTR13) +#define INTCICDIPTR14 (INTC.ICDIPTR14) +#define INTCICDIPTR15 (INTC.ICDIPTR15) +#define INTCICDIPTR16 (INTC.ICDIPTR16) +#define INTCICDIPTR17 (INTC.ICDIPTR17) +#define INTCICDIPTR18 (INTC.ICDIPTR18) +#define INTCICDIPTR19 (INTC.ICDIPTR19) +#define INTCICDIPTR20 (INTC.ICDIPTR20) +#define INTCICDIPTR21 (INTC.ICDIPTR21) +#define INTCICDIPTR22 (INTC.ICDIPTR22) +#define INTCICDIPTR23 (INTC.ICDIPTR23) +#define INTCICDIPTR24 (INTC.ICDIPTR24) +#define INTCICDIPTR25 (INTC.ICDIPTR25) +#define INTCICDIPTR26 (INTC.ICDIPTR26) +#define INTCICDIPTR27 (INTC.ICDIPTR27) +#define INTCICDIPTR28 (INTC.ICDIPTR28) +#define INTCICDIPTR29 (INTC.ICDIPTR29) +#define INTCICDIPTR30 (INTC.ICDIPTR30) +#define INTCICDIPTR31 (INTC.ICDIPTR31) +#define INTCICDIPTR32 (INTC.ICDIPTR32) +#define INTCICDIPTR33 (INTC.ICDIPTR33) +#define INTCICDIPTR34 (INTC.ICDIPTR34) +#define INTCICDIPTR35 (INTC.ICDIPTR35) +#define INTCICDIPTR36 (INTC.ICDIPTR36) +#define INTCICDIPTR37 (INTC.ICDIPTR37) +#define INTCICDIPTR38 (INTC.ICDIPTR38) +#define INTCICDIPTR39 (INTC.ICDIPTR39) +#define INTCICDIPTR40 (INTC.ICDIPTR40) +#define INTCICDIPTR41 (INTC.ICDIPTR41) +#define INTCICDIPTR42 (INTC.ICDIPTR42) +#define INTCICDIPTR43 (INTC.ICDIPTR43) +#define INTCICDIPTR44 (INTC.ICDIPTR44) +#define INTCICDIPTR45 (INTC.ICDIPTR45) +#define INTCICDIPTR46 (INTC.ICDIPTR46) +#define INTCICDIPTR47 (INTC.ICDIPTR47) +#define INTCICDIPTR48 (INTC.ICDIPTR48) +#define INTCICDIPTR49 (INTC.ICDIPTR49) +#define INTCICDIPTR50 (INTC.ICDIPTR50) +#define INTCICDIPTR51 (INTC.ICDIPTR51) +#define INTCICDIPTR52 (INTC.ICDIPTR52) +#define INTCICDIPTR53 (INTC.ICDIPTR53) +#define INTCICDIPTR54 (INTC.ICDIPTR54) +#define INTCICDIPTR55 (INTC.ICDIPTR55) +#define INTCICDIPTR56 (INTC.ICDIPTR56) +#define INTCICDIPTR57 (INTC.ICDIPTR57) +#define INTCICDIPTR58 (INTC.ICDIPTR58) +#define INTCICDIPTR59 (INTC.ICDIPTR59) +#define INTCICDIPTR60 (INTC.ICDIPTR60) +#define INTCICDIPTR61 (INTC.ICDIPTR61) +#define INTCICDIPTR62 (INTC.ICDIPTR62) +#define INTCICDIPTR63 (INTC.ICDIPTR63) +#define INTCICDIPTR64 (INTC.ICDIPTR64) +#define INTCICDIPTR65 (INTC.ICDIPTR65) +#define INTCICDIPTR66 (INTC.ICDIPTR66) +#define INTCICDIPTR67 (INTC.ICDIPTR67) +#define INTCICDIPTR68 (INTC.ICDIPTR68) +#define INTCICDIPTR69 (INTC.ICDIPTR69) +#define INTCICDIPTR70 (INTC.ICDIPTR70) +#define INTCICDIPTR71 (INTC.ICDIPTR71) +#define INTCICDIPTR72 (INTC.ICDIPTR72) +#define INTCICDIPTR73 (INTC.ICDIPTR73) +#define INTCICDIPTR74 (INTC.ICDIPTR74) +#define INTCICDIPTR75 (INTC.ICDIPTR75) +#define INTCICDIPTR76 (INTC.ICDIPTR76) +#define INTCICDIPTR77 (INTC.ICDIPTR77) +#define INTCICDIPTR78 (INTC.ICDIPTR78) +#define INTCICDIPTR79 (INTC.ICDIPTR79) +#define INTCICDIPTR80 (INTC.ICDIPTR80) +#define INTCICDIPTR81 (INTC.ICDIPTR81) +#define INTCICDIPTR82 (INTC.ICDIPTR82) +#define INTCICDIPTR83 (INTC.ICDIPTR83) +#define INTCICDIPTR84 (INTC.ICDIPTR84) +#define INTCICDIPTR85 (INTC.ICDIPTR85) +#define INTCICDIPTR86 (INTC.ICDIPTR86) +#define INTCICDIPTR87 (INTC.ICDIPTR87) +#define INTCICDIPTR88 (INTC.ICDIPTR88) +#define INTCICDIPTR89 (INTC.ICDIPTR89) +#define INTCICDIPTR90 (INTC.ICDIPTR90) +#define INTCICDIPTR91 (INTC.ICDIPTR91) +#define INTCICDIPTR92 (INTC.ICDIPTR92) +#define INTCICDIPTR93 (INTC.ICDIPTR93) +#define INTCICDIPTR94 (INTC.ICDIPTR94) +#define INTCICDIPTR95 (INTC.ICDIPTR95) +#define INTCICDIPTR96 (INTC.ICDIPTR96) +#define INTCICDIPTR97 (INTC.ICDIPTR97) +#define INTCICDIPTR98 (INTC.ICDIPTR98) +#define INTCICDIPTR99 (INTC.ICDIPTR99) +#define INTCICDIPTR100 (INTC.ICDIPTR100) +#define INTCICDIPTR101 (INTC.ICDIPTR101) +#define INTCICDIPTR102 (INTC.ICDIPTR102) +#define INTCICDIPTR103 (INTC.ICDIPTR103) +#define INTCICDIPTR104 (INTC.ICDIPTR104) +#define INTCICDIPTR105 (INTC.ICDIPTR105) +#define INTCICDIPTR106 (INTC.ICDIPTR106) +#define INTCICDIPTR107 (INTC.ICDIPTR107) +#define INTCICDIPTR108 (INTC.ICDIPTR108) +#define INTCICDIPTR109 (INTC.ICDIPTR109) +#define INTCICDIPTR110 (INTC.ICDIPTR110) +#define INTCICDIPTR111 (INTC.ICDIPTR111) +#define INTCICDIPTR112 (INTC.ICDIPTR112) +#define INTCICDIPTR113 (INTC.ICDIPTR113) +#define INTCICDIPTR114 (INTC.ICDIPTR114) +#define INTCICDIPTR115 (INTC.ICDIPTR115) +#define INTCICDIPTR116 (INTC.ICDIPTR116) +#define INTCICDIPTR117 (INTC.ICDIPTR117) +#define INTCICDIPTR118 (INTC.ICDIPTR118) +#define INTCICDIPTR119 (INTC.ICDIPTR119) +#define INTCICDIPTR120 (INTC.ICDIPTR120) +#define INTCICDIPTR121 (INTC.ICDIPTR121) +#define INTCICDIPTR122 (INTC.ICDIPTR122) +#define INTCICDIPTR123 (INTC.ICDIPTR123) +#define INTCICDIPTR124 (INTC.ICDIPTR124) +#define INTCICDIPTR125 (INTC.ICDIPTR125) +#define INTCICDIPTR126 (INTC.ICDIPTR126) +#define INTCICDIPTR127 (INTC.ICDIPTR127) +#define INTCICDIPTR128 (INTC.ICDIPTR128) +#define INTCICDIPTR129 (INTC.ICDIPTR129) +#define INTCICDIPTR130 (INTC.ICDIPTR130) +#define INTCICDIPTR131 (INTC.ICDIPTR131) +#define INTCICDIPTR132 (INTC.ICDIPTR132) +#define INTCICDIPTR133 (INTC.ICDIPTR133) +#define INTCICDIPTR134 (INTC.ICDIPTR134) +#define INTCICDIPTR135 (INTC.ICDIPTR135) +#define INTCICDIPTR136 (INTC.ICDIPTR136) +#define INTCICDIPTR137 (INTC.ICDIPTR137) +#define INTCICDIPTR138 (INTC.ICDIPTR138) +#define INTCICDIPTR139 (INTC.ICDIPTR139) +#define INTCICDIPTR140 (INTC.ICDIPTR140) +#define INTCICDIPTR141 (INTC.ICDIPTR141) +#define INTCICDIPTR142 (INTC.ICDIPTR142) +#define INTCICDIPTR143 (INTC.ICDIPTR143) +#define INTCICDIPTR144 (INTC.ICDIPTR144) +#define INTCICDIPTR145 (INTC.ICDIPTR145) +#define INTCICDIPTR146 (INTC.ICDIPTR146) +#define INTCICDICFR0 (INTC.ICDICFR0) +#define INTCICDICFR1 (INTC.ICDICFR1) +#define INTCICDICFR2 (INTC.ICDICFR2) +#define INTCICDICFR3 (INTC.ICDICFR3) +#define INTCICDICFR4 (INTC.ICDICFR4) +#define INTCICDICFR5 (INTC.ICDICFR5) +#define INTCICDICFR6 (INTC.ICDICFR6) +#define INTCICDICFR7 (INTC.ICDICFR7) +#define INTCICDICFR8 (INTC.ICDICFR8) +#define INTCICDICFR9 (INTC.ICDICFR9) +#define INTCICDICFR10 (INTC.ICDICFR10) +#define INTCICDICFR11 (INTC.ICDICFR11) +#define INTCICDICFR12 (INTC.ICDICFR12) +#define INTCICDICFR13 (INTC.ICDICFR13) +#define INTCICDICFR14 (INTC.ICDICFR14) +#define INTCICDICFR15 (INTC.ICDICFR15) +#define INTCICDICFR16 (INTC.ICDICFR16) +#define INTCICDICFR17 (INTC.ICDICFR17) +#define INTCICDICFR18 (INTC.ICDICFR18) +#define INTCICDICFR19 (INTC.ICDICFR19) +#define INTCICDICFR20 (INTC.ICDICFR20) +#define INTCICDICFR21 (INTC.ICDICFR21) +#define INTCICDICFR22 (INTC.ICDICFR22) +#define INTCICDICFR23 (INTC.ICDICFR23) +#define INTCICDICFR24 (INTC.ICDICFR24) +#define INTCICDICFR25 (INTC.ICDICFR25) +#define INTCICDICFR26 (INTC.ICDICFR26) +#define INTCICDICFR27 (INTC.ICDICFR27) +#define INTCICDICFR28 (INTC.ICDICFR28) +#define INTCICDICFR29 (INTC.ICDICFR29) +#define INTCICDICFR30 (INTC.ICDICFR30) +#define INTCICDICFR31 (INTC.ICDICFR31) +#define INTCICDICFR32 (INTC.ICDICFR32) +#define INTCICDICFR33 (INTC.ICDICFR33) +#define INTCICDICFR34 (INTC.ICDICFR34) +#define INTCICDICFR35 (INTC.ICDICFR35) +#define INTCICDICFR36 (INTC.ICDICFR36) +#define INTCPPI_STATUS (INTC.PPI_STATUS) +#define INTCSPI_STATUS0 (INTC.SPI_STATUS0) +#define INTCSPI_STATUS1 (INTC.SPI_STATUS1) +#define INTCSPI_STATUS2 (INTC.SPI_STATUS2) +#define INTCSPI_STATUS3 (INTC.SPI_STATUS3) +#define INTCSPI_STATUS4 (INTC.SPI_STATUS4) +#define INTCSPI_STATUS5 (INTC.SPI_STATUS5) +#define INTCSPI_STATUS6 (INTC.SPI_STATUS6) +#define INTCSPI_STATUS7 (INTC.SPI_STATUS7) +#define INTCSPI_STATUS8 (INTC.SPI_STATUS8) +#define INTCSPI_STATUS9 (INTC.SPI_STATUS9) +#define INTCSPI_STATUS10 (INTC.SPI_STATUS10) +#define INTCSPI_STATUS11 (INTC.SPI_STATUS11) +#define INTCSPI_STATUS12 (INTC.SPI_STATUS12) +#define INTCSPI_STATUS13 (INTC.SPI_STATUS13) +#define INTCSPI_STATUS14 (INTC.SPI_STATUS14) +#define INTCSPI_STATUS15 (INTC.SPI_STATUS15) +#define INTCSPI_STATUS16 (INTC.SPI_STATUS16) +#define INTCICDSGIR (INTC.ICDSGIR) +#define INTCICCICR (INTC.ICCICR) +#define INTCICCPMR (INTC.ICCPMR) +#define INTCICCBPR (INTC.ICCBPR) +#define INTCICCIAR (INTC.ICCIAR) +#define INTCICCEOIR (INTC.ICCEOIR) +#define INTCICCRPR (INTC.ICCRPR) +#define INTCICCHPIR (INTC.ICCHPIR) +#define INTCICCABPR (INTC.ICCABPR) +#define INTCICCIIDR (INTC.ICCIIDR) +#define INTCICR0 (INTC.ICR0) +#define INTCICR1 (INTC.ICR1) +#define INTCIRQRR (INTC.IRQRR) + +#define INTC_ICDISR0_COUNT (19) +#define INTC_ICDISER0_COUNT (19) +#define INTC_ICDICER0_COUNT (19) +#define INTC_ICDISPR0_COUNT (19) +#define INTC_ICDICPR0_COUNT (19) +#define INTC_ICDABR0_COUNT (19) +#define INTC_ICDIPR0_COUNT (147) +#define INTC_ICDIPTR0_COUNT (147) +#define INTC_ICDICFR0_COUNT (37) +#define INTC_SPI_STATUS0_COUNT (17) + + +typedef struct st_intc +{ + /* INTC */ volatile uint32_t ICDDCR; /* ICDDCR */ volatile uint32_t ICDICTR; /* ICDICTR */ volatile uint32_t ICDIIDR; /* ICDIIDR */ volatile uint8_t dummy193[116]; /* */ -#define INTC_ICDISR0_COUNT 19 + +/* #define INTC_ICDISR0_COUNT (19) */ volatile uint32_t ICDISR0; /* ICDISR0 */ volatile uint32_t ICDISR1; /* ICDISR1 */ volatile uint32_t ICDISR2; /* ICDISR2 */ @@ -58,7 +557,8 @@ struct st_intc volatile uint32_t ICDISR17; /* ICDISR17 */ volatile uint32_t ICDISR18; /* ICDISR18 */ volatile uint8_t dummy194[52]; /* */ -#define INTC_ICDISER0_COUNT 19 + +/* #define INTC_ICDISER0_COUNT (19) */ volatile uint32_t ICDISER0; /* ICDISER0 */ volatile uint32_t ICDISER1; /* ICDISER1 */ volatile uint32_t ICDISER2; /* ICDISER2 */ @@ -79,7 +579,8 @@ struct st_intc volatile uint32_t ICDISER17; /* ICDISER17 */ volatile uint32_t ICDISER18; /* ICDISER18 */ volatile uint8_t dummy195[52]; /* */ -#define INTC_ICDICER0_COUNT 19 + +/* #define INTC_ICDICER0_COUNT (19) */ volatile uint32_t ICDICER0; /* ICDICER0 */ volatile uint32_t ICDICER1; /* ICDICER1 */ volatile uint32_t ICDICER2; /* ICDICER2 */ @@ -100,7 +601,8 @@ struct st_intc volatile uint32_t ICDICER17; /* ICDICER17 */ volatile uint32_t ICDICER18; /* ICDICER18 */ volatile uint8_t dummy196[52]; /* */ -#define INTC_ICDISPR0_COUNT 19 + +/* #define INTC_ICDISPR0_COUNT (19) */ volatile uint32_t ICDISPR0; /* ICDISPR0 */ volatile uint32_t ICDISPR1; /* ICDISPR1 */ volatile uint32_t ICDISPR2; /* ICDISPR2 */ @@ -121,7 +623,8 @@ struct st_intc volatile uint32_t ICDISPR17; /* ICDISPR17 */ volatile uint32_t ICDISPR18; /* ICDISPR18 */ volatile uint8_t dummy197[52]; /* */ -#define INTC_ICDICPR0_COUNT 19 + +/* #define INTC_ICDICPR0_COUNT (19) */ volatile uint32_t ICDICPR0; /* ICDICPR0 */ volatile uint32_t ICDICPR1; /* ICDICPR1 */ volatile uint32_t ICDICPR2; /* ICDICPR2 */ @@ -142,7 +645,8 @@ struct st_intc volatile uint32_t ICDICPR17; /* ICDICPR17 */ volatile uint32_t ICDICPR18; /* ICDICPR18 */ volatile uint8_t dummy198[52]; /* */ -#define INTC_ICDABR0_COUNT 19 + +/* #define INTC_ICDABR0_COUNT (19) */ volatile uint32_t ICDABR0; /* ICDABR0 */ volatile uint32_t ICDABR1; /* ICDABR1 */ volatile uint32_t ICDABR2; /* ICDABR2 */ @@ -163,7 +667,8 @@ struct st_intc volatile uint32_t ICDABR17; /* ICDABR17 */ volatile uint32_t ICDABR18; /* ICDABR18 */ volatile uint8_t dummy199[180]; /* */ -#define INTC_ICDIPR0_COUNT 147 + +/* #define INTC_ICDIPR0_COUNT (147) */ volatile uint32_t ICDIPR0; /* ICDIPR0 */ volatile uint32_t ICDIPR1; /* ICDIPR1 */ volatile uint32_t ICDIPR2; /* ICDIPR2 */ @@ -312,7 +817,8 @@ struct st_intc volatile uint32_t ICDIPR145; /* ICDIPR145 */ volatile uint32_t ICDIPR146; /* ICDIPR146 */ volatile uint8_t dummy200[436]; /* */ -#define INTC_ICDIPTR0_COUNT 147 + +/* #define INTC_ICDIPTR0_COUNT (147) */ volatile uint32_t ICDIPTR0; /* ICDIPTR0 */ volatile uint32_t ICDIPTR1; /* ICDIPTR1 */ volatile uint32_t ICDIPTR2; /* ICDIPTR2 */ @@ -461,7 +967,8 @@ struct st_intc volatile uint32_t ICDIPTR145; /* ICDIPTR145 */ volatile uint32_t ICDIPTR146; /* ICDIPTR146 */ volatile uint8_t dummy201[436]; /* */ -#define INTC_ICDICFR0_COUNT 37 + +/* #define INTC_ICDICFR0_COUNT (37) */ volatile uint32_t ICDICFR0; /* ICDICFR0 */ volatile uint32_t ICDICFR1; /* ICDICFR1 */ volatile uint32_t ICDICFR2; /* ICDICFR2 */ @@ -501,7 +1008,8 @@ struct st_intc volatile uint32_t ICDICFR36; /* ICDICFR36 */ volatile uint8_t dummy202[108]; /* */ volatile uint32_t PPI_STATUS; /* PPI_STATUS */ -#define INTC_SPI_STATUS0_COUNT 17 + +/* #define INTC_SPI_STATUS0_COUNT (17) */ volatile uint32_t SPI_STATUS0; /* SPI_STATUS0 */ volatile uint32_t SPI_STATUS1; /* SPI_STATUS1 */ volatile uint32_t SPI_STATUS2; /* SPI_STATUS2 */ @@ -536,491 +1044,11 @@ struct st_intc volatile uint16_t ICR0; /* ICR0 */ volatile uint16_t ICR1; /* ICR1 */ volatile uint16_t IRQRR; /* IRQRR */ -}; +} r_io_intc_t; -#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */ - - -#define INTCICDDCR INTC.ICDDCR -#define INTCICDICTR INTC.ICDICTR -#define INTCICDIIDR INTC.ICDIIDR -#define INTCICDISR0 INTC.ICDISR0 -#define INTCICDISR1 INTC.ICDISR1 -#define INTCICDISR2 INTC.ICDISR2 -#define INTCICDISR3 INTC.ICDISR3 -#define INTCICDISR4 INTC.ICDISR4 -#define INTCICDISR5 INTC.ICDISR5 -#define INTCICDISR6 INTC.ICDISR6 -#define INTCICDISR7 INTC.ICDISR7 -#define INTCICDISR8 INTC.ICDISR8 -#define INTCICDISR9 INTC.ICDISR9 -#define INTCICDISR10 INTC.ICDISR10 -#define INTCICDISR11 INTC.ICDISR11 -#define INTCICDISR12 INTC.ICDISR12 -#define INTCICDISR13 INTC.ICDISR13 -#define INTCICDISR14 INTC.ICDISR14 -#define INTCICDISR15 INTC.ICDISR15 -#define INTCICDISR16 INTC.ICDISR16 -#define INTCICDISR17 INTC.ICDISR17 -#define INTCICDISR18 INTC.ICDISR18 -#define INTCICDISER0 INTC.ICDISER0 -#define INTCICDISER1 INTC.ICDISER1 -#define INTCICDISER2 INTC.ICDISER2 -#define INTCICDISER3 INTC.ICDISER3 -#define INTCICDISER4 INTC.ICDISER4 -#define INTCICDISER5 INTC.ICDISER5 -#define INTCICDISER6 INTC.ICDISER6 -#define INTCICDISER7 INTC.ICDISER7 -#define INTCICDISER8 INTC.ICDISER8 -#define INTCICDISER9 INTC.ICDISER9 -#define INTCICDISER10 INTC.ICDISER10 -#define INTCICDISER11 INTC.ICDISER11 -#define INTCICDISER12 INTC.ICDISER12 -#define INTCICDISER13 INTC.ICDISER13 -#define INTCICDISER14 INTC.ICDISER14 -#define INTCICDISER15 INTC.ICDISER15 -#define INTCICDISER16 INTC.ICDISER16 -#define INTCICDISER17 INTC.ICDISER17 -#define INTCICDISER18 INTC.ICDISER18 -#define INTCICDICER0 INTC.ICDICER0 -#define INTCICDICER1 INTC.ICDICER1 -#define INTCICDICER2 INTC.ICDICER2 -#define INTCICDICER3 INTC.ICDICER3 -#define INTCICDICER4 INTC.ICDICER4 -#define INTCICDICER5 INTC.ICDICER5 -#define INTCICDICER6 INTC.ICDICER6 -#define INTCICDICER7 INTC.ICDICER7 -#define INTCICDICER8 INTC.ICDICER8 -#define INTCICDICER9 INTC.ICDICER9 -#define INTCICDICER10 INTC.ICDICER10 -#define INTCICDICER11 INTC.ICDICER11 -#define INTCICDICER12 INTC.ICDICER12 -#define INTCICDICER13 INTC.ICDICER13 -#define INTCICDICER14 INTC.ICDICER14 -#define INTCICDICER15 INTC.ICDICER15 -#define INTCICDICER16 INTC.ICDICER16 -#define INTCICDICER17 INTC.ICDICER17 -#define INTCICDICER18 INTC.ICDICER18 -#define INTCICDISPR0 INTC.ICDISPR0 -#define INTCICDISPR1 INTC.ICDISPR1 -#define INTCICDISPR2 INTC.ICDISPR2 -#define INTCICDISPR3 INTC.ICDISPR3 -#define INTCICDISPR4 INTC.ICDISPR4 -#define INTCICDISPR5 INTC.ICDISPR5 -#define INTCICDISPR6 INTC.ICDISPR6 -#define INTCICDISPR7 INTC.ICDISPR7 -#define INTCICDISPR8 INTC.ICDISPR8 -#define INTCICDISPR9 INTC.ICDISPR9 -#define INTCICDISPR10 INTC.ICDISPR10 -#define INTCICDISPR11 INTC.ICDISPR11 -#define INTCICDISPR12 INTC.ICDISPR12 -#define INTCICDISPR13 INTC.ICDISPR13 -#define INTCICDISPR14 INTC.ICDISPR14 -#define INTCICDISPR15 INTC.ICDISPR15 -#define INTCICDISPR16 INTC.ICDISPR16 -#define INTCICDISPR17 INTC.ICDISPR17 -#define INTCICDISPR18 INTC.ICDISPR18 -#define INTCICDICPR0 INTC.ICDICPR0 -#define INTCICDICPR1 INTC.ICDICPR1 -#define INTCICDICPR2 INTC.ICDICPR2 -#define INTCICDICPR3 INTC.ICDICPR3 -#define INTCICDICPR4 INTC.ICDICPR4 -#define INTCICDICPR5 INTC.ICDICPR5 -#define INTCICDICPR6 INTC.ICDICPR6 -#define INTCICDICPR7 INTC.ICDICPR7 -#define INTCICDICPR8 INTC.ICDICPR8 -#define INTCICDICPR9 INTC.ICDICPR9 -#define INTCICDICPR10 INTC.ICDICPR10 -#define INTCICDICPR11 INTC.ICDICPR11 -#define INTCICDICPR12 INTC.ICDICPR12 -#define INTCICDICPR13 INTC.ICDICPR13 -#define INTCICDICPR14 INTC.ICDICPR14 -#define INTCICDICPR15 INTC.ICDICPR15 -#define INTCICDICPR16 INTC.ICDICPR16 -#define INTCICDICPR17 INTC.ICDICPR17 -#define INTCICDICPR18 INTC.ICDICPR18 -#define INTCICDABR0 INTC.ICDABR0 -#define INTCICDABR1 INTC.ICDABR1 -#define INTCICDABR2 INTC.ICDABR2 -#define INTCICDABR3 INTC.ICDABR3 -#define INTCICDABR4 INTC.ICDABR4 -#define INTCICDABR5 INTC.ICDABR5 -#define INTCICDABR6 INTC.ICDABR6 -#define INTCICDABR7 INTC.ICDABR7 -#define INTCICDABR8 INTC.ICDABR8 -#define INTCICDABR9 INTC.ICDABR9 -#define INTCICDABR10 INTC.ICDABR10 -#define INTCICDABR11 INTC.ICDABR11 -#define INTCICDABR12 INTC.ICDABR12 -#define INTCICDABR13 INTC.ICDABR13 -#define INTCICDABR14 INTC.ICDABR14 -#define INTCICDABR15 INTC.ICDABR15 -#define INTCICDABR16 INTC.ICDABR16 -#define INTCICDABR17 INTC.ICDABR17 -#define INTCICDABR18 INTC.ICDABR18 -#define INTCICDIPR0 INTC.ICDIPR0 -#define INTCICDIPR1 INTC.ICDIPR1 -#define INTCICDIPR2 INTC.ICDIPR2 -#define INTCICDIPR3 INTC.ICDIPR3 -#define INTCICDIPR4 INTC.ICDIPR4 -#define INTCICDIPR5 INTC.ICDIPR5 -#define INTCICDIPR6 INTC.ICDIPR6 -#define INTCICDIPR7 INTC.ICDIPR7 -#define INTCICDIPR8 INTC.ICDIPR8 -#define INTCICDIPR9 INTC.ICDIPR9 -#define INTCICDIPR10 INTC.ICDIPR10 -#define INTCICDIPR11 INTC.ICDIPR11 -#define INTCICDIPR12 INTC.ICDIPR12 -#define INTCICDIPR13 INTC.ICDIPR13 -#define INTCICDIPR14 INTC.ICDIPR14 -#define INTCICDIPR15 INTC.ICDIPR15 -#define INTCICDIPR16 INTC.ICDIPR16 -#define INTCICDIPR17 INTC.ICDIPR17 -#define INTCICDIPR18 INTC.ICDIPR18 -#define INTCICDIPR19 INTC.ICDIPR19 -#define INTCICDIPR20 INTC.ICDIPR20 -#define INTCICDIPR21 INTC.ICDIPR21 -#define INTCICDIPR22 INTC.ICDIPR22 -#define INTCICDIPR23 INTC.ICDIPR23 -#define INTCICDIPR24 INTC.ICDIPR24 -#define INTCICDIPR25 INTC.ICDIPR25 -#define INTCICDIPR26 INTC.ICDIPR26 -#define INTCICDIPR27 INTC.ICDIPR27 -#define INTCICDIPR28 INTC.ICDIPR28 -#define INTCICDIPR29 INTC.ICDIPR29 -#define INTCICDIPR30 INTC.ICDIPR30 -#define INTCICDIPR31 INTC.ICDIPR31 -#define INTCICDIPR32 INTC.ICDIPR32 -#define INTCICDIPR33 INTC.ICDIPR33 -#define INTCICDIPR34 INTC.ICDIPR34 -#define INTCICDIPR35 INTC.ICDIPR35 -#define INTCICDIPR36 INTC.ICDIPR36 -#define INTCICDIPR37 INTC.ICDIPR37 -#define INTCICDIPR38 INTC.ICDIPR38 -#define INTCICDIPR39 INTC.ICDIPR39 -#define INTCICDIPR40 INTC.ICDIPR40 -#define INTCICDIPR41 INTC.ICDIPR41 -#define INTCICDIPR42 INTC.ICDIPR42 -#define INTCICDIPR43 INTC.ICDIPR43 -#define INTCICDIPR44 INTC.ICDIPR44 -#define INTCICDIPR45 INTC.ICDIPR45 -#define INTCICDIPR46 INTC.ICDIPR46 -#define INTCICDIPR47 INTC.ICDIPR47 -#define INTCICDIPR48 INTC.ICDIPR48 -#define INTCICDIPR49 INTC.ICDIPR49 -#define INTCICDIPR50 INTC.ICDIPR50 -#define INTCICDIPR51 INTC.ICDIPR51 -#define INTCICDIPR52 INTC.ICDIPR52 -#define INTCICDIPR53 INTC.ICDIPR53 -#define INTCICDIPR54 INTC.ICDIPR54 -#define INTCICDIPR55 INTC.ICDIPR55 -#define INTCICDIPR56 INTC.ICDIPR56 -#define INTCICDIPR57 INTC.ICDIPR57 -#define INTCICDIPR58 INTC.ICDIPR58 -#define INTCICDIPR59 INTC.ICDIPR59 -#define INTCICDIPR60 INTC.ICDIPR60 -#define INTCICDIPR61 INTC.ICDIPR61 -#define INTCICDIPR62 INTC.ICDIPR62 -#define INTCICDIPR63 INTC.ICDIPR63 -#define INTCICDIPR64 INTC.ICDIPR64 -#define INTCICDIPR65 INTC.ICDIPR65 -#define INTCICDIPR66 INTC.ICDIPR66 -#define INTCICDIPR67 INTC.ICDIPR67 -#define INTCICDIPR68 INTC.ICDIPR68 -#define INTCICDIPR69 INTC.ICDIPR69 -#define INTCICDIPR70 INTC.ICDIPR70 -#define INTCICDIPR71 INTC.ICDIPR71 -#define INTCICDIPR72 INTC.ICDIPR72 -#define INTCICDIPR73 INTC.ICDIPR73 -#define INTCICDIPR74 INTC.ICDIPR74 -#define INTCICDIPR75 INTC.ICDIPR75 -#define INTCICDIPR76 INTC.ICDIPR76 -#define INTCICDIPR77 INTC.ICDIPR77 -#define INTCICDIPR78 INTC.ICDIPR78 -#define INTCICDIPR79 INTC.ICDIPR79 -#define INTCICDIPR80 INTC.ICDIPR80 -#define INTCICDIPR81 INTC.ICDIPR81 -#define INTCICDIPR82 INTC.ICDIPR82 -#define INTCICDIPR83 INTC.ICDIPR83 -#define INTCICDIPR84 INTC.ICDIPR84 -#define INTCICDIPR85 INTC.ICDIPR85 -#define INTCICDIPR86 INTC.ICDIPR86 -#define INTCICDIPR87 INTC.ICDIPR87 -#define INTCICDIPR88 INTC.ICDIPR88 -#define INTCICDIPR89 INTC.ICDIPR89 -#define INTCICDIPR90 INTC.ICDIPR90 -#define INTCICDIPR91 INTC.ICDIPR91 -#define INTCICDIPR92 INTC.ICDIPR92 -#define INTCICDIPR93 INTC.ICDIPR93 -#define INTCICDIPR94 INTC.ICDIPR94 -#define INTCICDIPR95 INTC.ICDIPR95 -#define INTCICDIPR96 INTC.ICDIPR96 -#define INTCICDIPR97 INTC.ICDIPR97 -#define INTCICDIPR98 INTC.ICDIPR98 -#define INTCICDIPR99 INTC.ICDIPR99 -#define INTCICDIPR100 INTC.ICDIPR100 -#define INTCICDIPR101 INTC.ICDIPR101 -#define INTCICDIPR102 INTC.ICDIPR102 -#define INTCICDIPR103 INTC.ICDIPR103 -#define INTCICDIPR104 INTC.ICDIPR104 -#define INTCICDIPR105 INTC.ICDIPR105 -#define INTCICDIPR106 INTC.ICDIPR106 -#define INTCICDIPR107 INTC.ICDIPR107 -#define INTCICDIPR108 INTC.ICDIPR108 -#define INTCICDIPR109 INTC.ICDIPR109 -#define INTCICDIPR110 INTC.ICDIPR110 -#define INTCICDIPR111 INTC.ICDIPR111 -#define INTCICDIPR112 INTC.ICDIPR112 -#define INTCICDIPR113 INTC.ICDIPR113 -#define INTCICDIPR114 INTC.ICDIPR114 -#define INTCICDIPR115 INTC.ICDIPR115 -#define INTCICDIPR116 INTC.ICDIPR116 -#define INTCICDIPR117 INTC.ICDIPR117 -#define INTCICDIPR118 INTC.ICDIPR118 -#define INTCICDIPR119 INTC.ICDIPR119 -#define INTCICDIPR120 INTC.ICDIPR120 -#define INTCICDIPR121 INTC.ICDIPR121 -#define INTCICDIPR122 INTC.ICDIPR122 -#define INTCICDIPR123 INTC.ICDIPR123 -#define INTCICDIPR124 INTC.ICDIPR124 -#define INTCICDIPR125 INTC.ICDIPR125 -#define INTCICDIPR126 INTC.ICDIPR126 -#define INTCICDIPR127 INTC.ICDIPR127 -#define INTCICDIPR128 INTC.ICDIPR128 -#define INTCICDIPR129 INTC.ICDIPR129 -#define INTCICDIPR130 INTC.ICDIPR130 -#define INTCICDIPR131 INTC.ICDIPR131 -#define INTCICDIPR132 INTC.ICDIPR132 -#define INTCICDIPR133 INTC.ICDIPR133 -#define INTCICDIPR134 INTC.ICDIPR134 -#define INTCICDIPR135 INTC.ICDIPR135 -#define INTCICDIPR136 INTC.ICDIPR136 -#define INTCICDIPR137 INTC.ICDIPR137 -#define INTCICDIPR138 INTC.ICDIPR138 -#define INTCICDIPR139 INTC.ICDIPR139 -#define INTCICDIPR140 INTC.ICDIPR140 -#define INTCICDIPR141 INTC.ICDIPR141 -#define INTCICDIPR142 INTC.ICDIPR142 -#define INTCICDIPR143 INTC.ICDIPR143 -#define INTCICDIPR144 INTC.ICDIPR144 -#define INTCICDIPR145 INTC.ICDIPR145 -#define INTCICDIPR146 INTC.ICDIPR146 -#define INTCICDIPTR0 INTC.ICDIPTR0 -#define INTCICDIPTR1 INTC.ICDIPTR1 -#define INTCICDIPTR2 INTC.ICDIPTR2 -#define INTCICDIPTR3 INTC.ICDIPTR3 -#define INTCICDIPTR4 INTC.ICDIPTR4 -#define INTCICDIPTR5 INTC.ICDIPTR5 -#define INTCICDIPTR6 INTC.ICDIPTR6 -#define INTCICDIPTR7 INTC.ICDIPTR7 -#define INTCICDIPTR8 INTC.ICDIPTR8 -#define INTCICDIPTR9 INTC.ICDIPTR9 -#define INTCICDIPTR10 INTC.ICDIPTR10 -#define INTCICDIPTR11 INTC.ICDIPTR11 -#define INTCICDIPTR12 INTC.ICDIPTR12 -#define INTCICDIPTR13 INTC.ICDIPTR13 -#define INTCICDIPTR14 INTC.ICDIPTR14 -#define INTCICDIPTR15 INTC.ICDIPTR15 -#define INTCICDIPTR16 INTC.ICDIPTR16 -#define INTCICDIPTR17 INTC.ICDIPTR17 -#define INTCICDIPTR18 INTC.ICDIPTR18 -#define INTCICDIPTR19 INTC.ICDIPTR19 -#define INTCICDIPTR20 INTC.ICDIPTR20 -#define INTCICDIPTR21 INTC.ICDIPTR21 -#define INTCICDIPTR22 INTC.ICDIPTR22 -#define INTCICDIPTR23 INTC.ICDIPTR23 -#define INTCICDIPTR24 INTC.ICDIPTR24 -#define INTCICDIPTR25 INTC.ICDIPTR25 -#define INTCICDIPTR26 INTC.ICDIPTR26 -#define INTCICDIPTR27 INTC.ICDIPTR27 -#define INTCICDIPTR28 INTC.ICDIPTR28 -#define INTCICDIPTR29 INTC.ICDIPTR29 -#define INTCICDIPTR30 INTC.ICDIPTR30 -#define INTCICDIPTR31 INTC.ICDIPTR31 -#define INTCICDIPTR32 INTC.ICDIPTR32 -#define INTCICDIPTR33 INTC.ICDIPTR33 -#define INTCICDIPTR34 INTC.ICDIPTR34 -#define INTCICDIPTR35 INTC.ICDIPTR35 -#define INTCICDIPTR36 INTC.ICDIPTR36 -#define INTCICDIPTR37 INTC.ICDIPTR37 -#define INTCICDIPTR38 INTC.ICDIPTR38 -#define INTCICDIPTR39 INTC.ICDIPTR39 -#define INTCICDIPTR40 INTC.ICDIPTR40 -#define INTCICDIPTR41 INTC.ICDIPTR41 -#define INTCICDIPTR42 INTC.ICDIPTR42 -#define INTCICDIPTR43 INTC.ICDIPTR43 -#define INTCICDIPTR44 INTC.ICDIPTR44 -#define INTCICDIPTR45 INTC.ICDIPTR45 -#define INTCICDIPTR46 INTC.ICDIPTR46 -#define INTCICDIPTR47 INTC.ICDIPTR47 -#define INTCICDIPTR48 INTC.ICDIPTR48 -#define INTCICDIPTR49 INTC.ICDIPTR49 -#define INTCICDIPTR50 INTC.ICDIPTR50 -#define INTCICDIPTR51 INTC.ICDIPTR51 -#define INTCICDIPTR52 INTC.ICDIPTR52 -#define INTCICDIPTR53 INTC.ICDIPTR53 -#define INTCICDIPTR54 INTC.ICDIPTR54 -#define INTCICDIPTR55 INTC.ICDIPTR55 -#define INTCICDIPTR56 INTC.ICDIPTR56 -#define INTCICDIPTR57 INTC.ICDIPTR57 -#define INTCICDIPTR58 INTC.ICDIPTR58 -#define INTCICDIPTR59 INTC.ICDIPTR59 -#define INTCICDIPTR60 INTC.ICDIPTR60 -#define INTCICDIPTR61 INTC.ICDIPTR61 -#define INTCICDIPTR62 INTC.ICDIPTR62 -#define INTCICDIPTR63 INTC.ICDIPTR63 -#define INTCICDIPTR64 INTC.ICDIPTR64 -#define INTCICDIPTR65 INTC.ICDIPTR65 -#define INTCICDIPTR66 INTC.ICDIPTR66 -#define INTCICDIPTR67 INTC.ICDIPTR67 -#define INTCICDIPTR68 INTC.ICDIPTR68 -#define INTCICDIPTR69 INTC.ICDIPTR69 -#define INTCICDIPTR70 INTC.ICDIPTR70 -#define INTCICDIPTR71 INTC.ICDIPTR71 -#define INTCICDIPTR72 INTC.ICDIPTR72 -#define INTCICDIPTR73 INTC.ICDIPTR73 -#define INTCICDIPTR74 INTC.ICDIPTR74 -#define INTCICDIPTR75 INTC.ICDIPTR75 -#define INTCICDIPTR76 INTC.ICDIPTR76 -#define INTCICDIPTR77 INTC.ICDIPTR77 -#define INTCICDIPTR78 INTC.ICDIPTR78 -#define INTCICDIPTR79 INTC.ICDIPTR79 -#define INTCICDIPTR80 INTC.ICDIPTR80 -#define INTCICDIPTR81 INTC.ICDIPTR81 -#define INTCICDIPTR82 INTC.ICDIPTR82 -#define INTCICDIPTR83 INTC.ICDIPTR83 -#define INTCICDIPTR84 INTC.ICDIPTR84 -#define INTCICDIPTR85 INTC.ICDIPTR85 -#define INTCICDIPTR86 INTC.ICDIPTR86 -#define INTCICDIPTR87 INTC.ICDIPTR87 -#define INTCICDIPTR88 INTC.ICDIPTR88 -#define INTCICDIPTR89 INTC.ICDIPTR89 -#define INTCICDIPTR90 INTC.ICDIPTR90 -#define INTCICDIPTR91 INTC.ICDIPTR91 -#define INTCICDIPTR92 INTC.ICDIPTR92 -#define INTCICDIPTR93 INTC.ICDIPTR93 -#define INTCICDIPTR94 INTC.ICDIPTR94 -#define INTCICDIPTR95 INTC.ICDIPTR95 -#define INTCICDIPTR96 INTC.ICDIPTR96 -#define INTCICDIPTR97 INTC.ICDIPTR97 -#define INTCICDIPTR98 INTC.ICDIPTR98 -#define INTCICDIPTR99 INTC.ICDIPTR99 -#define INTCICDIPTR100 INTC.ICDIPTR100 -#define INTCICDIPTR101 INTC.ICDIPTR101 -#define INTCICDIPTR102 INTC.ICDIPTR102 -#define INTCICDIPTR103 INTC.ICDIPTR103 -#define INTCICDIPTR104 INTC.ICDIPTR104 -#define INTCICDIPTR105 INTC.ICDIPTR105 -#define INTCICDIPTR106 INTC.ICDIPTR106 -#define INTCICDIPTR107 INTC.ICDIPTR107 -#define INTCICDIPTR108 INTC.ICDIPTR108 -#define INTCICDIPTR109 INTC.ICDIPTR109 -#define INTCICDIPTR110 INTC.ICDIPTR110 -#define INTCICDIPTR111 INTC.ICDIPTR111 -#define INTCICDIPTR112 INTC.ICDIPTR112 -#define INTCICDIPTR113 INTC.ICDIPTR113 -#define INTCICDIPTR114 INTC.ICDIPTR114 -#define INTCICDIPTR115 INTC.ICDIPTR115 -#define INTCICDIPTR116 INTC.ICDIPTR116 -#define INTCICDIPTR117 INTC.ICDIPTR117 -#define INTCICDIPTR118 INTC.ICDIPTR118 -#define INTCICDIPTR119 INTC.ICDIPTR119 -#define INTCICDIPTR120 INTC.ICDIPTR120 -#define INTCICDIPTR121 INTC.ICDIPTR121 -#define INTCICDIPTR122 INTC.ICDIPTR122 -#define INTCICDIPTR123 INTC.ICDIPTR123 -#define INTCICDIPTR124 INTC.ICDIPTR124 -#define INTCICDIPTR125 INTC.ICDIPTR125 -#define INTCICDIPTR126 INTC.ICDIPTR126 -#define INTCICDIPTR127 INTC.ICDIPTR127 -#define INTCICDIPTR128 INTC.ICDIPTR128 -#define INTCICDIPTR129 INTC.ICDIPTR129 -#define INTCICDIPTR130 INTC.ICDIPTR130 -#define INTCICDIPTR131 INTC.ICDIPTR131 -#define INTCICDIPTR132 INTC.ICDIPTR132 -#define INTCICDIPTR133 INTC.ICDIPTR133 -#define INTCICDIPTR134 INTC.ICDIPTR134 -#define INTCICDIPTR135 INTC.ICDIPTR135 -#define INTCICDIPTR136 INTC.ICDIPTR136 -#define INTCICDIPTR137 INTC.ICDIPTR137 -#define INTCICDIPTR138 INTC.ICDIPTR138 -#define INTCICDIPTR139 INTC.ICDIPTR139 -#define INTCICDIPTR140 INTC.ICDIPTR140 -#define INTCICDIPTR141 INTC.ICDIPTR141 -#define INTCICDIPTR142 INTC.ICDIPTR142 -#define INTCICDIPTR143 INTC.ICDIPTR143 -#define INTCICDIPTR144 INTC.ICDIPTR144 -#define INTCICDIPTR145 INTC.ICDIPTR145 -#define INTCICDIPTR146 INTC.ICDIPTR146 -#define INTCICDICFR0 INTC.ICDICFR0 -#define INTCICDICFR1 INTC.ICDICFR1 -#define INTCICDICFR2 INTC.ICDICFR2 -#define INTCICDICFR3 INTC.ICDICFR3 -#define INTCICDICFR4 INTC.ICDICFR4 -#define INTCICDICFR5 INTC.ICDICFR5 -#define INTCICDICFR6 INTC.ICDICFR6 -#define INTCICDICFR7 INTC.ICDICFR7 -#define INTCICDICFR8 INTC.ICDICFR8 -#define INTCICDICFR9 INTC.ICDICFR9 -#define INTCICDICFR10 INTC.ICDICFR10 -#define INTCICDICFR11 INTC.ICDICFR11 -#define INTCICDICFR12 INTC.ICDICFR12 -#define INTCICDICFR13 INTC.ICDICFR13 -#define INTCICDICFR14 INTC.ICDICFR14 -#define INTCICDICFR15 INTC.ICDICFR15 -#define INTCICDICFR16 INTC.ICDICFR16 -#define INTCICDICFR17 INTC.ICDICFR17 -#define INTCICDICFR18 INTC.ICDICFR18 -#define INTCICDICFR19 INTC.ICDICFR19 -#define INTCICDICFR20 INTC.ICDICFR20 -#define INTCICDICFR21 INTC.ICDICFR21 -#define INTCICDICFR22 INTC.ICDICFR22 -#define INTCICDICFR23 INTC.ICDICFR23 -#define INTCICDICFR24 INTC.ICDICFR24 -#define INTCICDICFR25 INTC.ICDICFR25 -#define INTCICDICFR26 INTC.ICDICFR26 -#define INTCICDICFR27 INTC.ICDICFR27 -#define INTCICDICFR28 INTC.ICDICFR28 -#define INTCICDICFR29 INTC.ICDICFR29 -#define INTCICDICFR30 INTC.ICDICFR30 -#define INTCICDICFR31 INTC.ICDICFR31 -#define INTCICDICFR32 INTC.ICDICFR32 -#define INTCICDICFR33 INTC.ICDICFR33 -#define INTCICDICFR34 INTC.ICDICFR34 -#define INTCICDICFR35 INTC.ICDICFR35 -#define INTCICDICFR36 INTC.ICDICFR36 -#define INTCPPI_STATUS INTC.PPI_STATUS -#define INTCSPI_STATUS0 INTC.SPI_STATUS0 -#define INTCSPI_STATUS1 INTC.SPI_STATUS1 -#define INTCSPI_STATUS2 INTC.SPI_STATUS2 -#define INTCSPI_STATUS3 INTC.SPI_STATUS3 -#define INTCSPI_STATUS4 INTC.SPI_STATUS4 -#define INTCSPI_STATUS5 INTC.SPI_STATUS5 -#define INTCSPI_STATUS6 INTC.SPI_STATUS6 -#define INTCSPI_STATUS7 INTC.SPI_STATUS7 -#define INTCSPI_STATUS8 INTC.SPI_STATUS8 -#define INTCSPI_STATUS9 INTC.SPI_STATUS9 -#define INTCSPI_STATUS10 INTC.SPI_STATUS10 -#define INTCSPI_STATUS11 INTC.SPI_STATUS11 -#define INTCSPI_STATUS12 INTC.SPI_STATUS12 -#define INTCSPI_STATUS13 INTC.SPI_STATUS13 -#define INTCSPI_STATUS14 INTC.SPI_STATUS14 -#define INTCSPI_STATUS15 INTC.SPI_STATUS15 -#define INTCSPI_STATUS16 INTC.SPI_STATUS16 -#define INTCICDSGIR INTC.ICDSGIR -#define INTCICCICR INTC.ICCICR -#define INTCICCPMR INTC.ICCPMR -#define INTCICCBPR INTC.ICCBPR -#define INTCICCIAR INTC.ICCIAR -#define INTCICCEOIR INTC.ICCEOIR -#define INTCICCRPR INTC.ICCRPR -#define INTCICCHPIR INTC.ICCHPIR -#define INTCICCABPR INTC.ICCABPR -#define INTCICCIIDR INTC.ICCIIDR -#define INTCICR0 INTC.ICR0 -#define INTCICR1 INTC.ICR1 -#define INTCIRQRR INTC.IRQRR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h new file mode 100644 index 0000000000..434b931933 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h @@ -0,0 +1,118 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : iodefine_typedef.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) +******************************************************************************/ +#ifndef IODEFINE_TYPEDEF_H +#define IODEFINE_TYPEDEF_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +/* Shared types and macros for iodefine.h */ + +/*********************************************************************** +* Macro: IODEFINE_H_VERSION +************************************************************************/ +#define IODEFINE_H_VERSION (200) + + +/*********************************************************************** +* Enum: iodefine_byte_select_t +* +* R_IO_L - Low 16bit or Low 8 bit +* R_IO_H - High 16bit or Low 8 bit +* R_IO_LL - Low 8 bit +* R_IO_LH - Middle Low 8 bit +* R_IO_HL - Middle High 8 bit +* R_IO_HH - High 8 bit +************************************************************************/ +typedef enum iodefine_byte_select_t +{ + R_IO_L = 0, R_IO_H = 1, + R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3, + L = 0, H = 1, + LL= 0, LH = 1, HL = 2, HH = 3 +} iodefine_byte_select_t; + + +/*********************************************************************** +* Type: iodefine_reg32_t +* 32/16/8 bit access register +* +* - Padding : sizeof(iodefine_reg32_t) == 4 +* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +* &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg32_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ + volatile uint8_t UINT8[4]; /* 8-bit Access */ +} iodefine_reg32_t; + + +/*********************************************************************** +* Type: iodefine_reg32_16_t +* 32/16 bit access register +* +* - Padding : sizeof(iodefine_reg32_16_t) == 4 +* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg32_16_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ +} iodefine_reg32_16_t; + + +/*********************************************************************** +* Type: iodefine_reg16_8_t +* 16/8 bit access register +* +* - Padding : sizeof(iodefine_reg16_8_t) == 2 +* - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg16_8_t +{ + volatile uint16_t UINT16; /* 16-bit Access */ + volatile uint8_t UINT8[2]; /* 8-bit Access */ +} iodefine_reg16_8_t; + + +/* End of shared types and macros for iodefine.h */ +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h index 14665ef2d6..eb5d842138 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h @@ -18,25 +18,36 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : irda_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef IRDA_IODEFINE_H #define IRDA_IODEFINE_H - -struct st_irda -{ /* IRDA */ - volatile uint8_t IRCR; /* IRCR */ -}; - +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ #define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */ -#define IRDAIRCR IRDA.IRCR +#define IRDAIRCR (IRDA.IRCR) + + +typedef struct st_irda +{ + /* IRDA */ + volatile uint8_t IRCR; /* IRCR */ +} r_io_irda_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h index fa34ce2150..de1db5846a 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h @@ -18,20 +18,88 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : jcu_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef JCU_IODEFINE_H #define JCU_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_jcu -{ /* JCU */ +#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */ + + +/* Start of channel array defines of JCU */ + +/* Channel array defines of JCU_JCQTBL0 */ +/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */ +#define JCU_JCQTBL0_COUNT (4) +#define JCU_JCQTBL0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */ +#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */ +#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */ +#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */ + +/* End of channel array defines of JCU */ + + +#define JCUJCMOD (JCU.JCMOD) +#define JCUJCCMD (JCU.JCCMD) +#define JCUJCQTN (JCU.JCQTN) +#define JCUJCHTN (JCU.JCHTN) +#define JCUJCDRIU (JCU.JCDRIU) +#define JCUJCDRID (JCU.JCDRID) +#define JCUJCVSZU (JCU.JCVSZU) +#define JCUJCVSZD (JCU.JCVSZD) +#define JCUJCHSZU (JCU.JCHSZU) +#define JCUJCHSZD (JCU.JCHSZD) +#define JCUJCDTCU (JCU.JCDTCU) +#define JCUJCDTCM (JCU.JCDTCM) +#define JCUJCDTCD (JCU.JCDTCD) +#define JCUJINTE0 (JCU.JINTE0) +#define JCUJINTS0 (JCU.JINTS0) +#define JCUJCDERR (JCU.JCDERR) +#define JCUJCRST (JCU.JCRST) +#define JCUJIFECNT (JCU.JIFECNT) +#define JCUJIFESA (JCU.JIFESA) +#define JCUJIFESOFST (JCU.JIFESOFST) +#define JCUJIFEDA (JCU.JIFEDA) +#define JCUJIFESLC (JCU.JIFESLC) +#define JCUJIFEDDC (JCU.JIFEDDC) +#define JCUJIFDCNT (JCU.JIFDCNT) +#define JCUJIFDSA (JCU.JIFDSA) +#define JCUJIFDDOFST (JCU.JIFDDOFST) +#define JCUJIFDDA (JCU.JIFDDA) +#define JCUJIFDSDC (JCU.JIFDSDC) +#define JCUJIFDDLC (JCU.JIFDDLC) +#define JCUJIFDADT (JCU.JIFDADT) +#define JCUJINTE1 (JCU.JINTE1) +#define JCUJINTS1 (JCU.JINTS1) +#define JCUJIFESVSZ (JCU.JIFESVSZ) +#define JCUJIFESHSZ (JCU.JIFESHSZ) +#define JCUJCQTBL0 (JCU.JCQTBL0) +#define JCUJCQTBL1 (JCU.JCQTBL1) +#define JCUJCQTBL2 (JCU.JCQTBL2) +#define JCUJCQTBL3 (JCU.JCQTBL3) +#define JCUJCHTBD0 (JCU.JCHTBD0) +#define JCUJCHTBA0 (JCU.JCHTBA0) +#define JCUJCHTBD1 (JCU.JCHTBD1) +#define JCUJCHTBA1 (JCU.JCHTBA1) + + +typedef struct st_jcu +{ + /* JCU */ volatile uint8_t JCMOD; /* JCMOD */ volatile uint8_t JCCMD; /* JCCMD */ volatile uint8_t dummy145[1]; /* */ @@ -70,21 +138,29 @@ struct st_jcu volatile uint32_t JIFESVSZ; /* JIFESVSZ */ volatile uint32_t JIFESHSZ; /* JIFESHSZ */ volatile uint8_t dummy148[100]; /* */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL0; /* JCQTBL0 */ volatile uint8_t dummy149[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL1; /* JCQTBL1 */ volatile uint8_t dummy150[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL2; /* JCQTBL2 */ volatile uint8_t dummy151[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL3; /* JCQTBL3 */ volatile uint8_t dummy152[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCHTBD0; /* JCHTBD0 */ volatile uint8_t dummy153[31]; /* */ @@ -93,77 +169,29 @@ struct st_jcu volatile uint8_t JCHTBD1; /* JCHTBD1 */ volatile uint8_t dummy155[31]; /* */ volatile uint8_t JCHTBA1; /* JCHTBA1 */ -}; +} r_io_jcu_t; -struct st_jcu_from_jcqtbl0 +typedef struct st_jcu_from_jcqtbl0 { + volatile uint8_t JCQTBL0; /* JCQTBL0 */ volatile uint8_t dummy1[63]; /* */ -}; +} r_io_jcu_from_jcqtbl0_t; -#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */ +/* Channel array defines of JCU (2)*/ +#ifdef DECLARE_JCU_JCQTBL0_CHANNELS +volatile struct st_jcu_from_jcqtbl0* JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + JCU_JCQTBL0_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_JCU_JCQTBL0_CHANNELS */ +/* End of channel array defines of JCU (2)*/ -/* Start of channnel array defines of JCU */ - -/* Channnel array defines of JCU_JCQTBL0 */ -/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */ -#define JCU_JCQTBL0_COUNT 4 -#define JCU_JCQTBL0_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */ -#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */ -#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */ -#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */ - -/* End of channnel array defines of JCU */ - - -#define JCUJCMOD JCU.JCMOD -#define JCUJCCMD JCU.JCCMD -#define JCUJCQTN JCU.JCQTN -#define JCUJCHTN JCU.JCHTN -#define JCUJCDRIU JCU.JCDRIU -#define JCUJCDRID JCU.JCDRID -#define JCUJCVSZU JCU.JCVSZU -#define JCUJCVSZD JCU.JCVSZD -#define JCUJCHSZU JCU.JCHSZU -#define JCUJCHSZD JCU.JCHSZD -#define JCUJCDTCU JCU.JCDTCU -#define JCUJCDTCM JCU.JCDTCM -#define JCUJCDTCD JCU.JCDTCD -#define JCUJINTE0 JCU.JINTE0 -#define JCUJINTS0 JCU.JINTS0 -#define JCUJCDERR JCU.JCDERR -#define JCUJCRST JCU.JCRST -#define JCUJIFECNT JCU.JIFECNT -#define JCUJIFESA JCU.JIFESA -#define JCUJIFESOFST JCU.JIFESOFST -#define JCUJIFEDA JCU.JIFEDA -#define JCUJIFESLC JCU.JIFESLC -#define JCUJIFEDDC JCU.JIFEDDC -#define JCUJIFDCNT JCU.JIFDCNT -#define JCUJIFDSA JCU.JIFDSA -#define JCUJIFDDOFST JCU.JIFDDOFST -#define JCUJIFDDA JCU.JIFDDA -#define JCUJIFDSDC JCU.JIFDSDC -#define JCUJIFDDLC JCU.JIFDDLC -#define JCUJIFDADT JCU.JIFDADT -#define JCUJINTE1 JCU.JINTE1 -#define JCUJINTS1 JCU.JINTS1 -#define JCUJIFESVSZ JCU.JIFESVSZ -#define JCUJIFESHSZ JCU.JIFESHSZ -#define JCUJCQTBL0 JCU.JCQTBL0 -#define JCUJCQTBL1 JCU.JCQTBL1 -#define JCUJCQTBL2 JCU.JCQTBL2 -#define JCUJCQTBL3 JCU.JCQTBL3 -#define JCUJCHTBD0 JCU.JCHTBD0 -#define JCUJCHTBA0 JCU.JCHTBA0 -#define JCUJCHTBD1 JCU.JCHTBD1 -#define JCUJCHTBA1 JCU.JCHTBA1 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h index ba6cb180bf..76604a953f 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h @@ -18,20 +18,97 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : l2c_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef L2C_IODEFINE_H #define L2C_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_l2c -{ /* L2C */ +#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */ + + +/* Start of channel array defines of L2C */ + +/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */ +/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */ +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT (8) +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */ +#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */ +#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */ +#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */ +#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */ +#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */ +#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */ +#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */ + +/* End of channel array defines of L2C */ + + +#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID) +#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE) +#define L2CREG1_CONTROL (L2C.REG1_CONTROL) +#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL) +#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL) +#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL) +#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL) +#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG) +#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG) +#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1) +#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0) +#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK) +#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS) +#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS) +#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR) +#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC) +#define L2CREG7_INV_PA (L2C.REG7_INV_PA) +#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY) +#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA) +#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX) +#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY) +#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA) +#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX) +#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY) +#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0) +#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0) +#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1) +#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1) +#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2) +#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2) +#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3) +#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3) +#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4) +#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4) +#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5) +#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5) +#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6) +#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6) +#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7) +#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7) +#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN) +#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY) +#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START) +#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END) +#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL) +#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL) +#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL) + + +typedef struct st_l2c +{ + /* L2C */ volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */ volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */ volatile uint8_t dummy8[248]; /* */ @@ -66,37 +143,53 @@ struct st_l2c volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */ volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */ volatile uint8_t dummy17[256]; /* */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */ volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */ volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */ volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */ volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */ volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */ volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */ volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint8_t dummy18[16]; /* */ volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */ @@ -110,86 +203,29 @@ struct st_l2c volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */ volatile uint8_t dummy22[28]; /* */ volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */ -}; +} r_io_l2c_t; -struct st_l2c_from_reg9_d_lockdown0 +typedef struct st_l2c_from_reg9_d_lockdown0 { + volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ -}; +} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */; -#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */ +/* Channel array defines of L2C (2)*/ +#ifdef DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS +volatile struct st_l2c_from_reg9_d_lockdown0* L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */ +/* End of channel array defines of L2C (2)*/ -/* Start of channnel array defines of L2C */ - -/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */ -/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */ -#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT 8 -#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */ -#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */ -#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */ -#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */ -#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */ -#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */ -#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */ -#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */ - -/* End of channnel array defines of L2C */ - - -#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID -#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE -#define L2CREG1_CONTROL L2C.REG1_CONTROL -#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL -#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL -#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL -#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL -#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG -#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG -#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1 -#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0 -#define L2CREG2_INT_MASK L2C.REG2_INT_MASK -#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS -#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS -#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR -#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC -#define L2CREG7_INV_PA L2C.REG7_INV_PA -#define L2CREG7_INV_WAY L2C.REG7_INV_WAY -#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA -#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX -#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY -#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA -#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX -#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY -#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0 -#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0 -#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1 -#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1 -#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2 -#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2 -#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3 -#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3 -#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4 -#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4 -#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5 -#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5 -#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6 -#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6 -#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7 -#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7 -#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN -#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY -#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START -#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END -#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL -#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL -#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h index d46e7770b3..6c0fcc0877 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h @@ -18,25 +18,101 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : lin_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef LIN_IODEFINE_H #define LIN_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_lin -{ /* LIN */ +#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */ +#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */ + + +/* Start of channel array defines of LIN */ + +/* Channel array defines of LIN */ +/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */ +#define LIN_COUNT (2) +#define LIN_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &LIN0, &LIN1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of LIN */ + + +#define LIN0RLN30LWBR (LIN0.RLN3nLWBR) +#define LIN0RLN30LBRP0 (LIN0.RLN3nLBRP0) +#define LIN0RLN30LBRP1 (LIN0.RLN3nLBRP1) +#define LIN0RLN30LSTC (LIN0.RLN3nLSTC) +#define LIN0RLN30LMD (LIN0.RLN3nLMD) +#define LIN0RLN30LBFC (LIN0.RLN3nLBFC) +#define LIN0RLN30LSC (LIN0.RLN3nLSC) +#define LIN0RLN30LWUP (LIN0.RLN3nLWUP) +#define LIN0RLN30LIE (LIN0.RLN3nLIE) +#define LIN0RLN30LEDE (LIN0.RLN3nLEDE) +#define LIN0RLN30LCUC (LIN0.RLN3nLCUC) +#define LIN0RLN30LTRC (LIN0.RLN3nLTRC) +#define LIN0RLN30LMST (LIN0.RLN3nLMST) +#define LIN0RLN30LST (LIN0.RLN3nLST) +#define LIN0RLN30LEST (LIN0.RLN3nLEST) +#define LIN0RLN30LDFC (LIN0.RLN3nLDFC) +#define LIN0RLN30LIDB (LIN0.RLN3nLIDB) +#define LIN0RLN30LCBR (LIN0.RLN3nLCBR) +#define LIN0RLN30LDBR1 (LIN0.RLN3nLDBR1) +#define LIN0RLN30LDBR2 (LIN0.RLN3nLDBR2) +#define LIN0RLN30LDBR3 (LIN0.RLN3nLDBR3) +#define LIN0RLN30LDBR4 (LIN0.RLN3nLDBR4) +#define LIN0RLN30LDBR5 (LIN0.RLN3nLDBR5) +#define LIN0RLN30LDBR6 (LIN0.RLN3nLDBR6) +#define LIN0RLN30LDBR7 (LIN0.RLN3nLDBR7) +#define LIN0RLN30LDBR8 (LIN0.RLN3nLDBR8) +#define LIN1RLN31LWBR (LIN1.RLN3nLWBR) +#define LIN1RLN31LBRP0 (LIN1.RLN3nLBRP0) +#define LIN1RLN31LBRP1 (LIN1.RLN3nLBRP1) +#define LIN1RLN31LSTC (LIN1.RLN3nLSTC) +#define LIN1RLN31LMD (LIN1.RLN3nLMD) +#define LIN1RLN31LBFC (LIN1.RLN3nLBFC) +#define LIN1RLN31LSC (LIN1.RLN3nLSC) +#define LIN1RLN31LWUP (LIN1.RLN3nLWUP) +#define LIN1RLN31LIE (LIN1.RLN3nLIE) +#define LIN1RLN31LEDE (LIN1.RLN3nLEDE) +#define LIN1RLN31LCUC (LIN1.RLN3nLCUC) +#define LIN1RLN31LTRC (LIN1.RLN3nLTRC) +#define LIN1RLN31LMST (LIN1.RLN3nLMST) +#define LIN1RLN31LST (LIN1.RLN3nLST) +#define LIN1RLN31LEST (LIN1.RLN3nLEST) +#define LIN1RLN31LDFC (LIN1.RLN3nLDFC) +#define LIN1RLN31LIDB (LIN1.RLN3nLIDB) +#define LIN1RLN31LCBR (LIN1.RLN3nLCBR) +#define LIN1RLN31LDBR1 (LIN1.RLN3nLDBR1) +#define LIN1RLN31LDBR2 (LIN1.RLN3nLDBR2) +#define LIN1RLN31LDBR3 (LIN1.RLN3nLDBR3) +#define LIN1RLN31LDBR4 (LIN1.RLN3nLDBR4) +#define LIN1RLN31LDBR5 (LIN1.RLN3nLDBR5) +#define LIN1RLN31LDBR6 (LIN1.RLN3nLDBR6) +#define LIN1RLN31LDBR7 (LIN1.RLN3nLDBR7) +#define LIN1RLN31LDBR8 (LIN1.RLN3nLDBR8) + +#define LIN_LDBn_COUNT (8) + + +typedef struct st_lin +{ + /* LIN */ volatile uint8_t dummy1[1]; /* */ volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */ - union iodefine_reg16_8_t RLN3nLBRP01; /* RLN3nLBRP01 */ - + volatile uint8_t RLN3nLBRP0; /* RLN3nLBRP0 */ + volatile uint8_t RLN3nLBRP1; /* RLN3nLBRP1 */ volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */ volatile uint8_t dummy2[3]; /* */ volatile uint8_t RLN3nLMD; /* RLN3nLMD */ @@ -54,8 +130,9 @@ struct st_lin volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */ volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */ volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */ - volatile uint8_t RLN3nLUDB0; /* RLN3nLUDB0 */ -#define LIN_LDBn_COUNT 8 + volatile uint8_t dummy4[1]; /* */ + +/* #define LIN_LDBn_COUNT (8) */ volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */ volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */ volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */ @@ -64,111 +141,21 @@ struct st_lin volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */ volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */ volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */ - volatile uint8_t RLN3nLUOER; /* RLN3nLUOER */ - volatile uint8_t RLN3nLUOR1; /* RLN3nLUOR1 */ - volatile uint8_t dummy4[2]; /* */ - union iodefine_reg16_8_t RLN3nLUTDR; /* RLN3nLUTDR */ - union iodefine_reg16_8_t RLN3nLURDR; /* RLN3nLURDR */ - union iodefine_reg16_8_t RLN3nLUWTDR; /* RLN3nLUWTDR */ - -}; +} r_io_lin_t; -#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */ -#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */ +/* Channel array defines of LIN (2)*/ +#ifdef DECLARE_LIN_CHANNELS +volatile struct st_lin* LIN[ LIN_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + LIN_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_LIN_CHANNELS */ +/* End of channel array defines of LIN (2)*/ -/* Start of channnel array defines of LIN */ - -/* Channnel array defines of LIN */ -/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */ -#define LIN_COUNT 2 -#define LIN_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &LIN0, &LIN1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of LIN */ - - -#define LIN0RLN30LWBR LIN0.RLN3nLWBR -#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16 -#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L] -#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H] -#define LIN0RLN30LSTC LIN0.RLN3nLSTC -#define LIN0RLN30LMD LIN0.RLN3nLMD -#define LIN0RLN30LBFC LIN0.RLN3nLBFC -#define LIN0RLN30LSC LIN0.RLN3nLSC -#define LIN0RLN30LWUP LIN0.RLN3nLWUP -#define LIN0RLN30LIE LIN0.RLN3nLIE -#define LIN0RLN30LEDE LIN0.RLN3nLEDE -#define LIN0RLN30LCUC LIN0.RLN3nLCUC -#define LIN0RLN30LTRC LIN0.RLN3nLTRC -#define LIN0RLN30LMST LIN0.RLN3nLMST -#define LIN0RLN30LST LIN0.RLN3nLST -#define LIN0RLN30LEST LIN0.RLN3nLEST -#define LIN0RLN30LDFC LIN0.RLN3nLDFC -#define LIN0RLN30LIDB LIN0.RLN3nLIDB -#define LIN0RLN30LCBR LIN0.RLN3nLCBR -#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0 -#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1 -#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2 -#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3 -#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4 -#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5 -#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6 -#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7 -#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8 -#define LIN0RLN30LUOER LIN0.RLN3nLUOER -#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1 -#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16 -#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L] -#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H] -#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16 -#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L] -#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H] -#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16 -#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L] -#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H] -#define LIN1RLN31LWBR LIN1.RLN3nLWBR -#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16 -#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L] -#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H] -#define LIN1RLN31LSTC LIN1.RLN3nLSTC -#define LIN1RLN31LMD LIN1.RLN3nLMD -#define LIN1RLN31LBFC LIN1.RLN3nLBFC -#define LIN1RLN31LSC LIN1.RLN3nLSC -#define LIN1RLN31LWUP LIN1.RLN3nLWUP -#define LIN1RLN31LIE LIN1.RLN3nLIE -#define LIN1RLN31LEDE LIN1.RLN3nLEDE -#define LIN1RLN31LCUC LIN1.RLN3nLCUC -#define LIN1RLN31LTRC LIN1.RLN3nLTRC -#define LIN1RLN31LMST LIN1.RLN3nLMST -#define LIN1RLN31LST LIN1.RLN3nLST -#define LIN1RLN31LEST LIN1.RLN3nLEST -#define LIN1RLN31LDFC LIN1.RLN3nLDFC -#define LIN1RLN31LIDB LIN1.RLN3nLIDB -#define LIN1RLN31LCBR LIN1.RLN3nLCBR -#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0 -#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1 -#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2 -#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3 -#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4 -#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5 -#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6 -#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7 -#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8 -#define LIN1RLN31LUOER LIN1.RLN3nLUOER -#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1 -#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16 -#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L] -#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H] -#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16 -#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L] -#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H] -#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16 -#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L] -#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H] /* <-SEC M1.10.1 */ /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h index 64d52eef01..c32caa6952 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h @@ -18,20 +18,34 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : lvds_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.01a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef LVDS_IODEFINE_H #define LVDS_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_lvds -{ /* LVDS */ +#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */ + + +#define LVDSLVDS_UPDATE (LVDS.LVDS_UPDATE) +#define LVDSLVDSFCL (LVDS.LVDSFCL) +#define LVDSLCLKSELR (LVDS.LCLKSELR) +#define LVDSLPLLSETR (LVDS.LPLLSETR) +#define LVDSLPHYACC (LVDS.LPHYACC) + + +typedef struct st_lvds +{ + /* LVDS */ volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */ volatile uint32_t LVDSFCL; /* LVDSFCL */ volatile uint8_t dummy608[24]; /* */ @@ -39,16 +53,11 @@ struct st_lvds volatile uint32_t LPLLSETR; /* LPLLSETR */ volatile uint8_t dummy609[4]; /* */ volatile uint32_t LPHYACC; /* LPHYACC */ -}; +} r_io_lvds_t; -#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */ - - -#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE -#define LVDSLVDSFCL LVDS.LVDSFCL -#define LVDSLCLKSELR LVDS.LCLKSELR -#define LVDSLPLLSETR LVDS.LPLLSETR -#define LVDSLPHYACC LVDS.LPHYACC /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h index ae97365872..d06c767089 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h @@ -18,273 +18,29 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : mlb_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef MLB_IODEFINE_H #define MLB_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ /* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_mlb -{ /* MLB */ - volatile uint32_t DCCR; /* DCCR */ - volatile uint32_t SSCR; /* SSCR */ - volatile uint32_t SDCR; /* SDCR */ - volatile uint32_t SMCR; /* SMCR */ - volatile uint8_t dummy156[12]; /* */ - volatile uint32_t VCCR; /* VCCR */ - volatile uint32_t SBCR; /* SBCR */ - volatile uint32_t ABCR; /* ABCR */ - volatile uint32_t CBCR; /* CBCR */ - volatile uint32_t IBCR; /* IBCR */ - volatile uint32_t CICR; /* CICR */ - volatile uint8_t dummy157[12]; /* */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR0; /* CECR0 */ - volatile uint32_t CSCR0; /* CSCR0 */ - volatile uint32_t CCBCR0; /* CCBCR0 */ - volatile uint32_t CNBCR0; /* CNBCR0 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR1; /* CECR1 */ - volatile uint32_t CSCR1; /* CSCR1 */ - volatile uint32_t CCBCR1; /* CCBCR1 */ - volatile uint32_t CNBCR1; /* CNBCR1 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR2; /* CECR2 */ - volatile uint32_t CSCR2; /* CSCR2 */ - volatile uint32_t CCBCR2; /* CCBCR2 */ - volatile uint32_t CNBCR2; /* CNBCR2 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR3; /* CECR3 */ - volatile uint32_t CSCR3; /* CSCR3 */ - volatile uint32_t CCBCR3; /* CCBCR3 */ - volatile uint32_t CNBCR3; /* CNBCR3 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR4; /* CECR4 */ - volatile uint32_t CSCR4; /* CSCR4 */ - volatile uint32_t CCBCR4; /* CCBCR4 */ - volatile uint32_t CNBCR4; /* CNBCR4 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR5; /* CECR5 */ - volatile uint32_t CSCR5; /* CSCR5 */ - volatile uint32_t CCBCR5; /* CCBCR5 */ - volatile uint32_t CNBCR5; /* CNBCR5 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR6; /* CECR6 */ - volatile uint32_t CSCR6; /* CSCR6 */ - volatile uint32_t CCBCR6; /* CCBCR6 */ - volatile uint32_t CNBCR6; /* CNBCR6 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR7; /* CECR7 */ - volatile uint32_t CSCR7; /* CSCR7 */ - volatile uint32_t CCBCR7; /* CCBCR7 */ - volatile uint32_t CNBCR7; /* CNBCR7 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR8; /* CECR8 */ - volatile uint32_t CSCR8; /* CSCR8 */ - volatile uint32_t CCBCR8; /* CCBCR8 */ - volatile uint32_t CNBCR8; /* CNBCR8 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR9; /* CECR9 */ - volatile uint32_t CSCR9; /* CSCR9 */ - volatile uint32_t CCBCR9; /* CCBCR9 */ - volatile uint32_t CNBCR9; /* CNBCR9 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR10; /* CECR10 */ - volatile uint32_t CSCR10; /* CSCR10 */ - volatile uint32_t CCBCR10; /* CCBCR10 */ - volatile uint32_t CNBCR10; /* CNBCR10 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR11; /* CECR11 */ - volatile uint32_t CSCR11; /* CSCR11 */ - volatile uint32_t CCBCR11; /* CCBCR11 */ - volatile uint32_t CNBCR11; /* CNBCR11 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR12; /* CECR12 */ - volatile uint32_t CSCR12; /* CSCR12 */ - volatile uint32_t CCBCR12; /* CCBCR12 */ - volatile uint32_t CNBCR12; /* CNBCR12 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR13; /* CECR13 */ - volatile uint32_t CSCR13; /* CSCR13 */ - volatile uint32_t CCBCR13; /* CCBCR13 */ - volatile uint32_t CNBCR13; /* CNBCR13 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR14; /* CECR14 */ - volatile uint32_t CSCR14; /* CSCR14 */ - volatile uint32_t CCBCR14; /* CCBCR14 */ - volatile uint32_t CNBCR14; /* CNBCR14 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR15; /* CECR15 */ - volatile uint32_t CSCR15; /* CSCR15 */ - volatile uint32_t CCBCR15; /* CCBCR15 */ - volatile uint32_t CNBCR15; /* CNBCR15 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR16; /* CECR16 */ - volatile uint32_t CSCR16; /* CSCR16 */ - volatile uint32_t CCBCR16; /* CCBCR16 */ - volatile uint32_t CNBCR16; /* CNBCR16 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR17; /* CECR17 */ - volatile uint32_t CSCR17; /* CSCR17 */ - volatile uint32_t CCBCR17; /* CCBCR17 */ - volatile uint32_t CNBCR17; /* CNBCR17 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR18; /* CECR18 */ - volatile uint32_t CSCR18; /* CSCR18 */ - volatile uint32_t CCBCR18; /* CCBCR18 */ - volatile uint32_t CNBCR18; /* CNBCR18 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR19; /* CECR19 */ - volatile uint32_t CSCR19; /* CSCR19 */ - volatile uint32_t CCBCR19; /* CCBCR19 */ - volatile uint32_t CNBCR19; /* CNBCR19 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR20; /* CECR20 */ - volatile uint32_t CSCR20; /* CSCR20 */ - volatile uint32_t CCBCR20; /* CCBCR20 */ - volatile uint32_t CNBCR20; /* CNBCR20 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR21; /* CECR21 */ - volatile uint32_t CSCR21; /* CSCR21 */ - volatile uint32_t CCBCR21; /* CCBCR21 */ - volatile uint32_t CNBCR21; /* CNBCR21 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR22; /* CECR22 */ - volatile uint32_t CSCR22; /* CSCR22 */ - volatile uint32_t CCBCR22; /* CCBCR22 */ - volatile uint32_t CNBCR22; /* CNBCR22 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR23; /* CECR23 */ - volatile uint32_t CSCR23; /* CSCR23 */ - volatile uint32_t CCBCR23; /* CCBCR23 */ - volatile uint32_t CNBCR23; /* CNBCR23 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR24; /* CECR24 */ - volatile uint32_t CSCR24; /* CSCR24 */ - volatile uint32_t CCBCR24; /* CCBCR24 */ - volatile uint32_t CNBCR24; /* CNBCR24 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR25; /* CECR25 */ - volatile uint32_t CSCR25; /* CSCR25 */ - volatile uint32_t CCBCR25; /* CCBCR25 */ - volatile uint32_t CNBCR25; /* CNBCR25 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR26; /* CECR26 */ - volatile uint32_t CSCR26; /* CSCR26 */ - volatile uint32_t CCBCR26; /* CCBCR26 */ - volatile uint32_t CNBCR26; /* CNBCR26 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR27; /* CECR27 */ - volatile uint32_t CSCR27; /* CSCR27 */ - volatile uint32_t CCBCR27; /* CCBCR27 */ - volatile uint32_t CNBCR27; /* CNBCR27 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR28; /* CECR28 */ - volatile uint32_t CSCR28; /* CSCR28 */ - volatile uint32_t CCBCR28; /* CCBCR28 */ - volatile uint32_t CNBCR28; /* CNBCR28 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR29; /* CECR29 */ - volatile uint32_t CSCR29; /* CSCR29 */ - volatile uint32_t CCBCR29; /* CCBCR29 */ - volatile uint32_t CNBCR29; /* CNBCR29 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR30; /* CECR30 */ - volatile uint32_t CSCR30; /* CSCR30 */ - volatile uint32_t CCBCR30; /* CCBCR30 */ - volatile uint32_t CNBCR30; /* CNBCR30 */ -/* end of struct st_mlb_from_cecr0 */ - volatile uint8_t dummy158[80]; /* */ -#define MLB_LCBCR0_COUNT 31 - volatile uint32_t LCBCR0; /* LCBCR0 */ - volatile uint32_t LCBCR1; /* LCBCR1 */ - volatile uint32_t LCBCR2; /* LCBCR2 */ - volatile uint32_t LCBCR3; /* LCBCR3 */ - volatile uint32_t LCBCR4; /* LCBCR4 */ - volatile uint32_t LCBCR5; /* LCBCR5 */ - volatile uint32_t LCBCR6; /* LCBCR6 */ - volatile uint32_t LCBCR7; /* LCBCR7 */ - volatile uint32_t LCBCR8; /* LCBCR8 */ - volatile uint32_t LCBCR9; /* LCBCR9 */ - volatile uint32_t LCBCR10; /* LCBCR10 */ - volatile uint32_t LCBCR11; /* LCBCR11 */ - volatile uint32_t LCBCR12; /* LCBCR12 */ - volatile uint32_t LCBCR13; /* LCBCR13 */ - volatile uint32_t LCBCR14; /* LCBCR14 */ - volatile uint32_t LCBCR15; /* LCBCR15 */ - volatile uint32_t LCBCR16; /* LCBCR16 */ - volatile uint32_t LCBCR17; /* LCBCR17 */ - volatile uint32_t LCBCR18; /* LCBCR18 */ - volatile uint32_t LCBCR19; /* LCBCR19 */ - volatile uint32_t LCBCR20; /* LCBCR20 */ - volatile uint32_t LCBCR21; /* LCBCR21 */ - volatile uint32_t LCBCR22; /* LCBCR22 */ - volatile uint32_t LCBCR23; /* LCBCR23 */ - volatile uint32_t LCBCR24; /* LCBCR24 */ - volatile uint32_t LCBCR25; /* LCBCR25 */ - volatile uint32_t LCBCR26; /* LCBCR26 */ - volatile uint32_t LCBCR27; /* LCBCR27 */ - volatile uint32_t LCBCR28; /* LCBCR28 */ - volatile uint32_t LCBCR29; /* LCBCR29 */ - volatile uint32_t LCBCR30; /* LCBCR30 */ -}; - - -struct st_mlb_from_cecr0 -{ - volatile uint32_t CECR0; /* CECR0 */ - volatile uint32_t CSCR0; /* CSCR0 */ - volatile uint32_t CCBCR0; /* CCBCR0 */ - volatile uint32_t CNBCR0; /* CNBCR0 */ -}; - - #define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */ -/* Start of channnel array defines of MLB */ +/* Start of channel array defines of MLB */ -/* Channnel array defines of MLB_FROM_CECR0_ARRAY */ +/* Channel array defines of MLB_FROM_CECR0_ARRAY */ /*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */ -#define MLB_FROM_CECR0_ARRAY_COUNT 31 +#define MLB_FROM_CECR0_ARRAY_COUNT (31) #define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \ @@ -324,175 +80,500 @@ struct st_mlb_from_cecr0 #define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */ #define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */ -/* End of channnel array defines of MLB */ +/* End of channel array defines of MLB */ + + +#define MLBDCCR (MLB.DCCR) +#define MLBSSCR (MLB.SSCR) +#define MLBSDCR (MLB.SDCR) +#define MLBSMCR (MLB.SMCR) +#define MLBVCCR (MLB.VCCR) +#define MLBSBCR (MLB.SBCR) +#define MLBABCR (MLB.ABCR) +#define MLBCBCR (MLB.CBCR) +#define MLBIBCR (MLB.IBCR) +#define MLBCICR (MLB.CICR) +#define MLBCECR0 (MLB.CECR0) +#define MLBCSCR0 (MLB.CSCR0) +#define MLBCCBCR0 (MLB.CCBCR0) +#define MLBCNBCR0 (MLB.CNBCR0) +#define MLBCECR1 (MLB.CECR1) +#define MLBCSCR1 (MLB.CSCR1) +#define MLBCCBCR1 (MLB.CCBCR1) +#define MLBCNBCR1 (MLB.CNBCR1) +#define MLBCECR2 (MLB.CECR2) +#define MLBCSCR2 (MLB.CSCR2) +#define MLBCCBCR2 (MLB.CCBCR2) +#define MLBCNBCR2 (MLB.CNBCR2) +#define MLBCECR3 (MLB.CECR3) +#define MLBCSCR3 (MLB.CSCR3) +#define MLBCCBCR3 (MLB.CCBCR3) +#define MLBCNBCR3 (MLB.CNBCR3) +#define MLBCECR4 (MLB.CECR4) +#define MLBCSCR4 (MLB.CSCR4) +#define MLBCCBCR4 (MLB.CCBCR4) +#define MLBCNBCR4 (MLB.CNBCR4) +#define MLBCECR5 (MLB.CECR5) +#define MLBCSCR5 (MLB.CSCR5) +#define MLBCCBCR5 (MLB.CCBCR5) +#define MLBCNBCR5 (MLB.CNBCR5) +#define MLBCECR6 (MLB.CECR6) +#define MLBCSCR6 (MLB.CSCR6) +#define MLBCCBCR6 (MLB.CCBCR6) +#define MLBCNBCR6 (MLB.CNBCR6) +#define MLBCECR7 (MLB.CECR7) +#define MLBCSCR7 (MLB.CSCR7) +#define MLBCCBCR7 (MLB.CCBCR7) +#define MLBCNBCR7 (MLB.CNBCR7) +#define MLBCECR8 (MLB.CECR8) +#define MLBCSCR8 (MLB.CSCR8) +#define MLBCCBCR8 (MLB.CCBCR8) +#define MLBCNBCR8 (MLB.CNBCR8) +#define MLBCECR9 (MLB.CECR9) +#define MLBCSCR9 (MLB.CSCR9) +#define MLBCCBCR9 (MLB.CCBCR9) +#define MLBCNBCR9 (MLB.CNBCR9) +#define MLBCECR10 (MLB.CECR10) +#define MLBCSCR10 (MLB.CSCR10) +#define MLBCCBCR10 (MLB.CCBCR10) +#define MLBCNBCR10 (MLB.CNBCR10) +#define MLBCECR11 (MLB.CECR11) +#define MLBCSCR11 (MLB.CSCR11) +#define MLBCCBCR11 (MLB.CCBCR11) +#define MLBCNBCR11 (MLB.CNBCR11) +#define MLBCECR12 (MLB.CECR12) +#define MLBCSCR12 (MLB.CSCR12) +#define MLBCCBCR12 (MLB.CCBCR12) +#define MLBCNBCR12 (MLB.CNBCR12) +#define MLBCECR13 (MLB.CECR13) +#define MLBCSCR13 (MLB.CSCR13) +#define MLBCCBCR13 (MLB.CCBCR13) +#define MLBCNBCR13 (MLB.CNBCR13) +#define MLBCECR14 (MLB.CECR14) +#define MLBCSCR14 (MLB.CSCR14) +#define MLBCCBCR14 (MLB.CCBCR14) +#define MLBCNBCR14 (MLB.CNBCR14) +#define MLBCECR15 (MLB.CECR15) +#define MLBCSCR15 (MLB.CSCR15) +#define MLBCCBCR15 (MLB.CCBCR15) +#define MLBCNBCR15 (MLB.CNBCR15) +#define MLBCECR16 (MLB.CECR16) +#define MLBCSCR16 (MLB.CSCR16) +#define MLBCCBCR16 (MLB.CCBCR16) +#define MLBCNBCR16 (MLB.CNBCR16) +#define MLBCECR17 (MLB.CECR17) +#define MLBCSCR17 (MLB.CSCR17) +#define MLBCCBCR17 (MLB.CCBCR17) +#define MLBCNBCR17 (MLB.CNBCR17) +#define MLBCECR18 (MLB.CECR18) +#define MLBCSCR18 (MLB.CSCR18) +#define MLBCCBCR18 (MLB.CCBCR18) +#define MLBCNBCR18 (MLB.CNBCR18) +#define MLBCECR19 (MLB.CECR19) +#define MLBCSCR19 (MLB.CSCR19) +#define MLBCCBCR19 (MLB.CCBCR19) +#define MLBCNBCR19 (MLB.CNBCR19) +#define MLBCECR20 (MLB.CECR20) +#define MLBCSCR20 (MLB.CSCR20) +#define MLBCCBCR20 (MLB.CCBCR20) +#define MLBCNBCR20 (MLB.CNBCR20) +#define MLBCECR21 (MLB.CECR21) +#define MLBCSCR21 (MLB.CSCR21) +#define MLBCCBCR21 (MLB.CCBCR21) +#define MLBCNBCR21 (MLB.CNBCR21) +#define MLBCECR22 (MLB.CECR22) +#define MLBCSCR22 (MLB.CSCR22) +#define MLBCCBCR22 (MLB.CCBCR22) +#define MLBCNBCR22 (MLB.CNBCR22) +#define MLBCECR23 (MLB.CECR23) +#define MLBCSCR23 (MLB.CSCR23) +#define MLBCCBCR23 (MLB.CCBCR23) +#define MLBCNBCR23 (MLB.CNBCR23) +#define MLBCECR24 (MLB.CECR24) +#define MLBCSCR24 (MLB.CSCR24) +#define MLBCCBCR24 (MLB.CCBCR24) +#define MLBCNBCR24 (MLB.CNBCR24) +#define MLBCECR25 (MLB.CECR25) +#define MLBCSCR25 (MLB.CSCR25) +#define MLBCCBCR25 (MLB.CCBCR25) +#define MLBCNBCR25 (MLB.CNBCR25) +#define MLBCECR26 (MLB.CECR26) +#define MLBCSCR26 (MLB.CSCR26) +#define MLBCCBCR26 (MLB.CCBCR26) +#define MLBCNBCR26 (MLB.CNBCR26) +#define MLBCECR27 (MLB.CECR27) +#define MLBCSCR27 (MLB.CSCR27) +#define MLBCCBCR27 (MLB.CCBCR27) +#define MLBCNBCR27 (MLB.CNBCR27) +#define MLBCECR28 (MLB.CECR28) +#define MLBCSCR28 (MLB.CSCR28) +#define MLBCCBCR28 (MLB.CCBCR28) +#define MLBCNBCR28 (MLB.CNBCR28) +#define MLBCECR29 (MLB.CECR29) +#define MLBCSCR29 (MLB.CSCR29) +#define MLBCCBCR29 (MLB.CCBCR29) +#define MLBCNBCR29 (MLB.CNBCR29) +#define MLBCECR30 (MLB.CECR30) +#define MLBCSCR30 (MLB.CSCR30) +#define MLBCCBCR30 (MLB.CCBCR30) +#define MLBCNBCR30 (MLB.CNBCR30) +#define MLBLCBCR0 (MLB.LCBCR0) +#define MLBLCBCR1 (MLB.LCBCR1) +#define MLBLCBCR2 (MLB.LCBCR2) +#define MLBLCBCR3 (MLB.LCBCR3) +#define MLBLCBCR4 (MLB.LCBCR4) +#define MLBLCBCR5 (MLB.LCBCR5) +#define MLBLCBCR6 (MLB.LCBCR6) +#define MLBLCBCR7 (MLB.LCBCR7) +#define MLBLCBCR8 (MLB.LCBCR8) +#define MLBLCBCR9 (MLB.LCBCR9) +#define MLBLCBCR10 (MLB.LCBCR10) +#define MLBLCBCR11 (MLB.LCBCR11) +#define MLBLCBCR12 (MLB.LCBCR12) +#define MLBLCBCR13 (MLB.LCBCR13) +#define MLBLCBCR14 (MLB.LCBCR14) +#define MLBLCBCR15 (MLB.LCBCR15) +#define MLBLCBCR16 (MLB.LCBCR16) +#define MLBLCBCR17 (MLB.LCBCR17) +#define MLBLCBCR18 (MLB.LCBCR18) +#define MLBLCBCR19 (MLB.LCBCR19) +#define MLBLCBCR20 (MLB.LCBCR20) +#define MLBLCBCR21 (MLB.LCBCR21) +#define MLBLCBCR22 (MLB.LCBCR22) +#define MLBLCBCR23 (MLB.LCBCR23) +#define MLBLCBCR24 (MLB.LCBCR24) +#define MLBLCBCR25 (MLB.LCBCR25) +#define MLBLCBCR26 (MLB.LCBCR26) +#define MLBLCBCR27 (MLB.LCBCR27) +#define MLBLCBCR28 (MLB.LCBCR28) +#define MLBLCBCR29 (MLB.LCBCR29) +#define MLBLCBCR30 (MLB.LCBCR30) + +#define MLB_LCBCR0_COUNT (31) + + +typedef struct st_mlb +{ + /* MLB */ + volatile uint32_t DCCR; /* DCCR */ + volatile uint32_t SSCR; /* SSCR */ + volatile uint32_t SDCR; /* SDCR */ + volatile uint32_t SMCR; /* SMCR */ + volatile uint8_t dummy156[12]; /* */ + volatile uint32_t VCCR; /* VCCR */ + volatile uint32_t SBCR; /* SBCR */ + volatile uint32_t ABCR; /* ABCR */ + volatile uint32_t CBCR; /* CBCR */ + volatile uint32_t IBCR; /* IBCR */ + volatile uint32_t CICR; /* CICR */ + volatile uint8_t dummy157[12]; /* */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR0; /* CECR0 */ + volatile uint32_t CSCR0; /* CSCR0 */ + volatile uint32_t CCBCR0; /* CCBCR0 */ + volatile uint32_t CNBCR0; /* CNBCR0 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR1; /* CECR1 */ + volatile uint32_t CSCR1; /* CSCR1 */ + volatile uint32_t CCBCR1; /* CCBCR1 */ + volatile uint32_t CNBCR1; /* CNBCR1 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR2; /* CECR2 */ + volatile uint32_t CSCR2; /* CSCR2 */ + volatile uint32_t CCBCR2; /* CCBCR2 */ + volatile uint32_t CNBCR2; /* CNBCR2 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR3; /* CECR3 */ + volatile uint32_t CSCR3; /* CSCR3 */ + volatile uint32_t CCBCR3; /* CCBCR3 */ + volatile uint32_t CNBCR3; /* CNBCR3 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR4; /* CECR4 */ + volatile uint32_t CSCR4; /* CSCR4 */ + volatile uint32_t CCBCR4; /* CCBCR4 */ + volatile uint32_t CNBCR4; /* CNBCR4 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR5; /* CECR5 */ + volatile uint32_t CSCR5; /* CSCR5 */ + volatile uint32_t CCBCR5; /* CCBCR5 */ + volatile uint32_t CNBCR5; /* CNBCR5 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR6; /* CECR6 */ + volatile uint32_t CSCR6; /* CSCR6 */ + volatile uint32_t CCBCR6; /* CCBCR6 */ + volatile uint32_t CNBCR6; /* CNBCR6 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR7; /* CECR7 */ + volatile uint32_t CSCR7; /* CSCR7 */ + volatile uint32_t CCBCR7; /* CCBCR7 */ + volatile uint32_t CNBCR7; /* CNBCR7 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR8; /* CECR8 */ + volatile uint32_t CSCR8; /* CSCR8 */ + volatile uint32_t CCBCR8; /* CCBCR8 */ + volatile uint32_t CNBCR8; /* CNBCR8 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR9; /* CECR9 */ + volatile uint32_t CSCR9; /* CSCR9 */ + volatile uint32_t CCBCR9; /* CCBCR9 */ + volatile uint32_t CNBCR9; /* CNBCR9 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR10; /* CECR10 */ + volatile uint32_t CSCR10; /* CSCR10 */ + volatile uint32_t CCBCR10; /* CCBCR10 */ + volatile uint32_t CNBCR10; /* CNBCR10 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR11; /* CECR11 */ + volatile uint32_t CSCR11; /* CSCR11 */ + volatile uint32_t CCBCR11; /* CCBCR11 */ + volatile uint32_t CNBCR11; /* CNBCR11 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR12; /* CECR12 */ + volatile uint32_t CSCR12; /* CSCR12 */ + volatile uint32_t CCBCR12; /* CCBCR12 */ + volatile uint32_t CNBCR12; /* CNBCR12 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR13; /* CECR13 */ + volatile uint32_t CSCR13; /* CSCR13 */ + volatile uint32_t CCBCR13; /* CCBCR13 */ + volatile uint32_t CNBCR13; /* CNBCR13 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR14; /* CECR14 */ + volatile uint32_t CSCR14; /* CSCR14 */ + volatile uint32_t CCBCR14; /* CCBCR14 */ + volatile uint32_t CNBCR14; /* CNBCR14 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR15; /* CECR15 */ + volatile uint32_t CSCR15; /* CSCR15 */ + volatile uint32_t CCBCR15; /* CCBCR15 */ + volatile uint32_t CNBCR15; /* CNBCR15 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR16; /* CECR16 */ + volatile uint32_t CSCR16; /* CSCR16 */ + volatile uint32_t CCBCR16; /* CCBCR16 */ + volatile uint32_t CNBCR16; /* CNBCR16 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR17; /* CECR17 */ + volatile uint32_t CSCR17; /* CSCR17 */ + volatile uint32_t CCBCR17; /* CCBCR17 */ + volatile uint32_t CNBCR17; /* CNBCR17 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR18; /* CECR18 */ + volatile uint32_t CSCR18; /* CSCR18 */ + volatile uint32_t CCBCR18; /* CCBCR18 */ + volatile uint32_t CNBCR18; /* CNBCR18 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR19; /* CECR19 */ + volatile uint32_t CSCR19; /* CSCR19 */ + volatile uint32_t CCBCR19; /* CCBCR19 */ + volatile uint32_t CNBCR19; /* CNBCR19 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR20; /* CECR20 */ + volatile uint32_t CSCR20; /* CSCR20 */ + volatile uint32_t CCBCR20; /* CCBCR20 */ + volatile uint32_t CNBCR20; /* CNBCR20 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR21; /* CECR21 */ + volatile uint32_t CSCR21; /* CSCR21 */ + volatile uint32_t CCBCR21; /* CCBCR21 */ + volatile uint32_t CNBCR21; /* CNBCR21 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR22; /* CECR22 */ + volatile uint32_t CSCR22; /* CSCR22 */ + volatile uint32_t CCBCR22; /* CCBCR22 */ + volatile uint32_t CNBCR22; /* CNBCR22 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR23; /* CECR23 */ + volatile uint32_t CSCR23; /* CSCR23 */ + volatile uint32_t CCBCR23; /* CCBCR23 */ + volatile uint32_t CNBCR23; /* CNBCR23 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR24; /* CECR24 */ + volatile uint32_t CSCR24; /* CSCR24 */ + volatile uint32_t CCBCR24; /* CCBCR24 */ + volatile uint32_t CNBCR24; /* CNBCR24 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR25; /* CECR25 */ + volatile uint32_t CSCR25; /* CSCR25 */ + volatile uint32_t CCBCR25; /* CCBCR25 */ + volatile uint32_t CNBCR25; /* CNBCR25 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR26; /* CECR26 */ + volatile uint32_t CSCR26; /* CSCR26 */ + volatile uint32_t CCBCR26; /* CCBCR26 */ + volatile uint32_t CNBCR26; /* CNBCR26 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR27; /* CECR27 */ + volatile uint32_t CSCR27; /* CSCR27 */ + volatile uint32_t CCBCR27; /* CCBCR27 */ + volatile uint32_t CNBCR27; /* CNBCR27 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR28; /* CECR28 */ + volatile uint32_t CSCR28; /* CSCR28 */ + volatile uint32_t CCBCR28; /* CCBCR28 */ + volatile uint32_t CNBCR28; /* CNBCR28 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR29; /* CECR29 */ + volatile uint32_t CSCR29; /* CSCR29 */ + volatile uint32_t CCBCR29; /* CCBCR29 */ + volatile uint32_t CNBCR29; /* CNBCR29 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR30; /* CECR30 */ + volatile uint32_t CSCR30; /* CSCR30 */ + volatile uint32_t CCBCR30; /* CCBCR30 */ + volatile uint32_t CNBCR30; /* CNBCR30 */ + +/* end of struct st_mlb_from_cecr0 */ + volatile uint8_t dummy158[80]; /* */ + +/* #define MLB_LCBCR0_COUNT (31) */ + volatile uint32_t LCBCR0; /* LCBCR0 */ + volatile uint32_t LCBCR1; /* LCBCR1 */ + volatile uint32_t LCBCR2; /* LCBCR2 */ + volatile uint32_t LCBCR3; /* LCBCR3 */ + volatile uint32_t LCBCR4; /* LCBCR4 */ + volatile uint32_t LCBCR5; /* LCBCR5 */ + volatile uint32_t LCBCR6; /* LCBCR6 */ + volatile uint32_t LCBCR7; /* LCBCR7 */ + volatile uint32_t LCBCR8; /* LCBCR8 */ + volatile uint32_t LCBCR9; /* LCBCR9 */ + volatile uint32_t LCBCR10; /* LCBCR10 */ + volatile uint32_t LCBCR11; /* LCBCR11 */ + volatile uint32_t LCBCR12; /* LCBCR12 */ + volatile uint32_t LCBCR13; /* LCBCR13 */ + volatile uint32_t LCBCR14; /* LCBCR14 */ + volatile uint32_t LCBCR15; /* LCBCR15 */ + volatile uint32_t LCBCR16; /* LCBCR16 */ + volatile uint32_t LCBCR17; /* LCBCR17 */ + volatile uint32_t LCBCR18; /* LCBCR18 */ + volatile uint32_t LCBCR19; /* LCBCR19 */ + volatile uint32_t LCBCR20; /* LCBCR20 */ + volatile uint32_t LCBCR21; /* LCBCR21 */ + volatile uint32_t LCBCR22; /* LCBCR22 */ + volatile uint32_t LCBCR23; /* LCBCR23 */ + volatile uint32_t LCBCR24; /* LCBCR24 */ + volatile uint32_t LCBCR25; /* LCBCR25 */ + volatile uint32_t LCBCR26; /* LCBCR26 */ + volatile uint32_t LCBCR27; /* LCBCR27 */ + volatile uint32_t LCBCR28; /* LCBCR28 */ + volatile uint32_t LCBCR29; /* LCBCR29 */ + volatile uint32_t LCBCR30; /* LCBCR30 */ +} r_io_mlb_t; + + +typedef struct st_mlb_from_cecr0 +{ + + volatile uint32_t CECR0; /* CECR0 */ + volatile uint32_t CSCR0; /* CSCR0 */ + volatile uint32_t CCBCR0; /* CCBCR0 */ + volatile uint32_t CNBCR0; /* CNBCR0 */ +} r_io_mlb_from_cecr0_t; + + +/* Channel array defines of MLB (2)*/ +#ifdef DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS +volatile struct st_mlb_from_cecr0* MLB_FROM_CECR0_ARRAY[ MLB_FROM_CECR0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + MLB_FROM_CECR0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS */ +/* End of channel array defines of MLB (2)*/ -#define MLBDCCR MLB.DCCR -#define MLBSSCR MLB.SSCR -#define MLBSDCR MLB.SDCR -#define MLBSMCR MLB.SMCR -#define MLBVCCR MLB.VCCR -#define MLBSBCR MLB.SBCR -#define MLBABCR MLB.ABCR -#define MLBCBCR MLB.CBCR -#define MLBIBCR MLB.IBCR -#define MLBCICR MLB.CICR -#define MLBCECR0 MLB.CECR0 -#define MLBCSCR0 MLB.CSCR0 -#define MLBCCBCR0 MLB.CCBCR0 -#define MLBCNBCR0 MLB.CNBCR0 -#define MLBCECR1 MLB.CECR1 -#define MLBCSCR1 MLB.CSCR1 -#define MLBCCBCR1 MLB.CCBCR1 -#define MLBCNBCR1 MLB.CNBCR1 -#define MLBCECR2 MLB.CECR2 -#define MLBCSCR2 MLB.CSCR2 -#define MLBCCBCR2 MLB.CCBCR2 -#define MLBCNBCR2 MLB.CNBCR2 -#define MLBCECR3 MLB.CECR3 -#define MLBCSCR3 MLB.CSCR3 -#define MLBCCBCR3 MLB.CCBCR3 -#define MLBCNBCR3 MLB.CNBCR3 -#define MLBCECR4 MLB.CECR4 -#define MLBCSCR4 MLB.CSCR4 -#define MLBCCBCR4 MLB.CCBCR4 -#define MLBCNBCR4 MLB.CNBCR4 -#define MLBCECR5 MLB.CECR5 -#define MLBCSCR5 MLB.CSCR5 -#define MLBCCBCR5 MLB.CCBCR5 -#define MLBCNBCR5 MLB.CNBCR5 -#define MLBCECR6 MLB.CECR6 -#define MLBCSCR6 MLB.CSCR6 -#define MLBCCBCR6 MLB.CCBCR6 -#define MLBCNBCR6 MLB.CNBCR6 -#define MLBCECR7 MLB.CECR7 -#define MLBCSCR7 MLB.CSCR7 -#define MLBCCBCR7 MLB.CCBCR7 -#define MLBCNBCR7 MLB.CNBCR7 -#define MLBCECR8 MLB.CECR8 -#define MLBCSCR8 MLB.CSCR8 -#define MLBCCBCR8 MLB.CCBCR8 -#define MLBCNBCR8 MLB.CNBCR8 -#define MLBCECR9 MLB.CECR9 -#define MLBCSCR9 MLB.CSCR9 -#define MLBCCBCR9 MLB.CCBCR9 -#define MLBCNBCR9 MLB.CNBCR9 -#define MLBCECR10 MLB.CECR10 -#define MLBCSCR10 MLB.CSCR10 -#define MLBCCBCR10 MLB.CCBCR10 -#define MLBCNBCR10 MLB.CNBCR10 -#define MLBCECR11 MLB.CECR11 -#define MLBCSCR11 MLB.CSCR11 -#define MLBCCBCR11 MLB.CCBCR11 -#define MLBCNBCR11 MLB.CNBCR11 -#define MLBCECR12 MLB.CECR12 -#define MLBCSCR12 MLB.CSCR12 -#define MLBCCBCR12 MLB.CCBCR12 -#define MLBCNBCR12 MLB.CNBCR12 -#define MLBCECR13 MLB.CECR13 -#define MLBCSCR13 MLB.CSCR13 -#define MLBCCBCR13 MLB.CCBCR13 -#define MLBCNBCR13 MLB.CNBCR13 -#define MLBCECR14 MLB.CECR14 -#define MLBCSCR14 MLB.CSCR14 -#define MLBCCBCR14 MLB.CCBCR14 -#define MLBCNBCR14 MLB.CNBCR14 -#define MLBCECR15 MLB.CECR15 -#define MLBCSCR15 MLB.CSCR15 -#define MLBCCBCR15 MLB.CCBCR15 -#define MLBCNBCR15 MLB.CNBCR15 -#define MLBCECR16 MLB.CECR16 -#define MLBCSCR16 MLB.CSCR16 -#define MLBCCBCR16 MLB.CCBCR16 -#define MLBCNBCR16 MLB.CNBCR16 -#define MLBCECR17 MLB.CECR17 -#define MLBCSCR17 MLB.CSCR17 -#define MLBCCBCR17 MLB.CCBCR17 -#define MLBCNBCR17 MLB.CNBCR17 -#define MLBCECR18 MLB.CECR18 -#define MLBCSCR18 MLB.CSCR18 -#define MLBCCBCR18 MLB.CCBCR18 -#define MLBCNBCR18 MLB.CNBCR18 -#define MLBCECR19 MLB.CECR19 -#define MLBCSCR19 MLB.CSCR19 -#define MLBCCBCR19 MLB.CCBCR19 -#define MLBCNBCR19 MLB.CNBCR19 -#define MLBCECR20 MLB.CECR20 -#define MLBCSCR20 MLB.CSCR20 -#define MLBCCBCR20 MLB.CCBCR20 -#define MLBCNBCR20 MLB.CNBCR20 -#define MLBCECR21 MLB.CECR21 -#define MLBCSCR21 MLB.CSCR21 -#define MLBCCBCR21 MLB.CCBCR21 -#define MLBCNBCR21 MLB.CNBCR21 -#define MLBCECR22 MLB.CECR22 -#define MLBCSCR22 MLB.CSCR22 -#define MLBCCBCR22 MLB.CCBCR22 -#define MLBCNBCR22 MLB.CNBCR22 -#define MLBCECR23 MLB.CECR23 -#define MLBCSCR23 MLB.CSCR23 -#define MLBCCBCR23 MLB.CCBCR23 -#define MLBCNBCR23 MLB.CNBCR23 -#define MLBCECR24 MLB.CECR24 -#define MLBCSCR24 MLB.CSCR24 -#define MLBCCBCR24 MLB.CCBCR24 -#define MLBCNBCR24 MLB.CNBCR24 -#define MLBCECR25 MLB.CECR25 -#define MLBCSCR25 MLB.CSCR25 -#define MLBCCBCR25 MLB.CCBCR25 -#define MLBCNBCR25 MLB.CNBCR25 -#define MLBCECR26 MLB.CECR26 -#define MLBCSCR26 MLB.CSCR26 -#define MLBCCBCR26 MLB.CCBCR26 -#define MLBCNBCR26 MLB.CNBCR26 -#define MLBCECR27 MLB.CECR27 -#define MLBCSCR27 MLB.CSCR27 -#define MLBCCBCR27 MLB.CCBCR27 -#define MLBCNBCR27 MLB.CNBCR27 -#define MLBCECR28 MLB.CECR28 -#define MLBCSCR28 MLB.CSCR28 -#define MLBCCBCR28 MLB.CCBCR28 -#define MLBCNBCR28 MLB.CNBCR28 -#define MLBCECR29 MLB.CECR29 -#define MLBCSCR29 MLB.CSCR29 -#define MLBCCBCR29 MLB.CCBCR29 -#define MLBCNBCR29 MLB.CNBCR29 -#define MLBCECR30 MLB.CECR30 -#define MLBCSCR30 MLB.CSCR30 -#define MLBCCBCR30 MLB.CCBCR30 -#define MLBCNBCR30 MLB.CNBCR30 -#define MLBLCBCR0 MLB.LCBCR0 -#define MLBLCBCR1 MLB.LCBCR1 -#define MLBLCBCR2 MLB.LCBCR2 -#define MLBLCBCR3 MLB.LCBCR3 -#define MLBLCBCR4 MLB.LCBCR4 -#define MLBLCBCR5 MLB.LCBCR5 -#define MLBLCBCR6 MLB.LCBCR6 -#define MLBLCBCR7 MLB.LCBCR7 -#define MLBLCBCR8 MLB.LCBCR8 -#define MLBLCBCR9 MLB.LCBCR9 -#define MLBLCBCR10 MLB.LCBCR10 -#define MLBLCBCR11 MLB.LCBCR11 -#define MLBLCBCR12 MLB.LCBCR12 -#define MLBLCBCR13 MLB.LCBCR13 -#define MLBLCBCR14 MLB.LCBCR14 -#define MLBLCBCR15 MLB.LCBCR15 -#define MLBLCBCR16 MLB.LCBCR16 -#define MLBLCBCR17 MLB.LCBCR17 -#define MLBLCBCR18 MLB.LCBCR18 -#define MLBLCBCR19 MLB.LCBCR19 -#define MLBLCBCR20 MLB.LCBCR20 -#define MLBLCBCR21 MLB.LCBCR21 -#define MLBLCBCR22 MLB.LCBCR22 -#define MLBLCBCR23 MLB.LCBCR23 -#define MLBLCBCR24 MLB.LCBCR24 -#define MLBLCBCR25 MLB.LCBCR25 -#define MLBLCBCR26 MLB.LCBCR26 -#define MLBLCBCR27 MLB.LCBCR27 -#define MLBLCBCR28 MLB.LCBCR28 -#define MLBLCBCR29 MLB.LCBCR29 -#define MLBLCBCR30 MLB.LCBCR30 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ /* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h index 43a23670d0..cccfd79f66 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h @@ -18,20 +18,53 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : mmc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef MMC_IODEFINE_H #define MMC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_mmc -{ /* MMC */ +#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */ + + +#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH) +#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL) +#define MMCCE_ARG (MMC.CE_ARG) +#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12) +#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL) +#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET) +#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL) +#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC) +#define MMCCE_RESP3 (MMC.CE_RESP3) +#define MMCCE_RESP2 (MMC.CE_RESP2) +#define MMCCE_RESP1 (MMC.CE_RESP1) +#define MMCCE_RESP0 (MMC.CE_RESP0) +#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12) +#define MMCCE_DATA (MMC.CE_DATA) +#define MMCCE_INT (MMC.CE_INT) +#define MMCCE_INT_EN (MMC.CE_INT_EN) +#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1) +#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2) +#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE) +#define MMCCE_DETECT (MMC.CE_DETECT) +#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE) +#define MMCCE_VERSION (MMC.CE_VERSION) + +#define MMC_CE_RESPn_COUNT (4) + + +typedef struct st_mmc +{ + /* MMC */ volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */ volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */ volatile uint8_t dummy182[4]; /* */ @@ -41,7 +74,8 @@ struct st_mmc volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */ volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */ volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */ -#define MMC_CE_RESPn_COUNT 4 + +/* #define MMC_CE_RESPn_COUNT (4) */ volatile uint32_t CE_RESP3; /* CE_RESP3 */ volatile uint32_t CE_RESP2; /* CE_RESP2 */ volatile uint32_t CE_RESP1; /* CE_RESP1 */ @@ -60,33 +94,11 @@ struct st_mmc volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */ volatile uint8_t dummy186[4]; /* */ volatile uint32_t CE_VERSION; /* CE_VERSION */ -}; +} r_io_mmc_t; -#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */ - - -#define MMCCE_CMD_SETH MMC.CE_CMD_SETH -#define MMCCE_CMD_SETL MMC.CE_CMD_SETL -#define MMCCE_ARG MMC.CE_ARG -#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12 -#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL -#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET -#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL -#define MMCCE_BUF_ACC MMC.CE_BUF_ACC -#define MMCCE_RESP3 MMC.CE_RESP3 -#define MMCCE_RESP2 MMC.CE_RESP2 -#define MMCCE_RESP1 MMC.CE_RESP1 -#define MMCCE_RESP0 MMC.CE_RESP0 -#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12 -#define MMCCE_DATA MMC.CE_DATA -#define MMCCE_INT MMC.CE_INT -#define MMCCE_INT_EN MMC.CE_INT_EN -#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1 -#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2 -#define MMCCE_DMA_MODE MMC.CE_DMA_MODE -#define MMCCE_DETECT MMC.CE_DETECT -#define MMCCE_ADD_MODE MMC.CE_ADD_MODE -#define MMCCE_VERSION MMC.CE_VERSION /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h index c2d0aeec84..9e3248029f 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h @@ -18,20 +18,108 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : mtu2_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef MTU2_IODEFINE_H #define MTU2_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_mtu2 -{ /* MTU2 */ +#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */ + + +#define MTU2TCR_2 (MTU2.TCR_2) +#define MTU2TMDR_2 (MTU2.TMDR_2) +#define MTU2TIOR_2 (MTU2.TIOR_2) +#define MTU2TIER_2 (MTU2.TIER_2) +#define MTU2TSR_2 (MTU2.TSR_2) +#define MTU2TCNT_2 (MTU2.TCNT_2) +#define MTU2TGRA_2 (MTU2.TGRA_2) +#define MTU2TGRB_2 (MTU2.TGRB_2) +#define MTU2TCR_3 (MTU2.TCR_3) +#define MTU2TCR_4 (MTU2.TCR_4) +#define MTU2TMDR_3 (MTU2.TMDR_3) +#define MTU2TMDR_4 (MTU2.TMDR_4) +#define MTU2TIORH_3 (MTU2.TIORH_3) +#define MTU2TIORL_3 (MTU2.TIORL_3) +#define MTU2TIORH_4 (MTU2.TIORH_4) +#define MTU2TIORL_4 (MTU2.TIORL_4) +#define MTU2TIER_3 (MTU2.TIER_3) +#define MTU2TIER_4 (MTU2.TIER_4) +#define MTU2TOER (MTU2.TOER) +#define MTU2TGCR (MTU2.TGCR) +#define MTU2TOCR1 (MTU2.TOCR1) +#define MTU2TOCR2 (MTU2.TOCR2) +#define MTU2TCNT_3 (MTU2.TCNT_3) +#define MTU2TCNT_4 (MTU2.TCNT_4) +#define MTU2TCDR (MTU2.TCDR) +#define MTU2TDDR (MTU2.TDDR) +#define MTU2TGRA_3 (MTU2.TGRA_3) +#define MTU2TGRB_3 (MTU2.TGRB_3) +#define MTU2TGRA_4 (MTU2.TGRA_4) +#define MTU2TGRB_4 (MTU2.TGRB_4) +#define MTU2TCNTS (MTU2.TCNTS) +#define MTU2TCBR (MTU2.TCBR) +#define MTU2TGRC_3 (MTU2.TGRC_3) +#define MTU2TGRD_3 (MTU2.TGRD_3) +#define MTU2TGRC_4 (MTU2.TGRC_4) +#define MTU2TGRD_4 (MTU2.TGRD_4) +#define MTU2TSR_3 (MTU2.TSR_3) +#define MTU2TSR_4 (MTU2.TSR_4) +#define MTU2TITCR (MTU2.TITCR) +#define MTU2TITCNT (MTU2.TITCNT) +#define MTU2TBTER (MTU2.TBTER) +#define MTU2TDER (MTU2.TDER) +#define MTU2TOLBR (MTU2.TOLBR) +#define MTU2TBTM_3 (MTU2.TBTM_3) +#define MTU2TBTM_4 (MTU2.TBTM_4) +#define MTU2TADCR (MTU2.TADCR) +#define MTU2TADCORA_4 (MTU2.TADCORA_4) +#define MTU2TADCORB_4 (MTU2.TADCORB_4) +#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4) +#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4) +#define MTU2TWCR (MTU2.TWCR) +#define MTU2TSTR (MTU2.TSTR) +#define MTU2TSYR (MTU2.TSYR) +#define MTU2TRWER (MTU2.TRWER) +#define MTU2TCR_0 (MTU2.TCR_0) +#define MTU2TMDR_0 (MTU2.TMDR_0) +#define MTU2TIORH_0 (MTU2.TIORH_0) +#define MTU2TIORL_0 (MTU2.TIORL_0) +#define MTU2TIER_0 (MTU2.TIER_0) +#define MTU2TSR_0 (MTU2.TSR_0) +#define MTU2TCNT_0 (MTU2.TCNT_0) +#define MTU2TGRA_0 (MTU2.TGRA_0) +#define MTU2TGRB_0 (MTU2.TGRB_0) +#define MTU2TGRC_0 (MTU2.TGRC_0) +#define MTU2TGRD_0 (MTU2.TGRD_0) +#define MTU2TGRE_0 (MTU2.TGRE_0) +#define MTU2TGRF_0 (MTU2.TGRF_0) +#define MTU2TIER2_0 (MTU2.TIER2_0) +#define MTU2TSR2_0 (MTU2.TSR2_0) +#define MTU2TBTM_0 (MTU2.TBTM_0) +#define MTU2TCR_1 (MTU2.TCR_1) +#define MTU2TMDR_1 (MTU2.TMDR_1) +#define MTU2TIOR_1 (MTU2.TIOR_1) +#define MTU2TIER_1 (MTU2.TIER_1) +#define MTU2TSR_1 (MTU2.TSR_1) +#define MTU2TCNT_1 (MTU2.TCNT_1) +#define MTU2TGRA_1 (MTU2.TGRA_1) +#define MTU2TGRB_1 (MTU2.TGRB_1) +#define MTU2TICCR (MTU2.TICCR) + + +typedef struct st_mtu2 +{ + /* MTU2 */ volatile uint8_t TCR_2; /* TCR_2 */ volatile uint8_t TMDR_2; /* TMDR_2 */ volatile uint8_t TIOR_2; /* TIOR_2 */ @@ -128,90 +216,11 @@ struct st_mtu2 volatile uint16_t TGRB_1; /* TGRB_1 */ volatile uint8_t dummy536[4]; /* */ volatile uint8_t TICCR; /* TICCR */ -}; +} r_io_mtu2_t; -#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */ - - -#define MTU2TCR_2 MTU2.TCR_2 -#define MTU2TMDR_2 MTU2.TMDR_2 -#define MTU2TIOR_2 MTU2.TIOR_2 -#define MTU2TIER_2 MTU2.TIER_2 -#define MTU2TSR_2 MTU2.TSR_2 -#define MTU2TCNT_2 MTU2.TCNT_2 -#define MTU2TGRA_2 MTU2.TGRA_2 -#define MTU2TGRB_2 MTU2.TGRB_2 -#define MTU2TCR_3 MTU2.TCR_3 -#define MTU2TCR_4 MTU2.TCR_4 -#define MTU2TMDR_3 MTU2.TMDR_3 -#define MTU2TMDR_4 MTU2.TMDR_4 -#define MTU2TIORH_3 MTU2.TIORH_3 -#define MTU2TIORL_3 MTU2.TIORL_3 -#define MTU2TIORH_4 MTU2.TIORH_4 -#define MTU2TIORL_4 MTU2.TIORL_4 -#define MTU2TIER_3 MTU2.TIER_3 -#define MTU2TIER_4 MTU2.TIER_4 -#define MTU2TOER MTU2.TOER -#define MTU2TGCR MTU2.TGCR -#define MTU2TOCR1 MTU2.TOCR1 -#define MTU2TOCR2 MTU2.TOCR2 -#define MTU2TCNT_3 MTU2.TCNT_3 -#define MTU2TCNT_4 MTU2.TCNT_4 -#define MTU2TCDR MTU2.TCDR -#define MTU2TDDR MTU2.TDDR -#define MTU2TGRA_3 MTU2.TGRA_3 -#define MTU2TGRB_3 MTU2.TGRB_3 -#define MTU2TGRA_4 MTU2.TGRA_4 -#define MTU2TGRB_4 MTU2.TGRB_4 -#define MTU2TCNTS MTU2.TCNTS -#define MTU2TCBR MTU2.TCBR -#define MTU2TGRC_3 MTU2.TGRC_3 -#define MTU2TGRD_3 MTU2.TGRD_3 -#define MTU2TGRC_4 MTU2.TGRC_4 -#define MTU2TGRD_4 MTU2.TGRD_4 -#define MTU2TSR_3 MTU2.TSR_3 -#define MTU2TSR_4 MTU2.TSR_4 -#define MTU2TITCR MTU2.TITCR -#define MTU2TITCNT MTU2.TITCNT -#define MTU2TBTER MTU2.TBTER -#define MTU2TDER MTU2.TDER -#define MTU2TOLBR MTU2.TOLBR -#define MTU2TBTM_3 MTU2.TBTM_3 -#define MTU2TBTM_4 MTU2.TBTM_4 -#define MTU2TADCR MTU2.TADCR -#define MTU2TADCORA_4 MTU2.TADCORA_4 -#define MTU2TADCORB_4 MTU2.TADCORB_4 -#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4 -#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4 -#define MTU2TWCR MTU2.TWCR -#define MTU2TSTR MTU2.TSTR -#define MTU2TSYR MTU2.TSYR -#define MTU2TRWER MTU2.TRWER -#define MTU2TCR_0 MTU2.TCR_0 -#define MTU2TMDR_0 MTU2.TMDR_0 -#define MTU2TIORH_0 MTU2.TIORH_0 -#define MTU2TIORL_0 MTU2.TIORL_0 -#define MTU2TIER_0 MTU2.TIER_0 -#define MTU2TSR_0 MTU2.TSR_0 -#define MTU2TCNT_0 MTU2.TCNT_0 -#define MTU2TGRA_0 MTU2.TGRA_0 -#define MTU2TGRB_0 MTU2.TGRB_0 -#define MTU2TGRC_0 MTU2.TGRC_0 -#define MTU2TGRD_0 MTU2.TGRD_0 -#define MTU2TGRE_0 MTU2.TGRE_0 -#define MTU2TGRF_0 MTU2.TGRF_0 -#define MTU2TIER2_0 MTU2.TIER2_0 -#define MTU2TSR2_0 MTU2.TSR2_0 -#define MTU2TBTM_0 MTU2.TBTM_0 -#define MTU2TCR_1 MTU2.TCR_1 -#define MTU2TMDR_1 MTU2.TMDR_1 -#define MTU2TIOR_1 MTU2.TIOR_1 -#define MTU2TIER_1 MTU2.TIER_1 -#define MTU2TSR_1 MTU2.TSR_1 -#define MTU2TCNT_1 MTU2.TCNT_1 -#define MTU2TGRA_1 MTU2.TGRA_1 -#define MTU2TGRB_1 MTU2.TGRB_1 -#define MTU2TICCR MTU2.TICCR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h index b0aa5587db..f246dd3773 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h @@ -18,20 +18,55 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ostm_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef OSTM_IODEFINE_H #define OSTM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ostm -{ /* OSTM */ +#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */ +#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */ + + +/* Start of channel array defines of OSTM */ + +/* Channel array defines of OSTM */ +/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */ +#define OSTM_COUNT (2) +#define OSTM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &OSTM0, &OSTM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of OSTM */ + + +#define OSTM0CMP (OSTM0.OSTMnCMP) +#define OSTM0CNT (OSTM0.OSTMnCNT) +#define OSTM0TE (OSTM0.OSTMnTE) +#define OSTM0TS (OSTM0.OSTMnTS) +#define OSTM0TT (OSTM0.OSTMnTT) +#define OSTM0CTL (OSTM0.OSTMnCTL) +#define OSTM1CMP (OSTM1.OSTMnCMP) +#define OSTM1CNT (OSTM1.OSTMnCNT) +#define OSTM1TE (OSTM1.OSTMnTE) +#define OSTM1TS (OSTM1.OSTMnTS) +#define OSTM1TT (OSTM1.OSTMnTT) +#define OSTM1CTL (OSTM1.OSTMnCTL) + + +typedef struct st_ostm +{ + /* OSTM */ volatile uint32_t OSTMnCMP; /* OSTMnCMP */ volatile uint32_t OSTMnCNT; /* OSTMnCNT */ volatile uint8_t dummy1[8]; /* */ @@ -42,37 +77,21 @@ struct st_ostm volatile uint8_t OSTMnTT; /* OSTMnTT */ volatile uint8_t dummy4[7]; /* */ volatile uint8_t OSTMnCTL; /* OSTMnCTL */ -}; +} r_io_ostm_t; -#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */ -#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */ +/* Channel array defines of OSTM (2)*/ +#ifdef DECLARE_OSTM_CHANNELS +volatile struct st_ostm* OSTM[ OSTM_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + OSTM_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_OSTM_CHANNELS */ +/* End of channel array defines of OSTM (2)*/ -/* Start of channnel array defines of OSTM */ - -/* Channnel array defines of OSTM */ -/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */ -#define OSTM_COUNT 2 -#define OSTM_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &OSTM0, &OSTM1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of OSTM */ - - -#define OSTM0CMP OSTM0.OSTMnCMP -#define OSTM0CNT OSTM0.OSTMnCNT -#define OSTM0TE OSTM0.OSTMnTE -#define OSTM0TS OSTM0.OSTMnTS -#define OSTM0TT OSTM0.OSTMnTT -#define OSTM0CTL OSTM0.OSTMnCTL -#define OSTM1CMP OSTM1.OSTMnCMP -#define OSTM1CNT OSTM1.OSTMnCNT -#define OSTM1TE OSTM1.OSTMnTE -#define OSTM1TS OSTM1.OSTMnTS -#define OSTM1TT OSTM1.OSTMnTT -#define OSTM1CTL OSTM1.OSTMnCTL /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h index 230dd62947..e62a51cca3 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h @@ -18,25 +18,112 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : pfv_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef PFV_IODEFINE_H #define PFV_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_pfv -{ /* PFV */ +#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ +#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ + + +/* Start of channel array defines of PFV */ + +/* Channel array defines of PFV */ +/*(Sample) value = PFV[ channel ]->PFVCR; */ +#define PFV_COUNT (2) +#define PFV_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &PFV0, &PFV1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of PFV */ + + +#define PFV0PFVCR (PFV0.PFVCR) +#define PFV0PFVICR (PFV0.PFVICR) +#define PFV0PFVISR (PFV0.PFVISR) +#define PFV0PFVID0 (PFV0.PFVID0) +#define PFV0PFVID1 (PFV0.PFVID1) +#define PFV0PFVID2 (PFV0.PFVID2) +#define PFV0PFVID3 (PFV0.PFVID3) +#define PFV0PFVID4 (PFV0.PFVID4) +#define PFV0PFVID5 (PFV0.PFVID5) +#define PFV0PFVID6 (PFV0.PFVID6) +#define PFV0PFVID7 (PFV0.PFVID7) +#define PFV0PFVOD0 (PFV0.PFVOD0) +#define PFV0PFVOD1 (PFV0.PFVOD1) +#define PFV0PFVOD2 (PFV0.PFVOD2) +#define PFV0PFVOD3 (PFV0.PFVOD3) +#define PFV0PFVOD4 (PFV0.PFVOD4) +#define PFV0PFVOD5 (PFV0.PFVOD5) +#define PFV0PFVOD6 (PFV0.PFVOD6) +#define PFV0PFVOD7 (PFV0.PFVOD7) +#define PFV0PFVIFSR (PFV0.PFVIFSR) +#define PFV0PFVOFSR (PFV0.PFVOFSR) +#define PFV0PFVACR (PFV0.PFVACR) +#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE) +#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0) +#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1) +#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0) +#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1) +#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0) +#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1) +#define PFV0PFVSZR (PFV0.PFVSZR) +#define PFV1PFVCR (PFV1.PFVCR) +#define PFV1PFVICR (PFV1.PFVICR) +#define PFV1PFVISR (PFV1.PFVISR) +#define PFV1PFVID0 (PFV1.PFVID0) +#define PFV1PFVID1 (PFV1.PFVID1) +#define PFV1PFVID2 (PFV1.PFVID2) +#define PFV1PFVID3 (PFV1.PFVID3) +#define PFV1PFVID4 (PFV1.PFVID4) +#define PFV1PFVID5 (PFV1.PFVID5) +#define PFV1PFVID6 (PFV1.PFVID6) +#define PFV1PFVID7 (PFV1.PFVID7) +#define PFV1PFVOD0 (PFV1.PFVOD0) +#define PFV1PFVOD1 (PFV1.PFVOD1) +#define PFV1PFVOD2 (PFV1.PFVOD2) +#define PFV1PFVOD3 (PFV1.PFVOD3) +#define PFV1PFVOD4 (PFV1.PFVOD4) +#define PFV1PFVOD5 (PFV1.PFVOD5) +#define PFV1PFVOD6 (PFV1.PFVOD6) +#define PFV1PFVOD7 (PFV1.PFVOD7) +#define PFV1PFVIFSR (PFV1.PFVIFSR) +#define PFV1PFVOFSR (PFV1.PFVOFSR) +#define PFV1PFVACR (PFV1.PFVACR) +#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE) +#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0) +#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1) +#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0) +#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1) +#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0) +#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1) +#define PFV1PFVSZR (PFV1.PFVSZR) + +#define PFVID_COUNT (8) +#define PFVOD_COUNT (8) + + +typedef struct st_pfv +{ + /* PFV */ volatile uint32_t PFVCR; /* PFVCR */ volatile uint32_t PFVICR; /* PFVICR */ volatile uint32_t PFVISR; /* PFVISR */ volatile uint8_t dummy1[20]; /* */ -#define PFVID_COUNT 8 + +/* #define PFVID_COUNT (8) */ volatile uint32_t PFVID0; /* PFVID0 */ volatile uint32_t PFVID1; /* PFVID1 */ volatile uint32_t PFVID2; /* PFVID2 */ @@ -45,7 +132,8 @@ struct st_pfv volatile uint32_t PFVID5; /* PFVID5 */ volatile uint32_t PFVID6; /* PFVID6 */ volatile uint32_t PFVID7; /* PFVID7 */ -#define PFVOD_COUNT 8 + +/* #define PFVOD_COUNT (8) */ volatile uint32_t PFVOD0; /* PFVOD0 */ volatile uint32_t PFVOD1; /* PFVOD1 */ volatile uint32_t PFVOD2; /* PFVOD2 */ @@ -66,85 +154,21 @@ struct st_pfv volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */ volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */ volatile uint32_t PFVSZR; /* PFVSZR */ -}; +} r_io_pfv_t; -#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ -#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ +/* Channel array defines of PFV (2)*/ +#ifdef DECLARE_PFV_CHANNELS +volatile struct st_pfv* PFV[ PFV_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + PFV_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_PFV_CHANNELS */ +/* End of channel array defines of PFV (2)*/ -/* Start of channnel array defines of PFV */ - -/* Channnel array defines of PFV */ -/*(Sample) value = PFV[ channel ]->PFVCR; */ -#define PFV_COUNT 2 -#define PFV_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &PFV0, &PFV1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of PFV */ - - -#define PFV0PFVCR PFV0.PFVCR -#define PFV0PFVICR PFV0.PFVICR -#define PFV0PFVISR PFV0.PFVISR -#define PFV0PFVID0 PFV0.PFVID0 -#define PFV0PFVID1 PFV0.PFVID1 -#define PFV0PFVID2 PFV0.PFVID2 -#define PFV0PFVID3 PFV0.PFVID3 -#define PFV0PFVID4 PFV0.PFVID4 -#define PFV0PFVID5 PFV0.PFVID5 -#define PFV0PFVID6 PFV0.PFVID6 -#define PFV0PFVID7 PFV0.PFVID7 -#define PFV0PFVOD0 PFV0.PFVOD0 -#define PFV0PFVOD1 PFV0.PFVOD1 -#define PFV0PFVOD2 PFV0.PFVOD2 -#define PFV0PFVOD3 PFV0.PFVOD3 -#define PFV0PFVOD4 PFV0.PFVOD4 -#define PFV0PFVOD5 PFV0.PFVOD5 -#define PFV0PFVOD6 PFV0.PFVOD6 -#define PFV0PFVOD7 PFV0.PFVOD7 -#define PFV0PFVIFSR PFV0.PFVIFSR -#define PFV0PFVOFSR PFV0.PFVOFSR -#define PFV0PFVACR PFV0.PFVACR -#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE -#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0 -#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1 -#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0 -#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1 -#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0 -#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1 -#define PFV0PFVSZR PFV0.PFVSZR -#define PFV1PFVCR PFV1.PFVCR -#define PFV1PFVICR PFV1.PFVICR -#define PFV1PFVISR PFV1.PFVISR -#define PFV1PFVID0 PFV1.PFVID0 -#define PFV1PFVID1 PFV1.PFVID1 -#define PFV1PFVID2 PFV1.PFVID2 -#define PFV1PFVID3 PFV1.PFVID3 -#define PFV1PFVID4 PFV1.PFVID4 -#define PFV1PFVID5 PFV1.PFVID5 -#define PFV1PFVID6 PFV1.PFVID6 -#define PFV1PFVID7 PFV1.PFVID7 -#define PFV1PFVOD0 PFV1.PFVOD0 -#define PFV1PFVOD1 PFV1.PFVOD1 -#define PFV1PFVOD2 PFV1.PFVOD2 -#define PFV1PFVOD3 PFV1.PFVOD3 -#define PFV1PFVOD4 PFV1.PFVOD4 -#define PFV1PFVOD5 PFV1.PFVOD5 -#define PFV1PFVOD6 PFV1.PFVOD6 -#define PFV1PFVOD7 PFV1.PFVOD7 -#define PFV1PFVIFSR PFV1.PFVIFSR -#define PFV1PFVOFSR PFV1.PFVOFSR -#define PFV1PFVACR PFV1.PFVACR -#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE -#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0 -#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1 -#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0 -#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1 -#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0 -#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1 -#define PFV1PFVSZR PFV1.PFVSZR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h index a7143d481d..128b1099d8 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h @@ -18,83 +18,29 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : pwm_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef PWM_IODEFINE_H #define PWM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -union reg16_8_t -{ - volatile uint16_t UINT16; /* 16-bit Access */ - volatile uint8_t UINT8[2]; /* 8-bit Access */ -}; - -struct st_pwm -{ /* PWM */ - volatile uint8_t dummy559[2]; /* */ - union reg16_8_t PWBTCR; /* PWBTCR */ - - volatile uint8_t dummy560[216]; /* */ - -/* start of struct st_pwm_common */ - union reg16_8_t PWCR_1; /* PWCR_1 */ - - volatile uint8_t dummy561[2]; /* */ - union reg16_8_t PWPR_1; /* PWPR_1 */ - - volatile uint16_t PWCYR_1; /* PWCYR_1 */ - volatile uint16_t PWBFR_1A; /* PWBFR_1A */ - volatile uint16_t PWBFR_1C; /* PWBFR_1C */ - volatile uint16_t PWBFR_1E; /* PWBFR_1E */ - volatile uint16_t PWBFR_1G; /* PWBFR_1G */ -/* end of struct st_pwm_common */ - -/* start of struct st_pwm_common */ - union reg16_8_t PWCR_2; /* PWCR_2 */ - - volatile uint8_t dummy562[2]; /* */ - union reg16_8_t PWPR_2; /* PWPR_2 */ - - volatile uint16_t PWCYR_2; /* PWCYR_2 */ - volatile uint16_t PWBFR_2A; /* PWBFR_2A */ - volatile uint16_t PWBFR_2C; /* PWBFR_2C */ - volatile uint16_t PWBFR_2E; /* PWBFR_2E */ - volatile uint16_t PWBFR_2G; /* PWBFR_2G */ -/* end of struct st_pwm_common */ -}; - - -struct st_pwm_common -{ - union reg16_8_t PWCR_1; /* PWCR_1 */ - - volatile uint8_t dummy572[2]; /* */ - union reg16_8_t PWPR_1; /* PWPR_1 */ - - volatile uint16_t PWCYR_1; /* PWCYR_1 */ - volatile uint16_t PWBFR_1A; /* PWBFR_1A */ - volatile uint16_t PWBFR_1C; /* PWBFR_1C */ - volatile uint16_t PWBFR_1E; /* PWBFR_1E */ - volatile uint16_t PWBFR_1G; /* PWBFR_1G */ -}; - - #define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */ -/* Start of channnel array defines of PWM */ +/* Start of channel array defines of PWM */ -/* Channnel array defines of PWMn */ -/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */ -#define PWMn_COUNT 2 +/* Channel array defines of PWMn */ +/*(Sample) value = PWMn[ channel ]->PWCR_1; */ +#define PWMn_COUNT (2) #define PWMn_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &PWM1, &PWM2 \ @@ -102,34 +48,88 @@ struct st_pwm_common #define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */ #define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */ -/* End of channnel array defines of PWM */ +/* End of channel array defines of PWM */ + + +#define PWMPWBTCR (PWM.PWBTCR) +#define PWMPWCR_1 (PWM.PWCR_1) +#define PWMPWPR_1 (PWM.PWPR_1) +#define PWMPWCYR_1 (PWM.PWCYR_1) +#define PWMPWBFR_1A (PWM.PWBFR_1A) +#define PWMPWBFR_1C (PWM.PWBFR_1C) +#define PWMPWBFR_1E (PWM.PWBFR_1E) +#define PWMPWBFR_1G (PWM.PWBFR_1G) +#define PWMPWCR_2 (PWM.PWCR_2) +#define PWMPWPR_2 (PWM.PWPR_2) +#define PWMPWCYR_2 (PWM.PWCYR_2) +#define PWMPWBFR_2A (PWM.PWBFR_2A) +#define PWMPWBFR_2C (PWM.PWBFR_2C) +#define PWMPWBFR_2E (PWM.PWBFR_2E) +#define PWMPWBFR_2G (PWM.PWBFR_2G) + + +typedef struct st_pwm +{ + /* PWM */ + volatile uint8_t dummy559[2]; /* */ + volatile uint8_t PWBTCR; /* PWBTCR */ + volatile uint8_t dummy560[217]; /* */ + +/* start of struct st_pwm_common */ + volatile uint8_t PWCR_1; /* PWCR_1 */ + volatile uint8_t dummy561[3]; /* */ + volatile uint8_t PWPR_1; /* PWPR_1 */ + volatile uint8_t dummy562[1]; /* */ + volatile uint16_t PWCYR_1; /* PWCYR_1 */ + volatile uint16_t PWBFR_1A; /* PWBFR_1A */ + volatile uint16_t PWBFR_1C; /* PWBFR_1C */ + volatile uint16_t PWBFR_1E; /* PWBFR_1E */ + volatile uint16_t PWBFR_1G; /* PWBFR_1G */ + +/* end of struct st_pwm_common */ + +/* start of struct st_pwm_common */ + volatile uint8_t PWCR_2; /* PWCR_2 */ + volatile uint8_t dummy563[3]; /* */ + volatile uint8_t PWPR_2; /* PWPR_2 */ + volatile uint8_t dummy564[1]; /* */ + volatile uint16_t PWCYR_2; /* PWCYR_2 */ + volatile uint16_t PWBFR_2A; /* PWBFR_2A */ + volatile uint16_t PWBFR_2C; /* PWBFR_2C */ + volatile uint16_t PWBFR_2E; /* PWBFR_2E */ + volatile uint16_t PWBFR_2G; /* PWBFR_2G */ + +/* end of struct st_pwm_common */ +} r_io_pwm_t; + + +typedef struct st_pwm_common +{ + + volatile uint8_t PWCR_1; /* PWCR_1 */ + volatile uint8_t dummy562[3]; /* */ + volatile uint8_t PWPR_1; /* PWPR_1 */ + volatile uint8_t dummy563[1]; /* */ + volatile uint16_t PWCYR_1; /* PWCYR_1 */ + volatile uint16_t PWBFR_1A; /* PWBFR_1A */ + volatile uint16_t PWBFR_1C; /* PWBFR_1C */ + volatile uint16_t PWBFR_1E; /* PWBFR_1E */ + volatile uint16_t PWBFR_1G; /* PWBFR_1G */ +} r_io_pwm_common_t; + + +/* Channel array defines of PWMn (2)*/ +#ifdef DECLARE_PWMn_CHANNELS +volatile struct st_pwm_common* PWMn[ PWMn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + PWMn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_PWMn_CHANNELS */ +/* End of channel array defines of PWMn (2)*/ -#define PWMPWBTCR PWM.PWBTCR.UINT16 -#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0] -#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1] -#define PWMPWCR_1 PWM.PWCR_1.UINT16 -#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0] -#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1] -#define PWMPWPR_1 PWM.PWPR_1.UINT16 -#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0] -#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1] -#define PWMPWCYR_1 PWM.PWCYR_1 -#define PWMPWBFR_1A PWM.PWBFR_1A -#define PWMPWBFR_1C PWM.PWBFR_1C -#define PWMPWBFR_1E PWM.PWBFR_1E -#define PWMPWBFR_1G PWM.PWBFR_1G -#define PWMPWCR_2 PWM.PWCR_2.UINT16 -#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0] -#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1] -#define PWMPWPR_2 PWM.PWPR_2.UINT16 -#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0] -#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1] -#define PWMPWCYR_2 PWM.PWCYR_2 -#define PWMPWBFR_2A PWM.PWBFR_2A -#define PWMPWBFR_2C PWM.PWBFR_2C -#define PWMPWBFR_2E PWM.PWBFR_2E -#define PWMPWBFR_2G PWM.PWBFR_2G /* <-SEC M1.10.1 */ /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h index 9daefe447a..8fd2be68db 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h @@ -18,45 +18,20 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : riic_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef RIIC_IODEFINE_H #define RIIC_IODEFINE_H - -#include "reg32_t.h" - -struct st_riic -{ /* RIIC */ -#define RIICnCRm_COUNT 2 - union reg32_t RIICnCR1; /* RIICnCR1 */ - union reg32_t RIICnCR2; /* RIICnCR2 */ -#define RIICnMRm_COUNT 3 - union reg32_t RIICnMR1; /* RIICnMR1 */ - union reg32_t RIICnMR2; /* RIICnMR2 */ - union reg32_t RIICnMR3; /* RIICnMR3 */ - union reg32_t RIICnFER; /* RIICnFER */ - union reg32_t RIICnSER; /* RIICnSER */ - union reg32_t RIICnIER; /* RIICnIER */ -#define RIICnSRm_COUNT 2 - union reg32_t RIICnSR1; /* RIICnSR1 */ - union reg32_t RIICnSR2; /* RIICnSR2 */ -#define RIICnSARm_COUNT 3 - union reg32_t RIICnSAR0; /* RIICnSAR0 */ - union reg32_t RIICnSAR1; /* RIICnSAR1 */ - union reg32_t RIICnSAR2; /* RIICnSAR2 */ - union reg32_t RIICnBRL; /* RIICnBRL */ - union reg32_t RIICnBRH; /* RIICnBRH */ - union reg32_t RIICnDRT; /* RIICnDRT */ - union reg32_t RIICnDRR; /* RIICnDRR */ - -}; - +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ #define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */ #define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */ @@ -64,493 +39,546 @@ struct st_riic #define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */ -/* Start of channnel array defines of RIIC */ +/* Start of channel array defines of RIIC */ -/* Channnel array defines of RIIC */ +/* Channel array defines of RIIC */ /*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */ -#define RIIC_COUNT 4 +#define RIIC_COUNT (4) #define RIIC_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RIIC0, &RIIC1, &RIIC2, &RIIC3 \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of RIIC */ +/* End of channel array defines of RIIC */ -#define RIIC0CR1 RIIC0.RIICnCR1.UINT32 -#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L] -#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL] -#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH] -#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H] -#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL] -#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH] -#define RIIC0CR2 RIIC0.RIICnCR2.UINT32 -#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L] -#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL] -#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH] -#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H] -#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL] -#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH] -#define RIIC0MR1 RIIC0.RIICnMR1.UINT32 -#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L] -#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL] -#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH] -#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H] -#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL] -#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH] -#define RIIC0MR2 RIIC0.RIICnMR2.UINT32 -#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L] -#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL] -#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH] -#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H] -#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL] -#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH] -#define RIIC0MR3 RIIC0.RIICnMR3.UINT32 -#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L] -#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL] -#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH] -#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H] -#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL] -#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH] -#define RIIC0FER RIIC0.RIICnFER.UINT32 -#define RIIC0FERL RIIC0.RIICnFER.UINT16[L] -#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL] -#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH] -#define RIIC0FERH RIIC0.RIICnFER.UINT16[H] -#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL] -#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH] -#define RIIC0SER RIIC0.RIICnSER.UINT32 -#define RIIC0SERL RIIC0.RIICnSER.UINT16[L] -#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL] -#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH] -#define RIIC0SERH RIIC0.RIICnSER.UINT16[H] -#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL] -#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH] -#define RIIC0IER RIIC0.RIICnIER.UINT32 -#define RIIC0IERL RIIC0.RIICnIER.UINT16[L] -#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL] -#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH] -#define RIIC0IERH RIIC0.RIICnIER.UINT16[H] -#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL] -#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH] -#define RIIC0SR1 RIIC0.RIICnSR1.UINT32 -#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L] -#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL] -#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH] -#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H] -#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL] -#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH] -#define RIIC0SR2 RIIC0.RIICnSR2.UINT32 -#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L] -#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL] -#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH] -#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H] -#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL] -#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH] -#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32 -#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L] -#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL] -#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH] -#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H] -#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL] -#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH] -#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32 -#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L] -#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL] -#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH] -#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H] -#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL] -#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH] -#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32 -#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L] -#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL] -#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH] -#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H] -#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL] -#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH] -#define RIIC0BRL RIIC0.RIICnBRL.UINT32 -#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L] -#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL] -#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH] -#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H] -#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL] -#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH] -#define RIIC0BRH RIIC0.RIICnBRH.UINT32 -#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L] -#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL] -#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH] -#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H] -#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL] -#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH] -#define RIIC0DRT RIIC0.RIICnDRT.UINT32 -#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L] -#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL] -#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH] -#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H] -#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL] -#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH] -#define RIIC0DRR RIIC0.RIICnDRR.UINT32 -#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L] -#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL] -#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH] -#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H] -#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL] -#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH] -#define RIIC1CR1 RIIC1.RIICnCR1.UINT32 -#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L] -#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL] -#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH] -#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H] -#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL] -#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH] -#define RIIC1CR2 RIIC1.RIICnCR2.UINT32 -#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L] -#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL] -#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH] -#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H] -#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL] -#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH] -#define RIIC1MR1 RIIC1.RIICnMR1.UINT32 -#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L] -#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL] -#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH] -#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H] -#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL] -#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH] -#define RIIC1MR2 RIIC1.RIICnMR2.UINT32 -#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L] -#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL] -#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH] -#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H] -#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL] -#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH] -#define RIIC1MR3 RIIC1.RIICnMR3.UINT32 -#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L] -#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL] -#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH] -#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H] -#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL] -#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH] -#define RIIC1FER RIIC1.RIICnFER.UINT32 -#define RIIC1FERL RIIC1.RIICnFER.UINT16[L] -#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL] -#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH] -#define RIIC1FERH RIIC1.RIICnFER.UINT16[H] -#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL] -#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH] -#define RIIC1SER RIIC1.RIICnSER.UINT32 -#define RIIC1SERL RIIC1.RIICnSER.UINT16[L] -#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL] -#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH] -#define RIIC1SERH RIIC1.RIICnSER.UINT16[H] -#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL] -#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH] -#define RIIC1IER RIIC1.RIICnIER.UINT32 -#define RIIC1IERL RIIC1.RIICnIER.UINT16[L] -#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL] -#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH] -#define RIIC1IERH RIIC1.RIICnIER.UINT16[H] -#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL] -#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH] -#define RIIC1SR1 RIIC1.RIICnSR1.UINT32 -#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L] -#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL] -#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH] -#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H] -#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL] -#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH] -#define RIIC1SR2 RIIC1.RIICnSR2.UINT32 -#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L] -#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL] -#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH] -#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H] -#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL] -#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH] -#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32 -#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L] -#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL] -#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH] -#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H] -#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL] -#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH] -#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32 -#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L] -#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL] -#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH] -#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H] -#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL] -#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH] -#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32 -#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L] -#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL] -#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH] -#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H] -#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL] -#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH] -#define RIIC1BRL RIIC1.RIICnBRL.UINT32 -#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L] -#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL] -#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH] -#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H] -#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL] -#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH] -#define RIIC1BRH RIIC1.RIICnBRH.UINT32 -#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L] -#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL] -#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH] -#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H] -#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL] -#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH] -#define RIIC1DRT RIIC1.RIICnDRT.UINT32 -#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L] -#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL] -#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH] -#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H] -#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL] -#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH] -#define RIIC1DRR RIIC1.RIICnDRR.UINT32 -#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L] -#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL] -#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH] -#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H] -#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL] -#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH] -#define RIIC2CR1 RIIC2.RIICnCR1.UINT32 -#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L] -#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL] -#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH] -#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H] -#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL] -#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH] -#define RIIC2CR2 RIIC2.RIICnCR2.UINT32 -#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L] -#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL] -#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH] -#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H] -#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL] -#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH] -#define RIIC2MR1 RIIC2.RIICnMR1.UINT32 -#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L] -#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL] -#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH] -#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H] -#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL] -#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH] -#define RIIC2MR2 RIIC2.RIICnMR2.UINT32 -#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L] -#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL] -#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH] -#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H] -#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL] -#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH] -#define RIIC2MR3 RIIC2.RIICnMR3.UINT32 -#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L] -#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL] -#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH] -#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H] -#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL] -#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH] -#define RIIC2FER RIIC2.RIICnFER.UINT32 -#define RIIC2FERL RIIC2.RIICnFER.UINT16[L] -#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL] -#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH] -#define RIIC2FERH RIIC2.RIICnFER.UINT16[H] -#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL] -#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH] -#define RIIC2SER RIIC2.RIICnSER.UINT32 -#define RIIC2SERL RIIC2.RIICnSER.UINT16[L] -#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL] -#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH] -#define RIIC2SERH RIIC2.RIICnSER.UINT16[H] -#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL] -#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH] -#define RIIC2IER RIIC2.RIICnIER.UINT32 -#define RIIC2IERL RIIC2.RIICnIER.UINT16[L] -#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL] -#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH] -#define RIIC2IERH RIIC2.RIICnIER.UINT16[H] -#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL] -#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH] -#define RIIC2SR1 RIIC2.RIICnSR1.UINT32 -#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L] -#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL] -#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH] -#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H] -#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL] -#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH] -#define RIIC2SR2 RIIC2.RIICnSR2.UINT32 -#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L] -#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL] -#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH] -#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H] -#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL] -#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH] -#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32 -#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L] -#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL] -#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH] -#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H] -#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL] -#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH] -#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32 -#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L] -#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL] -#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH] -#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H] -#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL] -#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH] -#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32 -#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L] -#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL] -#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH] -#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H] -#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL] -#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH] -#define RIIC2BRL RIIC2.RIICnBRL.UINT32 -#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L] -#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL] -#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH] -#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H] -#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL] -#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH] -#define RIIC2BRH RIIC2.RIICnBRH.UINT32 -#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L] -#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL] -#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH] -#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H] -#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL] -#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH] -#define RIIC2DRT RIIC2.RIICnDRT.UINT32 -#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L] -#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL] -#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH] -#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H] -#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL] -#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH] -#define RIIC2DRR RIIC2.RIICnDRR.UINT32 -#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L] -#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL] -#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH] -#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H] -#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL] -#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH] -#define RIIC3CR1 RIIC3.RIICnCR1.UINT32 -#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L] -#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL] -#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH] -#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H] -#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL] -#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH] -#define RIIC3CR2 RIIC3.RIICnCR2.UINT32 -#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L] -#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL] -#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH] -#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H] -#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL] -#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH] -#define RIIC3MR1 RIIC3.RIICnMR1.UINT32 -#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L] -#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL] -#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH] -#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H] -#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL] -#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH] -#define RIIC3MR2 RIIC3.RIICnMR2.UINT32 -#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L] -#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL] -#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH] -#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H] -#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL] -#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH] -#define RIIC3MR3 RIIC3.RIICnMR3.UINT32 -#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L] -#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL] -#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH] -#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H] -#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL] -#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH] -#define RIIC3FER RIIC3.RIICnFER.UINT32 -#define RIIC3FERL RIIC3.RIICnFER.UINT16[L] -#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL] -#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH] -#define RIIC3FERH RIIC3.RIICnFER.UINT16[H] -#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL] -#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH] -#define RIIC3SER RIIC3.RIICnSER.UINT32 -#define RIIC3SERL RIIC3.RIICnSER.UINT16[L] -#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL] -#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH] -#define RIIC3SERH RIIC3.RIICnSER.UINT16[H] -#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL] -#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH] -#define RIIC3IER RIIC3.RIICnIER.UINT32 -#define RIIC3IERL RIIC3.RIICnIER.UINT16[L] -#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL] -#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH] -#define RIIC3IERH RIIC3.RIICnIER.UINT16[H] -#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL] -#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH] -#define RIIC3SR1 RIIC3.RIICnSR1.UINT32 -#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L] -#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL] -#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH] -#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H] -#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL] -#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH] -#define RIIC3SR2 RIIC3.RIICnSR2.UINT32 -#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L] -#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL] -#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH] -#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H] -#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL] -#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH] -#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32 -#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L] -#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL] -#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH] -#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H] -#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL] -#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH] -#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32 -#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L] -#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL] -#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH] -#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H] -#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL] -#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH] -#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32 -#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L] -#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL] -#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH] -#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H] -#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL] -#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH] -#define RIIC3BRL RIIC3.RIICnBRL.UINT32 -#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L] -#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL] -#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH] -#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H] -#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL] -#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH] -#define RIIC3BRH RIIC3.RIICnBRH.UINT32 -#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L] -#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL] -#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH] -#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H] -#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL] -#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH] -#define RIIC3DRT RIIC3.RIICnDRT.UINT32 -#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L] -#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL] -#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH] -#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H] -#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL] -#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH] -#define RIIC3DRR RIIC3.RIICnDRR.UINT32 -#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L] -#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL] -#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH] -#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H] -#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL] -#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH] +#define RIIC0CR1 (RIIC0.RIICnCR1.UINT32) +#define RIIC0CR1L (RIIC0.RIICnCR1.UINT16[R_IO_L]) +#define RIIC0CR1LL (RIIC0.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC0CR1LH (RIIC0.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC0CR1H (RIIC0.RIICnCR1.UINT16[R_IO_H]) +#define RIIC0CR1HL (RIIC0.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC0CR1HH (RIIC0.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC0CR2 (RIIC0.RIICnCR2.UINT32) +#define RIIC0CR2L (RIIC0.RIICnCR2.UINT16[R_IO_L]) +#define RIIC0CR2LL (RIIC0.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC0CR2LH (RIIC0.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC0CR2H (RIIC0.RIICnCR2.UINT16[R_IO_H]) +#define RIIC0CR2HL (RIIC0.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC0CR2HH (RIIC0.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC0MR1 (RIIC0.RIICnMR1.UINT32) +#define RIIC0MR1L (RIIC0.RIICnMR1.UINT16[R_IO_L]) +#define RIIC0MR1LL (RIIC0.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC0MR1LH (RIIC0.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC0MR1H (RIIC0.RIICnMR1.UINT16[R_IO_H]) +#define RIIC0MR1HL (RIIC0.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC0MR1HH (RIIC0.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC0MR2 (RIIC0.RIICnMR2.UINT32) +#define RIIC0MR2L (RIIC0.RIICnMR2.UINT16[R_IO_L]) +#define RIIC0MR2LL (RIIC0.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC0MR2LH (RIIC0.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC0MR2H (RIIC0.RIICnMR2.UINT16[R_IO_H]) +#define RIIC0MR2HL (RIIC0.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC0MR2HH (RIIC0.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC0MR3 (RIIC0.RIICnMR3.UINT32) +#define RIIC0MR3L (RIIC0.RIICnMR3.UINT16[R_IO_L]) +#define RIIC0MR3LL (RIIC0.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC0MR3LH (RIIC0.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC0MR3H (RIIC0.RIICnMR3.UINT16[R_IO_H]) +#define RIIC0MR3HL (RIIC0.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC0MR3HH (RIIC0.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC0FER (RIIC0.RIICnFER.UINT32) +#define RIIC0FERL (RIIC0.RIICnFER.UINT16[R_IO_L]) +#define RIIC0FERLL (RIIC0.RIICnFER.UINT8[R_IO_LL]) +#define RIIC0FERLH (RIIC0.RIICnFER.UINT8[R_IO_LH]) +#define RIIC0FERH (RIIC0.RIICnFER.UINT16[R_IO_H]) +#define RIIC0FERHL (RIIC0.RIICnFER.UINT8[R_IO_HL]) +#define RIIC0FERHH (RIIC0.RIICnFER.UINT8[R_IO_HH]) +#define RIIC0SER (RIIC0.RIICnSER.UINT32) +#define RIIC0SERL (RIIC0.RIICnSER.UINT16[R_IO_L]) +#define RIIC0SERLL (RIIC0.RIICnSER.UINT8[R_IO_LL]) +#define RIIC0SERLH (RIIC0.RIICnSER.UINT8[R_IO_LH]) +#define RIIC0SERH (RIIC0.RIICnSER.UINT16[R_IO_H]) +#define RIIC0SERHL (RIIC0.RIICnSER.UINT8[R_IO_HL]) +#define RIIC0SERHH (RIIC0.RIICnSER.UINT8[R_IO_HH]) +#define RIIC0IER (RIIC0.RIICnIER.UINT32) +#define RIIC0IERL (RIIC0.RIICnIER.UINT16[R_IO_L]) +#define RIIC0IERLL (RIIC0.RIICnIER.UINT8[R_IO_LL]) +#define RIIC0IERLH (RIIC0.RIICnIER.UINT8[R_IO_LH]) +#define RIIC0IERH (RIIC0.RIICnIER.UINT16[R_IO_H]) +#define RIIC0IERHL (RIIC0.RIICnIER.UINT8[R_IO_HL]) +#define RIIC0IERHH (RIIC0.RIICnIER.UINT8[R_IO_HH]) +#define RIIC0SR1 (RIIC0.RIICnSR1.UINT32) +#define RIIC0SR1L (RIIC0.RIICnSR1.UINT16[R_IO_L]) +#define RIIC0SR1LL (RIIC0.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC0SR1LH (RIIC0.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC0SR1H (RIIC0.RIICnSR1.UINT16[R_IO_H]) +#define RIIC0SR1HL (RIIC0.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC0SR1HH (RIIC0.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC0SR2 (RIIC0.RIICnSR2.UINT32) +#define RIIC0SR2L (RIIC0.RIICnSR2.UINT16[R_IO_L]) +#define RIIC0SR2LL (RIIC0.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC0SR2LH (RIIC0.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC0SR2H (RIIC0.RIICnSR2.UINT16[R_IO_H]) +#define RIIC0SR2HL (RIIC0.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC0SR2HH (RIIC0.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC0SAR0 (RIIC0.RIICnSAR0.UINT32) +#define RIIC0SAR0L (RIIC0.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC0SAR0LL (RIIC0.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC0SAR0LH (RIIC0.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC0SAR0H (RIIC0.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC0SAR0HL (RIIC0.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC0SAR0HH (RIIC0.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC0SAR1 (RIIC0.RIICnSAR1.UINT32) +#define RIIC0SAR1L (RIIC0.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC0SAR1LL (RIIC0.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC0SAR1LH (RIIC0.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC0SAR1H (RIIC0.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC0SAR1HL (RIIC0.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC0SAR1HH (RIIC0.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC0SAR2 (RIIC0.RIICnSAR2.UINT32) +#define RIIC0SAR2L (RIIC0.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC0SAR2LL (RIIC0.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC0SAR2LH (RIIC0.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC0SAR2H (RIIC0.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC0SAR2HL (RIIC0.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC0SAR2HH (RIIC0.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC0BRL (RIIC0.RIICnBRL.UINT32) +#define RIIC0BRLL (RIIC0.RIICnBRL.UINT16[R_IO_L]) +#define RIIC0BRLLL (RIIC0.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC0BRLLH (RIIC0.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC0BRLH (RIIC0.RIICnBRL.UINT16[R_IO_H]) +#define RIIC0BRLHL (RIIC0.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC0BRLHH (RIIC0.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC0BRH (RIIC0.RIICnBRH.UINT32) +#define RIIC0BRHL (RIIC0.RIICnBRH.UINT16[R_IO_L]) +#define RIIC0BRHLL (RIIC0.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC0BRHLH (RIIC0.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC0BRHH (RIIC0.RIICnBRH.UINT16[R_IO_H]) +#define RIIC0BRHHL (RIIC0.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC0BRHHH (RIIC0.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC0DRT (RIIC0.RIICnDRT.UINT32) +#define RIIC0DRTL (RIIC0.RIICnDRT.UINT16[R_IO_L]) +#define RIIC0DRTLL (RIIC0.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC0DRTLH (RIIC0.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC0DRTH (RIIC0.RIICnDRT.UINT16[R_IO_H]) +#define RIIC0DRTHL (RIIC0.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC0DRTHH (RIIC0.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC0DRR (RIIC0.RIICnDRR.UINT32) +#define RIIC0DRRL (RIIC0.RIICnDRR.UINT16[R_IO_L]) +#define RIIC0DRRLL (RIIC0.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC0DRRLH (RIIC0.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC0DRRH (RIIC0.RIICnDRR.UINT16[R_IO_H]) +#define RIIC0DRRHL (RIIC0.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC0DRRHH (RIIC0.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC1CR1 (RIIC1.RIICnCR1.UINT32) +#define RIIC1CR1L (RIIC1.RIICnCR1.UINT16[R_IO_L]) +#define RIIC1CR1LL (RIIC1.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC1CR1LH (RIIC1.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC1CR1H (RIIC1.RIICnCR1.UINT16[R_IO_H]) +#define RIIC1CR1HL (RIIC1.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC1CR1HH (RIIC1.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC1CR2 (RIIC1.RIICnCR2.UINT32) +#define RIIC1CR2L (RIIC1.RIICnCR2.UINT16[R_IO_L]) +#define RIIC1CR2LL (RIIC1.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC1CR2LH (RIIC1.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC1CR2H (RIIC1.RIICnCR2.UINT16[R_IO_H]) +#define RIIC1CR2HL (RIIC1.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC1CR2HH (RIIC1.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC1MR1 (RIIC1.RIICnMR1.UINT32) +#define RIIC1MR1L (RIIC1.RIICnMR1.UINT16[R_IO_L]) +#define RIIC1MR1LL (RIIC1.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC1MR1LH (RIIC1.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC1MR1H (RIIC1.RIICnMR1.UINT16[R_IO_H]) +#define RIIC1MR1HL (RIIC1.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC1MR1HH (RIIC1.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC1MR2 (RIIC1.RIICnMR2.UINT32) +#define RIIC1MR2L (RIIC1.RIICnMR2.UINT16[R_IO_L]) +#define RIIC1MR2LL (RIIC1.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC1MR2LH (RIIC1.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC1MR2H (RIIC1.RIICnMR2.UINT16[R_IO_H]) +#define RIIC1MR2HL (RIIC1.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC1MR2HH (RIIC1.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC1MR3 (RIIC1.RIICnMR3.UINT32) +#define RIIC1MR3L (RIIC1.RIICnMR3.UINT16[R_IO_L]) +#define RIIC1MR3LL (RIIC1.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC1MR3LH (RIIC1.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC1MR3H (RIIC1.RIICnMR3.UINT16[R_IO_H]) +#define RIIC1MR3HL (RIIC1.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC1MR3HH (RIIC1.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC1FER (RIIC1.RIICnFER.UINT32) +#define RIIC1FERL (RIIC1.RIICnFER.UINT16[R_IO_L]) +#define RIIC1FERLL (RIIC1.RIICnFER.UINT8[R_IO_LL]) +#define RIIC1FERLH (RIIC1.RIICnFER.UINT8[R_IO_LH]) +#define RIIC1FERH (RIIC1.RIICnFER.UINT16[R_IO_H]) +#define RIIC1FERHL (RIIC1.RIICnFER.UINT8[R_IO_HL]) +#define RIIC1FERHH (RIIC1.RIICnFER.UINT8[R_IO_HH]) +#define RIIC1SER (RIIC1.RIICnSER.UINT32) +#define RIIC1SERL (RIIC1.RIICnSER.UINT16[R_IO_L]) +#define RIIC1SERLL (RIIC1.RIICnSER.UINT8[R_IO_LL]) +#define RIIC1SERLH (RIIC1.RIICnSER.UINT8[R_IO_LH]) +#define RIIC1SERH (RIIC1.RIICnSER.UINT16[R_IO_H]) +#define RIIC1SERHL (RIIC1.RIICnSER.UINT8[R_IO_HL]) +#define RIIC1SERHH (RIIC1.RIICnSER.UINT8[R_IO_HH]) +#define RIIC1IER (RIIC1.RIICnIER.UINT32) +#define RIIC1IERL (RIIC1.RIICnIER.UINT16[R_IO_L]) +#define RIIC1IERLL (RIIC1.RIICnIER.UINT8[R_IO_LL]) +#define RIIC1IERLH (RIIC1.RIICnIER.UINT8[R_IO_LH]) +#define RIIC1IERH (RIIC1.RIICnIER.UINT16[R_IO_H]) +#define RIIC1IERHL (RIIC1.RIICnIER.UINT8[R_IO_HL]) +#define RIIC1IERHH (RIIC1.RIICnIER.UINT8[R_IO_HH]) +#define RIIC1SR1 (RIIC1.RIICnSR1.UINT32) +#define RIIC1SR1L (RIIC1.RIICnSR1.UINT16[R_IO_L]) +#define RIIC1SR1LL (RIIC1.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC1SR1LH (RIIC1.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC1SR1H (RIIC1.RIICnSR1.UINT16[R_IO_H]) +#define RIIC1SR1HL (RIIC1.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC1SR1HH (RIIC1.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC1SR2 (RIIC1.RIICnSR2.UINT32) +#define RIIC1SR2L (RIIC1.RIICnSR2.UINT16[R_IO_L]) +#define RIIC1SR2LL (RIIC1.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC1SR2LH (RIIC1.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC1SR2H (RIIC1.RIICnSR2.UINT16[R_IO_H]) +#define RIIC1SR2HL (RIIC1.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC1SR2HH (RIIC1.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC1SAR0 (RIIC1.RIICnSAR0.UINT32) +#define RIIC1SAR0L (RIIC1.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC1SAR0LL (RIIC1.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC1SAR0LH (RIIC1.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC1SAR0H (RIIC1.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC1SAR0HL (RIIC1.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC1SAR0HH (RIIC1.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC1SAR1 (RIIC1.RIICnSAR1.UINT32) +#define RIIC1SAR1L (RIIC1.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC1SAR1LL (RIIC1.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC1SAR1LH (RIIC1.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC1SAR1H (RIIC1.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC1SAR1HL (RIIC1.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC1SAR1HH (RIIC1.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC1SAR2 (RIIC1.RIICnSAR2.UINT32) +#define RIIC1SAR2L (RIIC1.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC1SAR2LL (RIIC1.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC1SAR2LH (RIIC1.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC1SAR2H (RIIC1.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC1SAR2HL (RIIC1.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC1SAR2HH (RIIC1.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC1BRL (RIIC1.RIICnBRL.UINT32) +#define RIIC1BRLL (RIIC1.RIICnBRL.UINT16[R_IO_L]) +#define RIIC1BRLLL (RIIC1.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC1BRLLH (RIIC1.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC1BRLH (RIIC1.RIICnBRL.UINT16[R_IO_H]) +#define RIIC1BRLHL (RIIC1.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC1BRLHH (RIIC1.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC1BRH (RIIC1.RIICnBRH.UINT32) +#define RIIC1BRHL (RIIC1.RIICnBRH.UINT16[R_IO_L]) +#define RIIC1BRHLL (RIIC1.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC1BRHLH (RIIC1.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC1BRHH (RIIC1.RIICnBRH.UINT16[R_IO_H]) +#define RIIC1BRHHL (RIIC1.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC1BRHHH (RIIC1.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC1DRT (RIIC1.RIICnDRT.UINT32) +#define RIIC1DRTL (RIIC1.RIICnDRT.UINT16[R_IO_L]) +#define RIIC1DRTLL (RIIC1.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC1DRTLH (RIIC1.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC1DRTH (RIIC1.RIICnDRT.UINT16[R_IO_H]) +#define RIIC1DRTHL (RIIC1.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC1DRTHH (RIIC1.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC1DRR (RIIC1.RIICnDRR.UINT32) +#define RIIC1DRRL (RIIC1.RIICnDRR.UINT16[R_IO_L]) +#define RIIC1DRRLL (RIIC1.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC1DRRLH (RIIC1.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC1DRRH (RIIC1.RIICnDRR.UINT16[R_IO_H]) +#define RIIC1DRRHL (RIIC1.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC1DRRHH (RIIC1.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC2CR1 (RIIC2.RIICnCR1.UINT32) +#define RIIC2CR1L (RIIC2.RIICnCR1.UINT16[R_IO_L]) +#define RIIC2CR1LL (RIIC2.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC2CR1LH (RIIC2.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC2CR1H (RIIC2.RIICnCR1.UINT16[R_IO_H]) +#define RIIC2CR1HL (RIIC2.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC2CR1HH (RIIC2.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC2CR2 (RIIC2.RIICnCR2.UINT32) +#define RIIC2CR2L (RIIC2.RIICnCR2.UINT16[R_IO_L]) +#define RIIC2CR2LL (RIIC2.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC2CR2LH (RIIC2.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC2CR2H (RIIC2.RIICnCR2.UINT16[R_IO_H]) +#define RIIC2CR2HL (RIIC2.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC2CR2HH (RIIC2.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC2MR1 (RIIC2.RIICnMR1.UINT32) +#define RIIC2MR1L (RIIC2.RIICnMR1.UINT16[R_IO_L]) +#define RIIC2MR1LL (RIIC2.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC2MR1LH (RIIC2.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC2MR1H (RIIC2.RIICnMR1.UINT16[R_IO_H]) +#define RIIC2MR1HL (RIIC2.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC2MR1HH (RIIC2.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC2MR2 (RIIC2.RIICnMR2.UINT32) +#define RIIC2MR2L (RIIC2.RIICnMR2.UINT16[R_IO_L]) +#define RIIC2MR2LL (RIIC2.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC2MR2LH (RIIC2.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC2MR2H (RIIC2.RIICnMR2.UINT16[R_IO_H]) +#define RIIC2MR2HL (RIIC2.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC2MR2HH (RIIC2.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC2MR3 (RIIC2.RIICnMR3.UINT32) +#define RIIC2MR3L (RIIC2.RIICnMR3.UINT16[R_IO_L]) +#define RIIC2MR3LL (RIIC2.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC2MR3LH (RIIC2.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC2MR3H (RIIC2.RIICnMR3.UINT16[R_IO_H]) +#define RIIC2MR3HL (RIIC2.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC2MR3HH (RIIC2.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC2FER (RIIC2.RIICnFER.UINT32) +#define RIIC2FERL (RIIC2.RIICnFER.UINT16[R_IO_L]) +#define RIIC2FERLL (RIIC2.RIICnFER.UINT8[R_IO_LL]) +#define RIIC2FERLH (RIIC2.RIICnFER.UINT8[R_IO_LH]) +#define RIIC2FERH (RIIC2.RIICnFER.UINT16[R_IO_H]) +#define RIIC2FERHL (RIIC2.RIICnFER.UINT8[R_IO_HL]) +#define RIIC2FERHH (RIIC2.RIICnFER.UINT8[R_IO_HH]) +#define RIIC2SER (RIIC2.RIICnSER.UINT32) +#define RIIC2SERL (RIIC2.RIICnSER.UINT16[R_IO_L]) +#define RIIC2SERLL (RIIC2.RIICnSER.UINT8[R_IO_LL]) +#define RIIC2SERLH (RIIC2.RIICnSER.UINT8[R_IO_LH]) +#define RIIC2SERH (RIIC2.RIICnSER.UINT16[R_IO_H]) +#define RIIC2SERHL (RIIC2.RIICnSER.UINT8[R_IO_HL]) +#define RIIC2SERHH (RIIC2.RIICnSER.UINT8[R_IO_HH]) +#define RIIC2IER (RIIC2.RIICnIER.UINT32) +#define RIIC2IERL (RIIC2.RIICnIER.UINT16[R_IO_L]) +#define RIIC2IERLL (RIIC2.RIICnIER.UINT8[R_IO_LL]) +#define RIIC2IERLH (RIIC2.RIICnIER.UINT8[R_IO_LH]) +#define RIIC2IERH (RIIC2.RIICnIER.UINT16[R_IO_H]) +#define RIIC2IERHL (RIIC2.RIICnIER.UINT8[R_IO_HL]) +#define RIIC2IERHH (RIIC2.RIICnIER.UINT8[R_IO_HH]) +#define RIIC2SR1 (RIIC2.RIICnSR1.UINT32) +#define RIIC2SR1L (RIIC2.RIICnSR1.UINT16[R_IO_L]) +#define RIIC2SR1LL (RIIC2.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC2SR1LH (RIIC2.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC2SR1H (RIIC2.RIICnSR1.UINT16[R_IO_H]) +#define RIIC2SR1HL (RIIC2.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC2SR1HH (RIIC2.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC2SR2 (RIIC2.RIICnSR2.UINT32) +#define RIIC2SR2L (RIIC2.RIICnSR2.UINT16[R_IO_L]) +#define RIIC2SR2LL (RIIC2.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC2SR2LH (RIIC2.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC2SR2H (RIIC2.RIICnSR2.UINT16[R_IO_H]) +#define RIIC2SR2HL (RIIC2.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC2SR2HH (RIIC2.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC2SAR0 (RIIC2.RIICnSAR0.UINT32) +#define RIIC2SAR0L (RIIC2.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC2SAR0LL (RIIC2.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC2SAR0LH (RIIC2.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC2SAR0H (RIIC2.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC2SAR0HL (RIIC2.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC2SAR0HH (RIIC2.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC2SAR1 (RIIC2.RIICnSAR1.UINT32) +#define RIIC2SAR1L (RIIC2.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC2SAR1LL (RIIC2.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC2SAR1LH (RIIC2.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC2SAR1H (RIIC2.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC2SAR1HL (RIIC2.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC2SAR1HH (RIIC2.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC2SAR2 (RIIC2.RIICnSAR2.UINT32) +#define RIIC2SAR2L (RIIC2.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC2SAR2LL (RIIC2.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC2SAR2LH (RIIC2.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC2SAR2H (RIIC2.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC2SAR2HL (RIIC2.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC2SAR2HH (RIIC2.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC2BRL (RIIC2.RIICnBRL.UINT32) +#define RIIC2BRLL (RIIC2.RIICnBRL.UINT16[R_IO_L]) +#define RIIC2BRLLL (RIIC2.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC2BRLLH (RIIC2.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC2BRLH (RIIC2.RIICnBRL.UINT16[R_IO_H]) +#define RIIC2BRLHL (RIIC2.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC2BRLHH (RIIC2.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC2BRH (RIIC2.RIICnBRH.UINT32) +#define RIIC2BRHL (RIIC2.RIICnBRH.UINT16[R_IO_L]) +#define RIIC2BRHLL (RIIC2.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC2BRHLH (RIIC2.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC2BRHH (RIIC2.RIICnBRH.UINT16[R_IO_H]) +#define RIIC2BRHHL (RIIC2.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC2BRHHH (RIIC2.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC2DRT (RIIC2.RIICnDRT.UINT32) +#define RIIC2DRTL (RIIC2.RIICnDRT.UINT16[R_IO_L]) +#define RIIC2DRTLL (RIIC2.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC2DRTLH (RIIC2.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC2DRTH (RIIC2.RIICnDRT.UINT16[R_IO_H]) +#define RIIC2DRTHL (RIIC2.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC2DRTHH (RIIC2.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC2DRR (RIIC2.RIICnDRR.UINT32) +#define RIIC2DRRL (RIIC2.RIICnDRR.UINT16[R_IO_L]) +#define RIIC2DRRLL (RIIC2.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC2DRRLH (RIIC2.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC2DRRH (RIIC2.RIICnDRR.UINT16[R_IO_H]) +#define RIIC2DRRHL (RIIC2.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC2DRRHH (RIIC2.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC3CR1 (RIIC3.RIICnCR1.UINT32) +#define RIIC3CR1L (RIIC3.RIICnCR1.UINT16[R_IO_L]) +#define RIIC3CR1LL (RIIC3.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC3CR1LH (RIIC3.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC3CR1H (RIIC3.RIICnCR1.UINT16[R_IO_H]) +#define RIIC3CR1HL (RIIC3.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC3CR1HH (RIIC3.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC3CR2 (RIIC3.RIICnCR2.UINT32) +#define RIIC3CR2L (RIIC3.RIICnCR2.UINT16[R_IO_L]) +#define RIIC3CR2LL (RIIC3.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC3CR2LH (RIIC3.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC3CR2H (RIIC3.RIICnCR2.UINT16[R_IO_H]) +#define RIIC3CR2HL (RIIC3.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC3CR2HH (RIIC3.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC3MR1 (RIIC3.RIICnMR1.UINT32) +#define RIIC3MR1L (RIIC3.RIICnMR1.UINT16[R_IO_L]) +#define RIIC3MR1LL (RIIC3.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC3MR1LH (RIIC3.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC3MR1H (RIIC3.RIICnMR1.UINT16[R_IO_H]) +#define RIIC3MR1HL (RIIC3.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC3MR1HH (RIIC3.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC3MR2 (RIIC3.RIICnMR2.UINT32) +#define RIIC3MR2L (RIIC3.RIICnMR2.UINT16[R_IO_L]) +#define RIIC3MR2LL (RIIC3.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC3MR2LH (RIIC3.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC3MR2H (RIIC3.RIICnMR2.UINT16[R_IO_H]) +#define RIIC3MR2HL (RIIC3.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC3MR2HH (RIIC3.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC3MR3 (RIIC3.RIICnMR3.UINT32) +#define RIIC3MR3L (RIIC3.RIICnMR3.UINT16[R_IO_L]) +#define RIIC3MR3LL (RIIC3.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC3MR3LH (RIIC3.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC3MR3H (RIIC3.RIICnMR3.UINT16[R_IO_H]) +#define RIIC3MR3HL (RIIC3.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC3MR3HH (RIIC3.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC3FER (RIIC3.RIICnFER.UINT32) +#define RIIC3FERL (RIIC3.RIICnFER.UINT16[R_IO_L]) +#define RIIC3FERLL (RIIC3.RIICnFER.UINT8[R_IO_LL]) +#define RIIC3FERLH (RIIC3.RIICnFER.UINT8[R_IO_LH]) +#define RIIC3FERH (RIIC3.RIICnFER.UINT16[R_IO_H]) +#define RIIC3FERHL (RIIC3.RIICnFER.UINT8[R_IO_HL]) +#define RIIC3FERHH (RIIC3.RIICnFER.UINT8[R_IO_HH]) +#define RIIC3SER (RIIC3.RIICnSER.UINT32) +#define RIIC3SERL (RIIC3.RIICnSER.UINT16[R_IO_L]) +#define RIIC3SERLL (RIIC3.RIICnSER.UINT8[R_IO_LL]) +#define RIIC3SERLH (RIIC3.RIICnSER.UINT8[R_IO_LH]) +#define RIIC3SERH (RIIC3.RIICnSER.UINT16[R_IO_H]) +#define RIIC3SERHL (RIIC3.RIICnSER.UINT8[R_IO_HL]) +#define RIIC3SERHH (RIIC3.RIICnSER.UINT8[R_IO_HH]) +#define RIIC3IER (RIIC3.RIICnIER.UINT32) +#define RIIC3IERL (RIIC3.RIICnIER.UINT16[R_IO_L]) +#define RIIC3IERLL (RIIC3.RIICnIER.UINT8[R_IO_LL]) +#define RIIC3IERLH (RIIC3.RIICnIER.UINT8[R_IO_LH]) +#define RIIC3IERH (RIIC3.RIICnIER.UINT16[R_IO_H]) +#define RIIC3IERHL (RIIC3.RIICnIER.UINT8[R_IO_HL]) +#define RIIC3IERHH (RIIC3.RIICnIER.UINT8[R_IO_HH]) +#define RIIC3SR1 (RIIC3.RIICnSR1.UINT32) +#define RIIC3SR1L (RIIC3.RIICnSR1.UINT16[R_IO_L]) +#define RIIC3SR1LL (RIIC3.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC3SR1LH (RIIC3.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC3SR1H (RIIC3.RIICnSR1.UINT16[R_IO_H]) +#define RIIC3SR1HL (RIIC3.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC3SR1HH (RIIC3.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC3SR2 (RIIC3.RIICnSR2.UINT32) +#define RIIC3SR2L (RIIC3.RIICnSR2.UINT16[R_IO_L]) +#define RIIC3SR2LL (RIIC3.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC3SR2LH (RIIC3.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC3SR2H (RIIC3.RIICnSR2.UINT16[R_IO_H]) +#define RIIC3SR2HL (RIIC3.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC3SR2HH (RIIC3.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC3SAR0 (RIIC3.RIICnSAR0.UINT32) +#define RIIC3SAR0L (RIIC3.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC3SAR0LL (RIIC3.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC3SAR0LH (RIIC3.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC3SAR0H (RIIC3.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC3SAR0HL (RIIC3.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC3SAR0HH (RIIC3.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC3SAR1 (RIIC3.RIICnSAR1.UINT32) +#define RIIC3SAR1L (RIIC3.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC3SAR1LL (RIIC3.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC3SAR1LH (RIIC3.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC3SAR1H (RIIC3.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC3SAR1HL (RIIC3.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC3SAR1HH (RIIC3.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC3SAR2 (RIIC3.RIICnSAR2.UINT32) +#define RIIC3SAR2L (RIIC3.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC3SAR2LL (RIIC3.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC3SAR2LH (RIIC3.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC3SAR2H (RIIC3.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC3SAR2HL (RIIC3.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC3SAR2HH (RIIC3.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC3BRL (RIIC3.RIICnBRL.UINT32) +#define RIIC3BRLL (RIIC3.RIICnBRL.UINT16[R_IO_L]) +#define RIIC3BRLLL (RIIC3.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC3BRLLH (RIIC3.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC3BRLH (RIIC3.RIICnBRL.UINT16[R_IO_H]) +#define RIIC3BRLHL (RIIC3.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC3BRLHH (RIIC3.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC3BRH (RIIC3.RIICnBRH.UINT32) +#define RIIC3BRHL (RIIC3.RIICnBRH.UINT16[R_IO_L]) +#define RIIC3BRHLL (RIIC3.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC3BRHLH (RIIC3.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC3BRHH (RIIC3.RIICnBRH.UINT16[R_IO_H]) +#define RIIC3BRHHL (RIIC3.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC3BRHHH (RIIC3.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC3DRT (RIIC3.RIICnDRT.UINT32) +#define RIIC3DRTL (RIIC3.RIICnDRT.UINT16[R_IO_L]) +#define RIIC3DRTLL (RIIC3.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC3DRTLH (RIIC3.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC3DRTH (RIIC3.RIICnDRT.UINT16[R_IO_H]) +#define RIIC3DRTHL (RIIC3.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC3DRTHH (RIIC3.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC3DRR (RIIC3.RIICnDRR.UINT32) +#define RIIC3DRRL (RIIC3.RIICnDRR.UINT16[R_IO_L]) +#define RIIC3DRRLL (RIIC3.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC3DRRLH (RIIC3.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC3DRRH (RIIC3.RIICnDRR.UINT16[R_IO_H]) +#define RIIC3DRRHL (RIIC3.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC3DRRHH (RIIC3.RIICnDRR.UINT8[R_IO_HH]) + +#define RIICnCRm_COUNT (2) +#define RIICnMRm_COUNT (3) +#define RIICnSRm_COUNT (2) +#define RIICnSARm_COUNT (3) + + +typedef struct st_riic +{ + /* RIIC */ + +/* #define RIICnCRm_COUNT (2) */ + union iodefine_reg32_t RIICnCR1; /* RIICnCR1 */ + union iodefine_reg32_t RIICnCR2; /* RIICnCR2 */ + +/* #define RIICnMRm_COUNT (3) */ + union iodefine_reg32_t RIICnMR1; /* RIICnMR1 */ + union iodefine_reg32_t RIICnMR2; /* RIICnMR2 */ + union iodefine_reg32_t RIICnMR3; /* RIICnMR3 */ + union iodefine_reg32_t RIICnFER; /* RIICnFER */ + union iodefine_reg32_t RIICnSER; /* RIICnSER */ + union iodefine_reg32_t RIICnIER; /* RIICnIER */ + +/* #define RIICnSRm_COUNT (2) */ + union iodefine_reg32_t RIICnSR1; /* RIICnSR1 */ + union iodefine_reg32_t RIICnSR2; /* RIICnSR2 */ + +/* #define RIICnSARm_COUNT (3) */ + union iodefine_reg32_t RIICnSAR0; /* RIICnSAR0 */ + union iodefine_reg32_t RIICnSAR1; /* RIICnSAR1 */ + union iodefine_reg32_t RIICnSAR2; /* RIICnSAR2 */ + union iodefine_reg32_t RIICnBRL; /* RIICnBRL */ + union iodefine_reg32_t RIICnBRH; /* RIICnBRH */ + union iodefine_reg32_t RIICnDRT; /* RIICnDRT */ + union iodefine_reg32_t RIICnDRR; /* RIICnDRR */ + +} r_io_riic_t; + + +/* Channel array defines of RIIC (2)*/ +#ifdef DECLARE_RIIC_CHANNELS +volatile struct st_riic* RIIC[ RIIC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RIIC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RIIC_CHANNELS */ +/* End of channel array defines of RIIC (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h index cfcfda568d..7d6a207693 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h @@ -18,30 +18,104 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : romdec_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef ROMDEC_IODEFINE_H #define ROMDEC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_romdec -{ /* ROMDEC */ +#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */ + + +#define ROMDECCROMEN (ROMDEC.CROMEN) +#define ROMDECCROMSY0 (ROMDEC.CROMSY0) +#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0) +#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1) +#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3) +#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4) +#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5) +#define ROMDECCROMST0 (ROMDEC.CROMST0) +#define ROMDECCROMST1 (ROMDEC.CROMST1) +#define ROMDECCROMST3 (ROMDEC.CROMST3) +#define ROMDECCROMST4 (ROMDEC.CROMST4) +#define ROMDECCROMST5 (ROMDEC.CROMST5) +#define ROMDECCROMST6 (ROMDEC.CROMST6) +#define ROMDECCBUFST0 (ROMDEC.CBUFST0) +#define ROMDECCBUFST1 (ROMDEC.CBUFST1) +#define ROMDECCBUFST2 (ROMDEC.CBUFST2) +#define ROMDECHEAD00 (ROMDEC.HEAD00) +#define ROMDECHEAD01 (ROMDEC.HEAD01) +#define ROMDECHEAD02 (ROMDEC.HEAD02) +#define ROMDECHEAD03 (ROMDEC.HEAD03) +#define ROMDECSHEAD00 (ROMDEC.SHEAD00) +#define ROMDECSHEAD01 (ROMDEC.SHEAD01) +#define ROMDECSHEAD02 (ROMDEC.SHEAD02) +#define ROMDECSHEAD03 (ROMDEC.SHEAD03) +#define ROMDECSHEAD04 (ROMDEC.SHEAD04) +#define ROMDECSHEAD05 (ROMDEC.SHEAD05) +#define ROMDECSHEAD06 (ROMDEC.SHEAD06) +#define ROMDECSHEAD07 (ROMDEC.SHEAD07) +#define ROMDECHEAD20 (ROMDEC.HEAD20) +#define ROMDECHEAD21 (ROMDEC.HEAD21) +#define ROMDECHEAD22 (ROMDEC.HEAD22) +#define ROMDECHEAD23 (ROMDEC.HEAD23) +#define ROMDECSHEAD20 (ROMDEC.SHEAD20) +#define ROMDECSHEAD21 (ROMDEC.SHEAD21) +#define ROMDECSHEAD22 (ROMDEC.SHEAD22) +#define ROMDECSHEAD23 (ROMDEC.SHEAD23) +#define ROMDECSHEAD24 (ROMDEC.SHEAD24) +#define ROMDECSHEAD25 (ROMDEC.SHEAD25) +#define ROMDECSHEAD26 (ROMDEC.SHEAD26) +#define ROMDECSHEAD27 (ROMDEC.SHEAD27) +#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0) +#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1) +#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2) +#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3) +#define ROMDECCROMST0M (ROMDEC.CROMST0M) +#define ROMDECROMDECRST (ROMDEC.ROMDECRST) +#define ROMDECRSTSTAT (ROMDEC.RSTSTAT) +#define ROMDECSSI (ROMDEC.SSI) +#define ROMDECINTHOLD (ROMDEC.INTHOLD) +#define ROMDECINHINT (ROMDEC.INHINT) +#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0) +#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2) +#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0) + +#define ROMDEC_CROMCTL0_COUNT (2) +#define ROMDEC_CROMST0_COUNT (2) +#define ROMDEC_CBUFST0_COUNT (3) +#define ROMDEC_HEAD00_COUNT (4) +#define ROMDEC_SHEAD00_COUNT (8) +#define ROMDEC_HEAD20_COUNT (4) +#define ROMDEC_SHEAD20_COUNT (8) +#define ROMDEC_CBUFCTL0_COUNT (4) +#define ROMDEC_STRMDIN0_COUNT (2) + + +typedef struct st_romdec +{ + /* ROMDEC */ volatile uint8_t CROMEN; /* CROMEN */ volatile uint8_t CROMSY0; /* CROMSY0 */ -#define ROMDEC_CROMCTL0_COUNT 2 + +/* #define ROMDEC_CROMCTL0_COUNT (2) */ volatile uint8_t CROMCTL0; /* CROMCTL0 */ volatile uint8_t CROMCTL1; /* CROMCTL1 */ volatile uint8_t dummy23[1]; /* */ volatile uint8_t CROMCTL3; /* CROMCTL3 */ volatile uint8_t CROMCTL4; /* CROMCTL4 */ volatile uint8_t CROMCTL5; /* CROMCTL5 */ -#define ROMDEC_CROMST0_COUNT 2 + +/* #define ROMDEC_CROMST0_COUNT (2) */ volatile uint8_t CROMST0; /* CROMST0 */ volatile uint8_t CROMST1; /* CROMST1 */ volatile uint8_t dummy24[1]; /* */ @@ -50,17 +124,20 @@ struct st_romdec volatile uint8_t CROMST5; /* CROMST5 */ volatile uint8_t CROMST6; /* CROMST6 */ volatile uint8_t dummy25[5]; /* */ -#define ROMDEC_CBUFST0_COUNT 3 + +/* #define ROMDEC_CBUFST0_COUNT (3) */ volatile uint8_t CBUFST0; /* CBUFST0 */ volatile uint8_t CBUFST1; /* CBUFST1 */ volatile uint8_t CBUFST2; /* CBUFST2 */ volatile uint8_t dummy26[1]; /* */ -#define ROMDEC_HEAD00_COUNT 4 + +/* #define ROMDEC_HEAD00_COUNT (4) */ volatile uint8_t HEAD00; /* HEAD00 */ volatile uint8_t HEAD01; /* HEAD01 */ volatile uint8_t HEAD02; /* HEAD02 */ volatile uint8_t HEAD03; /* HEAD03 */ -#define ROMDEC_SHEAD00_COUNT 8 + +/* #define ROMDEC_SHEAD00_COUNT (8) */ volatile uint8_t SHEAD00; /* SHEAD00 */ volatile uint8_t SHEAD01; /* SHEAD01 */ volatile uint8_t SHEAD02; /* SHEAD02 */ @@ -69,12 +146,14 @@ struct st_romdec volatile uint8_t SHEAD05; /* SHEAD05 */ volatile uint8_t SHEAD06; /* SHEAD06 */ volatile uint8_t SHEAD07; /* SHEAD07 */ -#define ROMDEC_HEAD20_COUNT 4 + +/* #define ROMDEC_HEAD20_COUNT (4) */ volatile uint8_t HEAD20; /* HEAD20 */ volatile uint8_t HEAD21; /* HEAD21 */ volatile uint8_t HEAD22; /* HEAD22 */ volatile uint8_t HEAD23; /* HEAD23 */ -#define ROMDEC_SHEAD20_COUNT 8 + +/* #define ROMDEC_SHEAD20_COUNT (8) */ volatile uint8_t SHEAD20; /* SHEAD20 */ volatile uint8_t SHEAD21; /* SHEAD21 */ volatile uint8_t SHEAD22; /* SHEAD22 */ @@ -84,7 +163,8 @@ struct st_romdec volatile uint8_t SHEAD26; /* SHEAD26 */ volatile uint8_t SHEAD27; /* SHEAD27 */ volatile uint8_t dummy27[16]; /* */ -#define ROMDEC_CBUFCTL0_COUNT 4 + +/* #define ROMDEC_CBUFCTL0_COUNT (4) */ volatile uint8_t CBUFCTL0; /* CBUFCTL0 */ volatile uint8_t CBUFCTL1; /* CBUFCTL1 */ volatile uint8_t CBUFCTL2; /* CBUFCTL2 */ @@ -99,68 +179,16 @@ struct st_romdec volatile uint8_t INTHOLD; /* INTHOLD */ volatile uint8_t INHINT; /* INHINT */ volatile uint8_t dummy31[246]; /* */ -#define ROMDEC_STRMDIN0_COUNT 2 + +/* #define ROMDEC_STRMDIN0_COUNT (2) */ volatile uint16_t STRMDIN0; /* STRMDIN0 */ volatile uint16_t STRMDIN2; /* STRMDIN2 */ volatile uint16_t STRMDOUT0; /* STRMDOUT0 */ -}; +} r_io_romdec_t; -#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */ - - -#define ROMDECCROMEN ROMDEC.CROMEN -#define ROMDECCROMSY0 ROMDEC.CROMSY0 -#define ROMDECCROMCTL0 ROMDEC.CROMCTL0 -#define ROMDECCROMCTL1 ROMDEC.CROMCTL1 -#define ROMDECCROMCTL3 ROMDEC.CROMCTL3 -#define ROMDECCROMCTL4 ROMDEC.CROMCTL4 -#define ROMDECCROMCTL5 ROMDEC.CROMCTL5 -#define ROMDECCROMST0 ROMDEC.CROMST0 -#define ROMDECCROMST1 ROMDEC.CROMST1 -#define ROMDECCROMST3 ROMDEC.CROMST3 -#define ROMDECCROMST4 ROMDEC.CROMST4 -#define ROMDECCROMST5 ROMDEC.CROMST5 -#define ROMDECCROMST6 ROMDEC.CROMST6 -#define ROMDECCBUFST0 ROMDEC.CBUFST0 -#define ROMDECCBUFST1 ROMDEC.CBUFST1 -#define ROMDECCBUFST2 ROMDEC.CBUFST2 -#define ROMDECHEAD00 ROMDEC.HEAD00 -#define ROMDECHEAD01 ROMDEC.HEAD01 -#define ROMDECHEAD02 ROMDEC.HEAD02 -#define ROMDECHEAD03 ROMDEC.HEAD03 -#define ROMDECSHEAD00 ROMDEC.SHEAD00 -#define ROMDECSHEAD01 ROMDEC.SHEAD01 -#define ROMDECSHEAD02 ROMDEC.SHEAD02 -#define ROMDECSHEAD03 ROMDEC.SHEAD03 -#define ROMDECSHEAD04 ROMDEC.SHEAD04 -#define ROMDECSHEAD05 ROMDEC.SHEAD05 -#define ROMDECSHEAD06 ROMDEC.SHEAD06 -#define ROMDECSHEAD07 ROMDEC.SHEAD07 -#define ROMDECHEAD20 ROMDEC.HEAD20 -#define ROMDECHEAD21 ROMDEC.HEAD21 -#define ROMDECHEAD22 ROMDEC.HEAD22 -#define ROMDECHEAD23 ROMDEC.HEAD23 -#define ROMDECSHEAD20 ROMDEC.SHEAD20 -#define ROMDECSHEAD21 ROMDEC.SHEAD21 -#define ROMDECSHEAD22 ROMDEC.SHEAD22 -#define ROMDECSHEAD23 ROMDEC.SHEAD23 -#define ROMDECSHEAD24 ROMDEC.SHEAD24 -#define ROMDECSHEAD25 ROMDEC.SHEAD25 -#define ROMDECSHEAD26 ROMDEC.SHEAD26 -#define ROMDECSHEAD27 ROMDEC.SHEAD27 -#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0 -#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1 -#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2 -#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3 -#define ROMDECCROMST0M ROMDEC.CROMST0M -#define ROMDECROMDECRST ROMDEC.ROMDECRST -#define ROMDECRSTSTAT ROMDEC.RSTSTAT -#define ROMDECSSI ROMDEC.SSI -#define ROMDECINTHOLD ROMDEC.INTHOLD -#define ROMDECINHINT ROMDEC.INHINT -#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0 -#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2 -#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h index 1698f027cc..38bc282098 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h @@ -18,1886 +18,30 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : rscan0_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef RSCAN0_IODEFINE_H #define RSCAN0_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ /* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_rscan0 -{ /* RSCAN0 */ -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C0CFG; /* C0CFG */ - union iodefine_reg32_t C0CTR; /* C0CTR */ - union iodefine_reg32_t C0STS; /* C0STS */ - union iodefine_reg32_t C0ERFL; /* C0ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C1CFG; /* C1CFG */ - union iodefine_reg32_t C1CTR; /* C1CTR */ - union iodefine_reg32_t C1STS; /* C1STS */ - union iodefine_reg32_t C1ERFL; /* C1ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C2CFG; /* C2CFG */ - union iodefine_reg32_t C2CTR; /* C2CTR */ - union iodefine_reg32_t C2STS; /* C2STS */ - union iodefine_reg32_t C2ERFL; /* C2ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C3CFG; /* C3CFG */ - union iodefine_reg32_t C3CTR; /* C3CTR */ - union iodefine_reg32_t C3STS; /* C3STS */ - union iodefine_reg32_t C3ERFL; /* C3ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C4CFG; /* C4CFG */ - union iodefine_reg32_t C4CTR; /* C4CTR */ - union iodefine_reg32_t C4STS; /* C4STS */ - union iodefine_reg32_t C4ERFL; /* C4ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - - volatile uint8_t dummy159[52]; /* */ - union iodefine_reg32_t GCFG; /* GCFG */ - union iodefine_reg32_t GCTR; /* GCTR */ - union iodefine_reg32_t GSTS; /* GSTS */ - union iodefine_reg32_t GERFL; /* GERFL */ - union iodefine_reg32_16_t GTSC; /* GTSC */ - union iodefine_reg32_t GAFLECTR; /* GAFLECTR */ -#define RSCAN0_GAFLCFG0_COUNT 2 - union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */ - union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */ - union iodefine_reg32_t RMNB; /* RMNB */ -#define RSCAN0_RMND0_COUNT 3 - union iodefine_reg32_t RMND0; /* RMND0 */ - union iodefine_reg32_t RMND1; /* RMND1 */ - union iodefine_reg32_t RMND2; /* RMND2 */ - - volatile uint8_t dummy160[4]; /* */ -#define RSCAN0_RFCC0_COUNT 8 - union iodefine_reg32_t RFCC0; /* RFCC0 */ - union iodefine_reg32_t RFCC1; /* RFCC1 */ - union iodefine_reg32_t RFCC2; /* RFCC2 */ - union iodefine_reg32_t RFCC3; /* RFCC3 */ - union iodefine_reg32_t RFCC4; /* RFCC4 */ - union iodefine_reg32_t RFCC5; /* RFCC5 */ - union iodefine_reg32_t RFCC6; /* RFCC6 */ - union iodefine_reg32_t RFCC7; /* RFCC7 */ -#define RSCAN0_RFSTS0_COUNT 8 - union iodefine_reg32_t RFSTS0; /* RFSTS0 */ - union iodefine_reg32_t RFSTS1; /* RFSTS1 */ - union iodefine_reg32_t RFSTS2; /* RFSTS2 */ - union iodefine_reg32_t RFSTS3; /* RFSTS3 */ - union iodefine_reg32_t RFSTS4; /* RFSTS4 */ - union iodefine_reg32_t RFSTS5; /* RFSTS5 */ - union iodefine_reg32_t RFSTS6; /* RFSTS6 */ - union iodefine_reg32_t RFSTS7; /* RFSTS7 */ -#define RSCAN0_RFPCTR0_COUNT 8 - union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */ - union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */ - union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */ - union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */ - union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */ - union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */ - union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */ - union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */ -#define RSCAN0_CFCC0_COUNT 15 - union iodefine_reg32_t CFCC0; /* CFCC0 */ - union iodefine_reg32_t CFCC1; /* CFCC1 */ - union iodefine_reg32_t CFCC2; /* CFCC2 */ - union iodefine_reg32_t CFCC3; /* CFCC3 */ - union iodefine_reg32_t CFCC4; /* CFCC4 */ - union iodefine_reg32_t CFCC5; /* CFCC5 */ - union iodefine_reg32_t CFCC6; /* CFCC6 */ - union iodefine_reg32_t CFCC7; /* CFCC7 */ - union iodefine_reg32_t CFCC8; /* CFCC8 */ - union iodefine_reg32_t CFCC9; /* CFCC9 */ - union iodefine_reg32_t CFCC10; /* CFCC10 */ - union iodefine_reg32_t CFCC11; /* CFCC11 */ - union iodefine_reg32_t CFCC12; /* CFCC12 */ - union iodefine_reg32_t CFCC13; /* CFCC13 */ - union iodefine_reg32_t CFCC14; /* CFCC14 */ - - volatile uint8_t dummy161[36]; /* */ -#define RSCAN0_CFSTS0_COUNT 15 - union iodefine_reg32_t CFSTS0; /* CFSTS0 */ - union iodefine_reg32_t CFSTS1; /* CFSTS1 */ - union iodefine_reg32_t CFSTS2; /* CFSTS2 */ - union iodefine_reg32_t CFSTS3; /* CFSTS3 */ - union iodefine_reg32_t CFSTS4; /* CFSTS4 */ - union iodefine_reg32_t CFSTS5; /* CFSTS5 */ - union iodefine_reg32_t CFSTS6; /* CFSTS6 */ - union iodefine_reg32_t CFSTS7; /* CFSTS7 */ - union iodefine_reg32_t CFSTS8; /* CFSTS8 */ - union iodefine_reg32_t CFSTS9; /* CFSTS9 */ - union iodefine_reg32_t CFSTS10; /* CFSTS10 */ - union iodefine_reg32_t CFSTS11; /* CFSTS11 */ - union iodefine_reg32_t CFSTS12; /* CFSTS12 */ - union iodefine_reg32_t CFSTS13; /* CFSTS13 */ - union iodefine_reg32_t CFSTS14; /* CFSTS14 */ - - volatile uint8_t dummy162[36]; /* */ -#define RSCAN0_CFPCTR0_COUNT 15 - union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */ - union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */ - union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */ - union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */ - union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */ - union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */ - union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */ - union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */ - union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */ - union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */ - union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */ - union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */ - union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */ - union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */ - union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */ - - volatile uint8_t dummy163[36]; /* */ - union iodefine_reg32_t FESTS; /* FESTS */ - union iodefine_reg32_t FFSTS; /* FFSTS */ - union iodefine_reg32_t FMSTS; /* FMSTS */ - union iodefine_reg32_t RFISTS; /* RFISTS */ - union iodefine_reg32_t CFRISTS; /* CFRISTS */ - union iodefine_reg32_t CFTISTS; /* CFTISTS */ - -#define RSCAN0_TMC0_COUNT 80 - volatile uint8_t TMC0; /* TMC0 */ - volatile uint8_t TMC1; /* TMC1 */ - volatile uint8_t TMC2; /* TMC2 */ - volatile uint8_t TMC3; /* TMC3 */ - volatile uint8_t TMC4; /* TMC4 */ - volatile uint8_t TMC5; /* TMC5 */ - volatile uint8_t TMC6; /* TMC6 */ - volatile uint8_t TMC7; /* TMC7 */ - volatile uint8_t TMC8; /* TMC8 */ - volatile uint8_t TMC9; /* TMC9 */ - volatile uint8_t TMC10; /* TMC10 */ - volatile uint8_t TMC11; /* TMC11 */ - volatile uint8_t TMC12; /* TMC12 */ - volatile uint8_t TMC13; /* TMC13 */ - volatile uint8_t TMC14; /* TMC14 */ - volatile uint8_t TMC15; /* TMC15 */ - volatile uint8_t TMC16; /* TMC16 */ - volatile uint8_t TMC17; /* TMC17 */ - volatile uint8_t TMC18; /* TMC18 */ - volatile uint8_t TMC19; /* TMC19 */ - volatile uint8_t TMC20; /* TMC20 */ - volatile uint8_t TMC21; /* TMC21 */ - volatile uint8_t TMC22; /* TMC22 */ - volatile uint8_t TMC23; /* TMC23 */ - volatile uint8_t TMC24; /* TMC24 */ - volatile uint8_t TMC25; /* TMC25 */ - volatile uint8_t TMC26; /* TMC26 */ - volatile uint8_t TMC27; /* TMC27 */ - volatile uint8_t TMC28; /* TMC28 */ - volatile uint8_t TMC29; /* TMC29 */ - volatile uint8_t TMC30; /* TMC30 */ - volatile uint8_t TMC31; /* TMC31 */ - volatile uint8_t TMC32; /* TMC32 */ - volatile uint8_t TMC33; /* TMC33 */ - volatile uint8_t TMC34; /* TMC34 */ - volatile uint8_t TMC35; /* TMC35 */ - volatile uint8_t TMC36; /* TMC36 */ - volatile uint8_t TMC37; /* TMC37 */ - volatile uint8_t TMC38; /* TMC38 */ - volatile uint8_t TMC39; /* TMC39 */ - volatile uint8_t TMC40; /* TMC40 */ - volatile uint8_t TMC41; /* TMC41 */ - volatile uint8_t TMC42; /* TMC42 */ - volatile uint8_t TMC43; /* TMC43 */ - volatile uint8_t TMC44; /* TMC44 */ - volatile uint8_t TMC45; /* TMC45 */ - volatile uint8_t TMC46; /* TMC46 */ - volatile uint8_t TMC47; /* TMC47 */ - volatile uint8_t TMC48; /* TMC48 */ - volatile uint8_t TMC49; /* TMC49 */ - volatile uint8_t TMC50; /* TMC50 */ - volatile uint8_t TMC51; /* TMC51 */ - volatile uint8_t TMC52; /* TMC52 */ - volatile uint8_t TMC53; /* TMC53 */ - volatile uint8_t TMC54; /* TMC54 */ - volatile uint8_t TMC55; /* TMC55 */ - volatile uint8_t TMC56; /* TMC56 */ - volatile uint8_t TMC57; /* TMC57 */ - volatile uint8_t TMC58; /* TMC58 */ - volatile uint8_t TMC59; /* TMC59 */ - volatile uint8_t TMC60; /* TMC60 */ - volatile uint8_t TMC61; /* TMC61 */ - volatile uint8_t TMC62; /* TMC62 */ - volatile uint8_t TMC63; /* TMC63 */ - volatile uint8_t TMC64; /* TMC64 */ - volatile uint8_t TMC65; /* TMC65 */ - volatile uint8_t TMC66; /* TMC66 */ - volatile uint8_t TMC67; /* TMC67 */ - volatile uint8_t TMC68; /* TMC68 */ - volatile uint8_t TMC69; /* TMC69 */ - volatile uint8_t TMC70; /* TMC70 */ - volatile uint8_t TMC71; /* TMC71 */ - volatile uint8_t TMC72; /* TMC72 */ - volatile uint8_t TMC73; /* TMC73 */ - volatile uint8_t TMC74; /* TMC74 */ - volatile uint8_t TMC75; /* TMC75 */ - volatile uint8_t TMC76; /* TMC76 */ - volatile uint8_t TMC77; /* TMC77 */ - volatile uint8_t TMC78; /* TMC78 */ - volatile uint8_t TMC79; /* TMC79 */ - volatile uint8_t dummy164[48]; /* */ -#define RSCAN0_TMSTS0_COUNT 80 - volatile uint8_t TMSTS0; /* TMSTS0 */ - volatile uint8_t TMSTS1; /* TMSTS1 */ - volatile uint8_t TMSTS2; /* TMSTS2 */ - volatile uint8_t TMSTS3; /* TMSTS3 */ - volatile uint8_t TMSTS4; /* TMSTS4 */ - volatile uint8_t TMSTS5; /* TMSTS5 */ - volatile uint8_t TMSTS6; /* TMSTS6 */ - volatile uint8_t TMSTS7; /* TMSTS7 */ - volatile uint8_t TMSTS8; /* TMSTS8 */ - volatile uint8_t TMSTS9; /* TMSTS9 */ - volatile uint8_t TMSTS10; /* TMSTS10 */ - volatile uint8_t TMSTS11; /* TMSTS11 */ - volatile uint8_t TMSTS12; /* TMSTS12 */ - volatile uint8_t TMSTS13; /* TMSTS13 */ - volatile uint8_t TMSTS14; /* TMSTS14 */ - volatile uint8_t TMSTS15; /* TMSTS15 */ - volatile uint8_t TMSTS16; /* TMSTS16 */ - volatile uint8_t TMSTS17; /* TMSTS17 */ - volatile uint8_t TMSTS18; /* TMSTS18 */ - volatile uint8_t TMSTS19; /* TMSTS19 */ - volatile uint8_t TMSTS20; /* TMSTS20 */ - volatile uint8_t TMSTS21; /* TMSTS21 */ - volatile uint8_t TMSTS22; /* TMSTS22 */ - volatile uint8_t TMSTS23; /* TMSTS23 */ - volatile uint8_t TMSTS24; /* TMSTS24 */ - volatile uint8_t TMSTS25; /* TMSTS25 */ - volatile uint8_t TMSTS26; /* TMSTS26 */ - volatile uint8_t TMSTS27; /* TMSTS27 */ - volatile uint8_t TMSTS28; /* TMSTS28 */ - volatile uint8_t TMSTS29; /* TMSTS29 */ - volatile uint8_t TMSTS30; /* TMSTS30 */ - volatile uint8_t TMSTS31; /* TMSTS31 */ - volatile uint8_t TMSTS32; /* TMSTS32 */ - volatile uint8_t TMSTS33; /* TMSTS33 */ - volatile uint8_t TMSTS34; /* TMSTS34 */ - volatile uint8_t TMSTS35; /* TMSTS35 */ - volatile uint8_t TMSTS36; /* TMSTS36 */ - volatile uint8_t TMSTS37; /* TMSTS37 */ - volatile uint8_t TMSTS38; /* TMSTS38 */ - volatile uint8_t TMSTS39; /* TMSTS39 */ - volatile uint8_t TMSTS40; /* TMSTS40 */ - volatile uint8_t TMSTS41; /* TMSTS41 */ - volatile uint8_t TMSTS42; /* TMSTS42 */ - volatile uint8_t TMSTS43; /* TMSTS43 */ - volatile uint8_t TMSTS44; /* TMSTS44 */ - volatile uint8_t TMSTS45; /* TMSTS45 */ - volatile uint8_t TMSTS46; /* TMSTS46 */ - volatile uint8_t TMSTS47; /* TMSTS47 */ - volatile uint8_t TMSTS48; /* TMSTS48 */ - volatile uint8_t TMSTS49; /* TMSTS49 */ - volatile uint8_t TMSTS50; /* TMSTS50 */ - volatile uint8_t TMSTS51; /* TMSTS51 */ - volatile uint8_t TMSTS52; /* TMSTS52 */ - volatile uint8_t TMSTS53; /* TMSTS53 */ - volatile uint8_t TMSTS54; /* TMSTS54 */ - volatile uint8_t TMSTS55; /* TMSTS55 */ - volatile uint8_t TMSTS56; /* TMSTS56 */ - volatile uint8_t TMSTS57; /* TMSTS57 */ - volatile uint8_t TMSTS58; /* TMSTS58 */ - volatile uint8_t TMSTS59; /* TMSTS59 */ - volatile uint8_t TMSTS60; /* TMSTS60 */ - volatile uint8_t TMSTS61; /* TMSTS61 */ - volatile uint8_t TMSTS62; /* TMSTS62 */ - volatile uint8_t TMSTS63; /* TMSTS63 */ - volatile uint8_t TMSTS64; /* TMSTS64 */ - volatile uint8_t TMSTS65; /* TMSTS65 */ - volatile uint8_t TMSTS66; /* TMSTS66 */ - volatile uint8_t TMSTS67; /* TMSTS67 */ - volatile uint8_t TMSTS68; /* TMSTS68 */ - volatile uint8_t TMSTS69; /* TMSTS69 */ - volatile uint8_t TMSTS70; /* TMSTS70 */ - volatile uint8_t TMSTS71; /* TMSTS71 */ - volatile uint8_t TMSTS72; /* TMSTS72 */ - volatile uint8_t TMSTS73; /* TMSTS73 */ - volatile uint8_t TMSTS74; /* TMSTS74 */ - volatile uint8_t TMSTS75; /* TMSTS75 */ - volatile uint8_t TMSTS76; /* TMSTS76 */ - volatile uint8_t TMSTS77; /* TMSTS77 */ - volatile uint8_t TMSTS78; /* TMSTS78 */ - volatile uint8_t TMSTS79; /* TMSTS79 */ - volatile uint8_t dummy165[48]; /* */ -#define RSCAN0_TMTRSTS0_COUNT 3 - union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */ - union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */ - union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */ - - volatile uint8_t dummy166[4]; /* */ -#define RSCAN0_TMTARSTS0_COUNT 3 - union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */ - union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */ - union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */ - - volatile uint8_t dummy167[4]; /* */ -#define RSCAN0_TMTCSTS0_COUNT 3 - union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */ - union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */ - union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */ - - volatile uint8_t dummy168[4]; /* */ -#define RSCAN0_TMTASTS0_COUNT 3 - union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */ - union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */ - union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */ - - volatile uint8_t dummy169[4]; /* */ -#define RSCAN0_TMIEC0_COUNT 3 - union iodefine_reg32_t TMIEC0; /* TMIEC0 */ - union iodefine_reg32_t TMIEC1; /* TMIEC1 */ - union iodefine_reg32_t TMIEC2; /* TMIEC2 */ - - volatile uint8_t dummy170[4]; /* */ -#define RSCAN0_TXQCC0_COUNT 5 - union iodefine_reg32_t TXQCC0; /* TXQCC0 */ - union iodefine_reg32_t TXQCC1; /* TXQCC1 */ - union iodefine_reg32_t TXQCC2; /* TXQCC2 */ - union iodefine_reg32_t TXQCC3; /* TXQCC3 */ - union iodefine_reg32_t TXQCC4; /* TXQCC4 */ - - volatile uint8_t dummy171[12]; /* */ -#define RSCAN0_TXQSTS0_COUNT 5 - union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */ - union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */ - union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */ - union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */ - union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */ - - volatile uint8_t dummy172[12]; /* */ -#define RSCAN0_TXQPCTR0_COUNT 5 - union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */ - union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */ - union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */ - union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */ - union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */ - - volatile uint8_t dummy173[12]; /* */ -#define RSCAN0_THLCC0_COUNT 5 - union iodefine_reg32_t THLCC0; /* THLCC0 */ - union iodefine_reg32_t THLCC1; /* THLCC1 */ - union iodefine_reg32_t THLCC2; /* THLCC2 */ - union iodefine_reg32_t THLCC3; /* THLCC3 */ - union iodefine_reg32_t THLCC4; /* THLCC4 */ - - volatile uint8_t dummy174[12]; /* */ -#define RSCAN0_THLSTS0_COUNT 5 - union iodefine_reg32_t THLSTS0; /* THLSTS0 */ - union iodefine_reg32_t THLSTS1; /* THLSTS1 */ - union iodefine_reg32_t THLSTS2; /* THLSTS2 */ - union iodefine_reg32_t THLSTS3; /* THLSTS3 */ - union iodefine_reg32_t THLSTS4; /* THLSTS4 */ - - volatile uint8_t dummy175[12]; /* */ -#define RSCAN0_THLPCTR0_COUNT 5 - union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */ - union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */ - union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */ - union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */ - union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */ - - volatile uint8_t dummy176[12]; /* */ -#define RSCAN0_GTINTSTS0_COUNT 2 - union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */ - union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */ - union iodefine_reg32_t GTSTCFG; /* GTSTCFG */ - union iodefine_reg32_t GTSTCTR; /* GTSTCTR */ - - volatile uint8_t dummy177[12]; /* */ - union iodefine_reg32_16_t GLOCKK; /* GLOCKK */ - - volatile uint8_t dummy178[128]; /* */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID0; /* GAFLID0 */ - union iodefine_reg32_t GAFLM0; /* GAFLM0 */ - union iodefine_reg32_t GAFLP00; /* GAFLP00 */ - union iodefine_reg32_t GAFLP10; /* GAFLP10 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID1; /* GAFLID1 */ - union iodefine_reg32_t GAFLM1; /* GAFLM1 */ - union iodefine_reg32_t GAFLP01; /* GAFLP01 */ - union iodefine_reg32_t GAFLP11; /* GAFLP11 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID2; /* GAFLID2 */ - union iodefine_reg32_t GAFLM2; /* GAFLM2 */ - union iodefine_reg32_t GAFLP02; /* GAFLP02 */ - union iodefine_reg32_t GAFLP12; /* GAFLP12 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID3; /* GAFLID3 */ - union iodefine_reg32_t GAFLM3; /* GAFLM3 */ - union iodefine_reg32_t GAFLP03; /* GAFLP03 */ - union iodefine_reg32_t GAFLP13; /* GAFLP13 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID4; /* GAFLID4 */ - union iodefine_reg32_t GAFLM4; /* GAFLM4 */ - union iodefine_reg32_t GAFLP04; /* GAFLP04 */ - union iodefine_reg32_t GAFLP14; /* GAFLP14 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID5; /* GAFLID5 */ - union iodefine_reg32_t GAFLM5; /* GAFLM5 */ - union iodefine_reg32_t GAFLP05; /* GAFLP05 */ - union iodefine_reg32_t GAFLP15; /* GAFLP15 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID6; /* GAFLID6 */ - union iodefine_reg32_t GAFLM6; /* GAFLM6 */ - union iodefine_reg32_t GAFLP06; /* GAFLP06 */ - union iodefine_reg32_t GAFLP16; /* GAFLP16 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID7; /* GAFLID7 */ - union iodefine_reg32_t GAFLM7; /* GAFLM7 */ - union iodefine_reg32_t GAFLP07; /* GAFLP07 */ - union iodefine_reg32_t GAFLP17; /* GAFLP17 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID8; /* GAFLID8 */ - union iodefine_reg32_t GAFLM8; /* GAFLM8 */ - union iodefine_reg32_t GAFLP08; /* GAFLP08 */ - union iodefine_reg32_t GAFLP18; /* GAFLP18 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID9; /* GAFLID9 */ - union iodefine_reg32_t GAFLM9; /* GAFLM9 */ - union iodefine_reg32_t GAFLP09; /* GAFLP09 */ - union iodefine_reg32_t GAFLP19; /* GAFLP19 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID10; /* GAFLID10 */ - union iodefine_reg32_t GAFLM10; /* GAFLM10 */ - union iodefine_reg32_t GAFLP010; /* GAFLP010 */ - union iodefine_reg32_t GAFLP110; /* GAFLP110 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID11; /* GAFLID11 */ - union iodefine_reg32_t GAFLM11; /* GAFLM11 */ - union iodefine_reg32_t GAFLP011; /* GAFLP011 */ - union iodefine_reg32_t GAFLP111; /* GAFLP111 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID12; /* GAFLID12 */ - union iodefine_reg32_t GAFLM12; /* GAFLM12 */ - union iodefine_reg32_t GAFLP012; /* GAFLP012 */ - union iodefine_reg32_t GAFLP112; /* GAFLP112 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID13; /* GAFLID13 */ - union iodefine_reg32_t GAFLM13; /* GAFLM13 */ - union iodefine_reg32_t GAFLP013; /* GAFLP013 */ - union iodefine_reg32_t GAFLP113; /* GAFLP113 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID14; /* GAFLID14 */ - union iodefine_reg32_t GAFLM14; /* GAFLM14 */ - union iodefine_reg32_t GAFLP014; /* GAFLP014 */ - union iodefine_reg32_t GAFLP114; /* GAFLP114 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID15; /* GAFLID15 */ - union iodefine_reg32_t GAFLM15; /* GAFLM15 */ - union iodefine_reg32_t GAFLP015; /* GAFLP015 */ - union iodefine_reg32_t GAFLP115; /* GAFLP115 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID0; /* RMID0 */ - union iodefine_reg32_t RMPTR0; /* RMPTR0 */ - union iodefine_reg32_t RMDF00; /* RMDF00 */ - union iodefine_reg32_t RMDF10; /* RMDF10 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID1; /* RMID1 */ - union iodefine_reg32_t RMPTR1; /* RMPTR1 */ - union iodefine_reg32_t RMDF01; /* RMDF01 */ - union iodefine_reg32_t RMDF11; /* RMDF11 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID2; /* RMID2 */ - union iodefine_reg32_t RMPTR2; /* RMPTR2 */ - union iodefine_reg32_t RMDF02; /* RMDF02 */ - union iodefine_reg32_t RMDF12; /* RMDF12 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID3; /* RMID3 */ - union iodefine_reg32_t RMPTR3; /* RMPTR3 */ - union iodefine_reg32_t RMDF03; /* RMDF03 */ - union iodefine_reg32_t RMDF13; /* RMDF13 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID4; /* RMID4 */ - union iodefine_reg32_t RMPTR4; /* RMPTR4 */ - union iodefine_reg32_t RMDF04; /* RMDF04 */ - union iodefine_reg32_t RMDF14; /* RMDF14 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID5; /* RMID5 */ - union iodefine_reg32_t RMPTR5; /* RMPTR5 */ - union iodefine_reg32_t RMDF05; /* RMDF05 */ - union iodefine_reg32_t RMDF15; /* RMDF15 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID6; /* RMID6 */ - union iodefine_reg32_t RMPTR6; /* RMPTR6 */ - union iodefine_reg32_t RMDF06; /* RMDF06 */ - union iodefine_reg32_t RMDF16; /* RMDF16 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID7; /* RMID7 */ - union iodefine_reg32_t RMPTR7; /* RMPTR7 */ - union iodefine_reg32_t RMDF07; /* RMDF07 */ - union iodefine_reg32_t RMDF17; /* RMDF17 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID8; /* RMID8 */ - union iodefine_reg32_t RMPTR8; /* RMPTR8 */ - union iodefine_reg32_t RMDF08; /* RMDF08 */ - union iodefine_reg32_t RMDF18; /* RMDF18 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID9; /* RMID9 */ - union iodefine_reg32_t RMPTR9; /* RMPTR9 */ - union iodefine_reg32_t RMDF09; /* RMDF09 */ - union iodefine_reg32_t RMDF19; /* RMDF19 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID10; /* RMID10 */ - union iodefine_reg32_t RMPTR10; /* RMPTR10 */ - union iodefine_reg32_t RMDF010; /* RMDF010 */ - union iodefine_reg32_t RMDF110; /* RMDF110 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID11; /* RMID11 */ - union iodefine_reg32_t RMPTR11; /* RMPTR11 */ - union iodefine_reg32_t RMDF011; /* RMDF011 */ - union iodefine_reg32_t RMDF111; /* RMDF111 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID12; /* RMID12 */ - union iodefine_reg32_t RMPTR12; /* RMPTR12 */ - union iodefine_reg32_t RMDF012; /* RMDF012 */ - union iodefine_reg32_t RMDF112; /* RMDF112 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID13; /* RMID13 */ - union iodefine_reg32_t RMPTR13; /* RMPTR13 */ - union iodefine_reg32_t RMDF013; /* RMDF013 */ - union iodefine_reg32_t RMDF113; /* RMDF113 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID14; /* RMID14 */ - union iodefine_reg32_t RMPTR14; /* RMPTR14 */ - union iodefine_reg32_t RMDF014; /* RMDF014 */ - union iodefine_reg32_t RMDF114; /* RMDF114 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID15; /* RMID15 */ - union iodefine_reg32_t RMPTR15; /* RMPTR15 */ - union iodefine_reg32_t RMDF015; /* RMDF015 */ - union iodefine_reg32_t RMDF115; /* RMDF115 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID16; /* RMID16 */ - union iodefine_reg32_t RMPTR16; /* RMPTR16 */ - union iodefine_reg32_t RMDF016; /* RMDF016 */ - union iodefine_reg32_t RMDF116; /* RMDF116 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID17; /* RMID17 */ - union iodefine_reg32_t RMPTR17; /* RMPTR17 */ - union iodefine_reg32_t RMDF017; /* RMDF017 */ - union iodefine_reg32_t RMDF117; /* RMDF117 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID18; /* RMID18 */ - union iodefine_reg32_t RMPTR18; /* RMPTR18 */ - union iodefine_reg32_t RMDF018; /* RMDF018 */ - union iodefine_reg32_t RMDF118; /* RMDF118 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID19; /* RMID19 */ - union iodefine_reg32_t RMPTR19; /* RMPTR19 */ - union iodefine_reg32_t RMDF019; /* RMDF019 */ - union iodefine_reg32_t RMDF119; /* RMDF119 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID20; /* RMID20 */ - union iodefine_reg32_t RMPTR20; /* RMPTR20 */ - union iodefine_reg32_t RMDF020; /* RMDF020 */ - union iodefine_reg32_t RMDF120; /* RMDF120 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID21; /* RMID21 */ - union iodefine_reg32_t RMPTR21; /* RMPTR21 */ - union iodefine_reg32_t RMDF021; /* RMDF021 */ - union iodefine_reg32_t RMDF121; /* RMDF121 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID22; /* RMID22 */ - union iodefine_reg32_t RMPTR22; /* RMPTR22 */ - union iodefine_reg32_t RMDF022; /* RMDF022 */ - union iodefine_reg32_t RMDF122; /* RMDF122 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID23; /* RMID23 */ - union iodefine_reg32_t RMPTR23; /* RMPTR23 */ - union iodefine_reg32_t RMDF023; /* RMDF023 */ - union iodefine_reg32_t RMDF123; /* RMDF123 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID24; /* RMID24 */ - union iodefine_reg32_t RMPTR24; /* RMPTR24 */ - union iodefine_reg32_t RMDF024; /* RMDF024 */ - union iodefine_reg32_t RMDF124; /* RMDF124 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID25; /* RMID25 */ - union iodefine_reg32_t RMPTR25; /* RMPTR25 */ - union iodefine_reg32_t RMDF025; /* RMDF025 */ - union iodefine_reg32_t RMDF125; /* RMDF125 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID26; /* RMID26 */ - union iodefine_reg32_t RMPTR26; /* RMPTR26 */ - union iodefine_reg32_t RMDF026; /* RMDF026 */ - union iodefine_reg32_t RMDF126; /* RMDF126 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID27; /* RMID27 */ - union iodefine_reg32_t RMPTR27; /* RMPTR27 */ - union iodefine_reg32_t RMDF027; /* RMDF027 */ - union iodefine_reg32_t RMDF127; /* RMDF127 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID28; /* RMID28 */ - union iodefine_reg32_t RMPTR28; /* RMPTR28 */ - union iodefine_reg32_t RMDF028; /* RMDF028 */ - union iodefine_reg32_t RMDF128; /* RMDF128 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID29; /* RMID29 */ - union iodefine_reg32_t RMPTR29; /* RMPTR29 */ - union iodefine_reg32_t RMDF029; /* RMDF029 */ - union iodefine_reg32_t RMDF129; /* RMDF129 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID30; /* RMID30 */ - union iodefine_reg32_t RMPTR30; /* RMPTR30 */ - union iodefine_reg32_t RMDF030; /* RMDF030 */ - union iodefine_reg32_t RMDF130; /* RMDF130 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID31; /* RMID31 */ - union iodefine_reg32_t RMPTR31; /* RMPTR31 */ - union iodefine_reg32_t RMDF031; /* RMDF031 */ - union iodefine_reg32_t RMDF131; /* RMDF131 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID32; /* RMID32 */ - union iodefine_reg32_t RMPTR32; /* RMPTR32 */ - union iodefine_reg32_t RMDF032; /* RMDF032 */ - union iodefine_reg32_t RMDF132; /* RMDF132 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID33; /* RMID33 */ - union iodefine_reg32_t RMPTR33; /* RMPTR33 */ - union iodefine_reg32_t RMDF033; /* RMDF033 */ - union iodefine_reg32_t RMDF133; /* RMDF133 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID34; /* RMID34 */ - union iodefine_reg32_t RMPTR34; /* RMPTR34 */ - union iodefine_reg32_t RMDF034; /* RMDF034 */ - union iodefine_reg32_t RMDF134; /* RMDF134 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID35; /* RMID35 */ - union iodefine_reg32_t RMPTR35; /* RMPTR35 */ - union iodefine_reg32_t RMDF035; /* RMDF035 */ - union iodefine_reg32_t RMDF135; /* RMDF135 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID36; /* RMID36 */ - union iodefine_reg32_t RMPTR36; /* RMPTR36 */ - union iodefine_reg32_t RMDF036; /* RMDF036 */ - union iodefine_reg32_t RMDF136; /* RMDF136 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID37; /* RMID37 */ - union iodefine_reg32_t RMPTR37; /* RMPTR37 */ - union iodefine_reg32_t RMDF037; /* RMDF037 */ - union iodefine_reg32_t RMDF137; /* RMDF137 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID38; /* RMID38 */ - union iodefine_reg32_t RMPTR38; /* RMPTR38 */ - union iodefine_reg32_t RMDF038; /* RMDF038 */ - union iodefine_reg32_t RMDF138; /* RMDF138 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID39; /* RMID39 */ - union iodefine_reg32_t RMPTR39; /* RMPTR39 */ - union iodefine_reg32_t RMDF039; /* RMDF039 */ - union iodefine_reg32_t RMDF139; /* RMDF139 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID40; /* RMID40 */ - union iodefine_reg32_t RMPTR40; /* RMPTR40 */ - union iodefine_reg32_t RMDF040; /* RMDF040 */ - union iodefine_reg32_t RMDF140; /* RMDF140 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID41; /* RMID41 */ - union iodefine_reg32_t RMPTR41; /* RMPTR41 */ - union iodefine_reg32_t RMDF041; /* RMDF041 */ - union iodefine_reg32_t RMDF141; /* RMDF141 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID42; /* RMID42 */ - union iodefine_reg32_t RMPTR42; /* RMPTR42 */ - union iodefine_reg32_t RMDF042; /* RMDF042 */ - union iodefine_reg32_t RMDF142; /* RMDF142 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID43; /* RMID43 */ - union iodefine_reg32_t RMPTR43; /* RMPTR43 */ - union iodefine_reg32_t RMDF043; /* RMDF043 */ - union iodefine_reg32_t RMDF143; /* RMDF143 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID44; /* RMID44 */ - union iodefine_reg32_t RMPTR44; /* RMPTR44 */ - union iodefine_reg32_t RMDF044; /* RMDF044 */ - union iodefine_reg32_t RMDF144; /* RMDF144 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID45; /* RMID45 */ - union iodefine_reg32_t RMPTR45; /* RMPTR45 */ - union iodefine_reg32_t RMDF045; /* RMDF045 */ - union iodefine_reg32_t RMDF145; /* RMDF145 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID46; /* RMID46 */ - union iodefine_reg32_t RMPTR46; /* RMPTR46 */ - union iodefine_reg32_t RMDF046; /* RMDF046 */ - union iodefine_reg32_t RMDF146; /* RMDF146 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID47; /* RMID47 */ - union iodefine_reg32_t RMPTR47; /* RMPTR47 */ - union iodefine_reg32_t RMDF047; /* RMDF047 */ - union iodefine_reg32_t RMDF147; /* RMDF147 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID48; /* RMID48 */ - union iodefine_reg32_t RMPTR48; /* RMPTR48 */ - union iodefine_reg32_t RMDF048; /* RMDF048 */ - union iodefine_reg32_t RMDF148; /* RMDF148 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID49; /* RMID49 */ - union iodefine_reg32_t RMPTR49; /* RMPTR49 */ - union iodefine_reg32_t RMDF049; /* RMDF049 */ - union iodefine_reg32_t RMDF149; /* RMDF149 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID50; /* RMID50 */ - union iodefine_reg32_t RMPTR50; /* RMPTR50 */ - union iodefine_reg32_t RMDF050; /* RMDF050 */ - union iodefine_reg32_t RMDF150; /* RMDF150 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID51; /* RMID51 */ - union iodefine_reg32_t RMPTR51; /* RMPTR51 */ - union iodefine_reg32_t RMDF051; /* RMDF051 */ - union iodefine_reg32_t RMDF151; /* RMDF151 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID52; /* RMID52 */ - union iodefine_reg32_t RMPTR52; /* RMPTR52 */ - union iodefine_reg32_t RMDF052; /* RMDF052 */ - union iodefine_reg32_t RMDF152; /* RMDF152 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID53; /* RMID53 */ - union iodefine_reg32_t RMPTR53; /* RMPTR53 */ - union iodefine_reg32_t RMDF053; /* RMDF053 */ - union iodefine_reg32_t RMDF153; /* RMDF153 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID54; /* RMID54 */ - union iodefine_reg32_t RMPTR54; /* RMPTR54 */ - union iodefine_reg32_t RMDF054; /* RMDF054 */ - union iodefine_reg32_t RMDF154; /* RMDF154 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID55; /* RMID55 */ - union iodefine_reg32_t RMPTR55; /* RMPTR55 */ - union iodefine_reg32_t RMDF055; /* RMDF055 */ - union iodefine_reg32_t RMDF155; /* RMDF155 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID56; /* RMID56 */ - union iodefine_reg32_t RMPTR56; /* RMPTR56 */ - union iodefine_reg32_t RMDF056; /* RMDF056 */ - union iodefine_reg32_t RMDF156; /* RMDF156 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID57; /* RMID57 */ - union iodefine_reg32_t RMPTR57; /* RMPTR57 */ - union iodefine_reg32_t RMDF057; /* RMDF057 */ - union iodefine_reg32_t RMDF157; /* RMDF157 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID58; /* RMID58 */ - union iodefine_reg32_t RMPTR58; /* RMPTR58 */ - union iodefine_reg32_t RMDF058; /* RMDF058 */ - union iodefine_reg32_t RMDF158; /* RMDF158 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID59; /* RMID59 */ - union iodefine_reg32_t RMPTR59; /* RMPTR59 */ - union iodefine_reg32_t RMDF059; /* RMDF059 */ - union iodefine_reg32_t RMDF159; /* RMDF159 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID60; /* RMID60 */ - union iodefine_reg32_t RMPTR60; /* RMPTR60 */ - union iodefine_reg32_t RMDF060; /* RMDF060 */ - union iodefine_reg32_t RMDF160; /* RMDF160 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID61; /* RMID61 */ - union iodefine_reg32_t RMPTR61; /* RMPTR61 */ - union iodefine_reg32_t RMDF061; /* RMDF061 */ - union iodefine_reg32_t RMDF161; /* RMDF161 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID62; /* RMID62 */ - union iodefine_reg32_t RMPTR62; /* RMPTR62 */ - union iodefine_reg32_t RMDF062; /* RMDF062 */ - union iodefine_reg32_t RMDF162; /* RMDF162 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID63; /* RMID63 */ - union iodefine_reg32_t RMPTR63; /* RMPTR63 */ - union iodefine_reg32_t RMDF063; /* RMDF063 */ - union iodefine_reg32_t RMDF163; /* RMDF163 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID64; /* RMID64 */ - union iodefine_reg32_t RMPTR64; /* RMPTR64 */ - union iodefine_reg32_t RMDF064; /* RMDF064 */ - union iodefine_reg32_t RMDF164; /* RMDF164 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID65; /* RMID65 */ - union iodefine_reg32_t RMPTR65; /* RMPTR65 */ - union iodefine_reg32_t RMDF065; /* RMDF065 */ - union iodefine_reg32_t RMDF165; /* RMDF165 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID66; /* RMID66 */ - union iodefine_reg32_t RMPTR66; /* RMPTR66 */ - union iodefine_reg32_t RMDF066; /* RMDF066 */ - union iodefine_reg32_t RMDF166; /* RMDF166 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID67; /* RMID67 */ - union iodefine_reg32_t RMPTR67; /* RMPTR67 */ - union iodefine_reg32_t RMDF067; /* RMDF067 */ - union iodefine_reg32_t RMDF167; /* RMDF167 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID68; /* RMID68 */ - union iodefine_reg32_t RMPTR68; /* RMPTR68 */ - union iodefine_reg32_t RMDF068; /* RMDF068 */ - union iodefine_reg32_t RMDF168; /* RMDF168 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID69; /* RMID69 */ - union iodefine_reg32_t RMPTR69; /* RMPTR69 */ - union iodefine_reg32_t RMDF069; /* RMDF069 */ - union iodefine_reg32_t RMDF169; /* RMDF169 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID70; /* RMID70 */ - union iodefine_reg32_t RMPTR70; /* RMPTR70 */ - union iodefine_reg32_t RMDF070; /* RMDF070 */ - union iodefine_reg32_t RMDF170; /* RMDF170 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID71; /* RMID71 */ - union iodefine_reg32_t RMPTR71; /* RMPTR71 */ - union iodefine_reg32_t RMDF071; /* RMDF071 */ - union iodefine_reg32_t RMDF171; /* RMDF171 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID72; /* RMID72 */ - union iodefine_reg32_t RMPTR72; /* RMPTR72 */ - union iodefine_reg32_t RMDF072; /* RMDF072 */ - union iodefine_reg32_t RMDF172; /* RMDF172 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID73; /* RMID73 */ - union iodefine_reg32_t RMPTR73; /* RMPTR73 */ - union iodefine_reg32_t RMDF073; /* RMDF073 */ - union iodefine_reg32_t RMDF173; /* RMDF173 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID74; /* RMID74 */ - union iodefine_reg32_t RMPTR74; /* RMPTR74 */ - union iodefine_reg32_t RMDF074; /* RMDF074 */ - union iodefine_reg32_t RMDF174; /* RMDF174 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID75; /* RMID75 */ - union iodefine_reg32_t RMPTR75; /* RMPTR75 */ - union iodefine_reg32_t RMDF075; /* RMDF075 */ - union iodefine_reg32_t RMDF175; /* RMDF175 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID76; /* RMID76 */ - union iodefine_reg32_t RMPTR76; /* RMPTR76 */ - union iodefine_reg32_t RMDF076; /* RMDF076 */ - union iodefine_reg32_t RMDF176; /* RMDF176 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID77; /* RMID77 */ - union iodefine_reg32_t RMPTR77; /* RMPTR77 */ - union iodefine_reg32_t RMDF077; /* RMDF077 */ - union iodefine_reg32_t RMDF177; /* RMDF177 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID78; /* RMID78 */ - union iodefine_reg32_t RMPTR78; /* RMPTR78 */ - union iodefine_reg32_t RMDF078; /* RMDF078 */ - union iodefine_reg32_t RMDF178; /* RMDF178 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID79; /* RMID79 */ - union iodefine_reg32_t RMPTR79; /* RMPTR79 */ - union iodefine_reg32_t RMDF079; /* RMDF079 */ - union iodefine_reg32_t RMDF179; /* RMDF179 */ -/* end of struct st_rscan_from_rscan0rmidp */ - - volatile uint8_t dummy179[768]; /* */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID0; /* RFID0 */ - union iodefine_reg32_t RFPTR0; /* RFPTR0 */ - union iodefine_reg32_t RFDF00; /* RFDF00 */ - union iodefine_reg32_t RFDF10; /* RFDF10 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID1; /* RFID1 */ - union iodefine_reg32_t RFPTR1; /* RFPTR1 */ - union iodefine_reg32_t RFDF01; /* RFDF01 */ - union iodefine_reg32_t RFDF11; /* RFDF11 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID2; /* RFID2 */ - union iodefine_reg32_t RFPTR2; /* RFPTR2 */ - union iodefine_reg32_t RFDF02; /* RFDF02 */ - union iodefine_reg32_t RFDF12; /* RFDF12 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID3; /* RFID3 */ - union iodefine_reg32_t RFPTR3; /* RFPTR3 */ - union iodefine_reg32_t RFDF03; /* RFDF03 */ - union iodefine_reg32_t RFDF13; /* RFDF13 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID4; /* RFID4 */ - union iodefine_reg32_t RFPTR4; /* RFPTR4 */ - union iodefine_reg32_t RFDF04; /* RFDF04 */ - union iodefine_reg32_t RFDF14; /* RFDF14 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID5; /* RFID5 */ - union iodefine_reg32_t RFPTR5; /* RFPTR5 */ - union iodefine_reg32_t RFDF05; /* RFDF05 */ - union iodefine_reg32_t RFDF15; /* RFDF15 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID6; /* RFID6 */ - union iodefine_reg32_t RFPTR6; /* RFPTR6 */ - union iodefine_reg32_t RFDF06; /* RFDF06 */ - union iodefine_reg32_t RFDF16; /* RFDF16 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID7; /* RFID7 */ - union iodefine_reg32_t RFPTR7; /* RFPTR7 */ - union iodefine_reg32_t RFDF07; /* RFDF07 */ - union iodefine_reg32_t RFDF17; /* RFDF17 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID0; /* CFID0 */ - union iodefine_reg32_t CFPTR0; /* CFPTR0 */ - union iodefine_reg32_t CFDF00; /* CFDF00 */ - union iodefine_reg32_t CFDF10; /* CFDF10 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID1; /* CFID1 */ - union iodefine_reg32_t CFPTR1; /* CFPTR1 */ - union iodefine_reg32_t CFDF01; /* CFDF01 */ - union iodefine_reg32_t CFDF11; /* CFDF11 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID2; /* CFID2 */ - union iodefine_reg32_t CFPTR2; /* CFPTR2 */ - union iodefine_reg32_t CFDF02; /* CFDF02 */ - union iodefine_reg32_t CFDF12; /* CFDF12 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID3; /* CFID3 */ - union iodefine_reg32_t CFPTR3; /* CFPTR3 */ - union iodefine_reg32_t CFDF03; /* CFDF03 */ - union iodefine_reg32_t CFDF13; /* CFDF13 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID4; /* CFID4 */ - union iodefine_reg32_t CFPTR4; /* CFPTR4 */ - union iodefine_reg32_t CFDF04; /* CFDF04 */ - union iodefine_reg32_t CFDF14; /* CFDF14 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID5; /* CFID5 */ - union iodefine_reg32_t CFPTR5; /* CFPTR5 */ - union iodefine_reg32_t CFDF05; /* CFDF05 */ - union iodefine_reg32_t CFDF15; /* CFDF15 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID6; /* CFID6 */ - union iodefine_reg32_t CFPTR6; /* CFPTR6 */ - union iodefine_reg32_t CFDF06; /* CFDF06 */ - union iodefine_reg32_t CFDF16; /* CFDF16 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID7; /* CFID7 */ - union iodefine_reg32_t CFPTR7; /* CFPTR7 */ - union iodefine_reg32_t CFDF07; /* CFDF07 */ - union iodefine_reg32_t CFDF17; /* CFDF17 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID8; /* CFID8 */ - union iodefine_reg32_t CFPTR8; /* CFPTR8 */ - union iodefine_reg32_t CFDF08; /* CFDF08 */ - union iodefine_reg32_t CFDF18; /* CFDF18 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID9; /* CFID9 */ - union iodefine_reg32_t CFPTR9; /* CFPTR9 */ - union iodefine_reg32_t CFDF09; /* CFDF09 */ - union iodefine_reg32_t CFDF19; /* CFDF19 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID10; /* CFID10 */ - union iodefine_reg32_t CFPTR10; /* CFPTR10 */ - union iodefine_reg32_t CFDF010; /* CFDF010 */ - union iodefine_reg32_t CFDF110; /* CFDF110 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID11; /* CFID11 */ - union iodefine_reg32_t CFPTR11; /* CFPTR11 */ - union iodefine_reg32_t CFDF011; /* CFDF011 */ - union iodefine_reg32_t CFDF111; /* CFDF111 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID12; /* CFID12 */ - union iodefine_reg32_t CFPTR12; /* CFPTR12 */ - union iodefine_reg32_t CFDF012; /* CFDF012 */ - union iodefine_reg32_t CFDF112; /* CFDF112 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID13; /* CFID13 */ - union iodefine_reg32_t CFPTR13; /* CFPTR13 */ - union iodefine_reg32_t CFDF013; /* CFDF013 */ - union iodefine_reg32_t CFDF113; /* CFDF113 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID14; /* CFID14 */ - union iodefine_reg32_t CFPTR14; /* CFPTR14 */ - union iodefine_reg32_t CFDF014; /* CFDF014 */ - union iodefine_reg32_t CFDF114; /* CFDF114 */ -/* end of struct st_rscan_from_rscan0cfidm */ - - volatile uint8_t dummy180[144]; /* */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID0; /* TMID0 */ - union iodefine_reg32_t TMPTR0; /* TMPTR0 */ - union iodefine_reg32_t TMDF00; /* TMDF00 */ - union iodefine_reg32_t TMDF10; /* TMDF10 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID1; /* TMID1 */ - union iodefine_reg32_t TMPTR1; /* TMPTR1 */ - union iodefine_reg32_t TMDF01; /* TMDF01 */ - union iodefine_reg32_t TMDF11; /* TMDF11 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID2; /* TMID2 */ - union iodefine_reg32_t TMPTR2; /* TMPTR2 */ - union iodefine_reg32_t TMDF02; /* TMDF02 */ - union iodefine_reg32_t TMDF12; /* TMDF12 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID3; /* TMID3 */ - union iodefine_reg32_t TMPTR3; /* TMPTR3 */ - union iodefine_reg32_t TMDF03; /* TMDF03 */ - union iodefine_reg32_t TMDF13; /* TMDF13 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID4; /* TMID4 */ - union iodefine_reg32_t TMPTR4; /* TMPTR4 */ - union iodefine_reg32_t TMDF04; /* TMDF04 */ - union iodefine_reg32_t TMDF14; /* TMDF14 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID5; /* TMID5 */ - union iodefine_reg32_t TMPTR5; /* TMPTR5 */ - union iodefine_reg32_t TMDF05; /* TMDF05 */ - union iodefine_reg32_t TMDF15; /* TMDF15 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID6; /* TMID6 */ - union iodefine_reg32_t TMPTR6; /* TMPTR6 */ - union iodefine_reg32_t TMDF06; /* TMDF06 */ - union iodefine_reg32_t TMDF16; /* TMDF16 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID7; /* TMID7 */ - union iodefine_reg32_t TMPTR7; /* TMPTR7 */ - union iodefine_reg32_t TMDF07; /* TMDF07 */ - union iodefine_reg32_t TMDF17; /* TMDF17 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID8; /* TMID8 */ - union iodefine_reg32_t TMPTR8; /* TMPTR8 */ - union iodefine_reg32_t TMDF08; /* TMDF08 */ - union iodefine_reg32_t TMDF18; /* TMDF18 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID9; /* TMID9 */ - union iodefine_reg32_t TMPTR9; /* TMPTR9 */ - union iodefine_reg32_t TMDF09; /* TMDF09 */ - union iodefine_reg32_t TMDF19; /* TMDF19 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID10; /* TMID10 */ - union iodefine_reg32_t TMPTR10; /* TMPTR10 */ - union iodefine_reg32_t TMDF010; /* TMDF010 */ - union iodefine_reg32_t TMDF110; /* TMDF110 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID11; /* TMID11 */ - union iodefine_reg32_t TMPTR11; /* TMPTR11 */ - union iodefine_reg32_t TMDF011; /* TMDF011 */ - union iodefine_reg32_t TMDF111; /* TMDF111 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID12; /* TMID12 */ - union iodefine_reg32_t TMPTR12; /* TMPTR12 */ - union iodefine_reg32_t TMDF012; /* TMDF012 */ - union iodefine_reg32_t TMDF112; /* TMDF112 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID13; /* TMID13 */ - union iodefine_reg32_t TMPTR13; /* TMPTR13 */ - union iodefine_reg32_t TMDF013; /* TMDF013 */ - union iodefine_reg32_t TMDF113; /* TMDF113 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID14; /* TMID14 */ - union iodefine_reg32_t TMPTR14; /* TMPTR14 */ - union iodefine_reg32_t TMDF014; /* TMDF014 */ - union iodefine_reg32_t TMDF114; /* TMDF114 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID15; /* TMID15 */ - union iodefine_reg32_t TMPTR15; /* TMPTR15 */ - union iodefine_reg32_t TMDF015; /* TMDF015 */ - union iodefine_reg32_t TMDF115; /* TMDF115 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID16; /* TMID16 */ - union iodefine_reg32_t TMPTR16; /* TMPTR16 */ - union iodefine_reg32_t TMDF016; /* TMDF016 */ - union iodefine_reg32_t TMDF116; /* TMDF116 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID17; /* TMID17 */ - union iodefine_reg32_t TMPTR17; /* TMPTR17 */ - union iodefine_reg32_t TMDF017; /* TMDF017 */ - union iodefine_reg32_t TMDF117; /* TMDF117 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID18; /* TMID18 */ - union iodefine_reg32_t TMPTR18; /* TMPTR18 */ - union iodefine_reg32_t TMDF018; /* TMDF018 */ - union iodefine_reg32_t TMDF118; /* TMDF118 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID19; /* TMID19 */ - union iodefine_reg32_t TMPTR19; /* TMPTR19 */ - union iodefine_reg32_t TMDF019; /* TMDF019 */ - union iodefine_reg32_t TMDF119; /* TMDF119 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID20; /* TMID20 */ - union iodefine_reg32_t TMPTR20; /* TMPTR20 */ - union iodefine_reg32_t TMDF020; /* TMDF020 */ - union iodefine_reg32_t TMDF120; /* TMDF120 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID21; /* TMID21 */ - union iodefine_reg32_t TMPTR21; /* TMPTR21 */ - union iodefine_reg32_t TMDF021; /* TMDF021 */ - union iodefine_reg32_t TMDF121; /* TMDF121 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID22; /* TMID22 */ - union iodefine_reg32_t TMPTR22; /* TMPTR22 */ - union iodefine_reg32_t TMDF022; /* TMDF022 */ - union iodefine_reg32_t TMDF122; /* TMDF122 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID23; /* TMID23 */ - union iodefine_reg32_t TMPTR23; /* TMPTR23 */ - union iodefine_reg32_t TMDF023; /* TMDF023 */ - union iodefine_reg32_t TMDF123; /* TMDF123 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID24; /* TMID24 */ - union iodefine_reg32_t TMPTR24; /* TMPTR24 */ - union iodefine_reg32_t TMDF024; /* TMDF024 */ - union iodefine_reg32_t TMDF124; /* TMDF124 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID25; /* TMID25 */ - union iodefine_reg32_t TMPTR25; /* TMPTR25 */ - union iodefine_reg32_t TMDF025; /* TMDF025 */ - union iodefine_reg32_t TMDF125; /* TMDF125 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID26; /* TMID26 */ - union iodefine_reg32_t TMPTR26; /* TMPTR26 */ - union iodefine_reg32_t TMDF026; /* TMDF026 */ - union iodefine_reg32_t TMDF126; /* TMDF126 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID27; /* TMID27 */ - union iodefine_reg32_t TMPTR27; /* TMPTR27 */ - union iodefine_reg32_t TMDF027; /* TMDF027 */ - union iodefine_reg32_t TMDF127; /* TMDF127 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID28; /* TMID28 */ - union iodefine_reg32_t TMPTR28; /* TMPTR28 */ - union iodefine_reg32_t TMDF028; /* TMDF028 */ - union iodefine_reg32_t TMDF128; /* TMDF128 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID29; /* TMID29 */ - union iodefine_reg32_t TMPTR29; /* TMPTR29 */ - union iodefine_reg32_t TMDF029; /* TMDF029 */ - union iodefine_reg32_t TMDF129; /* TMDF129 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID30; /* TMID30 */ - union iodefine_reg32_t TMPTR30; /* TMPTR30 */ - union iodefine_reg32_t TMDF030; /* TMDF030 */ - union iodefine_reg32_t TMDF130; /* TMDF130 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID31; /* TMID31 */ - union iodefine_reg32_t TMPTR31; /* TMPTR31 */ - union iodefine_reg32_t TMDF031; /* TMDF031 */ - union iodefine_reg32_t TMDF131; /* TMDF131 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID32; /* TMID32 */ - union iodefine_reg32_t TMPTR32; /* TMPTR32 */ - union iodefine_reg32_t TMDF032; /* TMDF032 */ - union iodefine_reg32_t TMDF132; /* TMDF132 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID33; /* TMID33 */ - union iodefine_reg32_t TMPTR33; /* TMPTR33 */ - union iodefine_reg32_t TMDF033; /* TMDF033 */ - union iodefine_reg32_t TMDF133; /* TMDF133 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID34; /* TMID34 */ - union iodefine_reg32_t TMPTR34; /* TMPTR34 */ - union iodefine_reg32_t TMDF034; /* TMDF034 */ - union iodefine_reg32_t TMDF134; /* TMDF134 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID35; /* TMID35 */ - union iodefine_reg32_t TMPTR35; /* TMPTR35 */ - union iodefine_reg32_t TMDF035; /* TMDF035 */ - union iodefine_reg32_t TMDF135; /* TMDF135 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID36; /* TMID36 */ - union iodefine_reg32_t TMPTR36; /* TMPTR36 */ - union iodefine_reg32_t TMDF036; /* TMDF036 */ - union iodefine_reg32_t TMDF136; /* TMDF136 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID37; /* TMID37 */ - union iodefine_reg32_t TMPTR37; /* TMPTR37 */ - union iodefine_reg32_t TMDF037; /* TMDF037 */ - union iodefine_reg32_t TMDF137; /* TMDF137 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID38; /* TMID38 */ - union iodefine_reg32_t TMPTR38; /* TMPTR38 */ - union iodefine_reg32_t TMDF038; /* TMDF038 */ - union iodefine_reg32_t TMDF138; /* TMDF138 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID39; /* TMID39 */ - union iodefine_reg32_t TMPTR39; /* TMPTR39 */ - union iodefine_reg32_t TMDF039; /* TMDF039 */ - union iodefine_reg32_t TMDF139; /* TMDF139 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID40; /* TMID40 */ - union iodefine_reg32_t TMPTR40; /* TMPTR40 */ - union iodefine_reg32_t TMDF040; /* TMDF040 */ - union iodefine_reg32_t TMDF140; /* TMDF140 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID41; /* TMID41 */ - union iodefine_reg32_t TMPTR41; /* TMPTR41 */ - union iodefine_reg32_t TMDF041; /* TMDF041 */ - union iodefine_reg32_t TMDF141; /* TMDF141 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID42; /* TMID42 */ - union iodefine_reg32_t TMPTR42; /* TMPTR42 */ - union iodefine_reg32_t TMDF042; /* TMDF042 */ - union iodefine_reg32_t TMDF142; /* TMDF142 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID43; /* TMID43 */ - union iodefine_reg32_t TMPTR43; /* TMPTR43 */ - union iodefine_reg32_t TMDF043; /* TMDF043 */ - union iodefine_reg32_t TMDF143; /* TMDF143 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID44; /* TMID44 */ - union iodefine_reg32_t TMPTR44; /* TMPTR44 */ - union iodefine_reg32_t TMDF044; /* TMDF044 */ - union iodefine_reg32_t TMDF144; /* TMDF144 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID45; /* TMID45 */ - union iodefine_reg32_t TMPTR45; /* TMPTR45 */ - union iodefine_reg32_t TMDF045; /* TMDF045 */ - union iodefine_reg32_t TMDF145; /* TMDF145 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID46; /* TMID46 */ - union iodefine_reg32_t TMPTR46; /* TMPTR46 */ - union iodefine_reg32_t TMDF046; /* TMDF046 */ - union iodefine_reg32_t TMDF146; /* TMDF146 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID47; /* TMID47 */ - union iodefine_reg32_t TMPTR47; /* TMPTR47 */ - union iodefine_reg32_t TMDF047; /* TMDF047 */ - union iodefine_reg32_t TMDF147; /* TMDF147 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID48; /* TMID48 */ - union iodefine_reg32_t TMPTR48; /* TMPTR48 */ - union iodefine_reg32_t TMDF048; /* TMDF048 */ - union iodefine_reg32_t TMDF148; /* TMDF148 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID49; /* TMID49 */ - union iodefine_reg32_t TMPTR49; /* TMPTR49 */ - union iodefine_reg32_t TMDF049; /* TMDF049 */ - union iodefine_reg32_t TMDF149; /* TMDF149 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID50; /* TMID50 */ - union iodefine_reg32_t TMPTR50; /* TMPTR50 */ - union iodefine_reg32_t TMDF050; /* TMDF050 */ - union iodefine_reg32_t TMDF150; /* TMDF150 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID51; /* TMID51 */ - union iodefine_reg32_t TMPTR51; /* TMPTR51 */ - union iodefine_reg32_t TMDF051; /* TMDF051 */ - union iodefine_reg32_t TMDF151; /* TMDF151 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID52; /* TMID52 */ - union iodefine_reg32_t TMPTR52; /* TMPTR52 */ - union iodefine_reg32_t TMDF052; /* TMDF052 */ - union iodefine_reg32_t TMDF152; /* TMDF152 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID53; /* TMID53 */ - union iodefine_reg32_t TMPTR53; /* TMPTR53 */ - union iodefine_reg32_t TMDF053; /* TMDF053 */ - union iodefine_reg32_t TMDF153; /* TMDF153 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID54; /* TMID54 */ - union iodefine_reg32_t TMPTR54; /* TMPTR54 */ - union iodefine_reg32_t TMDF054; /* TMDF054 */ - union iodefine_reg32_t TMDF154; /* TMDF154 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID55; /* TMID55 */ - union iodefine_reg32_t TMPTR55; /* TMPTR55 */ - union iodefine_reg32_t TMDF055; /* TMDF055 */ - union iodefine_reg32_t TMDF155; /* TMDF155 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID56; /* TMID56 */ - union iodefine_reg32_t TMPTR56; /* TMPTR56 */ - union iodefine_reg32_t TMDF056; /* TMDF056 */ - union iodefine_reg32_t TMDF156; /* TMDF156 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID57; /* TMID57 */ - union iodefine_reg32_t TMPTR57; /* TMPTR57 */ - union iodefine_reg32_t TMDF057; /* TMDF057 */ - union iodefine_reg32_t TMDF157; /* TMDF157 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID58; /* TMID58 */ - union iodefine_reg32_t TMPTR58; /* TMPTR58 */ - union iodefine_reg32_t TMDF058; /* TMDF058 */ - union iodefine_reg32_t TMDF158; /* TMDF158 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID59; /* TMID59 */ - union iodefine_reg32_t TMPTR59; /* TMPTR59 */ - union iodefine_reg32_t TMDF059; /* TMDF059 */ - union iodefine_reg32_t TMDF159; /* TMDF159 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID60; /* TMID60 */ - union iodefine_reg32_t TMPTR60; /* TMPTR60 */ - union iodefine_reg32_t TMDF060; /* TMDF060 */ - union iodefine_reg32_t TMDF160; /* TMDF160 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID61; /* TMID61 */ - union iodefine_reg32_t TMPTR61; /* TMPTR61 */ - union iodefine_reg32_t TMDF061; /* TMDF061 */ - union iodefine_reg32_t TMDF161; /* TMDF161 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID62; /* TMID62 */ - union iodefine_reg32_t TMPTR62; /* TMPTR62 */ - union iodefine_reg32_t TMDF062; /* TMDF062 */ - union iodefine_reg32_t TMDF162; /* TMDF162 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID63; /* TMID63 */ - union iodefine_reg32_t TMPTR63; /* TMPTR63 */ - union iodefine_reg32_t TMDF063; /* TMDF063 */ - union iodefine_reg32_t TMDF163; /* TMDF163 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID64; /* TMID64 */ - union iodefine_reg32_t TMPTR64; /* TMPTR64 */ - union iodefine_reg32_t TMDF064; /* TMDF064 */ - union iodefine_reg32_t TMDF164; /* TMDF164 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID65; /* TMID65 */ - union iodefine_reg32_t TMPTR65; /* TMPTR65 */ - union iodefine_reg32_t TMDF065; /* TMDF065 */ - union iodefine_reg32_t TMDF165; /* TMDF165 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID66; /* TMID66 */ - union iodefine_reg32_t TMPTR66; /* TMPTR66 */ - union iodefine_reg32_t TMDF066; /* TMDF066 */ - union iodefine_reg32_t TMDF166; /* TMDF166 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID67; /* TMID67 */ - union iodefine_reg32_t TMPTR67; /* TMPTR67 */ - union iodefine_reg32_t TMDF067; /* TMDF067 */ - union iodefine_reg32_t TMDF167; /* TMDF167 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID68; /* TMID68 */ - union iodefine_reg32_t TMPTR68; /* TMPTR68 */ - union iodefine_reg32_t TMDF068; /* TMDF068 */ - union iodefine_reg32_t TMDF168; /* TMDF168 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID69; /* TMID69 */ - union iodefine_reg32_t TMPTR69; /* TMPTR69 */ - union iodefine_reg32_t TMDF069; /* TMDF069 */ - union iodefine_reg32_t TMDF169; /* TMDF169 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID70; /* TMID70 */ - union iodefine_reg32_t TMPTR70; /* TMPTR70 */ - union iodefine_reg32_t TMDF070; /* TMDF070 */ - union iodefine_reg32_t TMDF170; /* TMDF170 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID71; /* TMID71 */ - union iodefine_reg32_t TMPTR71; /* TMPTR71 */ - union iodefine_reg32_t TMDF071; /* TMDF071 */ - union iodefine_reg32_t TMDF171; /* TMDF171 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID72; /* TMID72 */ - union iodefine_reg32_t TMPTR72; /* TMPTR72 */ - union iodefine_reg32_t TMDF072; /* TMDF072 */ - union iodefine_reg32_t TMDF172; /* TMDF172 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID73; /* TMID73 */ - union iodefine_reg32_t TMPTR73; /* TMPTR73 */ - union iodefine_reg32_t TMDF073; /* TMDF073 */ - union iodefine_reg32_t TMDF173; /* TMDF173 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID74; /* TMID74 */ - union iodefine_reg32_t TMPTR74; /* TMPTR74 */ - union iodefine_reg32_t TMDF074; /* TMDF074 */ - union iodefine_reg32_t TMDF174; /* TMDF174 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID75; /* TMID75 */ - union iodefine_reg32_t TMPTR75; /* TMPTR75 */ - union iodefine_reg32_t TMDF075; /* TMDF075 */ - union iodefine_reg32_t TMDF175; /* TMDF175 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID76; /* TMID76 */ - union iodefine_reg32_t TMPTR76; /* TMPTR76 */ - union iodefine_reg32_t TMDF076; /* TMDF076 */ - union iodefine_reg32_t TMDF176; /* TMDF176 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID77; /* TMID77 */ - union iodefine_reg32_t TMPTR77; /* TMPTR77 */ - union iodefine_reg32_t TMDF077; /* TMDF077 */ - union iodefine_reg32_t TMDF177; /* TMDF177 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID78; /* TMID78 */ - union iodefine_reg32_t TMPTR78; /* TMPTR78 */ - union iodefine_reg32_t TMDF078; /* TMDF078 */ - union iodefine_reg32_t TMDF178; /* TMDF178 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID79; /* TMID79 */ - union iodefine_reg32_t TMPTR79; /* TMPTR79 */ - union iodefine_reg32_t TMDF079; /* TMDF079 */ - union iodefine_reg32_t TMDF179; /* TMDF179 */ -/* end of struct st_rscan_from_rscan0tmidp */ - - volatile uint8_t dummy181[768]; /* */ -#define RSCAN0_THLACC0_COUNT 5 - union iodefine_reg32_t THLACC0; /* THLACC0 */ - union iodefine_reg32_t THLACC1; /* THLACC1 */ - union iodefine_reg32_t THLACC2; /* THLACC2 */ - union iodefine_reg32_t THLACC3; /* THLACC3 */ - union iodefine_reg32_t THLACC4; /* THLACC4 */ - -}; - - -struct st_rscan_from_rscan0cncfg -{ - union iodefine_reg32_t CnCFG; /* CnCFG */ - union iodefine_reg32_t CnCTR; /* CnCTR */ - union iodefine_reg32_t CnSTS; /* CnSTS */ - union iodefine_reg32_t CnERFL; /* CnERFL */ -}; - - -struct st_rscan_from_rscan0gaflidj -{ - union iodefine_reg32_t GAFLIDj; /* GAFLIDj */ - union iodefine_reg32_t GAFLMj; /* GAFLMj */ - union iodefine_reg32_t GAFLP0j; /* GAFLP0j */ - union iodefine_reg32_t GAFLP1j; /* GAFLP1j */ -}; - - -struct st_rscan_from_rscan0rmidp -{ - union iodefine_reg32_t RMIDp; /* RMIDp */ - union iodefine_reg32_t RMPTRp; /* RMPTRp */ - union iodefine_reg32_t RMDF0p; /* RMDF0p */ - union iodefine_reg32_t RMDF1p; /* RMDF1p */ -}; - - -struct st_rscan_from_rscan0rfidm -{ - union iodefine_reg32_t RFIDm; /* RFIDm */ - union iodefine_reg32_t RFPTRm; /* RFPTRm */ - union iodefine_reg32_t RFDF0m; /* RFDF0m */ - union iodefine_reg32_t RFDF1m; /* RFDF1m */ -}; - - -struct st_rscan_from_rscan0tmidp -{ - union iodefine_reg32_t TMIDp; /* TMIDp */ - union iodefine_reg32_t TMPTRp; /* TMPTRp */ - union iodefine_reg32_t TMDF0p; /* TMDF0p */ - union iodefine_reg32_t TMDF1p; /* TMDF1p */ -}; - - -struct st_rscan_from_rscan0cfidm -{ - union iodefine_reg32_t CFIDm; /* CFIDm */ - union iodefine_reg32_t CFPTRm; /* CFPTRm */ - union iodefine_reg32_t CFDF0m; /* CFDF0m */ - union iodefine_reg32_t CFDF1m; /* CFDF1m */ -}; - - #define RSCAN0 (*(struct st_rscan0 *)0xE803A000uL) /* RSCAN0 */ -/* Start of channnel array defines of RSCAN0 */ +/* Start of channel array defines of RSCAN0 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */ -/*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */ -#define RSCAN_FROM_RSCAN0CFIDm_COUNT 15 -#define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_CFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0_CFIDm[ channel ]->CFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0_CFIDm_COUNT (15) +#define RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \ &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \ @@ -1919,10 +63,10 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */ -/*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */ -#define RSCAN_FROM_RSCAN0TMIDp_COUNT 80 -#define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_TMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0_TMIDp[ channel ]->TMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0_TMIDp_COUNT (80) +#define RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \ &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \ @@ -2017,10 +161,10 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */ -/*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */ -#define RSCAN_FROM_RSCAN0RFIDm_COUNT 8 -#define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_RFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0_RFIDm[ channel ]->RFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0_RFIDm_COUNT (8) +#define RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ @@ -2034,10 +178,10 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */ -/*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */ -#define RSCAN_FROM_RSCAN0RMIDp_COUNT 80 -#define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_RMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0_RMIDp[ channel ]->RMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0_RMIDp_COUNT (80) +#define RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \ &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \ @@ -2132,10 +276,10 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */ -/*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */ -#define RSCAN_FROM_RSCAN0GAFLIDj_COUNT 16 -#define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_GAFLIDj */ +/*(Sample) value = RSCAN_FROM_RSCAN0_GAFLIDj[ channel ]->GAFLIDj.UINT32; */ +#define RSCAN_FROM_RSCAN0_GAFLIDj_COUNT (16) +#define RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \ &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \ @@ -2158,10 +302,10 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */ -/*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */ -#define RSCAN_FROM_RSCAN0CnCFG_COUNT 5 -#define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_CnCFG */ +/*(Sample) value = RSCAN_FROM_RSCAN0_CnCFG[ channel ]->CnCFG.UINT32; */ +#define RSCAN_FROM_RSCAN0_CnCFG_COUNT (5) +#define RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ @@ -2171,6868 +315,9032 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */ #define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */ -/* End of channnel array defines of RSCAN0 */ +/* End of channel array defines of RSCAN0 */ + + +#define RSCAN0C0CFG (RSCAN0.C0CFG.UINT32) +#define RSCAN0C0CFGL (RSCAN0.C0CFG.UINT16[R_IO_L]) +#define RSCAN0C0CFGLL (RSCAN0.C0CFG.UINT8[R_IO_LL]) +#define RSCAN0C0CFGLH (RSCAN0.C0CFG.UINT8[R_IO_LH]) +#define RSCAN0C0CFGH (RSCAN0.C0CFG.UINT16[R_IO_H]) +#define RSCAN0C0CFGHL (RSCAN0.C0CFG.UINT8[R_IO_HL]) +#define RSCAN0C0CFGHH (RSCAN0.C0CFG.UINT8[R_IO_HH]) +#define RSCAN0C0CTR (RSCAN0.C0CTR.UINT32) +#define RSCAN0C0CTRL (RSCAN0.C0CTR.UINT16[R_IO_L]) +#define RSCAN0C0CTRLL (RSCAN0.C0CTR.UINT8[R_IO_LL]) +#define RSCAN0C0CTRLH (RSCAN0.C0CTR.UINT8[R_IO_LH]) +#define RSCAN0C0CTRH (RSCAN0.C0CTR.UINT16[R_IO_H]) +#define RSCAN0C0CTRHL (RSCAN0.C0CTR.UINT8[R_IO_HL]) +#define RSCAN0C0CTRHH (RSCAN0.C0CTR.UINT8[R_IO_HH]) +#define RSCAN0C0STS (RSCAN0.C0STS.UINT32) +#define RSCAN0C0STSL (RSCAN0.C0STS.UINT16[R_IO_L]) +#define RSCAN0C0STSLL (RSCAN0.C0STS.UINT8[R_IO_LL]) +#define RSCAN0C0STSLH (RSCAN0.C0STS.UINT8[R_IO_LH]) +#define RSCAN0C0STSH (RSCAN0.C0STS.UINT16[R_IO_H]) +#define RSCAN0C0STSHL (RSCAN0.C0STS.UINT8[R_IO_HL]) +#define RSCAN0C0STSHH (RSCAN0.C0STS.UINT8[R_IO_HH]) +#define RSCAN0C0ERFL (RSCAN0.C0ERFL.UINT32) +#define RSCAN0C0ERFLL (RSCAN0.C0ERFL.UINT16[R_IO_L]) +#define RSCAN0C0ERFLLL (RSCAN0.C0ERFL.UINT8[R_IO_LL]) +#define RSCAN0C0ERFLLH (RSCAN0.C0ERFL.UINT8[R_IO_LH]) +#define RSCAN0C0ERFLH (RSCAN0.C0ERFL.UINT16[R_IO_H]) +#define RSCAN0C0ERFLHL (RSCAN0.C0ERFL.UINT8[R_IO_HL]) +#define RSCAN0C0ERFLHH (RSCAN0.C0ERFL.UINT8[R_IO_HH]) +#define RSCAN0C1CFG (RSCAN0.C1CFG.UINT32) +#define RSCAN0C1CFGL (RSCAN0.C1CFG.UINT16[R_IO_L]) +#define RSCAN0C1CFGLL (RSCAN0.C1CFG.UINT8[R_IO_LL]) +#define RSCAN0C1CFGLH (RSCAN0.C1CFG.UINT8[R_IO_LH]) +#define RSCAN0C1CFGH (RSCAN0.C1CFG.UINT16[R_IO_H]) +#define RSCAN0C1CFGHL (RSCAN0.C1CFG.UINT8[R_IO_HL]) +#define RSCAN0C1CFGHH (RSCAN0.C1CFG.UINT8[R_IO_HH]) +#define RSCAN0C1CTR (RSCAN0.C1CTR.UINT32) +#define RSCAN0C1CTRL (RSCAN0.C1CTR.UINT16[R_IO_L]) +#define RSCAN0C1CTRLL (RSCAN0.C1CTR.UINT8[R_IO_LL]) +#define RSCAN0C1CTRLH (RSCAN0.C1CTR.UINT8[R_IO_LH]) +#define RSCAN0C1CTRH (RSCAN0.C1CTR.UINT16[R_IO_H]) +#define RSCAN0C1CTRHL (RSCAN0.C1CTR.UINT8[R_IO_HL]) +#define RSCAN0C1CTRHH (RSCAN0.C1CTR.UINT8[R_IO_HH]) +#define RSCAN0C1STS (RSCAN0.C1STS.UINT32) +#define RSCAN0C1STSL (RSCAN0.C1STS.UINT16[R_IO_L]) +#define RSCAN0C1STSLL (RSCAN0.C1STS.UINT8[R_IO_LL]) +#define RSCAN0C1STSLH (RSCAN0.C1STS.UINT8[R_IO_LH]) +#define RSCAN0C1STSH (RSCAN0.C1STS.UINT16[R_IO_H]) +#define RSCAN0C1STSHL (RSCAN0.C1STS.UINT8[R_IO_HL]) +#define RSCAN0C1STSHH (RSCAN0.C1STS.UINT8[R_IO_HH]) +#define RSCAN0C1ERFL (RSCAN0.C1ERFL.UINT32) +#define RSCAN0C1ERFLL (RSCAN0.C1ERFL.UINT16[R_IO_L]) +#define RSCAN0C1ERFLLL (RSCAN0.C1ERFL.UINT8[R_IO_LL]) +#define RSCAN0C1ERFLLH (RSCAN0.C1ERFL.UINT8[R_IO_LH]) +#define RSCAN0C1ERFLH (RSCAN0.C1ERFL.UINT16[R_IO_H]) +#define RSCAN0C1ERFLHL (RSCAN0.C1ERFL.UINT8[R_IO_HL]) +#define RSCAN0C1ERFLHH (RSCAN0.C1ERFL.UINT8[R_IO_HH]) +#define RSCAN0C2CFG (RSCAN0.C2CFG.UINT32) +#define RSCAN0C2CFGL (RSCAN0.C2CFG.UINT16[R_IO_L]) +#define RSCAN0C2CFGLL (RSCAN0.C2CFG.UINT8[R_IO_LL]) +#define RSCAN0C2CFGLH (RSCAN0.C2CFG.UINT8[R_IO_LH]) +#define RSCAN0C2CFGH (RSCAN0.C2CFG.UINT16[R_IO_H]) +#define RSCAN0C2CFGHL (RSCAN0.C2CFG.UINT8[R_IO_HL]) +#define RSCAN0C2CFGHH (RSCAN0.C2CFG.UINT8[R_IO_HH]) +#define RSCAN0C2CTR (RSCAN0.C2CTR.UINT32) +#define RSCAN0C2CTRL (RSCAN0.C2CTR.UINT16[R_IO_L]) +#define RSCAN0C2CTRLL (RSCAN0.C2CTR.UINT8[R_IO_LL]) +#define RSCAN0C2CTRLH (RSCAN0.C2CTR.UINT8[R_IO_LH]) +#define RSCAN0C2CTRH (RSCAN0.C2CTR.UINT16[R_IO_H]) +#define RSCAN0C2CTRHL (RSCAN0.C2CTR.UINT8[R_IO_HL]) +#define RSCAN0C2CTRHH (RSCAN0.C2CTR.UINT8[R_IO_HH]) +#define RSCAN0C2STS (RSCAN0.C2STS.UINT32) +#define RSCAN0C2STSL (RSCAN0.C2STS.UINT16[R_IO_L]) +#define RSCAN0C2STSLL (RSCAN0.C2STS.UINT8[R_IO_LL]) +#define RSCAN0C2STSLH (RSCAN0.C2STS.UINT8[R_IO_LH]) +#define RSCAN0C2STSH (RSCAN0.C2STS.UINT16[R_IO_H]) +#define RSCAN0C2STSHL (RSCAN0.C2STS.UINT8[R_IO_HL]) +#define RSCAN0C2STSHH (RSCAN0.C2STS.UINT8[R_IO_HH]) +#define RSCAN0C2ERFL (RSCAN0.C2ERFL.UINT32) +#define RSCAN0C2ERFLL (RSCAN0.C2ERFL.UINT16[R_IO_L]) +#define RSCAN0C2ERFLLL (RSCAN0.C2ERFL.UINT8[R_IO_LL]) +#define RSCAN0C2ERFLLH (RSCAN0.C2ERFL.UINT8[R_IO_LH]) +#define RSCAN0C2ERFLH (RSCAN0.C2ERFL.UINT16[R_IO_H]) +#define RSCAN0C2ERFLHL (RSCAN0.C2ERFL.UINT8[R_IO_HL]) +#define RSCAN0C2ERFLHH (RSCAN0.C2ERFL.UINT8[R_IO_HH]) +#define RSCAN0C3CFG (RSCAN0.C3CFG.UINT32) +#define RSCAN0C3CFGL (RSCAN0.C3CFG.UINT16[R_IO_L]) +#define RSCAN0C3CFGLL (RSCAN0.C3CFG.UINT8[R_IO_LL]) +#define RSCAN0C3CFGLH (RSCAN0.C3CFG.UINT8[R_IO_LH]) +#define RSCAN0C3CFGH (RSCAN0.C3CFG.UINT16[R_IO_H]) +#define RSCAN0C3CFGHL (RSCAN0.C3CFG.UINT8[R_IO_HL]) +#define RSCAN0C3CFGHH (RSCAN0.C3CFG.UINT8[R_IO_HH]) +#define RSCAN0C3CTR (RSCAN0.C3CTR.UINT32) +#define RSCAN0C3CTRL (RSCAN0.C3CTR.UINT16[R_IO_L]) +#define RSCAN0C3CTRLL (RSCAN0.C3CTR.UINT8[R_IO_LL]) +#define RSCAN0C3CTRLH (RSCAN0.C3CTR.UINT8[R_IO_LH]) +#define RSCAN0C3CTRH (RSCAN0.C3CTR.UINT16[R_IO_H]) +#define RSCAN0C3CTRHL (RSCAN0.C3CTR.UINT8[R_IO_HL]) +#define RSCAN0C3CTRHH (RSCAN0.C3CTR.UINT8[R_IO_HH]) +#define RSCAN0C3STS (RSCAN0.C3STS.UINT32) +#define RSCAN0C3STSL (RSCAN0.C3STS.UINT16[R_IO_L]) +#define RSCAN0C3STSLL (RSCAN0.C3STS.UINT8[R_IO_LL]) +#define RSCAN0C3STSLH (RSCAN0.C3STS.UINT8[R_IO_LH]) +#define RSCAN0C3STSH (RSCAN0.C3STS.UINT16[R_IO_H]) +#define RSCAN0C3STSHL (RSCAN0.C3STS.UINT8[R_IO_HL]) +#define RSCAN0C3STSHH (RSCAN0.C3STS.UINT8[R_IO_HH]) +#define RSCAN0C3ERFL (RSCAN0.C3ERFL.UINT32) +#define RSCAN0C3ERFLL (RSCAN0.C3ERFL.UINT16[R_IO_L]) +#define RSCAN0C3ERFLLL (RSCAN0.C3ERFL.UINT8[R_IO_LL]) +#define RSCAN0C3ERFLLH (RSCAN0.C3ERFL.UINT8[R_IO_LH]) +#define RSCAN0C3ERFLH (RSCAN0.C3ERFL.UINT16[R_IO_H]) +#define RSCAN0C3ERFLHL (RSCAN0.C3ERFL.UINT8[R_IO_HL]) +#define RSCAN0C3ERFLHH (RSCAN0.C3ERFL.UINT8[R_IO_HH]) +#define RSCAN0C4CFG (RSCAN0.C4CFG.UINT32) +#define RSCAN0C4CFGL (RSCAN0.C4CFG.UINT16[R_IO_L]) +#define RSCAN0C4CFGLL (RSCAN0.C4CFG.UINT8[R_IO_LL]) +#define RSCAN0C4CFGLH (RSCAN0.C4CFG.UINT8[R_IO_LH]) +#define RSCAN0C4CFGH (RSCAN0.C4CFG.UINT16[R_IO_H]) +#define RSCAN0C4CFGHL (RSCAN0.C4CFG.UINT8[R_IO_HL]) +#define RSCAN0C4CFGHH (RSCAN0.C4CFG.UINT8[R_IO_HH]) +#define RSCAN0C4CTR (RSCAN0.C4CTR.UINT32) +#define RSCAN0C4CTRL (RSCAN0.C4CTR.UINT16[R_IO_L]) +#define RSCAN0C4CTRLL (RSCAN0.C4CTR.UINT8[R_IO_LL]) +#define RSCAN0C4CTRLH (RSCAN0.C4CTR.UINT8[R_IO_LH]) +#define RSCAN0C4CTRH (RSCAN0.C4CTR.UINT16[R_IO_H]) +#define RSCAN0C4CTRHL (RSCAN0.C4CTR.UINT8[R_IO_HL]) +#define RSCAN0C4CTRHH (RSCAN0.C4CTR.UINT8[R_IO_HH]) +#define RSCAN0C4STS (RSCAN0.C4STS.UINT32) +#define RSCAN0C4STSL (RSCAN0.C4STS.UINT16[R_IO_L]) +#define RSCAN0C4STSLL (RSCAN0.C4STS.UINT8[R_IO_LL]) +#define RSCAN0C4STSLH (RSCAN0.C4STS.UINT8[R_IO_LH]) +#define RSCAN0C4STSH (RSCAN0.C4STS.UINT16[R_IO_H]) +#define RSCAN0C4STSHL (RSCAN0.C4STS.UINT8[R_IO_HL]) +#define RSCAN0C4STSHH (RSCAN0.C4STS.UINT8[R_IO_HH]) +#define RSCAN0C4ERFL (RSCAN0.C4ERFL.UINT32) +#define RSCAN0C4ERFLL (RSCAN0.C4ERFL.UINT16[R_IO_L]) +#define RSCAN0C4ERFLLL (RSCAN0.C4ERFL.UINT8[R_IO_LL]) +#define RSCAN0C4ERFLLH (RSCAN0.C4ERFL.UINT8[R_IO_LH]) +#define RSCAN0C4ERFLH (RSCAN0.C4ERFL.UINT16[R_IO_H]) +#define RSCAN0C4ERFLHL (RSCAN0.C4ERFL.UINT8[R_IO_HL]) +#define RSCAN0C4ERFLHH (RSCAN0.C4ERFL.UINT8[R_IO_HH]) +#define RSCAN0GCFG (RSCAN0.GCFG.UINT32) +#define RSCAN0GCFGL (RSCAN0.GCFG.UINT16[R_IO_L]) +#define RSCAN0GCFGLL (RSCAN0.GCFG.UINT8[R_IO_LL]) +#define RSCAN0GCFGLH (RSCAN0.GCFG.UINT8[R_IO_LH]) +#define RSCAN0GCFGH (RSCAN0.GCFG.UINT16[R_IO_H]) +#define RSCAN0GCFGHL (RSCAN0.GCFG.UINT8[R_IO_HL]) +#define RSCAN0GCFGHH (RSCAN0.GCFG.UINT8[R_IO_HH]) +#define RSCAN0GCTR (RSCAN0.GCTR.UINT32) +#define RSCAN0GCTRL (RSCAN0.GCTR.UINT16[R_IO_L]) +#define RSCAN0GCTRLL (RSCAN0.GCTR.UINT8[R_IO_LL]) +#define RSCAN0GCTRLH (RSCAN0.GCTR.UINT8[R_IO_LH]) +#define RSCAN0GCTRH (RSCAN0.GCTR.UINT16[R_IO_H]) +#define RSCAN0GCTRHL (RSCAN0.GCTR.UINT8[R_IO_HL]) +#define RSCAN0GCTRHH (RSCAN0.GCTR.UINT8[R_IO_HH]) +#define RSCAN0GSTS (RSCAN0.GSTS.UINT32) +#define RSCAN0GSTSL (RSCAN0.GSTS.UINT16[R_IO_L]) +#define RSCAN0GSTSLL (RSCAN0.GSTS.UINT8[R_IO_LL]) +#define RSCAN0GSTSLH (RSCAN0.GSTS.UINT8[R_IO_LH]) +#define RSCAN0GSTSH (RSCAN0.GSTS.UINT16[R_IO_H]) +#define RSCAN0GSTSHL (RSCAN0.GSTS.UINT8[R_IO_HL]) +#define RSCAN0GSTSHH (RSCAN0.GSTS.UINT8[R_IO_HH]) +#define RSCAN0GERFL (RSCAN0.GERFL.UINT32) +#define RSCAN0GERFLL (RSCAN0.GERFL.UINT16[R_IO_L]) +#define RSCAN0GERFLLL (RSCAN0.GERFL.UINT8[R_IO_LL]) +#define RSCAN0GERFLLH (RSCAN0.GERFL.UINT8[R_IO_LH]) +#define RSCAN0GERFLH (RSCAN0.GERFL.UINT16[R_IO_H]) +#define RSCAN0GERFLHL (RSCAN0.GERFL.UINT8[R_IO_HL]) +#define RSCAN0GERFLHH (RSCAN0.GERFL.UINT8[R_IO_HH]) +#define RSCAN0GTSC (RSCAN0.GTSC.UINT32) +#define RSCAN0GTSCL (RSCAN0.GTSC.UINT16[R_IO_L]) +#define RSCAN0GTSCH (RSCAN0.GTSC.UINT16[R_IO_H]) +#define RSCAN0GAFLECTR (RSCAN0.GAFLECTR.UINT32) +#define RSCAN0GAFLECTRL (RSCAN0.GAFLECTR.UINT16[R_IO_L]) +#define RSCAN0GAFLECTRLL (RSCAN0.GAFLECTR.UINT8[R_IO_LL]) +#define RSCAN0GAFLECTRLH (RSCAN0.GAFLECTR.UINT8[R_IO_LH]) +#define RSCAN0GAFLECTRH (RSCAN0.GAFLECTR.UINT16[R_IO_H]) +#define RSCAN0GAFLECTRHL (RSCAN0.GAFLECTR.UINT8[R_IO_HL]) +#define RSCAN0GAFLECTRHH (RSCAN0.GAFLECTR.UINT8[R_IO_HH]) +#define RSCAN0GAFLCFG0 (RSCAN0.GAFLCFG0.UINT32) +#define RSCAN0GAFLCFG0L (RSCAN0.GAFLCFG0.UINT16[R_IO_L]) +#define RSCAN0GAFLCFG0LL (RSCAN0.GAFLCFG0.UINT8[R_IO_LL]) +#define RSCAN0GAFLCFG0LH (RSCAN0.GAFLCFG0.UINT8[R_IO_LH]) +#define RSCAN0GAFLCFG0H (RSCAN0.GAFLCFG0.UINT16[R_IO_H]) +#define RSCAN0GAFLCFG0HL (RSCAN0.GAFLCFG0.UINT8[R_IO_HL]) +#define RSCAN0GAFLCFG0HH (RSCAN0.GAFLCFG0.UINT8[R_IO_HH]) +#define RSCAN0GAFLCFG1 (RSCAN0.GAFLCFG1.UINT32) +#define RSCAN0GAFLCFG1L (RSCAN0.GAFLCFG1.UINT16[R_IO_L]) +#define RSCAN0GAFLCFG1LL (RSCAN0.GAFLCFG1.UINT8[R_IO_LL]) +#define RSCAN0GAFLCFG1LH (RSCAN0.GAFLCFG1.UINT8[R_IO_LH]) +#define RSCAN0GAFLCFG1H (RSCAN0.GAFLCFG1.UINT16[R_IO_H]) +#define RSCAN0GAFLCFG1HL (RSCAN0.GAFLCFG1.UINT8[R_IO_HL]) +#define RSCAN0GAFLCFG1HH (RSCAN0.GAFLCFG1.UINT8[R_IO_HH]) +#define RSCAN0RMNB (RSCAN0.RMNB.UINT32) +#define RSCAN0RMNBL (RSCAN0.RMNB.UINT16[R_IO_L]) +#define RSCAN0RMNBLL (RSCAN0.RMNB.UINT8[R_IO_LL]) +#define RSCAN0RMNBLH (RSCAN0.RMNB.UINT8[R_IO_LH]) +#define RSCAN0RMNBH (RSCAN0.RMNB.UINT16[R_IO_H]) +#define RSCAN0RMNBHL (RSCAN0.RMNB.UINT8[R_IO_HL]) +#define RSCAN0RMNBHH (RSCAN0.RMNB.UINT8[R_IO_HH]) +#define RSCAN0RMND0 (RSCAN0.RMND0.UINT32) +#define RSCAN0RMND0L (RSCAN0.RMND0.UINT16[R_IO_L]) +#define RSCAN0RMND0LL (RSCAN0.RMND0.UINT8[R_IO_LL]) +#define RSCAN0RMND0LH (RSCAN0.RMND0.UINT8[R_IO_LH]) +#define RSCAN0RMND0H (RSCAN0.RMND0.UINT16[R_IO_H]) +#define RSCAN0RMND0HL (RSCAN0.RMND0.UINT8[R_IO_HL]) +#define RSCAN0RMND0HH (RSCAN0.RMND0.UINT8[R_IO_HH]) +#define RSCAN0RMND1 (RSCAN0.RMND1.UINT32) +#define RSCAN0RMND1L (RSCAN0.RMND1.UINT16[R_IO_L]) +#define RSCAN0RMND1LL (RSCAN0.RMND1.UINT8[R_IO_LL]) +#define RSCAN0RMND1LH (RSCAN0.RMND1.UINT8[R_IO_LH]) +#define RSCAN0RMND1H (RSCAN0.RMND1.UINT16[R_IO_H]) +#define RSCAN0RMND1HL (RSCAN0.RMND1.UINT8[R_IO_HL]) +#define RSCAN0RMND1HH (RSCAN0.RMND1.UINT8[R_IO_HH]) +#define RSCAN0RMND2 (RSCAN0.RMND2.UINT32) +#define RSCAN0RMND2L (RSCAN0.RMND2.UINT16[R_IO_L]) +#define RSCAN0RMND2LL (RSCAN0.RMND2.UINT8[R_IO_LL]) +#define RSCAN0RMND2LH (RSCAN0.RMND2.UINT8[R_IO_LH]) +#define RSCAN0RMND2H (RSCAN0.RMND2.UINT16[R_IO_H]) +#define RSCAN0RMND2HL (RSCAN0.RMND2.UINT8[R_IO_HL]) +#define RSCAN0RMND2HH (RSCAN0.RMND2.UINT8[R_IO_HH]) +#define RSCAN0RFCC0 (RSCAN0.RFCC0.UINT32) +#define RSCAN0RFCC0L (RSCAN0.RFCC0.UINT16[R_IO_L]) +#define RSCAN0RFCC0LL (RSCAN0.RFCC0.UINT8[R_IO_LL]) +#define RSCAN0RFCC0LH (RSCAN0.RFCC0.UINT8[R_IO_LH]) +#define RSCAN0RFCC0H (RSCAN0.RFCC0.UINT16[R_IO_H]) +#define RSCAN0RFCC0HL (RSCAN0.RFCC0.UINT8[R_IO_HL]) +#define RSCAN0RFCC0HH (RSCAN0.RFCC0.UINT8[R_IO_HH]) +#define RSCAN0RFCC1 (RSCAN0.RFCC1.UINT32) +#define RSCAN0RFCC1L (RSCAN0.RFCC1.UINT16[R_IO_L]) +#define RSCAN0RFCC1LL (RSCAN0.RFCC1.UINT8[R_IO_LL]) +#define RSCAN0RFCC1LH (RSCAN0.RFCC1.UINT8[R_IO_LH]) +#define RSCAN0RFCC1H (RSCAN0.RFCC1.UINT16[R_IO_H]) +#define RSCAN0RFCC1HL (RSCAN0.RFCC1.UINT8[R_IO_HL]) +#define RSCAN0RFCC1HH (RSCAN0.RFCC1.UINT8[R_IO_HH]) +#define RSCAN0RFCC2 (RSCAN0.RFCC2.UINT32) +#define RSCAN0RFCC2L (RSCAN0.RFCC2.UINT16[R_IO_L]) +#define RSCAN0RFCC2LL (RSCAN0.RFCC2.UINT8[R_IO_LL]) +#define RSCAN0RFCC2LH (RSCAN0.RFCC2.UINT8[R_IO_LH]) +#define RSCAN0RFCC2H (RSCAN0.RFCC2.UINT16[R_IO_H]) +#define RSCAN0RFCC2HL (RSCAN0.RFCC2.UINT8[R_IO_HL]) +#define RSCAN0RFCC2HH (RSCAN0.RFCC2.UINT8[R_IO_HH]) +#define RSCAN0RFCC3 (RSCAN0.RFCC3.UINT32) +#define RSCAN0RFCC3L (RSCAN0.RFCC3.UINT16[R_IO_L]) +#define RSCAN0RFCC3LL (RSCAN0.RFCC3.UINT8[R_IO_LL]) +#define RSCAN0RFCC3LH (RSCAN0.RFCC3.UINT8[R_IO_LH]) +#define RSCAN0RFCC3H (RSCAN0.RFCC3.UINT16[R_IO_H]) +#define RSCAN0RFCC3HL (RSCAN0.RFCC3.UINT8[R_IO_HL]) +#define RSCAN0RFCC3HH (RSCAN0.RFCC3.UINT8[R_IO_HH]) +#define RSCAN0RFCC4 (RSCAN0.RFCC4.UINT32) +#define RSCAN0RFCC4L (RSCAN0.RFCC4.UINT16[R_IO_L]) +#define RSCAN0RFCC4LL (RSCAN0.RFCC4.UINT8[R_IO_LL]) +#define RSCAN0RFCC4LH (RSCAN0.RFCC4.UINT8[R_IO_LH]) +#define RSCAN0RFCC4H (RSCAN0.RFCC4.UINT16[R_IO_H]) +#define RSCAN0RFCC4HL (RSCAN0.RFCC4.UINT8[R_IO_HL]) +#define RSCAN0RFCC4HH (RSCAN0.RFCC4.UINT8[R_IO_HH]) +#define RSCAN0RFCC5 (RSCAN0.RFCC5.UINT32) +#define RSCAN0RFCC5L (RSCAN0.RFCC5.UINT16[R_IO_L]) +#define RSCAN0RFCC5LL (RSCAN0.RFCC5.UINT8[R_IO_LL]) +#define RSCAN0RFCC5LH (RSCAN0.RFCC5.UINT8[R_IO_LH]) +#define RSCAN0RFCC5H (RSCAN0.RFCC5.UINT16[R_IO_H]) +#define RSCAN0RFCC5HL (RSCAN0.RFCC5.UINT8[R_IO_HL]) +#define RSCAN0RFCC5HH (RSCAN0.RFCC5.UINT8[R_IO_HH]) +#define RSCAN0RFCC6 (RSCAN0.RFCC6.UINT32) +#define RSCAN0RFCC6L (RSCAN0.RFCC6.UINT16[R_IO_L]) +#define RSCAN0RFCC6LL (RSCAN0.RFCC6.UINT8[R_IO_LL]) +#define RSCAN0RFCC6LH (RSCAN0.RFCC6.UINT8[R_IO_LH]) +#define RSCAN0RFCC6H (RSCAN0.RFCC6.UINT16[R_IO_H]) +#define RSCAN0RFCC6HL (RSCAN0.RFCC6.UINT8[R_IO_HL]) +#define RSCAN0RFCC6HH (RSCAN0.RFCC6.UINT8[R_IO_HH]) +#define RSCAN0RFCC7 (RSCAN0.RFCC7.UINT32) +#define RSCAN0RFCC7L (RSCAN0.RFCC7.UINT16[R_IO_L]) +#define RSCAN0RFCC7LL (RSCAN0.RFCC7.UINT8[R_IO_LL]) +#define RSCAN0RFCC7LH (RSCAN0.RFCC7.UINT8[R_IO_LH]) +#define RSCAN0RFCC7H (RSCAN0.RFCC7.UINT16[R_IO_H]) +#define RSCAN0RFCC7HL (RSCAN0.RFCC7.UINT8[R_IO_HL]) +#define RSCAN0RFCC7HH (RSCAN0.RFCC7.UINT8[R_IO_HH]) +#define RSCAN0RFSTS0 (RSCAN0.RFSTS0.UINT32) +#define RSCAN0RFSTS0L (RSCAN0.RFSTS0.UINT16[R_IO_L]) +#define RSCAN0RFSTS0LL (RSCAN0.RFSTS0.UINT8[R_IO_LL]) +#define RSCAN0RFSTS0LH (RSCAN0.RFSTS0.UINT8[R_IO_LH]) +#define RSCAN0RFSTS0H (RSCAN0.RFSTS0.UINT16[R_IO_H]) +#define RSCAN0RFSTS0HL (RSCAN0.RFSTS0.UINT8[R_IO_HL]) +#define RSCAN0RFSTS0HH (RSCAN0.RFSTS0.UINT8[R_IO_HH]) +#define RSCAN0RFSTS1 (RSCAN0.RFSTS1.UINT32) +#define RSCAN0RFSTS1L (RSCAN0.RFSTS1.UINT16[R_IO_L]) +#define RSCAN0RFSTS1LL (RSCAN0.RFSTS1.UINT8[R_IO_LL]) +#define RSCAN0RFSTS1LH (RSCAN0.RFSTS1.UINT8[R_IO_LH]) +#define RSCAN0RFSTS1H (RSCAN0.RFSTS1.UINT16[R_IO_H]) +#define RSCAN0RFSTS1HL (RSCAN0.RFSTS1.UINT8[R_IO_HL]) +#define RSCAN0RFSTS1HH (RSCAN0.RFSTS1.UINT8[R_IO_HH]) +#define RSCAN0RFSTS2 (RSCAN0.RFSTS2.UINT32) +#define RSCAN0RFSTS2L (RSCAN0.RFSTS2.UINT16[R_IO_L]) +#define RSCAN0RFSTS2LL (RSCAN0.RFSTS2.UINT8[R_IO_LL]) +#define RSCAN0RFSTS2LH (RSCAN0.RFSTS2.UINT8[R_IO_LH]) +#define RSCAN0RFSTS2H (RSCAN0.RFSTS2.UINT16[R_IO_H]) +#define RSCAN0RFSTS2HL (RSCAN0.RFSTS2.UINT8[R_IO_HL]) +#define RSCAN0RFSTS2HH (RSCAN0.RFSTS2.UINT8[R_IO_HH]) +#define RSCAN0RFSTS3 (RSCAN0.RFSTS3.UINT32) +#define RSCAN0RFSTS3L (RSCAN0.RFSTS3.UINT16[R_IO_L]) +#define RSCAN0RFSTS3LL (RSCAN0.RFSTS3.UINT8[R_IO_LL]) +#define RSCAN0RFSTS3LH (RSCAN0.RFSTS3.UINT8[R_IO_LH]) +#define RSCAN0RFSTS3H (RSCAN0.RFSTS3.UINT16[R_IO_H]) +#define RSCAN0RFSTS3HL (RSCAN0.RFSTS3.UINT8[R_IO_HL]) +#define RSCAN0RFSTS3HH (RSCAN0.RFSTS3.UINT8[R_IO_HH]) +#define RSCAN0RFSTS4 (RSCAN0.RFSTS4.UINT32) +#define RSCAN0RFSTS4L (RSCAN0.RFSTS4.UINT16[R_IO_L]) +#define RSCAN0RFSTS4LL (RSCAN0.RFSTS4.UINT8[R_IO_LL]) +#define RSCAN0RFSTS4LH (RSCAN0.RFSTS4.UINT8[R_IO_LH]) +#define RSCAN0RFSTS4H (RSCAN0.RFSTS4.UINT16[R_IO_H]) +#define RSCAN0RFSTS4HL (RSCAN0.RFSTS4.UINT8[R_IO_HL]) +#define RSCAN0RFSTS4HH (RSCAN0.RFSTS4.UINT8[R_IO_HH]) +#define RSCAN0RFSTS5 (RSCAN0.RFSTS5.UINT32) +#define RSCAN0RFSTS5L (RSCAN0.RFSTS5.UINT16[R_IO_L]) +#define RSCAN0RFSTS5LL (RSCAN0.RFSTS5.UINT8[R_IO_LL]) +#define RSCAN0RFSTS5LH (RSCAN0.RFSTS5.UINT8[R_IO_LH]) +#define RSCAN0RFSTS5H (RSCAN0.RFSTS5.UINT16[R_IO_H]) +#define RSCAN0RFSTS5HL (RSCAN0.RFSTS5.UINT8[R_IO_HL]) +#define RSCAN0RFSTS5HH (RSCAN0.RFSTS5.UINT8[R_IO_HH]) +#define RSCAN0RFSTS6 (RSCAN0.RFSTS6.UINT32) +#define RSCAN0RFSTS6L (RSCAN0.RFSTS6.UINT16[R_IO_L]) +#define RSCAN0RFSTS6LL (RSCAN0.RFSTS6.UINT8[R_IO_LL]) +#define RSCAN0RFSTS6LH (RSCAN0.RFSTS6.UINT8[R_IO_LH]) +#define RSCAN0RFSTS6H (RSCAN0.RFSTS6.UINT16[R_IO_H]) +#define RSCAN0RFSTS6HL (RSCAN0.RFSTS6.UINT8[R_IO_HL]) +#define RSCAN0RFSTS6HH (RSCAN0.RFSTS6.UINT8[R_IO_HH]) +#define RSCAN0RFSTS7 (RSCAN0.RFSTS7.UINT32) +#define RSCAN0RFSTS7L (RSCAN0.RFSTS7.UINT16[R_IO_L]) +#define RSCAN0RFSTS7LL (RSCAN0.RFSTS7.UINT8[R_IO_LL]) +#define RSCAN0RFSTS7LH (RSCAN0.RFSTS7.UINT8[R_IO_LH]) +#define RSCAN0RFSTS7H (RSCAN0.RFSTS7.UINT16[R_IO_H]) +#define RSCAN0RFSTS7HL (RSCAN0.RFSTS7.UINT8[R_IO_HL]) +#define RSCAN0RFSTS7HH (RSCAN0.RFSTS7.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR0 (RSCAN0.RFPCTR0.UINT32) +#define RSCAN0RFPCTR0L (RSCAN0.RFPCTR0.UINT16[R_IO_L]) +#define RSCAN0RFPCTR0LL (RSCAN0.RFPCTR0.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR0LH (RSCAN0.RFPCTR0.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR0H (RSCAN0.RFPCTR0.UINT16[R_IO_H]) +#define RSCAN0RFPCTR0HL (RSCAN0.RFPCTR0.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR0HH (RSCAN0.RFPCTR0.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR1 (RSCAN0.RFPCTR1.UINT32) +#define RSCAN0RFPCTR1L (RSCAN0.RFPCTR1.UINT16[R_IO_L]) +#define RSCAN0RFPCTR1LL (RSCAN0.RFPCTR1.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR1LH (RSCAN0.RFPCTR1.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR1H (RSCAN0.RFPCTR1.UINT16[R_IO_H]) +#define RSCAN0RFPCTR1HL (RSCAN0.RFPCTR1.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR1HH (RSCAN0.RFPCTR1.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR2 (RSCAN0.RFPCTR2.UINT32) +#define RSCAN0RFPCTR2L (RSCAN0.RFPCTR2.UINT16[R_IO_L]) +#define RSCAN0RFPCTR2LL (RSCAN0.RFPCTR2.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR2LH (RSCAN0.RFPCTR2.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR2H (RSCAN0.RFPCTR2.UINT16[R_IO_H]) +#define RSCAN0RFPCTR2HL (RSCAN0.RFPCTR2.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR2HH (RSCAN0.RFPCTR2.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR3 (RSCAN0.RFPCTR3.UINT32) +#define RSCAN0RFPCTR3L (RSCAN0.RFPCTR3.UINT16[R_IO_L]) +#define RSCAN0RFPCTR3LL (RSCAN0.RFPCTR3.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR3LH (RSCAN0.RFPCTR3.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR3H (RSCAN0.RFPCTR3.UINT16[R_IO_H]) +#define RSCAN0RFPCTR3HL (RSCAN0.RFPCTR3.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR3HH (RSCAN0.RFPCTR3.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR4 (RSCAN0.RFPCTR4.UINT32) +#define RSCAN0RFPCTR4L (RSCAN0.RFPCTR4.UINT16[R_IO_L]) +#define RSCAN0RFPCTR4LL (RSCAN0.RFPCTR4.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR4LH (RSCAN0.RFPCTR4.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR4H (RSCAN0.RFPCTR4.UINT16[R_IO_H]) +#define RSCAN0RFPCTR4HL (RSCAN0.RFPCTR4.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR4HH (RSCAN0.RFPCTR4.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR5 (RSCAN0.RFPCTR5.UINT32) +#define RSCAN0RFPCTR5L (RSCAN0.RFPCTR5.UINT16[R_IO_L]) +#define RSCAN0RFPCTR5LL (RSCAN0.RFPCTR5.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR5LH (RSCAN0.RFPCTR5.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR5H (RSCAN0.RFPCTR5.UINT16[R_IO_H]) +#define RSCAN0RFPCTR5HL (RSCAN0.RFPCTR5.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR5HH (RSCAN0.RFPCTR5.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR6 (RSCAN0.RFPCTR6.UINT32) +#define RSCAN0RFPCTR6L (RSCAN0.RFPCTR6.UINT16[R_IO_L]) +#define RSCAN0RFPCTR6LL (RSCAN0.RFPCTR6.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR6LH (RSCAN0.RFPCTR6.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR6H (RSCAN0.RFPCTR6.UINT16[R_IO_H]) +#define RSCAN0RFPCTR6HL (RSCAN0.RFPCTR6.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR6HH (RSCAN0.RFPCTR6.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR7 (RSCAN0.RFPCTR7.UINT32) +#define RSCAN0RFPCTR7L (RSCAN0.RFPCTR7.UINT16[R_IO_L]) +#define RSCAN0RFPCTR7LL (RSCAN0.RFPCTR7.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR7LH (RSCAN0.RFPCTR7.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR7H (RSCAN0.RFPCTR7.UINT16[R_IO_H]) +#define RSCAN0RFPCTR7HL (RSCAN0.RFPCTR7.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR7HH (RSCAN0.RFPCTR7.UINT8[R_IO_HH]) +#define RSCAN0CFCC0 (RSCAN0.CFCC0.UINT32) +#define RSCAN0CFCC0L (RSCAN0.CFCC0.UINT16[R_IO_L]) +#define RSCAN0CFCC0LL (RSCAN0.CFCC0.UINT8[R_IO_LL]) +#define RSCAN0CFCC0LH (RSCAN0.CFCC0.UINT8[R_IO_LH]) +#define RSCAN0CFCC0H (RSCAN0.CFCC0.UINT16[R_IO_H]) +#define RSCAN0CFCC0HL (RSCAN0.CFCC0.UINT8[R_IO_HL]) +#define RSCAN0CFCC0HH (RSCAN0.CFCC0.UINT8[R_IO_HH]) +#define RSCAN0CFCC1 (RSCAN0.CFCC1.UINT32) +#define RSCAN0CFCC1L (RSCAN0.CFCC1.UINT16[R_IO_L]) +#define RSCAN0CFCC1LL (RSCAN0.CFCC1.UINT8[R_IO_LL]) +#define RSCAN0CFCC1LH (RSCAN0.CFCC1.UINT8[R_IO_LH]) +#define RSCAN0CFCC1H (RSCAN0.CFCC1.UINT16[R_IO_H]) +#define RSCAN0CFCC1HL (RSCAN0.CFCC1.UINT8[R_IO_HL]) +#define RSCAN0CFCC1HH (RSCAN0.CFCC1.UINT8[R_IO_HH]) +#define RSCAN0CFCC2 (RSCAN0.CFCC2.UINT32) +#define RSCAN0CFCC2L (RSCAN0.CFCC2.UINT16[R_IO_L]) +#define RSCAN0CFCC2LL (RSCAN0.CFCC2.UINT8[R_IO_LL]) +#define RSCAN0CFCC2LH (RSCAN0.CFCC2.UINT8[R_IO_LH]) +#define RSCAN0CFCC2H (RSCAN0.CFCC2.UINT16[R_IO_H]) +#define RSCAN0CFCC2HL (RSCAN0.CFCC2.UINT8[R_IO_HL]) +#define RSCAN0CFCC2HH (RSCAN0.CFCC2.UINT8[R_IO_HH]) +#define RSCAN0CFCC3 (RSCAN0.CFCC3.UINT32) +#define RSCAN0CFCC3L (RSCAN0.CFCC3.UINT16[R_IO_L]) +#define RSCAN0CFCC3LL (RSCAN0.CFCC3.UINT8[R_IO_LL]) +#define RSCAN0CFCC3LH (RSCAN0.CFCC3.UINT8[R_IO_LH]) +#define RSCAN0CFCC3H (RSCAN0.CFCC3.UINT16[R_IO_H]) +#define RSCAN0CFCC3HL (RSCAN0.CFCC3.UINT8[R_IO_HL]) +#define RSCAN0CFCC3HH (RSCAN0.CFCC3.UINT8[R_IO_HH]) +#define RSCAN0CFCC4 (RSCAN0.CFCC4.UINT32) +#define RSCAN0CFCC4L (RSCAN0.CFCC4.UINT16[R_IO_L]) +#define RSCAN0CFCC4LL (RSCAN0.CFCC4.UINT8[R_IO_LL]) +#define RSCAN0CFCC4LH (RSCAN0.CFCC4.UINT8[R_IO_LH]) +#define RSCAN0CFCC4H (RSCAN0.CFCC4.UINT16[R_IO_H]) +#define RSCAN0CFCC4HL (RSCAN0.CFCC4.UINT8[R_IO_HL]) +#define RSCAN0CFCC4HH (RSCAN0.CFCC4.UINT8[R_IO_HH]) +#define RSCAN0CFCC5 (RSCAN0.CFCC5.UINT32) +#define RSCAN0CFCC5L (RSCAN0.CFCC5.UINT16[R_IO_L]) +#define RSCAN0CFCC5LL (RSCAN0.CFCC5.UINT8[R_IO_LL]) +#define RSCAN0CFCC5LH (RSCAN0.CFCC5.UINT8[R_IO_LH]) +#define RSCAN0CFCC5H (RSCAN0.CFCC5.UINT16[R_IO_H]) +#define RSCAN0CFCC5HL (RSCAN0.CFCC5.UINT8[R_IO_HL]) +#define RSCAN0CFCC5HH (RSCAN0.CFCC5.UINT8[R_IO_HH]) +#define RSCAN0CFCC6 (RSCAN0.CFCC6.UINT32) +#define RSCAN0CFCC6L (RSCAN0.CFCC6.UINT16[R_IO_L]) +#define RSCAN0CFCC6LL (RSCAN0.CFCC6.UINT8[R_IO_LL]) +#define RSCAN0CFCC6LH (RSCAN0.CFCC6.UINT8[R_IO_LH]) +#define RSCAN0CFCC6H (RSCAN0.CFCC6.UINT16[R_IO_H]) +#define RSCAN0CFCC6HL (RSCAN0.CFCC6.UINT8[R_IO_HL]) +#define RSCAN0CFCC6HH (RSCAN0.CFCC6.UINT8[R_IO_HH]) +#define RSCAN0CFCC7 (RSCAN0.CFCC7.UINT32) +#define RSCAN0CFCC7L (RSCAN0.CFCC7.UINT16[R_IO_L]) +#define RSCAN0CFCC7LL (RSCAN0.CFCC7.UINT8[R_IO_LL]) +#define RSCAN0CFCC7LH (RSCAN0.CFCC7.UINT8[R_IO_LH]) +#define RSCAN0CFCC7H (RSCAN0.CFCC7.UINT16[R_IO_H]) +#define RSCAN0CFCC7HL (RSCAN0.CFCC7.UINT8[R_IO_HL]) +#define RSCAN0CFCC7HH (RSCAN0.CFCC7.UINT8[R_IO_HH]) +#define RSCAN0CFCC8 (RSCAN0.CFCC8.UINT32) +#define RSCAN0CFCC8L (RSCAN0.CFCC8.UINT16[R_IO_L]) +#define RSCAN0CFCC8LL (RSCAN0.CFCC8.UINT8[R_IO_LL]) +#define RSCAN0CFCC8LH (RSCAN0.CFCC8.UINT8[R_IO_LH]) +#define RSCAN0CFCC8H (RSCAN0.CFCC8.UINT16[R_IO_H]) +#define RSCAN0CFCC8HL (RSCAN0.CFCC8.UINT8[R_IO_HL]) +#define RSCAN0CFCC8HH (RSCAN0.CFCC8.UINT8[R_IO_HH]) +#define RSCAN0CFCC9 (RSCAN0.CFCC9.UINT32) +#define RSCAN0CFCC9L (RSCAN0.CFCC9.UINT16[R_IO_L]) +#define RSCAN0CFCC9LL (RSCAN0.CFCC9.UINT8[R_IO_LL]) +#define RSCAN0CFCC9LH (RSCAN0.CFCC9.UINT8[R_IO_LH]) +#define RSCAN0CFCC9H (RSCAN0.CFCC9.UINT16[R_IO_H]) +#define RSCAN0CFCC9HL (RSCAN0.CFCC9.UINT8[R_IO_HL]) +#define RSCAN0CFCC9HH (RSCAN0.CFCC9.UINT8[R_IO_HH]) +#define RSCAN0CFCC10 (RSCAN0.CFCC10.UINT32) +#define RSCAN0CFCC10L (RSCAN0.CFCC10.UINT16[R_IO_L]) +#define RSCAN0CFCC10LL (RSCAN0.CFCC10.UINT8[R_IO_LL]) +#define RSCAN0CFCC10LH (RSCAN0.CFCC10.UINT8[R_IO_LH]) +#define RSCAN0CFCC10H (RSCAN0.CFCC10.UINT16[R_IO_H]) +#define RSCAN0CFCC10HL (RSCAN0.CFCC10.UINT8[R_IO_HL]) +#define RSCAN0CFCC10HH (RSCAN0.CFCC10.UINT8[R_IO_HH]) +#define RSCAN0CFCC11 (RSCAN0.CFCC11.UINT32) +#define RSCAN0CFCC11L (RSCAN0.CFCC11.UINT16[R_IO_L]) +#define RSCAN0CFCC11LL (RSCAN0.CFCC11.UINT8[R_IO_LL]) +#define RSCAN0CFCC11LH (RSCAN0.CFCC11.UINT8[R_IO_LH]) +#define RSCAN0CFCC11H (RSCAN0.CFCC11.UINT16[R_IO_H]) +#define RSCAN0CFCC11HL (RSCAN0.CFCC11.UINT8[R_IO_HL]) +#define RSCAN0CFCC11HH (RSCAN0.CFCC11.UINT8[R_IO_HH]) +#define RSCAN0CFCC12 (RSCAN0.CFCC12.UINT32) +#define RSCAN0CFCC12L (RSCAN0.CFCC12.UINT16[R_IO_L]) +#define RSCAN0CFCC12LL (RSCAN0.CFCC12.UINT8[R_IO_LL]) +#define RSCAN0CFCC12LH (RSCAN0.CFCC12.UINT8[R_IO_LH]) +#define RSCAN0CFCC12H (RSCAN0.CFCC12.UINT16[R_IO_H]) +#define RSCAN0CFCC12HL (RSCAN0.CFCC12.UINT8[R_IO_HL]) +#define RSCAN0CFCC12HH (RSCAN0.CFCC12.UINT8[R_IO_HH]) +#define RSCAN0CFCC13 (RSCAN0.CFCC13.UINT32) +#define RSCAN0CFCC13L (RSCAN0.CFCC13.UINT16[R_IO_L]) +#define RSCAN0CFCC13LL (RSCAN0.CFCC13.UINT8[R_IO_LL]) +#define RSCAN0CFCC13LH (RSCAN0.CFCC13.UINT8[R_IO_LH]) +#define RSCAN0CFCC13H (RSCAN0.CFCC13.UINT16[R_IO_H]) +#define RSCAN0CFCC13HL (RSCAN0.CFCC13.UINT8[R_IO_HL]) +#define RSCAN0CFCC13HH (RSCAN0.CFCC13.UINT8[R_IO_HH]) +#define RSCAN0CFCC14 (RSCAN0.CFCC14.UINT32) +#define RSCAN0CFCC14L (RSCAN0.CFCC14.UINT16[R_IO_L]) +#define RSCAN0CFCC14LL (RSCAN0.CFCC14.UINT8[R_IO_LL]) +#define RSCAN0CFCC14LH (RSCAN0.CFCC14.UINT8[R_IO_LH]) +#define RSCAN0CFCC14H (RSCAN0.CFCC14.UINT16[R_IO_H]) +#define RSCAN0CFCC14HL (RSCAN0.CFCC14.UINT8[R_IO_HL]) +#define RSCAN0CFCC14HH (RSCAN0.CFCC14.UINT8[R_IO_HH]) +#define RSCAN0CFSTS0 (RSCAN0.CFSTS0.UINT32) +#define RSCAN0CFSTS0L (RSCAN0.CFSTS0.UINT16[R_IO_L]) +#define RSCAN0CFSTS0LL (RSCAN0.CFSTS0.UINT8[R_IO_LL]) +#define RSCAN0CFSTS0LH (RSCAN0.CFSTS0.UINT8[R_IO_LH]) +#define RSCAN0CFSTS0H (RSCAN0.CFSTS0.UINT16[R_IO_H]) +#define RSCAN0CFSTS0HL (RSCAN0.CFSTS0.UINT8[R_IO_HL]) +#define RSCAN0CFSTS0HH (RSCAN0.CFSTS0.UINT8[R_IO_HH]) +#define RSCAN0CFSTS1 (RSCAN0.CFSTS1.UINT32) +#define RSCAN0CFSTS1L (RSCAN0.CFSTS1.UINT16[R_IO_L]) +#define RSCAN0CFSTS1LL (RSCAN0.CFSTS1.UINT8[R_IO_LL]) +#define RSCAN0CFSTS1LH (RSCAN0.CFSTS1.UINT8[R_IO_LH]) +#define RSCAN0CFSTS1H (RSCAN0.CFSTS1.UINT16[R_IO_H]) +#define RSCAN0CFSTS1HL (RSCAN0.CFSTS1.UINT8[R_IO_HL]) +#define RSCAN0CFSTS1HH (RSCAN0.CFSTS1.UINT8[R_IO_HH]) +#define RSCAN0CFSTS2 (RSCAN0.CFSTS2.UINT32) +#define RSCAN0CFSTS2L (RSCAN0.CFSTS2.UINT16[R_IO_L]) +#define RSCAN0CFSTS2LL (RSCAN0.CFSTS2.UINT8[R_IO_LL]) +#define RSCAN0CFSTS2LH (RSCAN0.CFSTS2.UINT8[R_IO_LH]) +#define RSCAN0CFSTS2H (RSCAN0.CFSTS2.UINT16[R_IO_H]) +#define RSCAN0CFSTS2HL (RSCAN0.CFSTS2.UINT8[R_IO_HL]) +#define RSCAN0CFSTS2HH (RSCAN0.CFSTS2.UINT8[R_IO_HH]) +#define RSCAN0CFSTS3 (RSCAN0.CFSTS3.UINT32) +#define RSCAN0CFSTS3L (RSCAN0.CFSTS3.UINT16[R_IO_L]) +#define RSCAN0CFSTS3LL (RSCAN0.CFSTS3.UINT8[R_IO_LL]) +#define RSCAN0CFSTS3LH (RSCAN0.CFSTS3.UINT8[R_IO_LH]) +#define RSCAN0CFSTS3H (RSCAN0.CFSTS3.UINT16[R_IO_H]) +#define RSCAN0CFSTS3HL (RSCAN0.CFSTS3.UINT8[R_IO_HL]) +#define RSCAN0CFSTS3HH (RSCAN0.CFSTS3.UINT8[R_IO_HH]) +#define RSCAN0CFSTS4 (RSCAN0.CFSTS4.UINT32) +#define RSCAN0CFSTS4L (RSCAN0.CFSTS4.UINT16[R_IO_L]) +#define RSCAN0CFSTS4LL (RSCAN0.CFSTS4.UINT8[R_IO_LL]) +#define RSCAN0CFSTS4LH (RSCAN0.CFSTS4.UINT8[R_IO_LH]) +#define RSCAN0CFSTS4H (RSCAN0.CFSTS4.UINT16[R_IO_H]) +#define RSCAN0CFSTS4HL (RSCAN0.CFSTS4.UINT8[R_IO_HL]) +#define RSCAN0CFSTS4HH (RSCAN0.CFSTS4.UINT8[R_IO_HH]) +#define RSCAN0CFSTS5 (RSCAN0.CFSTS5.UINT32) +#define RSCAN0CFSTS5L (RSCAN0.CFSTS5.UINT16[R_IO_L]) +#define RSCAN0CFSTS5LL (RSCAN0.CFSTS5.UINT8[R_IO_LL]) +#define RSCAN0CFSTS5LH (RSCAN0.CFSTS5.UINT8[R_IO_LH]) +#define RSCAN0CFSTS5H (RSCAN0.CFSTS5.UINT16[R_IO_H]) +#define RSCAN0CFSTS5HL (RSCAN0.CFSTS5.UINT8[R_IO_HL]) +#define RSCAN0CFSTS5HH (RSCAN0.CFSTS5.UINT8[R_IO_HH]) +#define RSCAN0CFSTS6 (RSCAN0.CFSTS6.UINT32) +#define RSCAN0CFSTS6L (RSCAN0.CFSTS6.UINT16[R_IO_L]) +#define RSCAN0CFSTS6LL (RSCAN0.CFSTS6.UINT8[R_IO_LL]) +#define RSCAN0CFSTS6LH (RSCAN0.CFSTS6.UINT8[R_IO_LH]) +#define RSCAN0CFSTS6H (RSCAN0.CFSTS6.UINT16[R_IO_H]) +#define RSCAN0CFSTS6HL (RSCAN0.CFSTS6.UINT8[R_IO_HL]) +#define RSCAN0CFSTS6HH (RSCAN0.CFSTS6.UINT8[R_IO_HH]) +#define RSCAN0CFSTS7 (RSCAN0.CFSTS7.UINT32) +#define RSCAN0CFSTS7L (RSCAN0.CFSTS7.UINT16[R_IO_L]) +#define RSCAN0CFSTS7LL (RSCAN0.CFSTS7.UINT8[R_IO_LL]) +#define RSCAN0CFSTS7LH (RSCAN0.CFSTS7.UINT8[R_IO_LH]) +#define RSCAN0CFSTS7H (RSCAN0.CFSTS7.UINT16[R_IO_H]) +#define RSCAN0CFSTS7HL (RSCAN0.CFSTS7.UINT8[R_IO_HL]) +#define RSCAN0CFSTS7HH (RSCAN0.CFSTS7.UINT8[R_IO_HH]) +#define RSCAN0CFSTS8 (RSCAN0.CFSTS8.UINT32) +#define RSCAN0CFSTS8L (RSCAN0.CFSTS8.UINT16[R_IO_L]) +#define RSCAN0CFSTS8LL (RSCAN0.CFSTS8.UINT8[R_IO_LL]) +#define RSCAN0CFSTS8LH (RSCAN0.CFSTS8.UINT8[R_IO_LH]) +#define RSCAN0CFSTS8H (RSCAN0.CFSTS8.UINT16[R_IO_H]) +#define RSCAN0CFSTS8HL (RSCAN0.CFSTS8.UINT8[R_IO_HL]) +#define RSCAN0CFSTS8HH (RSCAN0.CFSTS8.UINT8[R_IO_HH]) +#define RSCAN0CFSTS9 (RSCAN0.CFSTS9.UINT32) +#define RSCAN0CFSTS9L (RSCAN0.CFSTS9.UINT16[R_IO_L]) +#define RSCAN0CFSTS9LL (RSCAN0.CFSTS9.UINT8[R_IO_LL]) +#define RSCAN0CFSTS9LH (RSCAN0.CFSTS9.UINT8[R_IO_LH]) +#define RSCAN0CFSTS9H (RSCAN0.CFSTS9.UINT16[R_IO_H]) +#define RSCAN0CFSTS9HL (RSCAN0.CFSTS9.UINT8[R_IO_HL]) +#define RSCAN0CFSTS9HH (RSCAN0.CFSTS9.UINT8[R_IO_HH]) +#define RSCAN0CFSTS10 (RSCAN0.CFSTS10.UINT32) +#define RSCAN0CFSTS10L (RSCAN0.CFSTS10.UINT16[R_IO_L]) +#define RSCAN0CFSTS10LL (RSCAN0.CFSTS10.UINT8[R_IO_LL]) +#define RSCAN0CFSTS10LH (RSCAN0.CFSTS10.UINT8[R_IO_LH]) +#define RSCAN0CFSTS10H (RSCAN0.CFSTS10.UINT16[R_IO_H]) +#define RSCAN0CFSTS10HL (RSCAN0.CFSTS10.UINT8[R_IO_HL]) +#define RSCAN0CFSTS10HH (RSCAN0.CFSTS10.UINT8[R_IO_HH]) +#define RSCAN0CFSTS11 (RSCAN0.CFSTS11.UINT32) +#define RSCAN0CFSTS11L (RSCAN0.CFSTS11.UINT16[R_IO_L]) +#define RSCAN0CFSTS11LL (RSCAN0.CFSTS11.UINT8[R_IO_LL]) +#define RSCAN0CFSTS11LH (RSCAN0.CFSTS11.UINT8[R_IO_LH]) +#define RSCAN0CFSTS11H (RSCAN0.CFSTS11.UINT16[R_IO_H]) +#define RSCAN0CFSTS11HL (RSCAN0.CFSTS11.UINT8[R_IO_HL]) +#define RSCAN0CFSTS11HH (RSCAN0.CFSTS11.UINT8[R_IO_HH]) +#define RSCAN0CFSTS12 (RSCAN0.CFSTS12.UINT32) +#define RSCAN0CFSTS12L (RSCAN0.CFSTS12.UINT16[R_IO_L]) +#define RSCAN0CFSTS12LL (RSCAN0.CFSTS12.UINT8[R_IO_LL]) +#define RSCAN0CFSTS12LH (RSCAN0.CFSTS12.UINT8[R_IO_LH]) +#define RSCAN0CFSTS12H (RSCAN0.CFSTS12.UINT16[R_IO_H]) +#define RSCAN0CFSTS12HL (RSCAN0.CFSTS12.UINT8[R_IO_HL]) +#define RSCAN0CFSTS12HH (RSCAN0.CFSTS12.UINT8[R_IO_HH]) +#define RSCAN0CFSTS13 (RSCAN0.CFSTS13.UINT32) +#define RSCAN0CFSTS13L (RSCAN0.CFSTS13.UINT16[R_IO_L]) +#define RSCAN0CFSTS13LL (RSCAN0.CFSTS13.UINT8[R_IO_LL]) +#define RSCAN0CFSTS13LH (RSCAN0.CFSTS13.UINT8[R_IO_LH]) +#define RSCAN0CFSTS13H (RSCAN0.CFSTS13.UINT16[R_IO_H]) +#define RSCAN0CFSTS13HL (RSCAN0.CFSTS13.UINT8[R_IO_HL]) +#define RSCAN0CFSTS13HH (RSCAN0.CFSTS13.UINT8[R_IO_HH]) +#define RSCAN0CFSTS14 (RSCAN0.CFSTS14.UINT32) +#define RSCAN0CFSTS14L (RSCAN0.CFSTS14.UINT16[R_IO_L]) +#define RSCAN0CFSTS14LL (RSCAN0.CFSTS14.UINT8[R_IO_LL]) +#define RSCAN0CFSTS14LH (RSCAN0.CFSTS14.UINT8[R_IO_LH]) +#define RSCAN0CFSTS14H (RSCAN0.CFSTS14.UINT16[R_IO_H]) +#define RSCAN0CFSTS14HL (RSCAN0.CFSTS14.UINT8[R_IO_HL]) +#define RSCAN0CFSTS14HH (RSCAN0.CFSTS14.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR0 (RSCAN0.CFPCTR0.UINT32) +#define RSCAN0CFPCTR0L (RSCAN0.CFPCTR0.UINT16[R_IO_L]) +#define RSCAN0CFPCTR0LL (RSCAN0.CFPCTR0.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR0LH (RSCAN0.CFPCTR0.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR0H (RSCAN0.CFPCTR0.UINT16[R_IO_H]) +#define RSCAN0CFPCTR0HL (RSCAN0.CFPCTR0.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR0HH (RSCAN0.CFPCTR0.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR1 (RSCAN0.CFPCTR1.UINT32) +#define RSCAN0CFPCTR1L (RSCAN0.CFPCTR1.UINT16[R_IO_L]) +#define RSCAN0CFPCTR1LL (RSCAN0.CFPCTR1.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR1LH (RSCAN0.CFPCTR1.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR1H (RSCAN0.CFPCTR1.UINT16[R_IO_H]) +#define RSCAN0CFPCTR1HL (RSCAN0.CFPCTR1.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR1HH (RSCAN0.CFPCTR1.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR2 (RSCAN0.CFPCTR2.UINT32) +#define RSCAN0CFPCTR2L (RSCAN0.CFPCTR2.UINT16[R_IO_L]) +#define RSCAN0CFPCTR2LL (RSCAN0.CFPCTR2.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR2LH (RSCAN0.CFPCTR2.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR2H (RSCAN0.CFPCTR2.UINT16[R_IO_H]) +#define RSCAN0CFPCTR2HL (RSCAN0.CFPCTR2.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR2HH (RSCAN0.CFPCTR2.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR3 (RSCAN0.CFPCTR3.UINT32) +#define RSCAN0CFPCTR3L (RSCAN0.CFPCTR3.UINT16[R_IO_L]) +#define RSCAN0CFPCTR3LL (RSCAN0.CFPCTR3.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR3LH (RSCAN0.CFPCTR3.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR3H (RSCAN0.CFPCTR3.UINT16[R_IO_H]) +#define RSCAN0CFPCTR3HL (RSCAN0.CFPCTR3.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR3HH (RSCAN0.CFPCTR3.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR4 (RSCAN0.CFPCTR4.UINT32) +#define RSCAN0CFPCTR4L (RSCAN0.CFPCTR4.UINT16[R_IO_L]) +#define RSCAN0CFPCTR4LL (RSCAN0.CFPCTR4.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR4LH (RSCAN0.CFPCTR4.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR4H (RSCAN0.CFPCTR4.UINT16[R_IO_H]) +#define RSCAN0CFPCTR4HL (RSCAN0.CFPCTR4.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR4HH (RSCAN0.CFPCTR4.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR5 (RSCAN0.CFPCTR5.UINT32) +#define RSCAN0CFPCTR5L (RSCAN0.CFPCTR5.UINT16[R_IO_L]) +#define RSCAN0CFPCTR5LL (RSCAN0.CFPCTR5.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR5LH (RSCAN0.CFPCTR5.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR5H (RSCAN0.CFPCTR5.UINT16[R_IO_H]) +#define RSCAN0CFPCTR5HL (RSCAN0.CFPCTR5.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR5HH (RSCAN0.CFPCTR5.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR6 (RSCAN0.CFPCTR6.UINT32) +#define RSCAN0CFPCTR6L (RSCAN0.CFPCTR6.UINT16[R_IO_L]) +#define RSCAN0CFPCTR6LL (RSCAN0.CFPCTR6.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR6LH (RSCAN0.CFPCTR6.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR6H (RSCAN0.CFPCTR6.UINT16[R_IO_H]) +#define RSCAN0CFPCTR6HL (RSCAN0.CFPCTR6.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR6HH (RSCAN0.CFPCTR6.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR7 (RSCAN0.CFPCTR7.UINT32) +#define RSCAN0CFPCTR7L (RSCAN0.CFPCTR7.UINT16[R_IO_L]) +#define RSCAN0CFPCTR7LL (RSCAN0.CFPCTR7.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR7LH (RSCAN0.CFPCTR7.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR7H (RSCAN0.CFPCTR7.UINT16[R_IO_H]) +#define RSCAN0CFPCTR7HL (RSCAN0.CFPCTR7.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR7HH (RSCAN0.CFPCTR7.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR8 (RSCAN0.CFPCTR8.UINT32) +#define RSCAN0CFPCTR8L (RSCAN0.CFPCTR8.UINT16[R_IO_L]) +#define RSCAN0CFPCTR8LL (RSCAN0.CFPCTR8.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR8LH (RSCAN0.CFPCTR8.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR8H (RSCAN0.CFPCTR8.UINT16[R_IO_H]) +#define RSCAN0CFPCTR8HL (RSCAN0.CFPCTR8.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR8HH (RSCAN0.CFPCTR8.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR9 (RSCAN0.CFPCTR9.UINT32) +#define RSCAN0CFPCTR9L (RSCAN0.CFPCTR9.UINT16[R_IO_L]) +#define RSCAN0CFPCTR9LL (RSCAN0.CFPCTR9.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR9LH (RSCAN0.CFPCTR9.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR9H (RSCAN0.CFPCTR9.UINT16[R_IO_H]) +#define RSCAN0CFPCTR9HL (RSCAN0.CFPCTR9.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR9HH (RSCAN0.CFPCTR9.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR10 (RSCAN0.CFPCTR10.UINT32) +#define RSCAN0CFPCTR10L (RSCAN0.CFPCTR10.UINT16[R_IO_L]) +#define RSCAN0CFPCTR10LL (RSCAN0.CFPCTR10.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR10LH (RSCAN0.CFPCTR10.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR10H (RSCAN0.CFPCTR10.UINT16[R_IO_H]) +#define RSCAN0CFPCTR10HL (RSCAN0.CFPCTR10.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR10HH (RSCAN0.CFPCTR10.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR11 (RSCAN0.CFPCTR11.UINT32) +#define RSCAN0CFPCTR11L (RSCAN0.CFPCTR11.UINT16[R_IO_L]) +#define RSCAN0CFPCTR11LL (RSCAN0.CFPCTR11.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR11LH (RSCAN0.CFPCTR11.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR11H (RSCAN0.CFPCTR11.UINT16[R_IO_H]) +#define RSCAN0CFPCTR11HL (RSCAN0.CFPCTR11.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR11HH (RSCAN0.CFPCTR11.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR12 (RSCAN0.CFPCTR12.UINT32) +#define RSCAN0CFPCTR12L (RSCAN0.CFPCTR12.UINT16[R_IO_L]) +#define RSCAN0CFPCTR12LL (RSCAN0.CFPCTR12.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR12LH (RSCAN0.CFPCTR12.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR12H (RSCAN0.CFPCTR12.UINT16[R_IO_H]) +#define RSCAN0CFPCTR12HL (RSCAN0.CFPCTR12.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR12HH (RSCAN0.CFPCTR12.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR13 (RSCAN0.CFPCTR13.UINT32) +#define RSCAN0CFPCTR13L (RSCAN0.CFPCTR13.UINT16[R_IO_L]) +#define RSCAN0CFPCTR13LL (RSCAN0.CFPCTR13.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR13LH (RSCAN0.CFPCTR13.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR13H (RSCAN0.CFPCTR13.UINT16[R_IO_H]) +#define RSCAN0CFPCTR13HL (RSCAN0.CFPCTR13.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR13HH (RSCAN0.CFPCTR13.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR14 (RSCAN0.CFPCTR14.UINT32) +#define RSCAN0CFPCTR14L (RSCAN0.CFPCTR14.UINT16[R_IO_L]) +#define RSCAN0CFPCTR14LL (RSCAN0.CFPCTR14.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR14LH (RSCAN0.CFPCTR14.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR14H (RSCAN0.CFPCTR14.UINT16[R_IO_H]) +#define RSCAN0CFPCTR14HL (RSCAN0.CFPCTR14.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR14HH (RSCAN0.CFPCTR14.UINT8[R_IO_HH]) +#define RSCAN0FESTS (RSCAN0.FESTS.UINT32) +#define RSCAN0FESTSL (RSCAN0.FESTS.UINT16[R_IO_L]) +#define RSCAN0FESTSLL (RSCAN0.FESTS.UINT8[R_IO_LL]) +#define RSCAN0FESTSLH (RSCAN0.FESTS.UINT8[R_IO_LH]) +#define RSCAN0FESTSH (RSCAN0.FESTS.UINT16[R_IO_H]) +#define RSCAN0FESTSHL (RSCAN0.FESTS.UINT8[R_IO_HL]) +#define RSCAN0FESTSHH (RSCAN0.FESTS.UINT8[R_IO_HH]) +#define RSCAN0FFSTS (RSCAN0.FFSTS.UINT32) +#define RSCAN0FFSTSL (RSCAN0.FFSTS.UINT16[R_IO_L]) +#define RSCAN0FFSTSLL (RSCAN0.FFSTS.UINT8[R_IO_LL]) +#define RSCAN0FFSTSLH (RSCAN0.FFSTS.UINT8[R_IO_LH]) +#define RSCAN0FFSTSH (RSCAN0.FFSTS.UINT16[R_IO_H]) +#define RSCAN0FFSTSHL (RSCAN0.FFSTS.UINT8[R_IO_HL]) +#define RSCAN0FFSTSHH (RSCAN0.FFSTS.UINT8[R_IO_HH]) +#define RSCAN0FMSTS (RSCAN0.FMSTS.UINT32) +#define RSCAN0FMSTSL (RSCAN0.FMSTS.UINT16[R_IO_L]) +#define RSCAN0FMSTSLL (RSCAN0.FMSTS.UINT8[R_IO_LL]) +#define RSCAN0FMSTSLH (RSCAN0.FMSTS.UINT8[R_IO_LH]) +#define RSCAN0FMSTSH (RSCAN0.FMSTS.UINT16[R_IO_H]) +#define RSCAN0FMSTSHL (RSCAN0.FMSTS.UINT8[R_IO_HL]) +#define RSCAN0FMSTSHH (RSCAN0.FMSTS.UINT8[R_IO_HH]) +#define RSCAN0RFISTS (RSCAN0.RFISTS.UINT32) +#define RSCAN0RFISTSL (RSCAN0.RFISTS.UINT16[R_IO_L]) +#define RSCAN0RFISTSLL (RSCAN0.RFISTS.UINT8[R_IO_LL]) +#define RSCAN0RFISTSLH (RSCAN0.RFISTS.UINT8[R_IO_LH]) +#define RSCAN0RFISTSH (RSCAN0.RFISTS.UINT16[R_IO_H]) +#define RSCAN0RFISTSHL (RSCAN0.RFISTS.UINT8[R_IO_HL]) +#define RSCAN0RFISTSHH (RSCAN0.RFISTS.UINT8[R_IO_HH]) +#define RSCAN0CFRISTS (RSCAN0.CFRISTS.UINT32) +#define RSCAN0CFRISTSL (RSCAN0.CFRISTS.UINT16[R_IO_L]) +#define RSCAN0CFRISTSLL (RSCAN0.CFRISTS.UINT8[R_IO_LL]) +#define RSCAN0CFRISTSLH (RSCAN0.CFRISTS.UINT8[R_IO_LH]) +#define RSCAN0CFRISTSH (RSCAN0.CFRISTS.UINT16[R_IO_H]) +#define RSCAN0CFRISTSHL (RSCAN0.CFRISTS.UINT8[R_IO_HL]) +#define RSCAN0CFRISTSHH (RSCAN0.CFRISTS.UINT8[R_IO_HH]) +#define RSCAN0CFTISTS (RSCAN0.CFTISTS.UINT32) +#define RSCAN0CFTISTSL (RSCAN0.CFTISTS.UINT16[R_IO_L]) +#define RSCAN0CFTISTSLL (RSCAN0.CFTISTS.UINT8[R_IO_LL]) +#define RSCAN0CFTISTSLH (RSCAN0.CFTISTS.UINT8[R_IO_LH]) +#define RSCAN0CFTISTSH (RSCAN0.CFTISTS.UINT16[R_IO_H]) +#define RSCAN0CFTISTSHL (RSCAN0.CFTISTS.UINT8[R_IO_HL]) +#define RSCAN0CFTISTSHH (RSCAN0.CFTISTS.UINT8[R_IO_HH]) +#define RSCAN0TMC0 (RSCAN0.TMC0) +#define RSCAN0TMC1 (RSCAN0.TMC1) +#define RSCAN0TMC2 (RSCAN0.TMC2) +#define RSCAN0TMC3 (RSCAN0.TMC3) +#define RSCAN0TMC4 (RSCAN0.TMC4) +#define RSCAN0TMC5 (RSCAN0.TMC5) +#define RSCAN0TMC6 (RSCAN0.TMC6) +#define RSCAN0TMC7 (RSCAN0.TMC7) +#define RSCAN0TMC8 (RSCAN0.TMC8) +#define RSCAN0TMC9 (RSCAN0.TMC9) +#define RSCAN0TMC10 (RSCAN0.TMC10) +#define RSCAN0TMC11 (RSCAN0.TMC11) +#define RSCAN0TMC12 (RSCAN0.TMC12) +#define RSCAN0TMC13 (RSCAN0.TMC13) +#define RSCAN0TMC14 (RSCAN0.TMC14) +#define RSCAN0TMC15 (RSCAN0.TMC15) +#define RSCAN0TMC16 (RSCAN0.TMC16) +#define RSCAN0TMC17 (RSCAN0.TMC17) +#define RSCAN0TMC18 (RSCAN0.TMC18) +#define RSCAN0TMC19 (RSCAN0.TMC19) +#define RSCAN0TMC20 (RSCAN0.TMC20) +#define RSCAN0TMC21 (RSCAN0.TMC21) +#define RSCAN0TMC22 (RSCAN0.TMC22) +#define RSCAN0TMC23 (RSCAN0.TMC23) +#define RSCAN0TMC24 (RSCAN0.TMC24) +#define RSCAN0TMC25 (RSCAN0.TMC25) +#define RSCAN0TMC26 (RSCAN0.TMC26) +#define RSCAN0TMC27 (RSCAN0.TMC27) +#define RSCAN0TMC28 (RSCAN0.TMC28) +#define RSCAN0TMC29 (RSCAN0.TMC29) +#define RSCAN0TMC30 (RSCAN0.TMC30) +#define RSCAN0TMC31 (RSCAN0.TMC31) +#define RSCAN0TMC32 (RSCAN0.TMC32) +#define RSCAN0TMC33 (RSCAN0.TMC33) +#define RSCAN0TMC34 (RSCAN0.TMC34) +#define RSCAN0TMC35 (RSCAN0.TMC35) +#define RSCAN0TMC36 (RSCAN0.TMC36) +#define RSCAN0TMC37 (RSCAN0.TMC37) +#define RSCAN0TMC38 (RSCAN0.TMC38) +#define RSCAN0TMC39 (RSCAN0.TMC39) +#define RSCAN0TMC40 (RSCAN0.TMC40) +#define RSCAN0TMC41 (RSCAN0.TMC41) +#define RSCAN0TMC42 (RSCAN0.TMC42) +#define RSCAN0TMC43 (RSCAN0.TMC43) +#define RSCAN0TMC44 (RSCAN0.TMC44) +#define RSCAN0TMC45 (RSCAN0.TMC45) +#define RSCAN0TMC46 (RSCAN0.TMC46) +#define RSCAN0TMC47 (RSCAN0.TMC47) +#define RSCAN0TMC48 (RSCAN0.TMC48) +#define RSCAN0TMC49 (RSCAN0.TMC49) +#define RSCAN0TMC50 (RSCAN0.TMC50) +#define RSCAN0TMC51 (RSCAN0.TMC51) +#define RSCAN0TMC52 (RSCAN0.TMC52) +#define RSCAN0TMC53 (RSCAN0.TMC53) +#define RSCAN0TMC54 (RSCAN0.TMC54) +#define RSCAN0TMC55 (RSCAN0.TMC55) +#define RSCAN0TMC56 (RSCAN0.TMC56) +#define RSCAN0TMC57 (RSCAN0.TMC57) +#define RSCAN0TMC58 (RSCAN0.TMC58) +#define RSCAN0TMC59 (RSCAN0.TMC59) +#define RSCAN0TMC60 (RSCAN0.TMC60) +#define RSCAN0TMC61 (RSCAN0.TMC61) +#define RSCAN0TMC62 (RSCAN0.TMC62) +#define RSCAN0TMC63 (RSCAN0.TMC63) +#define RSCAN0TMC64 (RSCAN0.TMC64) +#define RSCAN0TMC65 (RSCAN0.TMC65) +#define RSCAN0TMC66 (RSCAN0.TMC66) +#define RSCAN0TMC67 (RSCAN0.TMC67) +#define RSCAN0TMC68 (RSCAN0.TMC68) +#define RSCAN0TMC69 (RSCAN0.TMC69) +#define RSCAN0TMC70 (RSCAN0.TMC70) +#define RSCAN0TMC71 (RSCAN0.TMC71) +#define RSCAN0TMC72 (RSCAN0.TMC72) +#define RSCAN0TMC73 (RSCAN0.TMC73) +#define RSCAN0TMC74 (RSCAN0.TMC74) +#define RSCAN0TMC75 (RSCAN0.TMC75) +#define RSCAN0TMC76 (RSCAN0.TMC76) +#define RSCAN0TMC77 (RSCAN0.TMC77) +#define RSCAN0TMC78 (RSCAN0.TMC78) +#define RSCAN0TMC79 (RSCAN0.TMC79) +#define RSCAN0TMSTS0 (RSCAN0.TMSTS0) +#define RSCAN0TMSTS1 (RSCAN0.TMSTS1) +#define RSCAN0TMSTS2 (RSCAN0.TMSTS2) +#define RSCAN0TMSTS3 (RSCAN0.TMSTS3) +#define RSCAN0TMSTS4 (RSCAN0.TMSTS4) +#define RSCAN0TMSTS5 (RSCAN0.TMSTS5) +#define RSCAN0TMSTS6 (RSCAN0.TMSTS6) +#define RSCAN0TMSTS7 (RSCAN0.TMSTS7) +#define RSCAN0TMSTS8 (RSCAN0.TMSTS8) +#define RSCAN0TMSTS9 (RSCAN0.TMSTS9) +#define RSCAN0TMSTS10 (RSCAN0.TMSTS10) +#define RSCAN0TMSTS11 (RSCAN0.TMSTS11) +#define RSCAN0TMSTS12 (RSCAN0.TMSTS12) +#define RSCAN0TMSTS13 (RSCAN0.TMSTS13) +#define RSCAN0TMSTS14 (RSCAN0.TMSTS14) +#define RSCAN0TMSTS15 (RSCAN0.TMSTS15) +#define RSCAN0TMSTS16 (RSCAN0.TMSTS16) +#define RSCAN0TMSTS17 (RSCAN0.TMSTS17) +#define RSCAN0TMSTS18 (RSCAN0.TMSTS18) +#define RSCAN0TMSTS19 (RSCAN0.TMSTS19) +#define RSCAN0TMSTS20 (RSCAN0.TMSTS20) +#define RSCAN0TMSTS21 (RSCAN0.TMSTS21) +#define RSCAN0TMSTS22 (RSCAN0.TMSTS22) +#define RSCAN0TMSTS23 (RSCAN0.TMSTS23) +#define RSCAN0TMSTS24 (RSCAN0.TMSTS24) +#define RSCAN0TMSTS25 (RSCAN0.TMSTS25) +#define RSCAN0TMSTS26 (RSCAN0.TMSTS26) +#define RSCAN0TMSTS27 (RSCAN0.TMSTS27) +#define RSCAN0TMSTS28 (RSCAN0.TMSTS28) +#define RSCAN0TMSTS29 (RSCAN0.TMSTS29) +#define RSCAN0TMSTS30 (RSCAN0.TMSTS30) +#define RSCAN0TMSTS31 (RSCAN0.TMSTS31) +#define RSCAN0TMSTS32 (RSCAN0.TMSTS32) +#define RSCAN0TMSTS33 (RSCAN0.TMSTS33) +#define RSCAN0TMSTS34 (RSCAN0.TMSTS34) +#define RSCAN0TMSTS35 (RSCAN0.TMSTS35) +#define RSCAN0TMSTS36 (RSCAN0.TMSTS36) +#define RSCAN0TMSTS37 (RSCAN0.TMSTS37) +#define RSCAN0TMSTS38 (RSCAN0.TMSTS38) +#define RSCAN0TMSTS39 (RSCAN0.TMSTS39) +#define RSCAN0TMSTS40 (RSCAN0.TMSTS40) +#define RSCAN0TMSTS41 (RSCAN0.TMSTS41) +#define RSCAN0TMSTS42 (RSCAN0.TMSTS42) +#define RSCAN0TMSTS43 (RSCAN0.TMSTS43) +#define RSCAN0TMSTS44 (RSCAN0.TMSTS44) +#define RSCAN0TMSTS45 (RSCAN0.TMSTS45) +#define RSCAN0TMSTS46 (RSCAN0.TMSTS46) +#define RSCAN0TMSTS47 (RSCAN0.TMSTS47) +#define RSCAN0TMSTS48 (RSCAN0.TMSTS48) +#define RSCAN0TMSTS49 (RSCAN0.TMSTS49) +#define RSCAN0TMSTS50 (RSCAN0.TMSTS50) +#define RSCAN0TMSTS51 (RSCAN0.TMSTS51) +#define RSCAN0TMSTS52 (RSCAN0.TMSTS52) +#define RSCAN0TMSTS53 (RSCAN0.TMSTS53) +#define RSCAN0TMSTS54 (RSCAN0.TMSTS54) +#define RSCAN0TMSTS55 (RSCAN0.TMSTS55) +#define RSCAN0TMSTS56 (RSCAN0.TMSTS56) +#define RSCAN0TMSTS57 (RSCAN0.TMSTS57) +#define RSCAN0TMSTS58 (RSCAN0.TMSTS58) +#define RSCAN0TMSTS59 (RSCAN0.TMSTS59) +#define RSCAN0TMSTS60 (RSCAN0.TMSTS60) +#define RSCAN0TMSTS61 (RSCAN0.TMSTS61) +#define RSCAN0TMSTS62 (RSCAN0.TMSTS62) +#define RSCAN0TMSTS63 (RSCAN0.TMSTS63) +#define RSCAN0TMSTS64 (RSCAN0.TMSTS64) +#define RSCAN0TMSTS65 (RSCAN0.TMSTS65) +#define RSCAN0TMSTS66 (RSCAN0.TMSTS66) +#define RSCAN0TMSTS67 (RSCAN0.TMSTS67) +#define RSCAN0TMSTS68 (RSCAN0.TMSTS68) +#define RSCAN0TMSTS69 (RSCAN0.TMSTS69) +#define RSCAN0TMSTS70 (RSCAN0.TMSTS70) +#define RSCAN0TMSTS71 (RSCAN0.TMSTS71) +#define RSCAN0TMSTS72 (RSCAN0.TMSTS72) +#define RSCAN0TMSTS73 (RSCAN0.TMSTS73) +#define RSCAN0TMSTS74 (RSCAN0.TMSTS74) +#define RSCAN0TMSTS75 (RSCAN0.TMSTS75) +#define RSCAN0TMSTS76 (RSCAN0.TMSTS76) +#define RSCAN0TMSTS77 (RSCAN0.TMSTS77) +#define RSCAN0TMSTS78 (RSCAN0.TMSTS78) +#define RSCAN0TMSTS79 (RSCAN0.TMSTS79) +#define RSCAN0TMTRSTS0 (RSCAN0.TMTRSTS0.UINT32) +#define RSCAN0TMTRSTS0L (RSCAN0.TMTRSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTRSTS0LL (RSCAN0.TMTRSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTRSTS0LH (RSCAN0.TMTRSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTRSTS0H (RSCAN0.TMTRSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTRSTS0HL (RSCAN0.TMTRSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTRSTS0HH (RSCAN0.TMTRSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTRSTS1 (RSCAN0.TMTRSTS1.UINT32) +#define RSCAN0TMTRSTS1L (RSCAN0.TMTRSTS1.UINT16[R_IO_L]) +#define RSCAN0TMTRSTS1LL (RSCAN0.TMTRSTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTRSTS1LH (RSCAN0.TMTRSTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTRSTS1H (RSCAN0.TMTRSTS1.UINT16[R_IO_H]) +#define RSCAN0TMTRSTS1HL (RSCAN0.TMTRSTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTRSTS1HH (RSCAN0.TMTRSTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTRSTS2 (RSCAN0.TMTRSTS2.UINT32) +#define RSCAN0TMTRSTS2L (RSCAN0.TMTRSTS2.UINT16[R_IO_L]) +#define RSCAN0TMTRSTS2LL (RSCAN0.TMTRSTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTRSTS2LH (RSCAN0.TMTRSTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTRSTS2H (RSCAN0.TMTRSTS2.UINT16[R_IO_H]) +#define RSCAN0TMTRSTS2HL (RSCAN0.TMTRSTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTRSTS2HH (RSCAN0.TMTRSTS2.UINT8[R_IO_HH]) +#define RSCAN0TMTARSTS0 (RSCAN0.TMTARSTS0.UINT32) +#define RSCAN0TMTARSTS0L (RSCAN0.TMTARSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTARSTS0LL (RSCAN0.TMTARSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTARSTS0LH (RSCAN0.TMTARSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTARSTS0H (RSCAN0.TMTARSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTARSTS0HL (RSCAN0.TMTARSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTARSTS0HH (RSCAN0.TMTARSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTARSTS1 (RSCAN0.TMTARSTS1.UINT32) +#define RSCAN0TMTARSTS1L (RSCAN0.TMTARSTS1.UINT16[R_IO_L]) +#define RSCAN0TMTARSTS1LL (RSCAN0.TMTARSTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTARSTS1LH (RSCAN0.TMTARSTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTARSTS1H (RSCAN0.TMTARSTS1.UINT16[R_IO_H]) +#define RSCAN0TMTARSTS1HL (RSCAN0.TMTARSTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTARSTS1HH (RSCAN0.TMTARSTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTARSTS2 (RSCAN0.TMTARSTS2.UINT32) +#define RSCAN0TMTARSTS2L (RSCAN0.TMTARSTS2.UINT16[R_IO_L]) +#define RSCAN0TMTARSTS2LL (RSCAN0.TMTARSTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTARSTS2LH (RSCAN0.TMTARSTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTARSTS2H (RSCAN0.TMTARSTS2.UINT16[R_IO_H]) +#define RSCAN0TMTARSTS2HL (RSCAN0.TMTARSTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTARSTS2HH (RSCAN0.TMTARSTS2.UINT8[R_IO_HH]) +#define RSCAN0TMTCSTS0 (RSCAN0.TMTCSTS0.UINT32) +#define RSCAN0TMTCSTS0L (RSCAN0.TMTCSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTCSTS0LL (RSCAN0.TMTCSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTCSTS0LH (RSCAN0.TMTCSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTCSTS0H (RSCAN0.TMTCSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTCSTS0HL (RSCAN0.TMTCSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTCSTS0HH (RSCAN0.TMTCSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTCSTS1 (RSCAN0.TMTCSTS1.UINT32) +#define RSCAN0TMTCSTS1L (RSCAN0.TMTCSTS1.UINT16[R_IO_L]) +#define RSCAN0TMTCSTS1LL (RSCAN0.TMTCSTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTCSTS1LH (RSCAN0.TMTCSTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTCSTS1H (RSCAN0.TMTCSTS1.UINT16[R_IO_H]) +#define RSCAN0TMTCSTS1HL (RSCAN0.TMTCSTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTCSTS1HH (RSCAN0.TMTCSTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTCSTS2 (RSCAN0.TMTCSTS2.UINT32) +#define RSCAN0TMTCSTS2L (RSCAN0.TMTCSTS2.UINT16[R_IO_L]) +#define RSCAN0TMTCSTS2LL (RSCAN0.TMTCSTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTCSTS2LH (RSCAN0.TMTCSTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTCSTS2H (RSCAN0.TMTCSTS2.UINT16[R_IO_H]) +#define RSCAN0TMTCSTS2HL (RSCAN0.TMTCSTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTCSTS2HH (RSCAN0.TMTCSTS2.UINT8[R_IO_HH]) +#define RSCAN0TMTASTS0 (RSCAN0.TMTASTS0.UINT32) +#define RSCAN0TMTASTS0L (RSCAN0.TMTASTS0.UINT16[R_IO_L]) +#define RSCAN0TMTASTS0LL (RSCAN0.TMTASTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTASTS0LH (RSCAN0.TMTASTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTASTS0H (RSCAN0.TMTASTS0.UINT16[R_IO_H]) +#define RSCAN0TMTASTS0HL (RSCAN0.TMTASTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTASTS0HH (RSCAN0.TMTASTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTASTS1 (RSCAN0.TMTASTS1.UINT32) +#define RSCAN0TMTASTS1L (RSCAN0.TMTASTS1.UINT16[R_IO_L]) +#define RSCAN0TMTASTS1LL (RSCAN0.TMTASTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTASTS1LH (RSCAN0.TMTASTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTASTS1H (RSCAN0.TMTASTS1.UINT16[R_IO_H]) +#define RSCAN0TMTASTS1HL (RSCAN0.TMTASTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTASTS1HH (RSCAN0.TMTASTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTASTS2 (RSCAN0.TMTASTS2.UINT32) +#define RSCAN0TMTASTS2L (RSCAN0.TMTASTS2.UINT16[R_IO_L]) +#define RSCAN0TMTASTS2LL (RSCAN0.TMTASTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTASTS2LH (RSCAN0.TMTASTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTASTS2H (RSCAN0.TMTASTS2.UINT16[R_IO_H]) +#define RSCAN0TMTASTS2HL (RSCAN0.TMTASTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTASTS2HH (RSCAN0.TMTASTS2.UINT8[R_IO_HH]) +#define RSCAN0TMIEC0 (RSCAN0.TMIEC0.UINT32) +#define RSCAN0TMIEC0L (RSCAN0.TMIEC0.UINT16[R_IO_L]) +#define RSCAN0TMIEC0LL (RSCAN0.TMIEC0.UINT8[R_IO_LL]) +#define RSCAN0TMIEC0LH (RSCAN0.TMIEC0.UINT8[R_IO_LH]) +#define RSCAN0TMIEC0H (RSCAN0.TMIEC0.UINT16[R_IO_H]) +#define RSCAN0TMIEC0HL (RSCAN0.TMIEC0.UINT8[R_IO_HL]) +#define RSCAN0TMIEC0HH (RSCAN0.TMIEC0.UINT8[R_IO_HH]) +#define RSCAN0TMIEC1 (RSCAN0.TMIEC1.UINT32) +#define RSCAN0TMIEC1L (RSCAN0.TMIEC1.UINT16[R_IO_L]) +#define RSCAN0TMIEC1LL (RSCAN0.TMIEC1.UINT8[R_IO_LL]) +#define RSCAN0TMIEC1LH (RSCAN0.TMIEC1.UINT8[R_IO_LH]) +#define RSCAN0TMIEC1H (RSCAN0.TMIEC1.UINT16[R_IO_H]) +#define RSCAN0TMIEC1HL (RSCAN0.TMIEC1.UINT8[R_IO_HL]) +#define RSCAN0TMIEC1HH (RSCAN0.TMIEC1.UINT8[R_IO_HH]) +#define RSCAN0TMIEC2 (RSCAN0.TMIEC2.UINT32) +#define RSCAN0TMIEC2L (RSCAN0.TMIEC2.UINT16[R_IO_L]) +#define RSCAN0TMIEC2LL (RSCAN0.TMIEC2.UINT8[R_IO_LL]) +#define RSCAN0TMIEC2LH (RSCAN0.TMIEC2.UINT8[R_IO_LH]) +#define RSCAN0TMIEC2H (RSCAN0.TMIEC2.UINT16[R_IO_H]) +#define RSCAN0TMIEC2HL (RSCAN0.TMIEC2.UINT8[R_IO_HL]) +#define RSCAN0TMIEC2HH (RSCAN0.TMIEC2.UINT8[R_IO_HH]) +#define RSCAN0TXQCC0 (RSCAN0.TXQCC0.UINT32) +#define RSCAN0TXQCC0L (RSCAN0.TXQCC0.UINT16[R_IO_L]) +#define RSCAN0TXQCC0LL (RSCAN0.TXQCC0.UINT8[R_IO_LL]) +#define RSCAN0TXQCC0LH (RSCAN0.TXQCC0.UINT8[R_IO_LH]) +#define RSCAN0TXQCC0H (RSCAN0.TXQCC0.UINT16[R_IO_H]) +#define RSCAN0TXQCC0HL (RSCAN0.TXQCC0.UINT8[R_IO_HL]) +#define RSCAN0TXQCC0HH (RSCAN0.TXQCC0.UINT8[R_IO_HH]) +#define RSCAN0TXQCC1 (RSCAN0.TXQCC1.UINT32) +#define RSCAN0TXQCC1L (RSCAN0.TXQCC1.UINT16[R_IO_L]) +#define RSCAN0TXQCC1LL (RSCAN0.TXQCC1.UINT8[R_IO_LL]) +#define RSCAN0TXQCC1LH (RSCAN0.TXQCC1.UINT8[R_IO_LH]) +#define RSCAN0TXQCC1H (RSCAN0.TXQCC1.UINT16[R_IO_H]) +#define RSCAN0TXQCC1HL (RSCAN0.TXQCC1.UINT8[R_IO_HL]) +#define RSCAN0TXQCC1HH (RSCAN0.TXQCC1.UINT8[R_IO_HH]) +#define RSCAN0TXQCC2 (RSCAN0.TXQCC2.UINT32) +#define RSCAN0TXQCC2L (RSCAN0.TXQCC2.UINT16[R_IO_L]) +#define RSCAN0TXQCC2LL (RSCAN0.TXQCC2.UINT8[R_IO_LL]) +#define RSCAN0TXQCC2LH (RSCAN0.TXQCC2.UINT8[R_IO_LH]) +#define RSCAN0TXQCC2H (RSCAN0.TXQCC2.UINT16[R_IO_H]) +#define RSCAN0TXQCC2HL (RSCAN0.TXQCC2.UINT8[R_IO_HL]) +#define RSCAN0TXQCC2HH (RSCAN0.TXQCC2.UINT8[R_IO_HH]) +#define RSCAN0TXQCC3 (RSCAN0.TXQCC3.UINT32) +#define RSCAN0TXQCC3L (RSCAN0.TXQCC3.UINT16[R_IO_L]) +#define RSCAN0TXQCC3LL (RSCAN0.TXQCC3.UINT8[R_IO_LL]) +#define RSCAN0TXQCC3LH (RSCAN0.TXQCC3.UINT8[R_IO_LH]) +#define RSCAN0TXQCC3H (RSCAN0.TXQCC3.UINT16[R_IO_H]) +#define RSCAN0TXQCC3HL (RSCAN0.TXQCC3.UINT8[R_IO_HL]) +#define RSCAN0TXQCC3HH (RSCAN0.TXQCC3.UINT8[R_IO_HH]) +#define RSCAN0TXQCC4 (RSCAN0.TXQCC4.UINT32) +#define RSCAN0TXQCC4L (RSCAN0.TXQCC4.UINT16[R_IO_L]) +#define RSCAN0TXQCC4LL (RSCAN0.TXQCC4.UINT8[R_IO_LL]) +#define RSCAN0TXQCC4LH (RSCAN0.TXQCC4.UINT8[R_IO_LH]) +#define RSCAN0TXQCC4H (RSCAN0.TXQCC4.UINT16[R_IO_H]) +#define RSCAN0TXQCC4HL (RSCAN0.TXQCC4.UINT8[R_IO_HL]) +#define RSCAN0TXQCC4HH (RSCAN0.TXQCC4.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS0 (RSCAN0.TXQSTS0.UINT32) +#define RSCAN0TXQSTS0L (RSCAN0.TXQSTS0.UINT16[R_IO_L]) +#define RSCAN0TXQSTS0LL (RSCAN0.TXQSTS0.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS0LH (RSCAN0.TXQSTS0.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS0H (RSCAN0.TXQSTS0.UINT16[R_IO_H]) +#define RSCAN0TXQSTS0HL (RSCAN0.TXQSTS0.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS0HH (RSCAN0.TXQSTS0.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS1 (RSCAN0.TXQSTS1.UINT32) +#define RSCAN0TXQSTS1L (RSCAN0.TXQSTS1.UINT16[R_IO_L]) +#define RSCAN0TXQSTS1LL (RSCAN0.TXQSTS1.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS1LH (RSCAN0.TXQSTS1.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS1H (RSCAN0.TXQSTS1.UINT16[R_IO_H]) +#define RSCAN0TXQSTS1HL (RSCAN0.TXQSTS1.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS1HH (RSCAN0.TXQSTS1.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS2 (RSCAN0.TXQSTS2.UINT32) +#define RSCAN0TXQSTS2L (RSCAN0.TXQSTS2.UINT16[R_IO_L]) +#define RSCAN0TXQSTS2LL (RSCAN0.TXQSTS2.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS2LH (RSCAN0.TXQSTS2.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS2H (RSCAN0.TXQSTS2.UINT16[R_IO_H]) +#define RSCAN0TXQSTS2HL (RSCAN0.TXQSTS2.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS2HH (RSCAN0.TXQSTS2.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS3 (RSCAN0.TXQSTS3.UINT32) +#define RSCAN0TXQSTS3L (RSCAN0.TXQSTS3.UINT16[R_IO_L]) +#define RSCAN0TXQSTS3LL (RSCAN0.TXQSTS3.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS3LH (RSCAN0.TXQSTS3.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS3H (RSCAN0.TXQSTS3.UINT16[R_IO_H]) +#define RSCAN0TXQSTS3HL (RSCAN0.TXQSTS3.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS3HH (RSCAN0.TXQSTS3.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS4 (RSCAN0.TXQSTS4.UINT32) +#define RSCAN0TXQSTS4L (RSCAN0.TXQSTS4.UINT16[R_IO_L]) +#define RSCAN0TXQSTS4LL (RSCAN0.TXQSTS4.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS4LH (RSCAN0.TXQSTS4.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS4H (RSCAN0.TXQSTS4.UINT16[R_IO_H]) +#define RSCAN0TXQSTS4HL (RSCAN0.TXQSTS4.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS4HH (RSCAN0.TXQSTS4.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR0 (RSCAN0.TXQPCTR0.UINT32) +#define RSCAN0TXQPCTR0L (RSCAN0.TXQPCTR0.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR0LL (RSCAN0.TXQPCTR0.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR0LH (RSCAN0.TXQPCTR0.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR0H (RSCAN0.TXQPCTR0.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR0HL (RSCAN0.TXQPCTR0.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR0HH (RSCAN0.TXQPCTR0.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR1 (RSCAN0.TXQPCTR1.UINT32) +#define RSCAN0TXQPCTR1L (RSCAN0.TXQPCTR1.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR1LL (RSCAN0.TXQPCTR1.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR1LH (RSCAN0.TXQPCTR1.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR1H (RSCAN0.TXQPCTR1.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR1HL (RSCAN0.TXQPCTR1.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR1HH (RSCAN0.TXQPCTR1.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR2 (RSCAN0.TXQPCTR2.UINT32) +#define RSCAN0TXQPCTR2L (RSCAN0.TXQPCTR2.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR2LL (RSCAN0.TXQPCTR2.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR2LH (RSCAN0.TXQPCTR2.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR2H (RSCAN0.TXQPCTR2.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR2HL (RSCAN0.TXQPCTR2.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR2HH (RSCAN0.TXQPCTR2.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR3 (RSCAN0.TXQPCTR3.UINT32) +#define RSCAN0TXQPCTR3L (RSCAN0.TXQPCTR3.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR3LL (RSCAN0.TXQPCTR3.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR3LH (RSCAN0.TXQPCTR3.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR3H (RSCAN0.TXQPCTR3.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR3HL (RSCAN0.TXQPCTR3.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR3HH (RSCAN0.TXQPCTR3.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR4 (RSCAN0.TXQPCTR4.UINT32) +#define RSCAN0TXQPCTR4L (RSCAN0.TXQPCTR4.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR4LL (RSCAN0.TXQPCTR4.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR4LH (RSCAN0.TXQPCTR4.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR4H (RSCAN0.TXQPCTR4.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR4HL (RSCAN0.TXQPCTR4.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR4HH (RSCAN0.TXQPCTR4.UINT8[R_IO_HH]) +#define RSCAN0THLCC0 (RSCAN0.THLCC0.UINT32) +#define RSCAN0THLCC0L (RSCAN0.THLCC0.UINT16[R_IO_L]) +#define RSCAN0THLCC0LL (RSCAN0.THLCC0.UINT8[R_IO_LL]) +#define RSCAN0THLCC0LH (RSCAN0.THLCC0.UINT8[R_IO_LH]) +#define RSCAN0THLCC0H (RSCAN0.THLCC0.UINT16[R_IO_H]) +#define RSCAN0THLCC0HL (RSCAN0.THLCC0.UINT8[R_IO_HL]) +#define RSCAN0THLCC0HH (RSCAN0.THLCC0.UINT8[R_IO_HH]) +#define RSCAN0THLCC1 (RSCAN0.THLCC1.UINT32) +#define RSCAN0THLCC1L (RSCAN0.THLCC1.UINT16[R_IO_L]) +#define RSCAN0THLCC1LL (RSCAN0.THLCC1.UINT8[R_IO_LL]) +#define RSCAN0THLCC1LH (RSCAN0.THLCC1.UINT8[R_IO_LH]) +#define RSCAN0THLCC1H (RSCAN0.THLCC1.UINT16[R_IO_H]) +#define RSCAN0THLCC1HL (RSCAN0.THLCC1.UINT8[R_IO_HL]) +#define RSCAN0THLCC1HH (RSCAN0.THLCC1.UINT8[R_IO_HH]) +#define RSCAN0THLCC2 (RSCAN0.THLCC2.UINT32) +#define RSCAN0THLCC2L (RSCAN0.THLCC2.UINT16[R_IO_L]) +#define RSCAN0THLCC2LL (RSCAN0.THLCC2.UINT8[R_IO_LL]) +#define RSCAN0THLCC2LH (RSCAN0.THLCC2.UINT8[R_IO_LH]) +#define RSCAN0THLCC2H (RSCAN0.THLCC2.UINT16[R_IO_H]) +#define RSCAN0THLCC2HL (RSCAN0.THLCC2.UINT8[R_IO_HL]) +#define RSCAN0THLCC2HH (RSCAN0.THLCC2.UINT8[R_IO_HH]) +#define RSCAN0THLCC3 (RSCAN0.THLCC3.UINT32) +#define RSCAN0THLCC3L (RSCAN0.THLCC3.UINT16[R_IO_L]) +#define RSCAN0THLCC3LL (RSCAN0.THLCC3.UINT8[R_IO_LL]) +#define RSCAN0THLCC3LH (RSCAN0.THLCC3.UINT8[R_IO_LH]) +#define RSCAN0THLCC3H (RSCAN0.THLCC3.UINT16[R_IO_H]) +#define RSCAN0THLCC3HL (RSCAN0.THLCC3.UINT8[R_IO_HL]) +#define RSCAN0THLCC3HH (RSCAN0.THLCC3.UINT8[R_IO_HH]) +#define RSCAN0THLCC4 (RSCAN0.THLCC4.UINT32) +#define RSCAN0THLCC4L (RSCAN0.THLCC4.UINT16[R_IO_L]) +#define RSCAN0THLCC4LL (RSCAN0.THLCC4.UINT8[R_IO_LL]) +#define RSCAN0THLCC4LH (RSCAN0.THLCC4.UINT8[R_IO_LH]) +#define RSCAN0THLCC4H (RSCAN0.THLCC4.UINT16[R_IO_H]) +#define RSCAN0THLCC4HL (RSCAN0.THLCC4.UINT8[R_IO_HL]) +#define RSCAN0THLCC4HH (RSCAN0.THLCC4.UINT8[R_IO_HH]) +#define RSCAN0THLSTS0 (RSCAN0.THLSTS0.UINT32) +#define RSCAN0THLSTS0L (RSCAN0.THLSTS0.UINT16[R_IO_L]) +#define RSCAN0THLSTS0LL (RSCAN0.THLSTS0.UINT8[R_IO_LL]) +#define RSCAN0THLSTS0LH (RSCAN0.THLSTS0.UINT8[R_IO_LH]) +#define RSCAN0THLSTS0H (RSCAN0.THLSTS0.UINT16[R_IO_H]) +#define RSCAN0THLSTS0HL (RSCAN0.THLSTS0.UINT8[R_IO_HL]) +#define RSCAN0THLSTS0HH (RSCAN0.THLSTS0.UINT8[R_IO_HH]) +#define RSCAN0THLSTS1 (RSCAN0.THLSTS1.UINT32) +#define RSCAN0THLSTS1L (RSCAN0.THLSTS1.UINT16[R_IO_L]) +#define RSCAN0THLSTS1LL (RSCAN0.THLSTS1.UINT8[R_IO_LL]) +#define RSCAN0THLSTS1LH (RSCAN0.THLSTS1.UINT8[R_IO_LH]) +#define RSCAN0THLSTS1H (RSCAN0.THLSTS1.UINT16[R_IO_H]) +#define RSCAN0THLSTS1HL (RSCAN0.THLSTS1.UINT8[R_IO_HL]) +#define RSCAN0THLSTS1HH (RSCAN0.THLSTS1.UINT8[R_IO_HH]) +#define RSCAN0THLSTS2 (RSCAN0.THLSTS2.UINT32) +#define RSCAN0THLSTS2L (RSCAN0.THLSTS2.UINT16[R_IO_L]) +#define RSCAN0THLSTS2LL (RSCAN0.THLSTS2.UINT8[R_IO_LL]) +#define RSCAN0THLSTS2LH (RSCAN0.THLSTS2.UINT8[R_IO_LH]) +#define RSCAN0THLSTS2H (RSCAN0.THLSTS2.UINT16[R_IO_H]) +#define RSCAN0THLSTS2HL (RSCAN0.THLSTS2.UINT8[R_IO_HL]) +#define RSCAN0THLSTS2HH (RSCAN0.THLSTS2.UINT8[R_IO_HH]) +#define RSCAN0THLSTS3 (RSCAN0.THLSTS3.UINT32) +#define RSCAN0THLSTS3L (RSCAN0.THLSTS3.UINT16[R_IO_L]) +#define RSCAN0THLSTS3LL (RSCAN0.THLSTS3.UINT8[R_IO_LL]) +#define RSCAN0THLSTS3LH (RSCAN0.THLSTS3.UINT8[R_IO_LH]) +#define RSCAN0THLSTS3H (RSCAN0.THLSTS3.UINT16[R_IO_H]) +#define RSCAN0THLSTS3HL (RSCAN0.THLSTS3.UINT8[R_IO_HL]) +#define RSCAN0THLSTS3HH (RSCAN0.THLSTS3.UINT8[R_IO_HH]) +#define RSCAN0THLSTS4 (RSCAN0.THLSTS4.UINT32) +#define RSCAN0THLSTS4L (RSCAN0.THLSTS4.UINT16[R_IO_L]) +#define RSCAN0THLSTS4LL (RSCAN0.THLSTS4.UINT8[R_IO_LL]) +#define RSCAN0THLSTS4LH (RSCAN0.THLSTS4.UINT8[R_IO_LH]) +#define RSCAN0THLSTS4H (RSCAN0.THLSTS4.UINT16[R_IO_H]) +#define RSCAN0THLSTS4HL (RSCAN0.THLSTS4.UINT8[R_IO_HL]) +#define RSCAN0THLSTS4HH (RSCAN0.THLSTS4.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR0 (RSCAN0.THLPCTR0.UINT32) +#define RSCAN0THLPCTR0L (RSCAN0.THLPCTR0.UINT16[R_IO_L]) +#define RSCAN0THLPCTR0LL (RSCAN0.THLPCTR0.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR0LH (RSCAN0.THLPCTR0.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR0H (RSCAN0.THLPCTR0.UINT16[R_IO_H]) +#define RSCAN0THLPCTR0HL (RSCAN0.THLPCTR0.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR0HH (RSCAN0.THLPCTR0.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR1 (RSCAN0.THLPCTR1.UINT32) +#define RSCAN0THLPCTR1L (RSCAN0.THLPCTR1.UINT16[R_IO_L]) +#define RSCAN0THLPCTR1LL (RSCAN0.THLPCTR1.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR1LH (RSCAN0.THLPCTR1.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR1H (RSCAN0.THLPCTR1.UINT16[R_IO_H]) +#define RSCAN0THLPCTR1HL (RSCAN0.THLPCTR1.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR1HH (RSCAN0.THLPCTR1.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR2 (RSCAN0.THLPCTR2.UINT32) +#define RSCAN0THLPCTR2L (RSCAN0.THLPCTR2.UINT16[R_IO_L]) +#define RSCAN0THLPCTR2LL (RSCAN0.THLPCTR2.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR2LH (RSCAN0.THLPCTR2.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR2H (RSCAN0.THLPCTR2.UINT16[R_IO_H]) +#define RSCAN0THLPCTR2HL (RSCAN0.THLPCTR2.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR2HH (RSCAN0.THLPCTR2.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR3 (RSCAN0.THLPCTR3.UINT32) +#define RSCAN0THLPCTR3L (RSCAN0.THLPCTR3.UINT16[R_IO_L]) +#define RSCAN0THLPCTR3LL (RSCAN0.THLPCTR3.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR3LH (RSCAN0.THLPCTR3.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR3H (RSCAN0.THLPCTR3.UINT16[R_IO_H]) +#define RSCAN0THLPCTR3HL (RSCAN0.THLPCTR3.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR3HH (RSCAN0.THLPCTR3.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR4 (RSCAN0.THLPCTR4.UINT32) +#define RSCAN0THLPCTR4L (RSCAN0.THLPCTR4.UINT16[R_IO_L]) +#define RSCAN0THLPCTR4LL (RSCAN0.THLPCTR4.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR4LH (RSCAN0.THLPCTR4.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR4H (RSCAN0.THLPCTR4.UINT16[R_IO_H]) +#define RSCAN0THLPCTR4HL (RSCAN0.THLPCTR4.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR4HH (RSCAN0.THLPCTR4.UINT8[R_IO_HH]) +#define RSCAN0GTINTSTS0 (RSCAN0.GTINTSTS0.UINT32) +#define RSCAN0GTINTSTS0L (RSCAN0.GTINTSTS0.UINT16[R_IO_L]) +#define RSCAN0GTINTSTS0LL (RSCAN0.GTINTSTS0.UINT8[R_IO_LL]) +#define RSCAN0GTINTSTS0LH (RSCAN0.GTINTSTS0.UINT8[R_IO_LH]) +#define RSCAN0GTINTSTS0H (RSCAN0.GTINTSTS0.UINT16[R_IO_H]) +#define RSCAN0GTINTSTS0HL (RSCAN0.GTINTSTS0.UINT8[R_IO_HL]) +#define RSCAN0GTINTSTS0HH (RSCAN0.GTINTSTS0.UINT8[R_IO_HH]) +#define RSCAN0GTINTSTS1 (RSCAN0.GTINTSTS1.UINT32) +#define RSCAN0GTINTSTS1L (RSCAN0.GTINTSTS1.UINT16[R_IO_L]) +#define RSCAN0GTINTSTS1LL (RSCAN0.GTINTSTS1.UINT8[R_IO_LL]) +#define RSCAN0GTINTSTS1LH (RSCAN0.GTINTSTS1.UINT8[R_IO_LH]) +#define RSCAN0GTINTSTS1H (RSCAN0.GTINTSTS1.UINT16[R_IO_H]) +#define RSCAN0GTINTSTS1HL (RSCAN0.GTINTSTS1.UINT8[R_IO_HL]) +#define RSCAN0GTINTSTS1HH (RSCAN0.GTINTSTS1.UINT8[R_IO_HH]) +#define RSCAN0GTSTCFG (RSCAN0.GTSTCFG.UINT32) +#define RSCAN0GTSTCFGL (RSCAN0.GTSTCFG.UINT16[R_IO_L]) +#define RSCAN0GTSTCFGLL (RSCAN0.GTSTCFG.UINT8[R_IO_LL]) +#define RSCAN0GTSTCFGLH (RSCAN0.GTSTCFG.UINT8[R_IO_LH]) +#define RSCAN0GTSTCFGH (RSCAN0.GTSTCFG.UINT16[R_IO_H]) +#define RSCAN0GTSTCFGHL (RSCAN0.GTSTCFG.UINT8[R_IO_HL]) +#define RSCAN0GTSTCFGHH (RSCAN0.GTSTCFG.UINT8[R_IO_HH]) +#define RSCAN0GTSTCTR (RSCAN0.GTSTCTR.UINT32) +#define RSCAN0GTSTCTRL (RSCAN0.GTSTCTR.UINT16[R_IO_L]) +#define RSCAN0GTSTCTRLL (RSCAN0.GTSTCTR.UINT8[R_IO_LL]) +#define RSCAN0GTSTCTRLH (RSCAN0.GTSTCTR.UINT8[R_IO_LH]) +#define RSCAN0GTSTCTRH (RSCAN0.GTSTCTR.UINT16[R_IO_H]) +#define RSCAN0GTSTCTRHL (RSCAN0.GTSTCTR.UINT8[R_IO_HL]) +#define RSCAN0GTSTCTRHH (RSCAN0.GTSTCTR.UINT8[R_IO_HH]) +#define RSCAN0GLOCKK (RSCAN0.GLOCKK.UINT32) +#define RSCAN0GLOCKKL (RSCAN0.GLOCKK.UINT16[R_IO_L]) +#define RSCAN0GLOCKKH (RSCAN0.GLOCKK.UINT16[R_IO_H]) +#define RSCAN0GAFLID0 (RSCAN0.GAFLID0.UINT32) +#define RSCAN0GAFLID0L (RSCAN0.GAFLID0.UINT16[R_IO_L]) +#define RSCAN0GAFLID0LL (RSCAN0.GAFLID0.UINT8[R_IO_LL]) +#define RSCAN0GAFLID0LH (RSCAN0.GAFLID0.UINT8[R_IO_LH]) +#define RSCAN0GAFLID0H (RSCAN0.GAFLID0.UINT16[R_IO_H]) +#define RSCAN0GAFLID0HL (RSCAN0.GAFLID0.UINT8[R_IO_HL]) +#define RSCAN0GAFLID0HH (RSCAN0.GAFLID0.UINT8[R_IO_HH]) +#define RSCAN0GAFLM0 (RSCAN0.GAFLM0.UINT32) +#define RSCAN0GAFLM0L (RSCAN0.GAFLM0.UINT16[R_IO_L]) +#define RSCAN0GAFLM0LL (RSCAN0.GAFLM0.UINT8[R_IO_LL]) +#define RSCAN0GAFLM0LH (RSCAN0.GAFLM0.UINT8[R_IO_LH]) +#define RSCAN0GAFLM0H (RSCAN0.GAFLM0.UINT16[R_IO_H]) +#define RSCAN0GAFLM0HL (RSCAN0.GAFLM0.UINT8[R_IO_HL]) +#define RSCAN0GAFLM0HH (RSCAN0.GAFLM0.UINT8[R_IO_HH]) +#define RSCAN0GAFLP00 (RSCAN0.GAFLP00.UINT32) +#define RSCAN0GAFLP00L (RSCAN0.GAFLP00.UINT16[R_IO_L]) +#define RSCAN0GAFLP00LL (RSCAN0.GAFLP00.UINT8[R_IO_LL]) +#define RSCAN0GAFLP00LH (RSCAN0.GAFLP00.UINT8[R_IO_LH]) +#define RSCAN0GAFLP00H (RSCAN0.GAFLP00.UINT16[R_IO_H]) +#define RSCAN0GAFLP00HL (RSCAN0.GAFLP00.UINT8[R_IO_HL]) +#define RSCAN0GAFLP00HH (RSCAN0.GAFLP00.UINT8[R_IO_HH]) +#define RSCAN0GAFLP10 (RSCAN0.GAFLP10.UINT32) +#define RSCAN0GAFLP10L (RSCAN0.GAFLP10.UINT16[R_IO_L]) +#define RSCAN0GAFLP10LL (RSCAN0.GAFLP10.UINT8[R_IO_LL]) +#define RSCAN0GAFLP10LH (RSCAN0.GAFLP10.UINT8[R_IO_LH]) +#define RSCAN0GAFLP10H (RSCAN0.GAFLP10.UINT16[R_IO_H]) +#define RSCAN0GAFLP10HL (RSCAN0.GAFLP10.UINT8[R_IO_HL]) +#define RSCAN0GAFLP10HH (RSCAN0.GAFLP10.UINT8[R_IO_HH]) +#define RSCAN0GAFLID1 (RSCAN0.GAFLID1.UINT32) +#define RSCAN0GAFLID1L (RSCAN0.GAFLID1.UINT16[R_IO_L]) +#define RSCAN0GAFLID1LL (RSCAN0.GAFLID1.UINT8[R_IO_LL]) +#define RSCAN0GAFLID1LH (RSCAN0.GAFLID1.UINT8[R_IO_LH]) +#define RSCAN0GAFLID1H (RSCAN0.GAFLID1.UINT16[R_IO_H]) +#define RSCAN0GAFLID1HL (RSCAN0.GAFLID1.UINT8[R_IO_HL]) +#define RSCAN0GAFLID1HH (RSCAN0.GAFLID1.UINT8[R_IO_HH]) +#define RSCAN0GAFLM1 (RSCAN0.GAFLM1.UINT32) +#define RSCAN0GAFLM1L (RSCAN0.GAFLM1.UINT16[R_IO_L]) +#define RSCAN0GAFLM1LL (RSCAN0.GAFLM1.UINT8[R_IO_LL]) +#define RSCAN0GAFLM1LH (RSCAN0.GAFLM1.UINT8[R_IO_LH]) +#define RSCAN0GAFLM1H (RSCAN0.GAFLM1.UINT16[R_IO_H]) +#define RSCAN0GAFLM1HL (RSCAN0.GAFLM1.UINT8[R_IO_HL]) +#define RSCAN0GAFLM1HH (RSCAN0.GAFLM1.UINT8[R_IO_HH]) +#define RSCAN0GAFLP01 (RSCAN0.GAFLP01.UINT32) +#define RSCAN0GAFLP01L (RSCAN0.GAFLP01.UINT16[R_IO_L]) +#define RSCAN0GAFLP01LL (RSCAN0.GAFLP01.UINT8[R_IO_LL]) +#define RSCAN0GAFLP01LH (RSCAN0.GAFLP01.UINT8[R_IO_LH]) +#define RSCAN0GAFLP01H (RSCAN0.GAFLP01.UINT16[R_IO_H]) +#define RSCAN0GAFLP01HL (RSCAN0.GAFLP01.UINT8[R_IO_HL]) +#define RSCAN0GAFLP01HH (RSCAN0.GAFLP01.UINT8[R_IO_HH]) +#define RSCAN0GAFLP11 (RSCAN0.GAFLP11.UINT32) +#define RSCAN0GAFLP11L (RSCAN0.GAFLP11.UINT16[R_IO_L]) +#define RSCAN0GAFLP11LL (RSCAN0.GAFLP11.UINT8[R_IO_LL]) +#define RSCAN0GAFLP11LH (RSCAN0.GAFLP11.UINT8[R_IO_LH]) +#define RSCAN0GAFLP11H (RSCAN0.GAFLP11.UINT16[R_IO_H]) +#define RSCAN0GAFLP11HL (RSCAN0.GAFLP11.UINT8[R_IO_HL]) +#define RSCAN0GAFLP11HH (RSCAN0.GAFLP11.UINT8[R_IO_HH]) +#define RSCAN0GAFLID2 (RSCAN0.GAFLID2.UINT32) +#define RSCAN0GAFLID2L (RSCAN0.GAFLID2.UINT16[R_IO_L]) +#define RSCAN0GAFLID2LL (RSCAN0.GAFLID2.UINT8[R_IO_LL]) +#define RSCAN0GAFLID2LH (RSCAN0.GAFLID2.UINT8[R_IO_LH]) +#define RSCAN0GAFLID2H (RSCAN0.GAFLID2.UINT16[R_IO_H]) +#define RSCAN0GAFLID2HL (RSCAN0.GAFLID2.UINT8[R_IO_HL]) +#define RSCAN0GAFLID2HH (RSCAN0.GAFLID2.UINT8[R_IO_HH]) +#define RSCAN0GAFLM2 (RSCAN0.GAFLM2.UINT32) +#define RSCAN0GAFLM2L (RSCAN0.GAFLM2.UINT16[R_IO_L]) +#define RSCAN0GAFLM2LL (RSCAN0.GAFLM2.UINT8[R_IO_LL]) +#define RSCAN0GAFLM2LH (RSCAN0.GAFLM2.UINT8[R_IO_LH]) +#define RSCAN0GAFLM2H (RSCAN0.GAFLM2.UINT16[R_IO_H]) +#define RSCAN0GAFLM2HL (RSCAN0.GAFLM2.UINT8[R_IO_HL]) +#define RSCAN0GAFLM2HH (RSCAN0.GAFLM2.UINT8[R_IO_HH]) +#define RSCAN0GAFLP02 (RSCAN0.GAFLP02.UINT32) +#define RSCAN0GAFLP02L (RSCAN0.GAFLP02.UINT16[R_IO_L]) +#define RSCAN0GAFLP02LL (RSCAN0.GAFLP02.UINT8[R_IO_LL]) +#define RSCAN0GAFLP02LH (RSCAN0.GAFLP02.UINT8[R_IO_LH]) +#define RSCAN0GAFLP02H (RSCAN0.GAFLP02.UINT16[R_IO_H]) +#define RSCAN0GAFLP02HL (RSCAN0.GAFLP02.UINT8[R_IO_HL]) +#define RSCAN0GAFLP02HH (RSCAN0.GAFLP02.UINT8[R_IO_HH]) +#define RSCAN0GAFLP12 (RSCAN0.GAFLP12.UINT32) +#define RSCAN0GAFLP12L (RSCAN0.GAFLP12.UINT16[R_IO_L]) +#define RSCAN0GAFLP12LL (RSCAN0.GAFLP12.UINT8[R_IO_LL]) +#define RSCAN0GAFLP12LH (RSCAN0.GAFLP12.UINT8[R_IO_LH]) +#define RSCAN0GAFLP12H (RSCAN0.GAFLP12.UINT16[R_IO_H]) +#define RSCAN0GAFLP12HL (RSCAN0.GAFLP12.UINT8[R_IO_HL]) +#define RSCAN0GAFLP12HH (RSCAN0.GAFLP12.UINT8[R_IO_HH]) +#define RSCAN0GAFLID3 (RSCAN0.GAFLID3.UINT32) +#define RSCAN0GAFLID3L (RSCAN0.GAFLID3.UINT16[R_IO_L]) +#define RSCAN0GAFLID3LL (RSCAN0.GAFLID3.UINT8[R_IO_LL]) +#define RSCAN0GAFLID3LH (RSCAN0.GAFLID3.UINT8[R_IO_LH]) +#define RSCAN0GAFLID3H (RSCAN0.GAFLID3.UINT16[R_IO_H]) +#define RSCAN0GAFLID3HL (RSCAN0.GAFLID3.UINT8[R_IO_HL]) +#define RSCAN0GAFLID3HH (RSCAN0.GAFLID3.UINT8[R_IO_HH]) +#define RSCAN0GAFLM3 (RSCAN0.GAFLM3.UINT32) +#define RSCAN0GAFLM3L (RSCAN0.GAFLM3.UINT16[R_IO_L]) +#define RSCAN0GAFLM3LL (RSCAN0.GAFLM3.UINT8[R_IO_LL]) +#define RSCAN0GAFLM3LH (RSCAN0.GAFLM3.UINT8[R_IO_LH]) +#define RSCAN0GAFLM3H (RSCAN0.GAFLM3.UINT16[R_IO_H]) +#define RSCAN0GAFLM3HL (RSCAN0.GAFLM3.UINT8[R_IO_HL]) +#define RSCAN0GAFLM3HH (RSCAN0.GAFLM3.UINT8[R_IO_HH]) +#define RSCAN0GAFLP03 (RSCAN0.GAFLP03.UINT32) +#define RSCAN0GAFLP03L (RSCAN0.GAFLP03.UINT16[R_IO_L]) +#define RSCAN0GAFLP03LL (RSCAN0.GAFLP03.UINT8[R_IO_LL]) +#define RSCAN0GAFLP03LH (RSCAN0.GAFLP03.UINT8[R_IO_LH]) +#define RSCAN0GAFLP03H (RSCAN0.GAFLP03.UINT16[R_IO_H]) +#define RSCAN0GAFLP03HL (RSCAN0.GAFLP03.UINT8[R_IO_HL]) +#define RSCAN0GAFLP03HH (RSCAN0.GAFLP03.UINT8[R_IO_HH]) +#define RSCAN0GAFLP13 (RSCAN0.GAFLP13.UINT32) +#define RSCAN0GAFLP13L (RSCAN0.GAFLP13.UINT16[R_IO_L]) +#define RSCAN0GAFLP13LL (RSCAN0.GAFLP13.UINT8[R_IO_LL]) +#define RSCAN0GAFLP13LH (RSCAN0.GAFLP13.UINT8[R_IO_LH]) +#define RSCAN0GAFLP13H (RSCAN0.GAFLP13.UINT16[R_IO_H]) +#define RSCAN0GAFLP13HL (RSCAN0.GAFLP13.UINT8[R_IO_HL]) +#define RSCAN0GAFLP13HH (RSCAN0.GAFLP13.UINT8[R_IO_HH]) +#define RSCAN0GAFLID4 (RSCAN0.GAFLID4.UINT32) +#define RSCAN0GAFLID4L (RSCAN0.GAFLID4.UINT16[R_IO_L]) +#define RSCAN0GAFLID4LL (RSCAN0.GAFLID4.UINT8[R_IO_LL]) +#define RSCAN0GAFLID4LH (RSCAN0.GAFLID4.UINT8[R_IO_LH]) +#define RSCAN0GAFLID4H (RSCAN0.GAFLID4.UINT16[R_IO_H]) +#define RSCAN0GAFLID4HL (RSCAN0.GAFLID4.UINT8[R_IO_HL]) +#define RSCAN0GAFLID4HH (RSCAN0.GAFLID4.UINT8[R_IO_HH]) +#define RSCAN0GAFLM4 (RSCAN0.GAFLM4.UINT32) +#define RSCAN0GAFLM4L (RSCAN0.GAFLM4.UINT16[R_IO_L]) +#define RSCAN0GAFLM4LL (RSCAN0.GAFLM4.UINT8[R_IO_LL]) +#define RSCAN0GAFLM4LH (RSCAN0.GAFLM4.UINT8[R_IO_LH]) +#define RSCAN0GAFLM4H (RSCAN0.GAFLM4.UINT16[R_IO_H]) +#define RSCAN0GAFLM4HL (RSCAN0.GAFLM4.UINT8[R_IO_HL]) +#define RSCAN0GAFLM4HH (RSCAN0.GAFLM4.UINT8[R_IO_HH]) +#define RSCAN0GAFLP04 (RSCAN0.GAFLP04.UINT32) +#define RSCAN0GAFLP04L (RSCAN0.GAFLP04.UINT16[R_IO_L]) +#define RSCAN0GAFLP04LL (RSCAN0.GAFLP04.UINT8[R_IO_LL]) +#define RSCAN0GAFLP04LH (RSCAN0.GAFLP04.UINT8[R_IO_LH]) +#define RSCAN0GAFLP04H (RSCAN0.GAFLP04.UINT16[R_IO_H]) +#define RSCAN0GAFLP04HL (RSCAN0.GAFLP04.UINT8[R_IO_HL]) +#define RSCAN0GAFLP04HH (RSCAN0.GAFLP04.UINT8[R_IO_HH]) +#define RSCAN0GAFLP14 (RSCAN0.GAFLP14.UINT32) +#define RSCAN0GAFLP14L (RSCAN0.GAFLP14.UINT16[R_IO_L]) +#define RSCAN0GAFLP14LL (RSCAN0.GAFLP14.UINT8[R_IO_LL]) +#define RSCAN0GAFLP14LH (RSCAN0.GAFLP14.UINT8[R_IO_LH]) +#define RSCAN0GAFLP14H (RSCAN0.GAFLP14.UINT16[R_IO_H]) +#define RSCAN0GAFLP14HL (RSCAN0.GAFLP14.UINT8[R_IO_HL]) +#define RSCAN0GAFLP14HH (RSCAN0.GAFLP14.UINT8[R_IO_HH]) +#define RSCAN0GAFLID5 (RSCAN0.GAFLID5.UINT32) +#define RSCAN0GAFLID5L (RSCAN0.GAFLID5.UINT16[R_IO_L]) +#define RSCAN0GAFLID5LL (RSCAN0.GAFLID5.UINT8[R_IO_LL]) +#define RSCAN0GAFLID5LH (RSCAN0.GAFLID5.UINT8[R_IO_LH]) +#define RSCAN0GAFLID5H (RSCAN0.GAFLID5.UINT16[R_IO_H]) +#define RSCAN0GAFLID5HL (RSCAN0.GAFLID5.UINT8[R_IO_HL]) +#define RSCAN0GAFLID5HH (RSCAN0.GAFLID5.UINT8[R_IO_HH]) +#define RSCAN0GAFLM5 (RSCAN0.GAFLM5.UINT32) +#define RSCAN0GAFLM5L (RSCAN0.GAFLM5.UINT16[R_IO_L]) +#define RSCAN0GAFLM5LL (RSCAN0.GAFLM5.UINT8[R_IO_LL]) +#define RSCAN0GAFLM5LH (RSCAN0.GAFLM5.UINT8[R_IO_LH]) +#define RSCAN0GAFLM5H (RSCAN0.GAFLM5.UINT16[R_IO_H]) +#define RSCAN0GAFLM5HL (RSCAN0.GAFLM5.UINT8[R_IO_HL]) +#define RSCAN0GAFLM5HH (RSCAN0.GAFLM5.UINT8[R_IO_HH]) +#define RSCAN0GAFLP05 (RSCAN0.GAFLP05.UINT32) +#define RSCAN0GAFLP05L (RSCAN0.GAFLP05.UINT16[R_IO_L]) +#define RSCAN0GAFLP05LL (RSCAN0.GAFLP05.UINT8[R_IO_LL]) +#define RSCAN0GAFLP05LH (RSCAN0.GAFLP05.UINT8[R_IO_LH]) +#define RSCAN0GAFLP05H (RSCAN0.GAFLP05.UINT16[R_IO_H]) +#define RSCAN0GAFLP05HL (RSCAN0.GAFLP05.UINT8[R_IO_HL]) +#define RSCAN0GAFLP05HH (RSCAN0.GAFLP05.UINT8[R_IO_HH]) +#define RSCAN0GAFLP15 (RSCAN0.GAFLP15.UINT32) +#define RSCAN0GAFLP15L (RSCAN0.GAFLP15.UINT16[R_IO_L]) +#define RSCAN0GAFLP15LL (RSCAN0.GAFLP15.UINT8[R_IO_LL]) +#define RSCAN0GAFLP15LH (RSCAN0.GAFLP15.UINT8[R_IO_LH]) +#define RSCAN0GAFLP15H (RSCAN0.GAFLP15.UINT16[R_IO_H]) +#define RSCAN0GAFLP15HL (RSCAN0.GAFLP15.UINT8[R_IO_HL]) +#define RSCAN0GAFLP15HH (RSCAN0.GAFLP15.UINT8[R_IO_HH]) +#define RSCAN0GAFLID6 (RSCAN0.GAFLID6.UINT32) +#define RSCAN0GAFLID6L (RSCAN0.GAFLID6.UINT16[R_IO_L]) +#define RSCAN0GAFLID6LL (RSCAN0.GAFLID6.UINT8[R_IO_LL]) +#define RSCAN0GAFLID6LH (RSCAN0.GAFLID6.UINT8[R_IO_LH]) +#define RSCAN0GAFLID6H (RSCAN0.GAFLID6.UINT16[R_IO_H]) +#define RSCAN0GAFLID6HL (RSCAN0.GAFLID6.UINT8[R_IO_HL]) +#define RSCAN0GAFLID6HH (RSCAN0.GAFLID6.UINT8[R_IO_HH]) +#define RSCAN0GAFLM6 (RSCAN0.GAFLM6.UINT32) +#define RSCAN0GAFLM6L (RSCAN0.GAFLM6.UINT16[R_IO_L]) +#define RSCAN0GAFLM6LL (RSCAN0.GAFLM6.UINT8[R_IO_LL]) +#define RSCAN0GAFLM6LH (RSCAN0.GAFLM6.UINT8[R_IO_LH]) +#define RSCAN0GAFLM6H (RSCAN0.GAFLM6.UINT16[R_IO_H]) +#define RSCAN0GAFLM6HL (RSCAN0.GAFLM6.UINT8[R_IO_HL]) +#define RSCAN0GAFLM6HH (RSCAN0.GAFLM6.UINT8[R_IO_HH]) +#define RSCAN0GAFLP06 (RSCAN0.GAFLP06.UINT32) +#define RSCAN0GAFLP06L (RSCAN0.GAFLP06.UINT16[R_IO_L]) +#define RSCAN0GAFLP06LL (RSCAN0.GAFLP06.UINT8[R_IO_LL]) +#define RSCAN0GAFLP06LH (RSCAN0.GAFLP06.UINT8[R_IO_LH]) +#define RSCAN0GAFLP06H (RSCAN0.GAFLP06.UINT16[R_IO_H]) +#define RSCAN0GAFLP06HL (RSCAN0.GAFLP06.UINT8[R_IO_HL]) +#define RSCAN0GAFLP06HH (RSCAN0.GAFLP06.UINT8[R_IO_HH]) +#define RSCAN0GAFLP16 (RSCAN0.GAFLP16.UINT32) +#define RSCAN0GAFLP16L (RSCAN0.GAFLP16.UINT16[R_IO_L]) +#define RSCAN0GAFLP16LL (RSCAN0.GAFLP16.UINT8[R_IO_LL]) +#define RSCAN0GAFLP16LH (RSCAN0.GAFLP16.UINT8[R_IO_LH]) +#define RSCAN0GAFLP16H (RSCAN0.GAFLP16.UINT16[R_IO_H]) +#define RSCAN0GAFLP16HL (RSCAN0.GAFLP16.UINT8[R_IO_HL]) +#define RSCAN0GAFLP16HH (RSCAN0.GAFLP16.UINT8[R_IO_HH]) +#define RSCAN0GAFLID7 (RSCAN0.GAFLID7.UINT32) +#define RSCAN0GAFLID7L (RSCAN0.GAFLID7.UINT16[R_IO_L]) +#define RSCAN0GAFLID7LL (RSCAN0.GAFLID7.UINT8[R_IO_LL]) +#define RSCAN0GAFLID7LH (RSCAN0.GAFLID7.UINT8[R_IO_LH]) +#define RSCAN0GAFLID7H (RSCAN0.GAFLID7.UINT16[R_IO_H]) +#define RSCAN0GAFLID7HL (RSCAN0.GAFLID7.UINT8[R_IO_HL]) +#define RSCAN0GAFLID7HH (RSCAN0.GAFLID7.UINT8[R_IO_HH]) +#define RSCAN0GAFLM7 (RSCAN0.GAFLM7.UINT32) +#define RSCAN0GAFLM7L (RSCAN0.GAFLM7.UINT16[R_IO_L]) +#define RSCAN0GAFLM7LL (RSCAN0.GAFLM7.UINT8[R_IO_LL]) +#define RSCAN0GAFLM7LH (RSCAN0.GAFLM7.UINT8[R_IO_LH]) +#define RSCAN0GAFLM7H (RSCAN0.GAFLM7.UINT16[R_IO_H]) +#define RSCAN0GAFLM7HL (RSCAN0.GAFLM7.UINT8[R_IO_HL]) +#define RSCAN0GAFLM7HH (RSCAN0.GAFLM7.UINT8[R_IO_HH]) +#define RSCAN0GAFLP07 (RSCAN0.GAFLP07.UINT32) +#define RSCAN0GAFLP07L (RSCAN0.GAFLP07.UINT16[R_IO_L]) +#define RSCAN0GAFLP07LL (RSCAN0.GAFLP07.UINT8[R_IO_LL]) +#define RSCAN0GAFLP07LH (RSCAN0.GAFLP07.UINT8[R_IO_LH]) +#define RSCAN0GAFLP07H (RSCAN0.GAFLP07.UINT16[R_IO_H]) +#define RSCAN0GAFLP07HL (RSCAN0.GAFLP07.UINT8[R_IO_HL]) +#define RSCAN0GAFLP07HH (RSCAN0.GAFLP07.UINT8[R_IO_HH]) +#define RSCAN0GAFLP17 (RSCAN0.GAFLP17.UINT32) +#define RSCAN0GAFLP17L (RSCAN0.GAFLP17.UINT16[R_IO_L]) +#define RSCAN0GAFLP17LL (RSCAN0.GAFLP17.UINT8[R_IO_LL]) +#define RSCAN0GAFLP17LH (RSCAN0.GAFLP17.UINT8[R_IO_LH]) +#define RSCAN0GAFLP17H (RSCAN0.GAFLP17.UINT16[R_IO_H]) +#define RSCAN0GAFLP17HL (RSCAN0.GAFLP17.UINT8[R_IO_HL]) +#define RSCAN0GAFLP17HH (RSCAN0.GAFLP17.UINT8[R_IO_HH]) +#define RSCAN0GAFLID8 (RSCAN0.GAFLID8.UINT32) +#define RSCAN0GAFLID8L (RSCAN0.GAFLID8.UINT16[R_IO_L]) +#define RSCAN0GAFLID8LL (RSCAN0.GAFLID8.UINT8[R_IO_LL]) +#define RSCAN0GAFLID8LH (RSCAN0.GAFLID8.UINT8[R_IO_LH]) +#define RSCAN0GAFLID8H (RSCAN0.GAFLID8.UINT16[R_IO_H]) +#define RSCAN0GAFLID8HL (RSCAN0.GAFLID8.UINT8[R_IO_HL]) +#define RSCAN0GAFLID8HH (RSCAN0.GAFLID8.UINT8[R_IO_HH]) +#define RSCAN0GAFLM8 (RSCAN0.GAFLM8.UINT32) +#define RSCAN0GAFLM8L (RSCAN0.GAFLM8.UINT16[R_IO_L]) +#define RSCAN0GAFLM8LL (RSCAN0.GAFLM8.UINT8[R_IO_LL]) +#define RSCAN0GAFLM8LH (RSCAN0.GAFLM8.UINT8[R_IO_LH]) +#define RSCAN0GAFLM8H (RSCAN0.GAFLM8.UINT16[R_IO_H]) +#define RSCAN0GAFLM8HL (RSCAN0.GAFLM8.UINT8[R_IO_HL]) +#define RSCAN0GAFLM8HH (RSCAN0.GAFLM8.UINT8[R_IO_HH]) +#define RSCAN0GAFLP08 (RSCAN0.GAFLP08.UINT32) +#define RSCAN0GAFLP08L (RSCAN0.GAFLP08.UINT16[R_IO_L]) +#define RSCAN0GAFLP08LL (RSCAN0.GAFLP08.UINT8[R_IO_LL]) +#define RSCAN0GAFLP08LH (RSCAN0.GAFLP08.UINT8[R_IO_LH]) +#define RSCAN0GAFLP08H (RSCAN0.GAFLP08.UINT16[R_IO_H]) +#define RSCAN0GAFLP08HL (RSCAN0.GAFLP08.UINT8[R_IO_HL]) +#define RSCAN0GAFLP08HH (RSCAN0.GAFLP08.UINT8[R_IO_HH]) +#define RSCAN0GAFLP18 (RSCAN0.GAFLP18.UINT32) +#define RSCAN0GAFLP18L (RSCAN0.GAFLP18.UINT16[R_IO_L]) +#define RSCAN0GAFLP18LL (RSCAN0.GAFLP18.UINT8[R_IO_LL]) +#define RSCAN0GAFLP18LH (RSCAN0.GAFLP18.UINT8[R_IO_LH]) +#define RSCAN0GAFLP18H (RSCAN0.GAFLP18.UINT16[R_IO_H]) +#define RSCAN0GAFLP18HL (RSCAN0.GAFLP18.UINT8[R_IO_HL]) +#define RSCAN0GAFLP18HH (RSCAN0.GAFLP18.UINT8[R_IO_HH]) +#define RSCAN0GAFLID9 (RSCAN0.GAFLID9.UINT32) +#define RSCAN0GAFLID9L (RSCAN0.GAFLID9.UINT16[R_IO_L]) +#define RSCAN0GAFLID9LL (RSCAN0.GAFLID9.UINT8[R_IO_LL]) +#define RSCAN0GAFLID9LH (RSCAN0.GAFLID9.UINT8[R_IO_LH]) +#define RSCAN0GAFLID9H (RSCAN0.GAFLID9.UINT16[R_IO_H]) +#define RSCAN0GAFLID9HL (RSCAN0.GAFLID9.UINT8[R_IO_HL]) +#define RSCAN0GAFLID9HH (RSCAN0.GAFLID9.UINT8[R_IO_HH]) +#define RSCAN0GAFLM9 (RSCAN0.GAFLM9.UINT32) +#define RSCAN0GAFLM9L (RSCAN0.GAFLM9.UINT16[R_IO_L]) +#define RSCAN0GAFLM9LL (RSCAN0.GAFLM9.UINT8[R_IO_LL]) +#define RSCAN0GAFLM9LH (RSCAN0.GAFLM9.UINT8[R_IO_LH]) +#define RSCAN0GAFLM9H (RSCAN0.GAFLM9.UINT16[R_IO_H]) +#define RSCAN0GAFLM9HL (RSCAN0.GAFLM9.UINT8[R_IO_HL]) +#define RSCAN0GAFLM9HH (RSCAN0.GAFLM9.UINT8[R_IO_HH]) +#define RSCAN0GAFLP09 (RSCAN0.GAFLP09.UINT32) +#define RSCAN0GAFLP09L (RSCAN0.GAFLP09.UINT16[R_IO_L]) +#define RSCAN0GAFLP09LL (RSCAN0.GAFLP09.UINT8[R_IO_LL]) +#define RSCAN0GAFLP09LH (RSCAN0.GAFLP09.UINT8[R_IO_LH]) +#define RSCAN0GAFLP09H (RSCAN0.GAFLP09.UINT16[R_IO_H]) +#define RSCAN0GAFLP09HL (RSCAN0.GAFLP09.UINT8[R_IO_HL]) +#define RSCAN0GAFLP09HH (RSCAN0.GAFLP09.UINT8[R_IO_HH]) +#define RSCAN0GAFLP19 (RSCAN0.GAFLP19.UINT32) +#define RSCAN0GAFLP19L (RSCAN0.GAFLP19.UINT16[R_IO_L]) +#define RSCAN0GAFLP19LL (RSCAN0.GAFLP19.UINT8[R_IO_LL]) +#define RSCAN0GAFLP19LH (RSCAN0.GAFLP19.UINT8[R_IO_LH]) +#define RSCAN0GAFLP19H (RSCAN0.GAFLP19.UINT16[R_IO_H]) +#define RSCAN0GAFLP19HL (RSCAN0.GAFLP19.UINT8[R_IO_HL]) +#define RSCAN0GAFLP19HH (RSCAN0.GAFLP19.UINT8[R_IO_HH]) +#define RSCAN0GAFLID10 (RSCAN0.GAFLID10.UINT32) +#define RSCAN0GAFLID10L (RSCAN0.GAFLID10.UINT16[R_IO_L]) +#define RSCAN0GAFLID10LL (RSCAN0.GAFLID10.UINT8[R_IO_LL]) +#define RSCAN0GAFLID10LH (RSCAN0.GAFLID10.UINT8[R_IO_LH]) +#define RSCAN0GAFLID10H (RSCAN0.GAFLID10.UINT16[R_IO_H]) +#define RSCAN0GAFLID10HL (RSCAN0.GAFLID10.UINT8[R_IO_HL]) +#define RSCAN0GAFLID10HH (RSCAN0.GAFLID10.UINT8[R_IO_HH]) +#define RSCAN0GAFLM10 (RSCAN0.GAFLM10.UINT32) +#define RSCAN0GAFLM10L (RSCAN0.GAFLM10.UINT16[R_IO_L]) +#define RSCAN0GAFLM10LL (RSCAN0.GAFLM10.UINT8[R_IO_LL]) +#define RSCAN0GAFLM10LH (RSCAN0.GAFLM10.UINT8[R_IO_LH]) +#define RSCAN0GAFLM10H (RSCAN0.GAFLM10.UINT16[R_IO_H]) +#define RSCAN0GAFLM10HL (RSCAN0.GAFLM10.UINT8[R_IO_HL]) +#define RSCAN0GAFLM10HH (RSCAN0.GAFLM10.UINT8[R_IO_HH]) +#define RSCAN0GAFLP010 (RSCAN0.GAFLP010.UINT32) +#define RSCAN0GAFLP010L (RSCAN0.GAFLP010.UINT16[R_IO_L]) +#define RSCAN0GAFLP010LL (RSCAN0.GAFLP010.UINT8[R_IO_LL]) +#define RSCAN0GAFLP010LH (RSCAN0.GAFLP010.UINT8[R_IO_LH]) +#define RSCAN0GAFLP010H (RSCAN0.GAFLP010.UINT16[R_IO_H]) +#define RSCAN0GAFLP010HL (RSCAN0.GAFLP010.UINT8[R_IO_HL]) +#define RSCAN0GAFLP010HH (RSCAN0.GAFLP010.UINT8[R_IO_HH]) +#define RSCAN0GAFLP110 (RSCAN0.GAFLP110.UINT32) +#define RSCAN0GAFLP110L (RSCAN0.GAFLP110.UINT16[R_IO_L]) +#define RSCAN0GAFLP110LL (RSCAN0.GAFLP110.UINT8[R_IO_LL]) +#define RSCAN0GAFLP110LH (RSCAN0.GAFLP110.UINT8[R_IO_LH]) +#define RSCAN0GAFLP110H (RSCAN0.GAFLP110.UINT16[R_IO_H]) +#define RSCAN0GAFLP110HL (RSCAN0.GAFLP110.UINT8[R_IO_HL]) +#define RSCAN0GAFLP110HH (RSCAN0.GAFLP110.UINT8[R_IO_HH]) +#define RSCAN0GAFLID11 (RSCAN0.GAFLID11.UINT32) +#define RSCAN0GAFLID11L (RSCAN0.GAFLID11.UINT16[R_IO_L]) +#define RSCAN0GAFLID11LL (RSCAN0.GAFLID11.UINT8[R_IO_LL]) +#define RSCAN0GAFLID11LH (RSCAN0.GAFLID11.UINT8[R_IO_LH]) +#define RSCAN0GAFLID11H (RSCAN0.GAFLID11.UINT16[R_IO_H]) +#define RSCAN0GAFLID11HL (RSCAN0.GAFLID11.UINT8[R_IO_HL]) +#define RSCAN0GAFLID11HH (RSCAN0.GAFLID11.UINT8[R_IO_HH]) +#define RSCAN0GAFLM11 (RSCAN0.GAFLM11.UINT32) +#define RSCAN0GAFLM11L (RSCAN0.GAFLM11.UINT16[R_IO_L]) +#define RSCAN0GAFLM11LL (RSCAN0.GAFLM11.UINT8[R_IO_LL]) +#define RSCAN0GAFLM11LH (RSCAN0.GAFLM11.UINT8[R_IO_LH]) +#define RSCAN0GAFLM11H (RSCAN0.GAFLM11.UINT16[R_IO_H]) +#define RSCAN0GAFLM11HL (RSCAN0.GAFLM11.UINT8[R_IO_HL]) +#define RSCAN0GAFLM11HH (RSCAN0.GAFLM11.UINT8[R_IO_HH]) +#define RSCAN0GAFLP011 (RSCAN0.GAFLP011.UINT32) +#define RSCAN0GAFLP011L (RSCAN0.GAFLP011.UINT16[R_IO_L]) +#define RSCAN0GAFLP011LL (RSCAN0.GAFLP011.UINT8[R_IO_LL]) +#define RSCAN0GAFLP011LH (RSCAN0.GAFLP011.UINT8[R_IO_LH]) +#define RSCAN0GAFLP011H (RSCAN0.GAFLP011.UINT16[R_IO_H]) +#define RSCAN0GAFLP011HL (RSCAN0.GAFLP011.UINT8[R_IO_HL]) +#define RSCAN0GAFLP011HH (RSCAN0.GAFLP011.UINT8[R_IO_HH]) +#define RSCAN0GAFLP111 (RSCAN0.GAFLP111.UINT32) +#define RSCAN0GAFLP111L (RSCAN0.GAFLP111.UINT16[R_IO_L]) +#define RSCAN0GAFLP111LL (RSCAN0.GAFLP111.UINT8[R_IO_LL]) +#define RSCAN0GAFLP111LH (RSCAN0.GAFLP111.UINT8[R_IO_LH]) +#define RSCAN0GAFLP111H (RSCAN0.GAFLP111.UINT16[R_IO_H]) +#define RSCAN0GAFLP111HL (RSCAN0.GAFLP111.UINT8[R_IO_HL]) +#define RSCAN0GAFLP111HH (RSCAN0.GAFLP111.UINT8[R_IO_HH]) +#define RSCAN0GAFLID12 (RSCAN0.GAFLID12.UINT32) +#define RSCAN0GAFLID12L (RSCAN0.GAFLID12.UINT16[R_IO_L]) +#define RSCAN0GAFLID12LL (RSCAN0.GAFLID12.UINT8[R_IO_LL]) +#define RSCAN0GAFLID12LH (RSCAN0.GAFLID12.UINT8[R_IO_LH]) +#define RSCAN0GAFLID12H (RSCAN0.GAFLID12.UINT16[R_IO_H]) +#define RSCAN0GAFLID12HL (RSCAN0.GAFLID12.UINT8[R_IO_HL]) +#define RSCAN0GAFLID12HH (RSCAN0.GAFLID12.UINT8[R_IO_HH]) +#define RSCAN0GAFLM12 (RSCAN0.GAFLM12.UINT32) +#define RSCAN0GAFLM12L (RSCAN0.GAFLM12.UINT16[R_IO_L]) +#define RSCAN0GAFLM12LL (RSCAN0.GAFLM12.UINT8[R_IO_LL]) +#define RSCAN0GAFLM12LH (RSCAN0.GAFLM12.UINT8[R_IO_LH]) +#define RSCAN0GAFLM12H (RSCAN0.GAFLM12.UINT16[R_IO_H]) +#define RSCAN0GAFLM12HL (RSCAN0.GAFLM12.UINT8[R_IO_HL]) +#define RSCAN0GAFLM12HH (RSCAN0.GAFLM12.UINT8[R_IO_HH]) +#define RSCAN0GAFLP012 (RSCAN0.GAFLP012.UINT32) +#define RSCAN0GAFLP012L (RSCAN0.GAFLP012.UINT16[R_IO_L]) +#define RSCAN0GAFLP012LL (RSCAN0.GAFLP012.UINT8[R_IO_LL]) +#define RSCAN0GAFLP012LH (RSCAN0.GAFLP012.UINT8[R_IO_LH]) +#define RSCAN0GAFLP012H (RSCAN0.GAFLP012.UINT16[R_IO_H]) +#define RSCAN0GAFLP012HL (RSCAN0.GAFLP012.UINT8[R_IO_HL]) +#define RSCAN0GAFLP012HH (RSCAN0.GAFLP012.UINT8[R_IO_HH]) +#define RSCAN0GAFLP112 (RSCAN0.GAFLP112.UINT32) +#define RSCAN0GAFLP112L (RSCAN0.GAFLP112.UINT16[R_IO_L]) +#define RSCAN0GAFLP112LL (RSCAN0.GAFLP112.UINT8[R_IO_LL]) +#define RSCAN0GAFLP112LH (RSCAN0.GAFLP112.UINT8[R_IO_LH]) +#define RSCAN0GAFLP112H (RSCAN0.GAFLP112.UINT16[R_IO_H]) +#define RSCAN0GAFLP112HL (RSCAN0.GAFLP112.UINT8[R_IO_HL]) +#define RSCAN0GAFLP112HH (RSCAN0.GAFLP112.UINT8[R_IO_HH]) +#define RSCAN0GAFLID13 (RSCAN0.GAFLID13.UINT32) +#define RSCAN0GAFLID13L (RSCAN0.GAFLID13.UINT16[R_IO_L]) +#define RSCAN0GAFLID13LL (RSCAN0.GAFLID13.UINT8[R_IO_LL]) +#define RSCAN0GAFLID13LH (RSCAN0.GAFLID13.UINT8[R_IO_LH]) +#define RSCAN0GAFLID13H (RSCAN0.GAFLID13.UINT16[R_IO_H]) +#define RSCAN0GAFLID13HL (RSCAN0.GAFLID13.UINT8[R_IO_HL]) +#define RSCAN0GAFLID13HH (RSCAN0.GAFLID13.UINT8[R_IO_HH]) +#define RSCAN0GAFLM13 (RSCAN0.GAFLM13.UINT32) +#define RSCAN0GAFLM13L (RSCAN0.GAFLM13.UINT16[R_IO_L]) +#define RSCAN0GAFLM13LL (RSCAN0.GAFLM13.UINT8[R_IO_LL]) +#define RSCAN0GAFLM13LH (RSCAN0.GAFLM13.UINT8[R_IO_LH]) +#define RSCAN0GAFLM13H (RSCAN0.GAFLM13.UINT16[R_IO_H]) +#define RSCAN0GAFLM13HL (RSCAN0.GAFLM13.UINT8[R_IO_HL]) +#define RSCAN0GAFLM13HH (RSCAN0.GAFLM13.UINT8[R_IO_HH]) +#define RSCAN0GAFLP013 (RSCAN0.GAFLP013.UINT32) +#define RSCAN0GAFLP013L (RSCAN0.GAFLP013.UINT16[R_IO_L]) +#define RSCAN0GAFLP013LL (RSCAN0.GAFLP013.UINT8[R_IO_LL]) +#define RSCAN0GAFLP013LH (RSCAN0.GAFLP013.UINT8[R_IO_LH]) +#define RSCAN0GAFLP013H (RSCAN0.GAFLP013.UINT16[R_IO_H]) +#define RSCAN0GAFLP013HL (RSCAN0.GAFLP013.UINT8[R_IO_HL]) +#define RSCAN0GAFLP013HH (RSCAN0.GAFLP013.UINT8[R_IO_HH]) +#define RSCAN0GAFLP113 (RSCAN0.GAFLP113.UINT32) +#define RSCAN0GAFLP113L (RSCAN0.GAFLP113.UINT16[R_IO_L]) +#define RSCAN0GAFLP113LL (RSCAN0.GAFLP113.UINT8[R_IO_LL]) +#define RSCAN0GAFLP113LH (RSCAN0.GAFLP113.UINT8[R_IO_LH]) +#define RSCAN0GAFLP113H (RSCAN0.GAFLP113.UINT16[R_IO_H]) +#define RSCAN0GAFLP113HL (RSCAN0.GAFLP113.UINT8[R_IO_HL]) +#define RSCAN0GAFLP113HH (RSCAN0.GAFLP113.UINT8[R_IO_HH]) +#define RSCAN0GAFLID14 (RSCAN0.GAFLID14.UINT32) +#define RSCAN0GAFLID14L (RSCAN0.GAFLID14.UINT16[R_IO_L]) +#define RSCAN0GAFLID14LL (RSCAN0.GAFLID14.UINT8[R_IO_LL]) +#define RSCAN0GAFLID14LH (RSCAN0.GAFLID14.UINT8[R_IO_LH]) +#define RSCAN0GAFLID14H (RSCAN0.GAFLID14.UINT16[R_IO_H]) +#define RSCAN0GAFLID14HL (RSCAN0.GAFLID14.UINT8[R_IO_HL]) +#define RSCAN0GAFLID14HH (RSCAN0.GAFLID14.UINT8[R_IO_HH]) +#define RSCAN0GAFLM14 (RSCAN0.GAFLM14.UINT32) +#define RSCAN0GAFLM14L (RSCAN0.GAFLM14.UINT16[R_IO_L]) +#define RSCAN0GAFLM14LL (RSCAN0.GAFLM14.UINT8[R_IO_LL]) +#define RSCAN0GAFLM14LH (RSCAN0.GAFLM14.UINT8[R_IO_LH]) +#define RSCAN0GAFLM14H (RSCAN0.GAFLM14.UINT16[R_IO_H]) +#define RSCAN0GAFLM14HL (RSCAN0.GAFLM14.UINT8[R_IO_HL]) +#define RSCAN0GAFLM14HH (RSCAN0.GAFLM14.UINT8[R_IO_HH]) +#define RSCAN0GAFLP014 (RSCAN0.GAFLP014.UINT32) +#define RSCAN0GAFLP014L (RSCAN0.GAFLP014.UINT16[R_IO_L]) +#define RSCAN0GAFLP014LL (RSCAN0.GAFLP014.UINT8[R_IO_LL]) +#define RSCAN0GAFLP014LH (RSCAN0.GAFLP014.UINT8[R_IO_LH]) +#define RSCAN0GAFLP014H (RSCAN0.GAFLP014.UINT16[R_IO_H]) +#define RSCAN0GAFLP014HL (RSCAN0.GAFLP014.UINT8[R_IO_HL]) +#define RSCAN0GAFLP014HH (RSCAN0.GAFLP014.UINT8[R_IO_HH]) +#define RSCAN0GAFLP114 (RSCAN0.GAFLP114.UINT32) +#define RSCAN0GAFLP114L (RSCAN0.GAFLP114.UINT16[R_IO_L]) +#define RSCAN0GAFLP114LL (RSCAN0.GAFLP114.UINT8[R_IO_LL]) +#define RSCAN0GAFLP114LH (RSCAN0.GAFLP114.UINT8[R_IO_LH]) +#define RSCAN0GAFLP114H (RSCAN0.GAFLP114.UINT16[R_IO_H]) +#define RSCAN0GAFLP114HL (RSCAN0.GAFLP114.UINT8[R_IO_HL]) +#define RSCAN0GAFLP114HH (RSCAN0.GAFLP114.UINT8[R_IO_HH]) +#define RSCAN0GAFLID15 (RSCAN0.GAFLID15.UINT32) +#define RSCAN0GAFLID15L (RSCAN0.GAFLID15.UINT16[R_IO_L]) +#define RSCAN0GAFLID15LL (RSCAN0.GAFLID15.UINT8[R_IO_LL]) +#define RSCAN0GAFLID15LH (RSCAN0.GAFLID15.UINT8[R_IO_LH]) +#define RSCAN0GAFLID15H (RSCAN0.GAFLID15.UINT16[R_IO_H]) +#define RSCAN0GAFLID15HL (RSCAN0.GAFLID15.UINT8[R_IO_HL]) +#define RSCAN0GAFLID15HH (RSCAN0.GAFLID15.UINT8[R_IO_HH]) +#define RSCAN0GAFLM15 (RSCAN0.GAFLM15.UINT32) +#define RSCAN0GAFLM15L (RSCAN0.GAFLM15.UINT16[R_IO_L]) +#define RSCAN0GAFLM15LL (RSCAN0.GAFLM15.UINT8[R_IO_LL]) +#define RSCAN0GAFLM15LH (RSCAN0.GAFLM15.UINT8[R_IO_LH]) +#define RSCAN0GAFLM15H (RSCAN0.GAFLM15.UINT16[R_IO_H]) +#define RSCAN0GAFLM15HL (RSCAN0.GAFLM15.UINT8[R_IO_HL]) +#define RSCAN0GAFLM15HH (RSCAN0.GAFLM15.UINT8[R_IO_HH]) +#define RSCAN0GAFLP015 (RSCAN0.GAFLP015.UINT32) +#define RSCAN0GAFLP015L (RSCAN0.GAFLP015.UINT16[R_IO_L]) +#define RSCAN0GAFLP015LL (RSCAN0.GAFLP015.UINT8[R_IO_LL]) +#define RSCAN0GAFLP015LH (RSCAN0.GAFLP015.UINT8[R_IO_LH]) +#define RSCAN0GAFLP015H (RSCAN0.GAFLP015.UINT16[R_IO_H]) +#define RSCAN0GAFLP015HL (RSCAN0.GAFLP015.UINT8[R_IO_HL]) +#define RSCAN0GAFLP015HH (RSCAN0.GAFLP015.UINT8[R_IO_HH]) +#define RSCAN0GAFLP115 (RSCAN0.GAFLP115.UINT32) +#define RSCAN0GAFLP115L (RSCAN0.GAFLP115.UINT16[R_IO_L]) +#define RSCAN0GAFLP115LL (RSCAN0.GAFLP115.UINT8[R_IO_LL]) +#define RSCAN0GAFLP115LH (RSCAN0.GAFLP115.UINT8[R_IO_LH]) +#define RSCAN0GAFLP115H (RSCAN0.GAFLP115.UINT16[R_IO_H]) +#define RSCAN0GAFLP115HL (RSCAN0.GAFLP115.UINT8[R_IO_HL]) +#define RSCAN0GAFLP115HH (RSCAN0.GAFLP115.UINT8[R_IO_HH]) +#define RSCAN0RMID0 (RSCAN0.RMID0.UINT32) +#define RSCAN0RMID0L (RSCAN0.RMID0.UINT16[R_IO_L]) +#define RSCAN0RMID0LL (RSCAN0.RMID0.UINT8[R_IO_LL]) +#define RSCAN0RMID0LH (RSCAN0.RMID0.UINT8[R_IO_LH]) +#define RSCAN0RMID0H (RSCAN0.RMID0.UINT16[R_IO_H]) +#define RSCAN0RMID0HL (RSCAN0.RMID0.UINT8[R_IO_HL]) +#define RSCAN0RMID0HH (RSCAN0.RMID0.UINT8[R_IO_HH]) +#define RSCAN0RMPTR0 (RSCAN0.RMPTR0.UINT32) +#define RSCAN0RMPTR0L (RSCAN0.RMPTR0.UINT16[R_IO_L]) +#define RSCAN0RMPTR0LL (RSCAN0.RMPTR0.UINT8[R_IO_LL]) +#define RSCAN0RMPTR0LH (RSCAN0.RMPTR0.UINT8[R_IO_LH]) +#define RSCAN0RMPTR0H (RSCAN0.RMPTR0.UINT16[R_IO_H]) +#define RSCAN0RMPTR0HL (RSCAN0.RMPTR0.UINT8[R_IO_HL]) +#define RSCAN0RMPTR0HH (RSCAN0.RMPTR0.UINT8[R_IO_HH]) +#define RSCAN0RMDF00 (RSCAN0.RMDF00.UINT32) +#define RSCAN0RMDF00L (RSCAN0.RMDF00.UINT16[R_IO_L]) +#define RSCAN0RMDF00LL (RSCAN0.RMDF00.UINT8[R_IO_LL]) +#define RSCAN0RMDF00LH (RSCAN0.RMDF00.UINT8[R_IO_LH]) +#define RSCAN0RMDF00H (RSCAN0.RMDF00.UINT16[R_IO_H]) +#define RSCAN0RMDF00HL (RSCAN0.RMDF00.UINT8[R_IO_HL]) +#define RSCAN0RMDF00HH (RSCAN0.RMDF00.UINT8[R_IO_HH]) +#define RSCAN0RMDF10 (RSCAN0.RMDF10.UINT32) +#define RSCAN0RMDF10L (RSCAN0.RMDF10.UINT16[R_IO_L]) +#define RSCAN0RMDF10LL (RSCAN0.RMDF10.UINT8[R_IO_LL]) +#define RSCAN0RMDF10LH (RSCAN0.RMDF10.UINT8[R_IO_LH]) +#define RSCAN0RMDF10H (RSCAN0.RMDF10.UINT16[R_IO_H]) +#define RSCAN0RMDF10HL (RSCAN0.RMDF10.UINT8[R_IO_HL]) +#define RSCAN0RMDF10HH (RSCAN0.RMDF10.UINT8[R_IO_HH]) +#define RSCAN0RMID1 (RSCAN0.RMID1.UINT32) +#define RSCAN0RMID1L (RSCAN0.RMID1.UINT16[R_IO_L]) +#define RSCAN0RMID1LL (RSCAN0.RMID1.UINT8[R_IO_LL]) +#define RSCAN0RMID1LH (RSCAN0.RMID1.UINT8[R_IO_LH]) +#define RSCAN0RMID1H (RSCAN0.RMID1.UINT16[R_IO_H]) +#define RSCAN0RMID1HL (RSCAN0.RMID1.UINT8[R_IO_HL]) +#define RSCAN0RMID1HH (RSCAN0.RMID1.UINT8[R_IO_HH]) +#define RSCAN0RMPTR1 (RSCAN0.RMPTR1.UINT32) +#define RSCAN0RMPTR1L (RSCAN0.RMPTR1.UINT16[R_IO_L]) +#define RSCAN0RMPTR1LL (RSCAN0.RMPTR1.UINT8[R_IO_LL]) +#define RSCAN0RMPTR1LH (RSCAN0.RMPTR1.UINT8[R_IO_LH]) +#define RSCAN0RMPTR1H (RSCAN0.RMPTR1.UINT16[R_IO_H]) +#define RSCAN0RMPTR1HL (RSCAN0.RMPTR1.UINT8[R_IO_HL]) +#define RSCAN0RMPTR1HH (RSCAN0.RMPTR1.UINT8[R_IO_HH]) +#define RSCAN0RMDF01 (RSCAN0.RMDF01.UINT32) +#define RSCAN0RMDF01L (RSCAN0.RMDF01.UINT16[R_IO_L]) +#define RSCAN0RMDF01LL (RSCAN0.RMDF01.UINT8[R_IO_LL]) +#define RSCAN0RMDF01LH (RSCAN0.RMDF01.UINT8[R_IO_LH]) +#define RSCAN0RMDF01H (RSCAN0.RMDF01.UINT16[R_IO_H]) +#define RSCAN0RMDF01HL (RSCAN0.RMDF01.UINT8[R_IO_HL]) +#define RSCAN0RMDF01HH (RSCAN0.RMDF01.UINT8[R_IO_HH]) +#define RSCAN0RMDF11 (RSCAN0.RMDF11.UINT32) +#define RSCAN0RMDF11L (RSCAN0.RMDF11.UINT16[R_IO_L]) +#define RSCAN0RMDF11LL (RSCAN0.RMDF11.UINT8[R_IO_LL]) +#define RSCAN0RMDF11LH (RSCAN0.RMDF11.UINT8[R_IO_LH]) +#define RSCAN0RMDF11H (RSCAN0.RMDF11.UINT16[R_IO_H]) +#define RSCAN0RMDF11HL (RSCAN0.RMDF11.UINT8[R_IO_HL]) +#define RSCAN0RMDF11HH (RSCAN0.RMDF11.UINT8[R_IO_HH]) +#define RSCAN0RMID2 (RSCAN0.RMID2.UINT32) +#define RSCAN0RMID2L (RSCAN0.RMID2.UINT16[R_IO_L]) +#define RSCAN0RMID2LL (RSCAN0.RMID2.UINT8[R_IO_LL]) +#define RSCAN0RMID2LH (RSCAN0.RMID2.UINT8[R_IO_LH]) +#define RSCAN0RMID2H (RSCAN0.RMID2.UINT16[R_IO_H]) +#define RSCAN0RMID2HL (RSCAN0.RMID2.UINT8[R_IO_HL]) +#define RSCAN0RMID2HH (RSCAN0.RMID2.UINT8[R_IO_HH]) +#define RSCAN0RMPTR2 (RSCAN0.RMPTR2.UINT32) +#define RSCAN0RMPTR2L (RSCAN0.RMPTR2.UINT16[R_IO_L]) +#define RSCAN0RMPTR2LL (RSCAN0.RMPTR2.UINT8[R_IO_LL]) +#define RSCAN0RMPTR2LH (RSCAN0.RMPTR2.UINT8[R_IO_LH]) +#define RSCAN0RMPTR2H (RSCAN0.RMPTR2.UINT16[R_IO_H]) +#define RSCAN0RMPTR2HL (RSCAN0.RMPTR2.UINT8[R_IO_HL]) +#define RSCAN0RMPTR2HH (RSCAN0.RMPTR2.UINT8[R_IO_HH]) +#define RSCAN0RMDF02 (RSCAN0.RMDF02.UINT32) +#define RSCAN0RMDF02L (RSCAN0.RMDF02.UINT16[R_IO_L]) +#define RSCAN0RMDF02LL (RSCAN0.RMDF02.UINT8[R_IO_LL]) +#define RSCAN0RMDF02LH (RSCAN0.RMDF02.UINT8[R_IO_LH]) +#define RSCAN0RMDF02H (RSCAN0.RMDF02.UINT16[R_IO_H]) +#define RSCAN0RMDF02HL (RSCAN0.RMDF02.UINT8[R_IO_HL]) +#define RSCAN0RMDF02HH (RSCAN0.RMDF02.UINT8[R_IO_HH]) +#define RSCAN0RMDF12 (RSCAN0.RMDF12.UINT32) +#define RSCAN0RMDF12L (RSCAN0.RMDF12.UINT16[R_IO_L]) +#define RSCAN0RMDF12LL (RSCAN0.RMDF12.UINT8[R_IO_LL]) +#define RSCAN0RMDF12LH (RSCAN0.RMDF12.UINT8[R_IO_LH]) +#define RSCAN0RMDF12H (RSCAN0.RMDF12.UINT16[R_IO_H]) +#define RSCAN0RMDF12HL (RSCAN0.RMDF12.UINT8[R_IO_HL]) +#define RSCAN0RMDF12HH (RSCAN0.RMDF12.UINT8[R_IO_HH]) +#define RSCAN0RMID3 (RSCAN0.RMID3.UINT32) +#define RSCAN0RMID3L (RSCAN0.RMID3.UINT16[R_IO_L]) +#define RSCAN0RMID3LL (RSCAN0.RMID3.UINT8[R_IO_LL]) +#define RSCAN0RMID3LH (RSCAN0.RMID3.UINT8[R_IO_LH]) +#define RSCAN0RMID3H (RSCAN0.RMID3.UINT16[R_IO_H]) +#define RSCAN0RMID3HL (RSCAN0.RMID3.UINT8[R_IO_HL]) +#define RSCAN0RMID3HH (RSCAN0.RMID3.UINT8[R_IO_HH]) +#define RSCAN0RMPTR3 (RSCAN0.RMPTR3.UINT32) +#define RSCAN0RMPTR3L (RSCAN0.RMPTR3.UINT16[R_IO_L]) +#define RSCAN0RMPTR3LL (RSCAN0.RMPTR3.UINT8[R_IO_LL]) +#define RSCAN0RMPTR3LH (RSCAN0.RMPTR3.UINT8[R_IO_LH]) +#define RSCAN0RMPTR3H (RSCAN0.RMPTR3.UINT16[R_IO_H]) +#define RSCAN0RMPTR3HL (RSCAN0.RMPTR3.UINT8[R_IO_HL]) +#define RSCAN0RMPTR3HH (RSCAN0.RMPTR3.UINT8[R_IO_HH]) +#define RSCAN0RMDF03 (RSCAN0.RMDF03.UINT32) +#define RSCAN0RMDF03L (RSCAN0.RMDF03.UINT16[R_IO_L]) +#define RSCAN0RMDF03LL (RSCAN0.RMDF03.UINT8[R_IO_LL]) +#define RSCAN0RMDF03LH (RSCAN0.RMDF03.UINT8[R_IO_LH]) +#define RSCAN0RMDF03H (RSCAN0.RMDF03.UINT16[R_IO_H]) +#define RSCAN0RMDF03HL (RSCAN0.RMDF03.UINT8[R_IO_HL]) +#define RSCAN0RMDF03HH (RSCAN0.RMDF03.UINT8[R_IO_HH]) +#define RSCAN0RMDF13 (RSCAN0.RMDF13.UINT32) +#define RSCAN0RMDF13L (RSCAN0.RMDF13.UINT16[R_IO_L]) +#define RSCAN0RMDF13LL (RSCAN0.RMDF13.UINT8[R_IO_LL]) +#define RSCAN0RMDF13LH (RSCAN0.RMDF13.UINT8[R_IO_LH]) +#define RSCAN0RMDF13H (RSCAN0.RMDF13.UINT16[R_IO_H]) +#define RSCAN0RMDF13HL (RSCAN0.RMDF13.UINT8[R_IO_HL]) +#define RSCAN0RMDF13HH (RSCAN0.RMDF13.UINT8[R_IO_HH]) +#define RSCAN0RMID4 (RSCAN0.RMID4.UINT32) +#define RSCAN0RMID4L (RSCAN0.RMID4.UINT16[R_IO_L]) +#define RSCAN0RMID4LL (RSCAN0.RMID4.UINT8[R_IO_LL]) +#define RSCAN0RMID4LH (RSCAN0.RMID4.UINT8[R_IO_LH]) +#define RSCAN0RMID4H (RSCAN0.RMID4.UINT16[R_IO_H]) +#define RSCAN0RMID4HL (RSCAN0.RMID4.UINT8[R_IO_HL]) +#define RSCAN0RMID4HH (RSCAN0.RMID4.UINT8[R_IO_HH]) +#define RSCAN0RMPTR4 (RSCAN0.RMPTR4.UINT32) +#define RSCAN0RMPTR4L (RSCAN0.RMPTR4.UINT16[R_IO_L]) +#define RSCAN0RMPTR4LL (RSCAN0.RMPTR4.UINT8[R_IO_LL]) +#define RSCAN0RMPTR4LH (RSCAN0.RMPTR4.UINT8[R_IO_LH]) +#define RSCAN0RMPTR4H (RSCAN0.RMPTR4.UINT16[R_IO_H]) +#define RSCAN0RMPTR4HL (RSCAN0.RMPTR4.UINT8[R_IO_HL]) +#define RSCAN0RMPTR4HH (RSCAN0.RMPTR4.UINT8[R_IO_HH]) +#define RSCAN0RMDF04 (RSCAN0.RMDF04.UINT32) +#define RSCAN0RMDF04L (RSCAN0.RMDF04.UINT16[R_IO_L]) +#define RSCAN0RMDF04LL (RSCAN0.RMDF04.UINT8[R_IO_LL]) +#define RSCAN0RMDF04LH (RSCAN0.RMDF04.UINT8[R_IO_LH]) +#define RSCAN0RMDF04H (RSCAN0.RMDF04.UINT16[R_IO_H]) +#define RSCAN0RMDF04HL (RSCAN0.RMDF04.UINT8[R_IO_HL]) +#define RSCAN0RMDF04HH (RSCAN0.RMDF04.UINT8[R_IO_HH]) +#define RSCAN0RMDF14 (RSCAN0.RMDF14.UINT32) +#define RSCAN0RMDF14L (RSCAN0.RMDF14.UINT16[R_IO_L]) +#define RSCAN0RMDF14LL (RSCAN0.RMDF14.UINT8[R_IO_LL]) +#define RSCAN0RMDF14LH (RSCAN0.RMDF14.UINT8[R_IO_LH]) +#define RSCAN0RMDF14H (RSCAN0.RMDF14.UINT16[R_IO_H]) +#define RSCAN0RMDF14HL (RSCAN0.RMDF14.UINT8[R_IO_HL]) +#define RSCAN0RMDF14HH (RSCAN0.RMDF14.UINT8[R_IO_HH]) +#define RSCAN0RMID5 (RSCAN0.RMID5.UINT32) +#define RSCAN0RMID5L (RSCAN0.RMID5.UINT16[R_IO_L]) +#define RSCAN0RMID5LL (RSCAN0.RMID5.UINT8[R_IO_LL]) +#define RSCAN0RMID5LH (RSCAN0.RMID5.UINT8[R_IO_LH]) +#define RSCAN0RMID5H (RSCAN0.RMID5.UINT16[R_IO_H]) +#define RSCAN0RMID5HL (RSCAN0.RMID5.UINT8[R_IO_HL]) +#define RSCAN0RMID5HH (RSCAN0.RMID5.UINT8[R_IO_HH]) +#define RSCAN0RMPTR5 (RSCAN0.RMPTR5.UINT32) +#define RSCAN0RMPTR5L (RSCAN0.RMPTR5.UINT16[R_IO_L]) +#define RSCAN0RMPTR5LL (RSCAN0.RMPTR5.UINT8[R_IO_LL]) +#define RSCAN0RMPTR5LH (RSCAN0.RMPTR5.UINT8[R_IO_LH]) +#define RSCAN0RMPTR5H (RSCAN0.RMPTR5.UINT16[R_IO_H]) +#define RSCAN0RMPTR5HL (RSCAN0.RMPTR5.UINT8[R_IO_HL]) +#define RSCAN0RMPTR5HH (RSCAN0.RMPTR5.UINT8[R_IO_HH]) +#define RSCAN0RMDF05 (RSCAN0.RMDF05.UINT32) +#define RSCAN0RMDF05L (RSCAN0.RMDF05.UINT16[R_IO_L]) +#define RSCAN0RMDF05LL (RSCAN0.RMDF05.UINT8[R_IO_LL]) +#define RSCAN0RMDF05LH (RSCAN0.RMDF05.UINT8[R_IO_LH]) +#define RSCAN0RMDF05H (RSCAN0.RMDF05.UINT16[R_IO_H]) +#define RSCAN0RMDF05HL (RSCAN0.RMDF05.UINT8[R_IO_HL]) +#define RSCAN0RMDF05HH (RSCAN0.RMDF05.UINT8[R_IO_HH]) +#define RSCAN0RMDF15 (RSCAN0.RMDF15.UINT32) +#define RSCAN0RMDF15L (RSCAN0.RMDF15.UINT16[R_IO_L]) +#define RSCAN0RMDF15LL (RSCAN0.RMDF15.UINT8[R_IO_LL]) +#define RSCAN0RMDF15LH (RSCAN0.RMDF15.UINT8[R_IO_LH]) +#define RSCAN0RMDF15H (RSCAN0.RMDF15.UINT16[R_IO_H]) +#define RSCAN0RMDF15HL (RSCAN0.RMDF15.UINT8[R_IO_HL]) +#define RSCAN0RMDF15HH (RSCAN0.RMDF15.UINT8[R_IO_HH]) +#define RSCAN0RMID6 (RSCAN0.RMID6.UINT32) +#define RSCAN0RMID6L (RSCAN0.RMID6.UINT16[R_IO_L]) +#define RSCAN0RMID6LL (RSCAN0.RMID6.UINT8[R_IO_LL]) +#define RSCAN0RMID6LH (RSCAN0.RMID6.UINT8[R_IO_LH]) +#define RSCAN0RMID6H (RSCAN0.RMID6.UINT16[R_IO_H]) +#define RSCAN0RMID6HL (RSCAN0.RMID6.UINT8[R_IO_HL]) +#define RSCAN0RMID6HH (RSCAN0.RMID6.UINT8[R_IO_HH]) +#define RSCAN0RMPTR6 (RSCAN0.RMPTR6.UINT32) +#define RSCAN0RMPTR6L (RSCAN0.RMPTR6.UINT16[R_IO_L]) +#define RSCAN0RMPTR6LL (RSCAN0.RMPTR6.UINT8[R_IO_LL]) +#define RSCAN0RMPTR6LH (RSCAN0.RMPTR6.UINT8[R_IO_LH]) +#define RSCAN0RMPTR6H (RSCAN0.RMPTR6.UINT16[R_IO_H]) +#define RSCAN0RMPTR6HL (RSCAN0.RMPTR6.UINT8[R_IO_HL]) +#define RSCAN0RMPTR6HH (RSCAN0.RMPTR6.UINT8[R_IO_HH]) +#define RSCAN0RMDF06 (RSCAN0.RMDF06.UINT32) +#define RSCAN0RMDF06L (RSCAN0.RMDF06.UINT16[R_IO_L]) +#define RSCAN0RMDF06LL (RSCAN0.RMDF06.UINT8[R_IO_LL]) +#define RSCAN0RMDF06LH (RSCAN0.RMDF06.UINT8[R_IO_LH]) +#define RSCAN0RMDF06H (RSCAN0.RMDF06.UINT16[R_IO_H]) +#define RSCAN0RMDF06HL (RSCAN0.RMDF06.UINT8[R_IO_HL]) +#define RSCAN0RMDF06HH (RSCAN0.RMDF06.UINT8[R_IO_HH]) +#define RSCAN0RMDF16 (RSCAN0.RMDF16.UINT32) +#define RSCAN0RMDF16L (RSCAN0.RMDF16.UINT16[R_IO_L]) +#define RSCAN0RMDF16LL (RSCAN0.RMDF16.UINT8[R_IO_LL]) +#define RSCAN0RMDF16LH (RSCAN0.RMDF16.UINT8[R_IO_LH]) +#define RSCAN0RMDF16H (RSCAN0.RMDF16.UINT16[R_IO_H]) +#define RSCAN0RMDF16HL (RSCAN0.RMDF16.UINT8[R_IO_HL]) +#define RSCAN0RMDF16HH (RSCAN0.RMDF16.UINT8[R_IO_HH]) +#define RSCAN0RMID7 (RSCAN0.RMID7.UINT32) +#define RSCAN0RMID7L (RSCAN0.RMID7.UINT16[R_IO_L]) +#define RSCAN0RMID7LL (RSCAN0.RMID7.UINT8[R_IO_LL]) +#define RSCAN0RMID7LH (RSCAN0.RMID7.UINT8[R_IO_LH]) +#define RSCAN0RMID7H (RSCAN0.RMID7.UINT16[R_IO_H]) +#define RSCAN0RMID7HL (RSCAN0.RMID7.UINT8[R_IO_HL]) +#define RSCAN0RMID7HH (RSCAN0.RMID7.UINT8[R_IO_HH]) +#define RSCAN0RMPTR7 (RSCAN0.RMPTR7.UINT32) +#define RSCAN0RMPTR7L (RSCAN0.RMPTR7.UINT16[R_IO_L]) +#define RSCAN0RMPTR7LL (RSCAN0.RMPTR7.UINT8[R_IO_LL]) +#define RSCAN0RMPTR7LH (RSCAN0.RMPTR7.UINT8[R_IO_LH]) +#define RSCAN0RMPTR7H (RSCAN0.RMPTR7.UINT16[R_IO_H]) +#define RSCAN0RMPTR7HL (RSCAN0.RMPTR7.UINT8[R_IO_HL]) +#define RSCAN0RMPTR7HH (RSCAN0.RMPTR7.UINT8[R_IO_HH]) +#define RSCAN0RMDF07 (RSCAN0.RMDF07.UINT32) +#define RSCAN0RMDF07L (RSCAN0.RMDF07.UINT16[R_IO_L]) +#define RSCAN0RMDF07LL (RSCAN0.RMDF07.UINT8[R_IO_LL]) +#define RSCAN0RMDF07LH (RSCAN0.RMDF07.UINT8[R_IO_LH]) +#define RSCAN0RMDF07H (RSCAN0.RMDF07.UINT16[R_IO_H]) +#define RSCAN0RMDF07HL (RSCAN0.RMDF07.UINT8[R_IO_HL]) +#define RSCAN0RMDF07HH (RSCAN0.RMDF07.UINT8[R_IO_HH]) +#define RSCAN0RMDF17 (RSCAN0.RMDF17.UINT32) +#define RSCAN0RMDF17L (RSCAN0.RMDF17.UINT16[R_IO_L]) +#define RSCAN0RMDF17LL (RSCAN0.RMDF17.UINT8[R_IO_LL]) +#define RSCAN0RMDF17LH (RSCAN0.RMDF17.UINT8[R_IO_LH]) +#define RSCAN0RMDF17H (RSCAN0.RMDF17.UINT16[R_IO_H]) +#define RSCAN0RMDF17HL (RSCAN0.RMDF17.UINT8[R_IO_HL]) +#define RSCAN0RMDF17HH (RSCAN0.RMDF17.UINT8[R_IO_HH]) +#define RSCAN0RMID8 (RSCAN0.RMID8.UINT32) +#define RSCAN0RMID8L (RSCAN0.RMID8.UINT16[R_IO_L]) +#define RSCAN0RMID8LL (RSCAN0.RMID8.UINT8[R_IO_LL]) +#define RSCAN0RMID8LH (RSCAN0.RMID8.UINT8[R_IO_LH]) +#define RSCAN0RMID8H (RSCAN0.RMID8.UINT16[R_IO_H]) +#define RSCAN0RMID8HL (RSCAN0.RMID8.UINT8[R_IO_HL]) +#define RSCAN0RMID8HH (RSCAN0.RMID8.UINT8[R_IO_HH]) +#define RSCAN0RMPTR8 (RSCAN0.RMPTR8.UINT32) +#define RSCAN0RMPTR8L (RSCAN0.RMPTR8.UINT16[R_IO_L]) +#define RSCAN0RMPTR8LL (RSCAN0.RMPTR8.UINT8[R_IO_LL]) +#define RSCAN0RMPTR8LH (RSCAN0.RMPTR8.UINT8[R_IO_LH]) +#define RSCAN0RMPTR8H (RSCAN0.RMPTR8.UINT16[R_IO_H]) +#define RSCAN0RMPTR8HL (RSCAN0.RMPTR8.UINT8[R_IO_HL]) +#define RSCAN0RMPTR8HH (RSCAN0.RMPTR8.UINT8[R_IO_HH]) +#define RSCAN0RMDF08 (RSCAN0.RMDF08.UINT32) +#define RSCAN0RMDF08L (RSCAN0.RMDF08.UINT16[R_IO_L]) +#define RSCAN0RMDF08LL (RSCAN0.RMDF08.UINT8[R_IO_LL]) +#define RSCAN0RMDF08LH (RSCAN0.RMDF08.UINT8[R_IO_LH]) +#define RSCAN0RMDF08H (RSCAN0.RMDF08.UINT16[R_IO_H]) +#define RSCAN0RMDF08HL (RSCAN0.RMDF08.UINT8[R_IO_HL]) +#define RSCAN0RMDF08HH (RSCAN0.RMDF08.UINT8[R_IO_HH]) +#define RSCAN0RMDF18 (RSCAN0.RMDF18.UINT32) +#define RSCAN0RMDF18L (RSCAN0.RMDF18.UINT16[R_IO_L]) +#define RSCAN0RMDF18LL (RSCAN0.RMDF18.UINT8[R_IO_LL]) +#define RSCAN0RMDF18LH (RSCAN0.RMDF18.UINT8[R_IO_LH]) +#define RSCAN0RMDF18H (RSCAN0.RMDF18.UINT16[R_IO_H]) +#define RSCAN0RMDF18HL (RSCAN0.RMDF18.UINT8[R_IO_HL]) +#define RSCAN0RMDF18HH (RSCAN0.RMDF18.UINT8[R_IO_HH]) +#define RSCAN0RMID9 (RSCAN0.RMID9.UINT32) +#define RSCAN0RMID9L (RSCAN0.RMID9.UINT16[R_IO_L]) +#define RSCAN0RMID9LL (RSCAN0.RMID9.UINT8[R_IO_LL]) +#define RSCAN0RMID9LH (RSCAN0.RMID9.UINT8[R_IO_LH]) +#define RSCAN0RMID9H (RSCAN0.RMID9.UINT16[R_IO_H]) +#define RSCAN0RMID9HL (RSCAN0.RMID9.UINT8[R_IO_HL]) +#define RSCAN0RMID9HH (RSCAN0.RMID9.UINT8[R_IO_HH]) +#define RSCAN0RMPTR9 (RSCAN0.RMPTR9.UINT32) +#define RSCAN0RMPTR9L (RSCAN0.RMPTR9.UINT16[R_IO_L]) +#define RSCAN0RMPTR9LL (RSCAN0.RMPTR9.UINT8[R_IO_LL]) +#define RSCAN0RMPTR9LH (RSCAN0.RMPTR9.UINT8[R_IO_LH]) +#define RSCAN0RMPTR9H (RSCAN0.RMPTR9.UINT16[R_IO_H]) +#define RSCAN0RMPTR9HL (RSCAN0.RMPTR9.UINT8[R_IO_HL]) +#define RSCAN0RMPTR9HH (RSCAN0.RMPTR9.UINT8[R_IO_HH]) +#define RSCAN0RMDF09 (RSCAN0.RMDF09.UINT32) +#define RSCAN0RMDF09L (RSCAN0.RMDF09.UINT16[R_IO_L]) +#define RSCAN0RMDF09LL (RSCAN0.RMDF09.UINT8[R_IO_LL]) +#define RSCAN0RMDF09LH (RSCAN0.RMDF09.UINT8[R_IO_LH]) +#define RSCAN0RMDF09H (RSCAN0.RMDF09.UINT16[R_IO_H]) +#define RSCAN0RMDF09HL (RSCAN0.RMDF09.UINT8[R_IO_HL]) +#define RSCAN0RMDF09HH (RSCAN0.RMDF09.UINT8[R_IO_HH]) +#define RSCAN0RMDF19 (RSCAN0.RMDF19.UINT32) +#define RSCAN0RMDF19L (RSCAN0.RMDF19.UINT16[R_IO_L]) +#define RSCAN0RMDF19LL (RSCAN0.RMDF19.UINT8[R_IO_LL]) +#define RSCAN0RMDF19LH (RSCAN0.RMDF19.UINT8[R_IO_LH]) +#define RSCAN0RMDF19H (RSCAN0.RMDF19.UINT16[R_IO_H]) +#define RSCAN0RMDF19HL (RSCAN0.RMDF19.UINT8[R_IO_HL]) +#define RSCAN0RMDF19HH (RSCAN0.RMDF19.UINT8[R_IO_HH]) +#define RSCAN0RMID10 (RSCAN0.RMID10.UINT32) +#define RSCAN0RMID10L (RSCAN0.RMID10.UINT16[R_IO_L]) +#define RSCAN0RMID10LL (RSCAN0.RMID10.UINT8[R_IO_LL]) +#define RSCAN0RMID10LH (RSCAN0.RMID10.UINT8[R_IO_LH]) +#define RSCAN0RMID10H (RSCAN0.RMID10.UINT16[R_IO_H]) +#define RSCAN0RMID10HL (RSCAN0.RMID10.UINT8[R_IO_HL]) +#define RSCAN0RMID10HH (RSCAN0.RMID10.UINT8[R_IO_HH]) +#define RSCAN0RMPTR10 (RSCAN0.RMPTR10.UINT32) +#define RSCAN0RMPTR10L (RSCAN0.RMPTR10.UINT16[R_IO_L]) +#define RSCAN0RMPTR10LL (RSCAN0.RMPTR10.UINT8[R_IO_LL]) +#define RSCAN0RMPTR10LH (RSCAN0.RMPTR10.UINT8[R_IO_LH]) +#define RSCAN0RMPTR10H (RSCAN0.RMPTR10.UINT16[R_IO_H]) +#define RSCAN0RMPTR10HL (RSCAN0.RMPTR10.UINT8[R_IO_HL]) +#define RSCAN0RMPTR10HH (RSCAN0.RMPTR10.UINT8[R_IO_HH]) +#define RSCAN0RMDF010 (RSCAN0.RMDF010.UINT32) +#define RSCAN0RMDF010L (RSCAN0.RMDF010.UINT16[R_IO_L]) +#define RSCAN0RMDF010LL (RSCAN0.RMDF010.UINT8[R_IO_LL]) +#define RSCAN0RMDF010LH (RSCAN0.RMDF010.UINT8[R_IO_LH]) +#define RSCAN0RMDF010H (RSCAN0.RMDF010.UINT16[R_IO_H]) +#define RSCAN0RMDF010HL (RSCAN0.RMDF010.UINT8[R_IO_HL]) +#define RSCAN0RMDF010HH (RSCAN0.RMDF010.UINT8[R_IO_HH]) +#define RSCAN0RMDF110 (RSCAN0.RMDF110.UINT32) +#define RSCAN0RMDF110L (RSCAN0.RMDF110.UINT16[R_IO_L]) +#define RSCAN0RMDF110LL (RSCAN0.RMDF110.UINT8[R_IO_LL]) +#define RSCAN0RMDF110LH (RSCAN0.RMDF110.UINT8[R_IO_LH]) +#define RSCAN0RMDF110H (RSCAN0.RMDF110.UINT16[R_IO_H]) +#define RSCAN0RMDF110HL (RSCAN0.RMDF110.UINT8[R_IO_HL]) +#define RSCAN0RMDF110HH (RSCAN0.RMDF110.UINT8[R_IO_HH]) +#define RSCAN0RMID11 (RSCAN0.RMID11.UINT32) +#define RSCAN0RMID11L (RSCAN0.RMID11.UINT16[R_IO_L]) +#define RSCAN0RMID11LL (RSCAN0.RMID11.UINT8[R_IO_LL]) +#define RSCAN0RMID11LH (RSCAN0.RMID11.UINT8[R_IO_LH]) +#define RSCAN0RMID11H (RSCAN0.RMID11.UINT16[R_IO_H]) +#define RSCAN0RMID11HL (RSCAN0.RMID11.UINT8[R_IO_HL]) +#define RSCAN0RMID11HH (RSCAN0.RMID11.UINT8[R_IO_HH]) +#define RSCAN0RMPTR11 (RSCAN0.RMPTR11.UINT32) +#define RSCAN0RMPTR11L (RSCAN0.RMPTR11.UINT16[R_IO_L]) +#define RSCAN0RMPTR11LL (RSCAN0.RMPTR11.UINT8[R_IO_LL]) +#define RSCAN0RMPTR11LH (RSCAN0.RMPTR11.UINT8[R_IO_LH]) +#define RSCAN0RMPTR11H (RSCAN0.RMPTR11.UINT16[R_IO_H]) +#define RSCAN0RMPTR11HL (RSCAN0.RMPTR11.UINT8[R_IO_HL]) +#define RSCAN0RMPTR11HH (RSCAN0.RMPTR11.UINT8[R_IO_HH]) +#define RSCAN0RMDF011 (RSCAN0.RMDF011.UINT32) +#define RSCAN0RMDF011L (RSCAN0.RMDF011.UINT16[R_IO_L]) +#define RSCAN0RMDF011LL (RSCAN0.RMDF011.UINT8[R_IO_LL]) +#define RSCAN0RMDF011LH (RSCAN0.RMDF011.UINT8[R_IO_LH]) +#define RSCAN0RMDF011H (RSCAN0.RMDF011.UINT16[R_IO_H]) +#define RSCAN0RMDF011HL (RSCAN0.RMDF011.UINT8[R_IO_HL]) +#define RSCAN0RMDF011HH (RSCAN0.RMDF011.UINT8[R_IO_HH]) +#define RSCAN0RMDF111 (RSCAN0.RMDF111.UINT32) +#define RSCAN0RMDF111L (RSCAN0.RMDF111.UINT16[R_IO_L]) +#define RSCAN0RMDF111LL (RSCAN0.RMDF111.UINT8[R_IO_LL]) +#define RSCAN0RMDF111LH (RSCAN0.RMDF111.UINT8[R_IO_LH]) +#define RSCAN0RMDF111H (RSCAN0.RMDF111.UINT16[R_IO_H]) +#define RSCAN0RMDF111HL (RSCAN0.RMDF111.UINT8[R_IO_HL]) +#define RSCAN0RMDF111HH (RSCAN0.RMDF111.UINT8[R_IO_HH]) +#define RSCAN0RMID12 (RSCAN0.RMID12.UINT32) +#define RSCAN0RMID12L (RSCAN0.RMID12.UINT16[R_IO_L]) +#define RSCAN0RMID12LL (RSCAN0.RMID12.UINT8[R_IO_LL]) +#define RSCAN0RMID12LH (RSCAN0.RMID12.UINT8[R_IO_LH]) +#define RSCAN0RMID12H (RSCAN0.RMID12.UINT16[R_IO_H]) +#define RSCAN0RMID12HL (RSCAN0.RMID12.UINT8[R_IO_HL]) +#define RSCAN0RMID12HH (RSCAN0.RMID12.UINT8[R_IO_HH]) +#define RSCAN0RMPTR12 (RSCAN0.RMPTR12.UINT32) +#define RSCAN0RMPTR12L (RSCAN0.RMPTR12.UINT16[R_IO_L]) +#define RSCAN0RMPTR12LL (RSCAN0.RMPTR12.UINT8[R_IO_LL]) +#define RSCAN0RMPTR12LH (RSCAN0.RMPTR12.UINT8[R_IO_LH]) +#define RSCAN0RMPTR12H (RSCAN0.RMPTR12.UINT16[R_IO_H]) +#define RSCAN0RMPTR12HL (RSCAN0.RMPTR12.UINT8[R_IO_HL]) +#define RSCAN0RMPTR12HH (RSCAN0.RMPTR12.UINT8[R_IO_HH]) +#define RSCAN0RMDF012 (RSCAN0.RMDF012.UINT32) +#define RSCAN0RMDF012L (RSCAN0.RMDF012.UINT16[R_IO_L]) +#define RSCAN0RMDF012LL (RSCAN0.RMDF012.UINT8[R_IO_LL]) +#define RSCAN0RMDF012LH (RSCAN0.RMDF012.UINT8[R_IO_LH]) +#define RSCAN0RMDF012H (RSCAN0.RMDF012.UINT16[R_IO_H]) +#define RSCAN0RMDF012HL (RSCAN0.RMDF012.UINT8[R_IO_HL]) +#define RSCAN0RMDF012HH (RSCAN0.RMDF012.UINT8[R_IO_HH]) +#define RSCAN0RMDF112 (RSCAN0.RMDF112.UINT32) +#define RSCAN0RMDF112L (RSCAN0.RMDF112.UINT16[R_IO_L]) +#define RSCAN0RMDF112LL (RSCAN0.RMDF112.UINT8[R_IO_LL]) +#define RSCAN0RMDF112LH (RSCAN0.RMDF112.UINT8[R_IO_LH]) +#define RSCAN0RMDF112H (RSCAN0.RMDF112.UINT16[R_IO_H]) +#define RSCAN0RMDF112HL (RSCAN0.RMDF112.UINT8[R_IO_HL]) +#define RSCAN0RMDF112HH (RSCAN0.RMDF112.UINT8[R_IO_HH]) +#define RSCAN0RMID13 (RSCAN0.RMID13.UINT32) +#define RSCAN0RMID13L (RSCAN0.RMID13.UINT16[R_IO_L]) +#define RSCAN0RMID13LL (RSCAN0.RMID13.UINT8[R_IO_LL]) +#define RSCAN0RMID13LH (RSCAN0.RMID13.UINT8[R_IO_LH]) +#define RSCAN0RMID13H (RSCAN0.RMID13.UINT16[R_IO_H]) +#define RSCAN0RMID13HL (RSCAN0.RMID13.UINT8[R_IO_HL]) +#define RSCAN0RMID13HH (RSCAN0.RMID13.UINT8[R_IO_HH]) +#define RSCAN0RMPTR13 (RSCAN0.RMPTR13.UINT32) +#define RSCAN0RMPTR13L (RSCAN0.RMPTR13.UINT16[R_IO_L]) +#define RSCAN0RMPTR13LL (RSCAN0.RMPTR13.UINT8[R_IO_LL]) +#define RSCAN0RMPTR13LH (RSCAN0.RMPTR13.UINT8[R_IO_LH]) +#define RSCAN0RMPTR13H (RSCAN0.RMPTR13.UINT16[R_IO_H]) +#define RSCAN0RMPTR13HL (RSCAN0.RMPTR13.UINT8[R_IO_HL]) +#define RSCAN0RMPTR13HH (RSCAN0.RMPTR13.UINT8[R_IO_HH]) +#define RSCAN0RMDF013 (RSCAN0.RMDF013.UINT32) +#define RSCAN0RMDF013L (RSCAN0.RMDF013.UINT16[R_IO_L]) +#define RSCAN0RMDF013LL (RSCAN0.RMDF013.UINT8[R_IO_LL]) +#define RSCAN0RMDF013LH (RSCAN0.RMDF013.UINT8[R_IO_LH]) +#define RSCAN0RMDF013H (RSCAN0.RMDF013.UINT16[R_IO_H]) +#define RSCAN0RMDF013HL (RSCAN0.RMDF013.UINT8[R_IO_HL]) +#define RSCAN0RMDF013HH (RSCAN0.RMDF013.UINT8[R_IO_HH]) +#define RSCAN0RMDF113 (RSCAN0.RMDF113.UINT32) +#define RSCAN0RMDF113L (RSCAN0.RMDF113.UINT16[R_IO_L]) +#define RSCAN0RMDF113LL (RSCAN0.RMDF113.UINT8[R_IO_LL]) +#define RSCAN0RMDF113LH (RSCAN0.RMDF113.UINT8[R_IO_LH]) +#define RSCAN0RMDF113H (RSCAN0.RMDF113.UINT16[R_IO_H]) +#define RSCAN0RMDF113HL (RSCAN0.RMDF113.UINT8[R_IO_HL]) +#define RSCAN0RMDF113HH (RSCAN0.RMDF113.UINT8[R_IO_HH]) +#define RSCAN0RMID14 (RSCAN0.RMID14.UINT32) +#define RSCAN0RMID14L (RSCAN0.RMID14.UINT16[R_IO_L]) +#define RSCAN0RMID14LL (RSCAN0.RMID14.UINT8[R_IO_LL]) +#define RSCAN0RMID14LH (RSCAN0.RMID14.UINT8[R_IO_LH]) +#define RSCAN0RMID14H (RSCAN0.RMID14.UINT16[R_IO_H]) +#define RSCAN0RMID14HL (RSCAN0.RMID14.UINT8[R_IO_HL]) +#define RSCAN0RMID14HH (RSCAN0.RMID14.UINT8[R_IO_HH]) +#define RSCAN0RMPTR14 (RSCAN0.RMPTR14.UINT32) +#define RSCAN0RMPTR14L (RSCAN0.RMPTR14.UINT16[R_IO_L]) +#define RSCAN0RMPTR14LL (RSCAN0.RMPTR14.UINT8[R_IO_LL]) +#define RSCAN0RMPTR14LH (RSCAN0.RMPTR14.UINT8[R_IO_LH]) +#define RSCAN0RMPTR14H (RSCAN0.RMPTR14.UINT16[R_IO_H]) +#define RSCAN0RMPTR14HL (RSCAN0.RMPTR14.UINT8[R_IO_HL]) +#define RSCAN0RMPTR14HH (RSCAN0.RMPTR14.UINT8[R_IO_HH]) +#define RSCAN0RMDF014 (RSCAN0.RMDF014.UINT32) +#define RSCAN0RMDF014L (RSCAN0.RMDF014.UINT16[R_IO_L]) +#define RSCAN0RMDF014LL (RSCAN0.RMDF014.UINT8[R_IO_LL]) +#define RSCAN0RMDF014LH (RSCAN0.RMDF014.UINT8[R_IO_LH]) +#define RSCAN0RMDF014H (RSCAN0.RMDF014.UINT16[R_IO_H]) +#define RSCAN0RMDF014HL (RSCAN0.RMDF014.UINT8[R_IO_HL]) +#define RSCAN0RMDF014HH (RSCAN0.RMDF014.UINT8[R_IO_HH]) +#define RSCAN0RMDF114 (RSCAN0.RMDF114.UINT32) +#define RSCAN0RMDF114L (RSCAN0.RMDF114.UINT16[R_IO_L]) +#define RSCAN0RMDF114LL (RSCAN0.RMDF114.UINT8[R_IO_LL]) +#define RSCAN0RMDF114LH (RSCAN0.RMDF114.UINT8[R_IO_LH]) +#define RSCAN0RMDF114H (RSCAN0.RMDF114.UINT16[R_IO_H]) +#define RSCAN0RMDF114HL (RSCAN0.RMDF114.UINT8[R_IO_HL]) +#define RSCAN0RMDF114HH (RSCAN0.RMDF114.UINT8[R_IO_HH]) +#define RSCAN0RMID15 (RSCAN0.RMID15.UINT32) +#define RSCAN0RMID15L (RSCAN0.RMID15.UINT16[R_IO_L]) +#define RSCAN0RMID15LL (RSCAN0.RMID15.UINT8[R_IO_LL]) +#define RSCAN0RMID15LH (RSCAN0.RMID15.UINT8[R_IO_LH]) +#define RSCAN0RMID15H (RSCAN0.RMID15.UINT16[R_IO_H]) +#define RSCAN0RMID15HL (RSCAN0.RMID15.UINT8[R_IO_HL]) +#define RSCAN0RMID15HH (RSCAN0.RMID15.UINT8[R_IO_HH]) +#define RSCAN0RMPTR15 (RSCAN0.RMPTR15.UINT32) +#define RSCAN0RMPTR15L (RSCAN0.RMPTR15.UINT16[R_IO_L]) +#define RSCAN0RMPTR15LL (RSCAN0.RMPTR15.UINT8[R_IO_LL]) +#define RSCAN0RMPTR15LH (RSCAN0.RMPTR15.UINT8[R_IO_LH]) +#define RSCAN0RMPTR15H (RSCAN0.RMPTR15.UINT16[R_IO_H]) +#define RSCAN0RMPTR15HL (RSCAN0.RMPTR15.UINT8[R_IO_HL]) +#define RSCAN0RMPTR15HH (RSCAN0.RMPTR15.UINT8[R_IO_HH]) +#define RSCAN0RMDF015 (RSCAN0.RMDF015.UINT32) +#define RSCAN0RMDF015L (RSCAN0.RMDF015.UINT16[R_IO_L]) +#define RSCAN0RMDF015LL (RSCAN0.RMDF015.UINT8[R_IO_LL]) +#define RSCAN0RMDF015LH (RSCAN0.RMDF015.UINT8[R_IO_LH]) +#define RSCAN0RMDF015H (RSCAN0.RMDF015.UINT16[R_IO_H]) +#define RSCAN0RMDF015HL (RSCAN0.RMDF015.UINT8[R_IO_HL]) +#define RSCAN0RMDF015HH (RSCAN0.RMDF015.UINT8[R_IO_HH]) +#define RSCAN0RMDF115 (RSCAN0.RMDF115.UINT32) +#define RSCAN0RMDF115L (RSCAN0.RMDF115.UINT16[R_IO_L]) +#define RSCAN0RMDF115LL (RSCAN0.RMDF115.UINT8[R_IO_LL]) +#define RSCAN0RMDF115LH (RSCAN0.RMDF115.UINT8[R_IO_LH]) +#define RSCAN0RMDF115H (RSCAN0.RMDF115.UINT16[R_IO_H]) +#define RSCAN0RMDF115HL (RSCAN0.RMDF115.UINT8[R_IO_HL]) +#define RSCAN0RMDF115HH (RSCAN0.RMDF115.UINT8[R_IO_HH]) +#define RSCAN0RMID16 (RSCAN0.RMID16.UINT32) +#define RSCAN0RMID16L (RSCAN0.RMID16.UINT16[R_IO_L]) +#define RSCAN0RMID16LL (RSCAN0.RMID16.UINT8[R_IO_LL]) +#define RSCAN0RMID16LH (RSCAN0.RMID16.UINT8[R_IO_LH]) +#define RSCAN0RMID16H (RSCAN0.RMID16.UINT16[R_IO_H]) +#define RSCAN0RMID16HL (RSCAN0.RMID16.UINT8[R_IO_HL]) +#define RSCAN0RMID16HH (RSCAN0.RMID16.UINT8[R_IO_HH]) +#define RSCAN0RMPTR16 (RSCAN0.RMPTR16.UINT32) +#define RSCAN0RMPTR16L (RSCAN0.RMPTR16.UINT16[R_IO_L]) +#define RSCAN0RMPTR16LL (RSCAN0.RMPTR16.UINT8[R_IO_LL]) +#define RSCAN0RMPTR16LH (RSCAN0.RMPTR16.UINT8[R_IO_LH]) +#define RSCAN0RMPTR16H (RSCAN0.RMPTR16.UINT16[R_IO_H]) +#define RSCAN0RMPTR16HL (RSCAN0.RMPTR16.UINT8[R_IO_HL]) +#define RSCAN0RMPTR16HH (RSCAN0.RMPTR16.UINT8[R_IO_HH]) +#define RSCAN0RMDF016 (RSCAN0.RMDF016.UINT32) +#define RSCAN0RMDF016L (RSCAN0.RMDF016.UINT16[R_IO_L]) +#define RSCAN0RMDF016LL (RSCAN0.RMDF016.UINT8[R_IO_LL]) +#define RSCAN0RMDF016LH (RSCAN0.RMDF016.UINT8[R_IO_LH]) +#define RSCAN0RMDF016H (RSCAN0.RMDF016.UINT16[R_IO_H]) +#define RSCAN0RMDF016HL (RSCAN0.RMDF016.UINT8[R_IO_HL]) +#define RSCAN0RMDF016HH (RSCAN0.RMDF016.UINT8[R_IO_HH]) +#define RSCAN0RMDF116 (RSCAN0.RMDF116.UINT32) +#define RSCAN0RMDF116L (RSCAN0.RMDF116.UINT16[R_IO_L]) +#define RSCAN0RMDF116LL (RSCAN0.RMDF116.UINT8[R_IO_LL]) +#define RSCAN0RMDF116LH (RSCAN0.RMDF116.UINT8[R_IO_LH]) +#define RSCAN0RMDF116H (RSCAN0.RMDF116.UINT16[R_IO_H]) +#define RSCAN0RMDF116HL (RSCAN0.RMDF116.UINT8[R_IO_HL]) +#define RSCAN0RMDF116HH (RSCAN0.RMDF116.UINT8[R_IO_HH]) +#define RSCAN0RMID17 (RSCAN0.RMID17.UINT32) +#define RSCAN0RMID17L (RSCAN0.RMID17.UINT16[R_IO_L]) +#define RSCAN0RMID17LL (RSCAN0.RMID17.UINT8[R_IO_LL]) +#define RSCAN0RMID17LH (RSCAN0.RMID17.UINT8[R_IO_LH]) +#define RSCAN0RMID17H (RSCAN0.RMID17.UINT16[R_IO_H]) +#define RSCAN0RMID17HL (RSCAN0.RMID17.UINT8[R_IO_HL]) +#define RSCAN0RMID17HH (RSCAN0.RMID17.UINT8[R_IO_HH]) +#define RSCAN0RMPTR17 (RSCAN0.RMPTR17.UINT32) +#define RSCAN0RMPTR17L (RSCAN0.RMPTR17.UINT16[R_IO_L]) +#define RSCAN0RMPTR17LL (RSCAN0.RMPTR17.UINT8[R_IO_LL]) +#define RSCAN0RMPTR17LH (RSCAN0.RMPTR17.UINT8[R_IO_LH]) +#define RSCAN0RMPTR17H (RSCAN0.RMPTR17.UINT16[R_IO_H]) +#define RSCAN0RMPTR17HL (RSCAN0.RMPTR17.UINT8[R_IO_HL]) +#define RSCAN0RMPTR17HH (RSCAN0.RMPTR17.UINT8[R_IO_HH]) +#define RSCAN0RMDF017 (RSCAN0.RMDF017.UINT32) +#define RSCAN0RMDF017L (RSCAN0.RMDF017.UINT16[R_IO_L]) +#define RSCAN0RMDF017LL (RSCAN0.RMDF017.UINT8[R_IO_LL]) +#define RSCAN0RMDF017LH (RSCAN0.RMDF017.UINT8[R_IO_LH]) +#define RSCAN0RMDF017H (RSCAN0.RMDF017.UINT16[R_IO_H]) +#define RSCAN0RMDF017HL (RSCAN0.RMDF017.UINT8[R_IO_HL]) +#define RSCAN0RMDF017HH (RSCAN0.RMDF017.UINT8[R_IO_HH]) +#define RSCAN0RMDF117 (RSCAN0.RMDF117.UINT32) +#define RSCAN0RMDF117L (RSCAN0.RMDF117.UINT16[R_IO_L]) +#define RSCAN0RMDF117LL (RSCAN0.RMDF117.UINT8[R_IO_LL]) +#define RSCAN0RMDF117LH (RSCAN0.RMDF117.UINT8[R_IO_LH]) +#define RSCAN0RMDF117H (RSCAN0.RMDF117.UINT16[R_IO_H]) +#define RSCAN0RMDF117HL (RSCAN0.RMDF117.UINT8[R_IO_HL]) +#define RSCAN0RMDF117HH (RSCAN0.RMDF117.UINT8[R_IO_HH]) +#define RSCAN0RMID18 (RSCAN0.RMID18.UINT32) +#define RSCAN0RMID18L (RSCAN0.RMID18.UINT16[R_IO_L]) +#define RSCAN0RMID18LL (RSCAN0.RMID18.UINT8[R_IO_LL]) +#define RSCAN0RMID18LH (RSCAN0.RMID18.UINT8[R_IO_LH]) +#define RSCAN0RMID18H (RSCAN0.RMID18.UINT16[R_IO_H]) +#define RSCAN0RMID18HL (RSCAN0.RMID18.UINT8[R_IO_HL]) +#define RSCAN0RMID18HH (RSCAN0.RMID18.UINT8[R_IO_HH]) +#define RSCAN0RMPTR18 (RSCAN0.RMPTR18.UINT32) +#define RSCAN0RMPTR18L (RSCAN0.RMPTR18.UINT16[R_IO_L]) +#define RSCAN0RMPTR18LL (RSCAN0.RMPTR18.UINT8[R_IO_LL]) +#define RSCAN0RMPTR18LH (RSCAN0.RMPTR18.UINT8[R_IO_LH]) +#define RSCAN0RMPTR18H (RSCAN0.RMPTR18.UINT16[R_IO_H]) +#define RSCAN0RMPTR18HL (RSCAN0.RMPTR18.UINT8[R_IO_HL]) +#define RSCAN0RMPTR18HH (RSCAN0.RMPTR18.UINT8[R_IO_HH]) +#define RSCAN0RMDF018 (RSCAN0.RMDF018.UINT32) +#define RSCAN0RMDF018L (RSCAN0.RMDF018.UINT16[R_IO_L]) +#define RSCAN0RMDF018LL (RSCAN0.RMDF018.UINT8[R_IO_LL]) +#define RSCAN0RMDF018LH (RSCAN0.RMDF018.UINT8[R_IO_LH]) +#define RSCAN0RMDF018H (RSCAN0.RMDF018.UINT16[R_IO_H]) +#define RSCAN0RMDF018HL (RSCAN0.RMDF018.UINT8[R_IO_HL]) +#define RSCAN0RMDF018HH (RSCAN0.RMDF018.UINT8[R_IO_HH]) +#define RSCAN0RMDF118 (RSCAN0.RMDF118.UINT32) +#define RSCAN0RMDF118L (RSCAN0.RMDF118.UINT16[R_IO_L]) +#define RSCAN0RMDF118LL (RSCAN0.RMDF118.UINT8[R_IO_LL]) +#define RSCAN0RMDF118LH (RSCAN0.RMDF118.UINT8[R_IO_LH]) +#define RSCAN0RMDF118H (RSCAN0.RMDF118.UINT16[R_IO_H]) +#define RSCAN0RMDF118HL (RSCAN0.RMDF118.UINT8[R_IO_HL]) +#define RSCAN0RMDF118HH (RSCAN0.RMDF118.UINT8[R_IO_HH]) +#define RSCAN0RMID19 (RSCAN0.RMID19.UINT32) +#define RSCAN0RMID19L (RSCAN0.RMID19.UINT16[R_IO_L]) +#define RSCAN0RMID19LL (RSCAN0.RMID19.UINT8[R_IO_LL]) +#define RSCAN0RMID19LH (RSCAN0.RMID19.UINT8[R_IO_LH]) +#define RSCAN0RMID19H (RSCAN0.RMID19.UINT16[R_IO_H]) +#define RSCAN0RMID19HL (RSCAN0.RMID19.UINT8[R_IO_HL]) +#define RSCAN0RMID19HH (RSCAN0.RMID19.UINT8[R_IO_HH]) +#define RSCAN0RMPTR19 (RSCAN0.RMPTR19.UINT32) +#define RSCAN0RMPTR19L (RSCAN0.RMPTR19.UINT16[R_IO_L]) +#define RSCAN0RMPTR19LL (RSCAN0.RMPTR19.UINT8[R_IO_LL]) +#define RSCAN0RMPTR19LH (RSCAN0.RMPTR19.UINT8[R_IO_LH]) +#define RSCAN0RMPTR19H (RSCAN0.RMPTR19.UINT16[R_IO_H]) +#define RSCAN0RMPTR19HL (RSCAN0.RMPTR19.UINT8[R_IO_HL]) +#define RSCAN0RMPTR19HH (RSCAN0.RMPTR19.UINT8[R_IO_HH]) +#define RSCAN0RMDF019 (RSCAN0.RMDF019.UINT32) +#define RSCAN0RMDF019L (RSCAN0.RMDF019.UINT16[R_IO_L]) +#define RSCAN0RMDF019LL (RSCAN0.RMDF019.UINT8[R_IO_LL]) +#define RSCAN0RMDF019LH (RSCAN0.RMDF019.UINT8[R_IO_LH]) +#define RSCAN0RMDF019H (RSCAN0.RMDF019.UINT16[R_IO_H]) +#define RSCAN0RMDF019HL (RSCAN0.RMDF019.UINT8[R_IO_HL]) +#define RSCAN0RMDF019HH (RSCAN0.RMDF019.UINT8[R_IO_HH]) +#define RSCAN0RMDF119 (RSCAN0.RMDF119.UINT32) +#define RSCAN0RMDF119L (RSCAN0.RMDF119.UINT16[R_IO_L]) +#define RSCAN0RMDF119LL (RSCAN0.RMDF119.UINT8[R_IO_LL]) +#define RSCAN0RMDF119LH (RSCAN0.RMDF119.UINT8[R_IO_LH]) +#define RSCAN0RMDF119H (RSCAN0.RMDF119.UINT16[R_IO_H]) +#define RSCAN0RMDF119HL (RSCAN0.RMDF119.UINT8[R_IO_HL]) +#define RSCAN0RMDF119HH (RSCAN0.RMDF119.UINT8[R_IO_HH]) +#define RSCAN0RMID20 (RSCAN0.RMID20.UINT32) +#define RSCAN0RMID20L (RSCAN0.RMID20.UINT16[R_IO_L]) +#define RSCAN0RMID20LL (RSCAN0.RMID20.UINT8[R_IO_LL]) +#define RSCAN0RMID20LH (RSCAN0.RMID20.UINT8[R_IO_LH]) +#define RSCAN0RMID20H (RSCAN0.RMID20.UINT16[R_IO_H]) +#define RSCAN0RMID20HL (RSCAN0.RMID20.UINT8[R_IO_HL]) +#define RSCAN0RMID20HH (RSCAN0.RMID20.UINT8[R_IO_HH]) +#define RSCAN0RMPTR20 (RSCAN0.RMPTR20.UINT32) +#define RSCAN0RMPTR20L (RSCAN0.RMPTR20.UINT16[R_IO_L]) +#define RSCAN0RMPTR20LL (RSCAN0.RMPTR20.UINT8[R_IO_LL]) +#define RSCAN0RMPTR20LH (RSCAN0.RMPTR20.UINT8[R_IO_LH]) +#define RSCAN0RMPTR20H (RSCAN0.RMPTR20.UINT16[R_IO_H]) +#define RSCAN0RMPTR20HL (RSCAN0.RMPTR20.UINT8[R_IO_HL]) +#define RSCAN0RMPTR20HH (RSCAN0.RMPTR20.UINT8[R_IO_HH]) +#define RSCAN0RMDF020 (RSCAN0.RMDF020.UINT32) +#define RSCAN0RMDF020L (RSCAN0.RMDF020.UINT16[R_IO_L]) +#define RSCAN0RMDF020LL (RSCAN0.RMDF020.UINT8[R_IO_LL]) +#define RSCAN0RMDF020LH (RSCAN0.RMDF020.UINT8[R_IO_LH]) +#define RSCAN0RMDF020H (RSCAN0.RMDF020.UINT16[R_IO_H]) +#define RSCAN0RMDF020HL (RSCAN0.RMDF020.UINT8[R_IO_HL]) +#define RSCAN0RMDF020HH (RSCAN0.RMDF020.UINT8[R_IO_HH]) +#define RSCAN0RMDF120 (RSCAN0.RMDF120.UINT32) +#define RSCAN0RMDF120L (RSCAN0.RMDF120.UINT16[R_IO_L]) +#define RSCAN0RMDF120LL (RSCAN0.RMDF120.UINT8[R_IO_LL]) +#define RSCAN0RMDF120LH (RSCAN0.RMDF120.UINT8[R_IO_LH]) +#define RSCAN0RMDF120H (RSCAN0.RMDF120.UINT16[R_IO_H]) +#define RSCAN0RMDF120HL (RSCAN0.RMDF120.UINT8[R_IO_HL]) +#define RSCAN0RMDF120HH (RSCAN0.RMDF120.UINT8[R_IO_HH]) +#define RSCAN0RMID21 (RSCAN0.RMID21.UINT32) +#define RSCAN0RMID21L (RSCAN0.RMID21.UINT16[R_IO_L]) +#define RSCAN0RMID21LL (RSCAN0.RMID21.UINT8[R_IO_LL]) +#define RSCAN0RMID21LH (RSCAN0.RMID21.UINT8[R_IO_LH]) +#define RSCAN0RMID21H (RSCAN0.RMID21.UINT16[R_IO_H]) +#define RSCAN0RMID21HL (RSCAN0.RMID21.UINT8[R_IO_HL]) +#define RSCAN0RMID21HH (RSCAN0.RMID21.UINT8[R_IO_HH]) +#define RSCAN0RMPTR21 (RSCAN0.RMPTR21.UINT32) +#define RSCAN0RMPTR21L (RSCAN0.RMPTR21.UINT16[R_IO_L]) +#define RSCAN0RMPTR21LL (RSCAN0.RMPTR21.UINT8[R_IO_LL]) +#define RSCAN0RMPTR21LH (RSCAN0.RMPTR21.UINT8[R_IO_LH]) +#define RSCAN0RMPTR21H (RSCAN0.RMPTR21.UINT16[R_IO_H]) +#define RSCAN0RMPTR21HL (RSCAN0.RMPTR21.UINT8[R_IO_HL]) +#define RSCAN0RMPTR21HH (RSCAN0.RMPTR21.UINT8[R_IO_HH]) +#define RSCAN0RMDF021 (RSCAN0.RMDF021.UINT32) +#define RSCAN0RMDF021L (RSCAN0.RMDF021.UINT16[R_IO_L]) +#define RSCAN0RMDF021LL (RSCAN0.RMDF021.UINT8[R_IO_LL]) +#define RSCAN0RMDF021LH (RSCAN0.RMDF021.UINT8[R_IO_LH]) +#define RSCAN0RMDF021H (RSCAN0.RMDF021.UINT16[R_IO_H]) +#define RSCAN0RMDF021HL (RSCAN0.RMDF021.UINT8[R_IO_HL]) +#define RSCAN0RMDF021HH (RSCAN0.RMDF021.UINT8[R_IO_HH]) +#define RSCAN0RMDF121 (RSCAN0.RMDF121.UINT32) +#define RSCAN0RMDF121L (RSCAN0.RMDF121.UINT16[R_IO_L]) +#define RSCAN0RMDF121LL (RSCAN0.RMDF121.UINT8[R_IO_LL]) +#define RSCAN0RMDF121LH (RSCAN0.RMDF121.UINT8[R_IO_LH]) +#define RSCAN0RMDF121H (RSCAN0.RMDF121.UINT16[R_IO_H]) +#define RSCAN0RMDF121HL (RSCAN0.RMDF121.UINT8[R_IO_HL]) +#define RSCAN0RMDF121HH (RSCAN0.RMDF121.UINT8[R_IO_HH]) +#define RSCAN0RMID22 (RSCAN0.RMID22.UINT32) +#define RSCAN0RMID22L (RSCAN0.RMID22.UINT16[R_IO_L]) +#define RSCAN0RMID22LL (RSCAN0.RMID22.UINT8[R_IO_LL]) +#define RSCAN0RMID22LH (RSCAN0.RMID22.UINT8[R_IO_LH]) +#define RSCAN0RMID22H (RSCAN0.RMID22.UINT16[R_IO_H]) +#define RSCAN0RMID22HL (RSCAN0.RMID22.UINT8[R_IO_HL]) +#define RSCAN0RMID22HH (RSCAN0.RMID22.UINT8[R_IO_HH]) +#define RSCAN0RMPTR22 (RSCAN0.RMPTR22.UINT32) +#define RSCAN0RMPTR22L (RSCAN0.RMPTR22.UINT16[R_IO_L]) +#define RSCAN0RMPTR22LL (RSCAN0.RMPTR22.UINT8[R_IO_LL]) +#define RSCAN0RMPTR22LH (RSCAN0.RMPTR22.UINT8[R_IO_LH]) +#define RSCAN0RMPTR22H (RSCAN0.RMPTR22.UINT16[R_IO_H]) +#define RSCAN0RMPTR22HL (RSCAN0.RMPTR22.UINT8[R_IO_HL]) +#define RSCAN0RMPTR22HH (RSCAN0.RMPTR22.UINT8[R_IO_HH]) +#define RSCAN0RMDF022 (RSCAN0.RMDF022.UINT32) +#define RSCAN0RMDF022L (RSCAN0.RMDF022.UINT16[R_IO_L]) +#define RSCAN0RMDF022LL (RSCAN0.RMDF022.UINT8[R_IO_LL]) +#define RSCAN0RMDF022LH (RSCAN0.RMDF022.UINT8[R_IO_LH]) +#define RSCAN0RMDF022H (RSCAN0.RMDF022.UINT16[R_IO_H]) +#define RSCAN0RMDF022HL (RSCAN0.RMDF022.UINT8[R_IO_HL]) +#define RSCAN0RMDF022HH (RSCAN0.RMDF022.UINT8[R_IO_HH]) +#define RSCAN0RMDF122 (RSCAN0.RMDF122.UINT32) +#define RSCAN0RMDF122L (RSCAN0.RMDF122.UINT16[R_IO_L]) +#define RSCAN0RMDF122LL (RSCAN0.RMDF122.UINT8[R_IO_LL]) +#define RSCAN0RMDF122LH (RSCAN0.RMDF122.UINT8[R_IO_LH]) +#define RSCAN0RMDF122H (RSCAN0.RMDF122.UINT16[R_IO_H]) +#define RSCAN0RMDF122HL (RSCAN0.RMDF122.UINT8[R_IO_HL]) +#define RSCAN0RMDF122HH (RSCAN0.RMDF122.UINT8[R_IO_HH]) +#define RSCAN0RMID23 (RSCAN0.RMID23.UINT32) +#define RSCAN0RMID23L (RSCAN0.RMID23.UINT16[R_IO_L]) +#define RSCAN0RMID23LL (RSCAN0.RMID23.UINT8[R_IO_LL]) +#define RSCAN0RMID23LH (RSCAN0.RMID23.UINT8[R_IO_LH]) +#define RSCAN0RMID23H (RSCAN0.RMID23.UINT16[R_IO_H]) +#define RSCAN0RMID23HL (RSCAN0.RMID23.UINT8[R_IO_HL]) +#define RSCAN0RMID23HH (RSCAN0.RMID23.UINT8[R_IO_HH]) +#define RSCAN0RMPTR23 (RSCAN0.RMPTR23.UINT32) +#define RSCAN0RMPTR23L (RSCAN0.RMPTR23.UINT16[R_IO_L]) +#define RSCAN0RMPTR23LL (RSCAN0.RMPTR23.UINT8[R_IO_LL]) +#define RSCAN0RMPTR23LH (RSCAN0.RMPTR23.UINT8[R_IO_LH]) +#define RSCAN0RMPTR23H (RSCAN0.RMPTR23.UINT16[R_IO_H]) +#define RSCAN0RMPTR23HL (RSCAN0.RMPTR23.UINT8[R_IO_HL]) +#define RSCAN0RMPTR23HH (RSCAN0.RMPTR23.UINT8[R_IO_HH]) +#define RSCAN0RMDF023 (RSCAN0.RMDF023.UINT32) +#define RSCAN0RMDF023L (RSCAN0.RMDF023.UINT16[R_IO_L]) +#define RSCAN0RMDF023LL (RSCAN0.RMDF023.UINT8[R_IO_LL]) +#define RSCAN0RMDF023LH (RSCAN0.RMDF023.UINT8[R_IO_LH]) +#define RSCAN0RMDF023H (RSCAN0.RMDF023.UINT16[R_IO_H]) +#define RSCAN0RMDF023HL (RSCAN0.RMDF023.UINT8[R_IO_HL]) +#define RSCAN0RMDF023HH (RSCAN0.RMDF023.UINT8[R_IO_HH]) +#define RSCAN0RMDF123 (RSCAN0.RMDF123.UINT32) +#define RSCAN0RMDF123L (RSCAN0.RMDF123.UINT16[R_IO_L]) +#define RSCAN0RMDF123LL (RSCAN0.RMDF123.UINT8[R_IO_LL]) +#define RSCAN0RMDF123LH (RSCAN0.RMDF123.UINT8[R_IO_LH]) +#define RSCAN0RMDF123H (RSCAN0.RMDF123.UINT16[R_IO_H]) +#define RSCAN0RMDF123HL (RSCAN0.RMDF123.UINT8[R_IO_HL]) +#define RSCAN0RMDF123HH (RSCAN0.RMDF123.UINT8[R_IO_HH]) +#define RSCAN0RMID24 (RSCAN0.RMID24.UINT32) +#define RSCAN0RMID24L (RSCAN0.RMID24.UINT16[R_IO_L]) +#define RSCAN0RMID24LL (RSCAN0.RMID24.UINT8[R_IO_LL]) +#define RSCAN0RMID24LH (RSCAN0.RMID24.UINT8[R_IO_LH]) +#define RSCAN0RMID24H (RSCAN0.RMID24.UINT16[R_IO_H]) +#define RSCAN0RMID24HL (RSCAN0.RMID24.UINT8[R_IO_HL]) +#define RSCAN0RMID24HH (RSCAN0.RMID24.UINT8[R_IO_HH]) +#define RSCAN0RMPTR24 (RSCAN0.RMPTR24.UINT32) +#define RSCAN0RMPTR24L (RSCAN0.RMPTR24.UINT16[R_IO_L]) +#define RSCAN0RMPTR24LL (RSCAN0.RMPTR24.UINT8[R_IO_LL]) +#define RSCAN0RMPTR24LH (RSCAN0.RMPTR24.UINT8[R_IO_LH]) +#define RSCAN0RMPTR24H (RSCAN0.RMPTR24.UINT16[R_IO_H]) +#define RSCAN0RMPTR24HL (RSCAN0.RMPTR24.UINT8[R_IO_HL]) +#define RSCAN0RMPTR24HH (RSCAN0.RMPTR24.UINT8[R_IO_HH]) +#define RSCAN0RMDF024 (RSCAN0.RMDF024.UINT32) +#define RSCAN0RMDF024L (RSCAN0.RMDF024.UINT16[R_IO_L]) +#define RSCAN0RMDF024LL (RSCAN0.RMDF024.UINT8[R_IO_LL]) +#define RSCAN0RMDF024LH (RSCAN0.RMDF024.UINT8[R_IO_LH]) +#define RSCAN0RMDF024H (RSCAN0.RMDF024.UINT16[R_IO_H]) +#define RSCAN0RMDF024HL (RSCAN0.RMDF024.UINT8[R_IO_HL]) +#define RSCAN0RMDF024HH (RSCAN0.RMDF024.UINT8[R_IO_HH]) +#define RSCAN0RMDF124 (RSCAN0.RMDF124.UINT32) +#define RSCAN0RMDF124L (RSCAN0.RMDF124.UINT16[R_IO_L]) +#define RSCAN0RMDF124LL (RSCAN0.RMDF124.UINT8[R_IO_LL]) +#define RSCAN0RMDF124LH (RSCAN0.RMDF124.UINT8[R_IO_LH]) +#define RSCAN0RMDF124H (RSCAN0.RMDF124.UINT16[R_IO_H]) +#define RSCAN0RMDF124HL (RSCAN0.RMDF124.UINT8[R_IO_HL]) +#define RSCAN0RMDF124HH (RSCAN0.RMDF124.UINT8[R_IO_HH]) +#define RSCAN0RMID25 (RSCAN0.RMID25.UINT32) +#define RSCAN0RMID25L (RSCAN0.RMID25.UINT16[R_IO_L]) +#define RSCAN0RMID25LL (RSCAN0.RMID25.UINT8[R_IO_LL]) +#define RSCAN0RMID25LH (RSCAN0.RMID25.UINT8[R_IO_LH]) +#define RSCAN0RMID25H (RSCAN0.RMID25.UINT16[R_IO_H]) +#define RSCAN0RMID25HL (RSCAN0.RMID25.UINT8[R_IO_HL]) +#define RSCAN0RMID25HH (RSCAN0.RMID25.UINT8[R_IO_HH]) +#define RSCAN0RMPTR25 (RSCAN0.RMPTR25.UINT32) +#define RSCAN0RMPTR25L (RSCAN0.RMPTR25.UINT16[R_IO_L]) +#define RSCAN0RMPTR25LL (RSCAN0.RMPTR25.UINT8[R_IO_LL]) +#define RSCAN0RMPTR25LH (RSCAN0.RMPTR25.UINT8[R_IO_LH]) +#define RSCAN0RMPTR25H (RSCAN0.RMPTR25.UINT16[R_IO_H]) +#define RSCAN0RMPTR25HL (RSCAN0.RMPTR25.UINT8[R_IO_HL]) +#define RSCAN0RMPTR25HH (RSCAN0.RMPTR25.UINT8[R_IO_HH]) +#define RSCAN0RMDF025 (RSCAN0.RMDF025.UINT32) +#define RSCAN0RMDF025L (RSCAN0.RMDF025.UINT16[R_IO_L]) +#define RSCAN0RMDF025LL (RSCAN0.RMDF025.UINT8[R_IO_LL]) +#define RSCAN0RMDF025LH (RSCAN0.RMDF025.UINT8[R_IO_LH]) +#define RSCAN0RMDF025H (RSCAN0.RMDF025.UINT16[R_IO_H]) +#define RSCAN0RMDF025HL (RSCAN0.RMDF025.UINT8[R_IO_HL]) +#define RSCAN0RMDF025HH (RSCAN0.RMDF025.UINT8[R_IO_HH]) +#define RSCAN0RMDF125 (RSCAN0.RMDF125.UINT32) +#define RSCAN0RMDF125L (RSCAN0.RMDF125.UINT16[R_IO_L]) +#define RSCAN0RMDF125LL (RSCAN0.RMDF125.UINT8[R_IO_LL]) +#define RSCAN0RMDF125LH (RSCAN0.RMDF125.UINT8[R_IO_LH]) +#define RSCAN0RMDF125H (RSCAN0.RMDF125.UINT16[R_IO_H]) +#define RSCAN0RMDF125HL (RSCAN0.RMDF125.UINT8[R_IO_HL]) +#define RSCAN0RMDF125HH (RSCAN0.RMDF125.UINT8[R_IO_HH]) +#define RSCAN0RMID26 (RSCAN0.RMID26.UINT32) +#define RSCAN0RMID26L (RSCAN0.RMID26.UINT16[R_IO_L]) +#define RSCAN0RMID26LL (RSCAN0.RMID26.UINT8[R_IO_LL]) +#define RSCAN0RMID26LH (RSCAN0.RMID26.UINT8[R_IO_LH]) +#define RSCAN0RMID26H (RSCAN0.RMID26.UINT16[R_IO_H]) +#define RSCAN0RMID26HL (RSCAN0.RMID26.UINT8[R_IO_HL]) +#define RSCAN0RMID26HH (RSCAN0.RMID26.UINT8[R_IO_HH]) +#define RSCAN0RMPTR26 (RSCAN0.RMPTR26.UINT32) +#define RSCAN0RMPTR26L (RSCAN0.RMPTR26.UINT16[R_IO_L]) +#define RSCAN0RMPTR26LL (RSCAN0.RMPTR26.UINT8[R_IO_LL]) +#define RSCAN0RMPTR26LH (RSCAN0.RMPTR26.UINT8[R_IO_LH]) +#define RSCAN0RMPTR26H (RSCAN0.RMPTR26.UINT16[R_IO_H]) +#define RSCAN0RMPTR26HL (RSCAN0.RMPTR26.UINT8[R_IO_HL]) +#define RSCAN0RMPTR26HH (RSCAN0.RMPTR26.UINT8[R_IO_HH]) +#define RSCAN0RMDF026 (RSCAN0.RMDF026.UINT32) +#define RSCAN0RMDF026L (RSCAN0.RMDF026.UINT16[R_IO_L]) +#define RSCAN0RMDF026LL (RSCAN0.RMDF026.UINT8[R_IO_LL]) +#define RSCAN0RMDF026LH (RSCAN0.RMDF026.UINT8[R_IO_LH]) +#define RSCAN0RMDF026H (RSCAN0.RMDF026.UINT16[R_IO_H]) +#define RSCAN0RMDF026HL (RSCAN0.RMDF026.UINT8[R_IO_HL]) +#define RSCAN0RMDF026HH (RSCAN0.RMDF026.UINT8[R_IO_HH]) +#define RSCAN0RMDF126 (RSCAN0.RMDF126.UINT32) +#define RSCAN0RMDF126L (RSCAN0.RMDF126.UINT16[R_IO_L]) +#define RSCAN0RMDF126LL (RSCAN0.RMDF126.UINT8[R_IO_LL]) +#define RSCAN0RMDF126LH (RSCAN0.RMDF126.UINT8[R_IO_LH]) +#define RSCAN0RMDF126H (RSCAN0.RMDF126.UINT16[R_IO_H]) +#define RSCAN0RMDF126HL (RSCAN0.RMDF126.UINT8[R_IO_HL]) +#define RSCAN0RMDF126HH (RSCAN0.RMDF126.UINT8[R_IO_HH]) +#define RSCAN0RMID27 (RSCAN0.RMID27.UINT32) +#define RSCAN0RMID27L (RSCAN0.RMID27.UINT16[R_IO_L]) +#define RSCAN0RMID27LL (RSCAN0.RMID27.UINT8[R_IO_LL]) +#define RSCAN0RMID27LH (RSCAN0.RMID27.UINT8[R_IO_LH]) +#define RSCAN0RMID27H (RSCAN0.RMID27.UINT16[R_IO_H]) +#define RSCAN0RMID27HL (RSCAN0.RMID27.UINT8[R_IO_HL]) +#define RSCAN0RMID27HH (RSCAN0.RMID27.UINT8[R_IO_HH]) +#define RSCAN0RMPTR27 (RSCAN0.RMPTR27.UINT32) +#define RSCAN0RMPTR27L (RSCAN0.RMPTR27.UINT16[R_IO_L]) +#define RSCAN0RMPTR27LL (RSCAN0.RMPTR27.UINT8[R_IO_LL]) +#define RSCAN0RMPTR27LH (RSCAN0.RMPTR27.UINT8[R_IO_LH]) +#define RSCAN0RMPTR27H (RSCAN0.RMPTR27.UINT16[R_IO_H]) +#define RSCAN0RMPTR27HL (RSCAN0.RMPTR27.UINT8[R_IO_HL]) +#define RSCAN0RMPTR27HH (RSCAN0.RMPTR27.UINT8[R_IO_HH]) +#define RSCAN0RMDF027 (RSCAN0.RMDF027.UINT32) +#define RSCAN0RMDF027L (RSCAN0.RMDF027.UINT16[R_IO_L]) +#define RSCAN0RMDF027LL (RSCAN0.RMDF027.UINT8[R_IO_LL]) +#define RSCAN0RMDF027LH (RSCAN0.RMDF027.UINT8[R_IO_LH]) +#define RSCAN0RMDF027H (RSCAN0.RMDF027.UINT16[R_IO_H]) +#define RSCAN0RMDF027HL (RSCAN0.RMDF027.UINT8[R_IO_HL]) +#define RSCAN0RMDF027HH (RSCAN0.RMDF027.UINT8[R_IO_HH]) +#define RSCAN0RMDF127 (RSCAN0.RMDF127.UINT32) +#define RSCAN0RMDF127L (RSCAN0.RMDF127.UINT16[R_IO_L]) +#define RSCAN0RMDF127LL (RSCAN0.RMDF127.UINT8[R_IO_LL]) +#define RSCAN0RMDF127LH (RSCAN0.RMDF127.UINT8[R_IO_LH]) +#define RSCAN0RMDF127H (RSCAN0.RMDF127.UINT16[R_IO_H]) +#define RSCAN0RMDF127HL (RSCAN0.RMDF127.UINT8[R_IO_HL]) +#define RSCAN0RMDF127HH (RSCAN0.RMDF127.UINT8[R_IO_HH]) +#define RSCAN0RMID28 (RSCAN0.RMID28.UINT32) +#define RSCAN0RMID28L (RSCAN0.RMID28.UINT16[R_IO_L]) +#define RSCAN0RMID28LL (RSCAN0.RMID28.UINT8[R_IO_LL]) +#define RSCAN0RMID28LH (RSCAN0.RMID28.UINT8[R_IO_LH]) +#define RSCAN0RMID28H (RSCAN0.RMID28.UINT16[R_IO_H]) +#define RSCAN0RMID28HL (RSCAN0.RMID28.UINT8[R_IO_HL]) +#define RSCAN0RMID28HH (RSCAN0.RMID28.UINT8[R_IO_HH]) +#define RSCAN0RMPTR28 (RSCAN0.RMPTR28.UINT32) +#define RSCAN0RMPTR28L (RSCAN0.RMPTR28.UINT16[R_IO_L]) +#define RSCAN0RMPTR28LL (RSCAN0.RMPTR28.UINT8[R_IO_LL]) +#define RSCAN0RMPTR28LH (RSCAN0.RMPTR28.UINT8[R_IO_LH]) +#define RSCAN0RMPTR28H (RSCAN0.RMPTR28.UINT16[R_IO_H]) +#define RSCAN0RMPTR28HL (RSCAN0.RMPTR28.UINT8[R_IO_HL]) +#define RSCAN0RMPTR28HH (RSCAN0.RMPTR28.UINT8[R_IO_HH]) +#define RSCAN0RMDF028 (RSCAN0.RMDF028.UINT32) +#define RSCAN0RMDF028L (RSCAN0.RMDF028.UINT16[R_IO_L]) +#define RSCAN0RMDF028LL (RSCAN0.RMDF028.UINT8[R_IO_LL]) +#define RSCAN0RMDF028LH (RSCAN0.RMDF028.UINT8[R_IO_LH]) +#define RSCAN0RMDF028H (RSCAN0.RMDF028.UINT16[R_IO_H]) +#define RSCAN0RMDF028HL (RSCAN0.RMDF028.UINT8[R_IO_HL]) +#define RSCAN0RMDF028HH (RSCAN0.RMDF028.UINT8[R_IO_HH]) +#define RSCAN0RMDF128 (RSCAN0.RMDF128.UINT32) +#define RSCAN0RMDF128L (RSCAN0.RMDF128.UINT16[R_IO_L]) +#define RSCAN0RMDF128LL (RSCAN0.RMDF128.UINT8[R_IO_LL]) +#define RSCAN0RMDF128LH (RSCAN0.RMDF128.UINT8[R_IO_LH]) +#define RSCAN0RMDF128H (RSCAN0.RMDF128.UINT16[R_IO_H]) +#define RSCAN0RMDF128HL (RSCAN0.RMDF128.UINT8[R_IO_HL]) +#define RSCAN0RMDF128HH (RSCAN0.RMDF128.UINT8[R_IO_HH]) +#define RSCAN0RMID29 (RSCAN0.RMID29.UINT32) +#define RSCAN0RMID29L (RSCAN0.RMID29.UINT16[R_IO_L]) +#define RSCAN0RMID29LL (RSCAN0.RMID29.UINT8[R_IO_LL]) +#define RSCAN0RMID29LH (RSCAN0.RMID29.UINT8[R_IO_LH]) +#define RSCAN0RMID29H (RSCAN0.RMID29.UINT16[R_IO_H]) +#define RSCAN0RMID29HL (RSCAN0.RMID29.UINT8[R_IO_HL]) +#define RSCAN0RMID29HH (RSCAN0.RMID29.UINT8[R_IO_HH]) +#define RSCAN0RMPTR29 (RSCAN0.RMPTR29.UINT32) +#define RSCAN0RMPTR29L (RSCAN0.RMPTR29.UINT16[R_IO_L]) +#define RSCAN0RMPTR29LL (RSCAN0.RMPTR29.UINT8[R_IO_LL]) +#define RSCAN0RMPTR29LH (RSCAN0.RMPTR29.UINT8[R_IO_LH]) +#define RSCAN0RMPTR29H (RSCAN0.RMPTR29.UINT16[R_IO_H]) +#define RSCAN0RMPTR29HL (RSCAN0.RMPTR29.UINT8[R_IO_HL]) +#define RSCAN0RMPTR29HH (RSCAN0.RMPTR29.UINT8[R_IO_HH]) +#define RSCAN0RMDF029 (RSCAN0.RMDF029.UINT32) +#define RSCAN0RMDF029L (RSCAN0.RMDF029.UINT16[R_IO_L]) +#define RSCAN0RMDF029LL (RSCAN0.RMDF029.UINT8[R_IO_LL]) +#define RSCAN0RMDF029LH (RSCAN0.RMDF029.UINT8[R_IO_LH]) +#define RSCAN0RMDF029H (RSCAN0.RMDF029.UINT16[R_IO_H]) +#define RSCAN0RMDF029HL (RSCAN0.RMDF029.UINT8[R_IO_HL]) +#define RSCAN0RMDF029HH (RSCAN0.RMDF029.UINT8[R_IO_HH]) +#define RSCAN0RMDF129 (RSCAN0.RMDF129.UINT32) +#define RSCAN0RMDF129L (RSCAN0.RMDF129.UINT16[R_IO_L]) +#define RSCAN0RMDF129LL (RSCAN0.RMDF129.UINT8[R_IO_LL]) +#define RSCAN0RMDF129LH (RSCAN0.RMDF129.UINT8[R_IO_LH]) +#define RSCAN0RMDF129H (RSCAN0.RMDF129.UINT16[R_IO_H]) +#define RSCAN0RMDF129HL (RSCAN0.RMDF129.UINT8[R_IO_HL]) +#define RSCAN0RMDF129HH (RSCAN0.RMDF129.UINT8[R_IO_HH]) +#define RSCAN0RMID30 (RSCAN0.RMID30.UINT32) +#define RSCAN0RMID30L (RSCAN0.RMID30.UINT16[R_IO_L]) +#define RSCAN0RMID30LL (RSCAN0.RMID30.UINT8[R_IO_LL]) +#define RSCAN0RMID30LH (RSCAN0.RMID30.UINT8[R_IO_LH]) +#define RSCAN0RMID30H (RSCAN0.RMID30.UINT16[R_IO_H]) +#define RSCAN0RMID30HL (RSCAN0.RMID30.UINT8[R_IO_HL]) +#define RSCAN0RMID30HH (RSCAN0.RMID30.UINT8[R_IO_HH]) +#define RSCAN0RMPTR30 (RSCAN0.RMPTR30.UINT32) +#define RSCAN0RMPTR30L (RSCAN0.RMPTR30.UINT16[R_IO_L]) +#define RSCAN0RMPTR30LL (RSCAN0.RMPTR30.UINT8[R_IO_LL]) +#define RSCAN0RMPTR30LH (RSCAN0.RMPTR30.UINT8[R_IO_LH]) +#define RSCAN0RMPTR30H (RSCAN0.RMPTR30.UINT16[R_IO_H]) +#define RSCAN0RMPTR30HL (RSCAN0.RMPTR30.UINT8[R_IO_HL]) +#define RSCAN0RMPTR30HH (RSCAN0.RMPTR30.UINT8[R_IO_HH]) +#define RSCAN0RMDF030 (RSCAN0.RMDF030.UINT32) +#define RSCAN0RMDF030L (RSCAN0.RMDF030.UINT16[R_IO_L]) +#define RSCAN0RMDF030LL (RSCAN0.RMDF030.UINT8[R_IO_LL]) +#define RSCAN0RMDF030LH (RSCAN0.RMDF030.UINT8[R_IO_LH]) +#define RSCAN0RMDF030H (RSCAN0.RMDF030.UINT16[R_IO_H]) +#define RSCAN0RMDF030HL (RSCAN0.RMDF030.UINT8[R_IO_HL]) +#define RSCAN0RMDF030HH (RSCAN0.RMDF030.UINT8[R_IO_HH]) +#define RSCAN0RMDF130 (RSCAN0.RMDF130.UINT32) +#define RSCAN0RMDF130L (RSCAN0.RMDF130.UINT16[R_IO_L]) +#define RSCAN0RMDF130LL (RSCAN0.RMDF130.UINT8[R_IO_LL]) +#define RSCAN0RMDF130LH (RSCAN0.RMDF130.UINT8[R_IO_LH]) +#define RSCAN0RMDF130H (RSCAN0.RMDF130.UINT16[R_IO_H]) +#define RSCAN0RMDF130HL (RSCAN0.RMDF130.UINT8[R_IO_HL]) +#define RSCAN0RMDF130HH (RSCAN0.RMDF130.UINT8[R_IO_HH]) +#define RSCAN0RMID31 (RSCAN0.RMID31.UINT32) +#define RSCAN0RMID31L (RSCAN0.RMID31.UINT16[R_IO_L]) +#define RSCAN0RMID31LL (RSCAN0.RMID31.UINT8[R_IO_LL]) +#define RSCAN0RMID31LH (RSCAN0.RMID31.UINT8[R_IO_LH]) +#define RSCAN0RMID31H (RSCAN0.RMID31.UINT16[R_IO_H]) +#define RSCAN0RMID31HL (RSCAN0.RMID31.UINT8[R_IO_HL]) +#define RSCAN0RMID31HH (RSCAN0.RMID31.UINT8[R_IO_HH]) +#define RSCAN0RMPTR31 (RSCAN0.RMPTR31.UINT32) +#define RSCAN0RMPTR31L (RSCAN0.RMPTR31.UINT16[R_IO_L]) +#define RSCAN0RMPTR31LL (RSCAN0.RMPTR31.UINT8[R_IO_LL]) +#define RSCAN0RMPTR31LH (RSCAN0.RMPTR31.UINT8[R_IO_LH]) +#define RSCAN0RMPTR31H (RSCAN0.RMPTR31.UINT16[R_IO_H]) +#define RSCAN0RMPTR31HL (RSCAN0.RMPTR31.UINT8[R_IO_HL]) +#define RSCAN0RMPTR31HH (RSCAN0.RMPTR31.UINT8[R_IO_HH]) +#define RSCAN0RMDF031 (RSCAN0.RMDF031.UINT32) +#define RSCAN0RMDF031L (RSCAN0.RMDF031.UINT16[R_IO_L]) +#define RSCAN0RMDF031LL (RSCAN0.RMDF031.UINT8[R_IO_LL]) +#define RSCAN0RMDF031LH (RSCAN0.RMDF031.UINT8[R_IO_LH]) +#define RSCAN0RMDF031H (RSCAN0.RMDF031.UINT16[R_IO_H]) +#define RSCAN0RMDF031HL (RSCAN0.RMDF031.UINT8[R_IO_HL]) +#define RSCAN0RMDF031HH (RSCAN0.RMDF031.UINT8[R_IO_HH]) +#define RSCAN0RMDF131 (RSCAN0.RMDF131.UINT32) +#define RSCAN0RMDF131L (RSCAN0.RMDF131.UINT16[R_IO_L]) +#define RSCAN0RMDF131LL (RSCAN0.RMDF131.UINT8[R_IO_LL]) +#define RSCAN0RMDF131LH (RSCAN0.RMDF131.UINT8[R_IO_LH]) +#define RSCAN0RMDF131H (RSCAN0.RMDF131.UINT16[R_IO_H]) +#define RSCAN0RMDF131HL (RSCAN0.RMDF131.UINT8[R_IO_HL]) +#define RSCAN0RMDF131HH (RSCAN0.RMDF131.UINT8[R_IO_HH]) +#define RSCAN0RMID32 (RSCAN0.RMID32.UINT32) +#define RSCAN0RMID32L (RSCAN0.RMID32.UINT16[R_IO_L]) +#define RSCAN0RMID32LL (RSCAN0.RMID32.UINT8[R_IO_LL]) +#define RSCAN0RMID32LH (RSCAN0.RMID32.UINT8[R_IO_LH]) +#define RSCAN0RMID32H (RSCAN0.RMID32.UINT16[R_IO_H]) +#define RSCAN0RMID32HL (RSCAN0.RMID32.UINT8[R_IO_HL]) +#define RSCAN0RMID32HH (RSCAN0.RMID32.UINT8[R_IO_HH]) +#define RSCAN0RMPTR32 (RSCAN0.RMPTR32.UINT32) +#define RSCAN0RMPTR32L (RSCAN0.RMPTR32.UINT16[R_IO_L]) +#define RSCAN0RMPTR32LL (RSCAN0.RMPTR32.UINT8[R_IO_LL]) +#define RSCAN0RMPTR32LH (RSCAN0.RMPTR32.UINT8[R_IO_LH]) +#define RSCAN0RMPTR32H (RSCAN0.RMPTR32.UINT16[R_IO_H]) +#define RSCAN0RMPTR32HL (RSCAN0.RMPTR32.UINT8[R_IO_HL]) +#define RSCAN0RMPTR32HH (RSCAN0.RMPTR32.UINT8[R_IO_HH]) +#define RSCAN0RMDF032 (RSCAN0.RMDF032.UINT32) +#define RSCAN0RMDF032L (RSCAN0.RMDF032.UINT16[R_IO_L]) +#define RSCAN0RMDF032LL (RSCAN0.RMDF032.UINT8[R_IO_LL]) +#define RSCAN0RMDF032LH (RSCAN0.RMDF032.UINT8[R_IO_LH]) +#define RSCAN0RMDF032H (RSCAN0.RMDF032.UINT16[R_IO_H]) +#define RSCAN0RMDF032HL (RSCAN0.RMDF032.UINT8[R_IO_HL]) +#define RSCAN0RMDF032HH (RSCAN0.RMDF032.UINT8[R_IO_HH]) +#define RSCAN0RMDF132 (RSCAN0.RMDF132.UINT32) +#define RSCAN0RMDF132L (RSCAN0.RMDF132.UINT16[R_IO_L]) +#define RSCAN0RMDF132LL (RSCAN0.RMDF132.UINT8[R_IO_LL]) +#define RSCAN0RMDF132LH (RSCAN0.RMDF132.UINT8[R_IO_LH]) +#define RSCAN0RMDF132H (RSCAN0.RMDF132.UINT16[R_IO_H]) +#define RSCAN0RMDF132HL (RSCAN0.RMDF132.UINT8[R_IO_HL]) +#define RSCAN0RMDF132HH (RSCAN0.RMDF132.UINT8[R_IO_HH]) +#define RSCAN0RMID33 (RSCAN0.RMID33.UINT32) +#define RSCAN0RMID33L (RSCAN0.RMID33.UINT16[R_IO_L]) +#define RSCAN0RMID33LL (RSCAN0.RMID33.UINT8[R_IO_LL]) +#define RSCAN0RMID33LH (RSCAN0.RMID33.UINT8[R_IO_LH]) +#define RSCAN0RMID33H (RSCAN0.RMID33.UINT16[R_IO_H]) +#define RSCAN0RMID33HL (RSCAN0.RMID33.UINT8[R_IO_HL]) +#define RSCAN0RMID33HH (RSCAN0.RMID33.UINT8[R_IO_HH]) +#define RSCAN0RMPTR33 (RSCAN0.RMPTR33.UINT32) +#define RSCAN0RMPTR33L (RSCAN0.RMPTR33.UINT16[R_IO_L]) +#define RSCAN0RMPTR33LL (RSCAN0.RMPTR33.UINT8[R_IO_LL]) +#define RSCAN0RMPTR33LH (RSCAN0.RMPTR33.UINT8[R_IO_LH]) +#define RSCAN0RMPTR33H (RSCAN0.RMPTR33.UINT16[R_IO_H]) +#define RSCAN0RMPTR33HL (RSCAN0.RMPTR33.UINT8[R_IO_HL]) +#define RSCAN0RMPTR33HH (RSCAN0.RMPTR33.UINT8[R_IO_HH]) +#define RSCAN0RMDF033 (RSCAN0.RMDF033.UINT32) +#define RSCAN0RMDF033L (RSCAN0.RMDF033.UINT16[R_IO_L]) +#define RSCAN0RMDF033LL (RSCAN0.RMDF033.UINT8[R_IO_LL]) +#define RSCAN0RMDF033LH (RSCAN0.RMDF033.UINT8[R_IO_LH]) +#define RSCAN0RMDF033H (RSCAN0.RMDF033.UINT16[R_IO_H]) +#define RSCAN0RMDF033HL (RSCAN0.RMDF033.UINT8[R_IO_HL]) +#define RSCAN0RMDF033HH (RSCAN0.RMDF033.UINT8[R_IO_HH]) +#define RSCAN0RMDF133 (RSCAN0.RMDF133.UINT32) +#define RSCAN0RMDF133L (RSCAN0.RMDF133.UINT16[R_IO_L]) +#define RSCAN0RMDF133LL (RSCAN0.RMDF133.UINT8[R_IO_LL]) +#define RSCAN0RMDF133LH (RSCAN0.RMDF133.UINT8[R_IO_LH]) +#define RSCAN0RMDF133H (RSCAN0.RMDF133.UINT16[R_IO_H]) +#define RSCAN0RMDF133HL (RSCAN0.RMDF133.UINT8[R_IO_HL]) +#define RSCAN0RMDF133HH (RSCAN0.RMDF133.UINT8[R_IO_HH]) +#define RSCAN0RMID34 (RSCAN0.RMID34.UINT32) +#define RSCAN0RMID34L (RSCAN0.RMID34.UINT16[R_IO_L]) +#define RSCAN0RMID34LL (RSCAN0.RMID34.UINT8[R_IO_LL]) +#define RSCAN0RMID34LH (RSCAN0.RMID34.UINT8[R_IO_LH]) +#define RSCAN0RMID34H (RSCAN0.RMID34.UINT16[R_IO_H]) +#define RSCAN0RMID34HL (RSCAN0.RMID34.UINT8[R_IO_HL]) +#define RSCAN0RMID34HH (RSCAN0.RMID34.UINT8[R_IO_HH]) +#define RSCAN0RMPTR34 (RSCAN0.RMPTR34.UINT32) +#define RSCAN0RMPTR34L (RSCAN0.RMPTR34.UINT16[R_IO_L]) +#define RSCAN0RMPTR34LL (RSCAN0.RMPTR34.UINT8[R_IO_LL]) +#define RSCAN0RMPTR34LH (RSCAN0.RMPTR34.UINT8[R_IO_LH]) +#define RSCAN0RMPTR34H (RSCAN0.RMPTR34.UINT16[R_IO_H]) +#define RSCAN0RMPTR34HL (RSCAN0.RMPTR34.UINT8[R_IO_HL]) +#define RSCAN0RMPTR34HH (RSCAN0.RMPTR34.UINT8[R_IO_HH]) +#define RSCAN0RMDF034 (RSCAN0.RMDF034.UINT32) +#define RSCAN0RMDF034L (RSCAN0.RMDF034.UINT16[R_IO_L]) +#define RSCAN0RMDF034LL (RSCAN0.RMDF034.UINT8[R_IO_LL]) +#define RSCAN0RMDF034LH (RSCAN0.RMDF034.UINT8[R_IO_LH]) +#define RSCAN0RMDF034H (RSCAN0.RMDF034.UINT16[R_IO_H]) +#define RSCAN0RMDF034HL (RSCAN0.RMDF034.UINT8[R_IO_HL]) +#define RSCAN0RMDF034HH (RSCAN0.RMDF034.UINT8[R_IO_HH]) +#define RSCAN0RMDF134 (RSCAN0.RMDF134.UINT32) +#define RSCAN0RMDF134L (RSCAN0.RMDF134.UINT16[R_IO_L]) +#define RSCAN0RMDF134LL (RSCAN0.RMDF134.UINT8[R_IO_LL]) +#define RSCAN0RMDF134LH (RSCAN0.RMDF134.UINT8[R_IO_LH]) +#define RSCAN0RMDF134H (RSCAN0.RMDF134.UINT16[R_IO_H]) +#define RSCAN0RMDF134HL (RSCAN0.RMDF134.UINT8[R_IO_HL]) +#define RSCAN0RMDF134HH (RSCAN0.RMDF134.UINT8[R_IO_HH]) +#define RSCAN0RMID35 (RSCAN0.RMID35.UINT32) +#define RSCAN0RMID35L (RSCAN0.RMID35.UINT16[R_IO_L]) +#define RSCAN0RMID35LL (RSCAN0.RMID35.UINT8[R_IO_LL]) +#define RSCAN0RMID35LH (RSCAN0.RMID35.UINT8[R_IO_LH]) +#define RSCAN0RMID35H (RSCAN0.RMID35.UINT16[R_IO_H]) +#define RSCAN0RMID35HL (RSCAN0.RMID35.UINT8[R_IO_HL]) +#define RSCAN0RMID35HH (RSCAN0.RMID35.UINT8[R_IO_HH]) +#define RSCAN0RMPTR35 (RSCAN0.RMPTR35.UINT32) +#define RSCAN0RMPTR35L (RSCAN0.RMPTR35.UINT16[R_IO_L]) +#define RSCAN0RMPTR35LL (RSCAN0.RMPTR35.UINT8[R_IO_LL]) +#define RSCAN0RMPTR35LH (RSCAN0.RMPTR35.UINT8[R_IO_LH]) +#define RSCAN0RMPTR35H (RSCAN0.RMPTR35.UINT16[R_IO_H]) +#define RSCAN0RMPTR35HL (RSCAN0.RMPTR35.UINT8[R_IO_HL]) +#define RSCAN0RMPTR35HH (RSCAN0.RMPTR35.UINT8[R_IO_HH]) +#define RSCAN0RMDF035 (RSCAN0.RMDF035.UINT32) +#define RSCAN0RMDF035L (RSCAN0.RMDF035.UINT16[R_IO_L]) +#define RSCAN0RMDF035LL (RSCAN0.RMDF035.UINT8[R_IO_LL]) +#define RSCAN0RMDF035LH (RSCAN0.RMDF035.UINT8[R_IO_LH]) +#define RSCAN0RMDF035H (RSCAN0.RMDF035.UINT16[R_IO_H]) +#define RSCAN0RMDF035HL (RSCAN0.RMDF035.UINT8[R_IO_HL]) +#define RSCAN0RMDF035HH (RSCAN0.RMDF035.UINT8[R_IO_HH]) +#define RSCAN0RMDF135 (RSCAN0.RMDF135.UINT32) +#define RSCAN0RMDF135L (RSCAN0.RMDF135.UINT16[R_IO_L]) +#define RSCAN0RMDF135LL (RSCAN0.RMDF135.UINT8[R_IO_LL]) +#define RSCAN0RMDF135LH (RSCAN0.RMDF135.UINT8[R_IO_LH]) +#define RSCAN0RMDF135H (RSCAN0.RMDF135.UINT16[R_IO_H]) +#define RSCAN0RMDF135HL (RSCAN0.RMDF135.UINT8[R_IO_HL]) +#define RSCAN0RMDF135HH (RSCAN0.RMDF135.UINT8[R_IO_HH]) +#define RSCAN0RMID36 (RSCAN0.RMID36.UINT32) +#define RSCAN0RMID36L (RSCAN0.RMID36.UINT16[R_IO_L]) +#define RSCAN0RMID36LL (RSCAN0.RMID36.UINT8[R_IO_LL]) +#define RSCAN0RMID36LH (RSCAN0.RMID36.UINT8[R_IO_LH]) +#define RSCAN0RMID36H (RSCAN0.RMID36.UINT16[R_IO_H]) +#define RSCAN0RMID36HL (RSCAN0.RMID36.UINT8[R_IO_HL]) +#define RSCAN0RMID36HH (RSCAN0.RMID36.UINT8[R_IO_HH]) +#define RSCAN0RMPTR36 (RSCAN0.RMPTR36.UINT32) +#define RSCAN0RMPTR36L (RSCAN0.RMPTR36.UINT16[R_IO_L]) +#define RSCAN0RMPTR36LL (RSCAN0.RMPTR36.UINT8[R_IO_LL]) +#define RSCAN0RMPTR36LH (RSCAN0.RMPTR36.UINT8[R_IO_LH]) +#define RSCAN0RMPTR36H (RSCAN0.RMPTR36.UINT16[R_IO_H]) +#define RSCAN0RMPTR36HL (RSCAN0.RMPTR36.UINT8[R_IO_HL]) +#define RSCAN0RMPTR36HH (RSCAN0.RMPTR36.UINT8[R_IO_HH]) +#define RSCAN0RMDF036 (RSCAN0.RMDF036.UINT32) +#define RSCAN0RMDF036L (RSCAN0.RMDF036.UINT16[R_IO_L]) +#define RSCAN0RMDF036LL (RSCAN0.RMDF036.UINT8[R_IO_LL]) +#define RSCAN0RMDF036LH (RSCAN0.RMDF036.UINT8[R_IO_LH]) +#define RSCAN0RMDF036H (RSCAN0.RMDF036.UINT16[R_IO_H]) +#define RSCAN0RMDF036HL (RSCAN0.RMDF036.UINT8[R_IO_HL]) +#define RSCAN0RMDF036HH (RSCAN0.RMDF036.UINT8[R_IO_HH]) +#define RSCAN0RMDF136 (RSCAN0.RMDF136.UINT32) +#define RSCAN0RMDF136L (RSCAN0.RMDF136.UINT16[R_IO_L]) +#define RSCAN0RMDF136LL (RSCAN0.RMDF136.UINT8[R_IO_LL]) +#define RSCAN0RMDF136LH (RSCAN0.RMDF136.UINT8[R_IO_LH]) +#define RSCAN0RMDF136H (RSCAN0.RMDF136.UINT16[R_IO_H]) +#define RSCAN0RMDF136HL (RSCAN0.RMDF136.UINT8[R_IO_HL]) +#define RSCAN0RMDF136HH (RSCAN0.RMDF136.UINT8[R_IO_HH]) +#define RSCAN0RMID37 (RSCAN0.RMID37.UINT32) +#define RSCAN0RMID37L (RSCAN0.RMID37.UINT16[R_IO_L]) +#define RSCAN0RMID37LL (RSCAN0.RMID37.UINT8[R_IO_LL]) +#define RSCAN0RMID37LH (RSCAN0.RMID37.UINT8[R_IO_LH]) +#define RSCAN0RMID37H (RSCAN0.RMID37.UINT16[R_IO_H]) +#define RSCAN0RMID37HL (RSCAN0.RMID37.UINT8[R_IO_HL]) +#define RSCAN0RMID37HH (RSCAN0.RMID37.UINT8[R_IO_HH]) +#define RSCAN0RMPTR37 (RSCAN0.RMPTR37.UINT32) +#define RSCAN0RMPTR37L (RSCAN0.RMPTR37.UINT16[R_IO_L]) +#define RSCAN0RMPTR37LL (RSCAN0.RMPTR37.UINT8[R_IO_LL]) +#define RSCAN0RMPTR37LH (RSCAN0.RMPTR37.UINT8[R_IO_LH]) +#define RSCAN0RMPTR37H (RSCAN0.RMPTR37.UINT16[R_IO_H]) +#define RSCAN0RMPTR37HL (RSCAN0.RMPTR37.UINT8[R_IO_HL]) +#define RSCAN0RMPTR37HH (RSCAN0.RMPTR37.UINT8[R_IO_HH]) +#define RSCAN0RMDF037 (RSCAN0.RMDF037.UINT32) +#define RSCAN0RMDF037L (RSCAN0.RMDF037.UINT16[R_IO_L]) +#define RSCAN0RMDF037LL (RSCAN0.RMDF037.UINT8[R_IO_LL]) +#define RSCAN0RMDF037LH (RSCAN0.RMDF037.UINT8[R_IO_LH]) +#define RSCAN0RMDF037H (RSCAN0.RMDF037.UINT16[R_IO_H]) +#define RSCAN0RMDF037HL (RSCAN0.RMDF037.UINT8[R_IO_HL]) +#define RSCAN0RMDF037HH (RSCAN0.RMDF037.UINT8[R_IO_HH]) +#define RSCAN0RMDF137 (RSCAN0.RMDF137.UINT32) +#define RSCAN0RMDF137L (RSCAN0.RMDF137.UINT16[R_IO_L]) +#define RSCAN0RMDF137LL (RSCAN0.RMDF137.UINT8[R_IO_LL]) +#define RSCAN0RMDF137LH (RSCAN0.RMDF137.UINT8[R_IO_LH]) +#define RSCAN0RMDF137H (RSCAN0.RMDF137.UINT16[R_IO_H]) +#define RSCAN0RMDF137HL (RSCAN0.RMDF137.UINT8[R_IO_HL]) +#define RSCAN0RMDF137HH (RSCAN0.RMDF137.UINT8[R_IO_HH]) +#define RSCAN0RMID38 (RSCAN0.RMID38.UINT32) +#define RSCAN0RMID38L (RSCAN0.RMID38.UINT16[R_IO_L]) +#define RSCAN0RMID38LL (RSCAN0.RMID38.UINT8[R_IO_LL]) +#define RSCAN0RMID38LH (RSCAN0.RMID38.UINT8[R_IO_LH]) +#define RSCAN0RMID38H (RSCAN0.RMID38.UINT16[R_IO_H]) +#define RSCAN0RMID38HL (RSCAN0.RMID38.UINT8[R_IO_HL]) +#define RSCAN0RMID38HH (RSCAN0.RMID38.UINT8[R_IO_HH]) +#define RSCAN0RMPTR38 (RSCAN0.RMPTR38.UINT32) +#define RSCAN0RMPTR38L (RSCAN0.RMPTR38.UINT16[R_IO_L]) +#define RSCAN0RMPTR38LL (RSCAN0.RMPTR38.UINT8[R_IO_LL]) +#define RSCAN0RMPTR38LH (RSCAN0.RMPTR38.UINT8[R_IO_LH]) +#define RSCAN0RMPTR38H (RSCAN0.RMPTR38.UINT16[R_IO_H]) +#define RSCAN0RMPTR38HL (RSCAN0.RMPTR38.UINT8[R_IO_HL]) +#define RSCAN0RMPTR38HH (RSCAN0.RMPTR38.UINT8[R_IO_HH]) +#define RSCAN0RMDF038 (RSCAN0.RMDF038.UINT32) +#define RSCAN0RMDF038L (RSCAN0.RMDF038.UINT16[R_IO_L]) +#define RSCAN0RMDF038LL (RSCAN0.RMDF038.UINT8[R_IO_LL]) +#define RSCAN0RMDF038LH (RSCAN0.RMDF038.UINT8[R_IO_LH]) +#define RSCAN0RMDF038H (RSCAN0.RMDF038.UINT16[R_IO_H]) +#define RSCAN0RMDF038HL (RSCAN0.RMDF038.UINT8[R_IO_HL]) +#define RSCAN0RMDF038HH (RSCAN0.RMDF038.UINT8[R_IO_HH]) +#define RSCAN0RMDF138 (RSCAN0.RMDF138.UINT32) +#define RSCAN0RMDF138L (RSCAN0.RMDF138.UINT16[R_IO_L]) +#define RSCAN0RMDF138LL (RSCAN0.RMDF138.UINT8[R_IO_LL]) +#define RSCAN0RMDF138LH (RSCAN0.RMDF138.UINT8[R_IO_LH]) +#define RSCAN0RMDF138H (RSCAN0.RMDF138.UINT16[R_IO_H]) +#define RSCAN0RMDF138HL (RSCAN0.RMDF138.UINT8[R_IO_HL]) +#define RSCAN0RMDF138HH (RSCAN0.RMDF138.UINT8[R_IO_HH]) +#define RSCAN0RMID39 (RSCAN0.RMID39.UINT32) +#define RSCAN0RMID39L (RSCAN0.RMID39.UINT16[R_IO_L]) +#define RSCAN0RMID39LL (RSCAN0.RMID39.UINT8[R_IO_LL]) +#define RSCAN0RMID39LH (RSCAN0.RMID39.UINT8[R_IO_LH]) +#define RSCAN0RMID39H (RSCAN0.RMID39.UINT16[R_IO_H]) +#define RSCAN0RMID39HL (RSCAN0.RMID39.UINT8[R_IO_HL]) +#define RSCAN0RMID39HH (RSCAN0.RMID39.UINT8[R_IO_HH]) +#define RSCAN0RMPTR39 (RSCAN0.RMPTR39.UINT32) +#define RSCAN0RMPTR39L (RSCAN0.RMPTR39.UINT16[R_IO_L]) +#define RSCAN0RMPTR39LL (RSCAN0.RMPTR39.UINT8[R_IO_LL]) +#define RSCAN0RMPTR39LH (RSCAN0.RMPTR39.UINT8[R_IO_LH]) +#define RSCAN0RMPTR39H (RSCAN0.RMPTR39.UINT16[R_IO_H]) +#define RSCAN0RMPTR39HL (RSCAN0.RMPTR39.UINT8[R_IO_HL]) +#define RSCAN0RMPTR39HH (RSCAN0.RMPTR39.UINT8[R_IO_HH]) +#define RSCAN0RMDF039 (RSCAN0.RMDF039.UINT32) +#define RSCAN0RMDF039L (RSCAN0.RMDF039.UINT16[R_IO_L]) +#define RSCAN0RMDF039LL (RSCAN0.RMDF039.UINT8[R_IO_LL]) +#define RSCAN0RMDF039LH (RSCAN0.RMDF039.UINT8[R_IO_LH]) +#define RSCAN0RMDF039H (RSCAN0.RMDF039.UINT16[R_IO_H]) +#define RSCAN0RMDF039HL (RSCAN0.RMDF039.UINT8[R_IO_HL]) +#define RSCAN0RMDF039HH (RSCAN0.RMDF039.UINT8[R_IO_HH]) +#define RSCAN0RMDF139 (RSCAN0.RMDF139.UINT32) +#define RSCAN0RMDF139L (RSCAN0.RMDF139.UINT16[R_IO_L]) +#define RSCAN0RMDF139LL (RSCAN0.RMDF139.UINT8[R_IO_LL]) +#define RSCAN0RMDF139LH (RSCAN0.RMDF139.UINT8[R_IO_LH]) +#define RSCAN0RMDF139H (RSCAN0.RMDF139.UINT16[R_IO_H]) +#define RSCAN0RMDF139HL (RSCAN0.RMDF139.UINT8[R_IO_HL]) +#define RSCAN0RMDF139HH (RSCAN0.RMDF139.UINT8[R_IO_HH]) +#define RSCAN0RMID40 (RSCAN0.RMID40.UINT32) +#define RSCAN0RMID40L (RSCAN0.RMID40.UINT16[R_IO_L]) +#define RSCAN0RMID40LL (RSCAN0.RMID40.UINT8[R_IO_LL]) +#define RSCAN0RMID40LH (RSCAN0.RMID40.UINT8[R_IO_LH]) +#define RSCAN0RMID40H (RSCAN0.RMID40.UINT16[R_IO_H]) +#define RSCAN0RMID40HL (RSCAN0.RMID40.UINT8[R_IO_HL]) +#define RSCAN0RMID40HH (RSCAN0.RMID40.UINT8[R_IO_HH]) +#define RSCAN0RMPTR40 (RSCAN0.RMPTR40.UINT32) +#define RSCAN0RMPTR40L (RSCAN0.RMPTR40.UINT16[R_IO_L]) +#define RSCAN0RMPTR40LL (RSCAN0.RMPTR40.UINT8[R_IO_LL]) +#define RSCAN0RMPTR40LH (RSCAN0.RMPTR40.UINT8[R_IO_LH]) +#define RSCAN0RMPTR40H (RSCAN0.RMPTR40.UINT16[R_IO_H]) +#define RSCAN0RMPTR40HL (RSCAN0.RMPTR40.UINT8[R_IO_HL]) +#define RSCAN0RMPTR40HH (RSCAN0.RMPTR40.UINT8[R_IO_HH]) +#define RSCAN0RMDF040 (RSCAN0.RMDF040.UINT32) +#define RSCAN0RMDF040L (RSCAN0.RMDF040.UINT16[R_IO_L]) +#define RSCAN0RMDF040LL (RSCAN0.RMDF040.UINT8[R_IO_LL]) +#define RSCAN0RMDF040LH (RSCAN0.RMDF040.UINT8[R_IO_LH]) +#define RSCAN0RMDF040H (RSCAN0.RMDF040.UINT16[R_IO_H]) +#define RSCAN0RMDF040HL (RSCAN0.RMDF040.UINT8[R_IO_HL]) +#define RSCAN0RMDF040HH (RSCAN0.RMDF040.UINT8[R_IO_HH]) +#define RSCAN0RMDF140 (RSCAN0.RMDF140.UINT32) +#define RSCAN0RMDF140L (RSCAN0.RMDF140.UINT16[R_IO_L]) +#define RSCAN0RMDF140LL (RSCAN0.RMDF140.UINT8[R_IO_LL]) +#define RSCAN0RMDF140LH (RSCAN0.RMDF140.UINT8[R_IO_LH]) +#define RSCAN0RMDF140H (RSCAN0.RMDF140.UINT16[R_IO_H]) +#define RSCAN0RMDF140HL (RSCAN0.RMDF140.UINT8[R_IO_HL]) +#define RSCAN0RMDF140HH (RSCAN0.RMDF140.UINT8[R_IO_HH]) +#define RSCAN0RMID41 (RSCAN0.RMID41.UINT32) +#define RSCAN0RMID41L (RSCAN0.RMID41.UINT16[R_IO_L]) +#define RSCAN0RMID41LL (RSCAN0.RMID41.UINT8[R_IO_LL]) +#define RSCAN0RMID41LH (RSCAN0.RMID41.UINT8[R_IO_LH]) +#define RSCAN0RMID41H (RSCAN0.RMID41.UINT16[R_IO_H]) +#define RSCAN0RMID41HL (RSCAN0.RMID41.UINT8[R_IO_HL]) +#define RSCAN0RMID41HH (RSCAN0.RMID41.UINT8[R_IO_HH]) +#define RSCAN0RMPTR41 (RSCAN0.RMPTR41.UINT32) +#define RSCAN0RMPTR41L (RSCAN0.RMPTR41.UINT16[R_IO_L]) +#define RSCAN0RMPTR41LL (RSCAN0.RMPTR41.UINT8[R_IO_LL]) +#define RSCAN0RMPTR41LH (RSCAN0.RMPTR41.UINT8[R_IO_LH]) +#define RSCAN0RMPTR41H (RSCAN0.RMPTR41.UINT16[R_IO_H]) +#define RSCAN0RMPTR41HL (RSCAN0.RMPTR41.UINT8[R_IO_HL]) +#define RSCAN0RMPTR41HH (RSCAN0.RMPTR41.UINT8[R_IO_HH]) +#define RSCAN0RMDF041 (RSCAN0.RMDF041.UINT32) +#define RSCAN0RMDF041L (RSCAN0.RMDF041.UINT16[R_IO_L]) +#define RSCAN0RMDF041LL (RSCAN0.RMDF041.UINT8[R_IO_LL]) +#define RSCAN0RMDF041LH (RSCAN0.RMDF041.UINT8[R_IO_LH]) +#define RSCAN0RMDF041H (RSCAN0.RMDF041.UINT16[R_IO_H]) +#define RSCAN0RMDF041HL (RSCAN0.RMDF041.UINT8[R_IO_HL]) +#define RSCAN0RMDF041HH (RSCAN0.RMDF041.UINT8[R_IO_HH]) +#define RSCAN0RMDF141 (RSCAN0.RMDF141.UINT32) +#define RSCAN0RMDF141L (RSCAN0.RMDF141.UINT16[R_IO_L]) +#define RSCAN0RMDF141LL (RSCAN0.RMDF141.UINT8[R_IO_LL]) +#define RSCAN0RMDF141LH (RSCAN0.RMDF141.UINT8[R_IO_LH]) +#define RSCAN0RMDF141H (RSCAN0.RMDF141.UINT16[R_IO_H]) +#define RSCAN0RMDF141HL (RSCAN0.RMDF141.UINT8[R_IO_HL]) +#define RSCAN0RMDF141HH (RSCAN0.RMDF141.UINT8[R_IO_HH]) +#define RSCAN0RMID42 (RSCAN0.RMID42.UINT32) +#define RSCAN0RMID42L (RSCAN0.RMID42.UINT16[R_IO_L]) +#define RSCAN0RMID42LL (RSCAN0.RMID42.UINT8[R_IO_LL]) +#define RSCAN0RMID42LH (RSCAN0.RMID42.UINT8[R_IO_LH]) +#define RSCAN0RMID42H (RSCAN0.RMID42.UINT16[R_IO_H]) +#define RSCAN0RMID42HL (RSCAN0.RMID42.UINT8[R_IO_HL]) +#define RSCAN0RMID42HH (RSCAN0.RMID42.UINT8[R_IO_HH]) +#define RSCAN0RMPTR42 (RSCAN0.RMPTR42.UINT32) +#define RSCAN0RMPTR42L (RSCAN0.RMPTR42.UINT16[R_IO_L]) +#define RSCAN0RMPTR42LL (RSCAN0.RMPTR42.UINT8[R_IO_LL]) +#define RSCAN0RMPTR42LH (RSCAN0.RMPTR42.UINT8[R_IO_LH]) +#define RSCAN0RMPTR42H (RSCAN0.RMPTR42.UINT16[R_IO_H]) +#define RSCAN0RMPTR42HL (RSCAN0.RMPTR42.UINT8[R_IO_HL]) +#define RSCAN0RMPTR42HH (RSCAN0.RMPTR42.UINT8[R_IO_HH]) +#define RSCAN0RMDF042 (RSCAN0.RMDF042.UINT32) +#define RSCAN0RMDF042L (RSCAN0.RMDF042.UINT16[R_IO_L]) +#define RSCAN0RMDF042LL (RSCAN0.RMDF042.UINT8[R_IO_LL]) +#define RSCAN0RMDF042LH (RSCAN0.RMDF042.UINT8[R_IO_LH]) +#define RSCAN0RMDF042H (RSCAN0.RMDF042.UINT16[R_IO_H]) +#define RSCAN0RMDF042HL (RSCAN0.RMDF042.UINT8[R_IO_HL]) +#define RSCAN0RMDF042HH (RSCAN0.RMDF042.UINT8[R_IO_HH]) +#define RSCAN0RMDF142 (RSCAN0.RMDF142.UINT32) +#define RSCAN0RMDF142L (RSCAN0.RMDF142.UINT16[R_IO_L]) +#define RSCAN0RMDF142LL (RSCAN0.RMDF142.UINT8[R_IO_LL]) +#define RSCAN0RMDF142LH (RSCAN0.RMDF142.UINT8[R_IO_LH]) +#define RSCAN0RMDF142H (RSCAN0.RMDF142.UINT16[R_IO_H]) +#define RSCAN0RMDF142HL (RSCAN0.RMDF142.UINT8[R_IO_HL]) +#define RSCAN0RMDF142HH (RSCAN0.RMDF142.UINT8[R_IO_HH]) +#define RSCAN0RMID43 (RSCAN0.RMID43.UINT32) +#define RSCAN0RMID43L (RSCAN0.RMID43.UINT16[R_IO_L]) +#define RSCAN0RMID43LL (RSCAN0.RMID43.UINT8[R_IO_LL]) +#define RSCAN0RMID43LH (RSCAN0.RMID43.UINT8[R_IO_LH]) +#define RSCAN0RMID43H (RSCAN0.RMID43.UINT16[R_IO_H]) +#define RSCAN0RMID43HL (RSCAN0.RMID43.UINT8[R_IO_HL]) +#define RSCAN0RMID43HH (RSCAN0.RMID43.UINT8[R_IO_HH]) +#define RSCAN0RMPTR43 (RSCAN0.RMPTR43.UINT32) +#define RSCAN0RMPTR43L (RSCAN0.RMPTR43.UINT16[R_IO_L]) +#define RSCAN0RMPTR43LL (RSCAN0.RMPTR43.UINT8[R_IO_LL]) +#define RSCAN0RMPTR43LH (RSCAN0.RMPTR43.UINT8[R_IO_LH]) +#define RSCAN0RMPTR43H (RSCAN0.RMPTR43.UINT16[R_IO_H]) +#define RSCAN0RMPTR43HL (RSCAN0.RMPTR43.UINT8[R_IO_HL]) +#define RSCAN0RMPTR43HH (RSCAN0.RMPTR43.UINT8[R_IO_HH]) +#define RSCAN0RMDF043 (RSCAN0.RMDF043.UINT32) +#define RSCAN0RMDF043L (RSCAN0.RMDF043.UINT16[R_IO_L]) +#define RSCAN0RMDF043LL (RSCAN0.RMDF043.UINT8[R_IO_LL]) +#define RSCAN0RMDF043LH (RSCAN0.RMDF043.UINT8[R_IO_LH]) +#define RSCAN0RMDF043H (RSCAN0.RMDF043.UINT16[R_IO_H]) +#define RSCAN0RMDF043HL (RSCAN0.RMDF043.UINT8[R_IO_HL]) +#define RSCAN0RMDF043HH (RSCAN0.RMDF043.UINT8[R_IO_HH]) +#define RSCAN0RMDF143 (RSCAN0.RMDF143.UINT32) +#define RSCAN0RMDF143L (RSCAN0.RMDF143.UINT16[R_IO_L]) +#define RSCAN0RMDF143LL (RSCAN0.RMDF143.UINT8[R_IO_LL]) +#define RSCAN0RMDF143LH (RSCAN0.RMDF143.UINT8[R_IO_LH]) +#define RSCAN0RMDF143H (RSCAN0.RMDF143.UINT16[R_IO_H]) +#define RSCAN0RMDF143HL (RSCAN0.RMDF143.UINT8[R_IO_HL]) +#define RSCAN0RMDF143HH (RSCAN0.RMDF143.UINT8[R_IO_HH]) +#define RSCAN0RMID44 (RSCAN0.RMID44.UINT32) +#define RSCAN0RMID44L (RSCAN0.RMID44.UINT16[R_IO_L]) +#define RSCAN0RMID44LL (RSCAN0.RMID44.UINT8[R_IO_LL]) +#define RSCAN0RMID44LH (RSCAN0.RMID44.UINT8[R_IO_LH]) +#define RSCAN0RMID44H (RSCAN0.RMID44.UINT16[R_IO_H]) +#define RSCAN0RMID44HL (RSCAN0.RMID44.UINT8[R_IO_HL]) +#define RSCAN0RMID44HH (RSCAN0.RMID44.UINT8[R_IO_HH]) +#define RSCAN0RMPTR44 (RSCAN0.RMPTR44.UINT32) +#define RSCAN0RMPTR44L (RSCAN0.RMPTR44.UINT16[R_IO_L]) +#define RSCAN0RMPTR44LL (RSCAN0.RMPTR44.UINT8[R_IO_LL]) +#define RSCAN0RMPTR44LH (RSCAN0.RMPTR44.UINT8[R_IO_LH]) +#define RSCAN0RMPTR44H (RSCAN0.RMPTR44.UINT16[R_IO_H]) +#define RSCAN0RMPTR44HL (RSCAN0.RMPTR44.UINT8[R_IO_HL]) +#define RSCAN0RMPTR44HH (RSCAN0.RMPTR44.UINT8[R_IO_HH]) +#define RSCAN0RMDF044 (RSCAN0.RMDF044.UINT32) +#define RSCAN0RMDF044L (RSCAN0.RMDF044.UINT16[R_IO_L]) +#define RSCAN0RMDF044LL (RSCAN0.RMDF044.UINT8[R_IO_LL]) +#define RSCAN0RMDF044LH (RSCAN0.RMDF044.UINT8[R_IO_LH]) +#define RSCAN0RMDF044H (RSCAN0.RMDF044.UINT16[R_IO_H]) +#define RSCAN0RMDF044HL (RSCAN0.RMDF044.UINT8[R_IO_HL]) +#define RSCAN0RMDF044HH (RSCAN0.RMDF044.UINT8[R_IO_HH]) +#define RSCAN0RMDF144 (RSCAN0.RMDF144.UINT32) +#define RSCAN0RMDF144L (RSCAN0.RMDF144.UINT16[R_IO_L]) +#define RSCAN0RMDF144LL (RSCAN0.RMDF144.UINT8[R_IO_LL]) +#define RSCAN0RMDF144LH (RSCAN0.RMDF144.UINT8[R_IO_LH]) +#define RSCAN0RMDF144H (RSCAN0.RMDF144.UINT16[R_IO_H]) +#define RSCAN0RMDF144HL (RSCAN0.RMDF144.UINT8[R_IO_HL]) +#define RSCAN0RMDF144HH (RSCAN0.RMDF144.UINT8[R_IO_HH]) +#define RSCAN0RMID45 (RSCAN0.RMID45.UINT32) +#define RSCAN0RMID45L (RSCAN0.RMID45.UINT16[R_IO_L]) +#define RSCAN0RMID45LL (RSCAN0.RMID45.UINT8[R_IO_LL]) +#define RSCAN0RMID45LH (RSCAN0.RMID45.UINT8[R_IO_LH]) +#define RSCAN0RMID45H (RSCAN0.RMID45.UINT16[R_IO_H]) +#define RSCAN0RMID45HL (RSCAN0.RMID45.UINT8[R_IO_HL]) +#define RSCAN0RMID45HH (RSCAN0.RMID45.UINT8[R_IO_HH]) +#define RSCAN0RMPTR45 (RSCAN0.RMPTR45.UINT32) +#define RSCAN0RMPTR45L (RSCAN0.RMPTR45.UINT16[R_IO_L]) +#define RSCAN0RMPTR45LL (RSCAN0.RMPTR45.UINT8[R_IO_LL]) +#define RSCAN0RMPTR45LH (RSCAN0.RMPTR45.UINT8[R_IO_LH]) +#define RSCAN0RMPTR45H (RSCAN0.RMPTR45.UINT16[R_IO_H]) +#define RSCAN0RMPTR45HL (RSCAN0.RMPTR45.UINT8[R_IO_HL]) +#define RSCAN0RMPTR45HH (RSCAN0.RMPTR45.UINT8[R_IO_HH]) +#define RSCAN0RMDF045 (RSCAN0.RMDF045.UINT32) +#define RSCAN0RMDF045L (RSCAN0.RMDF045.UINT16[R_IO_L]) +#define RSCAN0RMDF045LL (RSCAN0.RMDF045.UINT8[R_IO_LL]) +#define RSCAN0RMDF045LH (RSCAN0.RMDF045.UINT8[R_IO_LH]) +#define RSCAN0RMDF045H (RSCAN0.RMDF045.UINT16[R_IO_H]) +#define RSCAN0RMDF045HL (RSCAN0.RMDF045.UINT8[R_IO_HL]) +#define RSCAN0RMDF045HH (RSCAN0.RMDF045.UINT8[R_IO_HH]) +#define RSCAN0RMDF145 (RSCAN0.RMDF145.UINT32) +#define RSCAN0RMDF145L (RSCAN0.RMDF145.UINT16[R_IO_L]) +#define RSCAN0RMDF145LL (RSCAN0.RMDF145.UINT8[R_IO_LL]) +#define RSCAN0RMDF145LH (RSCAN0.RMDF145.UINT8[R_IO_LH]) +#define RSCAN0RMDF145H (RSCAN0.RMDF145.UINT16[R_IO_H]) +#define RSCAN0RMDF145HL (RSCAN0.RMDF145.UINT8[R_IO_HL]) +#define RSCAN0RMDF145HH (RSCAN0.RMDF145.UINT8[R_IO_HH]) +#define RSCAN0RMID46 (RSCAN0.RMID46.UINT32) +#define RSCAN0RMID46L (RSCAN0.RMID46.UINT16[R_IO_L]) +#define RSCAN0RMID46LL (RSCAN0.RMID46.UINT8[R_IO_LL]) +#define RSCAN0RMID46LH (RSCAN0.RMID46.UINT8[R_IO_LH]) +#define RSCAN0RMID46H (RSCAN0.RMID46.UINT16[R_IO_H]) +#define RSCAN0RMID46HL (RSCAN0.RMID46.UINT8[R_IO_HL]) +#define RSCAN0RMID46HH (RSCAN0.RMID46.UINT8[R_IO_HH]) +#define RSCAN0RMPTR46 (RSCAN0.RMPTR46.UINT32) +#define RSCAN0RMPTR46L (RSCAN0.RMPTR46.UINT16[R_IO_L]) +#define RSCAN0RMPTR46LL (RSCAN0.RMPTR46.UINT8[R_IO_LL]) +#define RSCAN0RMPTR46LH (RSCAN0.RMPTR46.UINT8[R_IO_LH]) +#define RSCAN0RMPTR46H (RSCAN0.RMPTR46.UINT16[R_IO_H]) +#define RSCAN0RMPTR46HL (RSCAN0.RMPTR46.UINT8[R_IO_HL]) +#define RSCAN0RMPTR46HH (RSCAN0.RMPTR46.UINT8[R_IO_HH]) +#define RSCAN0RMDF046 (RSCAN0.RMDF046.UINT32) +#define RSCAN0RMDF046L (RSCAN0.RMDF046.UINT16[R_IO_L]) +#define RSCAN0RMDF046LL (RSCAN0.RMDF046.UINT8[R_IO_LL]) +#define RSCAN0RMDF046LH (RSCAN0.RMDF046.UINT8[R_IO_LH]) +#define RSCAN0RMDF046H (RSCAN0.RMDF046.UINT16[R_IO_H]) +#define RSCAN0RMDF046HL (RSCAN0.RMDF046.UINT8[R_IO_HL]) +#define RSCAN0RMDF046HH (RSCAN0.RMDF046.UINT8[R_IO_HH]) +#define RSCAN0RMDF146 (RSCAN0.RMDF146.UINT32) +#define RSCAN0RMDF146L (RSCAN0.RMDF146.UINT16[R_IO_L]) +#define RSCAN0RMDF146LL (RSCAN0.RMDF146.UINT8[R_IO_LL]) +#define RSCAN0RMDF146LH (RSCAN0.RMDF146.UINT8[R_IO_LH]) +#define RSCAN0RMDF146H (RSCAN0.RMDF146.UINT16[R_IO_H]) +#define RSCAN0RMDF146HL (RSCAN0.RMDF146.UINT8[R_IO_HL]) +#define RSCAN0RMDF146HH (RSCAN0.RMDF146.UINT8[R_IO_HH]) +#define RSCAN0RMID47 (RSCAN0.RMID47.UINT32) +#define RSCAN0RMID47L (RSCAN0.RMID47.UINT16[R_IO_L]) +#define RSCAN0RMID47LL (RSCAN0.RMID47.UINT8[R_IO_LL]) +#define RSCAN0RMID47LH (RSCAN0.RMID47.UINT8[R_IO_LH]) +#define RSCAN0RMID47H (RSCAN0.RMID47.UINT16[R_IO_H]) +#define RSCAN0RMID47HL (RSCAN0.RMID47.UINT8[R_IO_HL]) +#define RSCAN0RMID47HH (RSCAN0.RMID47.UINT8[R_IO_HH]) +#define RSCAN0RMPTR47 (RSCAN0.RMPTR47.UINT32) +#define RSCAN0RMPTR47L (RSCAN0.RMPTR47.UINT16[R_IO_L]) +#define RSCAN0RMPTR47LL (RSCAN0.RMPTR47.UINT8[R_IO_LL]) +#define RSCAN0RMPTR47LH (RSCAN0.RMPTR47.UINT8[R_IO_LH]) +#define RSCAN0RMPTR47H (RSCAN0.RMPTR47.UINT16[R_IO_H]) +#define RSCAN0RMPTR47HL (RSCAN0.RMPTR47.UINT8[R_IO_HL]) +#define RSCAN0RMPTR47HH (RSCAN0.RMPTR47.UINT8[R_IO_HH]) +#define RSCAN0RMDF047 (RSCAN0.RMDF047.UINT32) +#define RSCAN0RMDF047L (RSCAN0.RMDF047.UINT16[R_IO_L]) +#define RSCAN0RMDF047LL (RSCAN0.RMDF047.UINT8[R_IO_LL]) +#define RSCAN0RMDF047LH (RSCAN0.RMDF047.UINT8[R_IO_LH]) +#define RSCAN0RMDF047H (RSCAN0.RMDF047.UINT16[R_IO_H]) +#define RSCAN0RMDF047HL (RSCAN0.RMDF047.UINT8[R_IO_HL]) +#define RSCAN0RMDF047HH (RSCAN0.RMDF047.UINT8[R_IO_HH]) +#define RSCAN0RMDF147 (RSCAN0.RMDF147.UINT32) +#define RSCAN0RMDF147L (RSCAN0.RMDF147.UINT16[R_IO_L]) +#define RSCAN0RMDF147LL (RSCAN0.RMDF147.UINT8[R_IO_LL]) +#define RSCAN0RMDF147LH (RSCAN0.RMDF147.UINT8[R_IO_LH]) +#define RSCAN0RMDF147H (RSCAN0.RMDF147.UINT16[R_IO_H]) +#define RSCAN0RMDF147HL (RSCAN0.RMDF147.UINT8[R_IO_HL]) +#define RSCAN0RMDF147HH (RSCAN0.RMDF147.UINT8[R_IO_HH]) +#define RSCAN0RMID48 (RSCAN0.RMID48.UINT32) +#define RSCAN0RMID48L (RSCAN0.RMID48.UINT16[R_IO_L]) +#define RSCAN0RMID48LL (RSCAN0.RMID48.UINT8[R_IO_LL]) +#define RSCAN0RMID48LH (RSCAN0.RMID48.UINT8[R_IO_LH]) +#define RSCAN0RMID48H (RSCAN0.RMID48.UINT16[R_IO_H]) +#define RSCAN0RMID48HL (RSCAN0.RMID48.UINT8[R_IO_HL]) +#define RSCAN0RMID48HH (RSCAN0.RMID48.UINT8[R_IO_HH]) +#define RSCAN0RMPTR48 (RSCAN0.RMPTR48.UINT32) +#define RSCAN0RMPTR48L (RSCAN0.RMPTR48.UINT16[R_IO_L]) +#define RSCAN0RMPTR48LL (RSCAN0.RMPTR48.UINT8[R_IO_LL]) +#define RSCAN0RMPTR48LH (RSCAN0.RMPTR48.UINT8[R_IO_LH]) +#define RSCAN0RMPTR48H (RSCAN0.RMPTR48.UINT16[R_IO_H]) +#define RSCAN0RMPTR48HL (RSCAN0.RMPTR48.UINT8[R_IO_HL]) +#define RSCAN0RMPTR48HH (RSCAN0.RMPTR48.UINT8[R_IO_HH]) +#define RSCAN0RMDF048 (RSCAN0.RMDF048.UINT32) +#define RSCAN0RMDF048L (RSCAN0.RMDF048.UINT16[R_IO_L]) +#define RSCAN0RMDF048LL (RSCAN0.RMDF048.UINT8[R_IO_LL]) +#define RSCAN0RMDF048LH (RSCAN0.RMDF048.UINT8[R_IO_LH]) +#define RSCAN0RMDF048H (RSCAN0.RMDF048.UINT16[R_IO_H]) +#define RSCAN0RMDF048HL (RSCAN0.RMDF048.UINT8[R_IO_HL]) +#define RSCAN0RMDF048HH (RSCAN0.RMDF048.UINT8[R_IO_HH]) +#define RSCAN0RMDF148 (RSCAN0.RMDF148.UINT32) +#define RSCAN0RMDF148L (RSCAN0.RMDF148.UINT16[R_IO_L]) +#define RSCAN0RMDF148LL (RSCAN0.RMDF148.UINT8[R_IO_LL]) +#define RSCAN0RMDF148LH (RSCAN0.RMDF148.UINT8[R_IO_LH]) +#define RSCAN0RMDF148H (RSCAN0.RMDF148.UINT16[R_IO_H]) +#define RSCAN0RMDF148HL (RSCAN0.RMDF148.UINT8[R_IO_HL]) +#define RSCAN0RMDF148HH (RSCAN0.RMDF148.UINT8[R_IO_HH]) +#define RSCAN0RMID49 (RSCAN0.RMID49.UINT32) +#define RSCAN0RMID49L (RSCAN0.RMID49.UINT16[R_IO_L]) +#define RSCAN0RMID49LL (RSCAN0.RMID49.UINT8[R_IO_LL]) +#define RSCAN0RMID49LH (RSCAN0.RMID49.UINT8[R_IO_LH]) +#define RSCAN0RMID49H (RSCAN0.RMID49.UINT16[R_IO_H]) +#define RSCAN0RMID49HL (RSCAN0.RMID49.UINT8[R_IO_HL]) +#define RSCAN0RMID49HH (RSCAN0.RMID49.UINT8[R_IO_HH]) +#define RSCAN0RMPTR49 (RSCAN0.RMPTR49.UINT32) +#define RSCAN0RMPTR49L (RSCAN0.RMPTR49.UINT16[R_IO_L]) +#define RSCAN0RMPTR49LL (RSCAN0.RMPTR49.UINT8[R_IO_LL]) +#define RSCAN0RMPTR49LH (RSCAN0.RMPTR49.UINT8[R_IO_LH]) +#define RSCAN0RMPTR49H (RSCAN0.RMPTR49.UINT16[R_IO_H]) +#define RSCAN0RMPTR49HL (RSCAN0.RMPTR49.UINT8[R_IO_HL]) +#define RSCAN0RMPTR49HH (RSCAN0.RMPTR49.UINT8[R_IO_HH]) +#define RSCAN0RMDF049 (RSCAN0.RMDF049.UINT32) +#define RSCAN0RMDF049L (RSCAN0.RMDF049.UINT16[R_IO_L]) +#define RSCAN0RMDF049LL (RSCAN0.RMDF049.UINT8[R_IO_LL]) +#define RSCAN0RMDF049LH (RSCAN0.RMDF049.UINT8[R_IO_LH]) +#define RSCAN0RMDF049H (RSCAN0.RMDF049.UINT16[R_IO_H]) +#define RSCAN0RMDF049HL (RSCAN0.RMDF049.UINT8[R_IO_HL]) +#define RSCAN0RMDF049HH (RSCAN0.RMDF049.UINT8[R_IO_HH]) +#define RSCAN0RMDF149 (RSCAN0.RMDF149.UINT32) +#define RSCAN0RMDF149L (RSCAN0.RMDF149.UINT16[R_IO_L]) +#define RSCAN0RMDF149LL (RSCAN0.RMDF149.UINT8[R_IO_LL]) +#define RSCAN0RMDF149LH (RSCAN0.RMDF149.UINT8[R_IO_LH]) +#define RSCAN0RMDF149H (RSCAN0.RMDF149.UINT16[R_IO_H]) +#define RSCAN0RMDF149HL (RSCAN0.RMDF149.UINT8[R_IO_HL]) +#define RSCAN0RMDF149HH (RSCAN0.RMDF149.UINT8[R_IO_HH]) +#define RSCAN0RMID50 (RSCAN0.RMID50.UINT32) +#define RSCAN0RMID50L (RSCAN0.RMID50.UINT16[R_IO_L]) +#define RSCAN0RMID50LL (RSCAN0.RMID50.UINT8[R_IO_LL]) +#define RSCAN0RMID50LH (RSCAN0.RMID50.UINT8[R_IO_LH]) +#define RSCAN0RMID50H (RSCAN0.RMID50.UINT16[R_IO_H]) +#define RSCAN0RMID50HL (RSCAN0.RMID50.UINT8[R_IO_HL]) +#define RSCAN0RMID50HH (RSCAN0.RMID50.UINT8[R_IO_HH]) +#define RSCAN0RMPTR50 (RSCAN0.RMPTR50.UINT32) +#define RSCAN0RMPTR50L (RSCAN0.RMPTR50.UINT16[R_IO_L]) +#define RSCAN0RMPTR50LL (RSCAN0.RMPTR50.UINT8[R_IO_LL]) +#define RSCAN0RMPTR50LH (RSCAN0.RMPTR50.UINT8[R_IO_LH]) +#define RSCAN0RMPTR50H (RSCAN0.RMPTR50.UINT16[R_IO_H]) +#define RSCAN0RMPTR50HL (RSCAN0.RMPTR50.UINT8[R_IO_HL]) +#define RSCAN0RMPTR50HH (RSCAN0.RMPTR50.UINT8[R_IO_HH]) +#define RSCAN0RMDF050 (RSCAN0.RMDF050.UINT32) +#define RSCAN0RMDF050L (RSCAN0.RMDF050.UINT16[R_IO_L]) +#define RSCAN0RMDF050LL (RSCAN0.RMDF050.UINT8[R_IO_LL]) +#define RSCAN0RMDF050LH (RSCAN0.RMDF050.UINT8[R_IO_LH]) +#define RSCAN0RMDF050H (RSCAN0.RMDF050.UINT16[R_IO_H]) +#define RSCAN0RMDF050HL (RSCAN0.RMDF050.UINT8[R_IO_HL]) +#define RSCAN0RMDF050HH (RSCAN0.RMDF050.UINT8[R_IO_HH]) +#define RSCAN0RMDF150 (RSCAN0.RMDF150.UINT32) +#define RSCAN0RMDF150L (RSCAN0.RMDF150.UINT16[R_IO_L]) +#define RSCAN0RMDF150LL (RSCAN0.RMDF150.UINT8[R_IO_LL]) +#define RSCAN0RMDF150LH (RSCAN0.RMDF150.UINT8[R_IO_LH]) +#define RSCAN0RMDF150H (RSCAN0.RMDF150.UINT16[R_IO_H]) +#define RSCAN0RMDF150HL (RSCAN0.RMDF150.UINT8[R_IO_HL]) +#define RSCAN0RMDF150HH (RSCAN0.RMDF150.UINT8[R_IO_HH]) +#define RSCAN0RMID51 (RSCAN0.RMID51.UINT32) +#define RSCAN0RMID51L (RSCAN0.RMID51.UINT16[R_IO_L]) +#define RSCAN0RMID51LL (RSCAN0.RMID51.UINT8[R_IO_LL]) +#define RSCAN0RMID51LH (RSCAN0.RMID51.UINT8[R_IO_LH]) +#define RSCAN0RMID51H (RSCAN0.RMID51.UINT16[R_IO_H]) +#define RSCAN0RMID51HL (RSCAN0.RMID51.UINT8[R_IO_HL]) +#define RSCAN0RMID51HH (RSCAN0.RMID51.UINT8[R_IO_HH]) +#define RSCAN0RMPTR51 (RSCAN0.RMPTR51.UINT32) +#define RSCAN0RMPTR51L (RSCAN0.RMPTR51.UINT16[R_IO_L]) +#define RSCAN0RMPTR51LL (RSCAN0.RMPTR51.UINT8[R_IO_LL]) +#define RSCAN0RMPTR51LH (RSCAN0.RMPTR51.UINT8[R_IO_LH]) +#define RSCAN0RMPTR51H (RSCAN0.RMPTR51.UINT16[R_IO_H]) +#define RSCAN0RMPTR51HL (RSCAN0.RMPTR51.UINT8[R_IO_HL]) +#define RSCAN0RMPTR51HH (RSCAN0.RMPTR51.UINT8[R_IO_HH]) +#define RSCAN0RMDF051 (RSCAN0.RMDF051.UINT32) +#define RSCAN0RMDF051L (RSCAN0.RMDF051.UINT16[R_IO_L]) +#define RSCAN0RMDF051LL (RSCAN0.RMDF051.UINT8[R_IO_LL]) +#define RSCAN0RMDF051LH (RSCAN0.RMDF051.UINT8[R_IO_LH]) +#define RSCAN0RMDF051H (RSCAN0.RMDF051.UINT16[R_IO_H]) +#define RSCAN0RMDF051HL (RSCAN0.RMDF051.UINT8[R_IO_HL]) +#define RSCAN0RMDF051HH (RSCAN0.RMDF051.UINT8[R_IO_HH]) +#define RSCAN0RMDF151 (RSCAN0.RMDF151.UINT32) +#define RSCAN0RMDF151L (RSCAN0.RMDF151.UINT16[R_IO_L]) +#define RSCAN0RMDF151LL (RSCAN0.RMDF151.UINT8[R_IO_LL]) +#define RSCAN0RMDF151LH (RSCAN0.RMDF151.UINT8[R_IO_LH]) +#define RSCAN0RMDF151H (RSCAN0.RMDF151.UINT16[R_IO_H]) +#define RSCAN0RMDF151HL (RSCAN0.RMDF151.UINT8[R_IO_HL]) +#define RSCAN0RMDF151HH (RSCAN0.RMDF151.UINT8[R_IO_HH]) +#define RSCAN0RMID52 (RSCAN0.RMID52.UINT32) +#define RSCAN0RMID52L (RSCAN0.RMID52.UINT16[R_IO_L]) +#define RSCAN0RMID52LL (RSCAN0.RMID52.UINT8[R_IO_LL]) +#define RSCAN0RMID52LH (RSCAN0.RMID52.UINT8[R_IO_LH]) +#define RSCAN0RMID52H (RSCAN0.RMID52.UINT16[R_IO_H]) +#define RSCAN0RMID52HL (RSCAN0.RMID52.UINT8[R_IO_HL]) +#define RSCAN0RMID52HH (RSCAN0.RMID52.UINT8[R_IO_HH]) +#define RSCAN0RMPTR52 (RSCAN0.RMPTR52.UINT32) +#define RSCAN0RMPTR52L (RSCAN0.RMPTR52.UINT16[R_IO_L]) +#define RSCAN0RMPTR52LL (RSCAN0.RMPTR52.UINT8[R_IO_LL]) +#define RSCAN0RMPTR52LH (RSCAN0.RMPTR52.UINT8[R_IO_LH]) +#define RSCAN0RMPTR52H (RSCAN0.RMPTR52.UINT16[R_IO_H]) +#define RSCAN0RMPTR52HL (RSCAN0.RMPTR52.UINT8[R_IO_HL]) +#define RSCAN0RMPTR52HH (RSCAN0.RMPTR52.UINT8[R_IO_HH]) +#define RSCAN0RMDF052 (RSCAN0.RMDF052.UINT32) +#define RSCAN0RMDF052L (RSCAN0.RMDF052.UINT16[R_IO_L]) +#define RSCAN0RMDF052LL (RSCAN0.RMDF052.UINT8[R_IO_LL]) +#define RSCAN0RMDF052LH (RSCAN0.RMDF052.UINT8[R_IO_LH]) +#define RSCAN0RMDF052H (RSCAN0.RMDF052.UINT16[R_IO_H]) +#define RSCAN0RMDF052HL (RSCAN0.RMDF052.UINT8[R_IO_HL]) +#define RSCAN0RMDF052HH (RSCAN0.RMDF052.UINT8[R_IO_HH]) +#define RSCAN0RMDF152 (RSCAN0.RMDF152.UINT32) +#define RSCAN0RMDF152L (RSCAN0.RMDF152.UINT16[R_IO_L]) +#define RSCAN0RMDF152LL (RSCAN0.RMDF152.UINT8[R_IO_LL]) +#define RSCAN0RMDF152LH (RSCAN0.RMDF152.UINT8[R_IO_LH]) +#define RSCAN0RMDF152H (RSCAN0.RMDF152.UINT16[R_IO_H]) +#define RSCAN0RMDF152HL (RSCAN0.RMDF152.UINT8[R_IO_HL]) +#define RSCAN0RMDF152HH (RSCAN0.RMDF152.UINT8[R_IO_HH]) +#define RSCAN0RMID53 (RSCAN0.RMID53.UINT32) +#define RSCAN0RMID53L (RSCAN0.RMID53.UINT16[R_IO_L]) +#define RSCAN0RMID53LL (RSCAN0.RMID53.UINT8[R_IO_LL]) +#define RSCAN0RMID53LH (RSCAN0.RMID53.UINT8[R_IO_LH]) +#define RSCAN0RMID53H (RSCAN0.RMID53.UINT16[R_IO_H]) +#define RSCAN0RMID53HL (RSCAN0.RMID53.UINT8[R_IO_HL]) +#define RSCAN0RMID53HH (RSCAN0.RMID53.UINT8[R_IO_HH]) +#define RSCAN0RMPTR53 (RSCAN0.RMPTR53.UINT32) +#define RSCAN0RMPTR53L (RSCAN0.RMPTR53.UINT16[R_IO_L]) +#define RSCAN0RMPTR53LL (RSCAN0.RMPTR53.UINT8[R_IO_LL]) +#define RSCAN0RMPTR53LH (RSCAN0.RMPTR53.UINT8[R_IO_LH]) +#define RSCAN0RMPTR53H (RSCAN0.RMPTR53.UINT16[R_IO_H]) +#define RSCAN0RMPTR53HL (RSCAN0.RMPTR53.UINT8[R_IO_HL]) +#define RSCAN0RMPTR53HH (RSCAN0.RMPTR53.UINT8[R_IO_HH]) +#define RSCAN0RMDF053 (RSCAN0.RMDF053.UINT32) +#define RSCAN0RMDF053L (RSCAN0.RMDF053.UINT16[R_IO_L]) +#define RSCAN0RMDF053LL (RSCAN0.RMDF053.UINT8[R_IO_LL]) +#define RSCAN0RMDF053LH (RSCAN0.RMDF053.UINT8[R_IO_LH]) +#define RSCAN0RMDF053H (RSCAN0.RMDF053.UINT16[R_IO_H]) +#define RSCAN0RMDF053HL (RSCAN0.RMDF053.UINT8[R_IO_HL]) +#define RSCAN0RMDF053HH (RSCAN0.RMDF053.UINT8[R_IO_HH]) +#define RSCAN0RMDF153 (RSCAN0.RMDF153.UINT32) +#define RSCAN0RMDF153L (RSCAN0.RMDF153.UINT16[R_IO_L]) +#define RSCAN0RMDF153LL (RSCAN0.RMDF153.UINT8[R_IO_LL]) +#define RSCAN0RMDF153LH (RSCAN0.RMDF153.UINT8[R_IO_LH]) +#define RSCAN0RMDF153H (RSCAN0.RMDF153.UINT16[R_IO_H]) +#define RSCAN0RMDF153HL (RSCAN0.RMDF153.UINT8[R_IO_HL]) +#define RSCAN0RMDF153HH (RSCAN0.RMDF153.UINT8[R_IO_HH]) +#define RSCAN0RMID54 (RSCAN0.RMID54.UINT32) +#define RSCAN0RMID54L (RSCAN0.RMID54.UINT16[R_IO_L]) +#define RSCAN0RMID54LL (RSCAN0.RMID54.UINT8[R_IO_LL]) +#define RSCAN0RMID54LH (RSCAN0.RMID54.UINT8[R_IO_LH]) +#define RSCAN0RMID54H (RSCAN0.RMID54.UINT16[R_IO_H]) +#define RSCAN0RMID54HL (RSCAN0.RMID54.UINT8[R_IO_HL]) +#define RSCAN0RMID54HH (RSCAN0.RMID54.UINT8[R_IO_HH]) +#define RSCAN0RMPTR54 (RSCAN0.RMPTR54.UINT32) +#define RSCAN0RMPTR54L (RSCAN0.RMPTR54.UINT16[R_IO_L]) +#define RSCAN0RMPTR54LL (RSCAN0.RMPTR54.UINT8[R_IO_LL]) +#define RSCAN0RMPTR54LH (RSCAN0.RMPTR54.UINT8[R_IO_LH]) +#define RSCAN0RMPTR54H (RSCAN0.RMPTR54.UINT16[R_IO_H]) +#define RSCAN0RMPTR54HL (RSCAN0.RMPTR54.UINT8[R_IO_HL]) +#define RSCAN0RMPTR54HH (RSCAN0.RMPTR54.UINT8[R_IO_HH]) +#define RSCAN0RMDF054 (RSCAN0.RMDF054.UINT32) +#define RSCAN0RMDF054L (RSCAN0.RMDF054.UINT16[R_IO_L]) +#define RSCAN0RMDF054LL (RSCAN0.RMDF054.UINT8[R_IO_LL]) +#define RSCAN0RMDF054LH (RSCAN0.RMDF054.UINT8[R_IO_LH]) +#define RSCAN0RMDF054H (RSCAN0.RMDF054.UINT16[R_IO_H]) +#define RSCAN0RMDF054HL (RSCAN0.RMDF054.UINT8[R_IO_HL]) +#define RSCAN0RMDF054HH (RSCAN0.RMDF054.UINT8[R_IO_HH]) +#define RSCAN0RMDF154 (RSCAN0.RMDF154.UINT32) +#define RSCAN0RMDF154L (RSCAN0.RMDF154.UINT16[R_IO_L]) +#define RSCAN0RMDF154LL (RSCAN0.RMDF154.UINT8[R_IO_LL]) +#define RSCAN0RMDF154LH (RSCAN0.RMDF154.UINT8[R_IO_LH]) +#define RSCAN0RMDF154H (RSCAN0.RMDF154.UINT16[R_IO_H]) +#define RSCAN0RMDF154HL (RSCAN0.RMDF154.UINT8[R_IO_HL]) +#define RSCAN0RMDF154HH (RSCAN0.RMDF154.UINT8[R_IO_HH]) +#define RSCAN0RMID55 (RSCAN0.RMID55.UINT32) +#define RSCAN0RMID55L (RSCAN0.RMID55.UINT16[R_IO_L]) +#define RSCAN0RMID55LL (RSCAN0.RMID55.UINT8[R_IO_LL]) +#define RSCAN0RMID55LH (RSCAN0.RMID55.UINT8[R_IO_LH]) +#define RSCAN0RMID55H (RSCAN0.RMID55.UINT16[R_IO_H]) +#define RSCAN0RMID55HL (RSCAN0.RMID55.UINT8[R_IO_HL]) +#define RSCAN0RMID55HH (RSCAN0.RMID55.UINT8[R_IO_HH]) +#define RSCAN0RMPTR55 (RSCAN0.RMPTR55.UINT32) +#define RSCAN0RMPTR55L (RSCAN0.RMPTR55.UINT16[R_IO_L]) +#define RSCAN0RMPTR55LL (RSCAN0.RMPTR55.UINT8[R_IO_LL]) +#define RSCAN0RMPTR55LH (RSCAN0.RMPTR55.UINT8[R_IO_LH]) +#define RSCAN0RMPTR55H (RSCAN0.RMPTR55.UINT16[R_IO_H]) +#define RSCAN0RMPTR55HL (RSCAN0.RMPTR55.UINT8[R_IO_HL]) +#define RSCAN0RMPTR55HH (RSCAN0.RMPTR55.UINT8[R_IO_HH]) +#define RSCAN0RMDF055 (RSCAN0.RMDF055.UINT32) +#define RSCAN0RMDF055L (RSCAN0.RMDF055.UINT16[R_IO_L]) +#define RSCAN0RMDF055LL (RSCAN0.RMDF055.UINT8[R_IO_LL]) +#define RSCAN0RMDF055LH (RSCAN0.RMDF055.UINT8[R_IO_LH]) +#define RSCAN0RMDF055H (RSCAN0.RMDF055.UINT16[R_IO_H]) +#define RSCAN0RMDF055HL (RSCAN0.RMDF055.UINT8[R_IO_HL]) +#define RSCAN0RMDF055HH (RSCAN0.RMDF055.UINT8[R_IO_HH]) +#define RSCAN0RMDF155 (RSCAN0.RMDF155.UINT32) +#define RSCAN0RMDF155L (RSCAN0.RMDF155.UINT16[R_IO_L]) +#define RSCAN0RMDF155LL (RSCAN0.RMDF155.UINT8[R_IO_LL]) +#define RSCAN0RMDF155LH (RSCAN0.RMDF155.UINT8[R_IO_LH]) +#define RSCAN0RMDF155H (RSCAN0.RMDF155.UINT16[R_IO_H]) +#define RSCAN0RMDF155HL (RSCAN0.RMDF155.UINT8[R_IO_HL]) +#define RSCAN0RMDF155HH (RSCAN0.RMDF155.UINT8[R_IO_HH]) +#define RSCAN0RMID56 (RSCAN0.RMID56.UINT32) +#define RSCAN0RMID56L (RSCAN0.RMID56.UINT16[R_IO_L]) +#define RSCAN0RMID56LL (RSCAN0.RMID56.UINT8[R_IO_LL]) +#define RSCAN0RMID56LH (RSCAN0.RMID56.UINT8[R_IO_LH]) +#define RSCAN0RMID56H (RSCAN0.RMID56.UINT16[R_IO_H]) +#define RSCAN0RMID56HL (RSCAN0.RMID56.UINT8[R_IO_HL]) +#define RSCAN0RMID56HH (RSCAN0.RMID56.UINT8[R_IO_HH]) +#define RSCAN0RMPTR56 (RSCAN0.RMPTR56.UINT32) +#define RSCAN0RMPTR56L (RSCAN0.RMPTR56.UINT16[R_IO_L]) +#define RSCAN0RMPTR56LL (RSCAN0.RMPTR56.UINT8[R_IO_LL]) +#define RSCAN0RMPTR56LH (RSCAN0.RMPTR56.UINT8[R_IO_LH]) +#define RSCAN0RMPTR56H (RSCAN0.RMPTR56.UINT16[R_IO_H]) +#define RSCAN0RMPTR56HL (RSCAN0.RMPTR56.UINT8[R_IO_HL]) +#define RSCAN0RMPTR56HH (RSCAN0.RMPTR56.UINT8[R_IO_HH]) +#define RSCAN0RMDF056 (RSCAN0.RMDF056.UINT32) +#define RSCAN0RMDF056L (RSCAN0.RMDF056.UINT16[R_IO_L]) +#define RSCAN0RMDF056LL (RSCAN0.RMDF056.UINT8[R_IO_LL]) +#define RSCAN0RMDF056LH (RSCAN0.RMDF056.UINT8[R_IO_LH]) +#define RSCAN0RMDF056H (RSCAN0.RMDF056.UINT16[R_IO_H]) +#define RSCAN0RMDF056HL (RSCAN0.RMDF056.UINT8[R_IO_HL]) +#define RSCAN0RMDF056HH (RSCAN0.RMDF056.UINT8[R_IO_HH]) +#define RSCAN0RMDF156 (RSCAN0.RMDF156.UINT32) +#define RSCAN0RMDF156L (RSCAN0.RMDF156.UINT16[R_IO_L]) +#define RSCAN0RMDF156LL (RSCAN0.RMDF156.UINT8[R_IO_LL]) +#define RSCAN0RMDF156LH (RSCAN0.RMDF156.UINT8[R_IO_LH]) +#define RSCAN0RMDF156H (RSCAN0.RMDF156.UINT16[R_IO_H]) +#define RSCAN0RMDF156HL (RSCAN0.RMDF156.UINT8[R_IO_HL]) +#define RSCAN0RMDF156HH (RSCAN0.RMDF156.UINT8[R_IO_HH]) +#define RSCAN0RMID57 (RSCAN0.RMID57.UINT32) +#define RSCAN0RMID57L (RSCAN0.RMID57.UINT16[R_IO_L]) +#define RSCAN0RMID57LL (RSCAN0.RMID57.UINT8[R_IO_LL]) +#define RSCAN0RMID57LH (RSCAN0.RMID57.UINT8[R_IO_LH]) +#define RSCAN0RMID57H (RSCAN0.RMID57.UINT16[R_IO_H]) +#define RSCAN0RMID57HL (RSCAN0.RMID57.UINT8[R_IO_HL]) +#define RSCAN0RMID57HH (RSCAN0.RMID57.UINT8[R_IO_HH]) +#define RSCAN0RMPTR57 (RSCAN0.RMPTR57.UINT32) +#define RSCAN0RMPTR57L (RSCAN0.RMPTR57.UINT16[R_IO_L]) +#define RSCAN0RMPTR57LL (RSCAN0.RMPTR57.UINT8[R_IO_LL]) +#define RSCAN0RMPTR57LH (RSCAN0.RMPTR57.UINT8[R_IO_LH]) +#define RSCAN0RMPTR57H (RSCAN0.RMPTR57.UINT16[R_IO_H]) +#define RSCAN0RMPTR57HL (RSCAN0.RMPTR57.UINT8[R_IO_HL]) +#define RSCAN0RMPTR57HH (RSCAN0.RMPTR57.UINT8[R_IO_HH]) +#define RSCAN0RMDF057 (RSCAN0.RMDF057.UINT32) +#define RSCAN0RMDF057L (RSCAN0.RMDF057.UINT16[R_IO_L]) +#define RSCAN0RMDF057LL (RSCAN0.RMDF057.UINT8[R_IO_LL]) +#define RSCAN0RMDF057LH (RSCAN0.RMDF057.UINT8[R_IO_LH]) +#define RSCAN0RMDF057H (RSCAN0.RMDF057.UINT16[R_IO_H]) +#define RSCAN0RMDF057HL (RSCAN0.RMDF057.UINT8[R_IO_HL]) +#define RSCAN0RMDF057HH (RSCAN0.RMDF057.UINT8[R_IO_HH]) +#define RSCAN0RMDF157 (RSCAN0.RMDF157.UINT32) +#define RSCAN0RMDF157L (RSCAN0.RMDF157.UINT16[R_IO_L]) +#define RSCAN0RMDF157LL (RSCAN0.RMDF157.UINT8[R_IO_LL]) +#define RSCAN0RMDF157LH (RSCAN0.RMDF157.UINT8[R_IO_LH]) +#define RSCAN0RMDF157H (RSCAN0.RMDF157.UINT16[R_IO_H]) +#define RSCAN0RMDF157HL (RSCAN0.RMDF157.UINT8[R_IO_HL]) +#define RSCAN0RMDF157HH (RSCAN0.RMDF157.UINT8[R_IO_HH]) +#define RSCAN0RMID58 (RSCAN0.RMID58.UINT32) +#define RSCAN0RMID58L (RSCAN0.RMID58.UINT16[R_IO_L]) +#define RSCAN0RMID58LL (RSCAN0.RMID58.UINT8[R_IO_LL]) +#define RSCAN0RMID58LH (RSCAN0.RMID58.UINT8[R_IO_LH]) +#define RSCAN0RMID58H (RSCAN0.RMID58.UINT16[R_IO_H]) +#define RSCAN0RMID58HL (RSCAN0.RMID58.UINT8[R_IO_HL]) +#define RSCAN0RMID58HH (RSCAN0.RMID58.UINT8[R_IO_HH]) +#define RSCAN0RMPTR58 (RSCAN0.RMPTR58.UINT32) +#define RSCAN0RMPTR58L (RSCAN0.RMPTR58.UINT16[R_IO_L]) +#define RSCAN0RMPTR58LL (RSCAN0.RMPTR58.UINT8[R_IO_LL]) +#define RSCAN0RMPTR58LH (RSCAN0.RMPTR58.UINT8[R_IO_LH]) +#define RSCAN0RMPTR58H (RSCAN0.RMPTR58.UINT16[R_IO_H]) +#define RSCAN0RMPTR58HL (RSCAN0.RMPTR58.UINT8[R_IO_HL]) +#define RSCAN0RMPTR58HH (RSCAN0.RMPTR58.UINT8[R_IO_HH]) +#define RSCAN0RMDF058 (RSCAN0.RMDF058.UINT32) +#define RSCAN0RMDF058L (RSCAN0.RMDF058.UINT16[R_IO_L]) +#define RSCAN0RMDF058LL (RSCAN0.RMDF058.UINT8[R_IO_LL]) +#define RSCAN0RMDF058LH (RSCAN0.RMDF058.UINT8[R_IO_LH]) +#define RSCAN0RMDF058H (RSCAN0.RMDF058.UINT16[R_IO_H]) +#define RSCAN0RMDF058HL (RSCAN0.RMDF058.UINT8[R_IO_HL]) +#define RSCAN0RMDF058HH (RSCAN0.RMDF058.UINT8[R_IO_HH]) +#define RSCAN0RMDF158 (RSCAN0.RMDF158.UINT32) +#define RSCAN0RMDF158L (RSCAN0.RMDF158.UINT16[R_IO_L]) +#define RSCAN0RMDF158LL (RSCAN0.RMDF158.UINT8[R_IO_LL]) +#define RSCAN0RMDF158LH (RSCAN0.RMDF158.UINT8[R_IO_LH]) +#define RSCAN0RMDF158H (RSCAN0.RMDF158.UINT16[R_IO_H]) +#define RSCAN0RMDF158HL (RSCAN0.RMDF158.UINT8[R_IO_HL]) +#define RSCAN0RMDF158HH (RSCAN0.RMDF158.UINT8[R_IO_HH]) +#define RSCAN0RMID59 (RSCAN0.RMID59.UINT32) +#define RSCAN0RMID59L (RSCAN0.RMID59.UINT16[R_IO_L]) +#define RSCAN0RMID59LL (RSCAN0.RMID59.UINT8[R_IO_LL]) +#define RSCAN0RMID59LH (RSCAN0.RMID59.UINT8[R_IO_LH]) +#define RSCAN0RMID59H (RSCAN0.RMID59.UINT16[R_IO_H]) +#define RSCAN0RMID59HL (RSCAN0.RMID59.UINT8[R_IO_HL]) +#define RSCAN0RMID59HH (RSCAN0.RMID59.UINT8[R_IO_HH]) +#define RSCAN0RMPTR59 (RSCAN0.RMPTR59.UINT32) +#define RSCAN0RMPTR59L (RSCAN0.RMPTR59.UINT16[R_IO_L]) +#define RSCAN0RMPTR59LL (RSCAN0.RMPTR59.UINT8[R_IO_LL]) +#define RSCAN0RMPTR59LH (RSCAN0.RMPTR59.UINT8[R_IO_LH]) +#define RSCAN0RMPTR59H (RSCAN0.RMPTR59.UINT16[R_IO_H]) +#define RSCAN0RMPTR59HL (RSCAN0.RMPTR59.UINT8[R_IO_HL]) +#define RSCAN0RMPTR59HH (RSCAN0.RMPTR59.UINT8[R_IO_HH]) +#define RSCAN0RMDF059 (RSCAN0.RMDF059.UINT32) +#define RSCAN0RMDF059L (RSCAN0.RMDF059.UINT16[R_IO_L]) +#define RSCAN0RMDF059LL (RSCAN0.RMDF059.UINT8[R_IO_LL]) +#define RSCAN0RMDF059LH (RSCAN0.RMDF059.UINT8[R_IO_LH]) +#define RSCAN0RMDF059H (RSCAN0.RMDF059.UINT16[R_IO_H]) +#define RSCAN0RMDF059HL (RSCAN0.RMDF059.UINT8[R_IO_HL]) +#define RSCAN0RMDF059HH (RSCAN0.RMDF059.UINT8[R_IO_HH]) +#define RSCAN0RMDF159 (RSCAN0.RMDF159.UINT32) +#define RSCAN0RMDF159L (RSCAN0.RMDF159.UINT16[R_IO_L]) +#define RSCAN0RMDF159LL (RSCAN0.RMDF159.UINT8[R_IO_LL]) +#define RSCAN0RMDF159LH (RSCAN0.RMDF159.UINT8[R_IO_LH]) +#define RSCAN0RMDF159H (RSCAN0.RMDF159.UINT16[R_IO_H]) +#define RSCAN0RMDF159HL (RSCAN0.RMDF159.UINT8[R_IO_HL]) +#define RSCAN0RMDF159HH (RSCAN0.RMDF159.UINT8[R_IO_HH]) +#define RSCAN0RMID60 (RSCAN0.RMID60.UINT32) +#define RSCAN0RMID60L (RSCAN0.RMID60.UINT16[R_IO_L]) +#define RSCAN0RMID60LL (RSCAN0.RMID60.UINT8[R_IO_LL]) +#define RSCAN0RMID60LH (RSCAN0.RMID60.UINT8[R_IO_LH]) +#define RSCAN0RMID60H (RSCAN0.RMID60.UINT16[R_IO_H]) +#define RSCAN0RMID60HL (RSCAN0.RMID60.UINT8[R_IO_HL]) +#define RSCAN0RMID60HH (RSCAN0.RMID60.UINT8[R_IO_HH]) +#define RSCAN0RMPTR60 (RSCAN0.RMPTR60.UINT32) +#define RSCAN0RMPTR60L (RSCAN0.RMPTR60.UINT16[R_IO_L]) +#define RSCAN0RMPTR60LL (RSCAN0.RMPTR60.UINT8[R_IO_LL]) +#define RSCAN0RMPTR60LH (RSCAN0.RMPTR60.UINT8[R_IO_LH]) +#define RSCAN0RMPTR60H (RSCAN0.RMPTR60.UINT16[R_IO_H]) +#define RSCAN0RMPTR60HL (RSCAN0.RMPTR60.UINT8[R_IO_HL]) +#define RSCAN0RMPTR60HH (RSCAN0.RMPTR60.UINT8[R_IO_HH]) +#define RSCAN0RMDF060 (RSCAN0.RMDF060.UINT32) +#define RSCAN0RMDF060L (RSCAN0.RMDF060.UINT16[R_IO_L]) +#define RSCAN0RMDF060LL (RSCAN0.RMDF060.UINT8[R_IO_LL]) +#define RSCAN0RMDF060LH (RSCAN0.RMDF060.UINT8[R_IO_LH]) +#define RSCAN0RMDF060H (RSCAN0.RMDF060.UINT16[R_IO_H]) +#define RSCAN0RMDF060HL (RSCAN0.RMDF060.UINT8[R_IO_HL]) +#define RSCAN0RMDF060HH (RSCAN0.RMDF060.UINT8[R_IO_HH]) +#define RSCAN0RMDF160 (RSCAN0.RMDF160.UINT32) +#define RSCAN0RMDF160L (RSCAN0.RMDF160.UINT16[R_IO_L]) +#define RSCAN0RMDF160LL (RSCAN0.RMDF160.UINT8[R_IO_LL]) +#define RSCAN0RMDF160LH (RSCAN0.RMDF160.UINT8[R_IO_LH]) +#define RSCAN0RMDF160H (RSCAN0.RMDF160.UINT16[R_IO_H]) +#define RSCAN0RMDF160HL (RSCAN0.RMDF160.UINT8[R_IO_HL]) +#define RSCAN0RMDF160HH (RSCAN0.RMDF160.UINT8[R_IO_HH]) +#define RSCAN0RMID61 (RSCAN0.RMID61.UINT32) +#define RSCAN0RMID61L (RSCAN0.RMID61.UINT16[R_IO_L]) +#define RSCAN0RMID61LL (RSCAN0.RMID61.UINT8[R_IO_LL]) +#define RSCAN0RMID61LH (RSCAN0.RMID61.UINT8[R_IO_LH]) +#define RSCAN0RMID61H (RSCAN0.RMID61.UINT16[R_IO_H]) +#define RSCAN0RMID61HL (RSCAN0.RMID61.UINT8[R_IO_HL]) +#define RSCAN0RMID61HH (RSCAN0.RMID61.UINT8[R_IO_HH]) +#define RSCAN0RMPTR61 (RSCAN0.RMPTR61.UINT32) +#define RSCAN0RMPTR61L (RSCAN0.RMPTR61.UINT16[R_IO_L]) +#define RSCAN0RMPTR61LL (RSCAN0.RMPTR61.UINT8[R_IO_LL]) +#define RSCAN0RMPTR61LH (RSCAN0.RMPTR61.UINT8[R_IO_LH]) +#define RSCAN0RMPTR61H (RSCAN0.RMPTR61.UINT16[R_IO_H]) +#define RSCAN0RMPTR61HL (RSCAN0.RMPTR61.UINT8[R_IO_HL]) +#define RSCAN0RMPTR61HH (RSCAN0.RMPTR61.UINT8[R_IO_HH]) +#define RSCAN0RMDF061 (RSCAN0.RMDF061.UINT32) +#define RSCAN0RMDF061L (RSCAN0.RMDF061.UINT16[R_IO_L]) +#define RSCAN0RMDF061LL (RSCAN0.RMDF061.UINT8[R_IO_LL]) +#define RSCAN0RMDF061LH (RSCAN0.RMDF061.UINT8[R_IO_LH]) +#define RSCAN0RMDF061H (RSCAN0.RMDF061.UINT16[R_IO_H]) +#define RSCAN0RMDF061HL (RSCAN0.RMDF061.UINT8[R_IO_HL]) +#define RSCAN0RMDF061HH (RSCAN0.RMDF061.UINT8[R_IO_HH]) +#define RSCAN0RMDF161 (RSCAN0.RMDF161.UINT32) +#define RSCAN0RMDF161L (RSCAN0.RMDF161.UINT16[R_IO_L]) +#define RSCAN0RMDF161LL (RSCAN0.RMDF161.UINT8[R_IO_LL]) +#define RSCAN0RMDF161LH (RSCAN0.RMDF161.UINT8[R_IO_LH]) +#define RSCAN0RMDF161H (RSCAN0.RMDF161.UINT16[R_IO_H]) +#define RSCAN0RMDF161HL (RSCAN0.RMDF161.UINT8[R_IO_HL]) +#define RSCAN0RMDF161HH (RSCAN0.RMDF161.UINT8[R_IO_HH]) +#define RSCAN0RMID62 (RSCAN0.RMID62.UINT32) +#define RSCAN0RMID62L (RSCAN0.RMID62.UINT16[R_IO_L]) +#define RSCAN0RMID62LL (RSCAN0.RMID62.UINT8[R_IO_LL]) +#define RSCAN0RMID62LH (RSCAN0.RMID62.UINT8[R_IO_LH]) +#define RSCAN0RMID62H (RSCAN0.RMID62.UINT16[R_IO_H]) +#define RSCAN0RMID62HL (RSCAN0.RMID62.UINT8[R_IO_HL]) +#define RSCAN0RMID62HH (RSCAN0.RMID62.UINT8[R_IO_HH]) +#define RSCAN0RMPTR62 (RSCAN0.RMPTR62.UINT32) +#define RSCAN0RMPTR62L (RSCAN0.RMPTR62.UINT16[R_IO_L]) +#define RSCAN0RMPTR62LL (RSCAN0.RMPTR62.UINT8[R_IO_LL]) +#define RSCAN0RMPTR62LH (RSCAN0.RMPTR62.UINT8[R_IO_LH]) +#define RSCAN0RMPTR62H (RSCAN0.RMPTR62.UINT16[R_IO_H]) +#define RSCAN0RMPTR62HL (RSCAN0.RMPTR62.UINT8[R_IO_HL]) +#define RSCAN0RMPTR62HH (RSCAN0.RMPTR62.UINT8[R_IO_HH]) +#define RSCAN0RMDF062 (RSCAN0.RMDF062.UINT32) +#define RSCAN0RMDF062L (RSCAN0.RMDF062.UINT16[R_IO_L]) +#define RSCAN0RMDF062LL (RSCAN0.RMDF062.UINT8[R_IO_LL]) +#define RSCAN0RMDF062LH (RSCAN0.RMDF062.UINT8[R_IO_LH]) +#define RSCAN0RMDF062H (RSCAN0.RMDF062.UINT16[R_IO_H]) +#define RSCAN0RMDF062HL (RSCAN0.RMDF062.UINT8[R_IO_HL]) +#define RSCAN0RMDF062HH (RSCAN0.RMDF062.UINT8[R_IO_HH]) +#define RSCAN0RMDF162 (RSCAN0.RMDF162.UINT32) +#define RSCAN0RMDF162L (RSCAN0.RMDF162.UINT16[R_IO_L]) +#define RSCAN0RMDF162LL (RSCAN0.RMDF162.UINT8[R_IO_LL]) +#define RSCAN0RMDF162LH (RSCAN0.RMDF162.UINT8[R_IO_LH]) +#define RSCAN0RMDF162H (RSCAN0.RMDF162.UINT16[R_IO_H]) +#define RSCAN0RMDF162HL (RSCAN0.RMDF162.UINT8[R_IO_HL]) +#define RSCAN0RMDF162HH (RSCAN0.RMDF162.UINT8[R_IO_HH]) +#define RSCAN0RMID63 (RSCAN0.RMID63.UINT32) +#define RSCAN0RMID63L (RSCAN0.RMID63.UINT16[R_IO_L]) +#define RSCAN0RMID63LL (RSCAN0.RMID63.UINT8[R_IO_LL]) +#define RSCAN0RMID63LH (RSCAN0.RMID63.UINT8[R_IO_LH]) +#define RSCAN0RMID63H (RSCAN0.RMID63.UINT16[R_IO_H]) +#define RSCAN0RMID63HL (RSCAN0.RMID63.UINT8[R_IO_HL]) +#define RSCAN0RMID63HH (RSCAN0.RMID63.UINT8[R_IO_HH]) +#define RSCAN0RMPTR63 (RSCAN0.RMPTR63.UINT32) +#define RSCAN0RMPTR63L (RSCAN0.RMPTR63.UINT16[R_IO_L]) +#define RSCAN0RMPTR63LL (RSCAN0.RMPTR63.UINT8[R_IO_LL]) +#define RSCAN0RMPTR63LH (RSCAN0.RMPTR63.UINT8[R_IO_LH]) +#define RSCAN0RMPTR63H (RSCAN0.RMPTR63.UINT16[R_IO_H]) +#define RSCAN0RMPTR63HL (RSCAN0.RMPTR63.UINT8[R_IO_HL]) +#define RSCAN0RMPTR63HH (RSCAN0.RMPTR63.UINT8[R_IO_HH]) +#define RSCAN0RMDF063 (RSCAN0.RMDF063.UINT32) +#define RSCAN0RMDF063L (RSCAN0.RMDF063.UINT16[R_IO_L]) +#define RSCAN0RMDF063LL (RSCAN0.RMDF063.UINT8[R_IO_LL]) +#define RSCAN0RMDF063LH (RSCAN0.RMDF063.UINT8[R_IO_LH]) +#define RSCAN0RMDF063H (RSCAN0.RMDF063.UINT16[R_IO_H]) +#define RSCAN0RMDF063HL (RSCAN0.RMDF063.UINT8[R_IO_HL]) +#define RSCAN0RMDF063HH (RSCAN0.RMDF063.UINT8[R_IO_HH]) +#define RSCAN0RMDF163 (RSCAN0.RMDF163.UINT32) +#define RSCAN0RMDF163L (RSCAN0.RMDF163.UINT16[R_IO_L]) +#define RSCAN0RMDF163LL (RSCAN0.RMDF163.UINT8[R_IO_LL]) +#define RSCAN0RMDF163LH (RSCAN0.RMDF163.UINT8[R_IO_LH]) +#define RSCAN0RMDF163H (RSCAN0.RMDF163.UINT16[R_IO_H]) +#define RSCAN0RMDF163HL (RSCAN0.RMDF163.UINT8[R_IO_HL]) +#define RSCAN0RMDF163HH (RSCAN0.RMDF163.UINT8[R_IO_HH]) +#define RSCAN0RMID64 (RSCAN0.RMID64.UINT32) +#define RSCAN0RMID64L (RSCAN0.RMID64.UINT16[R_IO_L]) +#define RSCAN0RMID64LL (RSCAN0.RMID64.UINT8[R_IO_LL]) +#define RSCAN0RMID64LH (RSCAN0.RMID64.UINT8[R_IO_LH]) +#define RSCAN0RMID64H (RSCAN0.RMID64.UINT16[R_IO_H]) +#define RSCAN0RMID64HL (RSCAN0.RMID64.UINT8[R_IO_HL]) +#define RSCAN0RMID64HH (RSCAN0.RMID64.UINT8[R_IO_HH]) +#define RSCAN0RMPTR64 (RSCAN0.RMPTR64.UINT32) +#define RSCAN0RMPTR64L (RSCAN0.RMPTR64.UINT16[R_IO_L]) +#define RSCAN0RMPTR64LL (RSCAN0.RMPTR64.UINT8[R_IO_LL]) +#define RSCAN0RMPTR64LH (RSCAN0.RMPTR64.UINT8[R_IO_LH]) +#define RSCAN0RMPTR64H (RSCAN0.RMPTR64.UINT16[R_IO_H]) +#define RSCAN0RMPTR64HL (RSCAN0.RMPTR64.UINT8[R_IO_HL]) +#define RSCAN0RMPTR64HH (RSCAN0.RMPTR64.UINT8[R_IO_HH]) +#define RSCAN0RMDF064 (RSCAN0.RMDF064.UINT32) +#define RSCAN0RMDF064L (RSCAN0.RMDF064.UINT16[R_IO_L]) +#define RSCAN0RMDF064LL (RSCAN0.RMDF064.UINT8[R_IO_LL]) +#define RSCAN0RMDF064LH (RSCAN0.RMDF064.UINT8[R_IO_LH]) +#define RSCAN0RMDF064H (RSCAN0.RMDF064.UINT16[R_IO_H]) +#define RSCAN0RMDF064HL (RSCAN0.RMDF064.UINT8[R_IO_HL]) +#define RSCAN0RMDF064HH (RSCAN0.RMDF064.UINT8[R_IO_HH]) +#define RSCAN0RMDF164 (RSCAN0.RMDF164.UINT32) +#define RSCAN0RMDF164L (RSCAN0.RMDF164.UINT16[R_IO_L]) +#define RSCAN0RMDF164LL (RSCAN0.RMDF164.UINT8[R_IO_LL]) +#define RSCAN0RMDF164LH (RSCAN0.RMDF164.UINT8[R_IO_LH]) +#define RSCAN0RMDF164H (RSCAN0.RMDF164.UINT16[R_IO_H]) +#define RSCAN0RMDF164HL (RSCAN0.RMDF164.UINT8[R_IO_HL]) +#define RSCAN0RMDF164HH (RSCAN0.RMDF164.UINT8[R_IO_HH]) +#define RSCAN0RMID65 (RSCAN0.RMID65.UINT32) +#define RSCAN0RMID65L (RSCAN0.RMID65.UINT16[R_IO_L]) +#define RSCAN0RMID65LL (RSCAN0.RMID65.UINT8[R_IO_LL]) +#define RSCAN0RMID65LH (RSCAN0.RMID65.UINT8[R_IO_LH]) +#define RSCAN0RMID65H (RSCAN0.RMID65.UINT16[R_IO_H]) +#define RSCAN0RMID65HL (RSCAN0.RMID65.UINT8[R_IO_HL]) +#define RSCAN0RMID65HH (RSCAN0.RMID65.UINT8[R_IO_HH]) +#define RSCAN0RMPTR65 (RSCAN0.RMPTR65.UINT32) +#define RSCAN0RMPTR65L (RSCAN0.RMPTR65.UINT16[R_IO_L]) +#define RSCAN0RMPTR65LL (RSCAN0.RMPTR65.UINT8[R_IO_LL]) +#define RSCAN0RMPTR65LH (RSCAN0.RMPTR65.UINT8[R_IO_LH]) +#define RSCAN0RMPTR65H (RSCAN0.RMPTR65.UINT16[R_IO_H]) +#define RSCAN0RMPTR65HL (RSCAN0.RMPTR65.UINT8[R_IO_HL]) +#define RSCAN0RMPTR65HH (RSCAN0.RMPTR65.UINT8[R_IO_HH]) +#define RSCAN0RMDF065 (RSCAN0.RMDF065.UINT32) +#define RSCAN0RMDF065L (RSCAN0.RMDF065.UINT16[R_IO_L]) +#define RSCAN0RMDF065LL (RSCAN0.RMDF065.UINT8[R_IO_LL]) +#define RSCAN0RMDF065LH (RSCAN0.RMDF065.UINT8[R_IO_LH]) +#define RSCAN0RMDF065H (RSCAN0.RMDF065.UINT16[R_IO_H]) +#define RSCAN0RMDF065HL (RSCAN0.RMDF065.UINT8[R_IO_HL]) +#define RSCAN0RMDF065HH (RSCAN0.RMDF065.UINT8[R_IO_HH]) +#define RSCAN0RMDF165 (RSCAN0.RMDF165.UINT32) +#define RSCAN0RMDF165L (RSCAN0.RMDF165.UINT16[R_IO_L]) +#define RSCAN0RMDF165LL (RSCAN0.RMDF165.UINT8[R_IO_LL]) +#define RSCAN0RMDF165LH (RSCAN0.RMDF165.UINT8[R_IO_LH]) +#define RSCAN0RMDF165H (RSCAN0.RMDF165.UINT16[R_IO_H]) +#define RSCAN0RMDF165HL (RSCAN0.RMDF165.UINT8[R_IO_HL]) +#define RSCAN0RMDF165HH (RSCAN0.RMDF165.UINT8[R_IO_HH]) +#define RSCAN0RMID66 (RSCAN0.RMID66.UINT32) +#define RSCAN0RMID66L (RSCAN0.RMID66.UINT16[R_IO_L]) +#define RSCAN0RMID66LL (RSCAN0.RMID66.UINT8[R_IO_LL]) +#define RSCAN0RMID66LH (RSCAN0.RMID66.UINT8[R_IO_LH]) +#define RSCAN0RMID66H (RSCAN0.RMID66.UINT16[R_IO_H]) +#define RSCAN0RMID66HL (RSCAN0.RMID66.UINT8[R_IO_HL]) +#define RSCAN0RMID66HH (RSCAN0.RMID66.UINT8[R_IO_HH]) +#define RSCAN0RMPTR66 (RSCAN0.RMPTR66.UINT32) +#define RSCAN0RMPTR66L (RSCAN0.RMPTR66.UINT16[R_IO_L]) +#define RSCAN0RMPTR66LL (RSCAN0.RMPTR66.UINT8[R_IO_LL]) +#define RSCAN0RMPTR66LH (RSCAN0.RMPTR66.UINT8[R_IO_LH]) +#define RSCAN0RMPTR66H (RSCAN0.RMPTR66.UINT16[R_IO_H]) +#define RSCAN0RMPTR66HL (RSCAN0.RMPTR66.UINT8[R_IO_HL]) +#define RSCAN0RMPTR66HH (RSCAN0.RMPTR66.UINT8[R_IO_HH]) +#define RSCAN0RMDF066 (RSCAN0.RMDF066.UINT32) +#define RSCAN0RMDF066L (RSCAN0.RMDF066.UINT16[R_IO_L]) +#define RSCAN0RMDF066LL (RSCAN0.RMDF066.UINT8[R_IO_LL]) +#define RSCAN0RMDF066LH (RSCAN0.RMDF066.UINT8[R_IO_LH]) +#define RSCAN0RMDF066H (RSCAN0.RMDF066.UINT16[R_IO_H]) +#define RSCAN0RMDF066HL (RSCAN0.RMDF066.UINT8[R_IO_HL]) +#define RSCAN0RMDF066HH (RSCAN0.RMDF066.UINT8[R_IO_HH]) +#define RSCAN0RMDF166 (RSCAN0.RMDF166.UINT32) +#define RSCAN0RMDF166L (RSCAN0.RMDF166.UINT16[R_IO_L]) +#define RSCAN0RMDF166LL (RSCAN0.RMDF166.UINT8[R_IO_LL]) +#define RSCAN0RMDF166LH (RSCAN0.RMDF166.UINT8[R_IO_LH]) +#define RSCAN0RMDF166H (RSCAN0.RMDF166.UINT16[R_IO_H]) +#define RSCAN0RMDF166HL (RSCAN0.RMDF166.UINT8[R_IO_HL]) +#define RSCAN0RMDF166HH (RSCAN0.RMDF166.UINT8[R_IO_HH]) +#define RSCAN0RMID67 (RSCAN0.RMID67.UINT32) +#define RSCAN0RMID67L (RSCAN0.RMID67.UINT16[R_IO_L]) +#define RSCAN0RMID67LL (RSCAN0.RMID67.UINT8[R_IO_LL]) +#define RSCAN0RMID67LH (RSCAN0.RMID67.UINT8[R_IO_LH]) +#define RSCAN0RMID67H (RSCAN0.RMID67.UINT16[R_IO_H]) +#define RSCAN0RMID67HL (RSCAN0.RMID67.UINT8[R_IO_HL]) +#define RSCAN0RMID67HH (RSCAN0.RMID67.UINT8[R_IO_HH]) +#define RSCAN0RMPTR67 (RSCAN0.RMPTR67.UINT32) +#define RSCAN0RMPTR67L (RSCAN0.RMPTR67.UINT16[R_IO_L]) +#define RSCAN0RMPTR67LL (RSCAN0.RMPTR67.UINT8[R_IO_LL]) +#define RSCAN0RMPTR67LH (RSCAN0.RMPTR67.UINT8[R_IO_LH]) +#define RSCAN0RMPTR67H (RSCAN0.RMPTR67.UINT16[R_IO_H]) +#define RSCAN0RMPTR67HL (RSCAN0.RMPTR67.UINT8[R_IO_HL]) +#define RSCAN0RMPTR67HH (RSCAN0.RMPTR67.UINT8[R_IO_HH]) +#define RSCAN0RMDF067 (RSCAN0.RMDF067.UINT32) +#define RSCAN0RMDF067L (RSCAN0.RMDF067.UINT16[R_IO_L]) +#define RSCAN0RMDF067LL (RSCAN0.RMDF067.UINT8[R_IO_LL]) +#define RSCAN0RMDF067LH (RSCAN0.RMDF067.UINT8[R_IO_LH]) +#define RSCAN0RMDF067H (RSCAN0.RMDF067.UINT16[R_IO_H]) +#define RSCAN0RMDF067HL (RSCAN0.RMDF067.UINT8[R_IO_HL]) +#define RSCAN0RMDF067HH (RSCAN0.RMDF067.UINT8[R_IO_HH]) +#define RSCAN0RMDF167 (RSCAN0.RMDF167.UINT32) +#define RSCAN0RMDF167L (RSCAN0.RMDF167.UINT16[R_IO_L]) +#define RSCAN0RMDF167LL (RSCAN0.RMDF167.UINT8[R_IO_LL]) +#define RSCAN0RMDF167LH (RSCAN0.RMDF167.UINT8[R_IO_LH]) +#define RSCAN0RMDF167H (RSCAN0.RMDF167.UINT16[R_IO_H]) +#define RSCAN0RMDF167HL (RSCAN0.RMDF167.UINT8[R_IO_HL]) +#define RSCAN0RMDF167HH (RSCAN0.RMDF167.UINT8[R_IO_HH]) +#define RSCAN0RMID68 (RSCAN0.RMID68.UINT32) +#define RSCAN0RMID68L (RSCAN0.RMID68.UINT16[R_IO_L]) +#define RSCAN0RMID68LL (RSCAN0.RMID68.UINT8[R_IO_LL]) +#define RSCAN0RMID68LH (RSCAN0.RMID68.UINT8[R_IO_LH]) +#define RSCAN0RMID68H (RSCAN0.RMID68.UINT16[R_IO_H]) +#define RSCAN0RMID68HL (RSCAN0.RMID68.UINT8[R_IO_HL]) +#define RSCAN0RMID68HH (RSCAN0.RMID68.UINT8[R_IO_HH]) +#define RSCAN0RMPTR68 (RSCAN0.RMPTR68.UINT32) +#define RSCAN0RMPTR68L (RSCAN0.RMPTR68.UINT16[R_IO_L]) +#define RSCAN0RMPTR68LL (RSCAN0.RMPTR68.UINT8[R_IO_LL]) +#define RSCAN0RMPTR68LH (RSCAN0.RMPTR68.UINT8[R_IO_LH]) +#define RSCAN0RMPTR68H (RSCAN0.RMPTR68.UINT16[R_IO_H]) +#define RSCAN0RMPTR68HL (RSCAN0.RMPTR68.UINT8[R_IO_HL]) +#define RSCAN0RMPTR68HH (RSCAN0.RMPTR68.UINT8[R_IO_HH]) +#define RSCAN0RMDF068 (RSCAN0.RMDF068.UINT32) +#define RSCAN0RMDF068L (RSCAN0.RMDF068.UINT16[R_IO_L]) +#define RSCAN0RMDF068LL (RSCAN0.RMDF068.UINT8[R_IO_LL]) +#define RSCAN0RMDF068LH (RSCAN0.RMDF068.UINT8[R_IO_LH]) +#define RSCAN0RMDF068H (RSCAN0.RMDF068.UINT16[R_IO_H]) +#define RSCAN0RMDF068HL (RSCAN0.RMDF068.UINT8[R_IO_HL]) +#define RSCAN0RMDF068HH (RSCAN0.RMDF068.UINT8[R_IO_HH]) +#define RSCAN0RMDF168 (RSCAN0.RMDF168.UINT32) +#define RSCAN0RMDF168L (RSCAN0.RMDF168.UINT16[R_IO_L]) +#define RSCAN0RMDF168LL (RSCAN0.RMDF168.UINT8[R_IO_LL]) +#define RSCAN0RMDF168LH (RSCAN0.RMDF168.UINT8[R_IO_LH]) +#define RSCAN0RMDF168H (RSCAN0.RMDF168.UINT16[R_IO_H]) +#define RSCAN0RMDF168HL (RSCAN0.RMDF168.UINT8[R_IO_HL]) +#define RSCAN0RMDF168HH (RSCAN0.RMDF168.UINT8[R_IO_HH]) +#define RSCAN0RMID69 (RSCAN0.RMID69.UINT32) +#define RSCAN0RMID69L (RSCAN0.RMID69.UINT16[R_IO_L]) +#define RSCAN0RMID69LL (RSCAN0.RMID69.UINT8[R_IO_LL]) +#define RSCAN0RMID69LH (RSCAN0.RMID69.UINT8[R_IO_LH]) +#define RSCAN0RMID69H (RSCAN0.RMID69.UINT16[R_IO_H]) +#define RSCAN0RMID69HL (RSCAN0.RMID69.UINT8[R_IO_HL]) +#define RSCAN0RMID69HH (RSCAN0.RMID69.UINT8[R_IO_HH]) +#define RSCAN0RMPTR69 (RSCAN0.RMPTR69.UINT32) +#define RSCAN0RMPTR69L (RSCAN0.RMPTR69.UINT16[R_IO_L]) +#define RSCAN0RMPTR69LL (RSCAN0.RMPTR69.UINT8[R_IO_LL]) +#define RSCAN0RMPTR69LH (RSCAN0.RMPTR69.UINT8[R_IO_LH]) +#define RSCAN0RMPTR69H (RSCAN0.RMPTR69.UINT16[R_IO_H]) +#define RSCAN0RMPTR69HL (RSCAN0.RMPTR69.UINT8[R_IO_HL]) +#define RSCAN0RMPTR69HH (RSCAN0.RMPTR69.UINT8[R_IO_HH]) +#define RSCAN0RMDF069 (RSCAN0.RMDF069.UINT32) +#define RSCAN0RMDF069L (RSCAN0.RMDF069.UINT16[R_IO_L]) +#define RSCAN0RMDF069LL (RSCAN0.RMDF069.UINT8[R_IO_LL]) +#define RSCAN0RMDF069LH (RSCAN0.RMDF069.UINT8[R_IO_LH]) +#define RSCAN0RMDF069H (RSCAN0.RMDF069.UINT16[R_IO_H]) +#define RSCAN0RMDF069HL (RSCAN0.RMDF069.UINT8[R_IO_HL]) +#define RSCAN0RMDF069HH (RSCAN0.RMDF069.UINT8[R_IO_HH]) +#define RSCAN0RMDF169 (RSCAN0.RMDF169.UINT32) +#define RSCAN0RMDF169L (RSCAN0.RMDF169.UINT16[R_IO_L]) +#define RSCAN0RMDF169LL (RSCAN0.RMDF169.UINT8[R_IO_LL]) +#define RSCAN0RMDF169LH (RSCAN0.RMDF169.UINT8[R_IO_LH]) +#define RSCAN0RMDF169H (RSCAN0.RMDF169.UINT16[R_IO_H]) +#define RSCAN0RMDF169HL (RSCAN0.RMDF169.UINT8[R_IO_HL]) +#define RSCAN0RMDF169HH (RSCAN0.RMDF169.UINT8[R_IO_HH]) +#define RSCAN0RMID70 (RSCAN0.RMID70.UINT32) +#define RSCAN0RMID70L (RSCAN0.RMID70.UINT16[R_IO_L]) +#define RSCAN0RMID70LL (RSCAN0.RMID70.UINT8[R_IO_LL]) +#define RSCAN0RMID70LH (RSCAN0.RMID70.UINT8[R_IO_LH]) +#define RSCAN0RMID70H (RSCAN0.RMID70.UINT16[R_IO_H]) +#define RSCAN0RMID70HL (RSCAN0.RMID70.UINT8[R_IO_HL]) +#define RSCAN0RMID70HH (RSCAN0.RMID70.UINT8[R_IO_HH]) +#define RSCAN0RMPTR70 (RSCAN0.RMPTR70.UINT32) +#define RSCAN0RMPTR70L (RSCAN0.RMPTR70.UINT16[R_IO_L]) +#define RSCAN0RMPTR70LL (RSCAN0.RMPTR70.UINT8[R_IO_LL]) +#define RSCAN0RMPTR70LH (RSCAN0.RMPTR70.UINT8[R_IO_LH]) +#define RSCAN0RMPTR70H (RSCAN0.RMPTR70.UINT16[R_IO_H]) +#define RSCAN0RMPTR70HL (RSCAN0.RMPTR70.UINT8[R_IO_HL]) +#define RSCAN0RMPTR70HH (RSCAN0.RMPTR70.UINT8[R_IO_HH]) +#define RSCAN0RMDF070 (RSCAN0.RMDF070.UINT32) +#define RSCAN0RMDF070L (RSCAN0.RMDF070.UINT16[R_IO_L]) +#define RSCAN0RMDF070LL (RSCAN0.RMDF070.UINT8[R_IO_LL]) +#define RSCAN0RMDF070LH (RSCAN0.RMDF070.UINT8[R_IO_LH]) +#define RSCAN0RMDF070H (RSCAN0.RMDF070.UINT16[R_IO_H]) +#define RSCAN0RMDF070HL (RSCAN0.RMDF070.UINT8[R_IO_HL]) +#define RSCAN0RMDF070HH (RSCAN0.RMDF070.UINT8[R_IO_HH]) +#define RSCAN0RMDF170 (RSCAN0.RMDF170.UINT32) +#define RSCAN0RMDF170L (RSCAN0.RMDF170.UINT16[R_IO_L]) +#define RSCAN0RMDF170LL (RSCAN0.RMDF170.UINT8[R_IO_LL]) +#define RSCAN0RMDF170LH (RSCAN0.RMDF170.UINT8[R_IO_LH]) +#define RSCAN0RMDF170H (RSCAN0.RMDF170.UINT16[R_IO_H]) +#define RSCAN0RMDF170HL (RSCAN0.RMDF170.UINT8[R_IO_HL]) +#define RSCAN0RMDF170HH (RSCAN0.RMDF170.UINT8[R_IO_HH]) +#define RSCAN0RMID71 (RSCAN0.RMID71.UINT32) +#define RSCAN0RMID71L (RSCAN0.RMID71.UINT16[R_IO_L]) +#define RSCAN0RMID71LL (RSCAN0.RMID71.UINT8[R_IO_LL]) +#define RSCAN0RMID71LH (RSCAN0.RMID71.UINT8[R_IO_LH]) +#define RSCAN0RMID71H (RSCAN0.RMID71.UINT16[R_IO_H]) +#define RSCAN0RMID71HL (RSCAN0.RMID71.UINT8[R_IO_HL]) +#define RSCAN0RMID71HH (RSCAN0.RMID71.UINT8[R_IO_HH]) +#define RSCAN0RMPTR71 (RSCAN0.RMPTR71.UINT32) +#define RSCAN0RMPTR71L (RSCAN0.RMPTR71.UINT16[R_IO_L]) +#define RSCAN0RMPTR71LL (RSCAN0.RMPTR71.UINT8[R_IO_LL]) +#define RSCAN0RMPTR71LH (RSCAN0.RMPTR71.UINT8[R_IO_LH]) +#define RSCAN0RMPTR71H (RSCAN0.RMPTR71.UINT16[R_IO_H]) +#define RSCAN0RMPTR71HL (RSCAN0.RMPTR71.UINT8[R_IO_HL]) +#define RSCAN0RMPTR71HH (RSCAN0.RMPTR71.UINT8[R_IO_HH]) +#define RSCAN0RMDF071 (RSCAN0.RMDF071.UINT32) +#define RSCAN0RMDF071L (RSCAN0.RMDF071.UINT16[R_IO_L]) +#define RSCAN0RMDF071LL (RSCAN0.RMDF071.UINT8[R_IO_LL]) +#define RSCAN0RMDF071LH (RSCAN0.RMDF071.UINT8[R_IO_LH]) +#define RSCAN0RMDF071H (RSCAN0.RMDF071.UINT16[R_IO_H]) +#define RSCAN0RMDF071HL (RSCAN0.RMDF071.UINT8[R_IO_HL]) +#define RSCAN0RMDF071HH (RSCAN0.RMDF071.UINT8[R_IO_HH]) +#define RSCAN0RMDF171 (RSCAN0.RMDF171.UINT32) +#define RSCAN0RMDF171L (RSCAN0.RMDF171.UINT16[R_IO_L]) +#define RSCAN0RMDF171LL (RSCAN0.RMDF171.UINT8[R_IO_LL]) +#define RSCAN0RMDF171LH (RSCAN0.RMDF171.UINT8[R_IO_LH]) +#define RSCAN0RMDF171H (RSCAN0.RMDF171.UINT16[R_IO_H]) +#define RSCAN0RMDF171HL (RSCAN0.RMDF171.UINT8[R_IO_HL]) +#define RSCAN0RMDF171HH (RSCAN0.RMDF171.UINT8[R_IO_HH]) +#define RSCAN0RMID72 (RSCAN0.RMID72.UINT32) +#define RSCAN0RMID72L (RSCAN0.RMID72.UINT16[R_IO_L]) +#define RSCAN0RMID72LL (RSCAN0.RMID72.UINT8[R_IO_LL]) +#define RSCAN0RMID72LH (RSCAN0.RMID72.UINT8[R_IO_LH]) +#define RSCAN0RMID72H (RSCAN0.RMID72.UINT16[R_IO_H]) +#define RSCAN0RMID72HL (RSCAN0.RMID72.UINT8[R_IO_HL]) +#define RSCAN0RMID72HH (RSCAN0.RMID72.UINT8[R_IO_HH]) +#define RSCAN0RMPTR72 (RSCAN0.RMPTR72.UINT32) +#define RSCAN0RMPTR72L (RSCAN0.RMPTR72.UINT16[R_IO_L]) +#define RSCAN0RMPTR72LL (RSCAN0.RMPTR72.UINT8[R_IO_LL]) +#define RSCAN0RMPTR72LH (RSCAN0.RMPTR72.UINT8[R_IO_LH]) +#define RSCAN0RMPTR72H (RSCAN0.RMPTR72.UINT16[R_IO_H]) +#define RSCAN0RMPTR72HL (RSCAN0.RMPTR72.UINT8[R_IO_HL]) +#define RSCAN0RMPTR72HH (RSCAN0.RMPTR72.UINT8[R_IO_HH]) +#define RSCAN0RMDF072 (RSCAN0.RMDF072.UINT32) +#define RSCAN0RMDF072L (RSCAN0.RMDF072.UINT16[R_IO_L]) +#define RSCAN0RMDF072LL (RSCAN0.RMDF072.UINT8[R_IO_LL]) +#define RSCAN0RMDF072LH (RSCAN0.RMDF072.UINT8[R_IO_LH]) +#define RSCAN0RMDF072H (RSCAN0.RMDF072.UINT16[R_IO_H]) +#define RSCAN0RMDF072HL (RSCAN0.RMDF072.UINT8[R_IO_HL]) +#define RSCAN0RMDF072HH (RSCAN0.RMDF072.UINT8[R_IO_HH]) +#define RSCAN0RMDF172 (RSCAN0.RMDF172.UINT32) +#define RSCAN0RMDF172L (RSCAN0.RMDF172.UINT16[R_IO_L]) +#define RSCAN0RMDF172LL (RSCAN0.RMDF172.UINT8[R_IO_LL]) +#define RSCAN0RMDF172LH (RSCAN0.RMDF172.UINT8[R_IO_LH]) +#define RSCAN0RMDF172H (RSCAN0.RMDF172.UINT16[R_IO_H]) +#define RSCAN0RMDF172HL (RSCAN0.RMDF172.UINT8[R_IO_HL]) +#define RSCAN0RMDF172HH (RSCAN0.RMDF172.UINT8[R_IO_HH]) +#define RSCAN0RMID73 (RSCAN0.RMID73.UINT32) +#define RSCAN0RMID73L (RSCAN0.RMID73.UINT16[R_IO_L]) +#define RSCAN0RMID73LL (RSCAN0.RMID73.UINT8[R_IO_LL]) +#define RSCAN0RMID73LH (RSCAN0.RMID73.UINT8[R_IO_LH]) +#define RSCAN0RMID73H (RSCAN0.RMID73.UINT16[R_IO_H]) +#define RSCAN0RMID73HL (RSCAN0.RMID73.UINT8[R_IO_HL]) +#define RSCAN0RMID73HH (RSCAN0.RMID73.UINT8[R_IO_HH]) +#define RSCAN0RMPTR73 (RSCAN0.RMPTR73.UINT32) +#define RSCAN0RMPTR73L (RSCAN0.RMPTR73.UINT16[R_IO_L]) +#define RSCAN0RMPTR73LL (RSCAN0.RMPTR73.UINT8[R_IO_LL]) +#define RSCAN0RMPTR73LH (RSCAN0.RMPTR73.UINT8[R_IO_LH]) +#define RSCAN0RMPTR73H (RSCAN0.RMPTR73.UINT16[R_IO_H]) +#define RSCAN0RMPTR73HL (RSCAN0.RMPTR73.UINT8[R_IO_HL]) +#define RSCAN0RMPTR73HH (RSCAN0.RMPTR73.UINT8[R_IO_HH]) +#define RSCAN0RMDF073 (RSCAN0.RMDF073.UINT32) +#define RSCAN0RMDF073L (RSCAN0.RMDF073.UINT16[R_IO_L]) +#define RSCAN0RMDF073LL (RSCAN0.RMDF073.UINT8[R_IO_LL]) +#define RSCAN0RMDF073LH (RSCAN0.RMDF073.UINT8[R_IO_LH]) +#define RSCAN0RMDF073H (RSCAN0.RMDF073.UINT16[R_IO_H]) +#define RSCAN0RMDF073HL (RSCAN0.RMDF073.UINT8[R_IO_HL]) +#define RSCAN0RMDF073HH (RSCAN0.RMDF073.UINT8[R_IO_HH]) +#define RSCAN0RMDF173 (RSCAN0.RMDF173.UINT32) +#define RSCAN0RMDF173L (RSCAN0.RMDF173.UINT16[R_IO_L]) +#define RSCAN0RMDF173LL (RSCAN0.RMDF173.UINT8[R_IO_LL]) +#define RSCAN0RMDF173LH (RSCAN0.RMDF173.UINT8[R_IO_LH]) +#define RSCAN0RMDF173H (RSCAN0.RMDF173.UINT16[R_IO_H]) +#define RSCAN0RMDF173HL (RSCAN0.RMDF173.UINT8[R_IO_HL]) +#define RSCAN0RMDF173HH (RSCAN0.RMDF173.UINT8[R_IO_HH]) +#define RSCAN0RMID74 (RSCAN0.RMID74.UINT32) +#define RSCAN0RMID74L (RSCAN0.RMID74.UINT16[R_IO_L]) +#define RSCAN0RMID74LL (RSCAN0.RMID74.UINT8[R_IO_LL]) +#define RSCAN0RMID74LH (RSCAN0.RMID74.UINT8[R_IO_LH]) +#define RSCAN0RMID74H (RSCAN0.RMID74.UINT16[R_IO_H]) +#define RSCAN0RMID74HL (RSCAN0.RMID74.UINT8[R_IO_HL]) +#define RSCAN0RMID74HH (RSCAN0.RMID74.UINT8[R_IO_HH]) +#define RSCAN0RMPTR74 (RSCAN0.RMPTR74.UINT32) +#define RSCAN0RMPTR74L (RSCAN0.RMPTR74.UINT16[R_IO_L]) +#define RSCAN0RMPTR74LL (RSCAN0.RMPTR74.UINT8[R_IO_LL]) +#define RSCAN0RMPTR74LH (RSCAN0.RMPTR74.UINT8[R_IO_LH]) +#define RSCAN0RMPTR74H (RSCAN0.RMPTR74.UINT16[R_IO_H]) +#define RSCAN0RMPTR74HL (RSCAN0.RMPTR74.UINT8[R_IO_HL]) +#define RSCAN0RMPTR74HH (RSCAN0.RMPTR74.UINT8[R_IO_HH]) +#define RSCAN0RMDF074 (RSCAN0.RMDF074.UINT32) +#define RSCAN0RMDF074L (RSCAN0.RMDF074.UINT16[R_IO_L]) +#define RSCAN0RMDF074LL (RSCAN0.RMDF074.UINT8[R_IO_LL]) +#define RSCAN0RMDF074LH (RSCAN0.RMDF074.UINT8[R_IO_LH]) +#define RSCAN0RMDF074H (RSCAN0.RMDF074.UINT16[R_IO_H]) +#define RSCAN0RMDF074HL (RSCAN0.RMDF074.UINT8[R_IO_HL]) +#define RSCAN0RMDF074HH (RSCAN0.RMDF074.UINT8[R_IO_HH]) +#define RSCAN0RMDF174 (RSCAN0.RMDF174.UINT32) +#define RSCAN0RMDF174L (RSCAN0.RMDF174.UINT16[R_IO_L]) +#define RSCAN0RMDF174LL (RSCAN0.RMDF174.UINT8[R_IO_LL]) +#define RSCAN0RMDF174LH (RSCAN0.RMDF174.UINT8[R_IO_LH]) +#define RSCAN0RMDF174H (RSCAN0.RMDF174.UINT16[R_IO_H]) +#define RSCAN0RMDF174HL (RSCAN0.RMDF174.UINT8[R_IO_HL]) +#define RSCAN0RMDF174HH (RSCAN0.RMDF174.UINT8[R_IO_HH]) +#define RSCAN0RMID75 (RSCAN0.RMID75.UINT32) +#define RSCAN0RMID75L (RSCAN0.RMID75.UINT16[R_IO_L]) +#define RSCAN0RMID75LL (RSCAN0.RMID75.UINT8[R_IO_LL]) +#define RSCAN0RMID75LH (RSCAN0.RMID75.UINT8[R_IO_LH]) +#define RSCAN0RMID75H (RSCAN0.RMID75.UINT16[R_IO_H]) +#define RSCAN0RMID75HL (RSCAN0.RMID75.UINT8[R_IO_HL]) +#define RSCAN0RMID75HH (RSCAN0.RMID75.UINT8[R_IO_HH]) +#define RSCAN0RMPTR75 (RSCAN0.RMPTR75.UINT32) +#define RSCAN0RMPTR75L (RSCAN0.RMPTR75.UINT16[R_IO_L]) +#define RSCAN0RMPTR75LL (RSCAN0.RMPTR75.UINT8[R_IO_LL]) +#define RSCAN0RMPTR75LH (RSCAN0.RMPTR75.UINT8[R_IO_LH]) +#define RSCAN0RMPTR75H (RSCAN0.RMPTR75.UINT16[R_IO_H]) +#define RSCAN0RMPTR75HL (RSCAN0.RMPTR75.UINT8[R_IO_HL]) +#define RSCAN0RMPTR75HH (RSCAN0.RMPTR75.UINT8[R_IO_HH]) +#define RSCAN0RMDF075 (RSCAN0.RMDF075.UINT32) +#define RSCAN0RMDF075L (RSCAN0.RMDF075.UINT16[R_IO_L]) +#define RSCAN0RMDF075LL (RSCAN0.RMDF075.UINT8[R_IO_LL]) +#define RSCAN0RMDF075LH (RSCAN0.RMDF075.UINT8[R_IO_LH]) +#define RSCAN0RMDF075H (RSCAN0.RMDF075.UINT16[R_IO_H]) +#define RSCAN0RMDF075HL (RSCAN0.RMDF075.UINT8[R_IO_HL]) +#define RSCAN0RMDF075HH (RSCAN0.RMDF075.UINT8[R_IO_HH]) +#define RSCAN0RMDF175 (RSCAN0.RMDF175.UINT32) +#define RSCAN0RMDF175L (RSCAN0.RMDF175.UINT16[R_IO_L]) +#define RSCAN0RMDF175LL (RSCAN0.RMDF175.UINT8[R_IO_LL]) +#define RSCAN0RMDF175LH (RSCAN0.RMDF175.UINT8[R_IO_LH]) +#define RSCAN0RMDF175H (RSCAN0.RMDF175.UINT16[R_IO_H]) +#define RSCAN0RMDF175HL (RSCAN0.RMDF175.UINT8[R_IO_HL]) +#define RSCAN0RMDF175HH (RSCAN0.RMDF175.UINT8[R_IO_HH]) +#define RSCAN0RMID76 (RSCAN0.RMID76.UINT32) +#define RSCAN0RMID76L (RSCAN0.RMID76.UINT16[R_IO_L]) +#define RSCAN0RMID76LL (RSCAN0.RMID76.UINT8[R_IO_LL]) +#define RSCAN0RMID76LH (RSCAN0.RMID76.UINT8[R_IO_LH]) +#define RSCAN0RMID76H (RSCAN0.RMID76.UINT16[R_IO_H]) +#define RSCAN0RMID76HL (RSCAN0.RMID76.UINT8[R_IO_HL]) +#define RSCAN0RMID76HH (RSCAN0.RMID76.UINT8[R_IO_HH]) +#define RSCAN0RMPTR76 (RSCAN0.RMPTR76.UINT32) +#define RSCAN0RMPTR76L (RSCAN0.RMPTR76.UINT16[R_IO_L]) +#define RSCAN0RMPTR76LL (RSCAN0.RMPTR76.UINT8[R_IO_LL]) +#define RSCAN0RMPTR76LH (RSCAN0.RMPTR76.UINT8[R_IO_LH]) +#define RSCAN0RMPTR76H (RSCAN0.RMPTR76.UINT16[R_IO_H]) +#define RSCAN0RMPTR76HL (RSCAN0.RMPTR76.UINT8[R_IO_HL]) +#define RSCAN0RMPTR76HH (RSCAN0.RMPTR76.UINT8[R_IO_HH]) +#define RSCAN0RMDF076 (RSCAN0.RMDF076.UINT32) +#define RSCAN0RMDF076L (RSCAN0.RMDF076.UINT16[R_IO_L]) +#define RSCAN0RMDF076LL (RSCAN0.RMDF076.UINT8[R_IO_LL]) +#define RSCAN0RMDF076LH (RSCAN0.RMDF076.UINT8[R_IO_LH]) +#define RSCAN0RMDF076H (RSCAN0.RMDF076.UINT16[R_IO_H]) +#define RSCAN0RMDF076HL (RSCAN0.RMDF076.UINT8[R_IO_HL]) +#define RSCAN0RMDF076HH (RSCAN0.RMDF076.UINT8[R_IO_HH]) +#define RSCAN0RMDF176 (RSCAN0.RMDF176.UINT32) +#define RSCAN0RMDF176L (RSCAN0.RMDF176.UINT16[R_IO_L]) +#define RSCAN0RMDF176LL (RSCAN0.RMDF176.UINT8[R_IO_LL]) +#define RSCAN0RMDF176LH (RSCAN0.RMDF176.UINT8[R_IO_LH]) +#define RSCAN0RMDF176H (RSCAN0.RMDF176.UINT16[R_IO_H]) +#define RSCAN0RMDF176HL (RSCAN0.RMDF176.UINT8[R_IO_HL]) +#define RSCAN0RMDF176HH (RSCAN0.RMDF176.UINT8[R_IO_HH]) +#define RSCAN0RMID77 (RSCAN0.RMID77.UINT32) +#define RSCAN0RMID77L (RSCAN0.RMID77.UINT16[R_IO_L]) +#define RSCAN0RMID77LL (RSCAN0.RMID77.UINT8[R_IO_LL]) +#define RSCAN0RMID77LH (RSCAN0.RMID77.UINT8[R_IO_LH]) +#define RSCAN0RMID77H (RSCAN0.RMID77.UINT16[R_IO_H]) +#define RSCAN0RMID77HL (RSCAN0.RMID77.UINT8[R_IO_HL]) +#define RSCAN0RMID77HH (RSCAN0.RMID77.UINT8[R_IO_HH]) +#define RSCAN0RMPTR77 (RSCAN0.RMPTR77.UINT32) +#define RSCAN0RMPTR77L (RSCAN0.RMPTR77.UINT16[R_IO_L]) +#define RSCAN0RMPTR77LL (RSCAN0.RMPTR77.UINT8[R_IO_LL]) +#define RSCAN0RMPTR77LH (RSCAN0.RMPTR77.UINT8[R_IO_LH]) +#define RSCAN0RMPTR77H (RSCAN0.RMPTR77.UINT16[R_IO_H]) +#define RSCAN0RMPTR77HL (RSCAN0.RMPTR77.UINT8[R_IO_HL]) +#define RSCAN0RMPTR77HH (RSCAN0.RMPTR77.UINT8[R_IO_HH]) +#define RSCAN0RMDF077 (RSCAN0.RMDF077.UINT32) +#define RSCAN0RMDF077L (RSCAN0.RMDF077.UINT16[R_IO_L]) +#define RSCAN0RMDF077LL (RSCAN0.RMDF077.UINT8[R_IO_LL]) +#define RSCAN0RMDF077LH (RSCAN0.RMDF077.UINT8[R_IO_LH]) +#define RSCAN0RMDF077H (RSCAN0.RMDF077.UINT16[R_IO_H]) +#define RSCAN0RMDF077HL (RSCAN0.RMDF077.UINT8[R_IO_HL]) +#define RSCAN0RMDF077HH (RSCAN0.RMDF077.UINT8[R_IO_HH]) +#define RSCAN0RMDF177 (RSCAN0.RMDF177.UINT32) +#define RSCAN0RMDF177L (RSCAN0.RMDF177.UINT16[R_IO_L]) +#define RSCAN0RMDF177LL (RSCAN0.RMDF177.UINT8[R_IO_LL]) +#define RSCAN0RMDF177LH (RSCAN0.RMDF177.UINT8[R_IO_LH]) +#define RSCAN0RMDF177H (RSCAN0.RMDF177.UINT16[R_IO_H]) +#define RSCAN0RMDF177HL (RSCAN0.RMDF177.UINT8[R_IO_HL]) +#define RSCAN0RMDF177HH (RSCAN0.RMDF177.UINT8[R_IO_HH]) +#define RSCAN0RMID78 (RSCAN0.RMID78.UINT32) +#define RSCAN0RMID78L (RSCAN0.RMID78.UINT16[R_IO_L]) +#define RSCAN0RMID78LL (RSCAN0.RMID78.UINT8[R_IO_LL]) +#define RSCAN0RMID78LH (RSCAN0.RMID78.UINT8[R_IO_LH]) +#define RSCAN0RMID78H (RSCAN0.RMID78.UINT16[R_IO_H]) +#define RSCAN0RMID78HL (RSCAN0.RMID78.UINT8[R_IO_HL]) +#define RSCAN0RMID78HH (RSCAN0.RMID78.UINT8[R_IO_HH]) +#define RSCAN0RMPTR78 (RSCAN0.RMPTR78.UINT32) +#define RSCAN0RMPTR78L (RSCAN0.RMPTR78.UINT16[R_IO_L]) +#define RSCAN0RMPTR78LL (RSCAN0.RMPTR78.UINT8[R_IO_LL]) +#define RSCAN0RMPTR78LH (RSCAN0.RMPTR78.UINT8[R_IO_LH]) +#define RSCAN0RMPTR78H (RSCAN0.RMPTR78.UINT16[R_IO_H]) +#define RSCAN0RMPTR78HL (RSCAN0.RMPTR78.UINT8[R_IO_HL]) +#define RSCAN0RMPTR78HH (RSCAN0.RMPTR78.UINT8[R_IO_HH]) +#define RSCAN0RMDF078 (RSCAN0.RMDF078.UINT32) +#define RSCAN0RMDF078L (RSCAN0.RMDF078.UINT16[R_IO_L]) +#define RSCAN0RMDF078LL (RSCAN0.RMDF078.UINT8[R_IO_LL]) +#define RSCAN0RMDF078LH (RSCAN0.RMDF078.UINT8[R_IO_LH]) +#define RSCAN0RMDF078H (RSCAN0.RMDF078.UINT16[R_IO_H]) +#define RSCAN0RMDF078HL (RSCAN0.RMDF078.UINT8[R_IO_HL]) +#define RSCAN0RMDF078HH (RSCAN0.RMDF078.UINT8[R_IO_HH]) +#define RSCAN0RMDF178 (RSCAN0.RMDF178.UINT32) +#define RSCAN0RMDF178L (RSCAN0.RMDF178.UINT16[R_IO_L]) +#define RSCAN0RMDF178LL (RSCAN0.RMDF178.UINT8[R_IO_LL]) +#define RSCAN0RMDF178LH (RSCAN0.RMDF178.UINT8[R_IO_LH]) +#define RSCAN0RMDF178H (RSCAN0.RMDF178.UINT16[R_IO_H]) +#define RSCAN0RMDF178HL (RSCAN0.RMDF178.UINT8[R_IO_HL]) +#define RSCAN0RMDF178HH (RSCAN0.RMDF178.UINT8[R_IO_HH]) +#define RSCAN0RMID79 (RSCAN0.RMID79.UINT32) +#define RSCAN0RMID79L (RSCAN0.RMID79.UINT16[R_IO_L]) +#define RSCAN0RMID79LL (RSCAN0.RMID79.UINT8[R_IO_LL]) +#define RSCAN0RMID79LH (RSCAN0.RMID79.UINT8[R_IO_LH]) +#define RSCAN0RMID79H (RSCAN0.RMID79.UINT16[R_IO_H]) +#define RSCAN0RMID79HL (RSCAN0.RMID79.UINT8[R_IO_HL]) +#define RSCAN0RMID79HH (RSCAN0.RMID79.UINT8[R_IO_HH]) +#define RSCAN0RMPTR79 (RSCAN0.RMPTR79.UINT32) +#define RSCAN0RMPTR79L (RSCAN0.RMPTR79.UINT16[R_IO_L]) +#define RSCAN0RMPTR79LL (RSCAN0.RMPTR79.UINT8[R_IO_LL]) +#define RSCAN0RMPTR79LH (RSCAN0.RMPTR79.UINT8[R_IO_LH]) +#define RSCAN0RMPTR79H (RSCAN0.RMPTR79.UINT16[R_IO_H]) +#define RSCAN0RMPTR79HL (RSCAN0.RMPTR79.UINT8[R_IO_HL]) +#define RSCAN0RMPTR79HH (RSCAN0.RMPTR79.UINT8[R_IO_HH]) +#define RSCAN0RMDF079 (RSCAN0.RMDF079.UINT32) +#define RSCAN0RMDF079L (RSCAN0.RMDF079.UINT16[R_IO_L]) +#define RSCAN0RMDF079LL (RSCAN0.RMDF079.UINT8[R_IO_LL]) +#define RSCAN0RMDF079LH (RSCAN0.RMDF079.UINT8[R_IO_LH]) +#define RSCAN0RMDF079H (RSCAN0.RMDF079.UINT16[R_IO_H]) +#define RSCAN0RMDF079HL (RSCAN0.RMDF079.UINT8[R_IO_HL]) +#define RSCAN0RMDF079HH (RSCAN0.RMDF079.UINT8[R_IO_HH]) +#define RSCAN0RMDF179 (RSCAN0.RMDF179.UINT32) +#define RSCAN0RMDF179L (RSCAN0.RMDF179.UINT16[R_IO_L]) +#define RSCAN0RMDF179LL (RSCAN0.RMDF179.UINT8[R_IO_LL]) +#define RSCAN0RMDF179LH (RSCAN0.RMDF179.UINT8[R_IO_LH]) +#define RSCAN0RMDF179H (RSCAN0.RMDF179.UINT16[R_IO_H]) +#define RSCAN0RMDF179HL (RSCAN0.RMDF179.UINT8[R_IO_HL]) +#define RSCAN0RMDF179HH (RSCAN0.RMDF179.UINT8[R_IO_HH]) +#define RSCAN0RFID0 (RSCAN0.RFID0.UINT32) +#define RSCAN0RFID0L (RSCAN0.RFID0.UINT16[R_IO_L]) +#define RSCAN0RFID0LL (RSCAN0.RFID0.UINT8[R_IO_LL]) +#define RSCAN0RFID0LH (RSCAN0.RFID0.UINT8[R_IO_LH]) +#define RSCAN0RFID0H (RSCAN0.RFID0.UINT16[R_IO_H]) +#define RSCAN0RFID0HL (RSCAN0.RFID0.UINT8[R_IO_HL]) +#define RSCAN0RFID0HH (RSCAN0.RFID0.UINT8[R_IO_HH]) +#define RSCAN0RFPTR0 (RSCAN0.RFPTR0.UINT32) +#define RSCAN0RFPTR0L (RSCAN0.RFPTR0.UINT16[R_IO_L]) +#define RSCAN0RFPTR0LL (RSCAN0.RFPTR0.UINT8[R_IO_LL]) +#define RSCAN0RFPTR0LH (RSCAN0.RFPTR0.UINT8[R_IO_LH]) +#define RSCAN0RFPTR0H (RSCAN0.RFPTR0.UINT16[R_IO_H]) +#define RSCAN0RFPTR0HL (RSCAN0.RFPTR0.UINT8[R_IO_HL]) +#define RSCAN0RFPTR0HH (RSCAN0.RFPTR0.UINT8[R_IO_HH]) +#define RSCAN0RFDF00 (RSCAN0.RFDF00.UINT32) +#define RSCAN0RFDF00L (RSCAN0.RFDF00.UINT16[R_IO_L]) +#define RSCAN0RFDF00LL (RSCAN0.RFDF00.UINT8[R_IO_LL]) +#define RSCAN0RFDF00LH (RSCAN0.RFDF00.UINT8[R_IO_LH]) +#define RSCAN0RFDF00H (RSCAN0.RFDF00.UINT16[R_IO_H]) +#define RSCAN0RFDF00HL (RSCAN0.RFDF00.UINT8[R_IO_HL]) +#define RSCAN0RFDF00HH (RSCAN0.RFDF00.UINT8[R_IO_HH]) +#define RSCAN0RFDF10 (RSCAN0.RFDF10.UINT32) +#define RSCAN0RFDF10L (RSCAN0.RFDF10.UINT16[R_IO_L]) +#define RSCAN0RFDF10LL (RSCAN0.RFDF10.UINT8[R_IO_LL]) +#define RSCAN0RFDF10LH (RSCAN0.RFDF10.UINT8[R_IO_LH]) +#define RSCAN0RFDF10H (RSCAN0.RFDF10.UINT16[R_IO_H]) +#define RSCAN0RFDF10HL (RSCAN0.RFDF10.UINT8[R_IO_HL]) +#define RSCAN0RFDF10HH (RSCAN0.RFDF10.UINT8[R_IO_HH]) +#define RSCAN0RFID1 (RSCAN0.RFID1.UINT32) +#define RSCAN0RFID1L (RSCAN0.RFID1.UINT16[R_IO_L]) +#define RSCAN0RFID1LL (RSCAN0.RFID1.UINT8[R_IO_LL]) +#define RSCAN0RFID1LH (RSCAN0.RFID1.UINT8[R_IO_LH]) +#define RSCAN0RFID1H (RSCAN0.RFID1.UINT16[R_IO_H]) +#define RSCAN0RFID1HL (RSCAN0.RFID1.UINT8[R_IO_HL]) +#define RSCAN0RFID1HH (RSCAN0.RFID1.UINT8[R_IO_HH]) +#define RSCAN0RFPTR1 (RSCAN0.RFPTR1.UINT32) +#define RSCAN0RFPTR1L (RSCAN0.RFPTR1.UINT16[R_IO_L]) +#define RSCAN0RFPTR1LL (RSCAN0.RFPTR1.UINT8[R_IO_LL]) +#define RSCAN0RFPTR1LH (RSCAN0.RFPTR1.UINT8[R_IO_LH]) +#define RSCAN0RFPTR1H (RSCAN0.RFPTR1.UINT16[R_IO_H]) +#define RSCAN0RFPTR1HL (RSCAN0.RFPTR1.UINT8[R_IO_HL]) +#define RSCAN0RFPTR1HH (RSCAN0.RFPTR1.UINT8[R_IO_HH]) +#define RSCAN0RFDF01 (RSCAN0.RFDF01.UINT32) +#define RSCAN0RFDF01L (RSCAN0.RFDF01.UINT16[R_IO_L]) +#define RSCAN0RFDF01LL (RSCAN0.RFDF01.UINT8[R_IO_LL]) +#define RSCAN0RFDF01LH (RSCAN0.RFDF01.UINT8[R_IO_LH]) +#define RSCAN0RFDF01H (RSCAN0.RFDF01.UINT16[R_IO_H]) +#define RSCAN0RFDF01HL (RSCAN0.RFDF01.UINT8[R_IO_HL]) +#define RSCAN0RFDF01HH (RSCAN0.RFDF01.UINT8[R_IO_HH]) +#define RSCAN0RFDF11 (RSCAN0.RFDF11.UINT32) +#define RSCAN0RFDF11L (RSCAN0.RFDF11.UINT16[R_IO_L]) +#define RSCAN0RFDF11LL (RSCAN0.RFDF11.UINT8[R_IO_LL]) +#define RSCAN0RFDF11LH (RSCAN0.RFDF11.UINT8[R_IO_LH]) +#define RSCAN0RFDF11H (RSCAN0.RFDF11.UINT16[R_IO_H]) +#define RSCAN0RFDF11HL (RSCAN0.RFDF11.UINT8[R_IO_HL]) +#define RSCAN0RFDF11HH (RSCAN0.RFDF11.UINT8[R_IO_HH]) +#define RSCAN0RFID2 (RSCAN0.RFID2.UINT32) +#define RSCAN0RFID2L (RSCAN0.RFID2.UINT16[R_IO_L]) +#define RSCAN0RFID2LL (RSCAN0.RFID2.UINT8[R_IO_LL]) +#define RSCAN0RFID2LH (RSCAN0.RFID2.UINT8[R_IO_LH]) +#define RSCAN0RFID2H (RSCAN0.RFID2.UINT16[R_IO_H]) +#define RSCAN0RFID2HL (RSCAN0.RFID2.UINT8[R_IO_HL]) +#define RSCAN0RFID2HH (RSCAN0.RFID2.UINT8[R_IO_HH]) +#define RSCAN0RFPTR2 (RSCAN0.RFPTR2.UINT32) +#define RSCAN0RFPTR2L (RSCAN0.RFPTR2.UINT16[R_IO_L]) +#define RSCAN0RFPTR2LL (RSCAN0.RFPTR2.UINT8[R_IO_LL]) +#define RSCAN0RFPTR2LH (RSCAN0.RFPTR2.UINT8[R_IO_LH]) +#define RSCAN0RFPTR2H (RSCAN0.RFPTR2.UINT16[R_IO_H]) +#define RSCAN0RFPTR2HL (RSCAN0.RFPTR2.UINT8[R_IO_HL]) +#define RSCAN0RFPTR2HH (RSCAN0.RFPTR2.UINT8[R_IO_HH]) +#define RSCAN0RFDF02 (RSCAN0.RFDF02.UINT32) +#define RSCAN0RFDF02L (RSCAN0.RFDF02.UINT16[R_IO_L]) +#define RSCAN0RFDF02LL (RSCAN0.RFDF02.UINT8[R_IO_LL]) +#define RSCAN0RFDF02LH (RSCAN0.RFDF02.UINT8[R_IO_LH]) +#define RSCAN0RFDF02H (RSCAN0.RFDF02.UINT16[R_IO_H]) +#define RSCAN0RFDF02HL (RSCAN0.RFDF02.UINT8[R_IO_HL]) +#define RSCAN0RFDF02HH (RSCAN0.RFDF02.UINT8[R_IO_HH]) +#define RSCAN0RFDF12 (RSCAN0.RFDF12.UINT32) +#define RSCAN0RFDF12L (RSCAN0.RFDF12.UINT16[R_IO_L]) +#define RSCAN0RFDF12LL (RSCAN0.RFDF12.UINT8[R_IO_LL]) +#define RSCAN0RFDF12LH (RSCAN0.RFDF12.UINT8[R_IO_LH]) +#define RSCAN0RFDF12H (RSCAN0.RFDF12.UINT16[R_IO_H]) +#define RSCAN0RFDF12HL (RSCAN0.RFDF12.UINT8[R_IO_HL]) +#define RSCAN0RFDF12HH (RSCAN0.RFDF12.UINT8[R_IO_HH]) +#define RSCAN0RFID3 (RSCAN0.RFID3.UINT32) +#define RSCAN0RFID3L (RSCAN0.RFID3.UINT16[R_IO_L]) +#define RSCAN0RFID3LL (RSCAN0.RFID3.UINT8[R_IO_LL]) +#define RSCAN0RFID3LH (RSCAN0.RFID3.UINT8[R_IO_LH]) +#define RSCAN0RFID3H (RSCAN0.RFID3.UINT16[R_IO_H]) +#define RSCAN0RFID3HL (RSCAN0.RFID3.UINT8[R_IO_HL]) +#define RSCAN0RFID3HH (RSCAN0.RFID3.UINT8[R_IO_HH]) +#define RSCAN0RFPTR3 (RSCAN0.RFPTR3.UINT32) +#define RSCAN0RFPTR3L (RSCAN0.RFPTR3.UINT16[R_IO_L]) +#define RSCAN0RFPTR3LL (RSCAN0.RFPTR3.UINT8[R_IO_LL]) +#define RSCAN0RFPTR3LH (RSCAN0.RFPTR3.UINT8[R_IO_LH]) +#define RSCAN0RFPTR3H (RSCAN0.RFPTR3.UINT16[R_IO_H]) +#define RSCAN0RFPTR3HL (RSCAN0.RFPTR3.UINT8[R_IO_HL]) +#define RSCAN0RFPTR3HH (RSCAN0.RFPTR3.UINT8[R_IO_HH]) +#define RSCAN0RFDF03 (RSCAN0.RFDF03.UINT32) +#define RSCAN0RFDF03L (RSCAN0.RFDF03.UINT16[R_IO_L]) +#define RSCAN0RFDF03LL (RSCAN0.RFDF03.UINT8[R_IO_LL]) +#define RSCAN0RFDF03LH (RSCAN0.RFDF03.UINT8[R_IO_LH]) +#define RSCAN0RFDF03H (RSCAN0.RFDF03.UINT16[R_IO_H]) +#define RSCAN0RFDF03HL (RSCAN0.RFDF03.UINT8[R_IO_HL]) +#define RSCAN0RFDF03HH (RSCAN0.RFDF03.UINT8[R_IO_HH]) +#define RSCAN0RFDF13 (RSCAN0.RFDF13.UINT32) +#define RSCAN0RFDF13L (RSCAN0.RFDF13.UINT16[R_IO_L]) +#define RSCAN0RFDF13LL (RSCAN0.RFDF13.UINT8[R_IO_LL]) +#define RSCAN0RFDF13LH (RSCAN0.RFDF13.UINT8[R_IO_LH]) +#define RSCAN0RFDF13H (RSCAN0.RFDF13.UINT16[R_IO_H]) +#define RSCAN0RFDF13HL (RSCAN0.RFDF13.UINT8[R_IO_HL]) +#define RSCAN0RFDF13HH (RSCAN0.RFDF13.UINT8[R_IO_HH]) +#define RSCAN0RFID4 (RSCAN0.RFID4.UINT32) +#define RSCAN0RFID4L (RSCAN0.RFID4.UINT16[R_IO_L]) +#define RSCAN0RFID4LL (RSCAN0.RFID4.UINT8[R_IO_LL]) +#define RSCAN0RFID4LH (RSCAN0.RFID4.UINT8[R_IO_LH]) +#define RSCAN0RFID4H (RSCAN0.RFID4.UINT16[R_IO_H]) +#define RSCAN0RFID4HL (RSCAN0.RFID4.UINT8[R_IO_HL]) +#define RSCAN0RFID4HH (RSCAN0.RFID4.UINT8[R_IO_HH]) +#define RSCAN0RFPTR4 (RSCAN0.RFPTR4.UINT32) +#define RSCAN0RFPTR4L (RSCAN0.RFPTR4.UINT16[R_IO_L]) +#define RSCAN0RFPTR4LL (RSCAN0.RFPTR4.UINT8[R_IO_LL]) +#define RSCAN0RFPTR4LH (RSCAN0.RFPTR4.UINT8[R_IO_LH]) +#define RSCAN0RFPTR4H (RSCAN0.RFPTR4.UINT16[R_IO_H]) +#define RSCAN0RFPTR4HL (RSCAN0.RFPTR4.UINT8[R_IO_HL]) +#define RSCAN0RFPTR4HH (RSCAN0.RFPTR4.UINT8[R_IO_HH]) +#define RSCAN0RFDF04 (RSCAN0.RFDF04.UINT32) +#define RSCAN0RFDF04L (RSCAN0.RFDF04.UINT16[R_IO_L]) +#define RSCAN0RFDF04LL (RSCAN0.RFDF04.UINT8[R_IO_LL]) +#define RSCAN0RFDF04LH (RSCAN0.RFDF04.UINT8[R_IO_LH]) +#define RSCAN0RFDF04H (RSCAN0.RFDF04.UINT16[R_IO_H]) +#define RSCAN0RFDF04HL (RSCAN0.RFDF04.UINT8[R_IO_HL]) +#define RSCAN0RFDF04HH (RSCAN0.RFDF04.UINT8[R_IO_HH]) +#define RSCAN0RFDF14 (RSCAN0.RFDF14.UINT32) +#define RSCAN0RFDF14L (RSCAN0.RFDF14.UINT16[R_IO_L]) +#define RSCAN0RFDF14LL (RSCAN0.RFDF14.UINT8[R_IO_LL]) +#define RSCAN0RFDF14LH (RSCAN0.RFDF14.UINT8[R_IO_LH]) +#define RSCAN0RFDF14H (RSCAN0.RFDF14.UINT16[R_IO_H]) +#define RSCAN0RFDF14HL (RSCAN0.RFDF14.UINT8[R_IO_HL]) +#define RSCAN0RFDF14HH (RSCAN0.RFDF14.UINT8[R_IO_HH]) +#define RSCAN0RFID5 (RSCAN0.RFID5.UINT32) +#define RSCAN0RFID5L (RSCAN0.RFID5.UINT16[R_IO_L]) +#define RSCAN0RFID5LL (RSCAN0.RFID5.UINT8[R_IO_LL]) +#define RSCAN0RFID5LH (RSCAN0.RFID5.UINT8[R_IO_LH]) +#define RSCAN0RFID5H (RSCAN0.RFID5.UINT16[R_IO_H]) +#define RSCAN0RFID5HL (RSCAN0.RFID5.UINT8[R_IO_HL]) +#define RSCAN0RFID5HH (RSCAN0.RFID5.UINT8[R_IO_HH]) +#define RSCAN0RFPTR5 (RSCAN0.RFPTR5.UINT32) +#define RSCAN0RFPTR5L (RSCAN0.RFPTR5.UINT16[R_IO_L]) +#define RSCAN0RFPTR5LL (RSCAN0.RFPTR5.UINT8[R_IO_LL]) +#define RSCAN0RFPTR5LH (RSCAN0.RFPTR5.UINT8[R_IO_LH]) +#define RSCAN0RFPTR5H (RSCAN0.RFPTR5.UINT16[R_IO_H]) +#define RSCAN0RFPTR5HL (RSCAN0.RFPTR5.UINT8[R_IO_HL]) +#define RSCAN0RFPTR5HH (RSCAN0.RFPTR5.UINT8[R_IO_HH]) +#define RSCAN0RFDF05 (RSCAN0.RFDF05.UINT32) +#define RSCAN0RFDF05L (RSCAN0.RFDF05.UINT16[R_IO_L]) +#define RSCAN0RFDF05LL (RSCAN0.RFDF05.UINT8[R_IO_LL]) +#define RSCAN0RFDF05LH (RSCAN0.RFDF05.UINT8[R_IO_LH]) +#define RSCAN0RFDF05H (RSCAN0.RFDF05.UINT16[R_IO_H]) +#define RSCAN0RFDF05HL (RSCAN0.RFDF05.UINT8[R_IO_HL]) +#define RSCAN0RFDF05HH (RSCAN0.RFDF05.UINT8[R_IO_HH]) +#define RSCAN0RFDF15 (RSCAN0.RFDF15.UINT32) +#define RSCAN0RFDF15L (RSCAN0.RFDF15.UINT16[R_IO_L]) +#define RSCAN0RFDF15LL (RSCAN0.RFDF15.UINT8[R_IO_LL]) +#define RSCAN0RFDF15LH (RSCAN0.RFDF15.UINT8[R_IO_LH]) +#define RSCAN0RFDF15H (RSCAN0.RFDF15.UINT16[R_IO_H]) +#define RSCAN0RFDF15HL (RSCAN0.RFDF15.UINT8[R_IO_HL]) +#define RSCAN0RFDF15HH (RSCAN0.RFDF15.UINT8[R_IO_HH]) +#define RSCAN0RFID6 (RSCAN0.RFID6.UINT32) +#define RSCAN0RFID6L (RSCAN0.RFID6.UINT16[R_IO_L]) +#define RSCAN0RFID6LL (RSCAN0.RFID6.UINT8[R_IO_LL]) +#define RSCAN0RFID6LH (RSCAN0.RFID6.UINT8[R_IO_LH]) +#define RSCAN0RFID6H (RSCAN0.RFID6.UINT16[R_IO_H]) +#define RSCAN0RFID6HL (RSCAN0.RFID6.UINT8[R_IO_HL]) +#define RSCAN0RFID6HH (RSCAN0.RFID6.UINT8[R_IO_HH]) +#define RSCAN0RFPTR6 (RSCAN0.RFPTR6.UINT32) +#define RSCAN0RFPTR6L (RSCAN0.RFPTR6.UINT16[R_IO_L]) +#define RSCAN0RFPTR6LL (RSCAN0.RFPTR6.UINT8[R_IO_LL]) +#define RSCAN0RFPTR6LH (RSCAN0.RFPTR6.UINT8[R_IO_LH]) +#define RSCAN0RFPTR6H (RSCAN0.RFPTR6.UINT16[R_IO_H]) +#define RSCAN0RFPTR6HL (RSCAN0.RFPTR6.UINT8[R_IO_HL]) +#define RSCAN0RFPTR6HH (RSCAN0.RFPTR6.UINT8[R_IO_HH]) +#define RSCAN0RFDF06 (RSCAN0.RFDF06.UINT32) +#define RSCAN0RFDF06L (RSCAN0.RFDF06.UINT16[R_IO_L]) +#define RSCAN0RFDF06LL (RSCAN0.RFDF06.UINT8[R_IO_LL]) +#define RSCAN0RFDF06LH (RSCAN0.RFDF06.UINT8[R_IO_LH]) +#define RSCAN0RFDF06H (RSCAN0.RFDF06.UINT16[R_IO_H]) +#define RSCAN0RFDF06HL (RSCAN0.RFDF06.UINT8[R_IO_HL]) +#define RSCAN0RFDF06HH (RSCAN0.RFDF06.UINT8[R_IO_HH]) +#define RSCAN0RFDF16 (RSCAN0.RFDF16.UINT32) +#define RSCAN0RFDF16L (RSCAN0.RFDF16.UINT16[R_IO_L]) +#define RSCAN0RFDF16LL (RSCAN0.RFDF16.UINT8[R_IO_LL]) +#define RSCAN0RFDF16LH (RSCAN0.RFDF16.UINT8[R_IO_LH]) +#define RSCAN0RFDF16H (RSCAN0.RFDF16.UINT16[R_IO_H]) +#define RSCAN0RFDF16HL (RSCAN0.RFDF16.UINT8[R_IO_HL]) +#define RSCAN0RFDF16HH (RSCAN0.RFDF16.UINT8[R_IO_HH]) +#define RSCAN0RFID7 (RSCAN0.RFID7.UINT32) +#define RSCAN0RFID7L (RSCAN0.RFID7.UINT16[R_IO_L]) +#define RSCAN0RFID7LL (RSCAN0.RFID7.UINT8[R_IO_LL]) +#define RSCAN0RFID7LH (RSCAN0.RFID7.UINT8[R_IO_LH]) +#define RSCAN0RFID7H (RSCAN0.RFID7.UINT16[R_IO_H]) +#define RSCAN0RFID7HL (RSCAN0.RFID7.UINT8[R_IO_HL]) +#define RSCAN0RFID7HH (RSCAN0.RFID7.UINT8[R_IO_HH]) +#define RSCAN0RFPTR7 (RSCAN0.RFPTR7.UINT32) +#define RSCAN0RFPTR7L (RSCAN0.RFPTR7.UINT16[R_IO_L]) +#define RSCAN0RFPTR7LL (RSCAN0.RFPTR7.UINT8[R_IO_LL]) +#define RSCAN0RFPTR7LH (RSCAN0.RFPTR7.UINT8[R_IO_LH]) +#define RSCAN0RFPTR7H (RSCAN0.RFPTR7.UINT16[R_IO_H]) +#define RSCAN0RFPTR7HL (RSCAN0.RFPTR7.UINT8[R_IO_HL]) +#define RSCAN0RFPTR7HH (RSCAN0.RFPTR7.UINT8[R_IO_HH]) +#define RSCAN0RFDF07 (RSCAN0.RFDF07.UINT32) +#define RSCAN0RFDF07L (RSCAN0.RFDF07.UINT16[R_IO_L]) +#define RSCAN0RFDF07LL (RSCAN0.RFDF07.UINT8[R_IO_LL]) +#define RSCAN0RFDF07LH (RSCAN0.RFDF07.UINT8[R_IO_LH]) +#define RSCAN0RFDF07H (RSCAN0.RFDF07.UINT16[R_IO_H]) +#define RSCAN0RFDF07HL (RSCAN0.RFDF07.UINT8[R_IO_HL]) +#define RSCAN0RFDF07HH (RSCAN0.RFDF07.UINT8[R_IO_HH]) +#define RSCAN0RFDF17 (RSCAN0.RFDF17.UINT32) +#define RSCAN0RFDF17L (RSCAN0.RFDF17.UINT16[R_IO_L]) +#define RSCAN0RFDF17LL (RSCAN0.RFDF17.UINT8[R_IO_LL]) +#define RSCAN0RFDF17LH (RSCAN0.RFDF17.UINT8[R_IO_LH]) +#define RSCAN0RFDF17H (RSCAN0.RFDF17.UINT16[R_IO_H]) +#define RSCAN0RFDF17HL (RSCAN0.RFDF17.UINT8[R_IO_HL]) +#define RSCAN0RFDF17HH (RSCAN0.RFDF17.UINT8[R_IO_HH]) +#define RSCAN0CFID0 (RSCAN0.CFID0.UINT32) +#define RSCAN0CFID0L (RSCAN0.CFID0.UINT16[R_IO_L]) +#define RSCAN0CFID0LL (RSCAN0.CFID0.UINT8[R_IO_LL]) +#define RSCAN0CFID0LH (RSCAN0.CFID0.UINT8[R_IO_LH]) +#define RSCAN0CFID0H (RSCAN0.CFID0.UINT16[R_IO_H]) +#define RSCAN0CFID0HL (RSCAN0.CFID0.UINT8[R_IO_HL]) +#define RSCAN0CFID0HH (RSCAN0.CFID0.UINT8[R_IO_HH]) +#define RSCAN0CFPTR0 (RSCAN0.CFPTR0.UINT32) +#define RSCAN0CFPTR0L (RSCAN0.CFPTR0.UINT16[R_IO_L]) +#define RSCAN0CFPTR0LL (RSCAN0.CFPTR0.UINT8[R_IO_LL]) +#define RSCAN0CFPTR0LH (RSCAN0.CFPTR0.UINT8[R_IO_LH]) +#define RSCAN0CFPTR0H (RSCAN0.CFPTR0.UINT16[R_IO_H]) +#define RSCAN0CFPTR0HL (RSCAN0.CFPTR0.UINT8[R_IO_HL]) +#define RSCAN0CFPTR0HH (RSCAN0.CFPTR0.UINT8[R_IO_HH]) +#define RSCAN0CFDF00 (RSCAN0.CFDF00.UINT32) +#define RSCAN0CFDF00L (RSCAN0.CFDF00.UINT16[R_IO_L]) +#define RSCAN0CFDF00LL (RSCAN0.CFDF00.UINT8[R_IO_LL]) +#define RSCAN0CFDF00LH (RSCAN0.CFDF00.UINT8[R_IO_LH]) +#define RSCAN0CFDF00H (RSCAN0.CFDF00.UINT16[R_IO_H]) +#define RSCAN0CFDF00HL (RSCAN0.CFDF00.UINT8[R_IO_HL]) +#define RSCAN0CFDF00HH (RSCAN0.CFDF00.UINT8[R_IO_HH]) +#define RSCAN0CFDF10 (RSCAN0.CFDF10.UINT32) +#define RSCAN0CFDF10L (RSCAN0.CFDF10.UINT16[R_IO_L]) +#define RSCAN0CFDF10LL (RSCAN0.CFDF10.UINT8[R_IO_LL]) +#define RSCAN0CFDF10LH (RSCAN0.CFDF10.UINT8[R_IO_LH]) +#define RSCAN0CFDF10H (RSCAN0.CFDF10.UINT16[R_IO_H]) +#define RSCAN0CFDF10HL (RSCAN0.CFDF10.UINT8[R_IO_HL]) +#define RSCAN0CFDF10HH (RSCAN0.CFDF10.UINT8[R_IO_HH]) +#define RSCAN0CFID1 (RSCAN0.CFID1.UINT32) +#define RSCAN0CFID1L (RSCAN0.CFID1.UINT16[R_IO_L]) +#define RSCAN0CFID1LL (RSCAN0.CFID1.UINT8[R_IO_LL]) +#define RSCAN0CFID1LH (RSCAN0.CFID1.UINT8[R_IO_LH]) +#define RSCAN0CFID1H (RSCAN0.CFID1.UINT16[R_IO_H]) +#define RSCAN0CFID1HL (RSCAN0.CFID1.UINT8[R_IO_HL]) +#define RSCAN0CFID1HH (RSCAN0.CFID1.UINT8[R_IO_HH]) +#define RSCAN0CFPTR1 (RSCAN0.CFPTR1.UINT32) +#define RSCAN0CFPTR1L (RSCAN0.CFPTR1.UINT16[R_IO_L]) +#define RSCAN0CFPTR1LL (RSCAN0.CFPTR1.UINT8[R_IO_LL]) +#define RSCAN0CFPTR1LH (RSCAN0.CFPTR1.UINT8[R_IO_LH]) +#define RSCAN0CFPTR1H (RSCAN0.CFPTR1.UINT16[R_IO_H]) +#define RSCAN0CFPTR1HL (RSCAN0.CFPTR1.UINT8[R_IO_HL]) +#define RSCAN0CFPTR1HH (RSCAN0.CFPTR1.UINT8[R_IO_HH]) +#define RSCAN0CFDF01 (RSCAN0.CFDF01.UINT32) +#define RSCAN0CFDF01L (RSCAN0.CFDF01.UINT16[R_IO_L]) +#define RSCAN0CFDF01LL (RSCAN0.CFDF01.UINT8[R_IO_LL]) +#define RSCAN0CFDF01LH (RSCAN0.CFDF01.UINT8[R_IO_LH]) +#define RSCAN0CFDF01H (RSCAN0.CFDF01.UINT16[R_IO_H]) +#define RSCAN0CFDF01HL (RSCAN0.CFDF01.UINT8[R_IO_HL]) +#define RSCAN0CFDF01HH (RSCAN0.CFDF01.UINT8[R_IO_HH]) +#define RSCAN0CFDF11 (RSCAN0.CFDF11.UINT32) +#define RSCAN0CFDF11L (RSCAN0.CFDF11.UINT16[R_IO_L]) +#define RSCAN0CFDF11LL (RSCAN0.CFDF11.UINT8[R_IO_LL]) +#define RSCAN0CFDF11LH (RSCAN0.CFDF11.UINT8[R_IO_LH]) +#define RSCAN0CFDF11H (RSCAN0.CFDF11.UINT16[R_IO_H]) +#define RSCAN0CFDF11HL (RSCAN0.CFDF11.UINT8[R_IO_HL]) +#define RSCAN0CFDF11HH (RSCAN0.CFDF11.UINT8[R_IO_HH]) +#define RSCAN0CFID2 (RSCAN0.CFID2.UINT32) +#define RSCAN0CFID2L (RSCAN0.CFID2.UINT16[R_IO_L]) +#define RSCAN0CFID2LL (RSCAN0.CFID2.UINT8[R_IO_LL]) +#define RSCAN0CFID2LH (RSCAN0.CFID2.UINT8[R_IO_LH]) +#define RSCAN0CFID2H (RSCAN0.CFID2.UINT16[R_IO_H]) +#define RSCAN0CFID2HL (RSCAN0.CFID2.UINT8[R_IO_HL]) +#define RSCAN0CFID2HH (RSCAN0.CFID2.UINT8[R_IO_HH]) +#define RSCAN0CFPTR2 (RSCAN0.CFPTR2.UINT32) +#define RSCAN0CFPTR2L (RSCAN0.CFPTR2.UINT16[R_IO_L]) +#define RSCAN0CFPTR2LL (RSCAN0.CFPTR2.UINT8[R_IO_LL]) +#define RSCAN0CFPTR2LH (RSCAN0.CFPTR2.UINT8[R_IO_LH]) +#define RSCAN0CFPTR2H (RSCAN0.CFPTR2.UINT16[R_IO_H]) +#define RSCAN0CFPTR2HL (RSCAN0.CFPTR2.UINT8[R_IO_HL]) +#define RSCAN0CFPTR2HH (RSCAN0.CFPTR2.UINT8[R_IO_HH]) +#define RSCAN0CFDF02 (RSCAN0.CFDF02.UINT32) +#define RSCAN0CFDF02L (RSCAN0.CFDF02.UINT16[R_IO_L]) +#define RSCAN0CFDF02LL (RSCAN0.CFDF02.UINT8[R_IO_LL]) +#define RSCAN0CFDF02LH (RSCAN0.CFDF02.UINT8[R_IO_LH]) +#define RSCAN0CFDF02H (RSCAN0.CFDF02.UINT16[R_IO_H]) +#define RSCAN0CFDF02HL (RSCAN0.CFDF02.UINT8[R_IO_HL]) +#define RSCAN0CFDF02HH (RSCAN0.CFDF02.UINT8[R_IO_HH]) +#define RSCAN0CFDF12 (RSCAN0.CFDF12.UINT32) +#define RSCAN0CFDF12L (RSCAN0.CFDF12.UINT16[R_IO_L]) +#define RSCAN0CFDF12LL (RSCAN0.CFDF12.UINT8[R_IO_LL]) +#define RSCAN0CFDF12LH (RSCAN0.CFDF12.UINT8[R_IO_LH]) +#define RSCAN0CFDF12H (RSCAN0.CFDF12.UINT16[R_IO_H]) +#define RSCAN0CFDF12HL (RSCAN0.CFDF12.UINT8[R_IO_HL]) +#define RSCAN0CFDF12HH (RSCAN0.CFDF12.UINT8[R_IO_HH]) +#define RSCAN0CFID3 (RSCAN0.CFID3.UINT32) +#define RSCAN0CFID3L (RSCAN0.CFID3.UINT16[R_IO_L]) +#define RSCAN0CFID3LL (RSCAN0.CFID3.UINT8[R_IO_LL]) +#define RSCAN0CFID3LH (RSCAN0.CFID3.UINT8[R_IO_LH]) +#define RSCAN0CFID3H (RSCAN0.CFID3.UINT16[R_IO_H]) +#define RSCAN0CFID3HL (RSCAN0.CFID3.UINT8[R_IO_HL]) +#define RSCAN0CFID3HH (RSCAN0.CFID3.UINT8[R_IO_HH]) +#define RSCAN0CFPTR3 (RSCAN0.CFPTR3.UINT32) +#define RSCAN0CFPTR3L (RSCAN0.CFPTR3.UINT16[R_IO_L]) +#define RSCAN0CFPTR3LL (RSCAN0.CFPTR3.UINT8[R_IO_LL]) +#define RSCAN0CFPTR3LH (RSCAN0.CFPTR3.UINT8[R_IO_LH]) +#define RSCAN0CFPTR3H (RSCAN0.CFPTR3.UINT16[R_IO_H]) +#define RSCAN0CFPTR3HL (RSCAN0.CFPTR3.UINT8[R_IO_HL]) +#define RSCAN0CFPTR3HH (RSCAN0.CFPTR3.UINT8[R_IO_HH]) +#define RSCAN0CFDF03 (RSCAN0.CFDF03.UINT32) +#define RSCAN0CFDF03L (RSCAN0.CFDF03.UINT16[R_IO_L]) +#define RSCAN0CFDF03LL (RSCAN0.CFDF03.UINT8[R_IO_LL]) +#define RSCAN0CFDF03LH (RSCAN0.CFDF03.UINT8[R_IO_LH]) +#define RSCAN0CFDF03H (RSCAN0.CFDF03.UINT16[R_IO_H]) +#define RSCAN0CFDF03HL (RSCAN0.CFDF03.UINT8[R_IO_HL]) +#define RSCAN0CFDF03HH (RSCAN0.CFDF03.UINT8[R_IO_HH]) +#define RSCAN0CFDF13 (RSCAN0.CFDF13.UINT32) +#define RSCAN0CFDF13L (RSCAN0.CFDF13.UINT16[R_IO_L]) +#define RSCAN0CFDF13LL (RSCAN0.CFDF13.UINT8[R_IO_LL]) +#define RSCAN0CFDF13LH (RSCAN0.CFDF13.UINT8[R_IO_LH]) +#define RSCAN0CFDF13H (RSCAN0.CFDF13.UINT16[R_IO_H]) +#define RSCAN0CFDF13HL (RSCAN0.CFDF13.UINT8[R_IO_HL]) +#define RSCAN0CFDF13HH (RSCAN0.CFDF13.UINT8[R_IO_HH]) +#define RSCAN0CFID4 (RSCAN0.CFID4.UINT32) +#define RSCAN0CFID4L (RSCAN0.CFID4.UINT16[R_IO_L]) +#define RSCAN0CFID4LL (RSCAN0.CFID4.UINT8[R_IO_LL]) +#define RSCAN0CFID4LH (RSCAN0.CFID4.UINT8[R_IO_LH]) +#define RSCAN0CFID4H (RSCAN0.CFID4.UINT16[R_IO_H]) +#define RSCAN0CFID4HL (RSCAN0.CFID4.UINT8[R_IO_HL]) +#define RSCAN0CFID4HH (RSCAN0.CFID4.UINT8[R_IO_HH]) +#define RSCAN0CFPTR4 (RSCAN0.CFPTR4.UINT32) +#define RSCAN0CFPTR4L (RSCAN0.CFPTR4.UINT16[R_IO_L]) +#define RSCAN0CFPTR4LL (RSCAN0.CFPTR4.UINT8[R_IO_LL]) +#define RSCAN0CFPTR4LH (RSCAN0.CFPTR4.UINT8[R_IO_LH]) +#define RSCAN0CFPTR4H (RSCAN0.CFPTR4.UINT16[R_IO_H]) +#define RSCAN0CFPTR4HL (RSCAN0.CFPTR4.UINT8[R_IO_HL]) +#define RSCAN0CFPTR4HH (RSCAN0.CFPTR4.UINT8[R_IO_HH]) +#define RSCAN0CFDF04 (RSCAN0.CFDF04.UINT32) +#define RSCAN0CFDF04L (RSCAN0.CFDF04.UINT16[R_IO_L]) +#define RSCAN0CFDF04LL (RSCAN0.CFDF04.UINT8[R_IO_LL]) +#define RSCAN0CFDF04LH (RSCAN0.CFDF04.UINT8[R_IO_LH]) +#define RSCAN0CFDF04H (RSCAN0.CFDF04.UINT16[R_IO_H]) +#define RSCAN0CFDF04HL (RSCAN0.CFDF04.UINT8[R_IO_HL]) +#define RSCAN0CFDF04HH (RSCAN0.CFDF04.UINT8[R_IO_HH]) +#define RSCAN0CFDF14 (RSCAN0.CFDF14.UINT32) +#define RSCAN0CFDF14L (RSCAN0.CFDF14.UINT16[R_IO_L]) +#define RSCAN0CFDF14LL (RSCAN0.CFDF14.UINT8[R_IO_LL]) +#define RSCAN0CFDF14LH (RSCAN0.CFDF14.UINT8[R_IO_LH]) +#define RSCAN0CFDF14H (RSCAN0.CFDF14.UINT16[R_IO_H]) +#define RSCAN0CFDF14HL (RSCAN0.CFDF14.UINT8[R_IO_HL]) +#define RSCAN0CFDF14HH (RSCAN0.CFDF14.UINT8[R_IO_HH]) +#define RSCAN0CFID5 (RSCAN0.CFID5.UINT32) +#define RSCAN0CFID5L (RSCAN0.CFID5.UINT16[R_IO_L]) +#define RSCAN0CFID5LL (RSCAN0.CFID5.UINT8[R_IO_LL]) +#define RSCAN0CFID5LH (RSCAN0.CFID5.UINT8[R_IO_LH]) +#define RSCAN0CFID5H (RSCAN0.CFID5.UINT16[R_IO_H]) +#define RSCAN0CFID5HL (RSCAN0.CFID5.UINT8[R_IO_HL]) +#define RSCAN0CFID5HH (RSCAN0.CFID5.UINT8[R_IO_HH]) +#define RSCAN0CFPTR5 (RSCAN0.CFPTR5.UINT32) +#define RSCAN0CFPTR5L (RSCAN0.CFPTR5.UINT16[R_IO_L]) +#define RSCAN0CFPTR5LL (RSCAN0.CFPTR5.UINT8[R_IO_LL]) +#define RSCAN0CFPTR5LH (RSCAN0.CFPTR5.UINT8[R_IO_LH]) +#define RSCAN0CFPTR5H (RSCAN0.CFPTR5.UINT16[R_IO_H]) +#define RSCAN0CFPTR5HL (RSCAN0.CFPTR5.UINT8[R_IO_HL]) +#define RSCAN0CFPTR5HH (RSCAN0.CFPTR5.UINT8[R_IO_HH]) +#define RSCAN0CFDF05 (RSCAN0.CFDF05.UINT32) +#define RSCAN0CFDF05L (RSCAN0.CFDF05.UINT16[R_IO_L]) +#define RSCAN0CFDF05LL (RSCAN0.CFDF05.UINT8[R_IO_LL]) +#define RSCAN0CFDF05LH (RSCAN0.CFDF05.UINT8[R_IO_LH]) +#define RSCAN0CFDF05H (RSCAN0.CFDF05.UINT16[R_IO_H]) +#define RSCAN0CFDF05HL (RSCAN0.CFDF05.UINT8[R_IO_HL]) +#define RSCAN0CFDF05HH (RSCAN0.CFDF05.UINT8[R_IO_HH]) +#define RSCAN0CFDF15 (RSCAN0.CFDF15.UINT32) +#define RSCAN0CFDF15L (RSCAN0.CFDF15.UINT16[R_IO_L]) +#define RSCAN0CFDF15LL (RSCAN0.CFDF15.UINT8[R_IO_LL]) +#define RSCAN0CFDF15LH (RSCAN0.CFDF15.UINT8[R_IO_LH]) +#define RSCAN0CFDF15H (RSCAN0.CFDF15.UINT16[R_IO_H]) +#define RSCAN0CFDF15HL (RSCAN0.CFDF15.UINT8[R_IO_HL]) +#define RSCAN0CFDF15HH (RSCAN0.CFDF15.UINT8[R_IO_HH]) +#define RSCAN0CFID6 (RSCAN0.CFID6.UINT32) +#define RSCAN0CFID6L (RSCAN0.CFID6.UINT16[R_IO_L]) +#define RSCAN0CFID6LL (RSCAN0.CFID6.UINT8[R_IO_LL]) +#define RSCAN0CFID6LH (RSCAN0.CFID6.UINT8[R_IO_LH]) +#define RSCAN0CFID6H (RSCAN0.CFID6.UINT16[R_IO_H]) +#define RSCAN0CFID6HL (RSCAN0.CFID6.UINT8[R_IO_HL]) +#define RSCAN0CFID6HH (RSCAN0.CFID6.UINT8[R_IO_HH]) +#define RSCAN0CFPTR6 (RSCAN0.CFPTR6.UINT32) +#define RSCAN0CFPTR6L (RSCAN0.CFPTR6.UINT16[R_IO_L]) +#define RSCAN0CFPTR6LL (RSCAN0.CFPTR6.UINT8[R_IO_LL]) +#define RSCAN0CFPTR6LH (RSCAN0.CFPTR6.UINT8[R_IO_LH]) +#define RSCAN0CFPTR6H (RSCAN0.CFPTR6.UINT16[R_IO_H]) +#define RSCAN0CFPTR6HL (RSCAN0.CFPTR6.UINT8[R_IO_HL]) +#define RSCAN0CFPTR6HH (RSCAN0.CFPTR6.UINT8[R_IO_HH]) +#define RSCAN0CFDF06 (RSCAN0.CFDF06.UINT32) +#define RSCAN0CFDF06L (RSCAN0.CFDF06.UINT16[R_IO_L]) +#define RSCAN0CFDF06LL (RSCAN0.CFDF06.UINT8[R_IO_LL]) +#define RSCAN0CFDF06LH (RSCAN0.CFDF06.UINT8[R_IO_LH]) +#define RSCAN0CFDF06H (RSCAN0.CFDF06.UINT16[R_IO_H]) +#define RSCAN0CFDF06HL (RSCAN0.CFDF06.UINT8[R_IO_HL]) +#define RSCAN0CFDF06HH (RSCAN0.CFDF06.UINT8[R_IO_HH]) +#define RSCAN0CFDF16 (RSCAN0.CFDF16.UINT32) +#define RSCAN0CFDF16L (RSCAN0.CFDF16.UINT16[R_IO_L]) +#define RSCAN0CFDF16LL (RSCAN0.CFDF16.UINT8[R_IO_LL]) +#define RSCAN0CFDF16LH (RSCAN0.CFDF16.UINT8[R_IO_LH]) +#define RSCAN0CFDF16H (RSCAN0.CFDF16.UINT16[R_IO_H]) +#define RSCAN0CFDF16HL (RSCAN0.CFDF16.UINT8[R_IO_HL]) +#define RSCAN0CFDF16HH (RSCAN0.CFDF16.UINT8[R_IO_HH]) +#define RSCAN0CFID7 (RSCAN0.CFID7.UINT32) +#define RSCAN0CFID7L (RSCAN0.CFID7.UINT16[R_IO_L]) +#define RSCAN0CFID7LL (RSCAN0.CFID7.UINT8[R_IO_LL]) +#define RSCAN0CFID7LH (RSCAN0.CFID7.UINT8[R_IO_LH]) +#define RSCAN0CFID7H (RSCAN0.CFID7.UINT16[R_IO_H]) +#define RSCAN0CFID7HL (RSCAN0.CFID7.UINT8[R_IO_HL]) +#define RSCAN0CFID7HH (RSCAN0.CFID7.UINT8[R_IO_HH]) +#define RSCAN0CFPTR7 (RSCAN0.CFPTR7.UINT32) +#define RSCAN0CFPTR7L (RSCAN0.CFPTR7.UINT16[R_IO_L]) +#define RSCAN0CFPTR7LL (RSCAN0.CFPTR7.UINT8[R_IO_LL]) +#define RSCAN0CFPTR7LH (RSCAN0.CFPTR7.UINT8[R_IO_LH]) +#define RSCAN0CFPTR7H (RSCAN0.CFPTR7.UINT16[R_IO_H]) +#define RSCAN0CFPTR7HL (RSCAN0.CFPTR7.UINT8[R_IO_HL]) +#define RSCAN0CFPTR7HH (RSCAN0.CFPTR7.UINT8[R_IO_HH]) +#define RSCAN0CFDF07 (RSCAN0.CFDF07.UINT32) +#define RSCAN0CFDF07L (RSCAN0.CFDF07.UINT16[R_IO_L]) +#define RSCAN0CFDF07LL (RSCAN0.CFDF07.UINT8[R_IO_LL]) +#define RSCAN0CFDF07LH (RSCAN0.CFDF07.UINT8[R_IO_LH]) +#define RSCAN0CFDF07H (RSCAN0.CFDF07.UINT16[R_IO_H]) +#define RSCAN0CFDF07HL (RSCAN0.CFDF07.UINT8[R_IO_HL]) +#define RSCAN0CFDF07HH (RSCAN0.CFDF07.UINT8[R_IO_HH]) +#define RSCAN0CFDF17 (RSCAN0.CFDF17.UINT32) +#define RSCAN0CFDF17L (RSCAN0.CFDF17.UINT16[R_IO_L]) +#define RSCAN0CFDF17LL (RSCAN0.CFDF17.UINT8[R_IO_LL]) +#define RSCAN0CFDF17LH (RSCAN0.CFDF17.UINT8[R_IO_LH]) +#define RSCAN0CFDF17H (RSCAN0.CFDF17.UINT16[R_IO_H]) +#define RSCAN0CFDF17HL (RSCAN0.CFDF17.UINT8[R_IO_HL]) +#define RSCAN0CFDF17HH (RSCAN0.CFDF17.UINT8[R_IO_HH]) +#define RSCAN0CFID8 (RSCAN0.CFID8.UINT32) +#define RSCAN0CFID8L (RSCAN0.CFID8.UINT16[R_IO_L]) +#define RSCAN0CFID8LL (RSCAN0.CFID8.UINT8[R_IO_LL]) +#define RSCAN0CFID8LH (RSCAN0.CFID8.UINT8[R_IO_LH]) +#define RSCAN0CFID8H (RSCAN0.CFID8.UINT16[R_IO_H]) +#define RSCAN0CFID8HL (RSCAN0.CFID8.UINT8[R_IO_HL]) +#define RSCAN0CFID8HH (RSCAN0.CFID8.UINT8[R_IO_HH]) +#define RSCAN0CFPTR8 (RSCAN0.CFPTR8.UINT32) +#define RSCAN0CFPTR8L (RSCAN0.CFPTR8.UINT16[R_IO_L]) +#define RSCAN0CFPTR8LL (RSCAN0.CFPTR8.UINT8[R_IO_LL]) +#define RSCAN0CFPTR8LH (RSCAN0.CFPTR8.UINT8[R_IO_LH]) +#define RSCAN0CFPTR8H (RSCAN0.CFPTR8.UINT16[R_IO_H]) +#define RSCAN0CFPTR8HL (RSCAN0.CFPTR8.UINT8[R_IO_HL]) +#define RSCAN0CFPTR8HH (RSCAN0.CFPTR8.UINT8[R_IO_HH]) +#define RSCAN0CFDF08 (RSCAN0.CFDF08.UINT32) +#define RSCAN0CFDF08L (RSCAN0.CFDF08.UINT16[R_IO_L]) +#define RSCAN0CFDF08LL (RSCAN0.CFDF08.UINT8[R_IO_LL]) +#define RSCAN0CFDF08LH (RSCAN0.CFDF08.UINT8[R_IO_LH]) +#define RSCAN0CFDF08H (RSCAN0.CFDF08.UINT16[R_IO_H]) +#define RSCAN0CFDF08HL (RSCAN0.CFDF08.UINT8[R_IO_HL]) +#define RSCAN0CFDF08HH (RSCAN0.CFDF08.UINT8[R_IO_HH]) +#define RSCAN0CFDF18 (RSCAN0.CFDF18.UINT32) +#define RSCAN0CFDF18L (RSCAN0.CFDF18.UINT16[R_IO_L]) +#define RSCAN0CFDF18LL (RSCAN0.CFDF18.UINT8[R_IO_LL]) +#define RSCAN0CFDF18LH (RSCAN0.CFDF18.UINT8[R_IO_LH]) +#define RSCAN0CFDF18H (RSCAN0.CFDF18.UINT16[R_IO_H]) +#define RSCAN0CFDF18HL (RSCAN0.CFDF18.UINT8[R_IO_HL]) +#define RSCAN0CFDF18HH (RSCAN0.CFDF18.UINT8[R_IO_HH]) +#define RSCAN0CFID9 (RSCAN0.CFID9.UINT32) +#define RSCAN0CFID9L (RSCAN0.CFID9.UINT16[R_IO_L]) +#define RSCAN0CFID9LL (RSCAN0.CFID9.UINT8[R_IO_LL]) +#define RSCAN0CFID9LH (RSCAN0.CFID9.UINT8[R_IO_LH]) +#define RSCAN0CFID9H (RSCAN0.CFID9.UINT16[R_IO_H]) +#define RSCAN0CFID9HL (RSCAN0.CFID9.UINT8[R_IO_HL]) +#define RSCAN0CFID9HH (RSCAN0.CFID9.UINT8[R_IO_HH]) +#define RSCAN0CFPTR9 (RSCAN0.CFPTR9.UINT32) +#define RSCAN0CFPTR9L (RSCAN0.CFPTR9.UINT16[R_IO_L]) +#define RSCAN0CFPTR9LL (RSCAN0.CFPTR9.UINT8[R_IO_LL]) +#define RSCAN0CFPTR9LH (RSCAN0.CFPTR9.UINT8[R_IO_LH]) +#define RSCAN0CFPTR9H (RSCAN0.CFPTR9.UINT16[R_IO_H]) +#define RSCAN0CFPTR9HL (RSCAN0.CFPTR9.UINT8[R_IO_HL]) +#define RSCAN0CFPTR9HH (RSCAN0.CFPTR9.UINT8[R_IO_HH]) +#define RSCAN0CFDF09 (RSCAN0.CFDF09.UINT32) +#define RSCAN0CFDF09L (RSCAN0.CFDF09.UINT16[R_IO_L]) +#define RSCAN0CFDF09LL (RSCAN0.CFDF09.UINT8[R_IO_LL]) +#define RSCAN0CFDF09LH (RSCAN0.CFDF09.UINT8[R_IO_LH]) +#define RSCAN0CFDF09H (RSCAN0.CFDF09.UINT16[R_IO_H]) +#define RSCAN0CFDF09HL (RSCAN0.CFDF09.UINT8[R_IO_HL]) +#define RSCAN0CFDF09HH (RSCAN0.CFDF09.UINT8[R_IO_HH]) +#define RSCAN0CFDF19 (RSCAN0.CFDF19.UINT32) +#define RSCAN0CFDF19L (RSCAN0.CFDF19.UINT16[R_IO_L]) +#define RSCAN0CFDF19LL (RSCAN0.CFDF19.UINT8[R_IO_LL]) +#define RSCAN0CFDF19LH (RSCAN0.CFDF19.UINT8[R_IO_LH]) +#define RSCAN0CFDF19H (RSCAN0.CFDF19.UINT16[R_IO_H]) +#define RSCAN0CFDF19HL (RSCAN0.CFDF19.UINT8[R_IO_HL]) +#define RSCAN0CFDF19HH (RSCAN0.CFDF19.UINT8[R_IO_HH]) +#define RSCAN0CFID10 (RSCAN0.CFID10.UINT32) +#define RSCAN0CFID10L (RSCAN0.CFID10.UINT16[R_IO_L]) +#define RSCAN0CFID10LL (RSCAN0.CFID10.UINT8[R_IO_LL]) +#define RSCAN0CFID10LH (RSCAN0.CFID10.UINT8[R_IO_LH]) +#define RSCAN0CFID10H (RSCAN0.CFID10.UINT16[R_IO_H]) +#define RSCAN0CFID10HL (RSCAN0.CFID10.UINT8[R_IO_HL]) +#define RSCAN0CFID10HH (RSCAN0.CFID10.UINT8[R_IO_HH]) +#define RSCAN0CFPTR10 (RSCAN0.CFPTR10.UINT32) +#define RSCAN0CFPTR10L (RSCAN0.CFPTR10.UINT16[R_IO_L]) +#define RSCAN0CFPTR10LL (RSCAN0.CFPTR10.UINT8[R_IO_LL]) +#define RSCAN0CFPTR10LH (RSCAN0.CFPTR10.UINT8[R_IO_LH]) +#define RSCAN0CFPTR10H (RSCAN0.CFPTR10.UINT16[R_IO_H]) +#define RSCAN0CFPTR10HL (RSCAN0.CFPTR10.UINT8[R_IO_HL]) +#define RSCAN0CFPTR10HH (RSCAN0.CFPTR10.UINT8[R_IO_HH]) +#define RSCAN0CFDF010 (RSCAN0.CFDF010.UINT32) +#define RSCAN0CFDF010L (RSCAN0.CFDF010.UINT16[R_IO_L]) +#define RSCAN0CFDF010LL (RSCAN0.CFDF010.UINT8[R_IO_LL]) +#define RSCAN0CFDF010LH (RSCAN0.CFDF010.UINT8[R_IO_LH]) +#define RSCAN0CFDF010H (RSCAN0.CFDF010.UINT16[R_IO_H]) +#define RSCAN0CFDF010HL (RSCAN0.CFDF010.UINT8[R_IO_HL]) +#define RSCAN0CFDF010HH (RSCAN0.CFDF010.UINT8[R_IO_HH]) +#define RSCAN0CFDF110 (RSCAN0.CFDF110.UINT32) +#define RSCAN0CFDF110L (RSCAN0.CFDF110.UINT16[R_IO_L]) +#define RSCAN0CFDF110LL (RSCAN0.CFDF110.UINT8[R_IO_LL]) +#define RSCAN0CFDF110LH (RSCAN0.CFDF110.UINT8[R_IO_LH]) +#define RSCAN0CFDF110H (RSCAN0.CFDF110.UINT16[R_IO_H]) +#define RSCAN0CFDF110HL (RSCAN0.CFDF110.UINT8[R_IO_HL]) +#define RSCAN0CFDF110HH (RSCAN0.CFDF110.UINT8[R_IO_HH]) +#define RSCAN0CFID11 (RSCAN0.CFID11.UINT32) +#define RSCAN0CFID11L (RSCAN0.CFID11.UINT16[R_IO_L]) +#define RSCAN0CFID11LL (RSCAN0.CFID11.UINT8[R_IO_LL]) +#define RSCAN0CFID11LH (RSCAN0.CFID11.UINT8[R_IO_LH]) +#define RSCAN0CFID11H (RSCAN0.CFID11.UINT16[R_IO_H]) +#define RSCAN0CFID11HL (RSCAN0.CFID11.UINT8[R_IO_HL]) +#define RSCAN0CFID11HH (RSCAN0.CFID11.UINT8[R_IO_HH]) +#define RSCAN0CFPTR11 (RSCAN0.CFPTR11.UINT32) +#define RSCAN0CFPTR11L (RSCAN0.CFPTR11.UINT16[R_IO_L]) +#define RSCAN0CFPTR11LL (RSCAN0.CFPTR11.UINT8[R_IO_LL]) +#define RSCAN0CFPTR11LH (RSCAN0.CFPTR11.UINT8[R_IO_LH]) +#define RSCAN0CFPTR11H (RSCAN0.CFPTR11.UINT16[R_IO_H]) +#define RSCAN0CFPTR11HL (RSCAN0.CFPTR11.UINT8[R_IO_HL]) +#define RSCAN0CFPTR11HH (RSCAN0.CFPTR11.UINT8[R_IO_HH]) +#define RSCAN0CFDF011 (RSCAN0.CFDF011.UINT32) +#define RSCAN0CFDF011L (RSCAN0.CFDF011.UINT16[R_IO_L]) +#define RSCAN0CFDF011LL (RSCAN0.CFDF011.UINT8[R_IO_LL]) +#define RSCAN0CFDF011LH (RSCAN0.CFDF011.UINT8[R_IO_LH]) +#define RSCAN0CFDF011H (RSCAN0.CFDF011.UINT16[R_IO_H]) +#define RSCAN0CFDF011HL (RSCAN0.CFDF011.UINT8[R_IO_HL]) +#define RSCAN0CFDF011HH (RSCAN0.CFDF011.UINT8[R_IO_HH]) +#define RSCAN0CFDF111 (RSCAN0.CFDF111.UINT32) +#define RSCAN0CFDF111L (RSCAN0.CFDF111.UINT16[R_IO_L]) +#define RSCAN0CFDF111LL (RSCAN0.CFDF111.UINT8[R_IO_LL]) +#define RSCAN0CFDF111LH (RSCAN0.CFDF111.UINT8[R_IO_LH]) +#define RSCAN0CFDF111H (RSCAN0.CFDF111.UINT16[R_IO_H]) +#define RSCAN0CFDF111HL (RSCAN0.CFDF111.UINT8[R_IO_HL]) +#define RSCAN0CFDF111HH (RSCAN0.CFDF111.UINT8[R_IO_HH]) +#define RSCAN0CFID12 (RSCAN0.CFID12.UINT32) +#define RSCAN0CFID12L (RSCAN0.CFID12.UINT16[R_IO_L]) +#define RSCAN0CFID12LL (RSCAN0.CFID12.UINT8[R_IO_LL]) +#define RSCAN0CFID12LH (RSCAN0.CFID12.UINT8[R_IO_LH]) +#define RSCAN0CFID12H (RSCAN0.CFID12.UINT16[R_IO_H]) +#define RSCAN0CFID12HL (RSCAN0.CFID12.UINT8[R_IO_HL]) +#define RSCAN0CFID12HH (RSCAN0.CFID12.UINT8[R_IO_HH]) +#define RSCAN0CFPTR12 (RSCAN0.CFPTR12.UINT32) +#define RSCAN0CFPTR12L (RSCAN0.CFPTR12.UINT16[R_IO_L]) +#define RSCAN0CFPTR12LL (RSCAN0.CFPTR12.UINT8[R_IO_LL]) +#define RSCAN0CFPTR12LH (RSCAN0.CFPTR12.UINT8[R_IO_LH]) +#define RSCAN0CFPTR12H (RSCAN0.CFPTR12.UINT16[R_IO_H]) +#define RSCAN0CFPTR12HL (RSCAN0.CFPTR12.UINT8[R_IO_HL]) +#define RSCAN0CFPTR12HH (RSCAN0.CFPTR12.UINT8[R_IO_HH]) +#define RSCAN0CFDF012 (RSCAN0.CFDF012.UINT32) +#define RSCAN0CFDF012L (RSCAN0.CFDF012.UINT16[R_IO_L]) +#define RSCAN0CFDF012LL (RSCAN0.CFDF012.UINT8[R_IO_LL]) +#define RSCAN0CFDF012LH (RSCAN0.CFDF012.UINT8[R_IO_LH]) +#define RSCAN0CFDF012H (RSCAN0.CFDF012.UINT16[R_IO_H]) +#define RSCAN0CFDF012HL (RSCAN0.CFDF012.UINT8[R_IO_HL]) +#define RSCAN0CFDF012HH (RSCAN0.CFDF012.UINT8[R_IO_HH]) +#define RSCAN0CFDF112 (RSCAN0.CFDF112.UINT32) +#define RSCAN0CFDF112L (RSCAN0.CFDF112.UINT16[R_IO_L]) +#define RSCAN0CFDF112LL (RSCAN0.CFDF112.UINT8[R_IO_LL]) +#define RSCAN0CFDF112LH (RSCAN0.CFDF112.UINT8[R_IO_LH]) +#define RSCAN0CFDF112H (RSCAN0.CFDF112.UINT16[R_IO_H]) +#define RSCAN0CFDF112HL (RSCAN0.CFDF112.UINT8[R_IO_HL]) +#define RSCAN0CFDF112HH (RSCAN0.CFDF112.UINT8[R_IO_HH]) +#define RSCAN0CFID13 (RSCAN0.CFID13.UINT32) +#define RSCAN0CFID13L (RSCAN0.CFID13.UINT16[R_IO_L]) +#define RSCAN0CFID13LL (RSCAN0.CFID13.UINT8[R_IO_LL]) +#define RSCAN0CFID13LH (RSCAN0.CFID13.UINT8[R_IO_LH]) +#define RSCAN0CFID13H (RSCAN0.CFID13.UINT16[R_IO_H]) +#define RSCAN0CFID13HL (RSCAN0.CFID13.UINT8[R_IO_HL]) +#define RSCAN0CFID13HH (RSCAN0.CFID13.UINT8[R_IO_HH]) +#define RSCAN0CFPTR13 (RSCAN0.CFPTR13.UINT32) +#define RSCAN0CFPTR13L (RSCAN0.CFPTR13.UINT16[R_IO_L]) +#define RSCAN0CFPTR13LL (RSCAN0.CFPTR13.UINT8[R_IO_LL]) +#define RSCAN0CFPTR13LH (RSCAN0.CFPTR13.UINT8[R_IO_LH]) +#define RSCAN0CFPTR13H (RSCAN0.CFPTR13.UINT16[R_IO_H]) +#define RSCAN0CFPTR13HL (RSCAN0.CFPTR13.UINT8[R_IO_HL]) +#define RSCAN0CFPTR13HH (RSCAN0.CFPTR13.UINT8[R_IO_HH]) +#define RSCAN0CFDF013 (RSCAN0.CFDF013.UINT32) +#define RSCAN0CFDF013L (RSCAN0.CFDF013.UINT16[R_IO_L]) +#define RSCAN0CFDF013LL (RSCAN0.CFDF013.UINT8[R_IO_LL]) +#define RSCAN0CFDF013LH (RSCAN0.CFDF013.UINT8[R_IO_LH]) +#define RSCAN0CFDF013H (RSCAN0.CFDF013.UINT16[R_IO_H]) +#define RSCAN0CFDF013HL (RSCAN0.CFDF013.UINT8[R_IO_HL]) +#define RSCAN0CFDF013HH (RSCAN0.CFDF013.UINT8[R_IO_HH]) +#define RSCAN0CFDF113 (RSCAN0.CFDF113.UINT32) +#define RSCAN0CFDF113L (RSCAN0.CFDF113.UINT16[R_IO_L]) +#define RSCAN0CFDF113LL (RSCAN0.CFDF113.UINT8[R_IO_LL]) +#define RSCAN0CFDF113LH (RSCAN0.CFDF113.UINT8[R_IO_LH]) +#define RSCAN0CFDF113H (RSCAN0.CFDF113.UINT16[R_IO_H]) +#define RSCAN0CFDF113HL (RSCAN0.CFDF113.UINT8[R_IO_HL]) +#define RSCAN0CFDF113HH (RSCAN0.CFDF113.UINT8[R_IO_HH]) +#define RSCAN0CFID14 (RSCAN0.CFID14.UINT32) +#define RSCAN0CFID14L (RSCAN0.CFID14.UINT16[R_IO_L]) +#define RSCAN0CFID14LL (RSCAN0.CFID14.UINT8[R_IO_LL]) +#define RSCAN0CFID14LH (RSCAN0.CFID14.UINT8[R_IO_LH]) +#define RSCAN0CFID14H (RSCAN0.CFID14.UINT16[R_IO_H]) +#define RSCAN0CFID14HL (RSCAN0.CFID14.UINT8[R_IO_HL]) +#define RSCAN0CFID14HH (RSCAN0.CFID14.UINT8[R_IO_HH]) +#define RSCAN0CFPTR14 (RSCAN0.CFPTR14.UINT32) +#define RSCAN0CFPTR14L (RSCAN0.CFPTR14.UINT16[R_IO_L]) +#define RSCAN0CFPTR14LL (RSCAN0.CFPTR14.UINT8[R_IO_LL]) +#define RSCAN0CFPTR14LH (RSCAN0.CFPTR14.UINT8[R_IO_LH]) +#define RSCAN0CFPTR14H (RSCAN0.CFPTR14.UINT16[R_IO_H]) +#define RSCAN0CFPTR14HL (RSCAN0.CFPTR14.UINT8[R_IO_HL]) +#define RSCAN0CFPTR14HH (RSCAN0.CFPTR14.UINT8[R_IO_HH]) +#define RSCAN0CFDF014 (RSCAN0.CFDF014.UINT32) +#define RSCAN0CFDF014L (RSCAN0.CFDF014.UINT16[R_IO_L]) +#define RSCAN0CFDF014LL (RSCAN0.CFDF014.UINT8[R_IO_LL]) +#define RSCAN0CFDF014LH (RSCAN0.CFDF014.UINT8[R_IO_LH]) +#define RSCAN0CFDF014H (RSCAN0.CFDF014.UINT16[R_IO_H]) +#define RSCAN0CFDF014HL (RSCAN0.CFDF014.UINT8[R_IO_HL]) +#define RSCAN0CFDF014HH (RSCAN0.CFDF014.UINT8[R_IO_HH]) +#define RSCAN0CFDF114 (RSCAN0.CFDF114.UINT32) +#define RSCAN0CFDF114L (RSCAN0.CFDF114.UINT16[R_IO_L]) +#define RSCAN0CFDF114LL (RSCAN0.CFDF114.UINT8[R_IO_LL]) +#define RSCAN0CFDF114LH (RSCAN0.CFDF114.UINT8[R_IO_LH]) +#define RSCAN0CFDF114H (RSCAN0.CFDF114.UINT16[R_IO_H]) +#define RSCAN0CFDF114HL (RSCAN0.CFDF114.UINT8[R_IO_HL]) +#define RSCAN0CFDF114HH (RSCAN0.CFDF114.UINT8[R_IO_HH]) +#define RSCAN0TMID0 (RSCAN0.TMID0.UINT32) +#define RSCAN0TMID0L (RSCAN0.TMID0.UINT16[R_IO_L]) +#define RSCAN0TMID0LL (RSCAN0.TMID0.UINT8[R_IO_LL]) +#define RSCAN0TMID0LH (RSCAN0.TMID0.UINT8[R_IO_LH]) +#define RSCAN0TMID0H (RSCAN0.TMID0.UINT16[R_IO_H]) +#define RSCAN0TMID0HL (RSCAN0.TMID0.UINT8[R_IO_HL]) +#define RSCAN0TMID0HH (RSCAN0.TMID0.UINT8[R_IO_HH]) +#define RSCAN0TMPTR0 (RSCAN0.TMPTR0.UINT32) +#define RSCAN0TMPTR0L (RSCAN0.TMPTR0.UINT16[R_IO_L]) +#define RSCAN0TMPTR0LL (RSCAN0.TMPTR0.UINT8[R_IO_LL]) +#define RSCAN0TMPTR0LH (RSCAN0.TMPTR0.UINT8[R_IO_LH]) +#define RSCAN0TMPTR0H (RSCAN0.TMPTR0.UINT16[R_IO_H]) +#define RSCAN0TMPTR0HL (RSCAN0.TMPTR0.UINT8[R_IO_HL]) +#define RSCAN0TMPTR0HH (RSCAN0.TMPTR0.UINT8[R_IO_HH]) +#define RSCAN0TMDF00 (RSCAN0.TMDF00.UINT32) +#define RSCAN0TMDF00L (RSCAN0.TMDF00.UINT16[R_IO_L]) +#define RSCAN0TMDF00LL (RSCAN0.TMDF00.UINT8[R_IO_LL]) +#define RSCAN0TMDF00LH (RSCAN0.TMDF00.UINT8[R_IO_LH]) +#define RSCAN0TMDF00H (RSCAN0.TMDF00.UINT16[R_IO_H]) +#define RSCAN0TMDF00HL (RSCAN0.TMDF00.UINT8[R_IO_HL]) +#define RSCAN0TMDF00HH (RSCAN0.TMDF00.UINT8[R_IO_HH]) +#define RSCAN0TMDF10 (RSCAN0.TMDF10.UINT32) +#define RSCAN0TMDF10L (RSCAN0.TMDF10.UINT16[R_IO_L]) +#define RSCAN0TMDF10LL (RSCAN0.TMDF10.UINT8[R_IO_LL]) +#define RSCAN0TMDF10LH (RSCAN0.TMDF10.UINT8[R_IO_LH]) +#define RSCAN0TMDF10H (RSCAN0.TMDF10.UINT16[R_IO_H]) +#define RSCAN0TMDF10HL (RSCAN0.TMDF10.UINT8[R_IO_HL]) +#define RSCAN0TMDF10HH (RSCAN0.TMDF10.UINT8[R_IO_HH]) +#define RSCAN0TMID1 (RSCAN0.TMID1.UINT32) +#define RSCAN0TMID1L (RSCAN0.TMID1.UINT16[R_IO_L]) +#define RSCAN0TMID1LL (RSCAN0.TMID1.UINT8[R_IO_LL]) +#define RSCAN0TMID1LH (RSCAN0.TMID1.UINT8[R_IO_LH]) +#define RSCAN0TMID1H (RSCAN0.TMID1.UINT16[R_IO_H]) +#define RSCAN0TMID1HL (RSCAN0.TMID1.UINT8[R_IO_HL]) +#define RSCAN0TMID1HH (RSCAN0.TMID1.UINT8[R_IO_HH]) +#define RSCAN0TMPTR1 (RSCAN0.TMPTR1.UINT32) +#define RSCAN0TMPTR1L (RSCAN0.TMPTR1.UINT16[R_IO_L]) +#define RSCAN0TMPTR1LL (RSCAN0.TMPTR1.UINT8[R_IO_LL]) +#define RSCAN0TMPTR1LH (RSCAN0.TMPTR1.UINT8[R_IO_LH]) +#define RSCAN0TMPTR1H (RSCAN0.TMPTR1.UINT16[R_IO_H]) +#define RSCAN0TMPTR1HL (RSCAN0.TMPTR1.UINT8[R_IO_HL]) +#define RSCAN0TMPTR1HH (RSCAN0.TMPTR1.UINT8[R_IO_HH]) +#define RSCAN0TMDF01 (RSCAN0.TMDF01.UINT32) +#define RSCAN0TMDF01L (RSCAN0.TMDF01.UINT16[R_IO_L]) +#define RSCAN0TMDF01LL (RSCAN0.TMDF01.UINT8[R_IO_LL]) +#define RSCAN0TMDF01LH (RSCAN0.TMDF01.UINT8[R_IO_LH]) +#define RSCAN0TMDF01H (RSCAN0.TMDF01.UINT16[R_IO_H]) +#define RSCAN0TMDF01HL (RSCAN0.TMDF01.UINT8[R_IO_HL]) +#define RSCAN0TMDF01HH (RSCAN0.TMDF01.UINT8[R_IO_HH]) +#define RSCAN0TMDF11 (RSCAN0.TMDF11.UINT32) +#define RSCAN0TMDF11L (RSCAN0.TMDF11.UINT16[R_IO_L]) +#define RSCAN0TMDF11LL (RSCAN0.TMDF11.UINT8[R_IO_LL]) +#define RSCAN0TMDF11LH (RSCAN0.TMDF11.UINT8[R_IO_LH]) +#define RSCAN0TMDF11H (RSCAN0.TMDF11.UINT16[R_IO_H]) +#define RSCAN0TMDF11HL (RSCAN0.TMDF11.UINT8[R_IO_HL]) +#define RSCAN0TMDF11HH (RSCAN0.TMDF11.UINT8[R_IO_HH]) +#define RSCAN0TMID2 (RSCAN0.TMID2.UINT32) +#define RSCAN0TMID2L (RSCAN0.TMID2.UINT16[R_IO_L]) +#define RSCAN0TMID2LL (RSCAN0.TMID2.UINT8[R_IO_LL]) +#define RSCAN0TMID2LH (RSCAN0.TMID2.UINT8[R_IO_LH]) +#define RSCAN0TMID2H (RSCAN0.TMID2.UINT16[R_IO_H]) +#define RSCAN0TMID2HL (RSCAN0.TMID2.UINT8[R_IO_HL]) +#define RSCAN0TMID2HH (RSCAN0.TMID2.UINT8[R_IO_HH]) +#define RSCAN0TMPTR2 (RSCAN0.TMPTR2.UINT32) +#define RSCAN0TMPTR2L (RSCAN0.TMPTR2.UINT16[R_IO_L]) +#define RSCAN0TMPTR2LL (RSCAN0.TMPTR2.UINT8[R_IO_LL]) +#define RSCAN0TMPTR2LH (RSCAN0.TMPTR2.UINT8[R_IO_LH]) +#define RSCAN0TMPTR2H (RSCAN0.TMPTR2.UINT16[R_IO_H]) +#define RSCAN0TMPTR2HL (RSCAN0.TMPTR2.UINT8[R_IO_HL]) +#define RSCAN0TMPTR2HH (RSCAN0.TMPTR2.UINT8[R_IO_HH]) +#define RSCAN0TMDF02 (RSCAN0.TMDF02.UINT32) +#define RSCAN0TMDF02L (RSCAN0.TMDF02.UINT16[R_IO_L]) +#define RSCAN0TMDF02LL (RSCAN0.TMDF02.UINT8[R_IO_LL]) +#define RSCAN0TMDF02LH (RSCAN0.TMDF02.UINT8[R_IO_LH]) +#define RSCAN0TMDF02H (RSCAN0.TMDF02.UINT16[R_IO_H]) +#define RSCAN0TMDF02HL (RSCAN0.TMDF02.UINT8[R_IO_HL]) +#define RSCAN0TMDF02HH (RSCAN0.TMDF02.UINT8[R_IO_HH]) +#define RSCAN0TMDF12 (RSCAN0.TMDF12.UINT32) +#define RSCAN0TMDF12L (RSCAN0.TMDF12.UINT16[R_IO_L]) +#define RSCAN0TMDF12LL (RSCAN0.TMDF12.UINT8[R_IO_LL]) +#define RSCAN0TMDF12LH (RSCAN0.TMDF12.UINT8[R_IO_LH]) +#define RSCAN0TMDF12H (RSCAN0.TMDF12.UINT16[R_IO_H]) +#define RSCAN0TMDF12HL (RSCAN0.TMDF12.UINT8[R_IO_HL]) +#define RSCAN0TMDF12HH (RSCAN0.TMDF12.UINT8[R_IO_HH]) +#define RSCAN0TMID3 (RSCAN0.TMID3.UINT32) +#define RSCAN0TMID3L (RSCAN0.TMID3.UINT16[R_IO_L]) +#define RSCAN0TMID3LL (RSCAN0.TMID3.UINT8[R_IO_LL]) +#define RSCAN0TMID3LH (RSCAN0.TMID3.UINT8[R_IO_LH]) +#define RSCAN0TMID3H (RSCAN0.TMID3.UINT16[R_IO_H]) +#define RSCAN0TMID3HL (RSCAN0.TMID3.UINT8[R_IO_HL]) +#define RSCAN0TMID3HH (RSCAN0.TMID3.UINT8[R_IO_HH]) +#define RSCAN0TMPTR3 (RSCAN0.TMPTR3.UINT32) +#define RSCAN0TMPTR3L (RSCAN0.TMPTR3.UINT16[R_IO_L]) +#define RSCAN0TMPTR3LL (RSCAN0.TMPTR3.UINT8[R_IO_LL]) +#define RSCAN0TMPTR3LH (RSCAN0.TMPTR3.UINT8[R_IO_LH]) +#define RSCAN0TMPTR3H (RSCAN0.TMPTR3.UINT16[R_IO_H]) +#define RSCAN0TMPTR3HL (RSCAN0.TMPTR3.UINT8[R_IO_HL]) +#define RSCAN0TMPTR3HH (RSCAN0.TMPTR3.UINT8[R_IO_HH]) +#define RSCAN0TMDF03 (RSCAN0.TMDF03.UINT32) +#define RSCAN0TMDF03L (RSCAN0.TMDF03.UINT16[R_IO_L]) +#define RSCAN0TMDF03LL (RSCAN0.TMDF03.UINT8[R_IO_LL]) +#define RSCAN0TMDF03LH (RSCAN0.TMDF03.UINT8[R_IO_LH]) +#define RSCAN0TMDF03H (RSCAN0.TMDF03.UINT16[R_IO_H]) +#define RSCAN0TMDF03HL (RSCAN0.TMDF03.UINT8[R_IO_HL]) +#define RSCAN0TMDF03HH (RSCAN0.TMDF03.UINT8[R_IO_HH]) +#define RSCAN0TMDF13 (RSCAN0.TMDF13.UINT32) +#define RSCAN0TMDF13L (RSCAN0.TMDF13.UINT16[R_IO_L]) +#define RSCAN0TMDF13LL (RSCAN0.TMDF13.UINT8[R_IO_LL]) +#define RSCAN0TMDF13LH (RSCAN0.TMDF13.UINT8[R_IO_LH]) +#define RSCAN0TMDF13H (RSCAN0.TMDF13.UINT16[R_IO_H]) +#define RSCAN0TMDF13HL (RSCAN0.TMDF13.UINT8[R_IO_HL]) +#define RSCAN0TMDF13HH (RSCAN0.TMDF13.UINT8[R_IO_HH]) +#define RSCAN0TMID4 (RSCAN0.TMID4.UINT32) +#define RSCAN0TMID4L (RSCAN0.TMID4.UINT16[R_IO_L]) +#define RSCAN0TMID4LL (RSCAN0.TMID4.UINT8[R_IO_LL]) +#define RSCAN0TMID4LH (RSCAN0.TMID4.UINT8[R_IO_LH]) +#define RSCAN0TMID4H (RSCAN0.TMID4.UINT16[R_IO_H]) +#define RSCAN0TMID4HL (RSCAN0.TMID4.UINT8[R_IO_HL]) +#define RSCAN0TMID4HH (RSCAN0.TMID4.UINT8[R_IO_HH]) +#define RSCAN0TMPTR4 (RSCAN0.TMPTR4.UINT32) +#define RSCAN0TMPTR4L (RSCAN0.TMPTR4.UINT16[R_IO_L]) +#define RSCAN0TMPTR4LL (RSCAN0.TMPTR4.UINT8[R_IO_LL]) +#define RSCAN0TMPTR4LH (RSCAN0.TMPTR4.UINT8[R_IO_LH]) +#define RSCAN0TMPTR4H (RSCAN0.TMPTR4.UINT16[R_IO_H]) +#define RSCAN0TMPTR4HL (RSCAN0.TMPTR4.UINT8[R_IO_HL]) +#define RSCAN0TMPTR4HH (RSCAN0.TMPTR4.UINT8[R_IO_HH]) +#define RSCAN0TMDF04 (RSCAN0.TMDF04.UINT32) +#define RSCAN0TMDF04L (RSCAN0.TMDF04.UINT16[R_IO_L]) +#define RSCAN0TMDF04LL (RSCAN0.TMDF04.UINT8[R_IO_LL]) +#define RSCAN0TMDF04LH (RSCAN0.TMDF04.UINT8[R_IO_LH]) +#define RSCAN0TMDF04H (RSCAN0.TMDF04.UINT16[R_IO_H]) +#define RSCAN0TMDF04HL (RSCAN0.TMDF04.UINT8[R_IO_HL]) +#define RSCAN0TMDF04HH (RSCAN0.TMDF04.UINT8[R_IO_HH]) +#define RSCAN0TMDF14 (RSCAN0.TMDF14.UINT32) +#define RSCAN0TMDF14L (RSCAN0.TMDF14.UINT16[R_IO_L]) +#define RSCAN0TMDF14LL (RSCAN0.TMDF14.UINT8[R_IO_LL]) +#define RSCAN0TMDF14LH (RSCAN0.TMDF14.UINT8[R_IO_LH]) +#define RSCAN0TMDF14H (RSCAN0.TMDF14.UINT16[R_IO_H]) +#define RSCAN0TMDF14HL (RSCAN0.TMDF14.UINT8[R_IO_HL]) +#define RSCAN0TMDF14HH (RSCAN0.TMDF14.UINT8[R_IO_HH]) +#define RSCAN0TMID5 (RSCAN0.TMID5.UINT32) +#define RSCAN0TMID5L (RSCAN0.TMID5.UINT16[R_IO_L]) +#define RSCAN0TMID5LL (RSCAN0.TMID5.UINT8[R_IO_LL]) +#define RSCAN0TMID5LH (RSCAN0.TMID5.UINT8[R_IO_LH]) +#define RSCAN0TMID5H (RSCAN0.TMID5.UINT16[R_IO_H]) +#define RSCAN0TMID5HL (RSCAN0.TMID5.UINT8[R_IO_HL]) +#define RSCAN0TMID5HH (RSCAN0.TMID5.UINT8[R_IO_HH]) +#define RSCAN0TMPTR5 (RSCAN0.TMPTR5.UINT32) +#define RSCAN0TMPTR5L (RSCAN0.TMPTR5.UINT16[R_IO_L]) +#define RSCAN0TMPTR5LL (RSCAN0.TMPTR5.UINT8[R_IO_LL]) +#define RSCAN0TMPTR5LH (RSCAN0.TMPTR5.UINT8[R_IO_LH]) +#define RSCAN0TMPTR5H (RSCAN0.TMPTR5.UINT16[R_IO_H]) +#define RSCAN0TMPTR5HL (RSCAN0.TMPTR5.UINT8[R_IO_HL]) +#define RSCAN0TMPTR5HH (RSCAN0.TMPTR5.UINT8[R_IO_HH]) +#define RSCAN0TMDF05 (RSCAN0.TMDF05.UINT32) +#define RSCAN0TMDF05L (RSCAN0.TMDF05.UINT16[R_IO_L]) +#define RSCAN0TMDF05LL (RSCAN0.TMDF05.UINT8[R_IO_LL]) +#define RSCAN0TMDF05LH (RSCAN0.TMDF05.UINT8[R_IO_LH]) +#define RSCAN0TMDF05H (RSCAN0.TMDF05.UINT16[R_IO_H]) +#define RSCAN0TMDF05HL (RSCAN0.TMDF05.UINT8[R_IO_HL]) +#define RSCAN0TMDF05HH (RSCAN0.TMDF05.UINT8[R_IO_HH]) +#define RSCAN0TMDF15 (RSCAN0.TMDF15.UINT32) +#define RSCAN0TMDF15L (RSCAN0.TMDF15.UINT16[R_IO_L]) +#define RSCAN0TMDF15LL (RSCAN0.TMDF15.UINT8[R_IO_LL]) +#define RSCAN0TMDF15LH (RSCAN0.TMDF15.UINT8[R_IO_LH]) +#define RSCAN0TMDF15H (RSCAN0.TMDF15.UINT16[R_IO_H]) +#define RSCAN0TMDF15HL (RSCAN0.TMDF15.UINT8[R_IO_HL]) +#define RSCAN0TMDF15HH (RSCAN0.TMDF15.UINT8[R_IO_HH]) +#define RSCAN0TMID6 (RSCAN0.TMID6.UINT32) +#define RSCAN0TMID6L (RSCAN0.TMID6.UINT16[R_IO_L]) +#define RSCAN0TMID6LL (RSCAN0.TMID6.UINT8[R_IO_LL]) +#define RSCAN0TMID6LH (RSCAN0.TMID6.UINT8[R_IO_LH]) +#define RSCAN0TMID6H (RSCAN0.TMID6.UINT16[R_IO_H]) +#define RSCAN0TMID6HL (RSCAN0.TMID6.UINT8[R_IO_HL]) +#define RSCAN0TMID6HH (RSCAN0.TMID6.UINT8[R_IO_HH]) +#define RSCAN0TMPTR6 (RSCAN0.TMPTR6.UINT32) +#define RSCAN0TMPTR6L (RSCAN0.TMPTR6.UINT16[R_IO_L]) +#define RSCAN0TMPTR6LL (RSCAN0.TMPTR6.UINT8[R_IO_LL]) +#define RSCAN0TMPTR6LH (RSCAN0.TMPTR6.UINT8[R_IO_LH]) +#define RSCAN0TMPTR6H (RSCAN0.TMPTR6.UINT16[R_IO_H]) +#define RSCAN0TMPTR6HL (RSCAN0.TMPTR6.UINT8[R_IO_HL]) +#define RSCAN0TMPTR6HH (RSCAN0.TMPTR6.UINT8[R_IO_HH]) +#define RSCAN0TMDF06 (RSCAN0.TMDF06.UINT32) +#define RSCAN0TMDF06L (RSCAN0.TMDF06.UINT16[R_IO_L]) +#define RSCAN0TMDF06LL (RSCAN0.TMDF06.UINT8[R_IO_LL]) +#define RSCAN0TMDF06LH (RSCAN0.TMDF06.UINT8[R_IO_LH]) +#define RSCAN0TMDF06H (RSCAN0.TMDF06.UINT16[R_IO_H]) +#define RSCAN0TMDF06HL (RSCAN0.TMDF06.UINT8[R_IO_HL]) +#define RSCAN0TMDF06HH (RSCAN0.TMDF06.UINT8[R_IO_HH]) +#define RSCAN0TMDF16 (RSCAN0.TMDF16.UINT32) +#define RSCAN0TMDF16L (RSCAN0.TMDF16.UINT16[R_IO_L]) +#define RSCAN0TMDF16LL (RSCAN0.TMDF16.UINT8[R_IO_LL]) +#define RSCAN0TMDF16LH (RSCAN0.TMDF16.UINT8[R_IO_LH]) +#define RSCAN0TMDF16H (RSCAN0.TMDF16.UINT16[R_IO_H]) +#define RSCAN0TMDF16HL (RSCAN0.TMDF16.UINT8[R_IO_HL]) +#define RSCAN0TMDF16HH (RSCAN0.TMDF16.UINT8[R_IO_HH]) +#define RSCAN0TMID7 (RSCAN0.TMID7.UINT32) +#define RSCAN0TMID7L (RSCAN0.TMID7.UINT16[R_IO_L]) +#define RSCAN0TMID7LL (RSCAN0.TMID7.UINT8[R_IO_LL]) +#define RSCAN0TMID7LH (RSCAN0.TMID7.UINT8[R_IO_LH]) +#define RSCAN0TMID7H (RSCAN0.TMID7.UINT16[R_IO_H]) +#define RSCAN0TMID7HL (RSCAN0.TMID7.UINT8[R_IO_HL]) +#define RSCAN0TMID7HH (RSCAN0.TMID7.UINT8[R_IO_HH]) +#define RSCAN0TMPTR7 (RSCAN0.TMPTR7.UINT32) +#define RSCAN0TMPTR7L (RSCAN0.TMPTR7.UINT16[R_IO_L]) +#define RSCAN0TMPTR7LL (RSCAN0.TMPTR7.UINT8[R_IO_LL]) +#define RSCAN0TMPTR7LH (RSCAN0.TMPTR7.UINT8[R_IO_LH]) +#define RSCAN0TMPTR7H (RSCAN0.TMPTR7.UINT16[R_IO_H]) +#define RSCAN0TMPTR7HL (RSCAN0.TMPTR7.UINT8[R_IO_HL]) +#define RSCAN0TMPTR7HH (RSCAN0.TMPTR7.UINT8[R_IO_HH]) +#define RSCAN0TMDF07 (RSCAN0.TMDF07.UINT32) +#define RSCAN0TMDF07L (RSCAN0.TMDF07.UINT16[R_IO_L]) +#define RSCAN0TMDF07LL (RSCAN0.TMDF07.UINT8[R_IO_LL]) +#define RSCAN0TMDF07LH (RSCAN0.TMDF07.UINT8[R_IO_LH]) +#define RSCAN0TMDF07H (RSCAN0.TMDF07.UINT16[R_IO_H]) +#define RSCAN0TMDF07HL (RSCAN0.TMDF07.UINT8[R_IO_HL]) +#define RSCAN0TMDF07HH (RSCAN0.TMDF07.UINT8[R_IO_HH]) +#define RSCAN0TMDF17 (RSCAN0.TMDF17.UINT32) +#define RSCAN0TMDF17L (RSCAN0.TMDF17.UINT16[R_IO_L]) +#define RSCAN0TMDF17LL (RSCAN0.TMDF17.UINT8[R_IO_LL]) +#define RSCAN0TMDF17LH (RSCAN0.TMDF17.UINT8[R_IO_LH]) +#define RSCAN0TMDF17H (RSCAN0.TMDF17.UINT16[R_IO_H]) +#define RSCAN0TMDF17HL (RSCAN0.TMDF17.UINT8[R_IO_HL]) +#define RSCAN0TMDF17HH (RSCAN0.TMDF17.UINT8[R_IO_HH]) +#define RSCAN0TMID8 (RSCAN0.TMID8.UINT32) +#define RSCAN0TMID8L (RSCAN0.TMID8.UINT16[R_IO_L]) +#define RSCAN0TMID8LL (RSCAN0.TMID8.UINT8[R_IO_LL]) +#define RSCAN0TMID8LH (RSCAN0.TMID8.UINT8[R_IO_LH]) +#define RSCAN0TMID8H (RSCAN0.TMID8.UINT16[R_IO_H]) +#define RSCAN0TMID8HL (RSCAN0.TMID8.UINT8[R_IO_HL]) +#define RSCAN0TMID8HH (RSCAN0.TMID8.UINT8[R_IO_HH]) +#define RSCAN0TMPTR8 (RSCAN0.TMPTR8.UINT32) +#define RSCAN0TMPTR8L (RSCAN0.TMPTR8.UINT16[R_IO_L]) +#define RSCAN0TMPTR8LL (RSCAN0.TMPTR8.UINT8[R_IO_LL]) +#define RSCAN0TMPTR8LH (RSCAN0.TMPTR8.UINT8[R_IO_LH]) +#define RSCAN0TMPTR8H (RSCAN0.TMPTR8.UINT16[R_IO_H]) +#define RSCAN0TMPTR8HL (RSCAN0.TMPTR8.UINT8[R_IO_HL]) +#define RSCAN0TMPTR8HH (RSCAN0.TMPTR8.UINT8[R_IO_HH]) +#define RSCAN0TMDF08 (RSCAN0.TMDF08.UINT32) +#define RSCAN0TMDF08L (RSCAN0.TMDF08.UINT16[R_IO_L]) +#define RSCAN0TMDF08LL (RSCAN0.TMDF08.UINT8[R_IO_LL]) +#define RSCAN0TMDF08LH (RSCAN0.TMDF08.UINT8[R_IO_LH]) +#define RSCAN0TMDF08H (RSCAN0.TMDF08.UINT16[R_IO_H]) +#define RSCAN0TMDF08HL (RSCAN0.TMDF08.UINT8[R_IO_HL]) +#define RSCAN0TMDF08HH (RSCAN0.TMDF08.UINT8[R_IO_HH]) +#define RSCAN0TMDF18 (RSCAN0.TMDF18.UINT32) +#define RSCAN0TMDF18L (RSCAN0.TMDF18.UINT16[R_IO_L]) +#define RSCAN0TMDF18LL (RSCAN0.TMDF18.UINT8[R_IO_LL]) +#define RSCAN0TMDF18LH (RSCAN0.TMDF18.UINT8[R_IO_LH]) +#define RSCAN0TMDF18H (RSCAN0.TMDF18.UINT16[R_IO_H]) +#define RSCAN0TMDF18HL (RSCAN0.TMDF18.UINT8[R_IO_HL]) +#define RSCAN0TMDF18HH (RSCAN0.TMDF18.UINT8[R_IO_HH]) +#define RSCAN0TMID9 (RSCAN0.TMID9.UINT32) +#define RSCAN0TMID9L (RSCAN0.TMID9.UINT16[R_IO_L]) +#define RSCAN0TMID9LL (RSCAN0.TMID9.UINT8[R_IO_LL]) +#define RSCAN0TMID9LH (RSCAN0.TMID9.UINT8[R_IO_LH]) +#define RSCAN0TMID9H (RSCAN0.TMID9.UINT16[R_IO_H]) +#define RSCAN0TMID9HL (RSCAN0.TMID9.UINT8[R_IO_HL]) +#define RSCAN0TMID9HH (RSCAN0.TMID9.UINT8[R_IO_HH]) +#define RSCAN0TMPTR9 (RSCAN0.TMPTR9.UINT32) +#define RSCAN0TMPTR9L (RSCAN0.TMPTR9.UINT16[R_IO_L]) +#define RSCAN0TMPTR9LL (RSCAN0.TMPTR9.UINT8[R_IO_LL]) +#define RSCAN0TMPTR9LH (RSCAN0.TMPTR9.UINT8[R_IO_LH]) +#define RSCAN0TMPTR9H (RSCAN0.TMPTR9.UINT16[R_IO_H]) +#define RSCAN0TMPTR9HL (RSCAN0.TMPTR9.UINT8[R_IO_HL]) +#define RSCAN0TMPTR9HH (RSCAN0.TMPTR9.UINT8[R_IO_HH]) +#define RSCAN0TMDF09 (RSCAN0.TMDF09.UINT32) +#define RSCAN0TMDF09L (RSCAN0.TMDF09.UINT16[R_IO_L]) +#define RSCAN0TMDF09LL (RSCAN0.TMDF09.UINT8[R_IO_LL]) +#define RSCAN0TMDF09LH (RSCAN0.TMDF09.UINT8[R_IO_LH]) +#define RSCAN0TMDF09H (RSCAN0.TMDF09.UINT16[R_IO_H]) +#define RSCAN0TMDF09HL (RSCAN0.TMDF09.UINT8[R_IO_HL]) +#define RSCAN0TMDF09HH (RSCAN0.TMDF09.UINT8[R_IO_HH]) +#define RSCAN0TMDF19 (RSCAN0.TMDF19.UINT32) +#define RSCAN0TMDF19L (RSCAN0.TMDF19.UINT16[R_IO_L]) +#define RSCAN0TMDF19LL (RSCAN0.TMDF19.UINT8[R_IO_LL]) +#define RSCAN0TMDF19LH (RSCAN0.TMDF19.UINT8[R_IO_LH]) +#define RSCAN0TMDF19H (RSCAN0.TMDF19.UINT16[R_IO_H]) +#define RSCAN0TMDF19HL (RSCAN0.TMDF19.UINT8[R_IO_HL]) +#define RSCAN0TMDF19HH (RSCAN0.TMDF19.UINT8[R_IO_HH]) +#define RSCAN0TMID10 (RSCAN0.TMID10.UINT32) +#define RSCAN0TMID10L (RSCAN0.TMID10.UINT16[R_IO_L]) +#define RSCAN0TMID10LL (RSCAN0.TMID10.UINT8[R_IO_LL]) +#define RSCAN0TMID10LH (RSCAN0.TMID10.UINT8[R_IO_LH]) +#define RSCAN0TMID10H (RSCAN0.TMID10.UINT16[R_IO_H]) +#define RSCAN0TMID10HL (RSCAN0.TMID10.UINT8[R_IO_HL]) +#define RSCAN0TMID10HH (RSCAN0.TMID10.UINT8[R_IO_HH]) +#define RSCAN0TMPTR10 (RSCAN0.TMPTR10.UINT32) +#define RSCAN0TMPTR10L (RSCAN0.TMPTR10.UINT16[R_IO_L]) +#define RSCAN0TMPTR10LL (RSCAN0.TMPTR10.UINT8[R_IO_LL]) +#define RSCAN0TMPTR10LH (RSCAN0.TMPTR10.UINT8[R_IO_LH]) +#define RSCAN0TMPTR10H (RSCAN0.TMPTR10.UINT16[R_IO_H]) +#define RSCAN0TMPTR10HL (RSCAN0.TMPTR10.UINT8[R_IO_HL]) +#define RSCAN0TMPTR10HH (RSCAN0.TMPTR10.UINT8[R_IO_HH]) +#define RSCAN0TMDF010 (RSCAN0.TMDF010.UINT32) +#define RSCAN0TMDF010L (RSCAN0.TMDF010.UINT16[R_IO_L]) +#define RSCAN0TMDF010LL (RSCAN0.TMDF010.UINT8[R_IO_LL]) +#define RSCAN0TMDF010LH (RSCAN0.TMDF010.UINT8[R_IO_LH]) +#define RSCAN0TMDF010H (RSCAN0.TMDF010.UINT16[R_IO_H]) +#define RSCAN0TMDF010HL (RSCAN0.TMDF010.UINT8[R_IO_HL]) +#define RSCAN0TMDF010HH (RSCAN0.TMDF010.UINT8[R_IO_HH]) +#define RSCAN0TMDF110 (RSCAN0.TMDF110.UINT32) +#define RSCAN0TMDF110L (RSCAN0.TMDF110.UINT16[R_IO_L]) +#define RSCAN0TMDF110LL (RSCAN0.TMDF110.UINT8[R_IO_LL]) +#define RSCAN0TMDF110LH (RSCAN0.TMDF110.UINT8[R_IO_LH]) +#define RSCAN0TMDF110H (RSCAN0.TMDF110.UINT16[R_IO_H]) +#define RSCAN0TMDF110HL (RSCAN0.TMDF110.UINT8[R_IO_HL]) +#define RSCAN0TMDF110HH (RSCAN0.TMDF110.UINT8[R_IO_HH]) +#define RSCAN0TMID11 (RSCAN0.TMID11.UINT32) +#define RSCAN0TMID11L (RSCAN0.TMID11.UINT16[R_IO_L]) +#define RSCAN0TMID11LL (RSCAN0.TMID11.UINT8[R_IO_LL]) +#define RSCAN0TMID11LH (RSCAN0.TMID11.UINT8[R_IO_LH]) +#define RSCAN0TMID11H (RSCAN0.TMID11.UINT16[R_IO_H]) +#define RSCAN0TMID11HL (RSCAN0.TMID11.UINT8[R_IO_HL]) +#define RSCAN0TMID11HH (RSCAN0.TMID11.UINT8[R_IO_HH]) +#define RSCAN0TMPTR11 (RSCAN0.TMPTR11.UINT32) +#define RSCAN0TMPTR11L (RSCAN0.TMPTR11.UINT16[R_IO_L]) +#define RSCAN0TMPTR11LL (RSCAN0.TMPTR11.UINT8[R_IO_LL]) +#define RSCAN0TMPTR11LH (RSCAN0.TMPTR11.UINT8[R_IO_LH]) +#define RSCAN0TMPTR11H (RSCAN0.TMPTR11.UINT16[R_IO_H]) +#define RSCAN0TMPTR11HL (RSCAN0.TMPTR11.UINT8[R_IO_HL]) +#define RSCAN0TMPTR11HH (RSCAN0.TMPTR11.UINT8[R_IO_HH]) +#define RSCAN0TMDF011 (RSCAN0.TMDF011.UINT32) +#define RSCAN0TMDF011L (RSCAN0.TMDF011.UINT16[R_IO_L]) +#define RSCAN0TMDF011LL (RSCAN0.TMDF011.UINT8[R_IO_LL]) +#define RSCAN0TMDF011LH (RSCAN0.TMDF011.UINT8[R_IO_LH]) +#define RSCAN0TMDF011H (RSCAN0.TMDF011.UINT16[R_IO_H]) +#define RSCAN0TMDF011HL (RSCAN0.TMDF011.UINT8[R_IO_HL]) +#define RSCAN0TMDF011HH (RSCAN0.TMDF011.UINT8[R_IO_HH]) +#define RSCAN0TMDF111 (RSCAN0.TMDF111.UINT32) +#define RSCAN0TMDF111L (RSCAN0.TMDF111.UINT16[R_IO_L]) +#define RSCAN0TMDF111LL (RSCAN0.TMDF111.UINT8[R_IO_LL]) +#define RSCAN0TMDF111LH (RSCAN0.TMDF111.UINT8[R_IO_LH]) +#define RSCAN0TMDF111H (RSCAN0.TMDF111.UINT16[R_IO_H]) +#define RSCAN0TMDF111HL (RSCAN0.TMDF111.UINT8[R_IO_HL]) +#define RSCAN0TMDF111HH (RSCAN0.TMDF111.UINT8[R_IO_HH]) +#define RSCAN0TMID12 (RSCAN0.TMID12.UINT32) +#define RSCAN0TMID12L (RSCAN0.TMID12.UINT16[R_IO_L]) +#define RSCAN0TMID12LL (RSCAN0.TMID12.UINT8[R_IO_LL]) +#define RSCAN0TMID12LH (RSCAN0.TMID12.UINT8[R_IO_LH]) +#define RSCAN0TMID12H (RSCAN0.TMID12.UINT16[R_IO_H]) +#define RSCAN0TMID12HL (RSCAN0.TMID12.UINT8[R_IO_HL]) +#define RSCAN0TMID12HH (RSCAN0.TMID12.UINT8[R_IO_HH]) +#define RSCAN0TMPTR12 (RSCAN0.TMPTR12.UINT32) +#define RSCAN0TMPTR12L (RSCAN0.TMPTR12.UINT16[R_IO_L]) +#define RSCAN0TMPTR12LL (RSCAN0.TMPTR12.UINT8[R_IO_LL]) +#define RSCAN0TMPTR12LH (RSCAN0.TMPTR12.UINT8[R_IO_LH]) +#define RSCAN0TMPTR12H (RSCAN0.TMPTR12.UINT16[R_IO_H]) +#define RSCAN0TMPTR12HL (RSCAN0.TMPTR12.UINT8[R_IO_HL]) +#define RSCAN0TMPTR12HH (RSCAN0.TMPTR12.UINT8[R_IO_HH]) +#define RSCAN0TMDF012 (RSCAN0.TMDF012.UINT32) +#define RSCAN0TMDF012L (RSCAN0.TMDF012.UINT16[R_IO_L]) +#define RSCAN0TMDF012LL (RSCAN0.TMDF012.UINT8[R_IO_LL]) +#define RSCAN0TMDF012LH (RSCAN0.TMDF012.UINT8[R_IO_LH]) +#define RSCAN0TMDF012H (RSCAN0.TMDF012.UINT16[R_IO_H]) +#define RSCAN0TMDF012HL (RSCAN0.TMDF012.UINT8[R_IO_HL]) +#define RSCAN0TMDF012HH (RSCAN0.TMDF012.UINT8[R_IO_HH]) +#define RSCAN0TMDF112 (RSCAN0.TMDF112.UINT32) +#define RSCAN0TMDF112L (RSCAN0.TMDF112.UINT16[R_IO_L]) +#define RSCAN0TMDF112LL (RSCAN0.TMDF112.UINT8[R_IO_LL]) +#define RSCAN0TMDF112LH (RSCAN0.TMDF112.UINT8[R_IO_LH]) +#define RSCAN0TMDF112H (RSCAN0.TMDF112.UINT16[R_IO_H]) +#define RSCAN0TMDF112HL (RSCAN0.TMDF112.UINT8[R_IO_HL]) +#define RSCAN0TMDF112HH (RSCAN0.TMDF112.UINT8[R_IO_HH]) +#define RSCAN0TMID13 (RSCAN0.TMID13.UINT32) +#define RSCAN0TMID13L (RSCAN0.TMID13.UINT16[R_IO_L]) +#define RSCAN0TMID13LL (RSCAN0.TMID13.UINT8[R_IO_LL]) +#define RSCAN0TMID13LH (RSCAN0.TMID13.UINT8[R_IO_LH]) +#define RSCAN0TMID13H (RSCAN0.TMID13.UINT16[R_IO_H]) +#define RSCAN0TMID13HL (RSCAN0.TMID13.UINT8[R_IO_HL]) +#define RSCAN0TMID13HH (RSCAN0.TMID13.UINT8[R_IO_HH]) +#define RSCAN0TMPTR13 (RSCAN0.TMPTR13.UINT32) +#define RSCAN0TMPTR13L (RSCAN0.TMPTR13.UINT16[R_IO_L]) +#define RSCAN0TMPTR13LL (RSCAN0.TMPTR13.UINT8[R_IO_LL]) +#define RSCAN0TMPTR13LH (RSCAN0.TMPTR13.UINT8[R_IO_LH]) +#define RSCAN0TMPTR13H (RSCAN0.TMPTR13.UINT16[R_IO_H]) +#define RSCAN0TMPTR13HL (RSCAN0.TMPTR13.UINT8[R_IO_HL]) +#define RSCAN0TMPTR13HH (RSCAN0.TMPTR13.UINT8[R_IO_HH]) +#define RSCAN0TMDF013 (RSCAN0.TMDF013.UINT32) +#define RSCAN0TMDF013L (RSCAN0.TMDF013.UINT16[R_IO_L]) +#define RSCAN0TMDF013LL (RSCAN0.TMDF013.UINT8[R_IO_LL]) +#define RSCAN0TMDF013LH (RSCAN0.TMDF013.UINT8[R_IO_LH]) +#define RSCAN0TMDF013H (RSCAN0.TMDF013.UINT16[R_IO_H]) +#define RSCAN0TMDF013HL (RSCAN0.TMDF013.UINT8[R_IO_HL]) +#define RSCAN0TMDF013HH (RSCAN0.TMDF013.UINT8[R_IO_HH]) +#define RSCAN0TMDF113 (RSCAN0.TMDF113.UINT32) +#define RSCAN0TMDF113L (RSCAN0.TMDF113.UINT16[R_IO_L]) +#define RSCAN0TMDF113LL (RSCAN0.TMDF113.UINT8[R_IO_LL]) +#define RSCAN0TMDF113LH (RSCAN0.TMDF113.UINT8[R_IO_LH]) +#define RSCAN0TMDF113H (RSCAN0.TMDF113.UINT16[R_IO_H]) +#define RSCAN0TMDF113HL (RSCAN0.TMDF113.UINT8[R_IO_HL]) +#define RSCAN0TMDF113HH (RSCAN0.TMDF113.UINT8[R_IO_HH]) +#define RSCAN0TMID14 (RSCAN0.TMID14.UINT32) +#define RSCAN0TMID14L (RSCAN0.TMID14.UINT16[R_IO_L]) +#define RSCAN0TMID14LL (RSCAN0.TMID14.UINT8[R_IO_LL]) +#define RSCAN0TMID14LH (RSCAN0.TMID14.UINT8[R_IO_LH]) +#define RSCAN0TMID14H (RSCAN0.TMID14.UINT16[R_IO_H]) +#define RSCAN0TMID14HL (RSCAN0.TMID14.UINT8[R_IO_HL]) +#define RSCAN0TMID14HH (RSCAN0.TMID14.UINT8[R_IO_HH]) +#define RSCAN0TMPTR14 (RSCAN0.TMPTR14.UINT32) +#define RSCAN0TMPTR14L (RSCAN0.TMPTR14.UINT16[R_IO_L]) +#define RSCAN0TMPTR14LL (RSCAN0.TMPTR14.UINT8[R_IO_LL]) +#define RSCAN0TMPTR14LH (RSCAN0.TMPTR14.UINT8[R_IO_LH]) +#define RSCAN0TMPTR14H (RSCAN0.TMPTR14.UINT16[R_IO_H]) +#define RSCAN0TMPTR14HL (RSCAN0.TMPTR14.UINT8[R_IO_HL]) +#define RSCAN0TMPTR14HH (RSCAN0.TMPTR14.UINT8[R_IO_HH]) +#define RSCAN0TMDF014 (RSCAN0.TMDF014.UINT32) +#define RSCAN0TMDF014L (RSCAN0.TMDF014.UINT16[R_IO_L]) +#define RSCAN0TMDF014LL (RSCAN0.TMDF014.UINT8[R_IO_LL]) +#define RSCAN0TMDF014LH (RSCAN0.TMDF014.UINT8[R_IO_LH]) +#define RSCAN0TMDF014H (RSCAN0.TMDF014.UINT16[R_IO_H]) +#define RSCAN0TMDF014HL (RSCAN0.TMDF014.UINT8[R_IO_HL]) +#define RSCAN0TMDF014HH (RSCAN0.TMDF014.UINT8[R_IO_HH]) +#define RSCAN0TMDF114 (RSCAN0.TMDF114.UINT32) +#define RSCAN0TMDF114L (RSCAN0.TMDF114.UINT16[R_IO_L]) +#define RSCAN0TMDF114LL (RSCAN0.TMDF114.UINT8[R_IO_LL]) +#define RSCAN0TMDF114LH (RSCAN0.TMDF114.UINT8[R_IO_LH]) +#define RSCAN0TMDF114H (RSCAN0.TMDF114.UINT16[R_IO_H]) +#define RSCAN0TMDF114HL (RSCAN0.TMDF114.UINT8[R_IO_HL]) +#define RSCAN0TMDF114HH (RSCAN0.TMDF114.UINT8[R_IO_HH]) +#define RSCAN0TMID15 (RSCAN0.TMID15.UINT32) +#define RSCAN0TMID15L (RSCAN0.TMID15.UINT16[R_IO_L]) +#define RSCAN0TMID15LL (RSCAN0.TMID15.UINT8[R_IO_LL]) +#define RSCAN0TMID15LH (RSCAN0.TMID15.UINT8[R_IO_LH]) +#define RSCAN0TMID15H (RSCAN0.TMID15.UINT16[R_IO_H]) +#define RSCAN0TMID15HL (RSCAN0.TMID15.UINT8[R_IO_HL]) +#define RSCAN0TMID15HH (RSCAN0.TMID15.UINT8[R_IO_HH]) +#define RSCAN0TMPTR15 (RSCAN0.TMPTR15.UINT32) +#define RSCAN0TMPTR15L (RSCAN0.TMPTR15.UINT16[R_IO_L]) +#define RSCAN0TMPTR15LL (RSCAN0.TMPTR15.UINT8[R_IO_LL]) +#define RSCAN0TMPTR15LH (RSCAN0.TMPTR15.UINT8[R_IO_LH]) +#define RSCAN0TMPTR15H (RSCAN0.TMPTR15.UINT16[R_IO_H]) +#define RSCAN0TMPTR15HL (RSCAN0.TMPTR15.UINT8[R_IO_HL]) +#define RSCAN0TMPTR15HH (RSCAN0.TMPTR15.UINT8[R_IO_HH]) +#define RSCAN0TMDF015 (RSCAN0.TMDF015.UINT32) +#define RSCAN0TMDF015L (RSCAN0.TMDF015.UINT16[R_IO_L]) +#define RSCAN0TMDF015LL (RSCAN0.TMDF015.UINT8[R_IO_LL]) +#define RSCAN0TMDF015LH (RSCAN0.TMDF015.UINT8[R_IO_LH]) +#define RSCAN0TMDF015H (RSCAN0.TMDF015.UINT16[R_IO_H]) +#define RSCAN0TMDF015HL (RSCAN0.TMDF015.UINT8[R_IO_HL]) +#define RSCAN0TMDF015HH (RSCAN0.TMDF015.UINT8[R_IO_HH]) +#define RSCAN0TMDF115 (RSCAN0.TMDF115.UINT32) +#define RSCAN0TMDF115L (RSCAN0.TMDF115.UINT16[R_IO_L]) +#define RSCAN0TMDF115LL (RSCAN0.TMDF115.UINT8[R_IO_LL]) +#define RSCAN0TMDF115LH (RSCAN0.TMDF115.UINT8[R_IO_LH]) +#define RSCAN0TMDF115H (RSCAN0.TMDF115.UINT16[R_IO_H]) +#define RSCAN0TMDF115HL (RSCAN0.TMDF115.UINT8[R_IO_HL]) +#define RSCAN0TMDF115HH (RSCAN0.TMDF115.UINT8[R_IO_HH]) +#define RSCAN0TMID16 (RSCAN0.TMID16.UINT32) +#define RSCAN0TMID16L (RSCAN0.TMID16.UINT16[R_IO_L]) +#define RSCAN0TMID16LL (RSCAN0.TMID16.UINT8[R_IO_LL]) +#define RSCAN0TMID16LH (RSCAN0.TMID16.UINT8[R_IO_LH]) +#define RSCAN0TMID16H (RSCAN0.TMID16.UINT16[R_IO_H]) +#define RSCAN0TMID16HL (RSCAN0.TMID16.UINT8[R_IO_HL]) +#define RSCAN0TMID16HH (RSCAN0.TMID16.UINT8[R_IO_HH]) +#define RSCAN0TMPTR16 (RSCAN0.TMPTR16.UINT32) +#define RSCAN0TMPTR16L (RSCAN0.TMPTR16.UINT16[R_IO_L]) +#define RSCAN0TMPTR16LL (RSCAN0.TMPTR16.UINT8[R_IO_LL]) +#define RSCAN0TMPTR16LH (RSCAN0.TMPTR16.UINT8[R_IO_LH]) +#define RSCAN0TMPTR16H (RSCAN0.TMPTR16.UINT16[R_IO_H]) +#define RSCAN0TMPTR16HL (RSCAN0.TMPTR16.UINT8[R_IO_HL]) +#define RSCAN0TMPTR16HH (RSCAN0.TMPTR16.UINT8[R_IO_HH]) +#define RSCAN0TMDF016 (RSCAN0.TMDF016.UINT32) +#define RSCAN0TMDF016L (RSCAN0.TMDF016.UINT16[R_IO_L]) +#define RSCAN0TMDF016LL (RSCAN0.TMDF016.UINT8[R_IO_LL]) +#define RSCAN0TMDF016LH (RSCAN0.TMDF016.UINT8[R_IO_LH]) +#define RSCAN0TMDF016H (RSCAN0.TMDF016.UINT16[R_IO_H]) +#define RSCAN0TMDF016HL (RSCAN0.TMDF016.UINT8[R_IO_HL]) +#define RSCAN0TMDF016HH (RSCAN0.TMDF016.UINT8[R_IO_HH]) +#define RSCAN0TMDF116 (RSCAN0.TMDF116.UINT32) +#define RSCAN0TMDF116L (RSCAN0.TMDF116.UINT16[R_IO_L]) +#define RSCAN0TMDF116LL (RSCAN0.TMDF116.UINT8[R_IO_LL]) +#define RSCAN0TMDF116LH (RSCAN0.TMDF116.UINT8[R_IO_LH]) +#define RSCAN0TMDF116H (RSCAN0.TMDF116.UINT16[R_IO_H]) +#define RSCAN0TMDF116HL (RSCAN0.TMDF116.UINT8[R_IO_HL]) +#define RSCAN0TMDF116HH (RSCAN0.TMDF116.UINT8[R_IO_HH]) +#define RSCAN0TMID17 (RSCAN0.TMID17.UINT32) +#define RSCAN0TMID17L (RSCAN0.TMID17.UINT16[R_IO_L]) +#define RSCAN0TMID17LL (RSCAN0.TMID17.UINT8[R_IO_LL]) +#define RSCAN0TMID17LH (RSCAN0.TMID17.UINT8[R_IO_LH]) +#define RSCAN0TMID17H (RSCAN0.TMID17.UINT16[R_IO_H]) +#define RSCAN0TMID17HL (RSCAN0.TMID17.UINT8[R_IO_HL]) +#define RSCAN0TMID17HH (RSCAN0.TMID17.UINT8[R_IO_HH]) +#define RSCAN0TMPTR17 (RSCAN0.TMPTR17.UINT32) +#define RSCAN0TMPTR17L (RSCAN0.TMPTR17.UINT16[R_IO_L]) +#define RSCAN0TMPTR17LL (RSCAN0.TMPTR17.UINT8[R_IO_LL]) +#define RSCAN0TMPTR17LH (RSCAN0.TMPTR17.UINT8[R_IO_LH]) +#define RSCAN0TMPTR17H (RSCAN0.TMPTR17.UINT16[R_IO_H]) +#define RSCAN0TMPTR17HL (RSCAN0.TMPTR17.UINT8[R_IO_HL]) +#define RSCAN0TMPTR17HH (RSCAN0.TMPTR17.UINT8[R_IO_HH]) +#define RSCAN0TMDF017 (RSCAN0.TMDF017.UINT32) +#define RSCAN0TMDF017L (RSCAN0.TMDF017.UINT16[R_IO_L]) +#define RSCAN0TMDF017LL (RSCAN0.TMDF017.UINT8[R_IO_LL]) +#define RSCAN0TMDF017LH (RSCAN0.TMDF017.UINT8[R_IO_LH]) +#define RSCAN0TMDF017H (RSCAN0.TMDF017.UINT16[R_IO_H]) +#define RSCAN0TMDF017HL (RSCAN0.TMDF017.UINT8[R_IO_HL]) +#define RSCAN0TMDF017HH (RSCAN0.TMDF017.UINT8[R_IO_HH]) +#define RSCAN0TMDF117 (RSCAN0.TMDF117.UINT32) +#define RSCAN0TMDF117L (RSCAN0.TMDF117.UINT16[R_IO_L]) +#define RSCAN0TMDF117LL (RSCAN0.TMDF117.UINT8[R_IO_LL]) +#define RSCAN0TMDF117LH (RSCAN0.TMDF117.UINT8[R_IO_LH]) +#define RSCAN0TMDF117H (RSCAN0.TMDF117.UINT16[R_IO_H]) +#define RSCAN0TMDF117HL (RSCAN0.TMDF117.UINT8[R_IO_HL]) +#define RSCAN0TMDF117HH (RSCAN0.TMDF117.UINT8[R_IO_HH]) +#define RSCAN0TMID18 (RSCAN0.TMID18.UINT32) +#define RSCAN0TMID18L (RSCAN0.TMID18.UINT16[R_IO_L]) +#define RSCAN0TMID18LL (RSCAN0.TMID18.UINT8[R_IO_LL]) +#define RSCAN0TMID18LH (RSCAN0.TMID18.UINT8[R_IO_LH]) +#define RSCAN0TMID18H (RSCAN0.TMID18.UINT16[R_IO_H]) +#define RSCAN0TMID18HL (RSCAN0.TMID18.UINT8[R_IO_HL]) +#define RSCAN0TMID18HH (RSCAN0.TMID18.UINT8[R_IO_HH]) +#define RSCAN0TMPTR18 (RSCAN0.TMPTR18.UINT32) +#define RSCAN0TMPTR18L (RSCAN0.TMPTR18.UINT16[R_IO_L]) +#define RSCAN0TMPTR18LL (RSCAN0.TMPTR18.UINT8[R_IO_LL]) +#define RSCAN0TMPTR18LH (RSCAN0.TMPTR18.UINT8[R_IO_LH]) +#define RSCAN0TMPTR18H (RSCAN0.TMPTR18.UINT16[R_IO_H]) +#define RSCAN0TMPTR18HL (RSCAN0.TMPTR18.UINT8[R_IO_HL]) +#define RSCAN0TMPTR18HH (RSCAN0.TMPTR18.UINT8[R_IO_HH]) +#define RSCAN0TMDF018 (RSCAN0.TMDF018.UINT32) +#define RSCAN0TMDF018L (RSCAN0.TMDF018.UINT16[R_IO_L]) +#define RSCAN0TMDF018LL (RSCAN0.TMDF018.UINT8[R_IO_LL]) +#define RSCAN0TMDF018LH (RSCAN0.TMDF018.UINT8[R_IO_LH]) +#define RSCAN0TMDF018H (RSCAN0.TMDF018.UINT16[R_IO_H]) +#define RSCAN0TMDF018HL (RSCAN0.TMDF018.UINT8[R_IO_HL]) +#define RSCAN0TMDF018HH (RSCAN0.TMDF018.UINT8[R_IO_HH]) +#define RSCAN0TMDF118 (RSCAN0.TMDF118.UINT32) +#define RSCAN0TMDF118L (RSCAN0.TMDF118.UINT16[R_IO_L]) +#define RSCAN0TMDF118LL (RSCAN0.TMDF118.UINT8[R_IO_LL]) +#define RSCAN0TMDF118LH (RSCAN0.TMDF118.UINT8[R_IO_LH]) +#define RSCAN0TMDF118H (RSCAN0.TMDF118.UINT16[R_IO_H]) +#define RSCAN0TMDF118HL (RSCAN0.TMDF118.UINT8[R_IO_HL]) +#define RSCAN0TMDF118HH (RSCAN0.TMDF118.UINT8[R_IO_HH]) +#define RSCAN0TMID19 (RSCAN0.TMID19.UINT32) +#define RSCAN0TMID19L (RSCAN0.TMID19.UINT16[R_IO_L]) +#define RSCAN0TMID19LL (RSCAN0.TMID19.UINT8[R_IO_LL]) +#define RSCAN0TMID19LH (RSCAN0.TMID19.UINT8[R_IO_LH]) +#define RSCAN0TMID19H (RSCAN0.TMID19.UINT16[R_IO_H]) +#define RSCAN0TMID19HL (RSCAN0.TMID19.UINT8[R_IO_HL]) +#define RSCAN0TMID19HH (RSCAN0.TMID19.UINT8[R_IO_HH]) +#define RSCAN0TMPTR19 (RSCAN0.TMPTR19.UINT32) +#define RSCAN0TMPTR19L (RSCAN0.TMPTR19.UINT16[R_IO_L]) +#define RSCAN0TMPTR19LL (RSCAN0.TMPTR19.UINT8[R_IO_LL]) +#define RSCAN0TMPTR19LH (RSCAN0.TMPTR19.UINT8[R_IO_LH]) +#define RSCAN0TMPTR19H (RSCAN0.TMPTR19.UINT16[R_IO_H]) +#define RSCAN0TMPTR19HL (RSCAN0.TMPTR19.UINT8[R_IO_HL]) +#define RSCAN0TMPTR19HH (RSCAN0.TMPTR19.UINT8[R_IO_HH]) +#define RSCAN0TMDF019 (RSCAN0.TMDF019.UINT32) +#define RSCAN0TMDF019L (RSCAN0.TMDF019.UINT16[R_IO_L]) +#define RSCAN0TMDF019LL (RSCAN0.TMDF019.UINT8[R_IO_LL]) +#define RSCAN0TMDF019LH (RSCAN0.TMDF019.UINT8[R_IO_LH]) +#define RSCAN0TMDF019H (RSCAN0.TMDF019.UINT16[R_IO_H]) +#define RSCAN0TMDF019HL (RSCAN0.TMDF019.UINT8[R_IO_HL]) +#define RSCAN0TMDF019HH (RSCAN0.TMDF019.UINT8[R_IO_HH]) +#define RSCAN0TMDF119 (RSCAN0.TMDF119.UINT32) +#define RSCAN0TMDF119L (RSCAN0.TMDF119.UINT16[R_IO_L]) +#define RSCAN0TMDF119LL (RSCAN0.TMDF119.UINT8[R_IO_LL]) +#define RSCAN0TMDF119LH (RSCAN0.TMDF119.UINT8[R_IO_LH]) +#define RSCAN0TMDF119H (RSCAN0.TMDF119.UINT16[R_IO_H]) +#define RSCAN0TMDF119HL (RSCAN0.TMDF119.UINT8[R_IO_HL]) +#define RSCAN0TMDF119HH (RSCAN0.TMDF119.UINT8[R_IO_HH]) +#define RSCAN0TMID20 (RSCAN0.TMID20.UINT32) +#define RSCAN0TMID20L (RSCAN0.TMID20.UINT16[R_IO_L]) +#define RSCAN0TMID20LL (RSCAN0.TMID20.UINT8[R_IO_LL]) +#define RSCAN0TMID20LH (RSCAN0.TMID20.UINT8[R_IO_LH]) +#define RSCAN0TMID20H (RSCAN0.TMID20.UINT16[R_IO_H]) +#define RSCAN0TMID20HL (RSCAN0.TMID20.UINT8[R_IO_HL]) +#define RSCAN0TMID20HH (RSCAN0.TMID20.UINT8[R_IO_HH]) +#define RSCAN0TMPTR20 (RSCAN0.TMPTR20.UINT32) +#define RSCAN0TMPTR20L (RSCAN0.TMPTR20.UINT16[R_IO_L]) +#define RSCAN0TMPTR20LL (RSCAN0.TMPTR20.UINT8[R_IO_LL]) +#define RSCAN0TMPTR20LH (RSCAN0.TMPTR20.UINT8[R_IO_LH]) +#define RSCAN0TMPTR20H (RSCAN0.TMPTR20.UINT16[R_IO_H]) +#define RSCAN0TMPTR20HL (RSCAN0.TMPTR20.UINT8[R_IO_HL]) +#define RSCAN0TMPTR20HH (RSCAN0.TMPTR20.UINT8[R_IO_HH]) +#define RSCAN0TMDF020 (RSCAN0.TMDF020.UINT32) +#define RSCAN0TMDF020L (RSCAN0.TMDF020.UINT16[R_IO_L]) +#define RSCAN0TMDF020LL (RSCAN0.TMDF020.UINT8[R_IO_LL]) +#define RSCAN0TMDF020LH (RSCAN0.TMDF020.UINT8[R_IO_LH]) +#define RSCAN0TMDF020H (RSCAN0.TMDF020.UINT16[R_IO_H]) +#define RSCAN0TMDF020HL (RSCAN0.TMDF020.UINT8[R_IO_HL]) +#define RSCAN0TMDF020HH (RSCAN0.TMDF020.UINT8[R_IO_HH]) +#define RSCAN0TMDF120 (RSCAN0.TMDF120.UINT32) +#define RSCAN0TMDF120L (RSCAN0.TMDF120.UINT16[R_IO_L]) +#define RSCAN0TMDF120LL (RSCAN0.TMDF120.UINT8[R_IO_LL]) +#define RSCAN0TMDF120LH (RSCAN0.TMDF120.UINT8[R_IO_LH]) +#define RSCAN0TMDF120H (RSCAN0.TMDF120.UINT16[R_IO_H]) +#define RSCAN0TMDF120HL (RSCAN0.TMDF120.UINT8[R_IO_HL]) +#define RSCAN0TMDF120HH (RSCAN0.TMDF120.UINT8[R_IO_HH]) +#define RSCAN0TMID21 (RSCAN0.TMID21.UINT32) +#define RSCAN0TMID21L (RSCAN0.TMID21.UINT16[R_IO_L]) +#define RSCAN0TMID21LL (RSCAN0.TMID21.UINT8[R_IO_LL]) +#define RSCAN0TMID21LH (RSCAN0.TMID21.UINT8[R_IO_LH]) +#define RSCAN0TMID21H (RSCAN0.TMID21.UINT16[R_IO_H]) +#define RSCAN0TMID21HL (RSCAN0.TMID21.UINT8[R_IO_HL]) +#define RSCAN0TMID21HH (RSCAN0.TMID21.UINT8[R_IO_HH]) +#define RSCAN0TMPTR21 (RSCAN0.TMPTR21.UINT32) +#define RSCAN0TMPTR21L (RSCAN0.TMPTR21.UINT16[R_IO_L]) +#define RSCAN0TMPTR21LL (RSCAN0.TMPTR21.UINT8[R_IO_LL]) +#define RSCAN0TMPTR21LH (RSCAN0.TMPTR21.UINT8[R_IO_LH]) +#define RSCAN0TMPTR21H (RSCAN0.TMPTR21.UINT16[R_IO_H]) +#define RSCAN0TMPTR21HL (RSCAN0.TMPTR21.UINT8[R_IO_HL]) +#define RSCAN0TMPTR21HH (RSCAN0.TMPTR21.UINT8[R_IO_HH]) +#define RSCAN0TMDF021 (RSCAN0.TMDF021.UINT32) +#define RSCAN0TMDF021L (RSCAN0.TMDF021.UINT16[R_IO_L]) +#define RSCAN0TMDF021LL (RSCAN0.TMDF021.UINT8[R_IO_LL]) +#define RSCAN0TMDF021LH (RSCAN0.TMDF021.UINT8[R_IO_LH]) +#define RSCAN0TMDF021H (RSCAN0.TMDF021.UINT16[R_IO_H]) +#define RSCAN0TMDF021HL (RSCAN0.TMDF021.UINT8[R_IO_HL]) +#define RSCAN0TMDF021HH (RSCAN0.TMDF021.UINT8[R_IO_HH]) +#define RSCAN0TMDF121 (RSCAN0.TMDF121.UINT32) +#define RSCAN0TMDF121L (RSCAN0.TMDF121.UINT16[R_IO_L]) +#define RSCAN0TMDF121LL (RSCAN0.TMDF121.UINT8[R_IO_LL]) +#define RSCAN0TMDF121LH (RSCAN0.TMDF121.UINT8[R_IO_LH]) +#define RSCAN0TMDF121H (RSCAN0.TMDF121.UINT16[R_IO_H]) +#define RSCAN0TMDF121HL (RSCAN0.TMDF121.UINT8[R_IO_HL]) +#define RSCAN0TMDF121HH (RSCAN0.TMDF121.UINT8[R_IO_HH]) +#define RSCAN0TMID22 (RSCAN0.TMID22.UINT32) +#define RSCAN0TMID22L (RSCAN0.TMID22.UINT16[R_IO_L]) +#define RSCAN0TMID22LL (RSCAN0.TMID22.UINT8[R_IO_LL]) +#define RSCAN0TMID22LH (RSCAN0.TMID22.UINT8[R_IO_LH]) +#define RSCAN0TMID22H (RSCAN0.TMID22.UINT16[R_IO_H]) +#define RSCAN0TMID22HL (RSCAN0.TMID22.UINT8[R_IO_HL]) +#define RSCAN0TMID22HH (RSCAN0.TMID22.UINT8[R_IO_HH]) +#define RSCAN0TMPTR22 (RSCAN0.TMPTR22.UINT32) +#define RSCAN0TMPTR22L (RSCAN0.TMPTR22.UINT16[R_IO_L]) +#define RSCAN0TMPTR22LL (RSCAN0.TMPTR22.UINT8[R_IO_LL]) +#define RSCAN0TMPTR22LH (RSCAN0.TMPTR22.UINT8[R_IO_LH]) +#define RSCAN0TMPTR22H (RSCAN0.TMPTR22.UINT16[R_IO_H]) +#define RSCAN0TMPTR22HL (RSCAN0.TMPTR22.UINT8[R_IO_HL]) +#define RSCAN0TMPTR22HH (RSCAN0.TMPTR22.UINT8[R_IO_HH]) +#define RSCAN0TMDF022 (RSCAN0.TMDF022.UINT32) +#define RSCAN0TMDF022L (RSCAN0.TMDF022.UINT16[R_IO_L]) +#define RSCAN0TMDF022LL (RSCAN0.TMDF022.UINT8[R_IO_LL]) +#define RSCAN0TMDF022LH (RSCAN0.TMDF022.UINT8[R_IO_LH]) +#define RSCAN0TMDF022H (RSCAN0.TMDF022.UINT16[R_IO_H]) +#define RSCAN0TMDF022HL (RSCAN0.TMDF022.UINT8[R_IO_HL]) +#define RSCAN0TMDF022HH (RSCAN0.TMDF022.UINT8[R_IO_HH]) +#define RSCAN0TMDF122 (RSCAN0.TMDF122.UINT32) +#define RSCAN0TMDF122L (RSCAN0.TMDF122.UINT16[R_IO_L]) +#define RSCAN0TMDF122LL (RSCAN0.TMDF122.UINT8[R_IO_LL]) +#define RSCAN0TMDF122LH (RSCAN0.TMDF122.UINT8[R_IO_LH]) +#define RSCAN0TMDF122H (RSCAN0.TMDF122.UINT16[R_IO_H]) +#define RSCAN0TMDF122HL (RSCAN0.TMDF122.UINT8[R_IO_HL]) +#define RSCAN0TMDF122HH (RSCAN0.TMDF122.UINT8[R_IO_HH]) +#define RSCAN0TMID23 (RSCAN0.TMID23.UINT32) +#define RSCAN0TMID23L (RSCAN0.TMID23.UINT16[R_IO_L]) +#define RSCAN0TMID23LL (RSCAN0.TMID23.UINT8[R_IO_LL]) +#define RSCAN0TMID23LH (RSCAN0.TMID23.UINT8[R_IO_LH]) +#define RSCAN0TMID23H (RSCAN0.TMID23.UINT16[R_IO_H]) +#define RSCAN0TMID23HL (RSCAN0.TMID23.UINT8[R_IO_HL]) +#define RSCAN0TMID23HH (RSCAN0.TMID23.UINT8[R_IO_HH]) +#define RSCAN0TMPTR23 (RSCAN0.TMPTR23.UINT32) +#define RSCAN0TMPTR23L (RSCAN0.TMPTR23.UINT16[R_IO_L]) +#define RSCAN0TMPTR23LL (RSCAN0.TMPTR23.UINT8[R_IO_LL]) +#define RSCAN0TMPTR23LH (RSCAN0.TMPTR23.UINT8[R_IO_LH]) +#define RSCAN0TMPTR23H (RSCAN0.TMPTR23.UINT16[R_IO_H]) +#define RSCAN0TMPTR23HL (RSCAN0.TMPTR23.UINT8[R_IO_HL]) +#define RSCAN0TMPTR23HH (RSCAN0.TMPTR23.UINT8[R_IO_HH]) +#define RSCAN0TMDF023 (RSCAN0.TMDF023.UINT32) +#define RSCAN0TMDF023L (RSCAN0.TMDF023.UINT16[R_IO_L]) +#define RSCAN0TMDF023LL (RSCAN0.TMDF023.UINT8[R_IO_LL]) +#define RSCAN0TMDF023LH (RSCAN0.TMDF023.UINT8[R_IO_LH]) +#define RSCAN0TMDF023H (RSCAN0.TMDF023.UINT16[R_IO_H]) +#define RSCAN0TMDF023HL (RSCAN0.TMDF023.UINT8[R_IO_HL]) +#define RSCAN0TMDF023HH (RSCAN0.TMDF023.UINT8[R_IO_HH]) +#define RSCAN0TMDF123 (RSCAN0.TMDF123.UINT32) +#define RSCAN0TMDF123L (RSCAN0.TMDF123.UINT16[R_IO_L]) +#define RSCAN0TMDF123LL (RSCAN0.TMDF123.UINT8[R_IO_LL]) +#define RSCAN0TMDF123LH (RSCAN0.TMDF123.UINT8[R_IO_LH]) +#define RSCAN0TMDF123H (RSCAN0.TMDF123.UINT16[R_IO_H]) +#define RSCAN0TMDF123HL (RSCAN0.TMDF123.UINT8[R_IO_HL]) +#define RSCAN0TMDF123HH (RSCAN0.TMDF123.UINT8[R_IO_HH]) +#define RSCAN0TMID24 (RSCAN0.TMID24.UINT32) +#define RSCAN0TMID24L (RSCAN0.TMID24.UINT16[R_IO_L]) +#define RSCAN0TMID24LL (RSCAN0.TMID24.UINT8[R_IO_LL]) +#define RSCAN0TMID24LH (RSCAN0.TMID24.UINT8[R_IO_LH]) +#define RSCAN0TMID24H (RSCAN0.TMID24.UINT16[R_IO_H]) +#define RSCAN0TMID24HL (RSCAN0.TMID24.UINT8[R_IO_HL]) +#define RSCAN0TMID24HH (RSCAN0.TMID24.UINT8[R_IO_HH]) +#define RSCAN0TMPTR24 (RSCAN0.TMPTR24.UINT32) +#define RSCAN0TMPTR24L (RSCAN0.TMPTR24.UINT16[R_IO_L]) +#define RSCAN0TMPTR24LL (RSCAN0.TMPTR24.UINT8[R_IO_LL]) +#define RSCAN0TMPTR24LH (RSCAN0.TMPTR24.UINT8[R_IO_LH]) +#define RSCAN0TMPTR24H (RSCAN0.TMPTR24.UINT16[R_IO_H]) +#define RSCAN0TMPTR24HL (RSCAN0.TMPTR24.UINT8[R_IO_HL]) +#define RSCAN0TMPTR24HH (RSCAN0.TMPTR24.UINT8[R_IO_HH]) +#define RSCAN0TMDF024 (RSCAN0.TMDF024.UINT32) +#define RSCAN0TMDF024L (RSCAN0.TMDF024.UINT16[R_IO_L]) +#define RSCAN0TMDF024LL (RSCAN0.TMDF024.UINT8[R_IO_LL]) +#define RSCAN0TMDF024LH (RSCAN0.TMDF024.UINT8[R_IO_LH]) +#define RSCAN0TMDF024H (RSCAN0.TMDF024.UINT16[R_IO_H]) +#define RSCAN0TMDF024HL (RSCAN0.TMDF024.UINT8[R_IO_HL]) +#define RSCAN0TMDF024HH (RSCAN0.TMDF024.UINT8[R_IO_HH]) +#define RSCAN0TMDF124 (RSCAN0.TMDF124.UINT32) +#define RSCAN0TMDF124L (RSCAN0.TMDF124.UINT16[R_IO_L]) +#define RSCAN0TMDF124LL (RSCAN0.TMDF124.UINT8[R_IO_LL]) +#define RSCAN0TMDF124LH (RSCAN0.TMDF124.UINT8[R_IO_LH]) +#define RSCAN0TMDF124H (RSCAN0.TMDF124.UINT16[R_IO_H]) +#define RSCAN0TMDF124HL (RSCAN0.TMDF124.UINT8[R_IO_HL]) +#define RSCAN0TMDF124HH (RSCAN0.TMDF124.UINT8[R_IO_HH]) +#define RSCAN0TMID25 (RSCAN0.TMID25.UINT32) +#define RSCAN0TMID25L (RSCAN0.TMID25.UINT16[R_IO_L]) +#define RSCAN0TMID25LL (RSCAN0.TMID25.UINT8[R_IO_LL]) +#define RSCAN0TMID25LH (RSCAN0.TMID25.UINT8[R_IO_LH]) +#define RSCAN0TMID25H (RSCAN0.TMID25.UINT16[R_IO_H]) +#define RSCAN0TMID25HL (RSCAN0.TMID25.UINT8[R_IO_HL]) +#define RSCAN0TMID25HH (RSCAN0.TMID25.UINT8[R_IO_HH]) +#define RSCAN0TMPTR25 (RSCAN0.TMPTR25.UINT32) +#define RSCAN0TMPTR25L (RSCAN0.TMPTR25.UINT16[R_IO_L]) +#define RSCAN0TMPTR25LL (RSCAN0.TMPTR25.UINT8[R_IO_LL]) +#define RSCAN0TMPTR25LH (RSCAN0.TMPTR25.UINT8[R_IO_LH]) +#define RSCAN0TMPTR25H (RSCAN0.TMPTR25.UINT16[R_IO_H]) +#define RSCAN0TMPTR25HL (RSCAN0.TMPTR25.UINT8[R_IO_HL]) +#define RSCAN0TMPTR25HH (RSCAN0.TMPTR25.UINT8[R_IO_HH]) +#define RSCAN0TMDF025 (RSCAN0.TMDF025.UINT32) +#define RSCAN0TMDF025L (RSCAN0.TMDF025.UINT16[R_IO_L]) +#define RSCAN0TMDF025LL (RSCAN0.TMDF025.UINT8[R_IO_LL]) +#define RSCAN0TMDF025LH (RSCAN0.TMDF025.UINT8[R_IO_LH]) +#define RSCAN0TMDF025H (RSCAN0.TMDF025.UINT16[R_IO_H]) +#define RSCAN0TMDF025HL (RSCAN0.TMDF025.UINT8[R_IO_HL]) +#define RSCAN0TMDF025HH (RSCAN0.TMDF025.UINT8[R_IO_HH]) +#define RSCAN0TMDF125 (RSCAN0.TMDF125.UINT32) +#define RSCAN0TMDF125L (RSCAN0.TMDF125.UINT16[R_IO_L]) +#define RSCAN0TMDF125LL (RSCAN0.TMDF125.UINT8[R_IO_LL]) +#define RSCAN0TMDF125LH (RSCAN0.TMDF125.UINT8[R_IO_LH]) +#define RSCAN0TMDF125H (RSCAN0.TMDF125.UINT16[R_IO_H]) +#define RSCAN0TMDF125HL (RSCAN0.TMDF125.UINT8[R_IO_HL]) +#define RSCAN0TMDF125HH (RSCAN0.TMDF125.UINT8[R_IO_HH]) +#define RSCAN0TMID26 (RSCAN0.TMID26.UINT32) +#define RSCAN0TMID26L (RSCAN0.TMID26.UINT16[R_IO_L]) +#define RSCAN0TMID26LL (RSCAN0.TMID26.UINT8[R_IO_LL]) +#define RSCAN0TMID26LH (RSCAN0.TMID26.UINT8[R_IO_LH]) +#define RSCAN0TMID26H (RSCAN0.TMID26.UINT16[R_IO_H]) +#define RSCAN0TMID26HL (RSCAN0.TMID26.UINT8[R_IO_HL]) +#define RSCAN0TMID26HH (RSCAN0.TMID26.UINT8[R_IO_HH]) +#define RSCAN0TMPTR26 (RSCAN0.TMPTR26.UINT32) +#define RSCAN0TMPTR26L (RSCAN0.TMPTR26.UINT16[R_IO_L]) +#define RSCAN0TMPTR26LL (RSCAN0.TMPTR26.UINT8[R_IO_LL]) +#define RSCAN0TMPTR26LH (RSCAN0.TMPTR26.UINT8[R_IO_LH]) +#define RSCAN0TMPTR26H (RSCAN0.TMPTR26.UINT16[R_IO_H]) +#define RSCAN0TMPTR26HL (RSCAN0.TMPTR26.UINT8[R_IO_HL]) +#define RSCAN0TMPTR26HH (RSCAN0.TMPTR26.UINT8[R_IO_HH]) +#define RSCAN0TMDF026 (RSCAN0.TMDF026.UINT32) +#define RSCAN0TMDF026L (RSCAN0.TMDF026.UINT16[R_IO_L]) +#define RSCAN0TMDF026LL (RSCAN0.TMDF026.UINT8[R_IO_LL]) +#define RSCAN0TMDF026LH (RSCAN0.TMDF026.UINT8[R_IO_LH]) +#define RSCAN0TMDF026H (RSCAN0.TMDF026.UINT16[R_IO_H]) +#define RSCAN0TMDF026HL (RSCAN0.TMDF026.UINT8[R_IO_HL]) +#define RSCAN0TMDF026HH (RSCAN0.TMDF026.UINT8[R_IO_HH]) +#define RSCAN0TMDF126 (RSCAN0.TMDF126.UINT32) +#define RSCAN0TMDF126L (RSCAN0.TMDF126.UINT16[R_IO_L]) +#define RSCAN0TMDF126LL (RSCAN0.TMDF126.UINT8[R_IO_LL]) +#define RSCAN0TMDF126LH (RSCAN0.TMDF126.UINT8[R_IO_LH]) +#define RSCAN0TMDF126H (RSCAN0.TMDF126.UINT16[R_IO_H]) +#define RSCAN0TMDF126HL (RSCAN0.TMDF126.UINT8[R_IO_HL]) +#define RSCAN0TMDF126HH (RSCAN0.TMDF126.UINT8[R_IO_HH]) +#define RSCAN0TMID27 (RSCAN0.TMID27.UINT32) +#define RSCAN0TMID27L (RSCAN0.TMID27.UINT16[R_IO_L]) +#define RSCAN0TMID27LL (RSCAN0.TMID27.UINT8[R_IO_LL]) +#define RSCAN0TMID27LH (RSCAN0.TMID27.UINT8[R_IO_LH]) +#define RSCAN0TMID27H (RSCAN0.TMID27.UINT16[R_IO_H]) +#define RSCAN0TMID27HL (RSCAN0.TMID27.UINT8[R_IO_HL]) +#define RSCAN0TMID27HH (RSCAN0.TMID27.UINT8[R_IO_HH]) +#define RSCAN0TMPTR27 (RSCAN0.TMPTR27.UINT32) +#define RSCAN0TMPTR27L (RSCAN0.TMPTR27.UINT16[R_IO_L]) +#define RSCAN0TMPTR27LL (RSCAN0.TMPTR27.UINT8[R_IO_LL]) +#define RSCAN0TMPTR27LH (RSCAN0.TMPTR27.UINT8[R_IO_LH]) +#define RSCAN0TMPTR27H (RSCAN0.TMPTR27.UINT16[R_IO_H]) +#define RSCAN0TMPTR27HL (RSCAN0.TMPTR27.UINT8[R_IO_HL]) +#define RSCAN0TMPTR27HH (RSCAN0.TMPTR27.UINT8[R_IO_HH]) +#define RSCAN0TMDF027 (RSCAN0.TMDF027.UINT32) +#define RSCAN0TMDF027L (RSCAN0.TMDF027.UINT16[R_IO_L]) +#define RSCAN0TMDF027LL (RSCAN0.TMDF027.UINT8[R_IO_LL]) +#define RSCAN0TMDF027LH (RSCAN0.TMDF027.UINT8[R_IO_LH]) +#define RSCAN0TMDF027H (RSCAN0.TMDF027.UINT16[R_IO_H]) +#define RSCAN0TMDF027HL (RSCAN0.TMDF027.UINT8[R_IO_HL]) +#define RSCAN0TMDF027HH (RSCAN0.TMDF027.UINT8[R_IO_HH]) +#define RSCAN0TMDF127 (RSCAN0.TMDF127.UINT32) +#define RSCAN0TMDF127L (RSCAN0.TMDF127.UINT16[R_IO_L]) +#define RSCAN0TMDF127LL (RSCAN0.TMDF127.UINT8[R_IO_LL]) +#define RSCAN0TMDF127LH (RSCAN0.TMDF127.UINT8[R_IO_LH]) +#define RSCAN0TMDF127H (RSCAN0.TMDF127.UINT16[R_IO_H]) +#define RSCAN0TMDF127HL (RSCAN0.TMDF127.UINT8[R_IO_HL]) +#define RSCAN0TMDF127HH (RSCAN0.TMDF127.UINT8[R_IO_HH]) +#define RSCAN0TMID28 (RSCAN0.TMID28.UINT32) +#define RSCAN0TMID28L (RSCAN0.TMID28.UINT16[R_IO_L]) +#define RSCAN0TMID28LL (RSCAN0.TMID28.UINT8[R_IO_LL]) +#define RSCAN0TMID28LH (RSCAN0.TMID28.UINT8[R_IO_LH]) +#define RSCAN0TMID28H (RSCAN0.TMID28.UINT16[R_IO_H]) +#define RSCAN0TMID28HL (RSCAN0.TMID28.UINT8[R_IO_HL]) +#define RSCAN0TMID28HH (RSCAN0.TMID28.UINT8[R_IO_HH]) +#define RSCAN0TMPTR28 (RSCAN0.TMPTR28.UINT32) +#define RSCAN0TMPTR28L (RSCAN0.TMPTR28.UINT16[R_IO_L]) +#define RSCAN0TMPTR28LL (RSCAN0.TMPTR28.UINT8[R_IO_LL]) +#define RSCAN0TMPTR28LH (RSCAN0.TMPTR28.UINT8[R_IO_LH]) +#define RSCAN0TMPTR28H (RSCAN0.TMPTR28.UINT16[R_IO_H]) +#define RSCAN0TMPTR28HL (RSCAN0.TMPTR28.UINT8[R_IO_HL]) +#define RSCAN0TMPTR28HH (RSCAN0.TMPTR28.UINT8[R_IO_HH]) +#define RSCAN0TMDF028 (RSCAN0.TMDF028.UINT32) +#define RSCAN0TMDF028L (RSCAN0.TMDF028.UINT16[R_IO_L]) +#define RSCAN0TMDF028LL (RSCAN0.TMDF028.UINT8[R_IO_LL]) +#define RSCAN0TMDF028LH (RSCAN0.TMDF028.UINT8[R_IO_LH]) +#define RSCAN0TMDF028H (RSCAN0.TMDF028.UINT16[R_IO_H]) +#define RSCAN0TMDF028HL (RSCAN0.TMDF028.UINT8[R_IO_HL]) +#define RSCAN0TMDF028HH (RSCAN0.TMDF028.UINT8[R_IO_HH]) +#define RSCAN0TMDF128 (RSCAN0.TMDF128.UINT32) +#define RSCAN0TMDF128L (RSCAN0.TMDF128.UINT16[R_IO_L]) +#define RSCAN0TMDF128LL (RSCAN0.TMDF128.UINT8[R_IO_LL]) +#define RSCAN0TMDF128LH (RSCAN0.TMDF128.UINT8[R_IO_LH]) +#define RSCAN0TMDF128H (RSCAN0.TMDF128.UINT16[R_IO_H]) +#define RSCAN0TMDF128HL (RSCAN0.TMDF128.UINT8[R_IO_HL]) +#define RSCAN0TMDF128HH (RSCAN0.TMDF128.UINT8[R_IO_HH]) +#define RSCAN0TMID29 (RSCAN0.TMID29.UINT32) +#define RSCAN0TMID29L (RSCAN0.TMID29.UINT16[R_IO_L]) +#define RSCAN0TMID29LL (RSCAN0.TMID29.UINT8[R_IO_LL]) +#define RSCAN0TMID29LH (RSCAN0.TMID29.UINT8[R_IO_LH]) +#define RSCAN0TMID29H (RSCAN0.TMID29.UINT16[R_IO_H]) +#define RSCAN0TMID29HL (RSCAN0.TMID29.UINT8[R_IO_HL]) +#define RSCAN0TMID29HH (RSCAN0.TMID29.UINT8[R_IO_HH]) +#define RSCAN0TMPTR29 (RSCAN0.TMPTR29.UINT32) +#define RSCAN0TMPTR29L (RSCAN0.TMPTR29.UINT16[R_IO_L]) +#define RSCAN0TMPTR29LL (RSCAN0.TMPTR29.UINT8[R_IO_LL]) +#define RSCAN0TMPTR29LH (RSCAN0.TMPTR29.UINT8[R_IO_LH]) +#define RSCAN0TMPTR29H (RSCAN0.TMPTR29.UINT16[R_IO_H]) +#define RSCAN0TMPTR29HL (RSCAN0.TMPTR29.UINT8[R_IO_HL]) +#define RSCAN0TMPTR29HH (RSCAN0.TMPTR29.UINT8[R_IO_HH]) +#define RSCAN0TMDF029 (RSCAN0.TMDF029.UINT32) +#define RSCAN0TMDF029L (RSCAN0.TMDF029.UINT16[R_IO_L]) +#define RSCAN0TMDF029LL (RSCAN0.TMDF029.UINT8[R_IO_LL]) +#define RSCAN0TMDF029LH (RSCAN0.TMDF029.UINT8[R_IO_LH]) +#define RSCAN0TMDF029H (RSCAN0.TMDF029.UINT16[R_IO_H]) +#define RSCAN0TMDF029HL (RSCAN0.TMDF029.UINT8[R_IO_HL]) +#define RSCAN0TMDF029HH (RSCAN0.TMDF029.UINT8[R_IO_HH]) +#define RSCAN0TMDF129 (RSCAN0.TMDF129.UINT32) +#define RSCAN0TMDF129L (RSCAN0.TMDF129.UINT16[R_IO_L]) +#define RSCAN0TMDF129LL (RSCAN0.TMDF129.UINT8[R_IO_LL]) +#define RSCAN0TMDF129LH (RSCAN0.TMDF129.UINT8[R_IO_LH]) +#define RSCAN0TMDF129H (RSCAN0.TMDF129.UINT16[R_IO_H]) +#define RSCAN0TMDF129HL (RSCAN0.TMDF129.UINT8[R_IO_HL]) +#define RSCAN0TMDF129HH (RSCAN0.TMDF129.UINT8[R_IO_HH]) +#define RSCAN0TMID30 (RSCAN0.TMID30.UINT32) +#define RSCAN0TMID30L (RSCAN0.TMID30.UINT16[R_IO_L]) +#define RSCAN0TMID30LL (RSCAN0.TMID30.UINT8[R_IO_LL]) +#define RSCAN0TMID30LH (RSCAN0.TMID30.UINT8[R_IO_LH]) +#define RSCAN0TMID30H (RSCAN0.TMID30.UINT16[R_IO_H]) +#define RSCAN0TMID30HL (RSCAN0.TMID30.UINT8[R_IO_HL]) +#define RSCAN0TMID30HH (RSCAN0.TMID30.UINT8[R_IO_HH]) +#define RSCAN0TMPTR30 (RSCAN0.TMPTR30.UINT32) +#define RSCAN0TMPTR30L (RSCAN0.TMPTR30.UINT16[R_IO_L]) +#define RSCAN0TMPTR30LL (RSCAN0.TMPTR30.UINT8[R_IO_LL]) +#define RSCAN0TMPTR30LH (RSCAN0.TMPTR30.UINT8[R_IO_LH]) +#define RSCAN0TMPTR30H (RSCAN0.TMPTR30.UINT16[R_IO_H]) +#define RSCAN0TMPTR30HL (RSCAN0.TMPTR30.UINT8[R_IO_HL]) +#define RSCAN0TMPTR30HH (RSCAN0.TMPTR30.UINT8[R_IO_HH]) +#define RSCAN0TMDF030 (RSCAN0.TMDF030.UINT32) +#define RSCAN0TMDF030L (RSCAN0.TMDF030.UINT16[R_IO_L]) +#define RSCAN0TMDF030LL (RSCAN0.TMDF030.UINT8[R_IO_LL]) +#define RSCAN0TMDF030LH (RSCAN0.TMDF030.UINT8[R_IO_LH]) +#define RSCAN0TMDF030H (RSCAN0.TMDF030.UINT16[R_IO_H]) +#define RSCAN0TMDF030HL (RSCAN0.TMDF030.UINT8[R_IO_HL]) +#define RSCAN0TMDF030HH (RSCAN0.TMDF030.UINT8[R_IO_HH]) +#define RSCAN0TMDF130 (RSCAN0.TMDF130.UINT32) +#define RSCAN0TMDF130L (RSCAN0.TMDF130.UINT16[R_IO_L]) +#define RSCAN0TMDF130LL (RSCAN0.TMDF130.UINT8[R_IO_LL]) +#define RSCAN0TMDF130LH (RSCAN0.TMDF130.UINT8[R_IO_LH]) +#define RSCAN0TMDF130H (RSCAN0.TMDF130.UINT16[R_IO_H]) +#define RSCAN0TMDF130HL (RSCAN0.TMDF130.UINT8[R_IO_HL]) +#define RSCAN0TMDF130HH (RSCAN0.TMDF130.UINT8[R_IO_HH]) +#define RSCAN0TMID31 (RSCAN0.TMID31.UINT32) +#define RSCAN0TMID31L (RSCAN0.TMID31.UINT16[R_IO_L]) +#define RSCAN0TMID31LL (RSCAN0.TMID31.UINT8[R_IO_LL]) +#define RSCAN0TMID31LH (RSCAN0.TMID31.UINT8[R_IO_LH]) +#define RSCAN0TMID31H (RSCAN0.TMID31.UINT16[R_IO_H]) +#define RSCAN0TMID31HL (RSCAN0.TMID31.UINT8[R_IO_HL]) +#define RSCAN0TMID31HH (RSCAN0.TMID31.UINT8[R_IO_HH]) +#define RSCAN0TMPTR31 (RSCAN0.TMPTR31.UINT32) +#define RSCAN0TMPTR31L (RSCAN0.TMPTR31.UINT16[R_IO_L]) +#define RSCAN0TMPTR31LL (RSCAN0.TMPTR31.UINT8[R_IO_LL]) +#define RSCAN0TMPTR31LH (RSCAN0.TMPTR31.UINT8[R_IO_LH]) +#define RSCAN0TMPTR31H (RSCAN0.TMPTR31.UINT16[R_IO_H]) +#define RSCAN0TMPTR31HL (RSCAN0.TMPTR31.UINT8[R_IO_HL]) +#define RSCAN0TMPTR31HH (RSCAN0.TMPTR31.UINT8[R_IO_HH]) +#define RSCAN0TMDF031 (RSCAN0.TMDF031.UINT32) +#define RSCAN0TMDF031L (RSCAN0.TMDF031.UINT16[R_IO_L]) +#define RSCAN0TMDF031LL (RSCAN0.TMDF031.UINT8[R_IO_LL]) +#define RSCAN0TMDF031LH (RSCAN0.TMDF031.UINT8[R_IO_LH]) +#define RSCAN0TMDF031H (RSCAN0.TMDF031.UINT16[R_IO_H]) +#define RSCAN0TMDF031HL (RSCAN0.TMDF031.UINT8[R_IO_HL]) +#define RSCAN0TMDF031HH (RSCAN0.TMDF031.UINT8[R_IO_HH]) +#define RSCAN0TMDF131 (RSCAN0.TMDF131.UINT32) +#define RSCAN0TMDF131L (RSCAN0.TMDF131.UINT16[R_IO_L]) +#define RSCAN0TMDF131LL (RSCAN0.TMDF131.UINT8[R_IO_LL]) +#define RSCAN0TMDF131LH (RSCAN0.TMDF131.UINT8[R_IO_LH]) +#define RSCAN0TMDF131H (RSCAN0.TMDF131.UINT16[R_IO_H]) +#define RSCAN0TMDF131HL (RSCAN0.TMDF131.UINT8[R_IO_HL]) +#define RSCAN0TMDF131HH (RSCAN0.TMDF131.UINT8[R_IO_HH]) +#define RSCAN0TMID32 (RSCAN0.TMID32.UINT32) +#define RSCAN0TMID32L (RSCAN0.TMID32.UINT16[R_IO_L]) +#define RSCAN0TMID32LL (RSCAN0.TMID32.UINT8[R_IO_LL]) +#define RSCAN0TMID32LH (RSCAN0.TMID32.UINT8[R_IO_LH]) +#define RSCAN0TMID32H (RSCAN0.TMID32.UINT16[R_IO_H]) +#define RSCAN0TMID32HL (RSCAN0.TMID32.UINT8[R_IO_HL]) +#define RSCAN0TMID32HH (RSCAN0.TMID32.UINT8[R_IO_HH]) +#define RSCAN0TMPTR32 (RSCAN0.TMPTR32.UINT32) +#define RSCAN0TMPTR32L (RSCAN0.TMPTR32.UINT16[R_IO_L]) +#define RSCAN0TMPTR32LL (RSCAN0.TMPTR32.UINT8[R_IO_LL]) +#define RSCAN0TMPTR32LH (RSCAN0.TMPTR32.UINT8[R_IO_LH]) +#define RSCAN0TMPTR32H (RSCAN0.TMPTR32.UINT16[R_IO_H]) +#define RSCAN0TMPTR32HL (RSCAN0.TMPTR32.UINT8[R_IO_HL]) +#define RSCAN0TMPTR32HH (RSCAN0.TMPTR32.UINT8[R_IO_HH]) +#define RSCAN0TMDF032 (RSCAN0.TMDF032.UINT32) +#define RSCAN0TMDF032L (RSCAN0.TMDF032.UINT16[R_IO_L]) +#define RSCAN0TMDF032LL (RSCAN0.TMDF032.UINT8[R_IO_LL]) +#define RSCAN0TMDF032LH (RSCAN0.TMDF032.UINT8[R_IO_LH]) +#define RSCAN0TMDF032H (RSCAN0.TMDF032.UINT16[R_IO_H]) +#define RSCAN0TMDF032HL (RSCAN0.TMDF032.UINT8[R_IO_HL]) +#define RSCAN0TMDF032HH (RSCAN0.TMDF032.UINT8[R_IO_HH]) +#define RSCAN0TMDF132 (RSCAN0.TMDF132.UINT32) +#define RSCAN0TMDF132L (RSCAN0.TMDF132.UINT16[R_IO_L]) +#define RSCAN0TMDF132LL (RSCAN0.TMDF132.UINT8[R_IO_LL]) +#define RSCAN0TMDF132LH (RSCAN0.TMDF132.UINT8[R_IO_LH]) +#define RSCAN0TMDF132H (RSCAN0.TMDF132.UINT16[R_IO_H]) +#define RSCAN0TMDF132HL (RSCAN0.TMDF132.UINT8[R_IO_HL]) +#define RSCAN0TMDF132HH (RSCAN0.TMDF132.UINT8[R_IO_HH]) +#define RSCAN0TMID33 (RSCAN0.TMID33.UINT32) +#define RSCAN0TMID33L (RSCAN0.TMID33.UINT16[R_IO_L]) +#define RSCAN0TMID33LL (RSCAN0.TMID33.UINT8[R_IO_LL]) +#define RSCAN0TMID33LH (RSCAN0.TMID33.UINT8[R_IO_LH]) +#define RSCAN0TMID33H (RSCAN0.TMID33.UINT16[R_IO_H]) +#define RSCAN0TMID33HL (RSCAN0.TMID33.UINT8[R_IO_HL]) +#define RSCAN0TMID33HH (RSCAN0.TMID33.UINT8[R_IO_HH]) +#define RSCAN0TMPTR33 (RSCAN0.TMPTR33.UINT32) +#define RSCAN0TMPTR33L (RSCAN0.TMPTR33.UINT16[R_IO_L]) +#define RSCAN0TMPTR33LL (RSCAN0.TMPTR33.UINT8[R_IO_LL]) +#define RSCAN0TMPTR33LH (RSCAN0.TMPTR33.UINT8[R_IO_LH]) +#define RSCAN0TMPTR33H (RSCAN0.TMPTR33.UINT16[R_IO_H]) +#define RSCAN0TMPTR33HL (RSCAN0.TMPTR33.UINT8[R_IO_HL]) +#define RSCAN0TMPTR33HH (RSCAN0.TMPTR33.UINT8[R_IO_HH]) +#define RSCAN0TMDF033 (RSCAN0.TMDF033.UINT32) +#define RSCAN0TMDF033L (RSCAN0.TMDF033.UINT16[R_IO_L]) +#define RSCAN0TMDF033LL (RSCAN0.TMDF033.UINT8[R_IO_LL]) +#define RSCAN0TMDF033LH (RSCAN0.TMDF033.UINT8[R_IO_LH]) +#define RSCAN0TMDF033H (RSCAN0.TMDF033.UINT16[R_IO_H]) +#define RSCAN0TMDF033HL (RSCAN0.TMDF033.UINT8[R_IO_HL]) +#define RSCAN0TMDF033HH (RSCAN0.TMDF033.UINT8[R_IO_HH]) +#define RSCAN0TMDF133 (RSCAN0.TMDF133.UINT32) +#define RSCAN0TMDF133L (RSCAN0.TMDF133.UINT16[R_IO_L]) +#define RSCAN0TMDF133LL (RSCAN0.TMDF133.UINT8[R_IO_LL]) +#define RSCAN0TMDF133LH (RSCAN0.TMDF133.UINT8[R_IO_LH]) +#define RSCAN0TMDF133H (RSCAN0.TMDF133.UINT16[R_IO_H]) +#define RSCAN0TMDF133HL (RSCAN0.TMDF133.UINT8[R_IO_HL]) +#define RSCAN0TMDF133HH (RSCAN0.TMDF133.UINT8[R_IO_HH]) +#define RSCAN0TMID34 (RSCAN0.TMID34.UINT32) +#define RSCAN0TMID34L (RSCAN0.TMID34.UINT16[R_IO_L]) +#define RSCAN0TMID34LL (RSCAN0.TMID34.UINT8[R_IO_LL]) +#define RSCAN0TMID34LH (RSCAN0.TMID34.UINT8[R_IO_LH]) +#define RSCAN0TMID34H (RSCAN0.TMID34.UINT16[R_IO_H]) +#define RSCAN0TMID34HL (RSCAN0.TMID34.UINT8[R_IO_HL]) +#define RSCAN0TMID34HH (RSCAN0.TMID34.UINT8[R_IO_HH]) +#define RSCAN0TMPTR34 (RSCAN0.TMPTR34.UINT32) +#define RSCAN0TMPTR34L (RSCAN0.TMPTR34.UINT16[R_IO_L]) +#define RSCAN0TMPTR34LL (RSCAN0.TMPTR34.UINT8[R_IO_LL]) +#define RSCAN0TMPTR34LH (RSCAN0.TMPTR34.UINT8[R_IO_LH]) +#define RSCAN0TMPTR34H (RSCAN0.TMPTR34.UINT16[R_IO_H]) +#define RSCAN0TMPTR34HL (RSCAN0.TMPTR34.UINT8[R_IO_HL]) +#define RSCAN0TMPTR34HH (RSCAN0.TMPTR34.UINT8[R_IO_HH]) +#define RSCAN0TMDF034 (RSCAN0.TMDF034.UINT32) +#define RSCAN0TMDF034L (RSCAN0.TMDF034.UINT16[R_IO_L]) +#define RSCAN0TMDF034LL (RSCAN0.TMDF034.UINT8[R_IO_LL]) +#define RSCAN0TMDF034LH (RSCAN0.TMDF034.UINT8[R_IO_LH]) +#define RSCAN0TMDF034H (RSCAN0.TMDF034.UINT16[R_IO_H]) +#define RSCAN0TMDF034HL (RSCAN0.TMDF034.UINT8[R_IO_HL]) +#define RSCAN0TMDF034HH (RSCAN0.TMDF034.UINT8[R_IO_HH]) +#define RSCAN0TMDF134 (RSCAN0.TMDF134.UINT32) +#define RSCAN0TMDF134L (RSCAN0.TMDF134.UINT16[R_IO_L]) +#define RSCAN0TMDF134LL (RSCAN0.TMDF134.UINT8[R_IO_LL]) +#define RSCAN0TMDF134LH (RSCAN0.TMDF134.UINT8[R_IO_LH]) +#define RSCAN0TMDF134H (RSCAN0.TMDF134.UINT16[R_IO_H]) +#define RSCAN0TMDF134HL (RSCAN0.TMDF134.UINT8[R_IO_HL]) +#define RSCAN0TMDF134HH (RSCAN0.TMDF134.UINT8[R_IO_HH]) +#define RSCAN0TMID35 (RSCAN0.TMID35.UINT32) +#define RSCAN0TMID35L (RSCAN0.TMID35.UINT16[R_IO_L]) +#define RSCAN0TMID35LL (RSCAN0.TMID35.UINT8[R_IO_LL]) +#define RSCAN0TMID35LH (RSCAN0.TMID35.UINT8[R_IO_LH]) +#define RSCAN0TMID35H (RSCAN0.TMID35.UINT16[R_IO_H]) +#define RSCAN0TMID35HL (RSCAN0.TMID35.UINT8[R_IO_HL]) +#define RSCAN0TMID35HH (RSCAN0.TMID35.UINT8[R_IO_HH]) +#define RSCAN0TMPTR35 (RSCAN0.TMPTR35.UINT32) +#define RSCAN0TMPTR35L (RSCAN0.TMPTR35.UINT16[R_IO_L]) +#define RSCAN0TMPTR35LL (RSCAN0.TMPTR35.UINT8[R_IO_LL]) +#define RSCAN0TMPTR35LH (RSCAN0.TMPTR35.UINT8[R_IO_LH]) +#define RSCAN0TMPTR35H (RSCAN0.TMPTR35.UINT16[R_IO_H]) +#define RSCAN0TMPTR35HL (RSCAN0.TMPTR35.UINT8[R_IO_HL]) +#define RSCAN0TMPTR35HH (RSCAN0.TMPTR35.UINT8[R_IO_HH]) +#define RSCAN0TMDF035 (RSCAN0.TMDF035.UINT32) +#define RSCAN0TMDF035L (RSCAN0.TMDF035.UINT16[R_IO_L]) +#define RSCAN0TMDF035LL (RSCAN0.TMDF035.UINT8[R_IO_LL]) +#define RSCAN0TMDF035LH (RSCAN0.TMDF035.UINT8[R_IO_LH]) +#define RSCAN0TMDF035H (RSCAN0.TMDF035.UINT16[R_IO_H]) +#define RSCAN0TMDF035HL (RSCAN0.TMDF035.UINT8[R_IO_HL]) +#define RSCAN0TMDF035HH (RSCAN0.TMDF035.UINT8[R_IO_HH]) +#define RSCAN0TMDF135 (RSCAN0.TMDF135.UINT32) +#define RSCAN0TMDF135L (RSCAN0.TMDF135.UINT16[R_IO_L]) +#define RSCAN0TMDF135LL (RSCAN0.TMDF135.UINT8[R_IO_LL]) +#define RSCAN0TMDF135LH (RSCAN0.TMDF135.UINT8[R_IO_LH]) +#define RSCAN0TMDF135H (RSCAN0.TMDF135.UINT16[R_IO_H]) +#define RSCAN0TMDF135HL (RSCAN0.TMDF135.UINT8[R_IO_HL]) +#define RSCAN0TMDF135HH (RSCAN0.TMDF135.UINT8[R_IO_HH]) +#define RSCAN0TMID36 (RSCAN0.TMID36.UINT32) +#define RSCAN0TMID36L (RSCAN0.TMID36.UINT16[R_IO_L]) +#define RSCAN0TMID36LL (RSCAN0.TMID36.UINT8[R_IO_LL]) +#define RSCAN0TMID36LH (RSCAN0.TMID36.UINT8[R_IO_LH]) +#define RSCAN0TMID36H (RSCAN0.TMID36.UINT16[R_IO_H]) +#define RSCAN0TMID36HL (RSCAN0.TMID36.UINT8[R_IO_HL]) +#define RSCAN0TMID36HH (RSCAN0.TMID36.UINT8[R_IO_HH]) +#define RSCAN0TMPTR36 (RSCAN0.TMPTR36.UINT32) +#define RSCAN0TMPTR36L (RSCAN0.TMPTR36.UINT16[R_IO_L]) +#define RSCAN0TMPTR36LL (RSCAN0.TMPTR36.UINT8[R_IO_LL]) +#define RSCAN0TMPTR36LH (RSCAN0.TMPTR36.UINT8[R_IO_LH]) +#define RSCAN0TMPTR36H (RSCAN0.TMPTR36.UINT16[R_IO_H]) +#define RSCAN0TMPTR36HL (RSCAN0.TMPTR36.UINT8[R_IO_HL]) +#define RSCAN0TMPTR36HH (RSCAN0.TMPTR36.UINT8[R_IO_HH]) +#define RSCAN0TMDF036 (RSCAN0.TMDF036.UINT32) +#define RSCAN0TMDF036L (RSCAN0.TMDF036.UINT16[R_IO_L]) +#define RSCAN0TMDF036LL (RSCAN0.TMDF036.UINT8[R_IO_LL]) +#define RSCAN0TMDF036LH (RSCAN0.TMDF036.UINT8[R_IO_LH]) +#define RSCAN0TMDF036H (RSCAN0.TMDF036.UINT16[R_IO_H]) +#define RSCAN0TMDF036HL (RSCAN0.TMDF036.UINT8[R_IO_HL]) +#define RSCAN0TMDF036HH (RSCAN0.TMDF036.UINT8[R_IO_HH]) +#define RSCAN0TMDF136 (RSCAN0.TMDF136.UINT32) +#define RSCAN0TMDF136L (RSCAN0.TMDF136.UINT16[R_IO_L]) +#define RSCAN0TMDF136LL (RSCAN0.TMDF136.UINT8[R_IO_LL]) +#define RSCAN0TMDF136LH (RSCAN0.TMDF136.UINT8[R_IO_LH]) +#define RSCAN0TMDF136H (RSCAN0.TMDF136.UINT16[R_IO_H]) +#define RSCAN0TMDF136HL (RSCAN0.TMDF136.UINT8[R_IO_HL]) +#define RSCAN0TMDF136HH (RSCAN0.TMDF136.UINT8[R_IO_HH]) +#define RSCAN0TMID37 (RSCAN0.TMID37.UINT32) +#define RSCAN0TMID37L (RSCAN0.TMID37.UINT16[R_IO_L]) +#define RSCAN0TMID37LL (RSCAN0.TMID37.UINT8[R_IO_LL]) +#define RSCAN0TMID37LH (RSCAN0.TMID37.UINT8[R_IO_LH]) +#define RSCAN0TMID37H (RSCAN0.TMID37.UINT16[R_IO_H]) +#define RSCAN0TMID37HL (RSCAN0.TMID37.UINT8[R_IO_HL]) +#define RSCAN0TMID37HH (RSCAN0.TMID37.UINT8[R_IO_HH]) +#define RSCAN0TMPTR37 (RSCAN0.TMPTR37.UINT32) +#define RSCAN0TMPTR37L (RSCAN0.TMPTR37.UINT16[R_IO_L]) +#define RSCAN0TMPTR37LL (RSCAN0.TMPTR37.UINT8[R_IO_LL]) +#define RSCAN0TMPTR37LH (RSCAN0.TMPTR37.UINT8[R_IO_LH]) +#define RSCAN0TMPTR37H (RSCAN0.TMPTR37.UINT16[R_IO_H]) +#define RSCAN0TMPTR37HL (RSCAN0.TMPTR37.UINT8[R_IO_HL]) +#define RSCAN0TMPTR37HH (RSCAN0.TMPTR37.UINT8[R_IO_HH]) +#define RSCAN0TMDF037 (RSCAN0.TMDF037.UINT32) +#define RSCAN0TMDF037L (RSCAN0.TMDF037.UINT16[R_IO_L]) +#define RSCAN0TMDF037LL (RSCAN0.TMDF037.UINT8[R_IO_LL]) +#define RSCAN0TMDF037LH (RSCAN0.TMDF037.UINT8[R_IO_LH]) +#define RSCAN0TMDF037H (RSCAN0.TMDF037.UINT16[R_IO_H]) +#define RSCAN0TMDF037HL (RSCAN0.TMDF037.UINT8[R_IO_HL]) +#define RSCAN0TMDF037HH (RSCAN0.TMDF037.UINT8[R_IO_HH]) +#define RSCAN0TMDF137 (RSCAN0.TMDF137.UINT32) +#define RSCAN0TMDF137L (RSCAN0.TMDF137.UINT16[R_IO_L]) +#define RSCAN0TMDF137LL (RSCAN0.TMDF137.UINT8[R_IO_LL]) +#define RSCAN0TMDF137LH (RSCAN0.TMDF137.UINT8[R_IO_LH]) +#define RSCAN0TMDF137H (RSCAN0.TMDF137.UINT16[R_IO_H]) +#define RSCAN0TMDF137HL (RSCAN0.TMDF137.UINT8[R_IO_HL]) +#define RSCAN0TMDF137HH (RSCAN0.TMDF137.UINT8[R_IO_HH]) +#define RSCAN0TMID38 (RSCAN0.TMID38.UINT32) +#define RSCAN0TMID38L (RSCAN0.TMID38.UINT16[R_IO_L]) +#define RSCAN0TMID38LL (RSCAN0.TMID38.UINT8[R_IO_LL]) +#define RSCAN0TMID38LH (RSCAN0.TMID38.UINT8[R_IO_LH]) +#define RSCAN0TMID38H (RSCAN0.TMID38.UINT16[R_IO_H]) +#define RSCAN0TMID38HL (RSCAN0.TMID38.UINT8[R_IO_HL]) +#define RSCAN0TMID38HH (RSCAN0.TMID38.UINT8[R_IO_HH]) +#define RSCAN0TMPTR38 (RSCAN0.TMPTR38.UINT32) +#define RSCAN0TMPTR38L (RSCAN0.TMPTR38.UINT16[R_IO_L]) +#define RSCAN0TMPTR38LL (RSCAN0.TMPTR38.UINT8[R_IO_LL]) +#define RSCAN0TMPTR38LH (RSCAN0.TMPTR38.UINT8[R_IO_LH]) +#define RSCAN0TMPTR38H (RSCAN0.TMPTR38.UINT16[R_IO_H]) +#define RSCAN0TMPTR38HL (RSCAN0.TMPTR38.UINT8[R_IO_HL]) +#define RSCAN0TMPTR38HH (RSCAN0.TMPTR38.UINT8[R_IO_HH]) +#define RSCAN0TMDF038 (RSCAN0.TMDF038.UINT32) +#define RSCAN0TMDF038L (RSCAN0.TMDF038.UINT16[R_IO_L]) +#define RSCAN0TMDF038LL (RSCAN0.TMDF038.UINT8[R_IO_LL]) +#define RSCAN0TMDF038LH (RSCAN0.TMDF038.UINT8[R_IO_LH]) +#define RSCAN0TMDF038H (RSCAN0.TMDF038.UINT16[R_IO_H]) +#define RSCAN0TMDF038HL (RSCAN0.TMDF038.UINT8[R_IO_HL]) +#define RSCAN0TMDF038HH (RSCAN0.TMDF038.UINT8[R_IO_HH]) +#define RSCAN0TMDF138 (RSCAN0.TMDF138.UINT32) +#define RSCAN0TMDF138L (RSCAN0.TMDF138.UINT16[R_IO_L]) +#define RSCAN0TMDF138LL (RSCAN0.TMDF138.UINT8[R_IO_LL]) +#define RSCAN0TMDF138LH (RSCAN0.TMDF138.UINT8[R_IO_LH]) +#define RSCAN0TMDF138H (RSCAN0.TMDF138.UINT16[R_IO_H]) +#define RSCAN0TMDF138HL (RSCAN0.TMDF138.UINT8[R_IO_HL]) +#define RSCAN0TMDF138HH (RSCAN0.TMDF138.UINT8[R_IO_HH]) +#define RSCAN0TMID39 (RSCAN0.TMID39.UINT32) +#define RSCAN0TMID39L (RSCAN0.TMID39.UINT16[R_IO_L]) +#define RSCAN0TMID39LL (RSCAN0.TMID39.UINT8[R_IO_LL]) +#define RSCAN0TMID39LH (RSCAN0.TMID39.UINT8[R_IO_LH]) +#define RSCAN0TMID39H (RSCAN0.TMID39.UINT16[R_IO_H]) +#define RSCAN0TMID39HL (RSCAN0.TMID39.UINT8[R_IO_HL]) +#define RSCAN0TMID39HH (RSCAN0.TMID39.UINT8[R_IO_HH]) +#define RSCAN0TMPTR39 (RSCAN0.TMPTR39.UINT32) +#define RSCAN0TMPTR39L (RSCAN0.TMPTR39.UINT16[R_IO_L]) +#define RSCAN0TMPTR39LL (RSCAN0.TMPTR39.UINT8[R_IO_LL]) +#define RSCAN0TMPTR39LH (RSCAN0.TMPTR39.UINT8[R_IO_LH]) +#define RSCAN0TMPTR39H (RSCAN0.TMPTR39.UINT16[R_IO_H]) +#define RSCAN0TMPTR39HL (RSCAN0.TMPTR39.UINT8[R_IO_HL]) +#define RSCAN0TMPTR39HH (RSCAN0.TMPTR39.UINT8[R_IO_HH]) +#define RSCAN0TMDF039 (RSCAN0.TMDF039.UINT32) +#define RSCAN0TMDF039L (RSCAN0.TMDF039.UINT16[R_IO_L]) +#define RSCAN0TMDF039LL (RSCAN0.TMDF039.UINT8[R_IO_LL]) +#define RSCAN0TMDF039LH (RSCAN0.TMDF039.UINT8[R_IO_LH]) +#define RSCAN0TMDF039H (RSCAN0.TMDF039.UINT16[R_IO_H]) +#define RSCAN0TMDF039HL (RSCAN0.TMDF039.UINT8[R_IO_HL]) +#define RSCAN0TMDF039HH (RSCAN0.TMDF039.UINT8[R_IO_HH]) +#define RSCAN0TMDF139 (RSCAN0.TMDF139.UINT32) +#define RSCAN0TMDF139L (RSCAN0.TMDF139.UINT16[R_IO_L]) +#define RSCAN0TMDF139LL (RSCAN0.TMDF139.UINT8[R_IO_LL]) +#define RSCAN0TMDF139LH (RSCAN0.TMDF139.UINT8[R_IO_LH]) +#define RSCAN0TMDF139H (RSCAN0.TMDF139.UINT16[R_IO_H]) +#define RSCAN0TMDF139HL (RSCAN0.TMDF139.UINT8[R_IO_HL]) +#define RSCAN0TMDF139HH (RSCAN0.TMDF139.UINT8[R_IO_HH]) +#define RSCAN0TMID40 (RSCAN0.TMID40.UINT32) +#define RSCAN0TMID40L (RSCAN0.TMID40.UINT16[R_IO_L]) +#define RSCAN0TMID40LL (RSCAN0.TMID40.UINT8[R_IO_LL]) +#define RSCAN0TMID40LH (RSCAN0.TMID40.UINT8[R_IO_LH]) +#define RSCAN0TMID40H (RSCAN0.TMID40.UINT16[R_IO_H]) +#define RSCAN0TMID40HL (RSCAN0.TMID40.UINT8[R_IO_HL]) +#define RSCAN0TMID40HH (RSCAN0.TMID40.UINT8[R_IO_HH]) +#define RSCAN0TMPTR40 (RSCAN0.TMPTR40.UINT32) +#define RSCAN0TMPTR40L (RSCAN0.TMPTR40.UINT16[R_IO_L]) +#define RSCAN0TMPTR40LL (RSCAN0.TMPTR40.UINT8[R_IO_LL]) +#define RSCAN0TMPTR40LH (RSCAN0.TMPTR40.UINT8[R_IO_LH]) +#define RSCAN0TMPTR40H (RSCAN0.TMPTR40.UINT16[R_IO_H]) +#define RSCAN0TMPTR40HL (RSCAN0.TMPTR40.UINT8[R_IO_HL]) +#define RSCAN0TMPTR40HH (RSCAN0.TMPTR40.UINT8[R_IO_HH]) +#define RSCAN0TMDF040 (RSCAN0.TMDF040.UINT32) +#define RSCAN0TMDF040L (RSCAN0.TMDF040.UINT16[R_IO_L]) +#define RSCAN0TMDF040LL (RSCAN0.TMDF040.UINT8[R_IO_LL]) +#define RSCAN0TMDF040LH (RSCAN0.TMDF040.UINT8[R_IO_LH]) +#define RSCAN0TMDF040H (RSCAN0.TMDF040.UINT16[R_IO_H]) +#define RSCAN0TMDF040HL (RSCAN0.TMDF040.UINT8[R_IO_HL]) +#define RSCAN0TMDF040HH (RSCAN0.TMDF040.UINT8[R_IO_HH]) +#define RSCAN0TMDF140 (RSCAN0.TMDF140.UINT32) +#define RSCAN0TMDF140L (RSCAN0.TMDF140.UINT16[R_IO_L]) +#define RSCAN0TMDF140LL (RSCAN0.TMDF140.UINT8[R_IO_LL]) +#define RSCAN0TMDF140LH (RSCAN0.TMDF140.UINT8[R_IO_LH]) +#define RSCAN0TMDF140H (RSCAN0.TMDF140.UINT16[R_IO_H]) +#define RSCAN0TMDF140HL (RSCAN0.TMDF140.UINT8[R_IO_HL]) +#define RSCAN0TMDF140HH (RSCAN0.TMDF140.UINT8[R_IO_HH]) +#define RSCAN0TMID41 (RSCAN0.TMID41.UINT32) +#define RSCAN0TMID41L (RSCAN0.TMID41.UINT16[R_IO_L]) +#define RSCAN0TMID41LL (RSCAN0.TMID41.UINT8[R_IO_LL]) +#define RSCAN0TMID41LH (RSCAN0.TMID41.UINT8[R_IO_LH]) +#define RSCAN0TMID41H (RSCAN0.TMID41.UINT16[R_IO_H]) +#define RSCAN0TMID41HL (RSCAN0.TMID41.UINT8[R_IO_HL]) +#define RSCAN0TMID41HH (RSCAN0.TMID41.UINT8[R_IO_HH]) +#define RSCAN0TMPTR41 (RSCAN0.TMPTR41.UINT32) +#define RSCAN0TMPTR41L (RSCAN0.TMPTR41.UINT16[R_IO_L]) +#define RSCAN0TMPTR41LL (RSCAN0.TMPTR41.UINT8[R_IO_LL]) +#define RSCAN0TMPTR41LH (RSCAN0.TMPTR41.UINT8[R_IO_LH]) +#define RSCAN0TMPTR41H (RSCAN0.TMPTR41.UINT16[R_IO_H]) +#define RSCAN0TMPTR41HL (RSCAN0.TMPTR41.UINT8[R_IO_HL]) +#define RSCAN0TMPTR41HH (RSCAN0.TMPTR41.UINT8[R_IO_HH]) +#define RSCAN0TMDF041 (RSCAN0.TMDF041.UINT32) +#define RSCAN0TMDF041L (RSCAN0.TMDF041.UINT16[R_IO_L]) +#define RSCAN0TMDF041LL (RSCAN0.TMDF041.UINT8[R_IO_LL]) +#define RSCAN0TMDF041LH (RSCAN0.TMDF041.UINT8[R_IO_LH]) +#define RSCAN0TMDF041H (RSCAN0.TMDF041.UINT16[R_IO_H]) +#define RSCAN0TMDF041HL (RSCAN0.TMDF041.UINT8[R_IO_HL]) +#define RSCAN0TMDF041HH (RSCAN0.TMDF041.UINT8[R_IO_HH]) +#define RSCAN0TMDF141 (RSCAN0.TMDF141.UINT32) +#define RSCAN0TMDF141L (RSCAN0.TMDF141.UINT16[R_IO_L]) +#define RSCAN0TMDF141LL (RSCAN0.TMDF141.UINT8[R_IO_LL]) +#define RSCAN0TMDF141LH (RSCAN0.TMDF141.UINT8[R_IO_LH]) +#define RSCAN0TMDF141H (RSCAN0.TMDF141.UINT16[R_IO_H]) +#define RSCAN0TMDF141HL (RSCAN0.TMDF141.UINT8[R_IO_HL]) +#define RSCAN0TMDF141HH (RSCAN0.TMDF141.UINT8[R_IO_HH]) +#define RSCAN0TMID42 (RSCAN0.TMID42.UINT32) +#define RSCAN0TMID42L (RSCAN0.TMID42.UINT16[R_IO_L]) +#define RSCAN0TMID42LL (RSCAN0.TMID42.UINT8[R_IO_LL]) +#define RSCAN0TMID42LH (RSCAN0.TMID42.UINT8[R_IO_LH]) +#define RSCAN0TMID42H (RSCAN0.TMID42.UINT16[R_IO_H]) +#define RSCAN0TMID42HL (RSCAN0.TMID42.UINT8[R_IO_HL]) +#define RSCAN0TMID42HH (RSCAN0.TMID42.UINT8[R_IO_HH]) +#define RSCAN0TMPTR42 (RSCAN0.TMPTR42.UINT32) +#define RSCAN0TMPTR42L (RSCAN0.TMPTR42.UINT16[R_IO_L]) +#define RSCAN0TMPTR42LL (RSCAN0.TMPTR42.UINT8[R_IO_LL]) +#define RSCAN0TMPTR42LH (RSCAN0.TMPTR42.UINT8[R_IO_LH]) +#define RSCAN0TMPTR42H (RSCAN0.TMPTR42.UINT16[R_IO_H]) +#define RSCAN0TMPTR42HL (RSCAN0.TMPTR42.UINT8[R_IO_HL]) +#define RSCAN0TMPTR42HH (RSCAN0.TMPTR42.UINT8[R_IO_HH]) +#define RSCAN0TMDF042 (RSCAN0.TMDF042.UINT32) +#define RSCAN0TMDF042L (RSCAN0.TMDF042.UINT16[R_IO_L]) +#define RSCAN0TMDF042LL (RSCAN0.TMDF042.UINT8[R_IO_LL]) +#define RSCAN0TMDF042LH (RSCAN0.TMDF042.UINT8[R_IO_LH]) +#define RSCAN0TMDF042H (RSCAN0.TMDF042.UINT16[R_IO_H]) +#define RSCAN0TMDF042HL (RSCAN0.TMDF042.UINT8[R_IO_HL]) +#define RSCAN0TMDF042HH (RSCAN0.TMDF042.UINT8[R_IO_HH]) +#define RSCAN0TMDF142 (RSCAN0.TMDF142.UINT32) +#define RSCAN0TMDF142L (RSCAN0.TMDF142.UINT16[R_IO_L]) +#define RSCAN0TMDF142LL (RSCAN0.TMDF142.UINT8[R_IO_LL]) +#define RSCAN0TMDF142LH (RSCAN0.TMDF142.UINT8[R_IO_LH]) +#define RSCAN0TMDF142H (RSCAN0.TMDF142.UINT16[R_IO_H]) +#define RSCAN0TMDF142HL (RSCAN0.TMDF142.UINT8[R_IO_HL]) +#define RSCAN0TMDF142HH (RSCAN0.TMDF142.UINT8[R_IO_HH]) +#define RSCAN0TMID43 (RSCAN0.TMID43.UINT32) +#define RSCAN0TMID43L (RSCAN0.TMID43.UINT16[R_IO_L]) +#define RSCAN0TMID43LL (RSCAN0.TMID43.UINT8[R_IO_LL]) +#define RSCAN0TMID43LH (RSCAN0.TMID43.UINT8[R_IO_LH]) +#define RSCAN0TMID43H (RSCAN0.TMID43.UINT16[R_IO_H]) +#define RSCAN0TMID43HL (RSCAN0.TMID43.UINT8[R_IO_HL]) +#define RSCAN0TMID43HH (RSCAN0.TMID43.UINT8[R_IO_HH]) +#define RSCAN0TMPTR43 (RSCAN0.TMPTR43.UINT32) +#define RSCAN0TMPTR43L (RSCAN0.TMPTR43.UINT16[R_IO_L]) +#define RSCAN0TMPTR43LL (RSCAN0.TMPTR43.UINT8[R_IO_LL]) +#define RSCAN0TMPTR43LH (RSCAN0.TMPTR43.UINT8[R_IO_LH]) +#define RSCAN0TMPTR43H (RSCAN0.TMPTR43.UINT16[R_IO_H]) +#define RSCAN0TMPTR43HL (RSCAN0.TMPTR43.UINT8[R_IO_HL]) +#define RSCAN0TMPTR43HH (RSCAN0.TMPTR43.UINT8[R_IO_HH]) +#define RSCAN0TMDF043 (RSCAN0.TMDF043.UINT32) +#define RSCAN0TMDF043L (RSCAN0.TMDF043.UINT16[R_IO_L]) +#define RSCAN0TMDF043LL (RSCAN0.TMDF043.UINT8[R_IO_LL]) +#define RSCAN0TMDF043LH (RSCAN0.TMDF043.UINT8[R_IO_LH]) +#define RSCAN0TMDF043H (RSCAN0.TMDF043.UINT16[R_IO_H]) +#define RSCAN0TMDF043HL (RSCAN0.TMDF043.UINT8[R_IO_HL]) +#define RSCAN0TMDF043HH (RSCAN0.TMDF043.UINT8[R_IO_HH]) +#define RSCAN0TMDF143 (RSCAN0.TMDF143.UINT32) +#define RSCAN0TMDF143L (RSCAN0.TMDF143.UINT16[R_IO_L]) +#define RSCAN0TMDF143LL (RSCAN0.TMDF143.UINT8[R_IO_LL]) +#define RSCAN0TMDF143LH (RSCAN0.TMDF143.UINT8[R_IO_LH]) +#define RSCAN0TMDF143H (RSCAN0.TMDF143.UINT16[R_IO_H]) +#define RSCAN0TMDF143HL (RSCAN0.TMDF143.UINT8[R_IO_HL]) +#define RSCAN0TMDF143HH (RSCAN0.TMDF143.UINT8[R_IO_HH]) +#define RSCAN0TMID44 (RSCAN0.TMID44.UINT32) +#define RSCAN0TMID44L (RSCAN0.TMID44.UINT16[R_IO_L]) +#define RSCAN0TMID44LL (RSCAN0.TMID44.UINT8[R_IO_LL]) +#define RSCAN0TMID44LH (RSCAN0.TMID44.UINT8[R_IO_LH]) +#define RSCAN0TMID44H (RSCAN0.TMID44.UINT16[R_IO_H]) +#define RSCAN0TMID44HL (RSCAN0.TMID44.UINT8[R_IO_HL]) +#define RSCAN0TMID44HH (RSCAN0.TMID44.UINT8[R_IO_HH]) +#define RSCAN0TMPTR44 (RSCAN0.TMPTR44.UINT32) +#define RSCAN0TMPTR44L (RSCAN0.TMPTR44.UINT16[R_IO_L]) +#define RSCAN0TMPTR44LL (RSCAN0.TMPTR44.UINT8[R_IO_LL]) +#define RSCAN0TMPTR44LH (RSCAN0.TMPTR44.UINT8[R_IO_LH]) +#define RSCAN0TMPTR44H (RSCAN0.TMPTR44.UINT16[R_IO_H]) +#define RSCAN0TMPTR44HL (RSCAN0.TMPTR44.UINT8[R_IO_HL]) +#define RSCAN0TMPTR44HH (RSCAN0.TMPTR44.UINT8[R_IO_HH]) +#define RSCAN0TMDF044 (RSCAN0.TMDF044.UINT32) +#define RSCAN0TMDF044L (RSCAN0.TMDF044.UINT16[R_IO_L]) +#define RSCAN0TMDF044LL (RSCAN0.TMDF044.UINT8[R_IO_LL]) +#define RSCAN0TMDF044LH (RSCAN0.TMDF044.UINT8[R_IO_LH]) +#define RSCAN0TMDF044H (RSCAN0.TMDF044.UINT16[R_IO_H]) +#define RSCAN0TMDF044HL (RSCAN0.TMDF044.UINT8[R_IO_HL]) +#define RSCAN0TMDF044HH (RSCAN0.TMDF044.UINT8[R_IO_HH]) +#define RSCAN0TMDF144 (RSCAN0.TMDF144.UINT32) +#define RSCAN0TMDF144L (RSCAN0.TMDF144.UINT16[R_IO_L]) +#define RSCAN0TMDF144LL (RSCAN0.TMDF144.UINT8[R_IO_LL]) +#define RSCAN0TMDF144LH (RSCAN0.TMDF144.UINT8[R_IO_LH]) +#define RSCAN0TMDF144H (RSCAN0.TMDF144.UINT16[R_IO_H]) +#define RSCAN0TMDF144HL (RSCAN0.TMDF144.UINT8[R_IO_HL]) +#define RSCAN0TMDF144HH (RSCAN0.TMDF144.UINT8[R_IO_HH]) +#define RSCAN0TMID45 (RSCAN0.TMID45.UINT32) +#define RSCAN0TMID45L (RSCAN0.TMID45.UINT16[R_IO_L]) +#define RSCAN0TMID45LL (RSCAN0.TMID45.UINT8[R_IO_LL]) +#define RSCAN0TMID45LH (RSCAN0.TMID45.UINT8[R_IO_LH]) +#define RSCAN0TMID45H (RSCAN0.TMID45.UINT16[R_IO_H]) +#define RSCAN0TMID45HL (RSCAN0.TMID45.UINT8[R_IO_HL]) +#define RSCAN0TMID45HH (RSCAN0.TMID45.UINT8[R_IO_HH]) +#define RSCAN0TMPTR45 (RSCAN0.TMPTR45.UINT32) +#define RSCAN0TMPTR45L (RSCAN0.TMPTR45.UINT16[R_IO_L]) +#define RSCAN0TMPTR45LL (RSCAN0.TMPTR45.UINT8[R_IO_LL]) +#define RSCAN0TMPTR45LH (RSCAN0.TMPTR45.UINT8[R_IO_LH]) +#define RSCAN0TMPTR45H (RSCAN0.TMPTR45.UINT16[R_IO_H]) +#define RSCAN0TMPTR45HL (RSCAN0.TMPTR45.UINT8[R_IO_HL]) +#define RSCAN0TMPTR45HH (RSCAN0.TMPTR45.UINT8[R_IO_HH]) +#define RSCAN0TMDF045 (RSCAN0.TMDF045.UINT32) +#define RSCAN0TMDF045L (RSCAN0.TMDF045.UINT16[R_IO_L]) +#define RSCAN0TMDF045LL (RSCAN0.TMDF045.UINT8[R_IO_LL]) +#define RSCAN0TMDF045LH (RSCAN0.TMDF045.UINT8[R_IO_LH]) +#define RSCAN0TMDF045H (RSCAN0.TMDF045.UINT16[R_IO_H]) +#define RSCAN0TMDF045HL (RSCAN0.TMDF045.UINT8[R_IO_HL]) +#define RSCAN0TMDF045HH (RSCAN0.TMDF045.UINT8[R_IO_HH]) +#define RSCAN0TMDF145 (RSCAN0.TMDF145.UINT32) +#define RSCAN0TMDF145L (RSCAN0.TMDF145.UINT16[R_IO_L]) +#define RSCAN0TMDF145LL (RSCAN0.TMDF145.UINT8[R_IO_LL]) +#define RSCAN0TMDF145LH (RSCAN0.TMDF145.UINT8[R_IO_LH]) +#define RSCAN0TMDF145H (RSCAN0.TMDF145.UINT16[R_IO_H]) +#define RSCAN0TMDF145HL (RSCAN0.TMDF145.UINT8[R_IO_HL]) +#define RSCAN0TMDF145HH (RSCAN0.TMDF145.UINT8[R_IO_HH]) +#define RSCAN0TMID46 (RSCAN0.TMID46.UINT32) +#define RSCAN0TMID46L (RSCAN0.TMID46.UINT16[R_IO_L]) +#define RSCAN0TMID46LL (RSCAN0.TMID46.UINT8[R_IO_LL]) +#define RSCAN0TMID46LH (RSCAN0.TMID46.UINT8[R_IO_LH]) +#define RSCAN0TMID46H (RSCAN0.TMID46.UINT16[R_IO_H]) +#define RSCAN0TMID46HL (RSCAN0.TMID46.UINT8[R_IO_HL]) +#define RSCAN0TMID46HH (RSCAN0.TMID46.UINT8[R_IO_HH]) +#define RSCAN0TMPTR46 (RSCAN0.TMPTR46.UINT32) +#define RSCAN0TMPTR46L (RSCAN0.TMPTR46.UINT16[R_IO_L]) +#define RSCAN0TMPTR46LL (RSCAN0.TMPTR46.UINT8[R_IO_LL]) +#define RSCAN0TMPTR46LH (RSCAN0.TMPTR46.UINT8[R_IO_LH]) +#define RSCAN0TMPTR46H (RSCAN0.TMPTR46.UINT16[R_IO_H]) +#define RSCAN0TMPTR46HL (RSCAN0.TMPTR46.UINT8[R_IO_HL]) +#define RSCAN0TMPTR46HH (RSCAN0.TMPTR46.UINT8[R_IO_HH]) +#define RSCAN0TMDF046 (RSCAN0.TMDF046.UINT32) +#define RSCAN0TMDF046L (RSCAN0.TMDF046.UINT16[R_IO_L]) +#define RSCAN0TMDF046LL (RSCAN0.TMDF046.UINT8[R_IO_LL]) +#define RSCAN0TMDF046LH (RSCAN0.TMDF046.UINT8[R_IO_LH]) +#define RSCAN0TMDF046H (RSCAN0.TMDF046.UINT16[R_IO_H]) +#define RSCAN0TMDF046HL (RSCAN0.TMDF046.UINT8[R_IO_HL]) +#define RSCAN0TMDF046HH (RSCAN0.TMDF046.UINT8[R_IO_HH]) +#define RSCAN0TMDF146 (RSCAN0.TMDF146.UINT32) +#define RSCAN0TMDF146L (RSCAN0.TMDF146.UINT16[R_IO_L]) +#define RSCAN0TMDF146LL (RSCAN0.TMDF146.UINT8[R_IO_LL]) +#define RSCAN0TMDF146LH (RSCAN0.TMDF146.UINT8[R_IO_LH]) +#define RSCAN0TMDF146H (RSCAN0.TMDF146.UINT16[R_IO_H]) +#define RSCAN0TMDF146HL (RSCAN0.TMDF146.UINT8[R_IO_HL]) +#define RSCAN0TMDF146HH (RSCAN0.TMDF146.UINT8[R_IO_HH]) +#define RSCAN0TMID47 (RSCAN0.TMID47.UINT32) +#define RSCAN0TMID47L (RSCAN0.TMID47.UINT16[R_IO_L]) +#define RSCAN0TMID47LL (RSCAN0.TMID47.UINT8[R_IO_LL]) +#define RSCAN0TMID47LH (RSCAN0.TMID47.UINT8[R_IO_LH]) +#define RSCAN0TMID47H (RSCAN0.TMID47.UINT16[R_IO_H]) +#define RSCAN0TMID47HL (RSCAN0.TMID47.UINT8[R_IO_HL]) +#define RSCAN0TMID47HH (RSCAN0.TMID47.UINT8[R_IO_HH]) +#define RSCAN0TMPTR47 (RSCAN0.TMPTR47.UINT32) +#define RSCAN0TMPTR47L (RSCAN0.TMPTR47.UINT16[R_IO_L]) +#define RSCAN0TMPTR47LL (RSCAN0.TMPTR47.UINT8[R_IO_LL]) +#define RSCAN0TMPTR47LH (RSCAN0.TMPTR47.UINT8[R_IO_LH]) +#define RSCAN0TMPTR47H (RSCAN0.TMPTR47.UINT16[R_IO_H]) +#define RSCAN0TMPTR47HL (RSCAN0.TMPTR47.UINT8[R_IO_HL]) +#define RSCAN0TMPTR47HH (RSCAN0.TMPTR47.UINT8[R_IO_HH]) +#define RSCAN0TMDF047 (RSCAN0.TMDF047.UINT32) +#define RSCAN0TMDF047L (RSCAN0.TMDF047.UINT16[R_IO_L]) +#define RSCAN0TMDF047LL (RSCAN0.TMDF047.UINT8[R_IO_LL]) +#define RSCAN0TMDF047LH (RSCAN0.TMDF047.UINT8[R_IO_LH]) +#define RSCAN0TMDF047H (RSCAN0.TMDF047.UINT16[R_IO_H]) +#define RSCAN0TMDF047HL (RSCAN0.TMDF047.UINT8[R_IO_HL]) +#define RSCAN0TMDF047HH (RSCAN0.TMDF047.UINT8[R_IO_HH]) +#define RSCAN0TMDF147 (RSCAN0.TMDF147.UINT32) +#define RSCAN0TMDF147L (RSCAN0.TMDF147.UINT16[R_IO_L]) +#define RSCAN0TMDF147LL (RSCAN0.TMDF147.UINT8[R_IO_LL]) +#define RSCAN0TMDF147LH (RSCAN0.TMDF147.UINT8[R_IO_LH]) +#define RSCAN0TMDF147H (RSCAN0.TMDF147.UINT16[R_IO_H]) +#define RSCAN0TMDF147HL (RSCAN0.TMDF147.UINT8[R_IO_HL]) +#define RSCAN0TMDF147HH (RSCAN0.TMDF147.UINT8[R_IO_HH]) +#define RSCAN0TMID48 (RSCAN0.TMID48.UINT32) +#define RSCAN0TMID48L (RSCAN0.TMID48.UINT16[R_IO_L]) +#define RSCAN0TMID48LL (RSCAN0.TMID48.UINT8[R_IO_LL]) +#define RSCAN0TMID48LH (RSCAN0.TMID48.UINT8[R_IO_LH]) +#define RSCAN0TMID48H (RSCAN0.TMID48.UINT16[R_IO_H]) +#define RSCAN0TMID48HL (RSCAN0.TMID48.UINT8[R_IO_HL]) +#define RSCAN0TMID48HH (RSCAN0.TMID48.UINT8[R_IO_HH]) +#define RSCAN0TMPTR48 (RSCAN0.TMPTR48.UINT32) +#define RSCAN0TMPTR48L (RSCAN0.TMPTR48.UINT16[R_IO_L]) +#define RSCAN0TMPTR48LL (RSCAN0.TMPTR48.UINT8[R_IO_LL]) +#define RSCAN0TMPTR48LH (RSCAN0.TMPTR48.UINT8[R_IO_LH]) +#define RSCAN0TMPTR48H (RSCAN0.TMPTR48.UINT16[R_IO_H]) +#define RSCAN0TMPTR48HL (RSCAN0.TMPTR48.UINT8[R_IO_HL]) +#define RSCAN0TMPTR48HH (RSCAN0.TMPTR48.UINT8[R_IO_HH]) +#define RSCAN0TMDF048 (RSCAN0.TMDF048.UINT32) +#define RSCAN0TMDF048L (RSCAN0.TMDF048.UINT16[R_IO_L]) +#define RSCAN0TMDF048LL (RSCAN0.TMDF048.UINT8[R_IO_LL]) +#define RSCAN0TMDF048LH (RSCAN0.TMDF048.UINT8[R_IO_LH]) +#define RSCAN0TMDF048H (RSCAN0.TMDF048.UINT16[R_IO_H]) +#define RSCAN0TMDF048HL (RSCAN0.TMDF048.UINT8[R_IO_HL]) +#define RSCAN0TMDF048HH (RSCAN0.TMDF048.UINT8[R_IO_HH]) +#define RSCAN0TMDF148 (RSCAN0.TMDF148.UINT32) +#define RSCAN0TMDF148L (RSCAN0.TMDF148.UINT16[R_IO_L]) +#define RSCAN0TMDF148LL (RSCAN0.TMDF148.UINT8[R_IO_LL]) +#define RSCAN0TMDF148LH (RSCAN0.TMDF148.UINT8[R_IO_LH]) +#define RSCAN0TMDF148H (RSCAN0.TMDF148.UINT16[R_IO_H]) +#define RSCAN0TMDF148HL (RSCAN0.TMDF148.UINT8[R_IO_HL]) +#define RSCAN0TMDF148HH (RSCAN0.TMDF148.UINT8[R_IO_HH]) +#define RSCAN0TMID49 (RSCAN0.TMID49.UINT32) +#define RSCAN0TMID49L (RSCAN0.TMID49.UINT16[R_IO_L]) +#define RSCAN0TMID49LL (RSCAN0.TMID49.UINT8[R_IO_LL]) +#define RSCAN0TMID49LH (RSCAN0.TMID49.UINT8[R_IO_LH]) +#define RSCAN0TMID49H (RSCAN0.TMID49.UINT16[R_IO_H]) +#define RSCAN0TMID49HL (RSCAN0.TMID49.UINT8[R_IO_HL]) +#define RSCAN0TMID49HH (RSCAN0.TMID49.UINT8[R_IO_HH]) +#define RSCAN0TMPTR49 (RSCAN0.TMPTR49.UINT32) +#define RSCAN0TMPTR49L (RSCAN0.TMPTR49.UINT16[R_IO_L]) +#define RSCAN0TMPTR49LL (RSCAN0.TMPTR49.UINT8[R_IO_LL]) +#define RSCAN0TMPTR49LH (RSCAN0.TMPTR49.UINT8[R_IO_LH]) +#define RSCAN0TMPTR49H (RSCAN0.TMPTR49.UINT16[R_IO_H]) +#define RSCAN0TMPTR49HL (RSCAN0.TMPTR49.UINT8[R_IO_HL]) +#define RSCAN0TMPTR49HH (RSCAN0.TMPTR49.UINT8[R_IO_HH]) +#define RSCAN0TMDF049 (RSCAN0.TMDF049.UINT32) +#define RSCAN0TMDF049L (RSCAN0.TMDF049.UINT16[R_IO_L]) +#define RSCAN0TMDF049LL (RSCAN0.TMDF049.UINT8[R_IO_LL]) +#define RSCAN0TMDF049LH (RSCAN0.TMDF049.UINT8[R_IO_LH]) +#define RSCAN0TMDF049H (RSCAN0.TMDF049.UINT16[R_IO_H]) +#define RSCAN0TMDF049HL (RSCAN0.TMDF049.UINT8[R_IO_HL]) +#define RSCAN0TMDF049HH (RSCAN0.TMDF049.UINT8[R_IO_HH]) +#define RSCAN0TMDF149 (RSCAN0.TMDF149.UINT32) +#define RSCAN0TMDF149L (RSCAN0.TMDF149.UINT16[R_IO_L]) +#define RSCAN0TMDF149LL (RSCAN0.TMDF149.UINT8[R_IO_LL]) +#define RSCAN0TMDF149LH (RSCAN0.TMDF149.UINT8[R_IO_LH]) +#define RSCAN0TMDF149H (RSCAN0.TMDF149.UINT16[R_IO_H]) +#define RSCAN0TMDF149HL (RSCAN0.TMDF149.UINT8[R_IO_HL]) +#define RSCAN0TMDF149HH (RSCAN0.TMDF149.UINT8[R_IO_HH]) +#define RSCAN0TMID50 (RSCAN0.TMID50.UINT32) +#define RSCAN0TMID50L (RSCAN0.TMID50.UINT16[R_IO_L]) +#define RSCAN0TMID50LL (RSCAN0.TMID50.UINT8[R_IO_LL]) +#define RSCAN0TMID50LH (RSCAN0.TMID50.UINT8[R_IO_LH]) +#define RSCAN0TMID50H (RSCAN0.TMID50.UINT16[R_IO_H]) +#define RSCAN0TMID50HL (RSCAN0.TMID50.UINT8[R_IO_HL]) +#define RSCAN0TMID50HH (RSCAN0.TMID50.UINT8[R_IO_HH]) +#define RSCAN0TMPTR50 (RSCAN0.TMPTR50.UINT32) +#define RSCAN0TMPTR50L (RSCAN0.TMPTR50.UINT16[R_IO_L]) +#define RSCAN0TMPTR50LL (RSCAN0.TMPTR50.UINT8[R_IO_LL]) +#define RSCAN0TMPTR50LH (RSCAN0.TMPTR50.UINT8[R_IO_LH]) +#define RSCAN0TMPTR50H (RSCAN0.TMPTR50.UINT16[R_IO_H]) +#define RSCAN0TMPTR50HL (RSCAN0.TMPTR50.UINT8[R_IO_HL]) +#define RSCAN0TMPTR50HH (RSCAN0.TMPTR50.UINT8[R_IO_HH]) +#define RSCAN0TMDF050 (RSCAN0.TMDF050.UINT32) +#define RSCAN0TMDF050L (RSCAN0.TMDF050.UINT16[R_IO_L]) +#define RSCAN0TMDF050LL (RSCAN0.TMDF050.UINT8[R_IO_LL]) +#define RSCAN0TMDF050LH (RSCAN0.TMDF050.UINT8[R_IO_LH]) +#define RSCAN0TMDF050H (RSCAN0.TMDF050.UINT16[R_IO_H]) +#define RSCAN0TMDF050HL (RSCAN0.TMDF050.UINT8[R_IO_HL]) +#define RSCAN0TMDF050HH (RSCAN0.TMDF050.UINT8[R_IO_HH]) +#define RSCAN0TMDF150 (RSCAN0.TMDF150.UINT32) +#define RSCAN0TMDF150L (RSCAN0.TMDF150.UINT16[R_IO_L]) +#define RSCAN0TMDF150LL (RSCAN0.TMDF150.UINT8[R_IO_LL]) +#define RSCAN0TMDF150LH (RSCAN0.TMDF150.UINT8[R_IO_LH]) +#define RSCAN0TMDF150H (RSCAN0.TMDF150.UINT16[R_IO_H]) +#define RSCAN0TMDF150HL (RSCAN0.TMDF150.UINT8[R_IO_HL]) +#define RSCAN0TMDF150HH (RSCAN0.TMDF150.UINT8[R_IO_HH]) +#define RSCAN0TMID51 (RSCAN0.TMID51.UINT32) +#define RSCAN0TMID51L (RSCAN0.TMID51.UINT16[R_IO_L]) +#define RSCAN0TMID51LL (RSCAN0.TMID51.UINT8[R_IO_LL]) +#define RSCAN0TMID51LH (RSCAN0.TMID51.UINT8[R_IO_LH]) +#define RSCAN0TMID51H (RSCAN0.TMID51.UINT16[R_IO_H]) +#define RSCAN0TMID51HL (RSCAN0.TMID51.UINT8[R_IO_HL]) +#define RSCAN0TMID51HH (RSCAN0.TMID51.UINT8[R_IO_HH]) +#define RSCAN0TMPTR51 (RSCAN0.TMPTR51.UINT32) +#define RSCAN0TMPTR51L (RSCAN0.TMPTR51.UINT16[R_IO_L]) +#define RSCAN0TMPTR51LL (RSCAN0.TMPTR51.UINT8[R_IO_LL]) +#define RSCAN0TMPTR51LH (RSCAN0.TMPTR51.UINT8[R_IO_LH]) +#define RSCAN0TMPTR51H (RSCAN0.TMPTR51.UINT16[R_IO_H]) +#define RSCAN0TMPTR51HL (RSCAN0.TMPTR51.UINT8[R_IO_HL]) +#define RSCAN0TMPTR51HH (RSCAN0.TMPTR51.UINT8[R_IO_HH]) +#define RSCAN0TMDF051 (RSCAN0.TMDF051.UINT32) +#define RSCAN0TMDF051L (RSCAN0.TMDF051.UINT16[R_IO_L]) +#define RSCAN0TMDF051LL (RSCAN0.TMDF051.UINT8[R_IO_LL]) +#define RSCAN0TMDF051LH (RSCAN0.TMDF051.UINT8[R_IO_LH]) +#define RSCAN0TMDF051H (RSCAN0.TMDF051.UINT16[R_IO_H]) +#define RSCAN0TMDF051HL (RSCAN0.TMDF051.UINT8[R_IO_HL]) +#define RSCAN0TMDF051HH (RSCAN0.TMDF051.UINT8[R_IO_HH]) +#define RSCAN0TMDF151 (RSCAN0.TMDF151.UINT32) +#define RSCAN0TMDF151L (RSCAN0.TMDF151.UINT16[R_IO_L]) +#define RSCAN0TMDF151LL (RSCAN0.TMDF151.UINT8[R_IO_LL]) +#define RSCAN0TMDF151LH (RSCAN0.TMDF151.UINT8[R_IO_LH]) +#define RSCAN0TMDF151H (RSCAN0.TMDF151.UINT16[R_IO_H]) +#define RSCAN0TMDF151HL (RSCAN0.TMDF151.UINT8[R_IO_HL]) +#define RSCAN0TMDF151HH (RSCAN0.TMDF151.UINT8[R_IO_HH]) +#define RSCAN0TMID52 (RSCAN0.TMID52.UINT32) +#define RSCAN0TMID52L (RSCAN0.TMID52.UINT16[R_IO_L]) +#define RSCAN0TMID52LL (RSCAN0.TMID52.UINT8[R_IO_LL]) +#define RSCAN0TMID52LH (RSCAN0.TMID52.UINT8[R_IO_LH]) +#define RSCAN0TMID52H (RSCAN0.TMID52.UINT16[R_IO_H]) +#define RSCAN0TMID52HL (RSCAN0.TMID52.UINT8[R_IO_HL]) +#define RSCAN0TMID52HH (RSCAN0.TMID52.UINT8[R_IO_HH]) +#define RSCAN0TMPTR52 (RSCAN0.TMPTR52.UINT32) +#define RSCAN0TMPTR52L (RSCAN0.TMPTR52.UINT16[R_IO_L]) +#define RSCAN0TMPTR52LL (RSCAN0.TMPTR52.UINT8[R_IO_LL]) +#define RSCAN0TMPTR52LH (RSCAN0.TMPTR52.UINT8[R_IO_LH]) +#define RSCAN0TMPTR52H (RSCAN0.TMPTR52.UINT16[R_IO_H]) +#define RSCAN0TMPTR52HL (RSCAN0.TMPTR52.UINT8[R_IO_HL]) +#define RSCAN0TMPTR52HH (RSCAN0.TMPTR52.UINT8[R_IO_HH]) +#define RSCAN0TMDF052 (RSCAN0.TMDF052.UINT32) +#define RSCAN0TMDF052L (RSCAN0.TMDF052.UINT16[R_IO_L]) +#define RSCAN0TMDF052LL (RSCAN0.TMDF052.UINT8[R_IO_LL]) +#define RSCAN0TMDF052LH (RSCAN0.TMDF052.UINT8[R_IO_LH]) +#define RSCAN0TMDF052H (RSCAN0.TMDF052.UINT16[R_IO_H]) +#define RSCAN0TMDF052HL (RSCAN0.TMDF052.UINT8[R_IO_HL]) +#define RSCAN0TMDF052HH (RSCAN0.TMDF052.UINT8[R_IO_HH]) +#define RSCAN0TMDF152 (RSCAN0.TMDF152.UINT32) +#define RSCAN0TMDF152L (RSCAN0.TMDF152.UINT16[R_IO_L]) +#define RSCAN0TMDF152LL (RSCAN0.TMDF152.UINT8[R_IO_LL]) +#define RSCAN0TMDF152LH (RSCAN0.TMDF152.UINT8[R_IO_LH]) +#define RSCAN0TMDF152H (RSCAN0.TMDF152.UINT16[R_IO_H]) +#define RSCAN0TMDF152HL (RSCAN0.TMDF152.UINT8[R_IO_HL]) +#define RSCAN0TMDF152HH (RSCAN0.TMDF152.UINT8[R_IO_HH]) +#define RSCAN0TMID53 (RSCAN0.TMID53.UINT32) +#define RSCAN0TMID53L (RSCAN0.TMID53.UINT16[R_IO_L]) +#define RSCAN0TMID53LL (RSCAN0.TMID53.UINT8[R_IO_LL]) +#define RSCAN0TMID53LH (RSCAN0.TMID53.UINT8[R_IO_LH]) +#define RSCAN0TMID53H (RSCAN0.TMID53.UINT16[R_IO_H]) +#define RSCAN0TMID53HL (RSCAN0.TMID53.UINT8[R_IO_HL]) +#define RSCAN0TMID53HH (RSCAN0.TMID53.UINT8[R_IO_HH]) +#define RSCAN0TMPTR53 (RSCAN0.TMPTR53.UINT32) +#define RSCAN0TMPTR53L (RSCAN0.TMPTR53.UINT16[R_IO_L]) +#define RSCAN0TMPTR53LL (RSCAN0.TMPTR53.UINT8[R_IO_LL]) +#define RSCAN0TMPTR53LH (RSCAN0.TMPTR53.UINT8[R_IO_LH]) +#define RSCAN0TMPTR53H (RSCAN0.TMPTR53.UINT16[R_IO_H]) +#define RSCAN0TMPTR53HL (RSCAN0.TMPTR53.UINT8[R_IO_HL]) +#define RSCAN0TMPTR53HH (RSCAN0.TMPTR53.UINT8[R_IO_HH]) +#define RSCAN0TMDF053 (RSCAN0.TMDF053.UINT32) +#define RSCAN0TMDF053L (RSCAN0.TMDF053.UINT16[R_IO_L]) +#define RSCAN0TMDF053LL (RSCAN0.TMDF053.UINT8[R_IO_LL]) +#define RSCAN0TMDF053LH (RSCAN0.TMDF053.UINT8[R_IO_LH]) +#define RSCAN0TMDF053H (RSCAN0.TMDF053.UINT16[R_IO_H]) +#define RSCAN0TMDF053HL (RSCAN0.TMDF053.UINT8[R_IO_HL]) +#define RSCAN0TMDF053HH (RSCAN0.TMDF053.UINT8[R_IO_HH]) +#define RSCAN0TMDF153 (RSCAN0.TMDF153.UINT32) +#define RSCAN0TMDF153L (RSCAN0.TMDF153.UINT16[R_IO_L]) +#define RSCAN0TMDF153LL (RSCAN0.TMDF153.UINT8[R_IO_LL]) +#define RSCAN0TMDF153LH (RSCAN0.TMDF153.UINT8[R_IO_LH]) +#define RSCAN0TMDF153H (RSCAN0.TMDF153.UINT16[R_IO_H]) +#define RSCAN0TMDF153HL (RSCAN0.TMDF153.UINT8[R_IO_HL]) +#define RSCAN0TMDF153HH (RSCAN0.TMDF153.UINT8[R_IO_HH]) +#define RSCAN0TMID54 (RSCAN0.TMID54.UINT32) +#define RSCAN0TMID54L (RSCAN0.TMID54.UINT16[R_IO_L]) +#define RSCAN0TMID54LL (RSCAN0.TMID54.UINT8[R_IO_LL]) +#define RSCAN0TMID54LH (RSCAN0.TMID54.UINT8[R_IO_LH]) +#define RSCAN0TMID54H (RSCAN0.TMID54.UINT16[R_IO_H]) +#define RSCAN0TMID54HL (RSCAN0.TMID54.UINT8[R_IO_HL]) +#define RSCAN0TMID54HH (RSCAN0.TMID54.UINT8[R_IO_HH]) +#define RSCAN0TMPTR54 (RSCAN0.TMPTR54.UINT32) +#define RSCAN0TMPTR54L (RSCAN0.TMPTR54.UINT16[R_IO_L]) +#define RSCAN0TMPTR54LL (RSCAN0.TMPTR54.UINT8[R_IO_LL]) +#define RSCAN0TMPTR54LH (RSCAN0.TMPTR54.UINT8[R_IO_LH]) +#define RSCAN0TMPTR54H (RSCAN0.TMPTR54.UINT16[R_IO_H]) +#define RSCAN0TMPTR54HL (RSCAN0.TMPTR54.UINT8[R_IO_HL]) +#define RSCAN0TMPTR54HH (RSCAN0.TMPTR54.UINT8[R_IO_HH]) +#define RSCAN0TMDF054 (RSCAN0.TMDF054.UINT32) +#define RSCAN0TMDF054L (RSCAN0.TMDF054.UINT16[R_IO_L]) +#define RSCAN0TMDF054LL (RSCAN0.TMDF054.UINT8[R_IO_LL]) +#define RSCAN0TMDF054LH (RSCAN0.TMDF054.UINT8[R_IO_LH]) +#define RSCAN0TMDF054H (RSCAN0.TMDF054.UINT16[R_IO_H]) +#define RSCAN0TMDF054HL (RSCAN0.TMDF054.UINT8[R_IO_HL]) +#define RSCAN0TMDF054HH (RSCAN0.TMDF054.UINT8[R_IO_HH]) +#define RSCAN0TMDF154 (RSCAN0.TMDF154.UINT32) +#define RSCAN0TMDF154L (RSCAN0.TMDF154.UINT16[R_IO_L]) +#define RSCAN0TMDF154LL (RSCAN0.TMDF154.UINT8[R_IO_LL]) +#define RSCAN0TMDF154LH (RSCAN0.TMDF154.UINT8[R_IO_LH]) +#define RSCAN0TMDF154H (RSCAN0.TMDF154.UINT16[R_IO_H]) +#define RSCAN0TMDF154HL (RSCAN0.TMDF154.UINT8[R_IO_HL]) +#define RSCAN0TMDF154HH (RSCAN0.TMDF154.UINT8[R_IO_HH]) +#define RSCAN0TMID55 (RSCAN0.TMID55.UINT32) +#define RSCAN0TMID55L (RSCAN0.TMID55.UINT16[R_IO_L]) +#define RSCAN0TMID55LL (RSCAN0.TMID55.UINT8[R_IO_LL]) +#define RSCAN0TMID55LH (RSCAN0.TMID55.UINT8[R_IO_LH]) +#define RSCAN0TMID55H (RSCAN0.TMID55.UINT16[R_IO_H]) +#define RSCAN0TMID55HL (RSCAN0.TMID55.UINT8[R_IO_HL]) +#define RSCAN0TMID55HH (RSCAN0.TMID55.UINT8[R_IO_HH]) +#define RSCAN0TMPTR55 (RSCAN0.TMPTR55.UINT32) +#define RSCAN0TMPTR55L (RSCAN0.TMPTR55.UINT16[R_IO_L]) +#define RSCAN0TMPTR55LL (RSCAN0.TMPTR55.UINT8[R_IO_LL]) +#define RSCAN0TMPTR55LH (RSCAN0.TMPTR55.UINT8[R_IO_LH]) +#define RSCAN0TMPTR55H (RSCAN0.TMPTR55.UINT16[R_IO_H]) +#define RSCAN0TMPTR55HL (RSCAN0.TMPTR55.UINT8[R_IO_HL]) +#define RSCAN0TMPTR55HH (RSCAN0.TMPTR55.UINT8[R_IO_HH]) +#define RSCAN0TMDF055 (RSCAN0.TMDF055.UINT32) +#define RSCAN0TMDF055L (RSCAN0.TMDF055.UINT16[R_IO_L]) +#define RSCAN0TMDF055LL (RSCAN0.TMDF055.UINT8[R_IO_LL]) +#define RSCAN0TMDF055LH (RSCAN0.TMDF055.UINT8[R_IO_LH]) +#define RSCAN0TMDF055H (RSCAN0.TMDF055.UINT16[R_IO_H]) +#define RSCAN0TMDF055HL (RSCAN0.TMDF055.UINT8[R_IO_HL]) +#define RSCAN0TMDF055HH (RSCAN0.TMDF055.UINT8[R_IO_HH]) +#define RSCAN0TMDF155 (RSCAN0.TMDF155.UINT32) +#define RSCAN0TMDF155L (RSCAN0.TMDF155.UINT16[R_IO_L]) +#define RSCAN0TMDF155LL (RSCAN0.TMDF155.UINT8[R_IO_LL]) +#define RSCAN0TMDF155LH (RSCAN0.TMDF155.UINT8[R_IO_LH]) +#define RSCAN0TMDF155H (RSCAN0.TMDF155.UINT16[R_IO_H]) +#define RSCAN0TMDF155HL (RSCAN0.TMDF155.UINT8[R_IO_HL]) +#define RSCAN0TMDF155HH (RSCAN0.TMDF155.UINT8[R_IO_HH]) +#define RSCAN0TMID56 (RSCAN0.TMID56.UINT32) +#define RSCAN0TMID56L (RSCAN0.TMID56.UINT16[R_IO_L]) +#define RSCAN0TMID56LL (RSCAN0.TMID56.UINT8[R_IO_LL]) +#define RSCAN0TMID56LH (RSCAN0.TMID56.UINT8[R_IO_LH]) +#define RSCAN0TMID56H (RSCAN0.TMID56.UINT16[R_IO_H]) +#define RSCAN0TMID56HL (RSCAN0.TMID56.UINT8[R_IO_HL]) +#define RSCAN0TMID56HH (RSCAN0.TMID56.UINT8[R_IO_HH]) +#define RSCAN0TMPTR56 (RSCAN0.TMPTR56.UINT32) +#define RSCAN0TMPTR56L (RSCAN0.TMPTR56.UINT16[R_IO_L]) +#define RSCAN0TMPTR56LL (RSCAN0.TMPTR56.UINT8[R_IO_LL]) +#define RSCAN0TMPTR56LH (RSCAN0.TMPTR56.UINT8[R_IO_LH]) +#define RSCAN0TMPTR56H (RSCAN0.TMPTR56.UINT16[R_IO_H]) +#define RSCAN0TMPTR56HL (RSCAN0.TMPTR56.UINT8[R_IO_HL]) +#define RSCAN0TMPTR56HH (RSCAN0.TMPTR56.UINT8[R_IO_HH]) +#define RSCAN0TMDF056 (RSCAN0.TMDF056.UINT32) +#define RSCAN0TMDF056L (RSCAN0.TMDF056.UINT16[R_IO_L]) +#define RSCAN0TMDF056LL (RSCAN0.TMDF056.UINT8[R_IO_LL]) +#define RSCAN0TMDF056LH (RSCAN0.TMDF056.UINT8[R_IO_LH]) +#define RSCAN0TMDF056H (RSCAN0.TMDF056.UINT16[R_IO_H]) +#define RSCAN0TMDF056HL (RSCAN0.TMDF056.UINT8[R_IO_HL]) +#define RSCAN0TMDF056HH (RSCAN0.TMDF056.UINT8[R_IO_HH]) +#define RSCAN0TMDF156 (RSCAN0.TMDF156.UINT32) +#define RSCAN0TMDF156L (RSCAN0.TMDF156.UINT16[R_IO_L]) +#define RSCAN0TMDF156LL (RSCAN0.TMDF156.UINT8[R_IO_LL]) +#define RSCAN0TMDF156LH (RSCAN0.TMDF156.UINT8[R_IO_LH]) +#define RSCAN0TMDF156H (RSCAN0.TMDF156.UINT16[R_IO_H]) +#define RSCAN0TMDF156HL (RSCAN0.TMDF156.UINT8[R_IO_HL]) +#define RSCAN0TMDF156HH (RSCAN0.TMDF156.UINT8[R_IO_HH]) +#define RSCAN0TMID57 (RSCAN0.TMID57.UINT32) +#define RSCAN0TMID57L (RSCAN0.TMID57.UINT16[R_IO_L]) +#define RSCAN0TMID57LL (RSCAN0.TMID57.UINT8[R_IO_LL]) +#define RSCAN0TMID57LH (RSCAN0.TMID57.UINT8[R_IO_LH]) +#define RSCAN0TMID57H (RSCAN0.TMID57.UINT16[R_IO_H]) +#define RSCAN0TMID57HL (RSCAN0.TMID57.UINT8[R_IO_HL]) +#define RSCAN0TMID57HH (RSCAN0.TMID57.UINT8[R_IO_HH]) +#define RSCAN0TMPTR57 (RSCAN0.TMPTR57.UINT32) +#define RSCAN0TMPTR57L (RSCAN0.TMPTR57.UINT16[R_IO_L]) +#define RSCAN0TMPTR57LL (RSCAN0.TMPTR57.UINT8[R_IO_LL]) +#define RSCAN0TMPTR57LH (RSCAN0.TMPTR57.UINT8[R_IO_LH]) +#define RSCAN0TMPTR57H (RSCAN0.TMPTR57.UINT16[R_IO_H]) +#define RSCAN0TMPTR57HL (RSCAN0.TMPTR57.UINT8[R_IO_HL]) +#define RSCAN0TMPTR57HH (RSCAN0.TMPTR57.UINT8[R_IO_HH]) +#define RSCAN0TMDF057 (RSCAN0.TMDF057.UINT32) +#define RSCAN0TMDF057L (RSCAN0.TMDF057.UINT16[R_IO_L]) +#define RSCAN0TMDF057LL (RSCAN0.TMDF057.UINT8[R_IO_LL]) +#define RSCAN0TMDF057LH (RSCAN0.TMDF057.UINT8[R_IO_LH]) +#define RSCAN0TMDF057H (RSCAN0.TMDF057.UINT16[R_IO_H]) +#define RSCAN0TMDF057HL (RSCAN0.TMDF057.UINT8[R_IO_HL]) +#define RSCAN0TMDF057HH (RSCAN0.TMDF057.UINT8[R_IO_HH]) +#define RSCAN0TMDF157 (RSCAN0.TMDF157.UINT32) +#define RSCAN0TMDF157L (RSCAN0.TMDF157.UINT16[R_IO_L]) +#define RSCAN0TMDF157LL (RSCAN0.TMDF157.UINT8[R_IO_LL]) +#define RSCAN0TMDF157LH (RSCAN0.TMDF157.UINT8[R_IO_LH]) +#define RSCAN0TMDF157H (RSCAN0.TMDF157.UINT16[R_IO_H]) +#define RSCAN0TMDF157HL (RSCAN0.TMDF157.UINT8[R_IO_HL]) +#define RSCAN0TMDF157HH (RSCAN0.TMDF157.UINT8[R_IO_HH]) +#define RSCAN0TMID58 (RSCAN0.TMID58.UINT32) +#define RSCAN0TMID58L (RSCAN0.TMID58.UINT16[R_IO_L]) +#define RSCAN0TMID58LL (RSCAN0.TMID58.UINT8[R_IO_LL]) +#define RSCAN0TMID58LH (RSCAN0.TMID58.UINT8[R_IO_LH]) +#define RSCAN0TMID58H (RSCAN0.TMID58.UINT16[R_IO_H]) +#define RSCAN0TMID58HL (RSCAN0.TMID58.UINT8[R_IO_HL]) +#define RSCAN0TMID58HH (RSCAN0.TMID58.UINT8[R_IO_HH]) +#define RSCAN0TMPTR58 (RSCAN0.TMPTR58.UINT32) +#define RSCAN0TMPTR58L (RSCAN0.TMPTR58.UINT16[R_IO_L]) +#define RSCAN0TMPTR58LL (RSCAN0.TMPTR58.UINT8[R_IO_LL]) +#define RSCAN0TMPTR58LH (RSCAN0.TMPTR58.UINT8[R_IO_LH]) +#define RSCAN0TMPTR58H (RSCAN0.TMPTR58.UINT16[R_IO_H]) +#define RSCAN0TMPTR58HL (RSCAN0.TMPTR58.UINT8[R_IO_HL]) +#define RSCAN0TMPTR58HH (RSCAN0.TMPTR58.UINT8[R_IO_HH]) +#define RSCAN0TMDF058 (RSCAN0.TMDF058.UINT32) +#define RSCAN0TMDF058L (RSCAN0.TMDF058.UINT16[R_IO_L]) +#define RSCAN0TMDF058LL (RSCAN0.TMDF058.UINT8[R_IO_LL]) +#define RSCAN0TMDF058LH (RSCAN0.TMDF058.UINT8[R_IO_LH]) +#define RSCAN0TMDF058H (RSCAN0.TMDF058.UINT16[R_IO_H]) +#define RSCAN0TMDF058HL (RSCAN0.TMDF058.UINT8[R_IO_HL]) +#define RSCAN0TMDF058HH (RSCAN0.TMDF058.UINT8[R_IO_HH]) +#define RSCAN0TMDF158 (RSCAN0.TMDF158.UINT32) +#define RSCAN0TMDF158L (RSCAN0.TMDF158.UINT16[R_IO_L]) +#define RSCAN0TMDF158LL (RSCAN0.TMDF158.UINT8[R_IO_LL]) +#define RSCAN0TMDF158LH (RSCAN0.TMDF158.UINT8[R_IO_LH]) +#define RSCAN0TMDF158H (RSCAN0.TMDF158.UINT16[R_IO_H]) +#define RSCAN0TMDF158HL (RSCAN0.TMDF158.UINT8[R_IO_HL]) +#define RSCAN0TMDF158HH (RSCAN0.TMDF158.UINT8[R_IO_HH]) +#define RSCAN0TMID59 (RSCAN0.TMID59.UINT32) +#define RSCAN0TMID59L (RSCAN0.TMID59.UINT16[R_IO_L]) +#define RSCAN0TMID59LL (RSCAN0.TMID59.UINT8[R_IO_LL]) +#define RSCAN0TMID59LH (RSCAN0.TMID59.UINT8[R_IO_LH]) +#define RSCAN0TMID59H (RSCAN0.TMID59.UINT16[R_IO_H]) +#define RSCAN0TMID59HL (RSCAN0.TMID59.UINT8[R_IO_HL]) +#define RSCAN0TMID59HH (RSCAN0.TMID59.UINT8[R_IO_HH]) +#define RSCAN0TMPTR59 (RSCAN0.TMPTR59.UINT32) +#define RSCAN0TMPTR59L (RSCAN0.TMPTR59.UINT16[R_IO_L]) +#define RSCAN0TMPTR59LL (RSCAN0.TMPTR59.UINT8[R_IO_LL]) +#define RSCAN0TMPTR59LH (RSCAN0.TMPTR59.UINT8[R_IO_LH]) +#define RSCAN0TMPTR59H (RSCAN0.TMPTR59.UINT16[R_IO_H]) +#define RSCAN0TMPTR59HL (RSCAN0.TMPTR59.UINT8[R_IO_HL]) +#define RSCAN0TMPTR59HH (RSCAN0.TMPTR59.UINT8[R_IO_HH]) +#define RSCAN0TMDF059 (RSCAN0.TMDF059.UINT32) +#define RSCAN0TMDF059L (RSCAN0.TMDF059.UINT16[R_IO_L]) +#define RSCAN0TMDF059LL (RSCAN0.TMDF059.UINT8[R_IO_LL]) +#define RSCAN0TMDF059LH (RSCAN0.TMDF059.UINT8[R_IO_LH]) +#define RSCAN0TMDF059H (RSCAN0.TMDF059.UINT16[R_IO_H]) +#define RSCAN0TMDF059HL (RSCAN0.TMDF059.UINT8[R_IO_HL]) +#define RSCAN0TMDF059HH (RSCAN0.TMDF059.UINT8[R_IO_HH]) +#define RSCAN0TMDF159 (RSCAN0.TMDF159.UINT32) +#define RSCAN0TMDF159L (RSCAN0.TMDF159.UINT16[R_IO_L]) +#define RSCAN0TMDF159LL (RSCAN0.TMDF159.UINT8[R_IO_LL]) +#define RSCAN0TMDF159LH (RSCAN0.TMDF159.UINT8[R_IO_LH]) +#define RSCAN0TMDF159H (RSCAN0.TMDF159.UINT16[R_IO_H]) +#define RSCAN0TMDF159HL (RSCAN0.TMDF159.UINT8[R_IO_HL]) +#define RSCAN0TMDF159HH (RSCAN0.TMDF159.UINT8[R_IO_HH]) +#define RSCAN0TMID60 (RSCAN0.TMID60.UINT32) +#define RSCAN0TMID60L (RSCAN0.TMID60.UINT16[R_IO_L]) +#define RSCAN0TMID60LL (RSCAN0.TMID60.UINT8[R_IO_LL]) +#define RSCAN0TMID60LH (RSCAN0.TMID60.UINT8[R_IO_LH]) +#define RSCAN0TMID60H (RSCAN0.TMID60.UINT16[R_IO_H]) +#define RSCAN0TMID60HL (RSCAN0.TMID60.UINT8[R_IO_HL]) +#define RSCAN0TMID60HH (RSCAN0.TMID60.UINT8[R_IO_HH]) +#define RSCAN0TMPTR60 (RSCAN0.TMPTR60.UINT32) +#define RSCAN0TMPTR60L (RSCAN0.TMPTR60.UINT16[R_IO_L]) +#define RSCAN0TMPTR60LL (RSCAN0.TMPTR60.UINT8[R_IO_LL]) +#define RSCAN0TMPTR60LH (RSCAN0.TMPTR60.UINT8[R_IO_LH]) +#define RSCAN0TMPTR60H (RSCAN0.TMPTR60.UINT16[R_IO_H]) +#define RSCAN0TMPTR60HL (RSCAN0.TMPTR60.UINT8[R_IO_HL]) +#define RSCAN0TMPTR60HH (RSCAN0.TMPTR60.UINT8[R_IO_HH]) +#define RSCAN0TMDF060 (RSCAN0.TMDF060.UINT32) +#define RSCAN0TMDF060L (RSCAN0.TMDF060.UINT16[R_IO_L]) +#define RSCAN0TMDF060LL (RSCAN0.TMDF060.UINT8[R_IO_LL]) +#define RSCAN0TMDF060LH (RSCAN0.TMDF060.UINT8[R_IO_LH]) +#define RSCAN0TMDF060H (RSCAN0.TMDF060.UINT16[R_IO_H]) +#define RSCAN0TMDF060HL (RSCAN0.TMDF060.UINT8[R_IO_HL]) +#define RSCAN0TMDF060HH (RSCAN0.TMDF060.UINT8[R_IO_HH]) +#define RSCAN0TMDF160 (RSCAN0.TMDF160.UINT32) +#define RSCAN0TMDF160L (RSCAN0.TMDF160.UINT16[R_IO_L]) +#define RSCAN0TMDF160LL (RSCAN0.TMDF160.UINT8[R_IO_LL]) +#define RSCAN0TMDF160LH (RSCAN0.TMDF160.UINT8[R_IO_LH]) +#define RSCAN0TMDF160H (RSCAN0.TMDF160.UINT16[R_IO_H]) +#define RSCAN0TMDF160HL (RSCAN0.TMDF160.UINT8[R_IO_HL]) +#define RSCAN0TMDF160HH (RSCAN0.TMDF160.UINT8[R_IO_HH]) +#define RSCAN0TMID61 (RSCAN0.TMID61.UINT32) +#define RSCAN0TMID61L (RSCAN0.TMID61.UINT16[R_IO_L]) +#define RSCAN0TMID61LL (RSCAN0.TMID61.UINT8[R_IO_LL]) +#define RSCAN0TMID61LH (RSCAN0.TMID61.UINT8[R_IO_LH]) +#define RSCAN0TMID61H (RSCAN0.TMID61.UINT16[R_IO_H]) +#define RSCAN0TMID61HL (RSCAN0.TMID61.UINT8[R_IO_HL]) +#define RSCAN0TMID61HH (RSCAN0.TMID61.UINT8[R_IO_HH]) +#define RSCAN0TMPTR61 (RSCAN0.TMPTR61.UINT32) +#define RSCAN0TMPTR61L (RSCAN0.TMPTR61.UINT16[R_IO_L]) +#define RSCAN0TMPTR61LL (RSCAN0.TMPTR61.UINT8[R_IO_LL]) +#define RSCAN0TMPTR61LH (RSCAN0.TMPTR61.UINT8[R_IO_LH]) +#define RSCAN0TMPTR61H (RSCAN0.TMPTR61.UINT16[R_IO_H]) +#define RSCAN0TMPTR61HL (RSCAN0.TMPTR61.UINT8[R_IO_HL]) +#define RSCAN0TMPTR61HH (RSCAN0.TMPTR61.UINT8[R_IO_HH]) +#define RSCAN0TMDF061 (RSCAN0.TMDF061.UINT32) +#define RSCAN0TMDF061L (RSCAN0.TMDF061.UINT16[R_IO_L]) +#define RSCAN0TMDF061LL (RSCAN0.TMDF061.UINT8[R_IO_LL]) +#define RSCAN0TMDF061LH (RSCAN0.TMDF061.UINT8[R_IO_LH]) +#define RSCAN0TMDF061H (RSCAN0.TMDF061.UINT16[R_IO_H]) +#define RSCAN0TMDF061HL (RSCAN0.TMDF061.UINT8[R_IO_HL]) +#define RSCAN0TMDF061HH (RSCAN0.TMDF061.UINT8[R_IO_HH]) +#define RSCAN0TMDF161 (RSCAN0.TMDF161.UINT32) +#define RSCAN0TMDF161L (RSCAN0.TMDF161.UINT16[R_IO_L]) +#define RSCAN0TMDF161LL (RSCAN0.TMDF161.UINT8[R_IO_LL]) +#define RSCAN0TMDF161LH (RSCAN0.TMDF161.UINT8[R_IO_LH]) +#define RSCAN0TMDF161H (RSCAN0.TMDF161.UINT16[R_IO_H]) +#define RSCAN0TMDF161HL (RSCAN0.TMDF161.UINT8[R_IO_HL]) +#define RSCAN0TMDF161HH (RSCAN0.TMDF161.UINT8[R_IO_HH]) +#define RSCAN0TMID62 (RSCAN0.TMID62.UINT32) +#define RSCAN0TMID62L (RSCAN0.TMID62.UINT16[R_IO_L]) +#define RSCAN0TMID62LL (RSCAN0.TMID62.UINT8[R_IO_LL]) +#define RSCAN0TMID62LH (RSCAN0.TMID62.UINT8[R_IO_LH]) +#define RSCAN0TMID62H (RSCAN0.TMID62.UINT16[R_IO_H]) +#define RSCAN0TMID62HL (RSCAN0.TMID62.UINT8[R_IO_HL]) +#define RSCAN0TMID62HH (RSCAN0.TMID62.UINT8[R_IO_HH]) +#define RSCAN0TMPTR62 (RSCAN0.TMPTR62.UINT32) +#define RSCAN0TMPTR62L (RSCAN0.TMPTR62.UINT16[R_IO_L]) +#define RSCAN0TMPTR62LL (RSCAN0.TMPTR62.UINT8[R_IO_LL]) +#define RSCAN0TMPTR62LH (RSCAN0.TMPTR62.UINT8[R_IO_LH]) +#define RSCAN0TMPTR62H (RSCAN0.TMPTR62.UINT16[R_IO_H]) +#define RSCAN0TMPTR62HL (RSCAN0.TMPTR62.UINT8[R_IO_HL]) +#define RSCAN0TMPTR62HH (RSCAN0.TMPTR62.UINT8[R_IO_HH]) +#define RSCAN0TMDF062 (RSCAN0.TMDF062.UINT32) +#define RSCAN0TMDF062L (RSCAN0.TMDF062.UINT16[R_IO_L]) +#define RSCAN0TMDF062LL (RSCAN0.TMDF062.UINT8[R_IO_LL]) +#define RSCAN0TMDF062LH (RSCAN0.TMDF062.UINT8[R_IO_LH]) +#define RSCAN0TMDF062H (RSCAN0.TMDF062.UINT16[R_IO_H]) +#define RSCAN0TMDF062HL (RSCAN0.TMDF062.UINT8[R_IO_HL]) +#define RSCAN0TMDF062HH (RSCAN0.TMDF062.UINT8[R_IO_HH]) +#define RSCAN0TMDF162 (RSCAN0.TMDF162.UINT32) +#define RSCAN0TMDF162L (RSCAN0.TMDF162.UINT16[R_IO_L]) +#define RSCAN0TMDF162LL (RSCAN0.TMDF162.UINT8[R_IO_LL]) +#define RSCAN0TMDF162LH (RSCAN0.TMDF162.UINT8[R_IO_LH]) +#define RSCAN0TMDF162H (RSCAN0.TMDF162.UINT16[R_IO_H]) +#define RSCAN0TMDF162HL (RSCAN0.TMDF162.UINT8[R_IO_HL]) +#define RSCAN0TMDF162HH (RSCAN0.TMDF162.UINT8[R_IO_HH]) +#define RSCAN0TMID63 (RSCAN0.TMID63.UINT32) +#define RSCAN0TMID63L (RSCAN0.TMID63.UINT16[R_IO_L]) +#define RSCAN0TMID63LL (RSCAN0.TMID63.UINT8[R_IO_LL]) +#define RSCAN0TMID63LH (RSCAN0.TMID63.UINT8[R_IO_LH]) +#define RSCAN0TMID63H (RSCAN0.TMID63.UINT16[R_IO_H]) +#define RSCAN0TMID63HL (RSCAN0.TMID63.UINT8[R_IO_HL]) +#define RSCAN0TMID63HH (RSCAN0.TMID63.UINT8[R_IO_HH]) +#define RSCAN0TMPTR63 (RSCAN0.TMPTR63.UINT32) +#define RSCAN0TMPTR63L (RSCAN0.TMPTR63.UINT16[R_IO_L]) +#define RSCAN0TMPTR63LL (RSCAN0.TMPTR63.UINT8[R_IO_LL]) +#define RSCAN0TMPTR63LH (RSCAN0.TMPTR63.UINT8[R_IO_LH]) +#define RSCAN0TMPTR63H (RSCAN0.TMPTR63.UINT16[R_IO_H]) +#define RSCAN0TMPTR63HL (RSCAN0.TMPTR63.UINT8[R_IO_HL]) +#define RSCAN0TMPTR63HH (RSCAN0.TMPTR63.UINT8[R_IO_HH]) +#define RSCAN0TMDF063 (RSCAN0.TMDF063.UINT32) +#define RSCAN0TMDF063L (RSCAN0.TMDF063.UINT16[R_IO_L]) +#define RSCAN0TMDF063LL (RSCAN0.TMDF063.UINT8[R_IO_LL]) +#define RSCAN0TMDF063LH (RSCAN0.TMDF063.UINT8[R_IO_LH]) +#define RSCAN0TMDF063H (RSCAN0.TMDF063.UINT16[R_IO_H]) +#define RSCAN0TMDF063HL (RSCAN0.TMDF063.UINT8[R_IO_HL]) +#define RSCAN0TMDF063HH (RSCAN0.TMDF063.UINT8[R_IO_HH]) +#define RSCAN0TMDF163 (RSCAN0.TMDF163.UINT32) +#define RSCAN0TMDF163L (RSCAN0.TMDF163.UINT16[R_IO_L]) +#define RSCAN0TMDF163LL (RSCAN0.TMDF163.UINT8[R_IO_LL]) +#define RSCAN0TMDF163LH (RSCAN0.TMDF163.UINT8[R_IO_LH]) +#define RSCAN0TMDF163H (RSCAN0.TMDF163.UINT16[R_IO_H]) +#define RSCAN0TMDF163HL (RSCAN0.TMDF163.UINT8[R_IO_HL]) +#define RSCAN0TMDF163HH (RSCAN0.TMDF163.UINT8[R_IO_HH]) +#define RSCAN0TMID64 (RSCAN0.TMID64.UINT32) +#define RSCAN0TMID64L (RSCAN0.TMID64.UINT16[R_IO_L]) +#define RSCAN0TMID64LL (RSCAN0.TMID64.UINT8[R_IO_LL]) +#define RSCAN0TMID64LH (RSCAN0.TMID64.UINT8[R_IO_LH]) +#define RSCAN0TMID64H (RSCAN0.TMID64.UINT16[R_IO_H]) +#define RSCAN0TMID64HL (RSCAN0.TMID64.UINT8[R_IO_HL]) +#define RSCAN0TMID64HH (RSCAN0.TMID64.UINT8[R_IO_HH]) +#define RSCAN0TMPTR64 (RSCAN0.TMPTR64.UINT32) +#define RSCAN0TMPTR64L (RSCAN0.TMPTR64.UINT16[R_IO_L]) +#define RSCAN0TMPTR64LL (RSCAN0.TMPTR64.UINT8[R_IO_LL]) +#define RSCAN0TMPTR64LH (RSCAN0.TMPTR64.UINT8[R_IO_LH]) +#define RSCAN0TMPTR64H (RSCAN0.TMPTR64.UINT16[R_IO_H]) +#define RSCAN0TMPTR64HL (RSCAN0.TMPTR64.UINT8[R_IO_HL]) +#define RSCAN0TMPTR64HH (RSCAN0.TMPTR64.UINT8[R_IO_HH]) +#define RSCAN0TMDF064 (RSCAN0.TMDF064.UINT32) +#define RSCAN0TMDF064L (RSCAN0.TMDF064.UINT16[R_IO_L]) +#define RSCAN0TMDF064LL (RSCAN0.TMDF064.UINT8[R_IO_LL]) +#define RSCAN0TMDF064LH (RSCAN0.TMDF064.UINT8[R_IO_LH]) +#define RSCAN0TMDF064H (RSCAN0.TMDF064.UINT16[R_IO_H]) +#define RSCAN0TMDF064HL (RSCAN0.TMDF064.UINT8[R_IO_HL]) +#define RSCAN0TMDF064HH (RSCAN0.TMDF064.UINT8[R_IO_HH]) +#define RSCAN0TMDF164 (RSCAN0.TMDF164.UINT32) +#define RSCAN0TMDF164L (RSCAN0.TMDF164.UINT16[R_IO_L]) +#define RSCAN0TMDF164LL (RSCAN0.TMDF164.UINT8[R_IO_LL]) +#define RSCAN0TMDF164LH (RSCAN0.TMDF164.UINT8[R_IO_LH]) +#define RSCAN0TMDF164H (RSCAN0.TMDF164.UINT16[R_IO_H]) +#define RSCAN0TMDF164HL (RSCAN0.TMDF164.UINT8[R_IO_HL]) +#define RSCAN0TMDF164HH (RSCAN0.TMDF164.UINT8[R_IO_HH]) +#define RSCAN0TMID65 (RSCAN0.TMID65.UINT32) +#define RSCAN0TMID65L (RSCAN0.TMID65.UINT16[R_IO_L]) +#define RSCAN0TMID65LL (RSCAN0.TMID65.UINT8[R_IO_LL]) +#define RSCAN0TMID65LH (RSCAN0.TMID65.UINT8[R_IO_LH]) +#define RSCAN0TMID65H (RSCAN0.TMID65.UINT16[R_IO_H]) +#define RSCAN0TMID65HL (RSCAN0.TMID65.UINT8[R_IO_HL]) +#define RSCAN0TMID65HH (RSCAN0.TMID65.UINT8[R_IO_HH]) +#define RSCAN0TMPTR65 (RSCAN0.TMPTR65.UINT32) +#define RSCAN0TMPTR65L (RSCAN0.TMPTR65.UINT16[R_IO_L]) +#define RSCAN0TMPTR65LL (RSCAN0.TMPTR65.UINT8[R_IO_LL]) +#define RSCAN0TMPTR65LH (RSCAN0.TMPTR65.UINT8[R_IO_LH]) +#define RSCAN0TMPTR65H (RSCAN0.TMPTR65.UINT16[R_IO_H]) +#define RSCAN0TMPTR65HL (RSCAN0.TMPTR65.UINT8[R_IO_HL]) +#define RSCAN0TMPTR65HH (RSCAN0.TMPTR65.UINT8[R_IO_HH]) +#define RSCAN0TMDF065 (RSCAN0.TMDF065.UINT32) +#define RSCAN0TMDF065L (RSCAN0.TMDF065.UINT16[R_IO_L]) +#define RSCAN0TMDF065LL (RSCAN0.TMDF065.UINT8[R_IO_LL]) +#define RSCAN0TMDF065LH (RSCAN0.TMDF065.UINT8[R_IO_LH]) +#define RSCAN0TMDF065H (RSCAN0.TMDF065.UINT16[R_IO_H]) +#define RSCAN0TMDF065HL (RSCAN0.TMDF065.UINT8[R_IO_HL]) +#define RSCAN0TMDF065HH (RSCAN0.TMDF065.UINT8[R_IO_HH]) +#define RSCAN0TMDF165 (RSCAN0.TMDF165.UINT32) +#define RSCAN0TMDF165L (RSCAN0.TMDF165.UINT16[R_IO_L]) +#define RSCAN0TMDF165LL (RSCAN0.TMDF165.UINT8[R_IO_LL]) +#define RSCAN0TMDF165LH (RSCAN0.TMDF165.UINT8[R_IO_LH]) +#define RSCAN0TMDF165H (RSCAN0.TMDF165.UINT16[R_IO_H]) +#define RSCAN0TMDF165HL (RSCAN0.TMDF165.UINT8[R_IO_HL]) +#define RSCAN0TMDF165HH (RSCAN0.TMDF165.UINT8[R_IO_HH]) +#define RSCAN0TMID66 (RSCAN0.TMID66.UINT32) +#define RSCAN0TMID66L (RSCAN0.TMID66.UINT16[R_IO_L]) +#define RSCAN0TMID66LL (RSCAN0.TMID66.UINT8[R_IO_LL]) +#define RSCAN0TMID66LH (RSCAN0.TMID66.UINT8[R_IO_LH]) +#define RSCAN0TMID66H (RSCAN0.TMID66.UINT16[R_IO_H]) +#define RSCAN0TMID66HL (RSCAN0.TMID66.UINT8[R_IO_HL]) +#define RSCAN0TMID66HH (RSCAN0.TMID66.UINT8[R_IO_HH]) +#define RSCAN0TMPTR66 (RSCAN0.TMPTR66.UINT32) +#define RSCAN0TMPTR66L (RSCAN0.TMPTR66.UINT16[R_IO_L]) +#define RSCAN0TMPTR66LL (RSCAN0.TMPTR66.UINT8[R_IO_LL]) +#define RSCAN0TMPTR66LH (RSCAN0.TMPTR66.UINT8[R_IO_LH]) +#define RSCAN0TMPTR66H (RSCAN0.TMPTR66.UINT16[R_IO_H]) +#define RSCAN0TMPTR66HL (RSCAN0.TMPTR66.UINT8[R_IO_HL]) +#define RSCAN0TMPTR66HH (RSCAN0.TMPTR66.UINT8[R_IO_HH]) +#define RSCAN0TMDF066 (RSCAN0.TMDF066.UINT32) +#define RSCAN0TMDF066L (RSCAN0.TMDF066.UINT16[R_IO_L]) +#define RSCAN0TMDF066LL (RSCAN0.TMDF066.UINT8[R_IO_LL]) +#define RSCAN0TMDF066LH (RSCAN0.TMDF066.UINT8[R_IO_LH]) +#define RSCAN0TMDF066H (RSCAN0.TMDF066.UINT16[R_IO_H]) +#define RSCAN0TMDF066HL (RSCAN0.TMDF066.UINT8[R_IO_HL]) +#define RSCAN0TMDF066HH (RSCAN0.TMDF066.UINT8[R_IO_HH]) +#define RSCAN0TMDF166 (RSCAN0.TMDF166.UINT32) +#define RSCAN0TMDF166L (RSCAN0.TMDF166.UINT16[R_IO_L]) +#define RSCAN0TMDF166LL (RSCAN0.TMDF166.UINT8[R_IO_LL]) +#define RSCAN0TMDF166LH (RSCAN0.TMDF166.UINT8[R_IO_LH]) +#define RSCAN0TMDF166H (RSCAN0.TMDF166.UINT16[R_IO_H]) +#define RSCAN0TMDF166HL (RSCAN0.TMDF166.UINT8[R_IO_HL]) +#define RSCAN0TMDF166HH (RSCAN0.TMDF166.UINT8[R_IO_HH]) +#define RSCAN0TMID67 (RSCAN0.TMID67.UINT32) +#define RSCAN0TMID67L (RSCAN0.TMID67.UINT16[R_IO_L]) +#define RSCAN0TMID67LL (RSCAN0.TMID67.UINT8[R_IO_LL]) +#define RSCAN0TMID67LH (RSCAN0.TMID67.UINT8[R_IO_LH]) +#define RSCAN0TMID67H (RSCAN0.TMID67.UINT16[R_IO_H]) +#define RSCAN0TMID67HL (RSCAN0.TMID67.UINT8[R_IO_HL]) +#define RSCAN0TMID67HH (RSCAN0.TMID67.UINT8[R_IO_HH]) +#define RSCAN0TMPTR67 (RSCAN0.TMPTR67.UINT32) +#define RSCAN0TMPTR67L (RSCAN0.TMPTR67.UINT16[R_IO_L]) +#define RSCAN0TMPTR67LL (RSCAN0.TMPTR67.UINT8[R_IO_LL]) +#define RSCAN0TMPTR67LH (RSCAN0.TMPTR67.UINT8[R_IO_LH]) +#define RSCAN0TMPTR67H (RSCAN0.TMPTR67.UINT16[R_IO_H]) +#define RSCAN0TMPTR67HL (RSCAN0.TMPTR67.UINT8[R_IO_HL]) +#define RSCAN0TMPTR67HH (RSCAN0.TMPTR67.UINT8[R_IO_HH]) +#define RSCAN0TMDF067 (RSCAN0.TMDF067.UINT32) +#define RSCAN0TMDF067L (RSCAN0.TMDF067.UINT16[R_IO_L]) +#define RSCAN0TMDF067LL (RSCAN0.TMDF067.UINT8[R_IO_LL]) +#define RSCAN0TMDF067LH (RSCAN0.TMDF067.UINT8[R_IO_LH]) +#define RSCAN0TMDF067H (RSCAN0.TMDF067.UINT16[R_IO_H]) +#define RSCAN0TMDF067HL (RSCAN0.TMDF067.UINT8[R_IO_HL]) +#define RSCAN0TMDF067HH (RSCAN0.TMDF067.UINT8[R_IO_HH]) +#define RSCAN0TMDF167 (RSCAN0.TMDF167.UINT32) +#define RSCAN0TMDF167L (RSCAN0.TMDF167.UINT16[R_IO_L]) +#define RSCAN0TMDF167LL (RSCAN0.TMDF167.UINT8[R_IO_LL]) +#define RSCAN0TMDF167LH (RSCAN0.TMDF167.UINT8[R_IO_LH]) +#define RSCAN0TMDF167H (RSCAN0.TMDF167.UINT16[R_IO_H]) +#define RSCAN0TMDF167HL (RSCAN0.TMDF167.UINT8[R_IO_HL]) +#define RSCAN0TMDF167HH (RSCAN0.TMDF167.UINT8[R_IO_HH]) +#define RSCAN0TMID68 (RSCAN0.TMID68.UINT32) +#define RSCAN0TMID68L (RSCAN0.TMID68.UINT16[R_IO_L]) +#define RSCAN0TMID68LL (RSCAN0.TMID68.UINT8[R_IO_LL]) +#define RSCAN0TMID68LH (RSCAN0.TMID68.UINT8[R_IO_LH]) +#define RSCAN0TMID68H (RSCAN0.TMID68.UINT16[R_IO_H]) +#define RSCAN0TMID68HL (RSCAN0.TMID68.UINT8[R_IO_HL]) +#define RSCAN0TMID68HH (RSCAN0.TMID68.UINT8[R_IO_HH]) +#define RSCAN0TMPTR68 (RSCAN0.TMPTR68.UINT32) +#define RSCAN0TMPTR68L (RSCAN0.TMPTR68.UINT16[R_IO_L]) +#define RSCAN0TMPTR68LL (RSCAN0.TMPTR68.UINT8[R_IO_LL]) +#define RSCAN0TMPTR68LH (RSCAN0.TMPTR68.UINT8[R_IO_LH]) +#define RSCAN0TMPTR68H (RSCAN0.TMPTR68.UINT16[R_IO_H]) +#define RSCAN0TMPTR68HL (RSCAN0.TMPTR68.UINT8[R_IO_HL]) +#define RSCAN0TMPTR68HH (RSCAN0.TMPTR68.UINT8[R_IO_HH]) +#define RSCAN0TMDF068 (RSCAN0.TMDF068.UINT32) +#define RSCAN0TMDF068L (RSCAN0.TMDF068.UINT16[R_IO_L]) +#define RSCAN0TMDF068LL (RSCAN0.TMDF068.UINT8[R_IO_LL]) +#define RSCAN0TMDF068LH (RSCAN0.TMDF068.UINT8[R_IO_LH]) +#define RSCAN0TMDF068H (RSCAN0.TMDF068.UINT16[R_IO_H]) +#define RSCAN0TMDF068HL (RSCAN0.TMDF068.UINT8[R_IO_HL]) +#define RSCAN0TMDF068HH (RSCAN0.TMDF068.UINT8[R_IO_HH]) +#define RSCAN0TMDF168 (RSCAN0.TMDF168.UINT32) +#define RSCAN0TMDF168L (RSCAN0.TMDF168.UINT16[R_IO_L]) +#define RSCAN0TMDF168LL (RSCAN0.TMDF168.UINT8[R_IO_LL]) +#define RSCAN0TMDF168LH (RSCAN0.TMDF168.UINT8[R_IO_LH]) +#define RSCAN0TMDF168H (RSCAN0.TMDF168.UINT16[R_IO_H]) +#define RSCAN0TMDF168HL (RSCAN0.TMDF168.UINT8[R_IO_HL]) +#define RSCAN0TMDF168HH (RSCAN0.TMDF168.UINT8[R_IO_HH]) +#define RSCAN0TMID69 (RSCAN0.TMID69.UINT32) +#define RSCAN0TMID69L (RSCAN0.TMID69.UINT16[R_IO_L]) +#define RSCAN0TMID69LL (RSCAN0.TMID69.UINT8[R_IO_LL]) +#define RSCAN0TMID69LH (RSCAN0.TMID69.UINT8[R_IO_LH]) +#define RSCAN0TMID69H (RSCAN0.TMID69.UINT16[R_IO_H]) +#define RSCAN0TMID69HL (RSCAN0.TMID69.UINT8[R_IO_HL]) +#define RSCAN0TMID69HH (RSCAN0.TMID69.UINT8[R_IO_HH]) +#define RSCAN0TMPTR69 (RSCAN0.TMPTR69.UINT32) +#define RSCAN0TMPTR69L (RSCAN0.TMPTR69.UINT16[R_IO_L]) +#define RSCAN0TMPTR69LL (RSCAN0.TMPTR69.UINT8[R_IO_LL]) +#define RSCAN0TMPTR69LH (RSCAN0.TMPTR69.UINT8[R_IO_LH]) +#define RSCAN0TMPTR69H (RSCAN0.TMPTR69.UINT16[R_IO_H]) +#define RSCAN0TMPTR69HL (RSCAN0.TMPTR69.UINT8[R_IO_HL]) +#define RSCAN0TMPTR69HH (RSCAN0.TMPTR69.UINT8[R_IO_HH]) +#define RSCAN0TMDF069 (RSCAN0.TMDF069.UINT32) +#define RSCAN0TMDF069L (RSCAN0.TMDF069.UINT16[R_IO_L]) +#define RSCAN0TMDF069LL (RSCAN0.TMDF069.UINT8[R_IO_LL]) +#define RSCAN0TMDF069LH (RSCAN0.TMDF069.UINT8[R_IO_LH]) +#define RSCAN0TMDF069H (RSCAN0.TMDF069.UINT16[R_IO_H]) +#define RSCAN0TMDF069HL (RSCAN0.TMDF069.UINT8[R_IO_HL]) +#define RSCAN0TMDF069HH (RSCAN0.TMDF069.UINT8[R_IO_HH]) +#define RSCAN0TMDF169 (RSCAN0.TMDF169.UINT32) +#define RSCAN0TMDF169L (RSCAN0.TMDF169.UINT16[R_IO_L]) +#define RSCAN0TMDF169LL (RSCAN0.TMDF169.UINT8[R_IO_LL]) +#define RSCAN0TMDF169LH (RSCAN0.TMDF169.UINT8[R_IO_LH]) +#define RSCAN0TMDF169H (RSCAN0.TMDF169.UINT16[R_IO_H]) +#define RSCAN0TMDF169HL (RSCAN0.TMDF169.UINT8[R_IO_HL]) +#define RSCAN0TMDF169HH (RSCAN0.TMDF169.UINT8[R_IO_HH]) +#define RSCAN0TMID70 (RSCAN0.TMID70.UINT32) +#define RSCAN0TMID70L (RSCAN0.TMID70.UINT16[R_IO_L]) +#define RSCAN0TMID70LL (RSCAN0.TMID70.UINT8[R_IO_LL]) +#define RSCAN0TMID70LH (RSCAN0.TMID70.UINT8[R_IO_LH]) +#define RSCAN0TMID70H (RSCAN0.TMID70.UINT16[R_IO_H]) +#define RSCAN0TMID70HL (RSCAN0.TMID70.UINT8[R_IO_HL]) +#define RSCAN0TMID70HH (RSCAN0.TMID70.UINT8[R_IO_HH]) +#define RSCAN0TMPTR70 (RSCAN0.TMPTR70.UINT32) +#define RSCAN0TMPTR70L (RSCAN0.TMPTR70.UINT16[R_IO_L]) +#define RSCAN0TMPTR70LL (RSCAN0.TMPTR70.UINT8[R_IO_LL]) +#define RSCAN0TMPTR70LH (RSCAN0.TMPTR70.UINT8[R_IO_LH]) +#define RSCAN0TMPTR70H (RSCAN0.TMPTR70.UINT16[R_IO_H]) +#define RSCAN0TMPTR70HL (RSCAN0.TMPTR70.UINT8[R_IO_HL]) +#define RSCAN0TMPTR70HH (RSCAN0.TMPTR70.UINT8[R_IO_HH]) +#define RSCAN0TMDF070 (RSCAN0.TMDF070.UINT32) +#define RSCAN0TMDF070L (RSCAN0.TMDF070.UINT16[R_IO_L]) +#define RSCAN0TMDF070LL (RSCAN0.TMDF070.UINT8[R_IO_LL]) +#define RSCAN0TMDF070LH (RSCAN0.TMDF070.UINT8[R_IO_LH]) +#define RSCAN0TMDF070H (RSCAN0.TMDF070.UINT16[R_IO_H]) +#define RSCAN0TMDF070HL (RSCAN0.TMDF070.UINT8[R_IO_HL]) +#define RSCAN0TMDF070HH (RSCAN0.TMDF070.UINT8[R_IO_HH]) +#define RSCAN0TMDF170 (RSCAN0.TMDF170.UINT32) +#define RSCAN0TMDF170L (RSCAN0.TMDF170.UINT16[R_IO_L]) +#define RSCAN0TMDF170LL (RSCAN0.TMDF170.UINT8[R_IO_LL]) +#define RSCAN0TMDF170LH (RSCAN0.TMDF170.UINT8[R_IO_LH]) +#define RSCAN0TMDF170H (RSCAN0.TMDF170.UINT16[R_IO_H]) +#define RSCAN0TMDF170HL (RSCAN0.TMDF170.UINT8[R_IO_HL]) +#define RSCAN0TMDF170HH (RSCAN0.TMDF170.UINT8[R_IO_HH]) +#define RSCAN0TMID71 (RSCAN0.TMID71.UINT32) +#define RSCAN0TMID71L (RSCAN0.TMID71.UINT16[R_IO_L]) +#define RSCAN0TMID71LL (RSCAN0.TMID71.UINT8[R_IO_LL]) +#define RSCAN0TMID71LH (RSCAN0.TMID71.UINT8[R_IO_LH]) +#define RSCAN0TMID71H (RSCAN0.TMID71.UINT16[R_IO_H]) +#define RSCAN0TMID71HL (RSCAN0.TMID71.UINT8[R_IO_HL]) +#define RSCAN0TMID71HH (RSCAN0.TMID71.UINT8[R_IO_HH]) +#define RSCAN0TMPTR71 (RSCAN0.TMPTR71.UINT32) +#define RSCAN0TMPTR71L (RSCAN0.TMPTR71.UINT16[R_IO_L]) +#define RSCAN0TMPTR71LL (RSCAN0.TMPTR71.UINT8[R_IO_LL]) +#define RSCAN0TMPTR71LH (RSCAN0.TMPTR71.UINT8[R_IO_LH]) +#define RSCAN0TMPTR71H (RSCAN0.TMPTR71.UINT16[R_IO_H]) +#define RSCAN0TMPTR71HL (RSCAN0.TMPTR71.UINT8[R_IO_HL]) +#define RSCAN0TMPTR71HH (RSCAN0.TMPTR71.UINT8[R_IO_HH]) +#define RSCAN0TMDF071 (RSCAN0.TMDF071.UINT32) +#define RSCAN0TMDF071L (RSCAN0.TMDF071.UINT16[R_IO_L]) +#define RSCAN0TMDF071LL (RSCAN0.TMDF071.UINT8[R_IO_LL]) +#define RSCAN0TMDF071LH (RSCAN0.TMDF071.UINT8[R_IO_LH]) +#define RSCAN0TMDF071H (RSCAN0.TMDF071.UINT16[R_IO_H]) +#define RSCAN0TMDF071HL (RSCAN0.TMDF071.UINT8[R_IO_HL]) +#define RSCAN0TMDF071HH (RSCAN0.TMDF071.UINT8[R_IO_HH]) +#define RSCAN0TMDF171 (RSCAN0.TMDF171.UINT32) +#define RSCAN0TMDF171L (RSCAN0.TMDF171.UINT16[R_IO_L]) +#define RSCAN0TMDF171LL (RSCAN0.TMDF171.UINT8[R_IO_LL]) +#define RSCAN0TMDF171LH (RSCAN0.TMDF171.UINT8[R_IO_LH]) +#define RSCAN0TMDF171H (RSCAN0.TMDF171.UINT16[R_IO_H]) +#define RSCAN0TMDF171HL (RSCAN0.TMDF171.UINT8[R_IO_HL]) +#define RSCAN0TMDF171HH (RSCAN0.TMDF171.UINT8[R_IO_HH]) +#define RSCAN0TMID72 (RSCAN0.TMID72.UINT32) +#define RSCAN0TMID72L (RSCAN0.TMID72.UINT16[R_IO_L]) +#define RSCAN0TMID72LL (RSCAN0.TMID72.UINT8[R_IO_LL]) +#define RSCAN0TMID72LH (RSCAN0.TMID72.UINT8[R_IO_LH]) +#define RSCAN0TMID72H (RSCAN0.TMID72.UINT16[R_IO_H]) +#define RSCAN0TMID72HL (RSCAN0.TMID72.UINT8[R_IO_HL]) +#define RSCAN0TMID72HH (RSCAN0.TMID72.UINT8[R_IO_HH]) +#define RSCAN0TMPTR72 (RSCAN0.TMPTR72.UINT32) +#define RSCAN0TMPTR72L (RSCAN0.TMPTR72.UINT16[R_IO_L]) +#define RSCAN0TMPTR72LL (RSCAN0.TMPTR72.UINT8[R_IO_LL]) +#define RSCAN0TMPTR72LH (RSCAN0.TMPTR72.UINT8[R_IO_LH]) +#define RSCAN0TMPTR72H (RSCAN0.TMPTR72.UINT16[R_IO_H]) +#define RSCAN0TMPTR72HL (RSCAN0.TMPTR72.UINT8[R_IO_HL]) +#define RSCAN0TMPTR72HH (RSCAN0.TMPTR72.UINT8[R_IO_HH]) +#define RSCAN0TMDF072 (RSCAN0.TMDF072.UINT32) +#define RSCAN0TMDF072L (RSCAN0.TMDF072.UINT16[R_IO_L]) +#define RSCAN0TMDF072LL (RSCAN0.TMDF072.UINT8[R_IO_LL]) +#define RSCAN0TMDF072LH (RSCAN0.TMDF072.UINT8[R_IO_LH]) +#define RSCAN0TMDF072H (RSCAN0.TMDF072.UINT16[R_IO_H]) +#define RSCAN0TMDF072HL (RSCAN0.TMDF072.UINT8[R_IO_HL]) +#define RSCAN0TMDF072HH (RSCAN0.TMDF072.UINT8[R_IO_HH]) +#define RSCAN0TMDF172 (RSCAN0.TMDF172.UINT32) +#define RSCAN0TMDF172L (RSCAN0.TMDF172.UINT16[R_IO_L]) +#define RSCAN0TMDF172LL (RSCAN0.TMDF172.UINT8[R_IO_LL]) +#define RSCAN0TMDF172LH (RSCAN0.TMDF172.UINT8[R_IO_LH]) +#define RSCAN0TMDF172H (RSCAN0.TMDF172.UINT16[R_IO_H]) +#define RSCAN0TMDF172HL (RSCAN0.TMDF172.UINT8[R_IO_HL]) +#define RSCAN0TMDF172HH (RSCAN0.TMDF172.UINT8[R_IO_HH]) +#define RSCAN0TMID73 (RSCAN0.TMID73.UINT32) +#define RSCAN0TMID73L (RSCAN0.TMID73.UINT16[R_IO_L]) +#define RSCAN0TMID73LL (RSCAN0.TMID73.UINT8[R_IO_LL]) +#define RSCAN0TMID73LH (RSCAN0.TMID73.UINT8[R_IO_LH]) +#define RSCAN0TMID73H (RSCAN0.TMID73.UINT16[R_IO_H]) +#define RSCAN0TMID73HL (RSCAN0.TMID73.UINT8[R_IO_HL]) +#define RSCAN0TMID73HH (RSCAN0.TMID73.UINT8[R_IO_HH]) +#define RSCAN0TMPTR73 (RSCAN0.TMPTR73.UINT32) +#define RSCAN0TMPTR73L (RSCAN0.TMPTR73.UINT16[R_IO_L]) +#define RSCAN0TMPTR73LL (RSCAN0.TMPTR73.UINT8[R_IO_LL]) +#define RSCAN0TMPTR73LH (RSCAN0.TMPTR73.UINT8[R_IO_LH]) +#define RSCAN0TMPTR73H (RSCAN0.TMPTR73.UINT16[R_IO_H]) +#define RSCAN0TMPTR73HL (RSCAN0.TMPTR73.UINT8[R_IO_HL]) +#define RSCAN0TMPTR73HH (RSCAN0.TMPTR73.UINT8[R_IO_HH]) +#define RSCAN0TMDF073 (RSCAN0.TMDF073.UINT32) +#define RSCAN0TMDF073L (RSCAN0.TMDF073.UINT16[R_IO_L]) +#define RSCAN0TMDF073LL (RSCAN0.TMDF073.UINT8[R_IO_LL]) +#define RSCAN0TMDF073LH (RSCAN0.TMDF073.UINT8[R_IO_LH]) +#define RSCAN0TMDF073H (RSCAN0.TMDF073.UINT16[R_IO_H]) +#define RSCAN0TMDF073HL (RSCAN0.TMDF073.UINT8[R_IO_HL]) +#define RSCAN0TMDF073HH (RSCAN0.TMDF073.UINT8[R_IO_HH]) +#define RSCAN0TMDF173 (RSCAN0.TMDF173.UINT32) +#define RSCAN0TMDF173L (RSCAN0.TMDF173.UINT16[R_IO_L]) +#define RSCAN0TMDF173LL (RSCAN0.TMDF173.UINT8[R_IO_LL]) +#define RSCAN0TMDF173LH (RSCAN0.TMDF173.UINT8[R_IO_LH]) +#define RSCAN0TMDF173H (RSCAN0.TMDF173.UINT16[R_IO_H]) +#define RSCAN0TMDF173HL (RSCAN0.TMDF173.UINT8[R_IO_HL]) +#define RSCAN0TMDF173HH (RSCAN0.TMDF173.UINT8[R_IO_HH]) +#define RSCAN0TMID74 (RSCAN0.TMID74.UINT32) +#define RSCAN0TMID74L (RSCAN0.TMID74.UINT16[R_IO_L]) +#define RSCAN0TMID74LL (RSCAN0.TMID74.UINT8[R_IO_LL]) +#define RSCAN0TMID74LH (RSCAN0.TMID74.UINT8[R_IO_LH]) +#define RSCAN0TMID74H (RSCAN0.TMID74.UINT16[R_IO_H]) +#define RSCAN0TMID74HL (RSCAN0.TMID74.UINT8[R_IO_HL]) +#define RSCAN0TMID74HH (RSCAN0.TMID74.UINT8[R_IO_HH]) +#define RSCAN0TMPTR74 (RSCAN0.TMPTR74.UINT32) +#define RSCAN0TMPTR74L (RSCAN0.TMPTR74.UINT16[R_IO_L]) +#define RSCAN0TMPTR74LL (RSCAN0.TMPTR74.UINT8[R_IO_LL]) +#define RSCAN0TMPTR74LH (RSCAN0.TMPTR74.UINT8[R_IO_LH]) +#define RSCAN0TMPTR74H (RSCAN0.TMPTR74.UINT16[R_IO_H]) +#define RSCAN0TMPTR74HL (RSCAN0.TMPTR74.UINT8[R_IO_HL]) +#define RSCAN0TMPTR74HH (RSCAN0.TMPTR74.UINT8[R_IO_HH]) +#define RSCAN0TMDF074 (RSCAN0.TMDF074.UINT32) +#define RSCAN0TMDF074L (RSCAN0.TMDF074.UINT16[R_IO_L]) +#define RSCAN0TMDF074LL (RSCAN0.TMDF074.UINT8[R_IO_LL]) +#define RSCAN0TMDF074LH (RSCAN0.TMDF074.UINT8[R_IO_LH]) +#define RSCAN0TMDF074H (RSCAN0.TMDF074.UINT16[R_IO_H]) +#define RSCAN0TMDF074HL (RSCAN0.TMDF074.UINT8[R_IO_HL]) +#define RSCAN0TMDF074HH (RSCAN0.TMDF074.UINT8[R_IO_HH]) +#define RSCAN0TMDF174 (RSCAN0.TMDF174.UINT32) +#define RSCAN0TMDF174L (RSCAN0.TMDF174.UINT16[R_IO_L]) +#define RSCAN0TMDF174LL (RSCAN0.TMDF174.UINT8[R_IO_LL]) +#define RSCAN0TMDF174LH (RSCAN0.TMDF174.UINT8[R_IO_LH]) +#define RSCAN0TMDF174H (RSCAN0.TMDF174.UINT16[R_IO_H]) +#define RSCAN0TMDF174HL (RSCAN0.TMDF174.UINT8[R_IO_HL]) +#define RSCAN0TMDF174HH (RSCAN0.TMDF174.UINT8[R_IO_HH]) +#define RSCAN0TMID75 (RSCAN0.TMID75.UINT32) +#define RSCAN0TMID75L (RSCAN0.TMID75.UINT16[R_IO_L]) +#define RSCAN0TMID75LL (RSCAN0.TMID75.UINT8[R_IO_LL]) +#define RSCAN0TMID75LH (RSCAN0.TMID75.UINT8[R_IO_LH]) +#define RSCAN0TMID75H (RSCAN0.TMID75.UINT16[R_IO_H]) +#define RSCAN0TMID75HL (RSCAN0.TMID75.UINT8[R_IO_HL]) +#define RSCAN0TMID75HH (RSCAN0.TMID75.UINT8[R_IO_HH]) +#define RSCAN0TMPTR75 (RSCAN0.TMPTR75.UINT32) +#define RSCAN0TMPTR75L (RSCAN0.TMPTR75.UINT16[R_IO_L]) +#define RSCAN0TMPTR75LL (RSCAN0.TMPTR75.UINT8[R_IO_LL]) +#define RSCAN0TMPTR75LH (RSCAN0.TMPTR75.UINT8[R_IO_LH]) +#define RSCAN0TMPTR75H (RSCAN0.TMPTR75.UINT16[R_IO_H]) +#define RSCAN0TMPTR75HL (RSCAN0.TMPTR75.UINT8[R_IO_HL]) +#define RSCAN0TMPTR75HH (RSCAN0.TMPTR75.UINT8[R_IO_HH]) +#define RSCAN0TMDF075 (RSCAN0.TMDF075.UINT32) +#define RSCAN0TMDF075L (RSCAN0.TMDF075.UINT16[R_IO_L]) +#define RSCAN0TMDF075LL (RSCAN0.TMDF075.UINT8[R_IO_LL]) +#define RSCAN0TMDF075LH (RSCAN0.TMDF075.UINT8[R_IO_LH]) +#define RSCAN0TMDF075H (RSCAN0.TMDF075.UINT16[R_IO_H]) +#define RSCAN0TMDF075HL (RSCAN0.TMDF075.UINT8[R_IO_HL]) +#define RSCAN0TMDF075HH (RSCAN0.TMDF075.UINT8[R_IO_HH]) +#define RSCAN0TMDF175 (RSCAN0.TMDF175.UINT32) +#define RSCAN0TMDF175L (RSCAN0.TMDF175.UINT16[R_IO_L]) +#define RSCAN0TMDF175LL (RSCAN0.TMDF175.UINT8[R_IO_LL]) +#define RSCAN0TMDF175LH (RSCAN0.TMDF175.UINT8[R_IO_LH]) +#define RSCAN0TMDF175H (RSCAN0.TMDF175.UINT16[R_IO_H]) +#define RSCAN0TMDF175HL (RSCAN0.TMDF175.UINT8[R_IO_HL]) +#define RSCAN0TMDF175HH (RSCAN0.TMDF175.UINT8[R_IO_HH]) +#define RSCAN0TMID76 (RSCAN0.TMID76.UINT32) +#define RSCAN0TMID76L (RSCAN0.TMID76.UINT16[R_IO_L]) +#define RSCAN0TMID76LL (RSCAN0.TMID76.UINT8[R_IO_LL]) +#define RSCAN0TMID76LH (RSCAN0.TMID76.UINT8[R_IO_LH]) +#define RSCAN0TMID76H (RSCAN0.TMID76.UINT16[R_IO_H]) +#define RSCAN0TMID76HL (RSCAN0.TMID76.UINT8[R_IO_HL]) +#define RSCAN0TMID76HH (RSCAN0.TMID76.UINT8[R_IO_HH]) +#define RSCAN0TMPTR76 (RSCAN0.TMPTR76.UINT32) +#define RSCAN0TMPTR76L (RSCAN0.TMPTR76.UINT16[R_IO_L]) +#define RSCAN0TMPTR76LL (RSCAN0.TMPTR76.UINT8[R_IO_LL]) +#define RSCAN0TMPTR76LH (RSCAN0.TMPTR76.UINT8[R_IO_LH]) +#define RSCAN0TMPTR76H (RSCAN0.TMPTR76.UINT16[R_IO_H]) +#define RSCAN0TMPTR76HL (RSCAN0.TMPTR76.UINT8[R_IO_HL]) +#define RSCAN0TMPTR76HH (RSCAN0.TMPTR76.UINT8[R_IO_HH]) +#define RSCAN0TMDF076 (RSCAN0.TMDF076.UINT32) +#define RSCAN0TMDF076L (RSCAN0.TMDF076.UINT16[R_IO_L]) +#define RSCAN0TMDF076LL (RSCAN0.TMDF076.UINT8[R_IO_LL]) +#define RSCAN0TMDF076LH (RSCAN0.TMDF076.UINT8[R_IO_LH]) +#define RSCAN0TMDF076H (RSCAN0.TMDF076.UINT16[R_IO_H]) +#define RSCAN0TMDF076HL (RSCAN0.TMDF076.UINT8[R_IO_HL]) +#define RSCAN0TMDF076HH (RSCAN0.TMDF076.UINT8[R_IO_HH]) +#define RSCAN0TMDF176 (RSCAN0.TMDF176.UINT32) +#define RSCAN0TMDF176L (RSCAN0.TMDF176.UINT16[R_IO_L]) +#define RSCAN0TMDF176LL (RSCAN0.TMDF176.UINT8[R_IO_LL]) +#define RSCAN0TMDF176LH (RSCAN0.TMDF176.UINT8[R_IO_LH]) +#define RSCAN0TMDF176H (RSCAN0.TMDF176.UINT16[R_IO_H]) +#define RSCAN0TMDF176HL (RSCAN0.TMDF176.UINT8[R_IO_HL]) +#define RSCAN0TMDF176HH (RSCAN0.TMDF176.UINT8[R_IO_HH]) +#define RSCAN0TMID77 (RSCAN0.TMID77.UINT32) +#define RSCAN0TMID77L (RSCAN0.TMID77.UINT16[R_IO_L]) +#define RSCAN0TMID77LL (RSCAN0.TMID77.UINT8[R_IO_LL]) +#define RSCAN0TMID77LH (RSCAN0.TMID77.UINT8[R_IO_LH]) +#define RSCAN0TMID77H (RSCAN0.TMID77.UINT16[R_IO_H]) +#define RSCAN0TMID77HL (RSCAN0.TMID77.UINT8[R_IO_HL]) +#define RSCAN0TMID77HH (RSCAN0.TMID77.UINT8[R_IO_HH]) +#define RSCAN0TMPTR77 (RSCAN0.TMPTR77.UINT32) +#define RSCAN0TMPTR77L (RSCAN0.TMPTR77.UINT16[R_IO_L]) +#define RSCAN0TMPTR77LL (RSCAN0.TMPTR77.UINT8[R_IO_LL]) +#define RSCAN0TMPTR77LH (RSCAN0.TMPTR77.UINT8[R_IO_LH]) +#define RSCAN0TMPTR77H (RSCAN0.TMPTR77.UINT16[R_IO_H]) +#define RSCAN0TMPTR77HL (RSCAN0.TMPTR77.UINT8[R_IO_HL]) +#define RSCAN0TMPTR77HH (RSCAN0.TMPTR77.UINT8[R_IO_HH]) +#define RSCAN0TMDF077 (RSCAN0.TMDF077.UINT32) +#define RSCAN0TMDF077L (RSCAN0.TMDF077.UINT16[R_IO_L]) +#define RSCAN0TMDF077LL (RSCAN0.TMDF077.UINT8[R_IO_LL]) +#define RSCAN0TMDF077LH (RSCAN0.TMDF077.UINT8[R_IO_LH]) +#define RSCAN0TMDF077H (RSCAN0.TMDF077.UINT16[R_IO_H]) +#define RSCAN0TMDF077HL (RSCAN0.TMDF077.UINT8[R_IO_HL]) +#define RSCAN0TMDF077HH (RSCAN0.TMDF077.UINT8[R_IO_HH]) +#define RSCAN0TMDF177 (RSCAN0.TMDF177.UINT32) +#define RSCAN0TMDF177L (RSCAN0.TMDF177.UINT16[R_IO_L]) +#define RSCAN0TMDF177LL (RSCAN0.TMDF177.UINT8[R_IO_LL]) +#define RSCAN0TMDF177LH (RSCAN0.TMDF177.UINT8[R_IO_LH]) +#define RSCAN0TMDF177H (RSCAN0.TMDF177.UINT16[R_IO_H]) +#define RSCAN0TMDF177HL (RSCAN0.TMDF177.UINT8[R_IO_HL]) +#define RSCAN0TMDF177HH (RSCAN0.TMDF177.UINT8[R_IO_HH]) +#define RSCAN0TMID78 (RSCAN0.TMID78.UINT32) +#define RSCAN0TMID78L (RSCAN0.TMID78.UINT16[R_IO_L]) +#define RSCAN0TMID78LL (RSCAN0.TMID78.UINT8[R_IO_LL]) +#define RSCAN0TMID78LH (RSCAN0.TMID78.UINT8[R_IO_LH]) +#define RSCAN0TMID78H (RSCAN0.TMID78.UINT16[R_IO_H]) +#define RSCAN0TMID78HL (RSCAN0.TMID78.UINT8[R_IO_HL]) +#define RSCAN0TMID78HH (RSCAN0.TMID78.UINT8[R_IO_HH]) +#define RSCAN0TMPTR78 (RSCAN0.TMPTR78.UINT32) +#define RSCAN0TMPTR78L (RSCAN0.TMPTR78.UINT16[R_IO_L]) +#define RSCAN0TMPTR78LL (RSCAN0.TMPTR78.UINT8[R_IO_LL]) +#define RSCAN0TMPTR78LH (RSCAN0.TMPTR78.UINT8[R_IO_LH]) +#define RSCAN0TMPTR78H (RSCAN0.TMPTR78.UINT16[R_IO_H]) +#define RSCAN0TMPTR78HL (RSCAN0.TMPTR78.UINT8[R_IO_HL]) +#define RSCAN0TMPTR78HH (RSCAN0.TMPTR78.UINT8[R_IO_HH]) +#define RSCAN0TMDF078 (RSCAN0.TMDF078.UINT32) +#define RSCAN0TMDF078L (RSCAN0.TMDF078.UINT16[R_IO_L]) +#define RSCAN0TMDF078LL (RSCAN0.TMDF078.UINT8[R_IO_LL]) +#define RSCAN0TMDF078LH (RSCAN0.TMDF078.UINT8[R_IO_LH]) +#define RSCAN0TMDF078H (RSCAN0.TMDF078.UINT16[R_IO_H]) +#define RSCAN0TMDF078HL (RSCAN0.TMDF078.UINT8[R_IO_HL]) +#define RSCAN0TMDF078HH (RSCAN0.TMDF078.UINT8[R_IO_HH]) +#define RSCAN0TMDF178 (RSCAN0.TMDF178.UINT32) +#define RSCAN0TMDF178L (RSCAN0.TMDF178.UINT16[R_IO_L]) +#define RSCAN0TMDF178LL (RSCAN0.TMDF178.UINT8[R_IO_LL]) +#define RSCAN0TMDF178LH (RSCAN0.TMDF178.UINT8[R_IO_LH]) +#define RSCAN0TMDF178H (RSCAN0.TMDF178.UINT16[R_IO_H]) +#define RSCAN0TMDF178HL (RSCAN0.TMDF178.UINT8[R_IO_HL]) +#define RSCAN0TMDF178HH (RSCAN0.TMDF178.UINT8[R_IO_HH]) +#define RSCAN0TMID79 (RSCAN0.TMID79.UINT32) +#define RSCAN0TMID79L (RSCAN0.TMID79.UINT16[R_IO_L]) +#define RSCAN0TMID79LL (RSCAN0.TMID79.UINT8[R_IO_LL]) +#define RSCAN0TMID79LH (RSCAN0.TMID79.UINT8[R_IO_LH]) +#define RSCAN0TMID79H (RSCAN0.TMID79.UINT16[R_IO_H]) +#define RSCAN0TMID79HL (RSCAN0.TMID79.UINT8[R_IO_HL]) +#define RSCAN0TMID79HH (RSCAN0.TMID79.UINT8[R_IO_HH]) +#define RSCAN0TMPTR79 (RSCAN0.TMPTR79.UINT32) +#define RSCAN0TMPTR79L (RSCAN0.TMPTR79.UINT16[R_IO_L]) +#define RSCAN0TMPTR79LL (RSCAN0.TMPTR79.UINT8[R_IO_LL]) +#define RSCAN0TMPTR79LH (RSCAN0.TMPTR79.UINT8[R_IO_LH]) +#define RSCAN0TMPTR79H (RSCAN0.TMPTR79.UINT16[R_IO_H]) +#define RSCAN0TMPTR79HL (RSCAN0.TMPTR79.UINT8[R_IO_HL]) +#define RSCAN0TMPTR79HH (RSCAN0.TMPTR79.UINT8[R_IO_HH]) +#define RSCAN0TMDF079 (RSCAN0.TMDF079.UINT32) +#define RSCAN0TMDF079L (RSCAN0.TMDF079.UINT16[R_IO_L]) +#define RSCAN0TMDF079LL (RSCAN0.TMDF079.UINT8[R_IO_LL]) +#define RSCAN0TMDF079LH (RSCAN0.TMDF079.UINT8[R_IO_LH]) +#define RSCAN0TMDF079H (RSCAN0.TMDF079.UINT16[R_IO_H]) +#define RSCAN0TMDF079HL (RSCAN0.TMDF079.UINT8[R_IO_HL]) +#define RSCAN0TMDF079HH (RSCAN0.TMDF079.UINT8[R_IO_HH]) +#define RSCAN0TMDF179 (RSCAN0.TMDF179.UINT32) +#define RSCAN0TMDF179L (RSCAN0.TMDF179.UINT16[R_IO_L]) +#define RSCAN0TMDF179LL (RSCAN0.TMDF179.UINT8[R_IO_LL]) +#define RSCAN0TMDF179LH (RSCAN0.TMDF179.UINT8[R_IO_LH]) +#define RSCAN0TMDF179H (RSCAN0.TMDF179.UINT16[R_IO_H]) +#define RSCAN0TMDF179HL (RSCAN0.TMDF179.UINT8[R_IO_HL]) +#define RSCAN0TMDF179HH (RSCAN0.TMDF179.UINT8[R_IO_HH]) +#define RSCAN0THLACC0 (RSCAN0.THLACC0.UINT32) +#define RSCAN0THLACC0L (RSCAN0.THLACC0.UINT16[R_IO_L]) +#define RSCAN0THLACC0LL (RSCAN0.THLACC0.UINT8[R_IO_LL]) +#define RSCAN0THLACC0LH (RSCAN0.THLACC0.UINT8[R_IO_LH]) +#define RSCAN0THLACC0H (RSCAN0.THLACC0.UINT16[R_IO_H]) +#define RSCAN0THLACC0HL (RSCAN0.THLACC0.UINT8[R_IO_HL]) +#define RSCAN0THLACC0HH (RSCAN0.THLACC0.UINT8[R_IO_HH]) +#define RSCAN0THLACC1 (RSCAN0.THLACC1.UINT32) +#define RSCAN0THLACC1L (RSCAN0.THLACC1.UINT16[R_IO_L]) +#define RSCAN0THLACC1LL (RSCAN0.THLACC1.UINT8[R_IO_LL]) +#define RSCAN0THLACC1LH (RSCAN0.THLACC1.UINT8[R_IO_LH]) +#define RSCAN0THLACC1H (RSCAN0.THLACC1.UINT16[R_IO_H]) +#define RSCAN0THLACC1HL (RSCAN0.THLACC1.UINT8[R_IO_HL]) +#define RSCAN0THLACC1HH (RSCAN0.THLACC1.UINT8[R_IO_HH]) +#define RSCAN0THLACC2 (RSCAN0.THLACC2.UINT32) +#define RSCAN0THLACC2L (RSCAN0.THLACC2.UINT16[R_IO_L]) +#define RSCAN0THLACC2LL (RSCAN0.THLACC2.UINT8[R_IO_LL]) +#define RSCAN0THLACC2LH (RSCAN0.THLACC2.UINT8[R_IO_LH]) +#define RSCAN0THLACC2H (RSCAN0.THLACC2.UINT16[R_IO_H]) +#define RSCAN0THLACC2HL (RSCAN0.THLACC2.UINT8[R_IO_HL]) +#define RSCAN0THLACC2HH (RSCAN0.THLACC2.UINT8[R_IO_HH]) +#define RSCAN0THLACC3 (RSCAN0.THLACC3.UINT32) +#define RSCAN0THLACC3L (RSCAN0.THLACC3.UINT16[R_IO_L]) +#define RSCAN0THLACC3LL (RSCAN0.THLACC3.UINT8[R_IO_LL]) +#define RSCAN0THLACC3LH (RSCAN0.THLACC3.UINT8[R_IO_LH]) +#define RSCAN0THLACC3H (RSCAN0.THLACC3.UINT16[R_IO_H]) +#define RSCAN0THLACC3HL (RSCAN0.THLACC3.UINT8[R_IO_HL]) +#define RSCAN0THLACC3HH (RSCAN0.THLACC3.UINT8[R_IO_HH]) +#define RSCAN0THLACC4 (RSCAN0.THLACC4.UINT32) +#define RSCAN0THLACC4L (RSCAN0.THLACC4.UINT16[R_IO_L]) +#define RSCAN0THLACC4LL (RSCAN0.THLACC4.UINT8[R_IO_LL]) +#define RSCAN0THLACC4LH (RSCAN0.THLACC4.UINT8[R_IO_LH]) +#define RSCAN0THLACC4H (RSCAN0.THLACC4.UINT16[R_IO_H]) +#define RSCAN0THLACC4HL (RSCAN0.THLACC4.UINT8[R_IO_HL]) +#define RSCAN0THLACC4HH (RSCAN0.THLACC4.UINT8[R_IO_HH]) + +#define RSCAN0_GAFLCFG0_COUNT (2) +#define RSCAN0_RMND0_COUNT (3) +#define RSCAN0_RFCC0_COUNT (8) +#define RSCAN0_RFSTS0_COUNT (8) +#define RSCAN0_RFPCTR0_COUNT (8) +#define RSCAN0_CFCC0_COUNT (15) +#define RSCAN0_CFSTS0_COUNT (15) +#define RSCAN0_CFPCTR0_COUNT (15) +#define RSCAN0_TMC0_COUNT (80) +#define RSCAN0_TMSTS0_COUNT (80) +#define RSCAN0_TMTRSTS0_COUNT (3) +#define RSCAN0_TMTARSTS0_COUNT (3) +#define RSCAN0_TMTCSTS0_COUNT (3) +#define RSCAN0_TMTASTS0_COUNT (3) +#define RSCAN0_TMIEC0_COUNT (3) +#define RSCAN0_TXQCC0_COUNT (5) +#define RSCAN0_TXQSTS0_COUNT (5) +#define RSCAN0_TXQPCTR0_COUNT (5) +#define RSCAN0_THLCC0_COUNT (5) +#define RSCAN0_THLSTS0_COUNT (5) +#define RSCAN0_THLPCTR0_COUNT (5) +#define RSCAN0_GTINTSTS0_COUNT (2) +#define RSCAN0_THLACC0_COUNT (5) + + +typedef struct st_rscan0 +{ + /* RSCAN0 */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C0CFG; /* C0CFG */ + union iodefine_reg32_t C0CTR; /* C0CTR */ + union iodefine_reg32_t C0STS; /* C0STS */ + union iodefine_reg32_t C0ERFL; /* C0ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C1CFG; /* C1CFG */ + union iodefine_reg32_t C1CTR; /* C1CTR */ + union iodefine_reg32_t C1STS; /* C1STS */ + union iodefine_reg32_t C1ERFL; /* C1ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C2CFG; /* C2CFG */ + union iodefine_reg32_t C2CTR; /* C2CTR */ + union iodefine_reg32_t C2STS; /* C2STS */ + union iodefine_reg32_t C2ERFL; /* C2ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C3CFG; /* C3CFG */ + union iodefine_reg32_t C3CTR; /* C3CTR */ + union iodefine_reg32_t C3STS; /* C3STS */ + union iodefine_reg32_t C3ERFL; /* C3ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C4CFG; /* C4CFG */ + union iodefine_reg32_t C4CTR; /* C4CTR */ + union iodefine_reg32_t C4STS; /* C4STS */ + union iodefine_reg32_t C4ERFL; /* C4ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + + volatile uint8_t dummy159[52]; /* */ + union iodefine_reg32_t GCFG; /* GCFG */ + union iodefine_reg32_t GCTR; /* GCTR */ + union iodefine_reg32_t GSTS; /* GSTS */ + union iodefine_reg32_t GERFL; /* GERFL */ + union iodefine_reg32_16_t GTSC; /* GTSC */ + union iodefine_reg32_t GAFLECTR; /* GAFLECTR */ + +/* #define RSCAN0_GAFLCFG0_COUNT (2) */ + union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */ + union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */ + union iodefine_reg32_t RMNB; /* RMNB */ + +/* #define RSCAN0_RMND0_COUNT (3) */ + union iodefine_reg32_t RMND0; /* RMND0 */ + union iodefine_reg32_t RMND1; /* RMND1 */ + union iodefine_reg32_t RMND2; /* RMND2 */ + + volatile uint8_t dummy160[4]; /* */ + +/* #define RSCAN0_RFCC0_COUNT (8) */ + union iodefine_reg32_t RFCC0; /* RFCC0 */ + union iodefine_reg32_t RFCC1; /* RFCC1 */ + union iodefine_reg32_t RFCC2; /* RFCC2 */ + union iodefine_reg32_t RFCC3; /* RFCC3 */ + union iodefine_reg32_t RFCC4; /* RFCC4 */ + union iodefine_reg32_t RFCC5; /* RFCC5 */ + union iodefine_reg32_t RFCC6; /* RFCC6 */ + union iodefine_reg32_t RFCC7; /* RFCC7 */ + +/* #define RSCAN0_RFSTS0_COUNT (8) */ + union iodefine_reg32_t RFSTS0; /* RFSTS0 */ + union iodefine_reg32_t RFSTS1; /* RFSTS1 */ + union iodefine_reg32_t RFSTS2; /* RFSTS2 */ + union iodefine_reg32_t RFSTS3; /* RFSTS3 */ + union iodefine_reg32_t RFSTS4; /* RFSTS4 */ + union iodefine_reg32_t RFSTS5; /* RFSTS5 */ + union iodefine_reg32_t RFSTS6; /* RFSTS6 */ + union iodefine_reg32_t RFSTS7; /* RFSTS7 */ + +/* #define RSCAN0_RFPCTR0_COUNT (8) */ + union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */ + union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */ + union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */ + union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */ + union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */ + union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */ + union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */ + union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */ + +/* #define RSCAN0_CFCC0_COUNT (15) */ + union iodefine_reg32_t CFCC0; /* CFCC0 */ + union iodefine_reg32_t CFCC1; /* CFCC1 */ + union iodefine_reg32_t CFCC2; /* CFCC2 */ + union iodefine_reg32_t CFCC3; /* CFCC3 */ + union iodefine_reg32_t CFCC4; /* CFCC4 */ + union iodefine_reg32_t CFCC5; /* CFCC5 */ + union iodefine_reg32_t CFCC6; /* CFCC6 */ + union iodefine_reg32_t CFCC7; /* CFCC7 */ + union iodefine_reg32_t CFCC8; /* CFCC8 */ + union iodefine_reg32_t CFCC9; /* CFCC9 */ + union iodefine_reg32_t CFCC10; /* CFCC10 */ + union iodefine_reg32_t CFCC11; /* CFCC11 */ + union iodefine_reg32_t CFCC12; /* CFCC12 */ + union iodefine_reg32_t CFCC13; /* CFCC13 */ + union iodefine_reg32_t CFCC14; /* CFCC14 */ + + volatile uint8_t dummy161[36]; /* */ + +/* #define RSCAN0_CFSTS0_COUNT (15) */ + union iodefine_reg32_t CFSTS0; /* CFSTS0 */ + union iodefine_reg32_t CFSTS1; /* CFSTS1 */ + union iodefine_reg32_t CFSTS2; /* CFSTS2 */ + union iodefine_reg32_t CFSTS3; /* CFSTS3 */ + union iodefine_reg32_t CFSTS4; /* CFSTS4 */ + union iodefine_reg32_t CFSTS5; /* CFSTS5 */ + union iodefine_reg32_t CFSTS6; /* CFSTS6 */ + union iodefine_reg32_t CFSTS7; /* CFSTS7 */ + union iodefine_reg32_t CFSTS8; /* CFSTS8 */ + union iodefine_reg32_t CFSTS9; /* CFSTS9 */ + union iodefine_reg32_t CFSTS10; /* CFSTS10 */ + union iodefine_reg32_t CFSTS11; /* CFSTS11 */ + union iodefine_reg32_t CFSTS12; /* CFSTS12 */ + union iodefine_reg32_t CFSTS13; /* CFSTS13 */ + union iodefine_reg32_t CFSTS14; /* CFSTS14 */ + + volatile uint8_t dummy162[36]; /* */ + +/* #define RSCAN0_CFPCTR0_COUNT (15) */ + union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */ + union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */ + union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */ + union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */ + union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */ + union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */ + union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */ + union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */ + union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */ + union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */ + union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */ + union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */ + union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */ + union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */ + union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */ + + volatile uint8_t dummy163[36]; /* */ + union iodefine_reg32_t FESTS; /* FESTS */ + union iodefine_reg32_t FFSTS; /* FFSTS */ + union iodefine_reg32_t FMSTS; /* FMSTS */ + union iodefine_reg32_t RFISTS; /* RFISTS */ + union iodefine_reg32_t CFRISTS; /* CFRISTS */ + union iodefine_reg32_t CFTISTS; /* CFTISTS */ + + +/* #define RSCAN0_TMC0_COUNT (80) */ + volatile uint8_t TMC0; /* TMC0 */ + volatile uint8_t TMC1; /* TMC1 */ + volatile uint8_t TMC2; /* TMC2 */ + volatile uint8_t TMC3; /* TMC3 */ + volatile uint8_t TMC4; /* TMC4 */ + volatile uint8_t TMC5; /* TMC5 */ + volatile uint8_t TMC6; /* TMC6 */ + volatile uint8_t TMC7; /* TMC7 */ + volatile uint8_t TMC8; /* TMC8 */ + volatile uint8_t TMC9; /* TMC9 */ + volatile uint8_t TMC10; /* TMC10 */ + volatile uint8_t TMC11; /* TMC11 */ + volatile uint8_t TMC12; /* TMC12 */ + volatile uint8_t TMC13; /* TMC13 */ + volatile uint8_t TMC14; /* TMC14 */ + volatile uint8_t TMC15; /* TMC15 */ + volatile uint8_t TMC16; /* TMC16 */ + volatile uint8_t TMC17; /* TMC17 */ + volatile uint8_t TMC18; /* TMC18 */ + volatile uint8_t TMC19; /* TMC19 */ + volatile uint8_t TMC20; /* TMC20 */ + volatile uint8_t TMC21; /* TMC21 */ + volatile uint8_t TMC22; /* TMC22 */ + volatile uint8_t TMC23; /* TMC23 */ + volatile uint8_t TMC24; /* TMC24 */ + volatile uint8_t TMC25; /* TMC25 */ + volatile uint8_t TMC26; /* TMC26 */ + volatile uint8_t TMC27; /* TMC27 */ + volatile uint8_t TMC28; /* TMC28 */ + volatile uint8_t TMC29; /* TMC29 */ + volatile uint8_t TMC30; /* TMC30 */ + volatile uint8_t TMC31; /* TMC31 */ + volatile uint8_t TMC32; /* TMC32 */ + volatile uint8_t TMC33; /* TMC33 */ + volatile uint8_t TMC34; /* TMC34 */ + volatile uint8_t TMC35; /* TMC35 */ + volatile uint8_t TMC36; /* TMC36 */ + volatile uint8_t TMC37; /* TMC37 */ + volatile uint8_t TMC38; /* TMC38 */ + volatile uint8_t TMC39; /* TMC39 */ + volatile uint8_t TMC40; /* TMC40 */ + volatile uint8_t TMC41; /* TMC41 */ + volatile uint8_t TMC42; /* TMC42 */ + volatile uint8_t TMC43; /* TMC43 */ + volatile uint8_t TMC44; /* TMC44 */ + volatile uint8_t TMC45; /* TMC45 */ + volatile uint8_t TMC46; /* TMC46 */ + volatile uint8_t TMC47; /* TMC47 */ + volatile uint8_t TMC48; /* TMC48 */ + volatile uint8_t TMC49; /* TMC49 */ + volatile uint8_t TMC50; /* TMC50 */ + volatile uint8_t TMC51; /* TMC51 */ + volatile uint8_t TMC52; /* TMC52 */ + volatile uint8_t TMC53; /* TMC53 */ + volatile uint8_t TMC54; /* TMC54 */ + volatile uint8_t TMC55; /* TMC55 */ + volatile uint8_t TMC56; /* TMC56 */ + volatile uint8_t TMC57; /* TMC57 */ + volatile uint8_t TMC58; /* TMC58 */ + volatile uint8_t TMC59; /* TMC59 */ + volatile uint8_t TMC60; /* TMC60 */ + volatile uint8_t TMC61; /* TMC61 */ + volatile uint8_t TMC62; /* TMC62 */ + volatile uint8_t TMC63; /* TMC63 */ + volatile uint8_t TMC64; /* TMC64 */ + volatile uint8_t TMC65; /* TMC65 */ + volatile uint8_t TMC66; /* TMC66 */ + volatile uint8_t TMC67; /* TMC67 */ + volatile uint8_t TMC68; /* TMC68 */ + volatile uint8_t TMC69; /* TMC69 */ + volatile uint8_t TMC70; /* TMC70 */ + volatile uint8_t TMC71; /* TMC71 */ + volatile uint8_t TMC72; /* TMC72 */ + volatile uint8_t TMC73; /* TMC73 */ + volatile uint8_t TMC74; /* TMC74 */ + volatile uint8_t TMC75; /* TMC75 */ + volatile uint8_t TMC76; /* TMC76 */ + volatile uint8_t TMC77; /* TMC77 */ + volatile uint8_t TMC78; /* TMC78 */ + volatile uint8_t TMC79; /* TMC79 */ + volatile uint8_t dummy164[48]; /* */ + +/* #define RSCAN0_TMSTS0_COUNT (80) */ + volatile uint8_t TMSTS0; /* TMSTS0 */ + volatile uint8_t TMSTS1; /* TMSTS1 */ + volatile uint8_t TMSTS2; /* TMSTS2 */ + volatile uint8_t TMSTS3; /* TMSTS3 */ + volatile uint8_t TMSTS4; /* TMSTS4 */ + volatile uint8_t TMSTS5; /* TMSTS5 */ + volatile uint8_t TMSTS6; /* TMSTS6 */ + volatile uint8_t TMSTS7; /* TMSTS7 */ + volatile uint8_t TMSTS8; /* TMSTS8 */ + volatile uint8_t TMSTS9; /* TMSTS9 */ + volatile uint8_t TMSTS10; /* TMSTS10 */ + volatile uint8_t TMSTS11; /* TMSTS11 */ + volatile uint8_t TMSTS12; /* TMSTS12 */ + volatile uint8_t TMSTS13; /* TMSTS13 */ + volatile uint8_t TMSTS14; /* TMSTS14 */ + volatile uint8_t TMSTS15; /* TMSTS15 */ + volatile uint8_t TMSTS16; /* TMSTS16 */ + volatile uint8_t TMSTS17; /* TMSTS17 */ + volatile uint8_t TMSTS18; /* TMSTS18 */ + volatile uint8_t TMSTS19; /* TMSTS19 */ + volatile uint8_t TMSTS20; /* TMSTS20 */ + volatile uint8_t TMSTS21; /* TMSTS21 */ + volatile uint8_t TMSTS22; /* TMSTS22 */ + volatile uint8_t TMSTS23; /* TMSTS23 */ + volatile uint8_t TMSTS24; /* TMSTS24 */ + volatile uint8_t TMSTS25; /* TMSTS25 */ + volatile uint8_t TMSTS26; /* TMSTS26 */ + volatile uint8_t TMSTS27; /* TMSTS27 */ + volatile uint8_t TMSTS28; /* TMSTS28 */ + volatile uint8_t TMSTS29; /* TMSTS29 */ + volatile uint8_t TMSTS30; /* TMSTS30 */ + volatile uint8_t TMSTS31; /* TMSTS31 */ + volatile uint8_t TMSTS32; /* TMSTS32 */ + volatile uint8_t TMSTS33; /* TMSTS33 */ + volatile uint8_t TMSTS34; /* TMSTS34 */ + volatile uint8_t TMSTS35; /* TMSTS35 */ + volatile uint8_t TMSTS36; /* TMSTS36 */ + volatile uint8_t TMSTS37; /* TMSTS37 */ + volatile uint8_t TMSTS38; /* TMSTS38 */ + volatile uint8_t TMSTS39; /* TMSTS39 */ + volatile uint8_t TMSTS40; /* TMSTS40 */ + volatile uint8_t TMSTS41; /* TMSTS41 */ + volatile uint8_t TMSTS42; /* TMSTS42 */ + volatile uint8_t TMSTS43; /* TMSTS43 */ + volatile uint8_t TMSTS44; /* TMSTS44 */ + volatile uint8_t TMSTS45; /* TMSTS45 */ + volatile uint8_t TMSTS46; /* TMSTS46 */ + volatile uint8_t TMSTS47; /* TMSTS47 */ + volatile uint8_t TMSTS48; /* TMSTS48 */ + volatile uint8_t TMSTS49; /* TMSTS49 */ + volatile uint8_t TMSTS50; /* TMSTS50 */ + volatile uint8_t TMSTS51; /* TMSTS51 */ + volatile uint8_t TMSTS52; /* TMSTS52 */ + volatile uint8_t TMSTS53; /* TMSTS53 */ + volatile uint8_t TMSTS54; /* TMSTS54 */ + volatile uint8_t TMSTS55; /* TMSTS55 */ + volatile uint8_t TMSTS56; /* TMSTS56 */ + volatile uint8_t TMSTS57; /* TMSTS57 */ + volatile uint8_t TMSTS58; /* TMSTS58 */ + volatile uint8_t TMSTS59; /* TMSTS59 */ + volatile uint8_t TMSTS60; /* TMSTS60 */ + volatile uint8_t TMSTS61; /* TMSTS61 */ + volatile uint8_t TMSTS62; /* TMSTS62 */ + volatile uint8_t TMSTS63; /* TMSTS63 */ + volatile uint8_t TMSTS64; /* TMSTS64 */ + volatile uint8_t TMSTS65; /* TMSTS65 */ + volatile uint8_t TMSTS66; /* TMSTS66 */ + volatile uint8_t TMSTS67; /* TMSTS67 */ + volatile uint8_t TMSTS68; /* TMSTS68 */ + volatile uint8_t TMSTS69; /* TMSTS69 */ + volatile uint8_t TMSTS70; /* TMSTS70 */ + volatile uint8_t TMSTS71; /* TMSTS71 */ + volatile uint8_t TMSTS72; /* TMSTS72 */ + volatile uint8_t TMSTS73; /* TMSTS73 */ + volatile uint8_t TMSTS74; /* TMSTS74 */ + volatile uint8_t TMSTS75; /* TMSTS75 */ + volatile uint8_t TMSTS76; /* TMSTS76 */ + volatile uint8_t TMSTS77; /* TMSTS77 */ + volatile uint8_t TMSTS78; /* TMSTS78 */ + volatile uint8_t TMSTS79; /* TMSTS79 */ + volatile uint8_t dummy165[48]; /* */ + +/* #define RSCAN0_TMTRSTS0_COUNT (3) */ + union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */ + union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */ + union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */ + + volatile uint8_t dummy166[4]; /* */ + +/* #define RSCAN0_TMTARSTS0_COUNT (3) */ + union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */ + union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */ + union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */ + + volatile uint8_t dummy167[4]; /* */ + +/* #define RSCAN0_TMTCSTS0_COUNT (3) */ + union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */ + union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */ + union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */ + + volatile uint8_t dummy168[4]; /* */ + +/* #define RSCAN0_TMTASTS0_COUNT (3) */ + union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */ + union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */ + union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */ + + volatile uint8_t dummy169[4]; /* */ + +/* #define RSCAN0_TMIEC0_COUNT (3) */ + union iodefine_reg32_t TMIEC0; /* TMIEC0 */ + union iodefine_reg32_t TMIEC1; /* TMIEC1 */ + union iodefine_reg32_t TMIEC2; /* TMIEC2 */ + + volatile uint8_t dummy170[4]; /* */ + +/* #define RSCAN0_TXQCC0_COUNT (5) */ + union iodefine_reg32_t TXQCC0; /* TXQCC0 */ + union iodefine_reg32_t TXQCC1; /* TXQCC1 */ + union iodefine_reg32_t TXQCC2; /* TXQCC2 */ + union iodefine_reg32_t TXQCC3; /* TXQCC3 */ + union iodefine_reg32_t TXQCC4; /* TXQCC4 */ + + volatile uint8_t dummy171[12]; /* */ + +/* #define RSCAN0_TXQSTS0_COUNT (5) */ + union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */ + union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */ + union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */ + union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */ + union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */ + + volatile uint8_t dummy172[12]; /* */ + +/* #define RSCAN0_TXQPCTR0_COUNT (5) */ + union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */ + union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */ + union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */ + union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */ + union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */ + + volatile uint8_t dummy173[12]; /* */ + +/* #define RSCAN0_THLCC0_COUNT (5) */ + union iodefine_reg32_t THLCC0; /* THLCC0 */ + union iodefine_reg32_t THLCC1; /* THLCC1 */ + union iodefine_reg32_t THLCC2; /* THLCC2 */ + union iodefine_reg32_t THLCC3; /* THLCC3 */ + union iodefine_reg32_t THLCC4; /* THLCC4 */ + + volatile uint8_t dummy174[12]; /* */ + +/* #define RSCAN0_THLSTS0_COUNT (5) */ + union iodefine_reg32_t THLSTS0; /* THLSTS0 */ + union iodefine_reg32_t THLSTS1; /* THLSTS1 */ + union iodefine_reg32_t THLSTS2; /* THLSTS2 */ + union iodefine_reg32_t THLSTS3; /* THLSTS3 */ + union iodefine_reg32_t THLSTS4; /* THLSTS4 */ + + volatile uint8_t dummy175[12]; /* */ + +/* #define RSCAN0_THLPCTR0_COUNT (5) */ + union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */ + union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */ + union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */ + union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */ + union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */ + + volatile uint8_t dummy176[12]; /* */ + +/* #define RSCAN0_GTINTSTS0_COUNT (2) */ + union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */ + union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */ + union iodefine_reg32_t GTSTCFG; /* GTSTCFG */ + union iodefine_reg32_t GTSTCTR; /* GTSTCTR */ + + volatile uint8_t dummy177[12]; /* */ + union iodefine_reg32_16_t GLOCKK; /* GLOCKK */ + + volatile uint8_t dummy178[128]; /* */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID0; /* GAFLID0 */ + union iodefine_reg32_t GAFLM0; /* GAFLM0 */ + union iodefine_reg32_t GAFLP00; /* GAFLP00 */ + union iodefine_reg32_t GAFLP10; /* GAFLP10 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID1; /* GAFLID1 */ + union iodefine_reg32_t GAFLM1; /* GAFLM1 */ + union iodefine_reg32_t GAFLP01; /* GAFLP01 */ + union iodefine_reg32_t GAFLP11; /* GAFLP11 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID2; /* GAFLID2 */ + union iodefine_reg32_t GAFLM2; /* GAFLM2 */ + union iodefine_reg32_t GAFLP02; /* GAFLP02 */ + union iodefine_reg32_t GAFLP12; /* GAFLP12 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID3; /* GAFLID3 */ + union iodefine_reg32_t GAFLM3; /* GAFLM3 */ + union iodefine_reg32_t GAFLP03; /* GAFLP03 */ + union iodefine_reg32_t GAFLP13; /* GAFLP13 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID4; /* GAFLID4 */ + union iodefine_reg32_t GAFLM4; /* GAFLM4 */ + union iodefine_reg32_t GAFLP04; /* GAFLP04 */ + union iodefine_reg32_t GAFLP14; /* GAFLP14 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID5; /* GAFLID5 */ + union iodefine_reg32_t GAFLM5; /* GAFLM5 */ + union iodefine_reg32_t GAFLP05; /* GAFLP05 */ + union iodefine_reg32_t GAFLP15; /* GAFLP15 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID6; /* GAFLID6 */ + union iodefine_reg32_t GAFLM6; /* GAFLM6 */ + union iodefine_reg32_t GAFLP06; /* GAFLP06 */ + union iodefine_reg32_t GAFLP16; /* GAFLP16 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID7; /* GAFLID7 */ + union iodefine_reg32_t GAFLM7; /* GAFLM7 */ + union iodefine_reg32_t GAFLP07; /* GAFLP07 */ + union iodefine_reg32_t GAFLP17; /* GAFLP17 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID8; /* GAFLID8 */ + union iodefine_reg32_t GAFLM8; /* GAFLM8 */ + union iodefine_reg32_t GAFLP08; /* GAFLP08 */ + union iodefine_reg32_t GAFLP18; /* GAFLP18 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID9; /* GAFLID9 */ + union iodefine_reg32_t GAFLM9; /* GAFLM9 */ + union iodefine_reg32_t GAFLP09; /* GAFLP09 */ + union iodefine_reg32_t GAFLP19; /* GAFLP19 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID10; /* GAFLID10 */ + union iodefine_reg32_t GAFLM10; /* GAFLM10 */ + union iodefine_reg32_t GAFLP010; /* GAFLP010 */ + union iodefine_reg32_t GAFLP110; /* GAFLP110 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID11; /* GAFLID11 */ + union iodefine_reg32_t GAFLM11; /* GAFLM11 */ + union iodefine_reg32_t GAFLP011; /* GAFLP011 */ + union iodefine_reg32_t GAFLP111; /* GAFLP111 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID12; /* GAFLID12 */ + union iodefine_reg32_t GAFLM12; /* GAFLM12 */ + union iodefine_reg32_t GAFLP012; /* GAFLP012 */ + union iodefine_reg32_t GAFLP112; /* GAFLP112 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID13; /* GAFLID13 */ + union iodefine_reg32_t GAFLM13; /* GAFLM13 */ + union iodefine_reg32_t GAFLP013; /* GAFLP013 */ + union iodefine_reg32_t GAFLP113; /* GAFLP113 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID14; /* GAFLID14 */ + union iodefine_reg32_t GAFLM14; /* GAFLM14 */ + union iodefine_reg32_t GAFLP014; /* GAFLP014 */ + union iodefine_reg32_t GAFLP114; /* GAFLP114 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID15; /* GAFLID15 */ + union iodefine_reg32_t GAFLM15; /* GAFLM15 */ + union iodefine_reg32_t GAFLP015; /* GAFLP015 */ + union iodefine_reg32_t GAFLP115; /* GAFLP115 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID0; /* RMID0 */ + union iodefine_reg32_t RMPTR0; /* RMPTR0 */ + union iodefine_reg32_t RMDF00; /* RMDF00 */ + union iodefine_reg32_t RMDF10; /* RMDF10 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID1; /* RMID1 */ + union iodefine_reg32_t RMPTR1; /* RMPTR1 */ + union iodefine_reg32_t RMDF01; /* RMDF01 */ + union iodefine_reg32_t RMDF11; /* RMDF11 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID2; /* RMID2 */ + union iodefine_reg32_t RMPTR2; /* RMPTR2 */ + union iodefine_reg32_t RMDF02; /* RMDF02 */ + union iodefine_reg32_t RMDF12; /* RMDF12 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID3; /* RMID3 */ + union iodefine_reg32_t RMPTR3; /* RMPTR3 */ + union iodefine_reg32_t RMDF03; /* RMDF03 */ + union iodefine_reg32_t RMDF13; /* RMDF13 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID4; /* RMID4 */ + union iodefine_reg32_t RMPTR4; /* RMPTR4 */ + union iodefine_reg32_t RMDF04; /* RMDF04 */ + union iodefine_reg32_t RMDF14; /* RMDF14 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID5; /* RMID5 */ + union iodefine_reg32_t RMPTR5; /* RMPTR5 */ + union iodefine_reg32_t RMDF05; /* RMDF05 */ + union iodefine_reg32_t RMDF15; /* RMDF15 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID6; /* RMID6 */ + union iodefine_reg32_t RMPTR6; /* RMPTR6 */ + union iodefine_reg32_t RMDF06; /* RMDF06 */ + union iodefine_reg32_t RMDF16; /* RMDF16 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID7; /* RMID7 */ + union iodefine_reg32_t RMPTR7; /* RMPTR7 */ + union iodefine_reg32_t RMDF07; /* RMDF07 */ + union iodefine_reg32_t RMDF17; /* RMDF17 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID8; /* RMID8 */ + union iodefine_reg32_t RMPTR8; /* RMPTR8 */ + union iodefine_reg32_t RMDF08; /* RMDF08 */ + union iodefine_reg32_t RMDF18; /* RMDF18 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID9; /* RMID9 */ + union iodefine_reg32_t RMPTR9; /* RMPTR9 */ + union iodefine_reg32_t RMDF09; /* RMDF09 */ + union iodefine_reg32_t RMDF19; /* RMDF19 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID10; /* RMID10 */ + union iodefine_reg32_t RMPTR10; /* RMPTR10 */ + union iodefine_reg32_t RMDF010; /* RMDF010 */ + union iodefine_reg32_t RMDF110; /* RMDF110 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID11; /* RMID11 */ + union iodefine_reg32_t RMPTR11; /* RMPTR11 */ + union iodefine_reg32_t RMDF011; /* RMDF011 */ + union iodefine_reg32_t RMDF111; /* RMDF111 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID12; /* RMID12 */ + union iodefine_reg32_t RMPTR12; /* RMPTR12 */ + union iodefine_reg32_t RMDF012; /* RMDF012 */ + union iodefine_reg32_t RMDF112; /* RMDF112 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID13; /* RMID13 */ + union iodefine_reg32_t RMPTR13; /* RMPTR13 */ + union iodefine_reg32_t RMDF013; /* RMDF013 */ + union iodefine_reg32_t RMDF113; /* RMDF113 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID14; /* RMID14 */ + union iodefine_reg32_t RMPTR14; /* RMPTR14 */ + union iodefine_reg32_t RMDF014; /* RMDF014 */ + union iodefine_reg32_t RMDF114; /* RMDF114 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID15; /* RMID15 */ + union iodefine_reg32_t RMPTR15; /* RMPTR15 */ + union iodefine_reg32_t RMDF015; /* RMDF015 */ + union iodefine_reg32_t RMDF115; /* RMDF115 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID16; /* RMID16 */ + union iodefine_reg32_t RMPTR16; /* RMPTR16 */ + union iodefine_reg32_t RMDF016; /* RMDF016 */ + union iodefine_reg32_t RMDF116; /* RMDF116 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID17; /* RMID17 */ + union iodefine_reg32_t RMPTR17; /* RMPTR17 */ + union iodefine_reg32_t RMDF017; /* RMDF017 */ + union iodefine_reg32_t RMDF117; /* RMDF117 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID18; /* RMID18 */ + union iodefine_reg32_t RMPTR18; /* RMPTR18 */ + union iodefine_reg32_t RMDF018; /* RMDF018 */ + union iodefine_reg32_t RMDF118; /* RMDF118 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID19; /* RMID19 */ + union iodefine_reg32_t RMPTR19; /* RMPTR19 */ + union iodefine_reg32_t RMDF019; /* RMDF019 */ + union iodefine_reg32_t RMDF119; /* RMDF119 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID20; /* RMID20 */ + union iodefine_reg32_t RMPTR20; /* RMPTR20 */ + union iodefine_reg32_t RMDF020; /* RMDF020 */ + union iodefine_reg32_t RMDF120; /* RMDF120 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID21; /* RMID21 */ + union iodefine_reg32_t RMPTR21; /* RMPTR21 */ + union iodefine_reg32_t RMDF021; /* RMDF021 */ + union iodefine_reg32_t RMDF121; /* RMDF121 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID22; /* RMID22 */ + union iodefine_reg32_t RMPTR22; /* RMPTR22 */ + union iodefine_reg32_t RMDF022; /* RMDF022 */ + union iodefine_reg32_t RMDF122; /* RMDF122 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID23; /* RMID23 */ + union iodefine_reg32_t RMPTR23; /* RMPTR23 */ + union iodefine_reg32_t RMDF023; /* RMDF023 */ + union iodefine_reg32_t RMDF123; /* RMDF123 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID24; /* RMID24 */ + union iodefine_reg32_t RMPTR24; /* RMPTR24 */ + union iodefine_reg32_t RMDF024; /* RMDF024 */ + union iodefine_reg32_t RMDF124; /* RMDF124 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID25; /* RMID25 */ + union iodefine_reg32_t RMPTR25; /* RMPTR25 */ + union iodefine_reg32_t RMDF025; /* RMDF025 */ + union iodefine_reg32_t RMDF125; /* RMDF125 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID26; /* RMID26 */ + union iodefine_reg32_t RMPTR26; /* RMPTR26 */ + union iodefine_reg32_t RMDF026; /* RMDF026 */ + union iodefine_reg32_t RMDF126; /* RMDF126 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID27; /* RMID27 */ + union iodefine_reg32_t RMPTR27; /* RMPTR27 */ + union iodefine_reg32_t RMDF027; /* RMDF027 */ + union iodefine_reg32_t RMDF127; /* RMDF127 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID28; /* RMID28 */ + union iodefine_reg32_t RMPTR28; /* RMPTR28 */ + union iodefine_reg32_t RMDF028; /* RMDF028 */ + union iodefine_reg32_t RMDF128; /* RMDF128 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID29; /* RMID29 */ + union iodefine_reg32_t RMPTR29; /* RMPTR29 */ + union iodefine_reg32_t RMDF029; /* RMDF029 */ + union iodefine_reg32_t RMDF129; /* RMDF129 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID30; /* RMID30 */ + union iodefine_reg32_t RMPTR30; /* RMPTR30 */ + union iodefine_reg32_t RMDF030; /* RMDF030 */ + union iodefine_reg32_t RMDF130; /* RMDF130 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID31; /* RMID31 */ + union iodefine_reg32_t RMPTR31; /* RMPTR31 */ + union iodefine_reg32_t RMDF031; /* RMDF031 */ + union iodefine_reg32_t RMDF131; /* RMDF131 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID32; /* RMID32 */ + union iodefine_reg32_t RMPTR32; /* RMPTR32 */ + union iodefine_reg32_t RMDF032; /* RMDF032 */ + union iodefine_reg32_t RMDF132; /* RMDF132 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID33; /* RMID33 */ + union iodefine_reg32_t RMPTR33; /* RMPTR33 */ + union iodefine_reg32_t RMDF033; /* RMDF033 */ + union iodefine_reg32_t RMDF133; /* RMDF133 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID34; /* RMID34 */ + union iodefine_reg32_t RMPTR34; /* RMPTR34 */ + union iodefine_reg32_t RMDF034; /* RMDF034 */ + union iodefine_reg32_t RMDF134; /* RMDF134 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID35; /* RMID35 */ + union iodefine_reg32_t RMPTR35; /* RMPTR35 */ + union iodefine_reg32_t RMDF035; /* RMDF035 */ + union iodefine_reg32_t RMDF135; /* RMDF135 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID36; /* RMID36 */ + union iodefine_reg32_t RMPTR36; /* RMPTR36 */ + union iodefine_reg32_t RMDF036; /* RMDF036 */ + union iodefine_reg32_t RMDF136; /* RMDF136 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID37; /* RMID37 */ + union iodefine_reg32_t RMPTR37; /* RMPTR37 */ + union iodefine_reg32_t RMDF037; /* RMDF037 */ + union iodefine_reg32_t RMDF137; /* RMDF137 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID38; /* RMID38 */ + union iodefine_reg32_t RMPTR38; /* RMPTR38 */ + union iodefine_reg32_t RMDF038; /* RMDF038 */ + union iodefine_reg32_t RMDF138; /* RMDF138 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID39; /* RMID39 */ + union iodefine_reg32_t RMPTR39; /* RMPTR39 */ + union iodefine_reg32_t RMDF039; /* RMDF039 */ + union iodefine_reg32_t RMDF139; /* RMDF139 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID40; /* RMID40 */ + union iodefine_reg32_t RMPTR40; /* RMPTR40 */ + union iodefine_reg32_t RMDF040; /* RMDF040 */ + union iodefine_reg32_t RMDF140; /* RMDF140 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID41; /* RMID41 */ + union iodefine_reg32_t RMPTR41; /* RMPTR41 */ + union iodefine_reg32_t RMDF041; /* RMDF041 */ + union iodefine_reg32_t RMDF141; /* RMDF141 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID42; /* RMID42 */ + union iodefine_reg32_t RMPTR42; /* RMPTR42 */ + union iodefine_reg32_t RMDF042; /* RMDF042 */ + union iodefine_reg32_t RMDF142; /* RMDF142 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID43; /* RMID43 */ + union iodefine_reg32_t RMPTR43; /* RMPTR43 */ + union iodefine_reg32_t RMDF043; /* RMDF043 */ + union iodefine_reg32_t RMDF143; /* RMDF143 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID44; /* RMID44 */ + union iodefine_reg32_t RMPTR44; /* RMPTR44 */ + union iodefine_reg32_t RMDF044; /* RMDF044 */ + union iodefine_reg32_t RMDF144; /* RMDF144 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID45; /* RMID45 */ + union iodefine_reg32_t RMPTR45; /* RMPTR45 */ + union iodefine_reg32_t RMDF045; /* RMDF045 */ + union iodefine_reg32_t RMDF145; /* RMDF145 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID46; /* RMID46 */ + union iodefine_reg32_t RMPTR46; /* RMPTR46 */ + union iodefine_reg32_t RMDF046; /* RMDF046 */ + union iodefine_reg32_t RMDF146; /* RMDF146 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID47; /* RMID47 */ + union iodefine_reg32_t RMPTR47; /* RMPTR47 */ + union iodefine_reg32_t RMDF047; /* RMDF047 */ + union iodefine_reg32_t RMDF147; /* RMDF147 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID48; /* RMID48 */ + union iodefine_reg32_t RMPTR48; /* RMPTR48 */ + union iodefine_reg32_t RMDF048; /* RMDF048 */ + union iodefine_reg32_t RMDF148; /* RMDF148 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID49; /* RMID49 */ + union iodefine_reg32_t RMPTR49; /* RMPTR49 */ + union iodefine_reg32_t RMDF049; /* RMDF049 */ + union iodefine_reg32_t RMDF149; /* RMDF149 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID50; /* RMID50 */ + union iodefine_reg32_t RMPTR50; /* RMPTR50 */ + union iodefine_reg32_t RMDF050; /* RMDF050 */ + union iodefine_reg32_t RMDF150; /* RMDF150 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID51; /* RMID51 */ + union iodefine_reg32_t RMPTR51; /* RMPTR51 */ + union iodefine_reg32_t RMDF051; /* RMDF051 */ + union iodefine_reg32_t RMDF151; /* RMDF151 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID52; /* RMID52 */ + union iodefine_reg32_t RMPTR52; /* RMPTR52 */ + union iodefine_reg32_t RMDF052; /* RMDF052 */ + union iodefine_reg32_t RMDF152; /* RMDF152 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID53; /* RMID53 */ + union iodefine_reg32_t RMPTR53; /* RMPTR53 */ + union iodefine_reg32_t RMDF053; /* RMDF053 */ + union iodefine_reg32_t RMDF153; /* RMDF153 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID54; /* RMID54 */ + union iodefine_reg32_t RMPTR54; /* RMPTR54 */ + union iodefine_reg32_t RMDF054; /* RMDF054 */ + union iodefine_reg32_t RMDF154; /* RMDF154 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID55; /* RMID55 */ + union iodefine_reg32_t RMPTR55; /* RMPTR55 */ + union iodefine_reg32_t RMDF055; /* RMDF055 */ + union iodefine_reg32_t RMDF155; /* RMDF155 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID56; /* RMID56 */ + union iodefine_reg32_t RMPTR56; /* RMPTR56 */ + union iodefine_reg32_t RMDF056; /* RMDF056 */ + union iodefine_reg32_t RMDF156; /* RMDF156 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID57; /* RMID57 */ + union iodefine_reg32_t RMPTR57; /* RMPTR57 */ + union iodefine_reg32_t RMDF057; /* RMDF057 */ + union iodefine_reg32_t RMDF157; /* RMDF157 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID58; /* RMID58 */ + union iodefine_reg32_t RMPTR58; /* RMPTR58 */ + union iodefine_reg32_t RMDF058; /* RMDF058 */ + union iodefine_reg32_t RMDF158; /* RMDF158 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID59; /* RMID59 */ + union iodefine_reg32_t RMPTR59; /* RMPTR59 */ + union iodefine_reg32_t RMDF059; /* RMDF059 */ + union iodefine_reg32_t RMDF159; /* RMDF159 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID60; /* RMID60 */ + union iodefine_reg32_t RMPTR60; /* RMPTR60 */ + union iodefine_reg32_t RMDF060; /* RMDF060 */ + union iodefine_reg32_t RMDF160; /* RMDF160 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID61; /* RMID61 */ + union iodefine_reg32_t RMPTR61; /* RMPTR61 */ + union iodefine_reg32_t RMDF061; /* RMDF061 */ + union iodefine_reg32_t RMDF161; /* RMDF161 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID62; /* RMID62 */ + union iodefine_reg32_t RMPTR62; /* RMPTR62 */ + union iodefine_reg32_t RMDF062; /* RMDF062 */ + union iodefine_reg32_t RMDF162; /* RMDF162 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID63; /* RMID63 */ + union iodefine_reg32_t RMPTR63; /* RMPTR63 */ + union iodefine_reg32_t RMDF063; /* RMDF063 */ + union iodefine_reg32_t RMDF163; /* RMDF163 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID64; /* RMID64 */ + union iodefine_reg32_t RMPTR64; /* RMPTR64 */ + union iodefine_reg32_t RMDF064; /* RMDF064 */ + union iodefine_reg32_t RMDF164; /* RMDF164 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID65; /* RMID65 */ + union iodefine_reg32_t RMPTR65; /* RMPTR65 */ + union iodefine_reg32_t RMDF065; /* RMDF065 */ + union iodefine_reg32_t RMDF165; /* RMDF165 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID66; /* RMID66 */ + union iodefine_reg32_t RMPTR66; /* RMPTR66 */ + union iodefine_reg32_t RMDF066; /* RMDF066 */ + union iodefine_reg32_t RMDF166; /* RMDF166 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID67; /* RMID67 */ + union iodefine_reg32_t RMPTR67; /* RMPTR67 */ + union iodefine_reg32_t RMDF067; /* RMDF067 */ + union iodefine_reg32_t RMDF167; /* RMDF167 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID68; /* RMID68 */ + union iodefine_reg32_t RMPTR68; /* RMPTR68 */ + union iodefine_reg32_t RMDF068; /* RMDF068 */ + union iodefine_reg32_t RMDF168; /* RMDF168 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID69; /* RMID69 */ + union iodefine_reg32_t RMPTR69; /* RMPTR69 */ + union iodefine_reg32_t RMDF069; /* RMDF069 */ + union iodefine_reg32_t RMDF169; /* RMDF169 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID70; /* RMID70 */ + union iodefine_reg32_t RMPTR70; /* RMPTR70 */ + union iodefine_reg32_t RMDF070; /* RMDF070 */ + union iodefine_reg32_t RMDF170; /* RMDF170 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID71; /* RMID71 */ + union iodefine_reg32_t RMPTR71; /* RMPTR71 */ + union iodefine_reg32_t RMDF071; /* RMDF071 */ + union iodefine_reg32_t RMDF171; /* RMDF171 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID72; /* RMID72 */ + union iodefine_reg32_t RMPTR72; /* RMPTR72 */ + union iodefine_reg32_t RMDF072; /* RMDF072 */ + union iodefine_reg32_t RMDF172; /* RMDF172 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID73; /* RMID73 */ + union iodefine_reg32_t RMPTR73; /* RMPTR73 */ + union iodefine_reg32_t RMDF073; /* RMDF073 */ + union iodefine_reg32_t RMDF173; /* RMDF173 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID74; /* RMID74 */ + union iodefine_reg32_t RMPTR74; /* RMPTR74 */ + union iodefine_reg32_t RMDF074; /* RMDF074 */ + union iodefine_reg32_t RMDF174; /* RMDF174 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID75; /* RMID75 */ + union iodefine_reg32_t RMPTR75; /* RMPTR75 */ + union iodefine_reg32_t RMDF075; /* RMDF075 */ + union iodefine_reg32_t RMDF175; /* RMDF175 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID76; /* RMID76 */ + union iodefine_reg32_t RMPTR76; /* RMPTR76 */ + union iodefine_reg32_t RMDF076; /* RMDF076 */ + union iodefine_reg32_t RMDF176; /* RMDF176 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID77; /* RMID77 */ + union iodefine_reg32_t RMPTR77; /* RMPTR77 */ + union iodefine_reg32_t RMDF077; /* RMDF077 */ + union iodefine_reg32_t RMDF177; /* RMDF177 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID78; /* RMID78 */ + union iodefine_reg32_t RMPTR78; /* RMPTR78 */ + union iodefine_reg32_t RMDF078; /* RMDF078 */ + union iodefine_reg32_t RMDF178; /* RMDF178 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID79; /* RMID79 */ + union iodefine_reg32_t RMPTR79; /* RMPTR79 */ + union iodefine_reg32_t RMDF079; /* RMDF079 */ + union iodefine_reg32_t RMDF179; /* RMDF179 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + + volatile uint8_t dummy179[768]; /* */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID0; /* RFID0 */ + union iodefine_reg32_t RFPTR0; /* RFPTR0 */ + union iodefine_reg32_t RFDF00; /* RFDF00 */ + union iodefine_reg32_t RFDF10; /* RFDF10 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID1; /* RFID1 */ + union iodefine_reg32_t RFPTR1; /* RFPTR1 */ + union iodefine_reg32_t RFDF01; /* RFDF01 */ + union iodefine_reg32_t RFDF11; /* RFDF11 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID2; /* RFID2 */ + union iodefine_reg32_t RFPTR2; /* RFPTR2 */ + union iodefine_reg32_t RFDF02; /* RFDF02 */ + union iodefine_reg32_t RFDF12; /* RFDF12 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID3; /* RFID3 */ + union iodefine_reg32_t RFPTR3; /* RFPTR3 */ + union iodefine_reg32_t RFDF03; /* RFDF03 */ + union iodefine_reg32_t RFDF13; /* RFDF13 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID4; /* RFID4 */ + union iodefine_reg32_t RFPTR4; /* RFPTR4 */ + union iodefine_reg32_t RFDF04; /* RFDF04 */ + union iodefine_reg32_t RFDF14; /* RFDF14 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID5; /* RFID5 */ + union iodefine_reg32_t RFPTR5; /* RFPTR5 */ + union iodefine_reg32_t RFDF05; /* RFDF05 */ + union iodefine_reg32_t RFDF15; /* RFDF15 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID6; /* RFID6 */ + union iodefine_reg32_t RFPTR6; /* RFPTR6 */ + union iodefine_reg32_t RFDF06; /* RFDF06 */ + union iodefine_reg32_t RFDF16; /* RFDF16 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID7; /* RFID7 */ + union iodefine_reg32_t RFPTR7; /* RFPTR7 */ + union iodefine_reg32_t RFDF07; /* RFDF07 */ + union iodefine_reg32_t RFDF17; /* RFDF17 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID0; /* CFID0 */ + union iodefine_reg32_t CFPTR0; /* CFPTR0 */ + union iodefine_reg32_t CFDF00; /* CFDF00 */ + union iodefine_reg32_t CFDF10; /* CFDF10 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID1; /* CFID1 */ + union iodefine_reg32_t CFPTR1; /* CFPTR1 */ + union iodefine_reg32_t CFDF01; /* CFDF01 */ + union iodefine_reg32_t CFDF11; /* CFDF11 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID2; /* CFID2 */ + union iodefine_reg32_t CFPTR2; /* CFPTR2 */ + union iodefine_reg32_t CFDF02; /* CFDF02 */ + union iodefine_reg32_t CFDF12; /* CFDF12 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID3; /* CFID3 */ + union iodefine_reg32_t CFPTR3; /* CFPTR3 */ + union iodefine_reg32_t CFDF03; /* CFDF03 */ + union iodefine_reg32_t CFDF13; /* CFDF13 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID4; /* CFID4 */ + union iodefine_reg32_t CFPTR4; /* CFPTR4 */ + union iodefine_reg32_t CFDF04; /* CFDF04 */ + union iodefine_reg32_t CFDF14; /* CFDF14 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID5; /* CFID5 */ + union iodefine_reg32_t CFPTR5; /* CFPTR5 */ + union iodefine_reg32_t CFDF05; /* CFDF05 */ + union iodefine_reg32_t CFDF15; /* CFDF15 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID6; /* CFID6 */ + union iodefine_reg32_t CFPTR6; /* CFPTR6 */ + union iodefine_reg32_t CFDF06; /* CFDF06 */ + union iodefine_reg32_t CFDF16; /* CFDF16 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID7; /* CFID7 */ + union iodefine_reg32_t CFPTR7; /* CFPTR7 */ + union iodefine_reg32_t CFDF07; /* CFDF07 */ + union iodefine_reg32_t CFDF17; /* CFDF17 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID8; /* CFID8 */ + union iodefine_reg32_t CFPTR8; /* CFPTR8 */ + union iodefine_reg32_t CFDF08; /* CFDF08 */ + union iodefine_reg32_t CFDF18; /* CFDF18 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID9; /* CFID9 */ + union iodefine_reg32_t CFPTR9; /* CFPTR9 */ + union iodefine_reg32_t CFDF09; /* CFDF09 */ + union iodefine_reg32_t CFDF19; /* CFDF19 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID10; /* CFID10 */ + union iodefine_reg32_t CFPTR10; /* CFPTR10 */ + union iodefine_reg32_t CFDF010; /* CFDF010 */ + union iodefine_reg32_t CFDF110; /* CFDF110 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID11; /* CFID11 */ + union iodefine_reg32_t CFPTR11; /* CFPTR11 */ + union iodefine_reg32_t CFDF011; /* CFDF011 */ + union iodefine_reg32_t CFDF111; /* CFDF111 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID12; /* CFID12 */ + union iodefine_reg32_t CFPTR12; /* CFPTR12 */ + union iodefine_reg32_t CFDF012; /* CFDF012 */ + union iodefine_reg32_t CFDF112; /* CFDF112 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID13; /* CFID13 */ + union iodefine_reg32_t CFPTR13; /* CFPTR13 */ + union iodefine_reg32_t CFDF013; /* CFDF013 */ + union iodefine_reg32_t CFDF113; /* CFDF113 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID14; /* CFID14 */ + union iodefine_reg32_t CFPTR14; /* CFPTR14 */ + union iodefine_reg32_t CFDF014; /* CFDF014 */ + union iodefine_reg32_t CFDF114; /* CFDF114 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + + volatile uint8_t dummy180[144]; /* */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID0; /* TMID0 */ + union iodefine_reg32_t TMPTR0; /* TMPTR0 */ + union iodefine_reg32_t TMDF00; /* TMDF00 */ + union iodefine_reg32_t TMDF10; /* TMDF10 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID1; /* TMID1 */ + union iodefine_reg32_t TMPTR1; /* TMPTR1 */ + union iodefine_reg32_t TMDF01; /* TMDF01 */ + union iodefine_reg32_t TMDF11; /* TMDF11 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID2; /* TMID2 */ + union iodefine_reg32_t TMPTR2; /* TMPTR2 */ + union iodefine_reg32_t TMDF02; /* TMDF02 */ + union iodefine_reg32_t TMDF12; /* TMDF12 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID3; /* TMID3 */ + union iodefine_reg32_t TMPTR3; /* TMPTR3 */ + union iodefine_reg32_t TMDF03; /* TMDF03 */ + union iodefine_reg32_t TMDF13; /* TMDF13 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID4; /* TMID4 */ + union iodefine_reg32_t TMPTR4; /* TMPTR4 */ + union iodefine_reg32_t TMDF04; /* TMDF04 */ + union iodefine_reg32_t TMDF14; /* TMDF14 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID5; /* TMID5 */ + union iodefine_reg32_t TMPTR5; /* TMPTR5 */ + union iodefine_reg32_t TMDF05; /* TMDF05 */ + union iodefine_reg32_t TMDF15; /* TMDF15 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID6; /* TMID6 */ + union iodefine_reg32_t TMPTR6; /* TMPTR6 */ + union iodefine_reg32_t TMDF06; /* TMDF06 */ + union iodefine_reg32_t TMDF16; /* TMDF16 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID7; /* TMID7 */ + union iodefine_reg32_t TMPTR7; /* TMPTR7 */ + union iodefine_reg32_t TMDF07; /* TMDF07 */ + union iodefine_reg32_t TMDF17; /* TMDF17 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID8; /* TMID8 */ + union iodefine_reg32_t TMPTR8; /* TMPTR8 */ + union iodefine_reg32_t TMDF08; /* TMDF08 */ + union iodefine_reg32_t TMDF18; /* TMDF18 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID9; /* TMID9 */ + union iodefine_reg32_t TMPTR9; /* TMPTR9 */ + union iodefine_reg32_t TMDF09; /* TMDF09 */ + union iodefine_reg32_t TMDF19; /* TMDF19 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID10; /* TMID10 */ + union iodefine_reg32_t TMPTR10; /* TMPTR10 */ + union iodefine_reg32_t TMDF010; /* TMDF010 */ + union iodefine_reg32_t TMDF110; /* TMDF110 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID11; /* TMID11 */ + union iodefine_reg32_t TMPTR11; /* TMPTR11 */ + union iodefine_reg32_t TMDF011; /* TMDF011 */ + union iodefine_reg32_t TMDF111; /* TMDF111 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID12; /* TMID12 */ + union iodefine_reg32_t TMPTR12; /* TMPTR12 */ + union iodefine_reg32_t TMDF012; /* TMDF012 */ + union iodefine_reg32_t TMDF112; /* TMDF112 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID13; /* TMID13 */ + union iodefine_reg32_t TMPTR13; /* TMPTR13 */ + union iodefine_reg32_t TMDF013; /* TMDF013 */ + union iodefine_reg32_t TMDF113; /* TMDF113 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID14; /* TMID14 */ + union iodefine_reg32_t TMPTR14; /* TMPTR14 */ + union iodefine_reg32_t TMDF014; /* TMDF014 */ + union iodefine_reg32_t TMDF114; /* TMDF114 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID15; /* TMID15 */ + union iodefine_reg32_t TMPTR15; /* TMPTR15 */ + union iodefine_reg32_t TMDF015; /* TMDF015 */ + union iodefine_reg32_t TMDF115; /* TMDF115 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID16; /* TMID16 */ + union iodefine_reg32_t TMPTR16; /* TMPTR16 */ + union iodefine_reg32_t TMDF016; /* TMDF016 */ + union iodefine_reg32_t TMDF116; /* TMDF116 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID17; /* TMID17 */ + union iodefine_reg32_t TMPTR17; /* TMPTR17 */ + union iodefine_reg32_t TMDF017; /* TMDF017 */ + union iodefine_reg32_t TMDF117; /* TMDF117 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID18; /* TMID18 */ + union iodefine_reg32_t TMPTR18; /* TMPTR18 */ + union iodefine_reg32_t TMDF018; /* TMDF018 */ + union iodefine_reg32_t TMDF118; /* TMDF118 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID19; /* TMID19 */ + union iodefine_reg32_t TMPTR19; /* TMPTR19 */ + union iodefine_reg32_t TMDF019; /* TMDF019 */ + union iodefine_reg32_t TMDF119; /* TMDF119 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID20; /* TMID20 */ + union iodefine_reg32_t TMPTR20; /* TMPTR20 */ + union iodefine_reg32_t TMDF020; /* TMDF020 */ + union iodefine_reg32_t TMDF120; /* TMDF120 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID21; /* TMID21 */ + union iodefine_reg32_t TMPTR21; /* TMPTR21 */ + union iodefine_reg32_t TMDF021; /* TMDF021 */ + union iodefine_reg32_t TMDF121; /* TMDF121 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID22; /* TMID22 */ + union iodefine_reg32_t TMPTR22; /* TMPTR22 */ + union iodefine_reg32_t TMDF022; /* TMDF022 */ + union iodefine_reg32_t TMDF122; /* TMDF122 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID23; /* TMID23 */ + union iodefine_reg32_t TMPTR23; /* TMPTR23 */ + union iodefine_reg32_t TMDF023; /* TMDF023 */ + union iodefine_reg32_t TMDF123; /* TMDF123 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID24; /* TMID24 */ + union iodefine_reg32_t TMPTR24; /* TMPTR24 */ + union iodefine_reg32_t TMDF024; /* TMDF024 */ + union iodefine_reg32_t TMDF124; /* TMDF124 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID25; /* TMID25 */ + union iodefine_reg32_t TMPTR25; /* TMPTR25 */ + union iodefine_reg32_t TMDF025; /* TMDF025 */ + union iodefine_reg32_t TMDF125; /* TMDF125 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID26; /* TMID26 */ + union iodefine_reg32_t TMPTR26; /* TMPTR26 */ + union iodefine_reg32_t TMDF026; /* TMDF026 */ + union iodefine_reg32_t TMDF126; /* TMDF126 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID27; /* TMID27 */ + union iodefine_reg32_t TMPTR27; /* TMPTR27 */ + union iodefine_reg32_t TMDF027; /* TMDF027 */ + union iodefine_reg32_t TMDF127; /* TMDF127 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID28; /* TMID28 */ + union iodefine_reg32_t TMPTR28; /* TMPTR28 */ + union iodefine_reg32_t TMDF028; /* TMDF028 */ + union iodefine_reg32_t TMDF128; /* TMDF128 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID29; /* TMID29 */ + union iodefine_reg32_t TMPTR29; /* TMPTR29 */ + union iodefine_reg32_t TMDF029; /* TMDF029 */ + union iodefine_reg32_t TMDF129; /* TMDF129 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID30; /* TMID30 */ + union iodefine_reg32_t TMPTR30; /* TMPTR30 */ + union iodefine_reg32_t TMDF030; /* TMDF030 */ + union iodefine_reg32_t TMDF130; /* TMDF130 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID31; /* TMID31 */ + union iodefine_reg32_t TMPTR31; /* TMPTR31 */ + union iodefine_reg32_t TMDF031; /* TMDF031 */ + union iodefine_reg32_t TMDF131; /* TMDF131 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID32; /* TMID32 */ + union iodefine_reg32_t TMPTR32; /* TMPTR32 */ + union iodefine_reg32_t TMDF032; /* TMDF032 */ + union iodefine_reg32_t TMDF132; /* TMDF132 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID33; /* TMID33 */ + union iodefine_reg32_t TMPTR33; /* TMPTR33 */ + union iodefine_reg32_t TMDF033; /* TMDF033 */ + union iodefine_reg32_t TMDF133; /* TMDF133 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID34; /* TMID34 */ + union iodefine_reg32_t TMPTR34; /* TMPTR34 */ + union iodefine_reg32_t TMDF034; /* TMDF034 */ + union iodefine_reg32_t TMDF134; /* TMDF134 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID35; /* TMID35 */ + union iodefine_reg32_t TMPTR35; /* TMPTR35 */ + union iodefine_reg32_t TMDF035; /* TMDF035 */ + union iodefine_reg32_t TMDF135; /* TMDF135 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID36; /* TMID36 */ + union iodefine_reg32_t TMPTR36; /* TMPTR36 */ + union iodefine_reg32_t TMDF036; /* TMDF036 */ + union iodefine_reg32_t TMDF136; /* TMDF136 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID37; /* TMID37 */ + union iodefine_reg32_t TMPTR37; /* TMPTR37 */ + union iodefine_reg32_t TMDF037; /* TMDF037 */ + union iodefine_reg32_t TMDF137; /* TMDF137 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID38; /* TMID38 */ + union iodefine_reg32_t TMPTR38; /* TMPTR38 */ + union iodefine_reg32_t TMDF038; /* TMDF038 */ + union iodefine_reg32_t TMDF138; /* TMDF138 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID39; /* TMID39 */ + union iodefine_reg32_t TMPTR39; /* TMPTR39 */ + union iodefine_reg32_t TMDF039; /* TMDF039 */ + union iodefine_reg32_t TMDF139; /* TMDF139 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID40; /* TMID40 */ + union iodefine_reg32_t TMPTR40; /* TMPTR40 */ + union iodefine_reg32_t TMDF040; /* TMDF040 */ + union iodefine_reg32_t TMDF140; /* TMDF140 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID41; /* TMID41 */ + union iodefine_reg32_t TMPTR41; /* TMPTR41 */ + union iodefine_reg32_t TMDF041; /* TMDF041 */ + union iodefine_reg32_t TMDF141; /* TMDF141 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID42; /* TMID42 */ + union iodefine_reg32_t TMPTR42; /* TMPTR42 */ + union iodefine_reg32_t TMDF042; /* TMDF042 */ + union iodefine_reg32_t TMDF142; /* TMDF142 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID43; /* TMID43 */ + union iodefine_reg32_t TMPTR43; /* TMPTR43 */ + union iodefine_reg32_t TMDF043; /* TMDF043 */ + union iodefine_reg32_t TMDF143; /* TMDF143 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID44; /* TMID44 */ + union iodefine_reg32_t TMPTR44; /* TMPTR44 */ + union iodefine_reg32_t TMDF044; /* TMDF044 */ + union iodefine_reg32_t TMDF144; /* TMDF144 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID45; /* TMID45 */ + union iodefine_reg32_t TMPTR45; /* TMPTR45 */ + union iodefine_reg32_t TMDF045; /* TMDF045 */ + union iodefine_reg32_t TMDF145; /* TMDF145 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID46; /* TMID46 */ + union iodefine_reg32_t TMPTR46; /* TMPTR46 */ + union iodefine_reg32_t TMDF046; /* TMDF046 */ + union iodefine_reg32_t TMDF146; /* TMDF146 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID47; /* TMID47 */ + union iodefine_reg32_t TMPTR47; /* TMPTR47 */ + union iodefine_reg32_t TMDF047; /* TMDF047 */ + union iodefine_reg32_t TMDF147; /* TMDF147 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID48; /* TMID48 */ + union iodefine_reg32_t TMPTR48; /* TMPTR48 */ + union iodefine_reg32_t TMDF048; /* TMDF048 */ + union iodefine_reg32_t TMDF148; /* TMDF148 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID49; /* TMID49 */ + union iodefine_reg32_t TMPTR49; /* TMPTR49 */ + union iodefine_reg32_t TMDF049; /* TMDF049 */ + union iodefine_reg32_t TMDF149; /* TMDF149 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID50; /* TMID50 */ + union iodefine_reg32_t TMPTR50; /* TMPTR50 */ + union iodefine_reg32_t TMDF050; /* TMDF050 */ + union iodefine_reg32_t TMDF150; /* TMDF150 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID51; /* TMID51 */ + union iodefine_reg32_t TMPTR51; /* TMPTR51 */ + union iodefine_reg32_t TMDF051; /* TMDF051 */ + union iodefine_reg32_t TMDF151; /* TMDF151 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID52; /* TMID52 */ + union iodefine_reg32_t TMPTR52; /* TMPTR52 */ + union iodefine_reg32_t TMDF052; /* TMDF052 */ + union iodefine_reg32_t TMDF152; /* TMDF152 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID53; /* TMID53 */ + union iodefine_reg32_t TMPTR53; /* TMPTR53 */ + union iodefine_reg32_t TMDF053; /* TMDF053 */ + union iodefine_reg32_t TMDF153; /* TMDF153 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID54; /* TMID54 */ + union iodefine_reg32_t TMPTR54; /* TMPTR54 */ + union iodefine_reg32_t TMDF054; /* TMDF054 */ + union iodefine_reg32_t TMDF154; /* TMDF154 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID55; /* TMID55 */ + union iodefine_reg32_t TMPTR55; /* TMPTR55 */ + union iodefine_reg32_t TMDF055; /* TMDF055 */ + union iodefine_reg32_t TMDF155; /* TMDF155 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID56; /* TMID56 */ + union iodefine_reg32_t TMPTR56; /* TMPTR56 */ + union iodefine_reg32_t TMDF056; /* TMDF056 */ + union iodefine_reg32_t TMDF156; /* TMDF156 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID57; /* TMID57 */ + union iodefine_reg32_t TMPTR57; /* TMPTR57 */ + union iodefine_reg32_t TMDF057; /* TMDF057 */ + union iodefine_reg32_t TMDF157; /* TMDF157 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID58; /* TMID58 */ + union iodefine_reg32_t TMPTR58; /* TMPTR58 */ + union iodefine_reg32_t TMDF058; /* TMDF058 */ + union iodefine_reg32_t TMDF158; /* TMDF158 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID59; /* TMID59 */ + union iodefine_reg32_t TMPTR59; /* TMPTR59 */ + union iodefine_reg32_t TMDF059; /* TMDF059 */ + union iodefine_reg32_t TMDF159; /* TMDF159 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID60; /* TMID60 */ + union iodefine_reg32_t TMPTR60; /* TMPTR60 */ + union iodefine_reg32_t TMDF060; /* TMDF060 */ + union iodefine_reg32_t TMDF160; /* TMDF160 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID61; /* TMID61 */ + union iodefine_reg32_t TMPTR61; /* TMPTR61 */ + union iodefine_reg32_t TMDF061; /* TMDF061 */ + union iodefine_reg32_t TMDF161; /* TMDF161 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID62; /* TMID62 */ + union iodefine_reg32_t TMPTR62; /* TMPTR62 */ + union iodefine_reg32_t TMDF062; /* TMDF062 */ + union iodefine_reg32_t TMDF162; /* TMDF162 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID63; /* TMID63 */ + union iodefine_reg32_t TMPTR63; /* TMPTR63 */ + union iodefine_reg32_t TMDF063; /* TMDF063 */ + union iodefine_reg32_t TMDF163; /* TMDF163 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID64; /* TMID64 */ + union iodefine_reg32_t TMPTR64; /* TMPTR64 */ + union iodefine_reg32_t TMDF064; /* TMDF064 */ + union iodefine_reg32_t TMDF164; /* TMDF164 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID65; /* TMID65 */ + union iodefine_reg32_t TMPTR65; /* TMPTR65 */ + union iodefine_reg32_t TMDF065; /* TMDF065 */ + union iodefine_reg32_t TMDF165; /* TMDF165 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID66; /* TMID66 */ + union iodefine_reg32_t TMPTR66; /* TMPTR66 */ + union iodefine_reg32_t TMDF066; /* TMDF066 */ + union iodefine_reg32_t TMDF166; /* TMDF166 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID67; /* TMID67 */ + union iodefine_reg32_t TMPTR67; /* TMPTR67 */ + union iodefine_reg32_t TMDF067; /* TMDF067 */ + union iodefine_reg32_t TMDF167; /* TMDF167 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID68; /* TMID68 */ + union iodefine_reg32_t TMPTR68; /* TMPTR68 */ + union iodefine_reg32_t TMDF068; /* TMDF068 */ + union iodefine_reg32_t TMDF168; /* TMDF168 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID69; /* TMID69 */ + union iodefine_reg32_t TMPTR69; /* TMPTR69 */ + union iodefine_reg32_t TMDF069; /* TMDF069 */ + union iodefine_reg32_t TMDF169; /* TMDF169 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID70; /* TMID70 */ + union iodefine_reg32_t TMPTR70; /* TMPTR70 */ + union iodefine_reg32_t TMDF070; /* TMDF070 */ + union iodefine_reg32_t TMDF170; /* TMDF170 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID71; /* TMID71 */ + union iodefine_reg32_t TMPTR71; /* TMPTR71 */ + union iodefine_reg32_t TMDF071; /* TMDF071 */ + union iodefine_reg32_t TMDF171; /* TMDF171 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID72; /* TMID72 */ + union iodefine_reg32_t TMPTR72; /* TMPTR72 */ + union iodefine_reg32_t TMDF072; /* TMDF072 */ + union iodefine_reg32_t TMDF172; /* TMDF172 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID73; /* TMID73 */ + union iodefine_reg32_t TMPTR73; /* TMPTR73 */ + union iodefine_reg32_t TMDF073; /* TMDF073 */ + union iodefine_reg32_t TMDF173; /* TMDF173 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID74; /* TMID74 */ + union iodefine_reg32_t TMPTR74; /* TMPTR74 */ + union iodefine_reg32_t TMDF074; /* TMDF074 */ + union iodefine_reg32_t TMDF174; /* TMDF174 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID75; /* TMID75 */ + union iodefine_reg32_t TMPTR75; /* TMPTR75 */ + union iodefine_reg32_t TMDF075; /* TMDF075 */ + union iodefine_reg32_t TMDF175; /* TMDF175 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID76; /* TMID76 */ + union iodefine_reg32_t TMPTR76; /* TMPTR76 */ + union iodefine_reg32_t TMDF076; /* TMDF076 */ + union iodefine_reg32_t TMDF176; /* TMDF176 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID77; /* TMID77 */ + union iodefine_reg32_t TMPTR77; /* TMPTR77 */ + union iodefine_reg32_t TMDF077; /* TMDF077 */ + union iodefine_reg32_t TMDF177; /* TMDF177 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID78; /* TMID78 */ + union iodefine_reg32_t TMPTR78; /* TMPTR78 */ + union iodefine_reg32_t TMDF078; /* TMDF078 */ + union iodefine_reg32_t TMDF178; /* TMDF178 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID79; /* TMID79 */ + union iodefine_reg32_t TMPTR79; /* TMPTR79 */ + union iodefine_reg32_t TMDF079; /* TMDF079 */ + union iodefine_reg32_t TMDF179; /* TMDF179 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + + volatile uint8_t dummy181[768]; /* */ + +/* #define RSCAN0_THLACC0_COUNT (5) */ + union iodefine_reg32_t THLACC0; /* THLACC0 */ + union iodefine_reg32_t THLACC1; /* THLACC1 */ + union iodefine_reg32_t THLACC2; /* THLACC2 */ + union iodefine_reg32_t THLACC3; /* THLACC3 */ + union iodefine_reg32_t THLACC4; /* THLACC4 */ + +} r_io_rscan0_t; + + +typedef struct st_rscan_from_rscan0cncfg +{ + + union iodefine_reg32_t CnCFG; /* CnCFG */ + union iodefine_reg32_t CnCTR; /* CnCTR */ + union iodefine_reg32_t CnSTS; /* CnSTS */ + union iodefine_reg32_t CnERFL; /* CnERFL */ +} r_io_rscan_from_rscan0cncfg_t; + + +typedef struct st_rscan_from_rscan0gaflidj +{ + + union iodefine_reg32_t GAFLIDj; /* GAFLIDj */ + union iodefine_reg32_t GAFLMj; /* GAFLMj */ + union iodefine_reg32_t GAFLP0j; /* GAFLP0j */ + union iodefine_reg32_t GAFLP1j; /* GAFLP1j */ +} r_io_rscan_from_rscan0gaflidj_t; + + +typedef struct st_rscan_from_rscan0rmidp +{ + + union iodefine_reg32_t RMIDp; /* RMIDp */ + union iodefine_reg32_t RMPTRp; /* RMPTRp */ + union iodefine_reg32_t RMDF0p; /* RMDF0p */ + union iodefine_reg32_t RMDF1p; /* RMDF1p */ +} r_io_rscan_from_rscan0rmidp_t; + + +typedef struct st_rscan_from_rscan0rfidm +{ + + union iodefine_reg32_t RFIDm; /* RFIDm */ + union iodefine_reg32_t RFPTRm; /* RFPTRm */ + union iodefine_reg32_t RFDF0m; /* RFDF0m */ + union iodefine_reg32_t RFDF1m; /* RFDF1m */ +} r_io_rscan_from_rscan0rfidm_t; + + +typedef struct st_rscan_from_rscan0tmidp +{ + + union iodefine_reg32_t TMIDp; /* TMIDp */ + union iodefine_reg32_t TMPTRp; /* TMPTRp */ + union iodefine_reg32_t TMDF0p; /* TMDF0p */ + union iodefine_reg32_t TMDF1p; /* TMDF1p */ +} r_io_rscan_from_rscan0tmidp_t; + + +typedef struct st_rscan_from_rscan0cfidm +{ + + union iodefine_reg32_t CFIDm; /* CFIDm */ + union iodefine_reg32_t CFPTRm; /* CFPTRm */ + union iodefine_reg32_t CFDF0m; /* CFDF0m */ + union iodefine_reg32_t CFDF1m; /* CFDF1m */ +} r_io_rscan_from_rscan0cfidm_t; + + +/* Channel array defines of RSCAN0 (2)*/ +#ifdef DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS +volatile struct st_rscan_from_rscan0cfidm* RSCAN_FROM_RSCAN0_CFIDm[ RSCAN_FROM_RSCAN0_CFIDm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS +volatile struct st_rscan_from_rscan0tmidp* RSCAN_FROM_RSCAN0_TMIDp[ RSCAN_FROM_RSCAN0_TMIDp_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS +volatile struct st_rscan_from_rscan0rfidm* RSCAN_FROM_RSCAN0_RFIDm[ RSCAN_FROM_RSCAN0_RFIDm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS +volatile struct st_rscan_from_rscan0rmidp* RSCAN_FROM_RSCAN0_RMIDp[ RSCAN_FROM_RSCAN0_RMIDp_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS +volatile struct st_rscan_from_rscan0gaflidj* RSCAN_FROM_RSCAN0_GAFLIDj[ RSCAN_FROM_RSCAN0_GAFLIDj_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS +volatile struct st_rscan_from_rscan0cncfg* RSCAN_FROM_RSCAN0_CnCFG[ RSCAN_FROM_RSCAN0_CnCFG_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS */ +/* End of channel array defines of RSCAN0 (2)*/ -#define RSCAN0C0CFG RSCAN0.C0CFG.UINT32 -#define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L] -#define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL] -#define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH] -#define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H] -#define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL] -#define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH] -#define RSCAN0C0CTR RSCAN0.C0CTR.UINT32 -#define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L] -#define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL] -#define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH] -#define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H] -#define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL] -#define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH] -#define RSCAN0C0STS RSCAN0.C0STS.UINT32 -#define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L] -#define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL] -#define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH] -#define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H] -#define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL] -#define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH] -#define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32 -#define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L] -#define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL] -#define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH] -#define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H] -#define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL] -#define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH] -#define RSCAN0C1CFG RSCAN0.C1CFG.UINT32 -#define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L] -#define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL] -#define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH] -#define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H] -#define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL] -#define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH] -#define RSCAN0C1CTR RSCAN0.C1CTR.UINT32 -#define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L] -#define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL] -#define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH] -#define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H] -#define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL] -#define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH] -#define RSCAN0C1STS RSCAN0.C1STS.UINT32 -#define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L] -#define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL] -#define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH] -#define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H] -#define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL] -#define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH] -#define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32 -#define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L] -#define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL] -#define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH] -#define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H] -#define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL] -#define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH] -#define RSCAN0C2CFG RSCAN0.C2CFG.UINT32 -#define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L] -#define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL] -#define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH] -#define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H] -#define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL] -#define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH] -#define RSCAN0C2CTR RSCAN0.C2CTR.UINT32 -#define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L] -#define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL] -#define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH] -#define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H] -#define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL] -#define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH] -#define RSCAN0C2STS RSCAN0.C2STS.UINT32 -#define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L] -#define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL] -#define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH] -#define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H] -#define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL] -#define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH] -#define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32 -#define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L] -#define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL] -#define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH] -#define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H] -#define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL] -#define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH] -#define RSCAN0C3CFG RSCAN0.C3CFG.UINT32 -#define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L] -#define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL] -#define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH] -#define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H] -#define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL] -#define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH] -#define RSCAN0C3CTR RSCAN0.C3CTR.UINT32 -#define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L] -#define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL] -#define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH] -#define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H] -#define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL] -#define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH] -#define RSCAN0C3STS RSCAN0.C3STS.UINT32 -#define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L] -#define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL] -#define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH] -#define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H] -#define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL] -#define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH] -#define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32 -#define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L] -#define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL] -#define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH] -#define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H] -#define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL] -#define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH] -#define RSCAN0C4CFG RSCAN0.C4CFG.UINT32 -#define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L] -#define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL] -#define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH] -#define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H] -#define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL] -#define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH] -#define RSCAN0C4CTR RSCAN0.C4CTR.UINT32 -#define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L] -#define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL] -#define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH] -#define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H] -#define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL] -#define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH] -#define RSCAN0C4STS RSCAN0.C4STS.UINT32 -#define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L] -#define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL] -#define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH] -#define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H] -#define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL] -#define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH] -#define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32 -#define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L] -#define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL] -#define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH] -#define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H] -#define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL] -#define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH] -#define RSCAN0GCFG RSCAN0.GCFG.UINT32 -#define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L] -#define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL] -#define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH] -#define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H] -#define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL] -#define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH] -#define RSCAN0GCTR RSCAN0.GCTR.UINT32 -#define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L] -#define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL] -#define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH] -#define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H] -#define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL] -#define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH] -#define RSCAN0GSTS RSCAN0.GSTS.UINT32 -#define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L] -#define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL] -#define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH] -#define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H] -#define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL] -#define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH] -#define RSCAN0GERFL RSCAN0.GERFL.UINT32 -#define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L] -#define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL] -#define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH] -#define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H] -#define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL] -#define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH] -#define RSCAN0GTSC RSCAN0.GTSC.UINT32 -#define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L] -#define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H] -#define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32 -#define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L] -#define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL] -#define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH] -#define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H] -#define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL] -#define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH] -#define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32 -#define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L] -#define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL] -#define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH] -#define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H] -#define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL] -#define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH] -#define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32 -#define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L] -#define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL] -#define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH] -#define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H] -#define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL] -#define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH] -#define RSCAN0RMNB RSCAN0.RMNB.UINT32 -#define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L] -#define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL] -#define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH] -#define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H] -#define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL] -#define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH] -#define RSCAN0RMND0 RSCAN0.RMND0.UINT32 -#define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L] -#define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL] -#define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH] -#define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H] -#define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL] -#define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH] -#define RSCAN0RMND1 RSCAN0.RMND1.UINT32 -#define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L] -#define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL] -#define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH] -#define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H] -#define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL] -#define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH] -#define RSCAN0RMND2 RSCAN0.RMND2.UINT32 -#define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L] -#define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL] -#define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH] -#define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H] -#define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL] -#define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH] -#define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32 -#define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L] -#define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL] -#define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH] -#define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H] -#define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL] -#define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH] -#define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32 -#define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L] -#define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL] -#define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH] -#define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H] -#define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL] -#define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH] -#define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32 -#define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L] -#define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL] -#define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH] -#define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H] -#define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL] -#define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH] -#define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32 -#define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L] -#define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL] -#define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH] -#define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H] -#define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL] -#define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH] -#define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32 -#define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L] -#define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL] -#define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH] -#define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H] -#define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL] -#define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH] -#define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32 -#define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L] -#define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL] -#define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH] -#define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H] -#define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL] -#define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH] -#define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32 -#define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L] -#define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL] -#define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH] -#define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H] -#define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL] -#define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH] -#define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32 -#define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L] -#define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL] -#define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH] -#define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H] -#define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL] -#define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH] -#define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32 -#define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L] -#define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL] -#define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH] -#define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H] -#define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL] -#define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH] -#define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32 -#define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L] -#define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL] -#define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH] -#define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H] -#define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL] -#define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH] -#define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32 -#define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L] -#define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL] -#define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH] -#define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H] -#define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL] -#define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH] -#define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32 -#define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L] -#define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL] -#define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH] -#define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H] -#define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL] -#define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH] -#define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32 -#define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L] -#define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL] -#define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH] -#define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H] -#define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL] -#define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH] -#define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32 -#define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L] -#define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL] -#define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH] -#define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H] -#define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL] -#define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH] -#define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32 -#define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L] -#define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL] -#define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH] -#define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H] -#define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL] -#define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH] -#define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32 -#define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L] -#define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL] -#define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH] -#define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H] -#define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL] -#define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH] -#define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32 -#define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L] -#define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL] -#define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH] -#define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H] -#define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL] -#define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH] -#define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32 -#define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L] -#define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL] -#define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH] -#define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H] -#define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL] -#define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH] -#define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32 -#define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L] -#define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL] -#define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH] -#define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H] -#define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL] -#define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH] -#define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32 -#define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L] -#define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL] -#define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH] -#define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H] -#define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL] -#define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH] -#define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32 -#define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L] -#define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL] -#define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH] -#define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H] -#define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL] -#define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH] -#define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32 -#define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L] -#define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL] -#define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH] -#define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H] -#define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL] -#define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH] -#define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32 -#define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L] -#define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL] -#define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH] -#define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H] -#define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL] -#define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH] -#define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32 -#define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L] -#define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL] -#define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH] -#define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H] -#define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL] -#define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH] -#define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32 -#define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L] -#define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL] -#define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH] -#define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H] -#define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL] -#define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH] -#define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32 -#define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L] -#define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL] -#define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH] -#define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H] -#define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL] -#define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH] -#define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32 -#define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L] -#define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL] -#define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH] -#define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H] -#define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL] -#define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH] -#define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32 -#define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L] -#define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL] -#define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH] -#define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H] -#define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL] -#define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH] -#define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32 -#define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L] -#define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL] -#define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH] -#define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H] -#define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL] -#define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH] -#define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32 -#define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L] -#define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL] -#define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH] -#define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H] -#define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL] -#define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH] -#define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32 -#define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L] -#define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL] -#define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH] -#define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H] -#define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL] -#define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH] -#define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32 -#define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L] -#define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL] -#define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH] -#define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H] -#define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL] -#define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH] -#define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32 -#define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L] -#define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL] -#define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH] -#define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H] -#define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL] -#define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH] -#define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32 -#define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L] -#define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL] -#define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH] -#define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H] -#define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL] -#define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH] -#define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32 -#define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L] -#define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL] -#define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH] -#define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H] -#define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL] -#define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH] -#define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32 -#define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L] -#define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL] -#define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH] -#define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H] -#define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL] -#define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH] -#define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32 -#define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L] -#define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL] -#define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH] -#define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H] -#define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL] -#define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH] -#define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32 -#define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L] -#define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL] -#define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH] -#define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H] -#define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL] -#define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH] -#define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32 -#define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L] -#define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL] -#define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH] -#define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H] -#define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL] -#define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH] -#define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32 -#define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L] -#define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL] -#define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH] -#define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H] -#define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL] -#define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH] -#define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32 -#define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L] -#define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL] -#define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH] -#define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H] -#define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL] -#define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH] -#define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32 -#define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L] -#define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL] -#define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH] -#define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H] -#define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL] -#define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH] -#define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32 -#define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L] -#define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL] -#define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH] -#define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H] -#define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL] -#define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH] -#define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32 -#define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L] -#define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL] -#define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH] -#define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H] -#define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL] -#define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH] -#define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32 -#define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L] -#define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL] -#define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH] -#define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H] -#define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL] -#define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH] -#define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32 -#define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L] -#define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL] -#define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH] -#define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H] -#define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL] -#define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH] -#define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32 -#define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L] -#define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL] -#define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH] -#define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H] -#define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL] -#define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH] -#define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32 -#define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L] -#define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL] -#define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH] -#define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H] -#define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL] -#define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH] -#define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32 -#define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L] -#define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL] -#define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH] -#define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H] -#define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL] -#define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH] -#define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32 -#define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L] -#define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL] -#define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH] -#define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H] -#define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL] -#define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH] -#define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32 -#define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L] -#define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL] -#define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH] -#define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H] -#define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL] -#define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH] -#define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32 -#define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L] -#define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL] -#define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH] -#define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H] -#define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL] -#define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH] -#define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32 -#define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L] -#define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL] -#define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH] -#define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H] -#define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL] -#define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH] -#define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32 -#define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L] -#define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL] -#define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH] -#define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H] -#define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL] -#define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH] -#define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32 -#define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L] -#define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL] -#define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH] -#define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H] -#define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL] -#define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH] -#define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32 -#define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L] -#define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL] -#define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH] -#define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H] -#define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL] -#define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH] -#define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32 -#define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L] -#define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL] -#define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH] -#define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H] -#define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL] -#define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH] -#define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32 -#define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L] -#define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL] -#define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH] -#define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H] -#define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL] -#define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH] -#define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32 -#define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L] -#define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL] -#define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH] -#define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H] -#define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL] -#define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH] -#define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32 -#define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L] -#define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL] -#define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH] -#define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H] -#define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL] -#define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH] -#define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32 -#define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L] -#define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL] -#define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH] -#define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H] -#define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL] -#define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH] -#define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32 -#define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L] -#define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL] -#define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH] -#define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H] -#define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL] -#define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH] -#define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32 -#define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L] -#define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL] -#define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH] -#define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H] -#define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL] -#define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH] -#define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32 -#define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L] -#define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL] -#define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH] -#define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H] -#define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL] -#define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH] -#define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32 -#define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L] -#define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL] -#define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH] -#define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H] -#define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL] -#define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH] -#define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32 -#define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L] -#define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL] -#define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH] -#define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H] -#define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL] -#define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH] -#define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32 -#define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L] -#define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL] -#define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH] -#define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H] -#define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL] -#define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH] -#define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32 -#define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L] -#define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL] -#define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH] -#define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H] -#define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL] -#define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH] -#define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32 -#define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L] -#define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL] -#define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH] -#define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H] -#define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL] -#define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH] -#define RSCAN0FESTS RSCAN0.FESTS.UINT32 -#define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L] -#define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL] -#define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH] -#define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H] -#define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL] -#define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH] -#define RSCAN0FFSTS RSCAN0.FFSTS.UINT32 -#define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L] -#define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL] -#define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH] -#define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H] -#define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL] -#define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH] -#define RSCAN0FMSTS RSCAN0.FMSTS.UINT32 -#define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L] -#define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL] -#define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH] -#define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H] -#define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL] -#define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH] -#define RSCAN0RFISTS RSCAN0.RFISTS.UINT32 -#define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L] -#define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL] -#define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH] -#define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H] -#define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL] -#define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH] -#define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32 -#define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L] -#define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL] -#define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH] -#define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H] -#define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL] -#define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH] -#define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32 -#define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L] -#define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL] -#define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH] -#define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H] -#define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL] -#define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH] -#define RSCAN0TMC0 RSCAN0.TMC0 -#define RSCAN0TMC1 RSCAN0.TMC1 -#define RSCAN0TMC2 RSCAN0.TMC2 -#define RSCAN0TMC3 RSCAN0.TMC3 -#define RSCAN0TMC4 RSCAN0.TMC4 -#define RSCAN0TMC5 RSCAN0.TMC5 -#define RSCAN0TMC6 RSCAN0.TMC6 -#define RSCAN0TMC7 RSCAN0.TMC7 -#define RSCAN0TMC8 RSCAN0.TMC8 -#define RSCAN0TMC9 RSCAN0.TMC9 -#define RSCAN0TMC10 RSCAN0.TMC10 -#define RSCAN0TMC11 RSCAN0.TMC11 -#define RSCAN0TMC12 RSCAN0.TMC12 -#define RSCAN0TMC13 RSCAN0.TMC13 -#define RSCAN0TMC14 RSCAN0.TMC14 -#define RSCAN0TMC15 RSCAN0.TMC15 -#define RSCAN0TMC16 RSCAN0.TMC16 -#define RSCAN0TMC17 RSCAN0.TMC17 -#define RSCAN0TMC18 RSCAN0.TMC18 -#define RSCAN0TMC19 RSCAN0.TMC19 -#define RSCAN0TMC20 RSCAN0.TMC20 -#define RSCAN0TMC21 RSCAN0.TMC21 -#define RSCAN0TMC22 RSCAN0.TMC22 -#define RSCAN0TMC23 RSCAN0.TMC23 -#define RSCAN0TMC24 RSCAN0.TMC24 -#define RSCAN0TMC25 RSCAN0.TMC25 -#define RSCAN0TMC26 RSCAN0.TMC26 -#define RSCAN0TMC27 RSCAN0.TMC27 -#define RSCAN0TMC28 RSCAN0.TMC28 -#define RSCAN0TMC29 RSCAN0.TMC29 -#define RSCAN0TMC30 RSCAN0.TMC30 -#define RSCAN0TMC31 RSCAN0.TMC31 -#define RSCAN0TMC32 RSCAN0.TMC32 -#define RSCAN0TMC33 RSCAN0.TMC33 -#define RSCAN0TMC34 RSCAN0.TMC34 -#define RSCAN0TMC35 RSCAN0.TMC35 -#define RSCAN0TMC36 RSCAN0.TMC36 -#define RSCAN0TMC37 RSCAN0.TMC37 -#define RSCAN0TMC38 RSCAN0.TMC38 -#define RSCAN0TMC39 RSCAN0.TMC39 -#define RSCAN0TMC40 RSCAN0.TMC40 -#define RSCAN0TMC41 RSCAN0.TMC41 -#define RSCAN0TMC42 RSCAN0.TMC42 -#define RSCAN0TMC43 RSCAN0.TMC43 -#define RSCAN0TMC44 RSCAN0.TMC44 -#define RSCAN0TMC45 RSCAN0.TMC45 -#define RSCAN0TMC46 RSCAN0.TMC46 -#define RSCAN0TMC47 RSCAN0.TMC47 -#define RSCAN0TMC48 RSCAN0.TMC48 -#define RSCAN0TMC49 RSCAN0.TMC49 -#define RSCAN0TMC50 RSCAN0.TMC50 -#define RSCAN0TMC51 RSCAN0.TMC51 -#define RSCAN0TMC52 RSCAN0.TMC52 -#define RSCAN0TMC53 RSCAN0.TMC53 -#define RSCAN0TMC54 RSCAN0.TMC54 -#define RSCAN0TMC55 RSCAN0.TMC55 -#define RSCAN0TMC56 RSCAN0.TMC56 -#define RSCAN0TMC57 RSCAN0.TMC57 -#define RSCAN0TMC58 RSCAN0.TMC58 -#define RSCAN0TMC59 RSCAN0.TMC59 -#define RSCAN0TMC60 RSCAN0.TMC60 -#define RSCAN0TMC61 RSCAN0.TMC61 -#define RSCAN0TMC62 RSCAN0.TMC62 -#define RSCAN0TMC63 RSCAN0.TMC63 -#define RSCAN0TMC64 RSCAN0.TMC64 -#define RSCAN0TMC65 RSCAN0.TMC65 -#define RSCAN0TMC66 RSCAN0.TMC66 -#define RSCAN0TMC67 RSCAN0.TMC67 -#define RSCAN0TMC68 RSCAN0.TMC68 -#define RSCAN0TMC69 RSCAN0.TMC69 -#define RSCAN0TMC70 RSCAN0.TMC70 -#define RSCAN0TMC71 RSCAN0.TMC71 -#define RSCAN0TMC72 RSCAN0.TMC72 -#define RSCAN0TMC73 RSCAN0.TMC73 -#define RSCAN0TMC74 RSCAN0.TMC74 -#define RSCAN0TMC75 RSCAN0.TMC75 -#define RSCAN0TMC76 RSCAN0.TMC76 -#define RSCAN0TMC77 RSCAN0.TMC77 -#define RSCAN0TMC78 RSCAN0.TMC78 -#define RSCAN0TMC79 RSCAN0.TMC79 -#define RSCAN0TMSTS0 RSCAN0.TMSTS0 -#define RSCAN0TMSTS1 RSCAN0.TMSTS1 -#define RSCAN0TMSTS2 RSCAN0.TMSTS2 -#define RSCAN0TMSTS3 RSCAN0.TMSTS3 -#define RSCAN0TMSTS4 RSCAN0.TMSTS4 -#define RSCAN0TMSTS5 RSCAN0.TMSTS5 -#define RSCAN0TMSTS6 RSCAN0.TMSTS6 -#define RSCAN0TMSTS7 RSCAN0.TMSTS7 -#define RSCAN0TMSTS8 RSCAN0.TMSTS8 -#define RSCAN0TMSTS9 RSCAN0.TMSTS9 -#define RSCAN0TMSTS10 RSCAN0.TMSTS10 -#define RSCAN0TMSTS11 RSCAN0.TMSTS11 -#define RSCAN0TMSTS12 RSCAN0.TMSTS12 -#define RSCAN0TMSTS13 RSCAN0.TMSTS13 -#define RSCAN0TMSTS14 RSCAN0.TMSTS14 -#define RSCAN0TMSTS15 RSCAN0.TMSTS15 -#define RSCAN0TMSTS16 RSCAN0.TMSTS16 -#define RSCAN0TMSTS17 RSCAN0.TMSTS17 -#define RSCAN0TMSTS18 RSCAN0.TMSTS18 -#define RSCAN0TMSTS19 RSCAN0.TMSTS19 -#define RSCAN0TMSTS20 RSCAN0.TMSTS20 -#define RSCAN0TMSTS21 RSCAN0.TMSTS21 -#define RSCAN0TMSTS22 RSCAN0.TMSTS22 -#define RSCAN0TMSTS23 RSCAN0.TMSTS23 -#define RSCAN0TMSTS24 RSCAN0.TMSTS24 -#define RSCAN0TMSTS25 RSCAN0.TMSTS25 -#define RSCAN0TMSTS26 RSCAN0.TMSTS26 -#define RSCAN0TMSTS27 RSCAN0.TMSTS27 -#define RSCAN0TMSTS28 RSCAN0.TMSTS28 -#define RSCAN0TMSTS29 RSCAN0.TMSTS29 -#define RSCAN0TMSTS30 RSCAN0.TMSTS30 -#define RSCAN0TMSTS31 RSCAN0.TMSTS31 -#define RSCAN0TMSTS32 RSCAN0.TMSTS32 -#define RSCAN0TMSTS33 RSCAN0.TMSTS33 -#define RSCAN0TMSTS34 RSCAN0.TMSTS34 -#define RSCAN0TMSTS35 RSCAN0.TMSTS35 -#define RSCAN0TMSTS36 RSCAN0.TMSTS36 -#define RSCAN0TMSTS37 RSCAN0.TMSTS37 -#define RSCAN0TMSTS38 RSCAN0.TMSTS38 -#define RSCAN0TMSTS39 RSCAN0.TMSTS39 -#define RSCAN0TMSTS40 RSCAN0.TMSTS40 -#define RSCAN0TMSTS41 RSCAN0.TMSTS41 -#define RSCAN0TMSTS42 RSCAN0.TMSTS42 -#define RSCAN0TMSTS43 RSCAN0.TMSTS43 -#define RSCAN0TMSTS44 RSCAN0.TMSTS44 -#define RSCAN0TMSTS45 RSCAN0.TMSTS45 -#define RSCAN0TMSTS46 RSCAN0.TMSTS46 -#define RSCAN0TMSTS47 RSCAN0.TMSTS47 -#define RSCAN0TMSTS48 RSCAN0.TMSTS48 -#define RSCAN0TMSTS49 RSCAN0.TMSTS49 -#define RSCAN0TMSTS50 RSCAN0.TMSTS50 -#define RSCAN0TMSTS51 RSCAN0.TMSTS51 -#define RSCAN0TMSTS52 RSCAN0.TMSTS52 -#define RSCAN0TMSTS53 RSCAN0.TMSTS53 -#define RSCAN0TMSTS54 RSCAN0.TMSTS54 -#define RSCAN0TMSTS55 RSCAN0.TMSTS55 -#define RSCAN0TMSTS56 RSCAN0.TMSTS56 -#define RSCAN0TMSTS57 RSCAN0.TMSTS57 -#define RSCAN0TMSTS58 RSCAN0.TMSTS58 -#define RSCAN0TMSTS59 RSCAN0.TMSTS59 -#define RSCAN0TMSTS60 RSCAN0.TMSTS60 -#define RSCAN0TMSTS61 RSCAN0.TMSTS61 -#define RSCAN0TMSTS62 RSCAN0.TMSTS62 -#define RSCAN0TMSTS63 RSCAN0.TMSTS63 -#define RSCAN0TMSTS64 RSCAN0.TMSTS64 -#define RSCAN0TMSTS65 RSCAN0.TMSTS65 -#define RSCAN0TMSTS66 RSCAN0.TMSTS66 -#define RSCAN0TMSTS67 RSCAN0.TMSTS67 -#define RSCAN0TMSTS68 RSCAN0.TMSTS68 -#define RSCAN0TMSTS69 RSCAN0.TMSTS69 -#define RSCAN0TMSTS70 RSCAN0.TMSTS70 -#define RSCAN0TMSTS71 RSCAN0.TMSTS71 -#define RSCAN0TMSTS72 RSCAN0.TMSTS72 -#define RSCAN0TMSTS73 RSCAN0.TMSTS73 -#define RSCAN0TMSTS74 RSCAN0.TMSTS74 -#define RSCAN0TMSTS75 RSCAN0.TMSTS75 -#define RSCAN0TMSTS76 RSCAN0.TMSTS76 -#define RSCAN0TMSTS77 RSCAN0.TMSTS77 -#define RSCAN0TMSTS78 RSCAN0.TMSTS78 -#define RSCAN0TMSTS79 RSCAN0.TMSTS79 -#define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32 -#define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L] -#define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL] -#define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH] -#define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H] -#define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL] -#define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH] -#define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32 -#define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L] -#define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL] -#define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH] -#define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H] -#define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL] -#define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH] -#define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32 -#define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L] -#define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL] -#define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH] -#define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H] -#define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL] -#define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH] -#define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32 -#define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L] -#define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL] -#define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH] -#define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H] -#define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL] -#define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH] -#define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32 -#define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L] -#define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL] -#define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH] -#define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H] -#define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL] -#define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH] -#define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32 -#define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L] -#define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL] -#define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH] -#define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H] -#define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL] -#define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH] -#define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32 -#define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L] -#define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL] -#define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH] -#define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H] -#define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL] -#define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH] -#define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32 -#define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L] -#define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL] -#define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH] -#define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H] -#define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL] -#define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH] -#define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32 -#define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L] -#define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL] -#define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH] -#define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H] -#define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL] -#define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH] -#define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32 -#define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L] -#define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL] -#define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH] -#define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H] -#define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL] -#define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH] -#define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32 -#define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L] -#define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL] -#define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH] -#define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H] -#define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL] -#define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH] -#define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32 -#define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L] -#define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL] -#define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH] -#define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H] -#define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL] -#define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH] -#define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32 -#define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L] -#define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL] -#define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH] -#define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H] -#define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL] -#define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH] -#define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32 -#define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L] -#define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL] -#define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH] -#define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H] -#define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL] -#define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH] -#define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32 -#define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L] -#define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL] -#define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH] -#define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H] -#define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL] -#define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH] -#define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32 -#define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L] -#define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL] -#define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH] -#define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H] -#define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL] -#define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH] -#define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32 -#define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L] -#define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL] -#define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH] -#define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H] -#define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL] -#define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH] -#define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32 -#define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L] -#define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL] -#define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH] -#define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H] -#define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL] -#define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH] -#define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32 -#define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L] -#define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL] -#define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH] -#define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H] -#define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL] -#define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH] -#define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32 -#define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L] -#define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL] -#define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH] -#define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H] -#define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL] -#define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH] -#define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32 -#define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L] -#define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL] -#define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH] -#define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H] -#define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL] -#define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH] -#define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32 -#define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L] -#define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL] -#define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH] -#define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H] -#define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL] -#define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH] -#define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32 -#define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L] -#define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL] -#define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH] -#define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H] -#define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL] -#define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH] -#define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32 -#define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L] -#define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL] -#define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH] -#define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H] -#define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL] -#define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH] -#define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32 -#define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L] -#define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL] -#define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH] -#define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H] -#define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL] -#define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH] -#define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32 -#define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L] -#define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL] -#define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH] -#define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H] -#define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL] -#define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH] -#define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32 -#define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L] -#define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL] -#define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH] -#define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H] -#define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL] -#define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH] -#define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32 -#define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L] -#define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL] -#define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH] -#define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H] -#define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL] -#define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH] -#define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32 -#define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L] -#define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL] -#define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH] -#define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H] -#define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL] -#define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH] -#define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32 -#define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L] -#define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL] -#define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH] -#define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H] -#define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL] -#define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH] -#define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32 -#define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L] -#define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL] -#define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH] -#define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H] -#define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL] -#define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH] -#define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32 -#define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L] -#define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL] -#define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH] -#define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H] -#define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL] -#define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH] -#define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32 -#define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L] -#define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL] -#define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH] -#define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H] -#define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL] -#define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH] -#define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32 -#define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L] -#define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL] -#define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH] -#define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H] -#define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL] -#define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH] -#define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32 -#define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L] -#define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL] -#define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH] -#define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H] -#define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL] -#define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH] -#define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32 -#define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L] -#define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL] -#define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH] -#define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H] -#define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL] -#define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH] -#define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32 -#define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L] -#define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL] -#define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH] -#define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H] -#define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL] -#define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH] -#define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32 -#define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L] -#define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL] -#define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH] -#define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H] -#define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL] -#define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH] -#define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32 -#define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L] -#define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL] -#define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH] -#define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H] -#define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL] -#define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH] -#define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32 -#define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L] -#define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL] -#define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH] -#define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H] -#define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL] -#define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH] -#define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32 -#define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L] -#define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL] -#define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH] -#define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H] -#define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL] -#define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH] -#define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32 -#define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L] -#define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL] -#define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH] -#define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H] -#define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL] -#define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH] -#define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32 -#define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L] -#define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL] -#define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH] -#define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H] -#define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL] -#define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH] -#define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32 -#define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L] -#define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL] -#define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH] -#define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H] -#define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL] -#define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH] -#define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32 -#define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L] -#define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL] -#define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH] -#define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H] -#define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL] -#define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH] -#define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32 -#define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L] -#define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL] -#define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH] -#define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H] -#define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL] -#define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH] -#define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32 -#define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L] -#define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL] -#define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH] -#define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H] -#define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL] -#define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH] -#define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32 -#define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L] -#define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL] -#define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH] -#define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H] -#define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL] -#define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH] -#define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32 -#define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L] -#define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL] -#define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH] -#define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H] -#define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL] -#define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH] -#define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32 -#define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L] -#define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H] -#define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32 -#define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L] -#define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL] -#define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH] -#define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H] -#define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL] -#define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH] -#define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32 -#define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L] -#define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL] -#define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH] -#define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H] -#define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL] -#define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH] -#define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32 -#define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L] -#define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL] -#define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH] -#define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H] -#define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL] -#define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH] -#define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32 -#define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L] -#define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL] -#define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH] -#define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H] -#define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL] -#define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH] -#define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32 -#define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L] -#define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL] -#define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH] -#define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H] -#define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL] -#define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH] -#define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32 -#define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L] -#define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL] -#define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH] -#define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H] -#define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL] -#define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH] -#define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32 -#define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L] -#define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL] -#define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH] -#define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H] -#define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL] -#define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH] -#define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32 -#define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L] -#define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL] -#define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH] -#define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H] -#define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL] -#define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH] -#define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32 -#define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L] -#define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL] -#define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH] -#define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H] -#define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL] -#define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH] -#define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32 -#define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L] -#define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL] -#define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH] -#define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H] -#define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL] -#define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH] -#define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32 -#define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L] -#define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL] -#define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH] -#define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H] -#define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL] -#define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH] -#define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32 -#define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L] -#define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL] -#define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH] -#define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H] -#define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL] -#define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH] -#define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32 -#define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L] -#define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL] -#define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH] -#define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H] -#define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL] -#define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH] -#define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32 -#define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L] -#define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL] -#define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH] -#define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H] -#define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL] -#define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH] -#define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32 -#define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L] -#define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL] -#define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH] -#define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H] -#define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL] -#define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH] -#define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32 -#define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L] -#define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL] -#define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH] -#define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H] -#define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL] -#define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH] -#define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32 -#define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L] -#define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL] -#define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH] -#define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H] -#define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL] -#define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH] -#define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32 -#define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L] -#define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL] -#define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH] -#define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H] -#define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL] -#define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH] -#define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32 -#define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L] -#define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL] -#define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH] -#define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H] -#define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL] -#define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH] -#define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32 -#define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L] -#define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL] -#define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH] -#define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H] -#define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL] -#define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH] -#define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32 -#define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L] -#define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL] -#define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH] -#define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H] -#define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL] -#define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH] -#define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32 -#define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L] -#define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL] -#define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH] -#define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H] -#define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL] -#define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH] -#define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32 -#define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L] -#define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL] -#define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH] -#define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H] -#define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL] -#define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH] -#define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32 -#define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L] -#define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL] -#define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH] -#define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H] -#define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL] -#define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH] -#define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32 -#define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L] -#define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL] -#define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH] -#define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H] -#define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL] -#define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH] -#define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32 -#define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L] -#define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL] -#define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH] -#define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H] -#define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL] -#define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH] -#define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32 -#define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L] -#define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL] -#define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH] -#define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H] -#define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL] -#define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH] -#define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32 -#define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L] -#define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL] -#define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH] -#define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H] -#define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL] -#define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH] -#define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32 -#define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L] -#define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL] -#define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH] -#define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H] -#define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL] -#define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH] -#define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32 -#define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L] -#define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL] -#define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH] -#define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H] -#define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL] -#define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH] -#define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32 -#define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L] -#define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL] -#define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH] -#define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H] -#define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL] -#define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH] -#define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32 -#define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L] -#define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL] -#define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH] -#define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H] -#define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL] -#define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH] -#define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32 -#define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L] -#define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL] -#define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH] -#define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H] -#define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL] -#define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH] -#define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32 -#define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L] -#define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL] -#define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH] -#define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H] -#define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL] -#define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH] -#define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32 -#define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L] -#define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL] -#define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH] -#define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H] -#define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL] -#define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH] -#define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32 -#define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L] -#define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL] -#define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH] -#define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H] -#define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL] -#define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH] -#define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32 -#define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L] -#define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL] -#define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH] -#define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H] -#define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL] -#define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH] -#define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32 -#define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L] -#define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL] -#define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH] -#define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H] -#define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL] -#define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH] -#define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32 -#define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L] -#define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL] -#define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH] -#define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H] -#define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL] -#define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH] -#define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32 -#define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L] -#define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL] -#define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH] -#define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H] -#define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL] -#define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH] -#define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32 -#define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L] -#define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL] -#define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH] -#define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H] -#define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL] -#define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH] -#define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32 -#define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L] -#define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL] -#define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH] -#define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H] -#define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL] -#define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH] -#define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32 -#define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L] -#define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL] -#define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH] -#define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H] -#define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL] -#define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH] -#define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32 -#define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L] -#define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL] -#define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH] -#define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H] -#define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL] -#define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH] -#define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32 -#define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L] -#define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL] -#define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH] -#define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H] -#define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL] -#define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH] -#define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32 -#define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L] -#define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL] -#define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH] -#define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H] -#define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL] -#define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH] -#define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32 -#define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L] -#define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL] -#define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH] -#define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H] -#define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL] -#define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH] -#define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32 -#define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L] -#define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL] -#define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH] -#define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H] -#define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL] -#define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH] -#define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32 -#define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L] -#define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL] -#define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH] -#define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H] -#define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL] -#define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH] -#define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32 -#define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L] -#define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL] -#define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH] -#define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H] -#define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL] -#define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH] -#define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32 -#define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L] -#define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL] -#define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH] -#define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H] -#define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL] -#define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH] -#define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32 -#define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L] -#define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL] -#define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH] -#define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H] -#define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL] -#define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH] -#define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32 -#define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L] -#define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL] -#define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH] -#define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H] -#define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL] -#define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH] -#define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32 -#define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L] -#define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL] -#define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH] -#define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H] -#define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL] -#define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH] -#define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32 -#define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L] -#define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL] -#define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH] -#define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H] -#define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL] -#define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH] -#define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32 -#define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L] -#define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL] -#define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH] -#define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H] -#define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL] -#define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH] -#define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32 -#define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L] -#define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL] -#define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH] -#define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H] -#define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL] -#define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH] -#define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32 -#define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L] -#define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL] -#define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH] -#define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H] -#define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL] -#define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH] -#define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32 -#define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L] -#define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL] -#define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH] -#define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H] -#define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL] -#define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH] -#define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32 -#define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L] -#define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL] -#define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH] -#define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H] -#define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL] -#define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH] -#define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32 -#define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L] -#define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL] -#define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH] -#define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H] -#define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL] -#define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH] -#define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32 -#define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L] -#define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL] -#define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH] -#define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H] -#define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL] -#define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH] -#define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32 -#define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L] -#define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL] -#define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH] -#define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H] -#define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL] -#define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH] -#define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32 -#define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L] -#define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL] -#define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH] -#define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H] -#define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL] -#define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH] -#define RSCAN0RMID0 RSCAN0.RMID0.UINT32 -#define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L] -#define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL] -#define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH] -#define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H] -#define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL] -#define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH] -#define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32 -#define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L] -#define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL] -#define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH] -#define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H] -#define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL] -#define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH] -#define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32 -#define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L] -#define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL] -#define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH] -#define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H] -#define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL] -#define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH] -#define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32 -#define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L] -#define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL] -#define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH] -#define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H] -#define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL] -#define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH] -#define RSCAN0RMID1 RSCAN0.RMID1.UINT32 -#define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L] -#define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL] -#define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH] -#define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H] -#define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL] -#define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH] -#define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32 -#define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L] -#define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL] -#define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH] -#define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H] -#define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL] -#define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH] -#define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32 -#define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L] -#define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL] -#define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH] -#define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H] -#define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL] -#define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH] -#define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32 -#define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L] -#define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL] -#define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH] -#define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H] -#define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL] -#define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH] -#define RSCAN0RMID2 RSCAN0.RMID2.UINT32 -#define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L] -#define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL] -#define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH] -#define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H] -#define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL] -#define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH] -#define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32 -#define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L] -#define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL] -#define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH] -#define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H] -#define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL] -#define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH] -#define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32 -#define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L] -#define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL] -#define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH] -#define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H] -#define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL] -#define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH] -#define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32 -#define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L] -#define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL] -#define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH] -#define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H] -#define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL] -#define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH] -#define RSCAN0RMID3 RSCAN0.RMID3.UINT32 -#define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L] -#define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL] -#define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH] -#define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H] -#define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL] -#define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH] -#define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32 -#define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L] -#define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL] -#define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH] -#define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H] -#define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL] -#define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH] -#define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32 -#define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L] -#define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL] -#define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH] -#define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H] -#define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL] -#define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH] -#define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32 -#define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L] -#define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL] -#define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH] -#define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H] -#define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL] -#define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH] -#define RSCAN0RMID4 RSCAN0.RMID4.UINT32 -#define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L] -#define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL] -#define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH] -#define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H] -#define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL] -#define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH] -#define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32 -#define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L] -#define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL] -#define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH] -#define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H] -#define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL] -#define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH] -#define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32 -#define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L] -#define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL] -#define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH] -#define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H] -#define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL] -#define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH] -#define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32 -#define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L] -#define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL] -#define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH] -#define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H] -#define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL] -#define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH] -#define RSCAN0RMID5 RSCAN0.RMID5.UINT32 -#define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L] -#define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL] -#define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH] -#define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H] -#define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL] -#define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH] -#define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32 -#define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L] -#define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL] -#define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH] -#define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H] -#define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL] -#define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH] -#define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32 -#define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L] -#define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL] -#define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH] -#define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H] -#define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL] -#define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH] -#define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32 -#define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L] -#define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL] -#define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH] -#define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H] -#define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL] -#define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH] -#define RSCAN0RMID6 RSCAN0.RMID6.UINT32 -#define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L] -#define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL] -#define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH] -#define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H] -#define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL] -#define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH] -#define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32 -#define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L] -#define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL] -#define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH] -#define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H] -#define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL] -#define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH] -#define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32 -#define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L] -#define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL] -#define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH] -#define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H] -#define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL] -#define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH] -#define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32 -#define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L] -#define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL] -#define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH] -#define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H] -#define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL] -#define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH] -#define RSCAN0RMID7 RSCAN0.RMID7.UINT32 -#define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L] -#define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL] -#define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH] -#define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H] -#define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL] -#define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH] -#define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32 -#define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L] -#define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL] -#define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH] -#define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H] -#define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL] -#define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH] -#define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32 -#define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L] -#define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL] -#define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH] -#define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H] -#define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL] -#define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH] -#define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32 -#define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L] -#define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL] -#define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH] -#define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H] -#define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL] -#define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH] -#define RSCAN0RMID8 RSCAN0.RMID8.UINT32 -#define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L] -#define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL] -#define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH] -#define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H] -#define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL] -#define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH] -#define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32 -#define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L] -#define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL] -#define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH] -#define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H] -#define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL] -#define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH] -#define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32 -#define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L] -#define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL] -#define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH] -#define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H] -#define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL] -#define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH] -#define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32 -#define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L] -#define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL] -#define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH] -#define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H] -#define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL] -#define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH] -#define RSCAN0RMID9 RSCAN0.RMID9.UINT32 -#define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L] -#define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL] -#define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH] -#define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H] -#define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL] -#define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH] -#define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32 -#define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L] -#define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL] -#define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH] -#define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H] -#define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL] -#define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH] -#define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32 -#define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L] -#define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL] -#define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH] -#define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H] -#define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL] -#define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH] -#define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32 -#define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L] -#define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL] -#define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH] -#define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H] -#define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL] -#define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH] -#define RSCAN0RMID10 RSCAN0.RMID10.UINT32 -#define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L] -#define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL] -#define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH] -#define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H] -#define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL] -#define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH] -#define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32 -#define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L] -#define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL] -#define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH] -#define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H] -#define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL] -#define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH] -#define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32 -#define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L] -#define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL] -#define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH] -#define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H] -#define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL] -#define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH] -#define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32 -#define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L] -#define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL] -#define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH] -#define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H] -#define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL] -#define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH] -#define RSCAN0RMID11 RSCAN0.RMID11.UINT32 -#define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L] -#define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL] -#define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH] -#define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H] -#define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL] -#define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH] -#define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32 -#define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L] -#define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL] -#define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH] -#define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H] -#define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL] -#define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH] -#define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32 -#define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L] -#define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL] -#define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH] -#define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H] -#define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL] -#define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH] -#define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32 -#define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L] -#define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL] -#define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH] -#define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H] -#define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL] -#define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH] -#define RSCAN0RMID12 RSCAN0.RMID12.UINT32 -#define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L] -#define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL] -#define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH] -#define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H] -#define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL] -#define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH] -#define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32 -#define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L] -#define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL] -#define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH] -#define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H] -#define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL] -#define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH] -#define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32 -#define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L] -#define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL] -#define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH] -#define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H] -#define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL] -#define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH] -#define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32 -#define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L] -#define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL] -#define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH] -#define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H] -#define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL] -#define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH] -#define RSCAN0RMID13 RSCAN0.RMID13.UINT32 -#define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L] -#define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL] -#define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH] -#define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H] -#define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL] -#define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH] -#define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32 -#define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L] -#define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL] -#define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH] -#define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H] -#define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL] -#define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH] -#define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32 -#define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L] -#define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL] -#define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH] -#define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H] -#define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL] -#define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH] -#define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32 -#define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L] -#define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL] -#define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH] -#define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H] -#define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL] -#define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH] -#define RSCAN0RMID14 RSCAN0.RMID14.UINT32 -#define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L] -#define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL] -#define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH] -#define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H] -#define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL] -#define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH] -#define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32 -#define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L] -#define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL] -#define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH] -#define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H] -#define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL] -#define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH] -#define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32 -#define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L] -#define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL] -#define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH] -#define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H] -#define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL] -#define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH] -#define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32 -#define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L] -#define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL] -#define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH] -#define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H] -#define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL] -#define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH] -#define RSCAN0RMID15 RSCAN0.RMID15.UINT32 -#define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L] -#define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL] -#define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH] -#define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H] -#define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL] -#define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH] -#define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32 -#define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L] -#define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL] -#define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH] -#define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H] -#define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL] -#define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH] -#define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32 -#define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L] -#define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL] -#define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH] -#define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H] -#define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL] -#define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH] -#define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32 -#define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L] -#define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL] -#define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH] -#define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H] -#define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL] -#define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH] -#define RSCAN0RMID16 RSCAN0.RMID16.UINT32 -#define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L] -#define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL] -#define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH] -#define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H] -#define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL] -#define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH] -#define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32 -#define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L] -#define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL] -#define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH] -#define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H] -#define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL] -#define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH] -#define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32 -#define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L] -#define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL] -#define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH] -#define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H] -#define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL] -#define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH] -#define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32 -#define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L] -#define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL] -#define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH] -#define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H] -#define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL] -#define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH] -#define RSCAN0RMID17 RSCAN0.RMID17.UINT32 -#define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L] -#define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL] -#define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH] -#define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H] -#define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL] -#define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH] -#define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32 -#define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L] -#define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL] -#define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH] -#define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H] -#define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL] -#define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH] -#define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32 -#define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L] -#define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL] -#define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH] -#define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H] -#define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL] -#define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH] -#define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32 -#define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L] -#define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL] -#define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH] -#define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H] -#define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL] -#define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH] -#define RSCAN0RMID18 RSCAN0.RMID18.UINT32 -#define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L] -#define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL] -#define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH] -#define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H] -#define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL] -#define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH] -#define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32 -#define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L] -#define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL] -#define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH] -#define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H] -#define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL] -#define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH] -#define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32 -#define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L] -#define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL] -#define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH] -#define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H] -#define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL] -#define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH] -#define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32 -#define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L] -#define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL] -#define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH] -#define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H] -#define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL] -#define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH] -#define RSCAN0RMID19 RSCAN0.RMID19.UINT32 -#define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L] -#define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL] -#define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH] -#define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H] -#define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL] -#define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH] -#define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32 -#define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L] -#define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL] -#define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH] -#define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H] -#define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL] -#define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH] -#define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32 -#define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L] -#define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL] -#define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH] -#define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H] -#define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL] -#define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH] -#define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32 -#define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L] -#define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL] -#define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH] -#define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H] -#define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL] -#define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH] -#define RSCAN0RMID20 RSCAN0.RMID20.UINT32 -#define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L] -#define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL] -#define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH] -#define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H] -#define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL] -#define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH] -#define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32 -#define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L] -#define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL] -#define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH] -#define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H] -#define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL] -#define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH] -#define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32 -#define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L] -#define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL] -#define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH] -#define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H] -#define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL] -#define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH] -#define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32 -#define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L] -#define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL] -#define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH] -#define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H] -#define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL] -#define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH] -#define RSCAN0RMID21 RSCAN0.RMID21.UINT32 -#define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L] -#define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL] -#define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH] -#define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H] -#define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL] -#define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH] -#define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32 -#define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L] -#define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL] -#define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH] -#define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H] -#define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL] -#define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH] -#define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32 -#define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L] -#define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL] -#define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH] -#define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H] -#define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL] -#define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH] -#define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32 -#define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L] -#define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL] -#define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH] -#define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H] -#define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL] -#define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH] -#define RSCAN0RMID22 RSCAN0.RMID22.UINT32 -#define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L] -#define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL] -#define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH] -#define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H] -#define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL] -#define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH] -#define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32 -#define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L] -#define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL] -#define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH] -#define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H] -#define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL] -#define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH] -#define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32 -#define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L] -#define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL] -#define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH] -#define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H] -#define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL] -#define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH] -#define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32 -#define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L] -#define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL] -#define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH] -#define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H] -#define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL] -#define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH] -#define RSCAN0RMID23 RSCAN0.RMID23.UINT32 -#define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L] -#define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL] -#define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH] -#define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H] -#define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL] -#define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH] -#define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32 -#define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L] -#define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL] -#define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH] -#define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H] -#define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL] -#define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH] -#define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32 -#define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L] -#define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL] -#define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH] -#define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H] -#define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL] -#define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH] -#define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32 -#define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L] -#define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL] -#define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH] -#define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H] -#define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL] -#define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH] -#define RSCAN0RMID24 RSCAN0.RMID24.UINT32 -#define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L] -#define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL] -#define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH] -#define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H] -#define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL] -#define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH] -#define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32 -#define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L] -#define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL] -#define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH] -#define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H] -#define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL] -#define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH] -#define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32 -#define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L] -#define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL] -#define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH] -#define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H] -#define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL] -#define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH] -#define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32 -#define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L] -#define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL] -#define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH] -#define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H] -#define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL] -#define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH] -#define RSCAN0RMID25 RSCAN0.RMID25.UINT32 -#define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L] -#define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL] -#define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH] -#define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H] -#define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL] -#define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH] -#define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32 -#define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L] -#define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL] -#define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH] -#define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H] -#define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL] -#define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH] -#define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32 -#define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L] -#define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL] -#define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH] -#define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H] -#define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL] -#define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH] -#define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32 -#define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L] -#define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL] -#define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH] -#define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H] -#define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL] -#define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH] -#define RSCAN0RMID26 RSCAN0.RMID26.UINT32 -#define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L] -#define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL] -#define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH] -#define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H] -#define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL] -#define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH] -#define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32 -#define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L] -#define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL] -#define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH] -#define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H] -#define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL] -#define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH] -#define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32 -#define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L] -#define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL] -#define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH] -#define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H] -#define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL] -#define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH] -#define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32 -#define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L] -#define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL] -#define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH] -#define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H] -#define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL] -#define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH] -#define RSCAN0RMID27 RSCAN0.RMID27.UINT32 -#define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L] -#define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL] -#define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH] -#define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H] -#define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL] -#define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH] -#define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32 -#define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L] -#define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL] -#define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH] -#define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H] -#define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL] -#define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH] -#define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32 -#define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L] -#define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL] -#define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH] -#define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H] -#define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL] -#define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH] -#define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32 -#define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L] -#define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL] -#define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH] -#define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H] -#define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL] -#define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH] -#define RSCAN0RMID28 RSCAN0.RMID28.UINT32 -#define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L] -#define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL] -#define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH] -#define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H] -#define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL] -#define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH] -#define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32 -#define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L] -#define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL] -#define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH] -#define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H] -#define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL] -#define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH] -#define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32 -#define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L] -#define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL] -#define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH] -#define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H] -#define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL] -#define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH] -#define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32 -#define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L] -#define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL] -#define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH] -#define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H] -#define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL] -#define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH] -#define RSCAN0RMID29 RSCAN0.RMID29.UINT32 -#define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L] -#define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL] -#define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH] -#define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H] -#define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL] -#define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH] -#define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32 -#define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L] -#define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL] -#define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH] -#define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H] -#define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL] -#define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH] -#define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32 -#define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L] -#define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL] -#define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH] -#define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H] -#define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL] -#define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH] -#define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32 -#define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L] -#define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL] -#define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH] -#define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H] -#define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL] -#define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH] -#define RSCAN0RMID30 RSCAN0.RMID30.UINT32 -#define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L] -#define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL] -#define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH] -#define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H] -#define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL] -#define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH] -#define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32 -#define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L] -#define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL] -#define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH] -#define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H] -#define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL] -#define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH] -#define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32 -#define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L] -#define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL] -#define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH] -#define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H] -#define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL] -#define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH] -#define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32 -#define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L] -#define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL] -#define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH] -#define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H] -#define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL] -#define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH] -#define RSCAN0RMID31 RSCAN0.RMID31.UINT32 -#define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L] -#define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL] -#define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH] -#define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H] -#define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL] -#define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH] -#define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32 -#define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L] -#define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL] -#define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH] -#define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H] -#define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL] -#define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH] -#define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32 -#define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L] -#define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL] -#define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH] -#define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H] -#define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL] -#define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH] -#define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32 -#define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L] -#define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL] -#define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH] -#define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H] -#define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL] -#define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH] -#define RSCAN0RMID32 RSCAN0.RMID32.UINT32 -#define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L] -#define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL] -#define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH] -#define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H] -#define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL] -#define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH] -#define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32 -#define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L] -#define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL] -#define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH] -#define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H] -#define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL] -#define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH] -#define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32 -#define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L] -#define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL] -#define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH] -#define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H] -#define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL] -#define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH] -#define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32 -#define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L] -#define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL] -#define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH] -#define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H] -#define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL] -#define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH] -#define RSCAN0RMID33 RSCAN0.RMID33.UINT32 -#define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L] -#define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL] -#define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH] -#define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H] -#define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL] -#define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH] -#define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32 -#define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L] -#define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL] -#define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH] -#define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H] -#define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL] -#define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH] -#define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32 -#define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L] -#define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL] -#define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH] -#define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H] -#define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL] -#define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH] -#define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32 -#define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L] -#define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL] -#define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH] -#define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H] -#define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL] -#define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH] -#define RSCAN0RMID34 RSCAN0.RMID34.UINT32 -#define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L] -#define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL] -#define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH] -#define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H] -#define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL] -#define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH] -#define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32 -#define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L] -#define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL] -#define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH] -#define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H] -#define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL] -#define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH] -#define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32 -#define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L] -#define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL] -#define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH] -#define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H] -#define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL] -#define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH] -#define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32 -#define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L] -#define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL] -#define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH] -#define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H] -#define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL] -#define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH] -#define RSCAN0RMID35 RSCAN0.RMID35.UINT32 -#define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L] -#define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL] -#define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH] -#define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H] -#define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL] -#define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH] -#define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32 -#define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L] -#define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL] -#define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH] -#define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H] -#define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL] -#define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH] -#define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32 -#define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L] -#define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL] -#define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH] -#define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H] -#define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL] -#define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH] -#define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32 -#define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L] -#define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL] -#define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH] -#define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H] -#define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL] -#define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH] -#define RSCAN0RMID36 RSCAN0.RMID36.UINT32 -#define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L] -#define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL] -#define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH] -#define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H] -#define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL] -#define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH] -#define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32 -#define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L] -#define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL] -#define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH] -#define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H] -#define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL] -#define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH] -#define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32 -#define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L] -#define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL] -#define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH] -#define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H] -#define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL] -#define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH] -#define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32 -#define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L] -#define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL] -#define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH] -#define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H] -#define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL] -#define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH] -#define RSCAN0RMID37 RSCAN0.RMID37.UINT32 -#define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L] -#define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL] -#define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH] -#define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H] -#define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL] -#define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH] -#define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32 -#define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L] -#define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL] -#define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH] -#define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H] -#define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL] -#define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH] -#define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32 -#define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L] -#define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL] -#define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH] -#define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H] -#define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL] -#define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH] -#define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32 -#define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L] -#define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL] -#define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH] -#define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H] -#define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL] -#define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH] -#define RSCAN0RMID38 RSCAN0.RMID38.UINT32 -#define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L] -#define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL] -#define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH] -#define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H] -#define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL] -#define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH] -#define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32 -#define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L] -#define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL] -#define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH] -#define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H] -#define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL] -#define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH] -#define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32 -#define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L] -#define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL] -#define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH] -#define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H] -#define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL] -#define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH] -#define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32 -#define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L] -#define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL] -#define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH] -#define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H] -#define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL] -#define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH] -#define RSCAN0RMID39 RSCAN0.RMID39.UINT32 -#define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L] -#define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL] -#define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH] -#define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H] -#define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL] -#define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH] -#define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32 -#define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L] -#define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL] -#define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH] -#define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H] -#define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL] -#define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH] -#define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32 -#define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L] -#define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL] -#define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH] -#define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H] -#define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL] -#define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH] -#define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32 -#define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L] -#define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL] -#define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH] -#define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H] -#define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL] -#define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH] -#define RSCAN0RMID40 RSCAN0.RMID40.UINT32 -#define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L] -#define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL] -#define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH] -#define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H] -#define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL] -#define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH] -#define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32 -#define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L] -#define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL] -#define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH] -#define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H] -#define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL] -#define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH] -#define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32 -#define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L] -#define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL] -#define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH] -#define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H] -#define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL] -#define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH] -#define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32 -#define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L] -#define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL] -#define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH] -#define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H] -#define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL] -#define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH] -#define RSCAN0RMID41 RSCAN0.RMID41.UINT32 -#define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L] -#define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL] -#define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH] -#define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H] -#define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL] -#define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH] -#define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32 -#define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L] -#define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL] -#define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH] -#define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H] -#define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL] -#define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH] -#define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32 -#define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L] -#define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL] -#define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH] -#define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H] -#define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL] -#define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH] -#define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32 -#define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L] -#define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL] -#define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH] -#define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H] -#define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL] -#define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH] -#define RSCAN0RMID42 RSCAN0.RMID42.UINT32 -#define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L] -#define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL] -#define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH] -#define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H] -#define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL] -#define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH] -#define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32 -#define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L] -#define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL] -#define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH] -#define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H] -#define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL] -#define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH] -#define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32 -#define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L] -#define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL] -#define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH] -#define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H] -#define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL] -#define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH] -#define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32 -#define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L] -#define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL] -#define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH] -#define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H] -#define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL] -#define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH] -#define RSCAN0RMID43 RSCAN0.RMID43.UINT32 -#define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L] -#define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL] -#define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH] -#define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H] -#define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL] -#define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH] -#define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32 -#define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L] -#define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL] -#define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH] -#define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H] -#define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL] -#define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH] -#define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32 -#define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L] -#define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL] -#define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH] -#define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H] -#define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL] -#define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH] -#define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32 -#define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L] -#define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL] -#define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH] -#define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H] -#define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL] -#define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH] -#define RSCAN0RMID44 RSCAN0.RMID44.UINT32 -#define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L] -#define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL] -#define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH] -#define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H] -#define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL] -#define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH] -#define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32 -#define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L] -#define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL] -#define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH] -#define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H] -#define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL] -#define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH] -#define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32 -#define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L] -#define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL] -#define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH] -#define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H] -#define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL] -#define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH] -#define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32 -#define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L] -#define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL] -#define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH] -#define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H] -#define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL] -#define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH] -#define RSCAN0RMID45 RSCAN0.RMID45.UINT32 -#define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L] -#define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL] -#define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH] -#define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H] -#define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL] -#define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH] -#define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32 -#define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L] -#define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL] -#define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH] -#define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H] -#define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL] -#define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH] -#define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32 -#define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L] -#define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL] -#define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH] -#define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H] -#define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL] -#define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH] -#define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32 -#define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L] -#define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL] -#define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH] -#define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H] -#define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL] -#define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH] -#define RSCAN0RMID46 RSCAN0.RMID46.UINT32 -#define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L] -#define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL] -#define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH] -#define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H] -#define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL] -#define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH] -#define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32 -#define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L] -#define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL] -#define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH] -#define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H] -#define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL] -#define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH] -#define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32 -#define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L] -#define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL] -#define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH] -#define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H] -#define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL] -#define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH] -#define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32 -#define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L] -#define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL] -#define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH] -#define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H] -#define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL] -#define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH] -#define RSCAN0RMID47 RSCAN0.RMID47.UINT32 -#define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L] -#define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL] -#define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH] -#define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H] -#define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL] -#define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH] -#define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32 -#define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L] -#define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL] -#define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH] -#define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H] -#define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL] -#define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH] -#define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32 -#define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L] -#define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL] -#define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH] -#define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H] -#define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL] -#define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH] -#define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32 -#define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L] -#define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL] -#define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH] -#define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H] -#define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL] -#define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH] -#define RSCAN0RMID48 RSCAN0.RMID48.UINT32 -#define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L] -#define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL] -#define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH] -#define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H] -#define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL] -#define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH] -#define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32 -#define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L] -#define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL] -#define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH] -#define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H] -#define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL] -#define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH] -#define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32 -#define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L] -#define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL] -#define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH] -#define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H] -#define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL] -#define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH] -#define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32 -#define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L] -#define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL] -#define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH] -#define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H] -#define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL] -#define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH] -#define RSCAN0RMID49 RSCAN0.RMID49.UINT32 -#define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L] -#define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL] -#define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH] -#define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H] -#define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL] -#define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH] -#define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32 -#define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L] -#define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL] -#define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH] -#define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H] -#define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL] -#define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH] -#define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32 -#define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L] -#define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL] -#define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH] -#define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H] -#define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL] -#define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH] -#define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32 -#define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L] -#define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL] -#define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH] -#define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H] -#define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL] -#define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH] -#define RSCAN0RMID50 RSCAN0.RMID50.UINT32 -#define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L] -#define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL] -#define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH] -#define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H] -#define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL] -#define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH] -#define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32 -#define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L] -#define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL] -#define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH] -#define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H] -#define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL] -#define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH] -#define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32 -#define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L] -#define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL] -#define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH] -#define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H] -#define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL] -#define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH] -#define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32 -#define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L] -#define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL] -#define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH] -#define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H] -#define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL] -#define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH] -#define RSCAN0RMID51 RSCAN0.RMID51.UINT32 -#define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L] -#define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL] -#define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH] -#define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H] -#define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL] -#define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH] -#define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32 -#define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L] -#define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL] -#define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH] -#define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H] -#define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL] -#define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH] -#define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32 -#define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L] -#define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL] -#define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH] -#define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H] -#define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL] -#define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH] -#define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32 -#define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L] -#define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL] -#define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH] -#define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H] -#define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL] -#define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH] -#define RSCAN0RMID52 RSCAN0.RMID52.UINT32 -#define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L] -#define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL] -#define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH] -#define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H] -#define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL] -#define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH] -#define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32 -#define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L] -#define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL] -#define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH] -#define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H] -#define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL] -#define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH] -#define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32 -#define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L] -#define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL] -#define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH] -#define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H] -#define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL] -#define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH] -#define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32 -#define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L] -#define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL] -#define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH] -#define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H] -#define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL] -#define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH] -#define RSCAN0RMID53 RSCAN0.RMID53.UINT32 -#define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L] -#define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL] -#define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH] -#define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H] -#define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL] -#define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH] -#define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32 -#define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L] -#define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL] -#define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH] -#define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H] -#define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL] -#define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH] -#define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32 -#define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L] -#define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL] -#define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH] -#define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H] -#define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL] -#define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH] -#define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32 -#define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L] -#define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL] -#define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH] -#define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H] -#define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL] -#define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH] -#define RSCAN0RMID54 RSCAN0.RMID54.UINT32 -#define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L] -#define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL] -#define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH] -#define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H] -#define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL] -#define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH] -#define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32 -#define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L] -#define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL] -#define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH] -#define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H] -#define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL] -#define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH] -#define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32 -#define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L] -#define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL] -#define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH] -#define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H] -#define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL] -#define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH] -#define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32 -#define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L] -#define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL] -#define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH] -#define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H] -#define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL] -#define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH] -#define RSCAN0RMID55 RSCAN0.RMID55.UINT32 -#define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L] -#define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL] -#define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH] -#define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H] -#define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL] -#define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH] -#define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32 -#define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L] -#define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL] -#define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH] -#define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H] -#define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL] -#define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH] -#define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32 -#define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L] -#define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL] -#define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH] -#define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H] -#define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL] -#define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH] -#define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32 -#define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L] -#define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL] -#define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH] -#define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H] -#define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL] -#define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH] -#define RSCAN0RMID56 RSCAN0.RMID56.UINT32 -#define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L] -#define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL] -#define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH] -#define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H] -#define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL] -#define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH] -#define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32 -#define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L] -#define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL] -#define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH] -#define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H] -#define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL] -#define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH] -#define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32 -#define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L] -#define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL] -#define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH] -#define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H] -#define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL] -#define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH] -#define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32 -#define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L] -#define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL] -#define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH] -#define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H] -#define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL] -#define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH] -#define RSCAN0RMID57 RSCAN0.RMID57.UINT32 -#define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L] -#define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL] -#define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH] -#define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H] -#define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL] -#define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH] -#define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32 -#define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L] -#define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL] -#define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH] -#define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H] -#define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL] -#define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH] -#define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32 -#define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L] -#define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL] -#define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH] -#define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H] -#define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL] -#define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH] -#define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32 -#define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L] -#define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL] -#define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH] -#define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H] -#define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL] -#define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH] -#define RSCAN0RMID58 RSCAN0.RMID58.UINT32 -#define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L] -#define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL] -#define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH] -#define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H] -#define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL] -#define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH] -#define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32 -#define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L] -#define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL] -#define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH] -#define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H] -#define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL] -#define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH] -#define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32 -#define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L] -#define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL] -#define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH] -#define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H] -#define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL] -#define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH] -#define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32 -#define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L] -#define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL] -#define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH] -#define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H] -#define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL] -#define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH] -#define RSCAN0RMID59 RSCAN0.RMID59.UINT32 -#define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L] -#define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL] -#define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH] -#define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H] -#define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL] -#define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH] -#define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32 -#define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L] -#define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL] -#define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH] -#define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H] -#define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL] -#define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH] -#define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32 -#define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L] -#define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL] -#define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH] -#define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H] -#define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL] -#define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH] -#define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32 -#define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L] -#define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL] -#define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH] -#define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H] -#define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL] -#define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH] -#define RSCAN0RMID60 RSCAN0.RMID60.UINT32 -#define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L] -#define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL] -#define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH] -#define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H] -#define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL] -#define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH] -#define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32 -#define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L] -#define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL] -#define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH] -#define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H] -#define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL] -#define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH] -#define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32 -#define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L] -#define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL] -#define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH] -#define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H] -#define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL] -#define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH] -#define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32 -#define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L] -#define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL] -#define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH] -#define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H] -#define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL] -#define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH] -#define RSCAN0RMID61 RSCAN0.RMID61.UINT32 -#define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L] -#define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL] -#define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH] -#define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H] -#define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL] -#define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH] -#define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32 -#define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L] -#define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL] -#define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH] -#define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H] -#define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL] -#define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH] -#define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32 -#define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L] -#define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL] -#define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH] -#define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H] -#define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL] -#define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH] -#define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32 -#define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L] -#define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL] -#define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH] -#define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H] -#define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL] -#define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH] -#define RSCAN0RMID62 RSCAN0.RMID62.UINT32 -#define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L] -#define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL] -#define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH] -#define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H] -#define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL] -#define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH] -#define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32 -#define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L] -#define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL] -#define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH] -#define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H] -#define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL] -#define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH] -#define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32 -#define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L] -#define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL] -#define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH] -#define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H] -#define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL] -#define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH] -#define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32 -#define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L] -#define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL] -#define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH] -#define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H] -#define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL] -#define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH] -#define RSCAN0RMID63 RSCAN0.RMID63.UINT32 -#define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L] -#define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL] -#define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH] -#define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H] -#define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL] -#define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH] -#define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32 -#define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L] -#define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL] -#define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH] -#define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H] -#define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL] -#define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH] -#define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32 -#define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L] -#define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL] -#define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH] -#define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H] -#define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL] -#define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH] -#define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32 -#define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L] -#define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL] -#define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH] -#define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H] -#define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL] -#define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH] -#define RSCAN0RMID64 RSCAN0.RMID64.UINT32 -#define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L] -#define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL] -#define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH] -#define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H] -#define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL] -#define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH] -#define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32 -#define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L] -#define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL] -#define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH] -#define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H] -#define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL] -#define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH] -#define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32 -#define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L] -#define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL] -#define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH] -#define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H] -#define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL] -#define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH] -#define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32 -#define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L] -#define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL] -#define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH] -#define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H] -#define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL] -#define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH] -#define RSCAN0RMID65 RSCAN0.RMID65.UINT32 -#define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L] -#define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL] -#define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH] -#define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H] -#define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL] -#define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH] -#define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32 -#define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L] -#define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL] -#define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH] -#define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H] -#define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL] -#define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH] -#define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32 -#define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L] -#define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL] -#define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH] -#define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H] -#define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL] -#define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH] -#define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32 -#define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L] -#define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL] -#define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH] -#define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H] -#define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL] -#define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH] -#define RSCAN0RMID66 RSCAN0.RMID66.UINT32 -#define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L] -#define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL] -#define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH] -#define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H] -#define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL] -#define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH] -#define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32 -#define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L] -#define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL] -#define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH] -#define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H] -#define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL] -#define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH] -#define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32 -#define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L] -#define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL] -#define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH] -#define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H] -#define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL] -#define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH] -#define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32 -#define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L] -#define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL] -#define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH] -#define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H] -#define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL] -#define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH] -#define RSCAN0RMID67 RSCAN0.RMID67.UINT32 -#define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L] -#define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL] -#define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH] -#define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H] -#define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL] -#define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH] -#define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32 -#define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L] -#define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL] -#define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH] -#define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H] -#define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL] -#define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH] -#define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32 -#define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L] -#define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL] -#define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH] -#define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H] -#define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL] -#define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH] -#define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32 -#define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L] -#define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL] -#define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH] -#define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H] -#define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL] -#define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH] -#define RSCAN0RMID68 RSCAN0.RMID68.UINT32 -#define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L] -#define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL] -#define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH] -#define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H] -#define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL] -#define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH] -#define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32 -#define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L] -#define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL] -#define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH] -#define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H] -#define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL] -#define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH] -#define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32 -#define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L] -#define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL] -#define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH] -#define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H] -#define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL] -#define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH] -#define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32 -#define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L] -#define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL] -#define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH] -#define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H] -#define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL] -#define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH] -#define RSCAN0RMID69 RSCAN0.RMID69.UINT32 -#define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L] -#define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL] -#define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH] -#define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H] -#define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL] -#define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH] -#define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32 -#define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L] -#define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL] -#define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH] -#define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H] -#define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL] -#define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH] -#define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32 -#define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L] -#define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL] -#define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH] -#define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H] -#define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL] -#define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH] -#define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32 -#define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L] -#define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL] -#define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH] -#define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H] -#define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL] -#define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH] -#define RSCAN0RMID70 RSCAN0.RMID70.UINT32 -#define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L] -#define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL] -#define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH] -#define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H] -#define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL] -#define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH] -#define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32 -#define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L] -#define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL] -#define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH] -#define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H] -#define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL] -#define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH] -#define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32 -#define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L] -#define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL] -#define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH] -#define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H] -#define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL] -#define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH] -#define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32 -#define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L] -#define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL] -#define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH] -#define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H] -#define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL] -#define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH] -#define RSCAN0RMID71 RSCAN0.RMID71.UINT32 -#define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L] -#define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL] -#define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH] -#define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H] -#define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL] -#define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH] -#define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32 -#define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L] -#define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL] -#define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH] -#define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H] -#define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL] -#define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH] -#define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32 -#define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L] -#define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL] -#define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH] -#define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H] -#define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL] -#define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH] -#define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32 -#define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L] -#define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL] -#define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH] -#define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H] -#define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL] -#define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH] -#define RSCAN0RMID72 RSCAN0.RMID72.UINT32 -#define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L] -#define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL] -#define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH] -#define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H] -#define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL] -#define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH] -#define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32 -#define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L] -#define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL] -#define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH] -#define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H] -#define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL] -#define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH] -#define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32 -#define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L] -#define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL] -#define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH] -#define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H] -#define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL] -#define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH] -#define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32 -#define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L] -#define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL] -#define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH] -#define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H] -#define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL] -#define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH] -#define RSCAN0RMID73 RSCAN0.RMID73.UINT32 -#define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L] -#define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL] -#define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH] -#define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H] -#define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL] -#define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH] -#define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32 -#define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L] -#define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL] -#define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH] -#define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H] -#define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL] -#define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH] -#define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32 -#define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L] -#define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL] -#define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH] -#define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H] -#define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL] -#define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH] -#define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32 -#define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L] -#define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL] -#define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH] -#define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H] -#define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL] -#define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH] -#define RSCAN0RMID74 RSCAN0.RMID74.UINT32 -#define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L] -#define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL] -#define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH] -#define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H] -#define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL] -#define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH] -#define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32 -#define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L] -#define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL] -#define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH] -#define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H] -#define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL] -#define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH] -#define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32 -#define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L] -#define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL] -#define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH] -#define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H] -#define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL] -#define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH] -#define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32 -#define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L] -#define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL] -#define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH] -#define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H] -#define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL] -#define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH] -#define RSCAN0RMID75 RSCAN0.RMID75.UINT32 -#define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L] -#define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL] -#define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH] -#define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H] -#define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL] -#define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH] -#define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32 -#define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L] -#define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL] -#define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH] -#define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H] -#define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL] -#define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH] -#define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32 -#define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L] -#define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL] -#define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH] -#define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H] -#define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL] -#define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH] -#define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32 -#define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L] -#define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL] -#define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH] -#define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H] -#define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL] -#define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH] -#define RSCAN0RMID76 RSCAN0.RMID76.UINT32 -#define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L] -#define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL] -#define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH] -#define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H] -#define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL] -#define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH] -#define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32 -#define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L] -#define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL] -#define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH] -#define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H] -#define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL] -#define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH] -#define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32 -#define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L] -#define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL] -#define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH] -#define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H] -#define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL] -#define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH] -#define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32 -#define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L] -#define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL] -#define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH] -#define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H] -#define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL] -#define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH] -#define RSCAN0RMID77 RSCAN0.RMID77.UINT32 -#define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L] -#define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL] -#define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH] -#define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H] -#define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL] -#define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH] -#define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32 -#define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L] -#define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL] -#define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH] -#define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H] -#define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL] -#define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH] -#define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32 -#define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L] -#define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL] -#define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH] -#define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H] -#define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL] -#define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH] -#define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32 -#define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L] -#define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL] -#define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH] -#define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H] -#define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL] -#define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH] -#define RSCAN0RMID78 RSCAN0.RMID78.UINT32 -#define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L] -#define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL] -#define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH] -#define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H] -#define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL] -#define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH] -#define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32 -#define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L] -#define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL] -#define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH] -#define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H] -#define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL] -#define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH] -#define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32 -#define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L] -#define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL] -#define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH] -#define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H] -#define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL] -#define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH] -#define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32 -#define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L] -#define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL] -#define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH] -#define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H] -#define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL] -#define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH] -#define RSCAN0RMID79 RSCAN0.RMID79.UINT32 -#define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L] -#define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL] -#define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH] -#define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H] -#define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL] -#define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH] -#define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32 -#define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L] -#define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL] -#define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH] -#define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H] -#define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL] -#define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH] -#define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32 -#define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L] -#define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL] -#define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH] -#define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H] -#define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL] -#define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH] -#define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32 -#define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L] -#define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL] -#define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH] -#define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H] -#define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL] -#define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH] -#define RSCAN0RFID0 RSCAN0.RFID0.UINT32 -#define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L] -#define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL] -#define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH] -#define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H] -#define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL] -#define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH] -#define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32 -#define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L] -#define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL] -#define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH] -#define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H] -#define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL] -#define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH] -#define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32 -#define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L] -#define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL] -#define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH] -#define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H] -#define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL] -#define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH] -#define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32 -#define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L] -#define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL] -#define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH] -#define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H] -#define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL] -#define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH] -#define RSCAN0RFID1 RSCAN0.RFID1.UINT32 -#define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L] -#define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL] -#define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH] -#define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H] -#define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL] -#define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH] -#define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32 -#define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L] -#define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL] -#define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH] -#define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H] -#define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL] -#define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH] -#define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32 -#define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L] -#define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL] -#define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH] -#define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H] -#define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL] -#define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH] -#define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32 -#define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L] -#define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL] -#define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH] -#define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H] -#define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL] -#define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH] -#define RSCAN0RFID2 RSCAN0.RFID2.UINT32 -#define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L] -#define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL] -#define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH] -#define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H] -#define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL] -#define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH] -#define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32 -#define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L] -#define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL] -#define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH] -#define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H] -#define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL] -#define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH] -#define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32 -#define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L] -#define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL] -#define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH] -#define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H] -#define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL] -#define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH] -#define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32 -#define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L] -#define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL] -#define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH] -#define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H] -#define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL] -#define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH] -#define RSCAN0RFID3 RSCAN0.RFID3.UINT32 -#define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L] -#define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL] -#define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH] -#define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H] -#define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL] -#define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH] -#define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32 -#define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L] -#define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL] -#define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH] -#define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H] -#define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL] -#define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH] -#define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32 -#define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L] -#define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL] -#define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH] -#define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H] -#define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL] -#define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH] -#define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32 -#define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L] -#define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL] -#define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH] -#define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H] -#define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL] -#define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH] -#define RSCAN0RFID4 RSCAN0.RFID4.UINT32 -#define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L] -#define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL] -#define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH] -#define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H] -#define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL] -#define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH] -#define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32 -#define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L] -#define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL] -#define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH] -#define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H] -#define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL] -#define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH] -#define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32 -#define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L] -#define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL] -#define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH] -#define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H] -#define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL] -#define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH] -#define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32 -#define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L] -#define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL] -#define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH] -#define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H] -#define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL] -#define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH] -#define RSCAN0RFID5 RSCAN0.RFID5.UINT32 -#define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L] -#define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL] -#define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH] -#define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H] -#define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL] -#define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH] -#define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32 -#define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L] -#define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL] -#define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH] -#define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H] -#define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL] -#define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH] -#define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32 -#define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L] -#define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL] -#define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH] -#define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H] -#define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL] -#define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH] -#define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32 -#define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L] -#define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL] -#define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH] -#define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H] -#define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL] -#define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH] -#define RSCAN0RFID6 RSCAN0.RFID6.UINT32 -#define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L] -#define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL] -#define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH] -#define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H] -#define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL] -#define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH] -#define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32 -#define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L] -#define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL] -#define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH] -#define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H] -#define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL] -#define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH] -#define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32 -#define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L] -#define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL] -#define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH] -#define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H] -#define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL] -#define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH] -#define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32 -#define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L] -#define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL] -#define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH] -#define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H] -#define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL] -#define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH] -#define RSCAN0RFID7 RSCAN0.RFID7.UINT32 -#define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L] -#define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL] -#define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH] -#define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H] -#define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL] -#define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH] -#define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32 -#define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L] -#define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL] -#define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH] -#define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H] -#define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL] -#define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH] -#define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32 -#define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L] -#define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL] -#define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH] -#define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H] -#define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL] -#define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH] -#define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32 -#define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L] -#define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL] -#define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH] -#define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H] -#define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL] -#define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH] -#define RSCAN0CFID0 RSCAN0.CFID0.UINT32 -#define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L] -#define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL] -#define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH] -#define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H] -#define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL] -#define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH] -#define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32 -#define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L] -#define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL] -#define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH] -#define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H] -#define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL] -#define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH] -#define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32 -#define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L] -#define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL] -#define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH] -#define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H] -#define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL] -#define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH] -#define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32 -#define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L] -#define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL] -#define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH] -#define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H] -#define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL] -#define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH] -#define RSCAN0CFID1 RSCAN0.CFID1.UINT32 -#define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L] -#define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL] -#define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH] -#define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H] -#define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL] -#define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH] -#define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32 -#define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L] -#define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL] -#define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH] -#define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H] -#define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL] -#define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH] -#define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32 -#define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L] -#define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL] -#define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH] -#define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H] -#define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL] -#define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH] -#define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32 -#define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L] -#define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL] -#define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH] -#define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H] -#define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL] -#define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH] -#define RSCAN0CFID2 RSCAN0.CFID2.UINT32 -#define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L] -#define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL] -#define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH] -#define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H] -#define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL] -#define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH] -#define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32 -#define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L] -#define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL] -#define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH] -#define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H] -#define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL] -#define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH] -#define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32 -#define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L] -#define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL] -#define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH] -#define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H] -#define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL] -#define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH] -#define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32 -#define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L] -#define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL] -#define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH] -#define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H] -#define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL] -#define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH] -#define RSCAN0CFID3 RSCAN0.CFID3.UINT32 -#define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L] -#define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL] -#define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH] -#define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H] -#define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL] -#define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH] -#define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32 -#define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L] -#define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL] -#define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH] -#define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H] -#define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL] -#define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH] -#define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32 -#define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L] -#define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL] -#define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH] -#define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H] -#define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL] -#define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH] -#define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32 -#define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L] -#define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL] -#define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH] -#define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H] -#define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL] -#define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH] -#define RSCAN0CFID4 RSCAN0.CFID4.UINT32 -#define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L] -#define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL] -#define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH] -#define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H] -#define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL] -#define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH] -#define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32 -#define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L] -#define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL] -#define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH] -#define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H] -#define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL] -#define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH] -#define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32 -#define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L] -#define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL] -#define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH] -#define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H] -#define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL] -#define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH] -#define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32 -#define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L] -#define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL] -#define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH] -#define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H] -#define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL] -#define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH] -#define RSCAN0CFID5 RSCAN0.CFID5.UINT32 -#define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L] -#define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL] -#define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH] -#define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H] -#define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL] -#define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH] -#define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32 -#define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L] -#define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL] -#define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH] -#define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H] -#define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL] -#define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH] -#define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32 -#define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L] -#define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL] -#define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH] -#define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H] -#define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL] -#define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH] -#define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32 -#define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L] -#define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL] -#define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH] -#define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H] -#define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL] -#define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH] -#define RSCAN0CFID6 RSCAN0.CFID6.UINT32 -#define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L] -#define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL] -#define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH] -#define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H] -#define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL] -#define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH] -#define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32 -#define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L] -#define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL] -#define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH] -#define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H] -#define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL] -#define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH] -#define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32 -#define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L] -#define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL] -#define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH] -#define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H] -#define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL] -#define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH] -#define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32 -#define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L] -#define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL] -#define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH] -#define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H] -#define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL] -#define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH] -#define RSCAN0CFID7 RSCAN0.CFID7.UINT32 -#define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L] -#define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL] -#define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH] -#define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H] -#define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL] -#define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH] -#define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32 -#define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L] -#define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL] -#define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH] -#define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H] -#define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL] -#define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH] -#define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32 -#define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L] -#define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL] -#define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH] -#define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H] -#define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL] -#define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH] -#define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32 -#define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L] -#define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL] -#define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH] -#define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H] -#define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL] -#define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH] -#define RSCAN0CFID8 RSCAN0.CFID8.UINT32 -#define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L] -#define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL] -#define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH] -#define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H] -#define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL] -#define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH] -#define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32 -#define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L] -#define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL] -#define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH] -#define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H] -#define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL] -#define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH] -#define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32 -#define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L] -#define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL] -#define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH] -#define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H] -#define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL] -#define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH] -#define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32 -#define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L] -#define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL] -#define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH] -#define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H] -#define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL] -#define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH] -#define RSCAN0CFID9 RSCAN0.CFID9.UINT32 -#define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L] -#define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL] -#define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH] -#define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H] -#define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL] -#define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH] -#define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32 -#define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L] -#define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL] -#define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH] -#define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H] -#define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL] -#define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH] -#define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32 -#define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L] -#define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL] -#define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH] -#define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H] -#define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL] -#define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH] -#define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32 -#define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L] -#define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL] -#define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH] -#define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H] -#define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL] -#define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH] -#define RSCAN0CFID10 RSCAN0.CFID10.UINT32 -#define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L] -#define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL] -#define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH] -#define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H] -#define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL] -#define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH] -#define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32 -#define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L] -#define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL] -#define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH] -#define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H] -#define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL] -#define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH] -#define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32 -#define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L] -#define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL] -#define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH] -#define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H] -#define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL] -#define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH] -#define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32 -#define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L] -#define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL] -#define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH] -#define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H] -#define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL] -#define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH] -#define RSCAN0CFID11 RSCAN0.CFID11.UINT32 -#define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L] -#define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL] -#define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH] -#define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H] -#define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL] -#define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH] -#define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32 -#define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L] -#define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL] -#define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH] -#define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H] -#define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL] -#define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH] -#define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32 -#define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L] -#define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL] -#define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH] -#define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H] -#define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL] -#define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH] -#define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32 -#define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L] -#define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL] -#define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH] -#define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H] -#define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL] -#define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH] -#define RSCAN0CFID12 RSCAN0.CFID12.UINT32 -#define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L] -#define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL] -#define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH] -#define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H] -#define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL] -#define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH] -#define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32 -#define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L] -#define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL] -#define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH] -#define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H] -#define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL] -#define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH] -#define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32 -#define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L] -#define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL] -#define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH] -#define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H] -#define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL] -#define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH] -#define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32 -#define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L] -#define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL] -#define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH] -#define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H] -#define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL] -#define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH] -#define RSCAN0CFID13 RSCAN0.CFID13.UINT32 -#define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L] -#define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL] -#define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH] -#define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H] -#define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL] -#define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH] -#define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32 -#define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L] -#define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL] -#define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH] -#define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H] -#define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL] -#define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH] -#define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32 -#define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L] -#define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL] -#define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH] -#define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H] -#define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL] -#define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH] -#define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32 -#define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L] -#define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL] -#define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH] -#define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H] -#define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL] -#define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH] -#define RSCAN0CFID14 RSCAN0.CFID14.UINT32 -#define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L] -#define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL] -#define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH] -#define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H] -#define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL] -#define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH] -#define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32 -#define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L] -#define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL] -#define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH] -#define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H] -#define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL] -#define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH] -#define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32 -#define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L] -#define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL] -#define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH] -#define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H] -#define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL] -#define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH] -#define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32 -#define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L] -#define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL] -#define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH] -#define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H] -#define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL] -#define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH] -#define RSCAN0TMID0 RSCAN0.TMID0.UINT32 -#define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L] -#define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL] -#define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH] -#define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H] -#define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL] -#define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH] -#define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32 -#define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L] -#define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL] -#define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH] -#define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H] -#define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL] -#define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH] -#define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32 -#define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L] -#define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL] -#define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH] -#define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H] -#define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL] -#define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH] -#define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32 -#define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L] -#define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL] -#define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH] -#define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H] -#define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL] -#define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH] -#define RSCAN0TMID1 RSCAN0.TMID1.UINT32 -#define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L] -#define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL] -#define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH] -#define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H] -#define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL] -#define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH] -#define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32 -#define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L] -#define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL] -#define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH] -#define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H] -#define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL] -#define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH] -#define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32 -#define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L] -#define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL] -#define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH] -#define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H] -#define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL] -#define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH] -#define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32 -#define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L] -#define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL] -#define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH] -#define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H] -#define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL] -#define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH] -#define RSCAN0TMID2 RSCAN0.TMID2.UINT32 -#define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L] -#define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL] -#define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH] -#define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H] -#define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL] -#define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH] -#define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32 -#define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L] -#define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL] -#define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH] -#define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H] -#define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL] -#define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH] -#define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32 -#define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L] -#define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL] -#define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH] -#define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H] -#define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL] -#define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH] -#define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32 -#define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L] -#define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL] -#define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH] -#define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H] -#define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL] -#define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH] -#define RSCAN0TMID3 RSCAN0.TMID3.UINT32 -#define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L] -#define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL] -#define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH] -#define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H] -#define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL] -#define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH] -#define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32 -#define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L] -#define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL] -#define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH] -#define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H] -#define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL] -#define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH] -#define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32 -#define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L] -#define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL] -#define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH] -#define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H] -#define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL] -#define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH] -#define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32 -#define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L] -#define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL] -#define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH] -#define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H] -#define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL] -#define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH] -#define RSCAN0TMID4 RSCAN0.TMID4.UINT32 -#define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L] -#define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL] -#define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH] -#define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H] -#define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL] -#define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH] -#define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32 -#define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L] -#define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL] -#define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH] -#define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H] -#define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL] -#define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH] -#define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32 -#define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L] -#define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL] -#define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH] -#define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H] -#define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL] -#define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH] -#define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32 -#define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L] -#define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL] -#define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH] -#define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H] -#define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL] -#define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH] -#define RSCAN0TMID5 RSCAN0.TMID5.UINT32 -#define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L] -#define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL] -#define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH] -#define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H] -#define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL] -#define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH] -#define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32 -#define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L] -#define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL] -#define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH] -#define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H] -#define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL] -#define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH] -#define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32 -#define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L] -#define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL] -#define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH] -#define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H] -#define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL] -#define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH] -#define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32 -#define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L] -#define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL] -#define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH] -#define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H] -#define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL] -#define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH] -#define RSCAN0TMID6 RSCAN0.TMID6.UINT32 -#define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L] -#define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL] -#define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH] -#define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H] -#define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL] -#define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH] -#define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32 -#define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L] -#define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL] -#define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH] -#define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H] -#define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL] -#define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH] -#define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32 -#define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L] -#define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL] -#define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH] -#define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H] -#define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL] -#define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH] -#define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32 -#define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L] -#define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL] -#define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH] -#define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H] -#define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL] -#define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH] -#define RSCAN0TMID7 RSCAN0.TMID7.UINT32 -#define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L] -#define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL] -#define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH] -#define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H] -#define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL] -#define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH] -#define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32 -#define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L] -#define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL] -#define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH] -#define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H] -#define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL] -#define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH] -#define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32 -#define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L] -#define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL] -#define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH] -#define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H] -#define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL] -#define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH] -#define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32 -#define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L] -#define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL] -#define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH] -#define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H] -#define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL] -#define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH] -#define RSCAN0TMID8 RSCAN0.TMID8.UINT32 -#define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L] -#define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL] -#define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH] -#define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H] -#define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL] -#define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH] -#define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32 -#define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L] -#define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL] -#define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH] -#define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H] -#define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL] -#define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH] -#define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32 -#define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L] -#define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL] -#define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH] -#define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H] -#define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL] -#define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH] -#define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32 -#define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L] -#define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL] -#define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH] -#define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H] -#define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL] -#define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH] -#define RSCAN0TMID9 RSCAN0.TMID9.UINT32 -#define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L] -#define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL] -#define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH] -#define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H] -#define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL] -#define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH] -#define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32 -#define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L] -#define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL] -#define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH] -#define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H] -#define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL] -#define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH] -#define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32 -#define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L] -#define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL] -#define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH] -#define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H] -#define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL] -#define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH] -#define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32 -#define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L] -#define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL] -#define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH] -#define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H] -#define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL] -#define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH] -#define RSCAN0TMID10 RSCAN0.TMID10.UINT32 -#define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L] -#define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL] -#define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH] -#define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H] -#define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL] -#define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH] -#define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32 -#define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L] -#define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL] -#define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH] -#define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H] -#define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL] -#define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH] -#define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32 -#define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L] -#define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL] -#define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH] -#define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H] -#define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL] -#define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH] -#define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32 -#define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L] -#define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL] -#define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH] -#define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H] -#define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL] -#define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH] -#define RSCAN0TMID11 RSCAN0.TMID11.UINT32 -#define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L] -#define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL] -#define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH] -#define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H] -#define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL] -#define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH] -#define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32 -#define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L] -#define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL] -#define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH] -#define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H] -#define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL] -#define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH] -#define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32 -#define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L] -#define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL] -#define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH] -#define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H] -#define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL] -#define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH] -#define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32 -#define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L] -#define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL] -#define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH] -#define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H] -#define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL] -#define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH] -#define RSCAN0TMID12 RSCAN0.TMID12.UINT32 -#define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L] -#define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL] -#define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH] -#define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H] -#define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL] -#define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH] -#define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32 -#define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L] -#define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL] -#define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH] -#define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H] -#define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL] -#define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH] -#define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32 -#define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L] -#define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL] -#define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH] -#define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H] -#define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL] -#define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH] -#define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32 -#define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L] -#define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL] -#define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH] -#define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H] -#define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL] -#define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH] -#define RSCAN0TMID13 RSCAN0.TMID13.UINT32 -#define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L] -#define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL] -#define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH] -#define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H] -#define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL] -#define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH] -#define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32 -#define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L] -#define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL] -#define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH] -#define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H] -#define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL] -#define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH] -#define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32 -#define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L] -#define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL] -#define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH] -#define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H] -#define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL] -#define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH] -#define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32 -#define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L] -#define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL] -#define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH] -#define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H] -#define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL] -#define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH] -#define RSCAN0TMID14 RSCAN0.TMID14.UINT32 -#define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L] -#define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL] -#define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH] -#define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H] -#define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL] -#define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH] -#define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32 -#define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L] -#define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL] -#define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH] -#define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H] -#define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL] -#define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH] -#define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32 -#define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L] -#define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL] -#define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH] -#define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H] -#define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL] -#define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH] -#define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32 -#define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L] -#define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL] -#define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH] -#define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H] -#define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL] -#define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH] -#define RSCAN0TMID15 RSCAN0.TMID15.UINT32 -#define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L] -#define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL] -#define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH] -#define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H] -#define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL] -#define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH] -#define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32 -#define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L] -#define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL] -#define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH] -#define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H] -#define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL] -#define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH] -#define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32 -#define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L] -#define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL] -#define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH] -#define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H] -#define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL] -#define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH] -#define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32 -#define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L] -#define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL] -#define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH] -#define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H] -#define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL] -#define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH] -#define RSCAN0TMID16 RSCAN0.TMID16.UINT32 -#define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L] -#define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL] -#define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH] -#define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H] -#define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL] -#define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH] -#define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32 -#define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L] -#define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL] -#define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH] -#define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H] -#define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL] -#define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH] -#define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32 -#define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L] -#define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL] -#define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH] -#define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H] -#define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL] -#define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH] -#define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32 -#define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L] -#define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL] -#define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH] -#define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H] -#define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL] -#define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH] -#define RSCAN0TMID17 RSCAN0.TMID17.UINT32 -#define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L] -#define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL] -#define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH] -#define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H] -#define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL] -#define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH] -#define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32 -#define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L] -#define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL] -#define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH] -#define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H] -#define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL] -#define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH] -#define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32 -#define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L] -#define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL] -#define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH] -#define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H] -#define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL] -#define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH] -#define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32 -#define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L] -#define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL] -#define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH] -#define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H] -#define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL] -#define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH] -#define RSCAN0TMID18 RSCAN0.TMID18.UINT32 -#define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L] -#define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL] -#define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH] -#define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H] -#define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL] -#define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH] -#define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32 -#define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L] -#define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL] -#define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH] -#define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H] -#define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL] -#define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH] -#define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32 -#define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L] -#define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL] -#define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH] -#define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H] -#define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL] -#define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH] -#define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32 -#define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L] -#define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL] -#define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH] -#define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H] -#define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL] -#define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH] -#define RSCAN0TMID19 RSCAN0.TMID19.UINT32 -#define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L] -#define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL] -#define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH] -#define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H] -#define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL] -#define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH] -#define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32 -#define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L] -#define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL] -#define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH] -#define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H] -#define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL] -#define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH] -#define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32 -#define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L] -#define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL] -#define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH] -#define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H] -#define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL] -#define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH] -#define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32 -#define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L] -#define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL] -#define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH] -#define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H] -#define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL] -#define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH] -#define RSCAN0TMID20 RSCAN0.TMID20.UINT32 -#define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L] -#define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL] -#define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH] -#define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H] -#define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL] -#define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH] -#define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32 -#define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L] -#define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL] -#define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH] -#define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H] -#define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL] -#define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH] -#define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32 -#define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L] -#define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL] -#define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH] -#define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H] -#define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL] -#define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH] -#define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32 -#define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L] -#define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL] -#define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH] -#define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H] -#define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL] -#define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH] -#define RSCAN0TMID21 RSCAN0.TMID21.UINT32 -#define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L] -#define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL] -#define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH] -#define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H] -#define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL] -#define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH] -#define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32 -#define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L] -#define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL] -#define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH] -#define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H] -#define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL] -#define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH] -#define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32 -#define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L] -#define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL] -#define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH] -#define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H] -#define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL] -#define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH] -#define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32 -#define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L] -#define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL] -#define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH] -#define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H] -#define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL] -#define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH] -#define RSCAN0TMID22 RSCAN0.TMID22.UINT32 -#define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L] -#define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL] -#define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH] -#define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H] -#define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL] -#define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH] -#define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32 -#define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L] -#define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL] -#define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH] -#define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H] -#define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL] -#define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH] -#define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32 -#define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L] -#define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL] -#define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH] -#define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H] -#define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL] -#define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH] -#define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32 -#define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L] -#define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL] -#define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH] -#define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H] -#define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL] -#define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH] -#define RSCAN0TMID23 RSCAN0.TMID23.UINT32 -#define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L] -#define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL] -#define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH] -#define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H] -#define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL] -#define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH] -#define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32 -#define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L] -#define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL] -#define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH] -#define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H] -#define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL] -#define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH] -#define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32 -#define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L] -#define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL] -#define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH] -#define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H] -#define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL] -#define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH] -#define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32 -#define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L] -#define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL] -#define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH] -#define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H] -#define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL] -#define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH] -#define RSCAN0TMID24 RSCAN0.TMID24.UINT32 -#define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L] -#define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL] -#define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH] -#define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H] -#define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL] -#define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH] -#define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32 -#define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L] -#define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL] -#define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH] -#define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H] -#define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL] -#define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH] -#define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32 -#define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L] -#define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL] -#define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH] -#define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H] -#define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL] -#define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH] -#define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32 -#define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L] -#define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL] -#define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH] -#define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H] -#define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL] -#define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH] -#define RSCAN0TMID25 RSCAN0.TMID25.UINT32 -#define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L] -#define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL] -#define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH] -#define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H] -#define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL] -#define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH] -#define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32 -#define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L] -#define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL] -#define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH] -#define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H] -#define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL] -#define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH] -#define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32 -#define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L] -#define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL] -#define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH] -#define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H] -#define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL] -#define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH] -#define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32 -#define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L] -#define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL] -#define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH] -#define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H] -#define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL] -#define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH] -#define RSCAN0TMID26 RSCAN0.TMID26.UINT32 -#define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L] -#define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL] -#define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH] -#define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H] -#define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL] -#define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH] -#define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32 -#define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L] -#define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL] -#define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH] -#define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H] -#define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL] -#define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH] -#define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32 -#define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L] -#define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL] -#define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH] -#define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H] -#define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL] -#define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH] -#define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32 -#define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L] -#define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL] -#define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH] -#define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H] -#define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL] -#define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH] -#define RSCAN0TMID27 RSCAN0.TMID27.UINT32 -#define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L] -#define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL] -#define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH] -#define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H] -#define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL] -#define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH] -#define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32 -#define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L] -#define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL] -#define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH] -#define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H] -#define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL] -#define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH] -#define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32 -#define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L] -#define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL] -#define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH] -#define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H] -#define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL] -#define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH] -#define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32 -#define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L] -#define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL] -#define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH] -#define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H] -#define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL] -#define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH] -#define RSCAN0TMID28 RSCAN0.TMID28.UINT32 -#define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L] -#define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL] -#define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH] -#define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H] -#define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL] -#define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH] -#define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32 -#define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L] -#define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL] -#define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH] -#define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H] -#define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL] -#define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH] -#define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32 -#define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L] -#define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL] -#define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH] -#define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H] -#define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL] -#define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH] -#define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32 -#define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L] -#define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL] -#define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH] -#define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H] -#define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL] -#define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH] -#define RSCAN0TMID29 RSCAN0.TMID29.UINT32 -#define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L] -#define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL] -#define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH] -#define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H] -#define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL] -#define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH] -#define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32 -#define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L] -#define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL] -#define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH] -#define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H] -#define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL] -#define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH] -#define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32 -#define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L] -#define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL] -#define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH] -#define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H] -#define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL] -#define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH] -#define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32 -#define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L] -#define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL] -#define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH] -#define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H] -#define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL] -#define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH] -#define RSCAN0TMID30 RSCAN0.TMID30.UINT32 -#define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L] -#define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL] -#define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH] -#define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H] -#define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL] -#define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH] -#define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32 -#define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L] -#define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL] -#define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH] -#define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H] -#define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL] -#define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH] -#define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32 -#define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L] -#define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL] -#define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH] -#define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H] -#define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL] -#define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH] -#define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32 -#define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L] -#define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL] -#define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH] -#define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H] -#define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL] -#define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH] -#define RSCAN0TMID31 RSCAN0.TMID31.UINT32 -#define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L] -#define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL] -#define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH] -#define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H] -#define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL] -#define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH] -#define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32 -#define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L] -#define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL] -#define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH] -#define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H] -#define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL] -#define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH] -#define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32 -#define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L] -#define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL] -#define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH] -#define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H] -#define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL] -#define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH] -#define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32 -#define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L] -#define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL] -#define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH] -#define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H] -#define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL] -#define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH] -#define RSCAN0TMID32 RSCAN0.TMID32.UINT32 -#define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L] -#define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL] -#define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH] -#define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H] -#define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL] -#define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH] -#define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32 -#define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L] -#define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL] -#define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH] -#define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H] -#define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL] -#define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH] -#define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32 -#define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L] -#define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL] -#define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH] -#define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H] -#define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL] -#define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH] -#define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32 -#define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L] -#define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL] -#define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH] -#define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H] -#define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL] -#define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH] -#define RSCAN0TMID33 RSCAN0.TMID33.UINT32 -#define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L] -#define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL] -#define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH] -#define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H] -#define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL] -#define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH] -#define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32 -#define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L] -#define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL] -#define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH] -#define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H] -#define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL] -#define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH] -#define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32 -#define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L] -#define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL] -#define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH] -#define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H] -#define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL] -#define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH] -#define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32 -#define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L] -#define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL] -#define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH] -#define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H] -#define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL] -#define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH] -#define RSCAN0TMID34 RSCAN0.TMID34.UINT32 -#define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L] -#define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL] -#define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH] -#define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H] -#define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL] -#define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH] -#define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32 -#define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L] -#define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL] -#define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH] -#define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H] -#define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL] -#define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH] -#define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32 -#define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L] -#define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL] -#define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH] -#define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H] -#define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL] -#define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH] -#define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32 -#define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L] -#define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL] -#define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH] -#define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H] -#define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL] -#define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH] -#define RSCAN0TMID35 RSCAN0.TMID35.UINT32 -#define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L] -#define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL] -#define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH] -#define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H] -#define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL] -#define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH] -#define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32 -#define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L] -#define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL] -#define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH] -#define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H] -#define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL] -#define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH] -#define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32 -#define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L] -#define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL] -#define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH] -#define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H] -#define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL] -#define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH] -#define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32 -#define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L] -#define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL] -#define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH] -#define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H] -#define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL] -#define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH] -#define RSCAN0TMID36 RSCAN0.TMID36.UINT32 -#define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L] -#define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL] -#define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH] -#define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H] -#define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL] -#define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH] -#define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32 -#define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L] -#define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL] -#define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH] -#define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H] -#define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL] -#define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH] -#define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32 -#define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L] -#define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL] -#define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH] -#define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H] -#define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL] -#define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH] -#define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32 -#define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L] -#define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL] -#define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH] -#define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H] -#define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL] -#define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH] -#define RSCAN0TMID37 RSCAN0.TMID37.UINT32 -#define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L] -#define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL] -#define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH] -#define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H] -#define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL] -#define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH] -#define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32 -#define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L] -#define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL] -#define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH] -#define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H] -#define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL] -#define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH] -#define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32 -#define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L] -#define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL] -#define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH] -#define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H] -#define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL] -#define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH] -#define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32 -#define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L] -#define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL] -#define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH] -#define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H] -#define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL] -#define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH] -#define RSCAN0TMID38 RSCAN0.TMID38.UINT32 -#define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L] -#define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL] -#define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH] -#define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H] -#define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL] -#define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH] -#define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32 -#define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L] -#define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL] -#define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH] -#define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H] -#define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL] -#define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH] -#define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32 -#define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L] -#define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL] -#define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH] -#define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H] -#define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL] -#define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH] -#define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32 -#define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L] -#define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL] -#define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH] -#define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H] -#define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL] -#define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH] -#define RSCAN0TMID39 RSCAN0.TMID39.UINT32 -#define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L] -#define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL] -#define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH] -#define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H] -#define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL] -#define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH] -#define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32 -#define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L] -#define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL] -#define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH] -#define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H] -#define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL] -#define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH] -#define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32 -#define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L] -#define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL] -#define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH] -#define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H] -#define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL] -#define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH] -#define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32 -#define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L] -#define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL] -#define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH] -#define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H] -#define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL] -#define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH] -#define RSCAN0TMID40 RSCAN0.TMID40.UINT32 -#define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L] -#define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL] -#define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH] -#define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H] -#define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL] -#define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH] -#define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32 -#define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L] -#define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL] -#define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH] -#define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H] -#define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL] -#define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH] -#define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32 -#define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L] -#define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL] -#define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH] -#define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H] -#define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL] -#define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH] -#define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32 -#define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L] -#define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL] -#define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH] -#define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H] -#define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL] -#define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH] -#define RSCAN0TMID41 RSCAN0.TMID41.UINT32 -#define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L] -#define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL] -#define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH] -#define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H] -#define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL] -#define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH] -#define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32 -#define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L] -#define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL] -#define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH] -#define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H] -#define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL] -#define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH] -#define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32 -#define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L] -#define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL] -#define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH] -#define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H] -#define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL] -#define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH] -#define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32 -#define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L] -#define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL] -#define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH] -#define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H] -#define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL] -#define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH] -#define RSCAN0TMID42 RSCAN0.TMID42.UINT32 -#define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L] -#define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL] -#define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH] -#define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H] -#define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL] -#define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH] -#define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32 -#define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L] -#define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL] -#define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH] -#define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H] -#define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL] -#define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH] -#define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32 -#define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L] -#define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL] -#define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH] -#define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H] -#define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL] -#define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH] -#define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32 -#define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L] -#define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL] -#define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH] -#define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H] -#define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL] -#define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH] -#define RSCAN0TMID43 RSCAN0.TMID43.UINT32 -#define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L] -#define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL] -#define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH] -#define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H] -#define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL] -#define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH] -#define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32 -#define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L] -#define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL] -#define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH] -#define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H] -#define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL] -#define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH] -#define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32 -#define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L] -#define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL] -#define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH] -#define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H] -#define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL] -#define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH] -#define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32 -#define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L] -#define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL] -#define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH] -#define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H] -#define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL] -#define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH] -#define RSCAN0TMID44 RSCAN0.TMID44.UINT32 -#define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L] -#define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL] -#define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH] -#define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H] -#define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL] -#define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH] -#define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32 -#define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L] -#define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL] -#define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH] -#define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H] -#define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL] -#define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH] -#define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32 -#define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L] -#define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL] -#define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH] -#define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H] -#define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL] -#define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH] -#define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32 -#define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L] -#define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL] -#define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH] -#define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H] -#define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL] -#define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH] -#define RSCAN0TMID45 RSCAN0.TMID45.UINT32 -#define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L] -#define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL] -#define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH] -#define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H] -#define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL] -#define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH] -#define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32 -#define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L] -#define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL] -#define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH] -#define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H] -#define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL] -#define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH] -#define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32 -#define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L] -#define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL] -#define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH] -#define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H] -#define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL] -#define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH] -#define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32 -#define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L] -#define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL] -#define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH] -#define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H] -#define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL] -#define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH] -#define RSCAN0TMID46 RSCAN0.TMID46.UINT32 -#define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L] -#define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL] -#define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH] -#define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H] -#define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL] -#define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH] -#define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32 -#define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L] -#define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL] -#define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH] -#define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H] -#define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL] -#define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH] -#define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32 -#define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L] -#define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL] -#define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH] -#define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H] -#define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL] -#define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH] -#define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32 -#define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L] -#define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL] -#define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH] -#define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H] -#define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL] -#define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH] -#define RSCAN0TMID47 RSCAN0.TMID47.UINT32 -#define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L] -#define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL] -#define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH] -#define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H] -#define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL] -#define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH] -#define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32 -#define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L] -#define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL] -#define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH] -#define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H] -#define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL] -#define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH] -#define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32 -#define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L] -#define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL] -#define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH] -#define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H] -#define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL] -#define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH] -#define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32 -#define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L] -#define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL] -#define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH] -#define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H] -#define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL] -#define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH] -#define RSCAN0TMID48 RSCAN0.TMID48.UINT32 -#define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L] -#define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL] -#define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH] -#define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H] -#define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL] -#define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH] -#define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32 -#define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L] -#define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL] -#define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH] -#define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H] -#define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL] -#define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH] -#define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32 -#define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L] -#define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL] -#define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH] -#define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H] -#define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL] -#define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH] -#define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32 -#define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L] -#define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL] -#define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH] -#define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H] -#define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL] -#define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH] -#define RSCAN0TMID49 RSCAN0.TMID49.UINT32 -#define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L] -#define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL] -#define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH] -#define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H] -#define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL] -#define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH] -#define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32 -#define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L] -#define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL] -#define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH] -#define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H] -#define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL] -#define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH] -#define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32 -#define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L] -#define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL] -#define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH] -#define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H] -#define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL] -#define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH] -#define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32 -#define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L] -#define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL] -#define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH] -#define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H] -#define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL] -#define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH] -#define RSCAN0TMID50 RSCAN0.TMID50.UINT32 -#define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L] -#define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL] -#define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH] -#define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H] -#define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL] -#define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH] -#define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32 -#define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L] -#define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL] -#define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH] -#define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H] -#define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL] -#define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH] -#define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32 -#define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L] -#define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL] -#define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH] -#define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H] -#define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL] -#define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH] -#define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32 -#define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L] -#define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL] -#define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH] -#define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H] -#define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL] -#define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH] -#define RSCAN0TMID51 RSCAN0.TMID51.UINT32 -#define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L] -#define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL] -#define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH] -#define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H] -#define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL] -#define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH] -#define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32 -#define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L] -#define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL] -#define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH] -#define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H] -#define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL] -#define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH] -#define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32 -#define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L] -#define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL] -#define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH] -#define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H] -#define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL] -#define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH] -#define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32 -#define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L] -#define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL] -#define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH] -#define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H] -#define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL] -#define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH] -#define RSCAN0TMID52 RSCAN0.TMID52.UINT32 -#define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L] -#define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL] -#define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH] -#define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H] -#define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL] -#define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH] -#define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32 -#define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L] -#define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL] -#define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH] -#define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H] -#define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL] -#define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH] -#define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32 -#define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L] -#define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL] -#define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH] -#define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H] -#define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL] -#define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH] -#define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32 -#define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L] -#define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL] -#define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH] -#define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H] -#define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL] -#define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH] -#define RSCAN0TMID53 RSCAN0.TMID53.UINT32 -#define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L] -#define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL] -#define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH] -#define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H] -#define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL] -#define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH] -#define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32 -#define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L] -#define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL] -#define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH] -#define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H] -#define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL] -#define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH] -#define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32 -#define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L] -#define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL] -#define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH] -#define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H] -#define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL] -#define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH] -#define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32 -#define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L] -#define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL] -#define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH] -#define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H] -#define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL] -#define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH] -#define RSCAN0TMID54 RSCAN0.TMID54.UINT32 -#define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L] -#define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL] -#define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH] -#define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H] -#define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL] -#define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH] -#define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32 -#define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L] -#define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL] -#define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH] -#define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H] -#define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL] -#define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH] -#define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32 -#define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L] -#define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL] -#define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH] -#define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H] -#define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL] -#define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH] -#define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32 -#define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L] -#define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL] -#define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH] -#define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H] -#define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL] -#define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH] -#define RSCAN0TMID55 RSCAN0.TMID55.UINT32 -#define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L] -#define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL] -#define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH] -#define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H] -#define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL] -#define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH] -#define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32 -#define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L] -#define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL] -#define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH] -#define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H] -#define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL] -#define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH] -#define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32 -#define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L] -#define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL] -#define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH] -#define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H] -#define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL] -#define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH] -#define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32 -#define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L] -#define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL] -#define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH] -#define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H] -#define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL] -#define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH] -#define RSCAN0TMID56 RSCAN0.TMID56.UINT32 -#define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L] -#define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL] -#define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH] -#define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H] -#define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL] -#define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH] -#define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32 -#define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L] -#define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL] -#define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH] -#define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H] -#define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL] -#define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH] -#define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32 -#define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L] -#define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL] -#define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH] -#define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H] -#define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL] -#define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH] -#define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32 -#define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L] -#define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL] -#define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH] -#define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H] -#define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL] -#define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH] -#define RSCAN0TMID57 RSCAN0.TMID57.UINT32 -#define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L] -#define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL] -#define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH] -#define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H] -#define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL] -#define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH] -#define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32 -#define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L] -#define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL] -#define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH] -#define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H] -#define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL] -#define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH] -#define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32 -#define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L] -#define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL] -#define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH] -#define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H] -#define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL] -#define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH] -#define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32 -#define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L] -#define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL] -#define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH] -#define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H] -#define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL] -#define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH] -#define RSCAN0TMID58 RSCAN0.TMID58.UINT32 -#define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L] -#define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL] -#define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH] -#define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H] -#define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL] -#define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH] -#define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32 -#define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L] -#define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL] -#define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH] -#define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H] -#define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL] -#define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH] -#define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32 -#define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L] -#define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL] -#define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH] -#define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H] -#define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL] -#define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH] -#define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32 -#define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L] -#define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL] -#define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH] -#define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H] -#define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL] -#define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH] -#define RSCAN0TMID59 RSCAN0.TMID59.UINT32 -#define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L] -#define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL] -#define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH] -#define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H] -#define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL] -#define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH] -#define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32 -#define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L] -#define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL] -#define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH] -#define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H] -#define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL] -#define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH] -#define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32 -#define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L] -#define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL] -#define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH] -#define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H] -#define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL] -#define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH] -#define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32 -#define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L] -#define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL] -#define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH] -#define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H] -#define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL] -#define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH] -#define RSCAN0TMID60 RSCAN0.TMID60.UINT32 -#define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L] -#define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL] -#define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH] -#define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H] -#define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL] -#define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH] -#define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32 -#define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L] -#define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL] -#define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH] -#define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H] -#define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL] -#define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH] -#define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32 -#define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L] -#define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL] -#define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH] -#define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H] -#define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL] -#define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH] -#define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32 -#define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L] -#define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL] -#define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH] -#define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H] -#define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL] -#define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH] -#define RSCAN0TMID61 RSCAN0.TMID61.UINT32 -#define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L] -#define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL] -#define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH] -#define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H] -#define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL] -#define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH] -#define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32 -#define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L] -#define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL] -#define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH] -#define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H] -#define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL] -#define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH] -#define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32 -#define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L] -#define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL] -#define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH] -#define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H] -#define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL] -#define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH] -#define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32 -#define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L] -#define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL] -#define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH] -#define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H] -#define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL] -#define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH] -#define RSCAN0TMID62 RSCAN0.TMID62.UINT32 -#define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L] -#define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL] -#define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH] -#define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H] -#define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL] -#define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH] -#define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32 -#define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L] -#define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL] -#define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH] -#define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H] -#define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL] -#define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH] -#define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32 -#define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L] -#define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL] -#define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH] -#define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H] -#define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL] -#define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH] -#define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32 -#define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L] -#define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL] -#define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH] -#define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H] -#define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL] -#define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH] -#define RSCAN0TMID63 RSCAN0.TMID63.UINT32 -#define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L] -#define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL] -#define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH] -#define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H] -#define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL] -#define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH] -#define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32 -#define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L] -#define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL] -#define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH] -#define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H] -#define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL] -#define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH] -#define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32 -#define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L] -#define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL] -#define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH] -#define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H] -#define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL] -#define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH] -#define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32 -#define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L] -#define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL] -#define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH] -#define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H] -#define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL] -#define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH] -#define RSCAN0TMID64 RSCAN0.TMID64.UINT32 -#define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L] -#define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL] -#define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH] -#define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H] -#define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL] -#define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH] -#define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32 -#define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L] -#define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL] -#define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH] -#define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H] -#define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL] -#define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH] -#define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32 -#define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L] -#define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL] -#define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH] -#define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H] -#define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL] -#define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH] -#define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32 -#define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L] -#define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL] -#define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH] -#define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H] -#define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL] -#define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH] -#define RSCAN0TMID65 RSCAN0.TMID65.UINT32 -#define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L] -#define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL] -#define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH] -#define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H] -#define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL] -#define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH] -#define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32 -#define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L] -#define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL] -#define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH] -#define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H] -#define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL] -#define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH] -#define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32 -#define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L] -#define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL] -#define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH] -#define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H] -#define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL] -#define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH] -#define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32 -#define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L] -#define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL] -#define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH] -#define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H] -#define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL] -#define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH] -#define RSCAN0TMID66 RSCAN0.TMID66.UINT32 -#define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L] -#define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL] -#define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH] -#define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H] -#define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL] -#define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH] -#define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32 -#define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L] -#define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL] -#define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH] -#define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H] -#define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL] -#define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH] -#define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32 -#define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L] -#define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL] -#define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH] -#define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H] -#define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL] -#define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH] -#define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32 -#define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L] -#define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL] -#define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH] -#define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H] -#define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL] -#define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH] -#define RSCAN0TMID67 RSCAN0.TMID67.UINT32 -#define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L] -#define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL] -#define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH] -#define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H] -#define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL] -#define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH] -#define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32 -#define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L] -#define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL] -#define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH] -#define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H] -#define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL] -#define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH] -#define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32 -#define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L] -#define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL] -#define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH] -#define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H] -#define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL] -#define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH] -#define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32 -#define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L] -#define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL] -#define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH] -#define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H] -#define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL] -#define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH] -#define RSCAN0TMID68 RSCAN0.TMID68.UINT32 -#define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L] -#define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL] -#define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH] -#define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H] -#define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL] -#define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH] -#define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32 -#define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L] -#define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL] -#define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH] -#define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H] -#define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL] -#define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH] -#define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32 -#define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L] -#define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL] -#define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH] -#define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H] -#define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL] -#define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH] -#define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32 -#define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L] -#define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL] -#define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH] -#define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H] -#define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL] -#define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH] -#define RSCAN0TMID69 RSCAN0.TMID69.UINT32 -#define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L] -#define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL] -#define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH] -#define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H] -#define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL] -#define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH] -#define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32 -#define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L] -#define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL] -#define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH] -#define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H] -#define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL] -#define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH] -#define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32 -#define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L] -#define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL] -#define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH] -#define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H] -#define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL] -#define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH] -#define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32 -#define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L] -#define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL] -#define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH] -#define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H] -#define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL] -#define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH] -#define RSCAN0TMID70 RSCAN0.TMID70.UINT32 -#define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L] -#define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL] -#define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH] -#define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H] -#define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL] -#define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH] -#define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32 -#define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L] -#define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL] -#define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH] -#define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H] -#define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL] -#define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH] -#define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32 -#define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L] -#define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL] -#define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH] -#define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H] -#define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL] -#define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH] -#define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32 -#define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L] -#define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL] -#define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH] -#define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H] -#define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL] -#define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH] -#define RSCAN0TMID71 RSCAN0.TMID71.UINT32 -#define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L] -#define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL] -#define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH] -#define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H] -#define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL] -#define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH] -#define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32 -#define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L] -#define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL] -#define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH] -#define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H] -#define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL] -#define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH] -#define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32 -#define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L] -#define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL] -#define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH] -#define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H] -#define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL] -#define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH] -#define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32 -#define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L] -#define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL] -#define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH] -#define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H] -#define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL] -#define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH] -#define RSCAN0TMID72 RSCAN0.TMID72.UINT32 -#define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L] -#define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL] -#define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH] -#define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H] -#define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL] -#define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH] -#define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32 -#define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L] -#define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL] -#define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH] -#define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H] -#define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL] -#define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH] -#define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32 -#define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L] -#define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL] -#define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH] -#define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H] -#define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL] -#define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH] -#define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32 -#define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L] -#define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL] -#define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH] -#define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H] -#define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL] -#define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH] -#define RSCAN0TMID73 RSCAN0.TMID73.UINT32 -#define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L] -#define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL] -#define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH] -#define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H] -#define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL] -#define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH] -#define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32 -#define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L] -#define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL] -#define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH] -#define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H] -#define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL] -#define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH] -#define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32 -#define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L] -#define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL] -#define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH] -#define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H] -#define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL] -#define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH] -#define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32 -#define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L] -#define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL] -#define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH] -#define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H] -#define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL] -#define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH] -#define RSCAN0TMID74 RSCAN0.TMID74.UINT32 -#define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L] -#define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL] -#define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH] -#define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H] -#define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL] -#define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH] -#define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32 -#define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L] -#define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL] -#define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH] -#define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H] -#define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL] -#define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH] -#define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32 -#define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L] -#define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL] -#define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH] -#define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H] -#define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL] -#define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH] -#define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32 -#define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L] -#define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL] -#define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH] -#define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H] -#define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL] -#define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH] -#define RSCAN0TMID75 RSCAN0.TMID75.UINT32 -#define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L] -#define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL] -#define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH] -#define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H] -#define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL] -#define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH] -#define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32 -#define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L] -#define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL] -#define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH] -#define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H] -#define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL] -#define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH] -#define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32 -#define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L] -#define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL] -#define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH] -#define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H] -#define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL] -#define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH] -#define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32 -#define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L] -#define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL] -#define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH] -#define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H] -#define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL] -#define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH] -#define RSCAN0TMID76 RSCAN0.TMID76.UINT32 -#define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L] -#define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL] -#define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH] -#define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H] -#define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL] -#define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH] -#define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32 -#define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L] -#define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL] -#define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH] -#define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H] -#define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL] -#define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH] -#define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32 -#define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L] -#define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL] -#define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH] -#define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H] -#define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL] -#define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH] -#define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32 -#define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L] -#define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL] -#define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH] -#define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H] -#define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL] -#define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH] -#define RSCAN0TMID77 RSCAN0.TMID77.UINT32 -#define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L] -#define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL] -#define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH] -#define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H] -#define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL] -#define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH] -#define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32 -#define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L] -#define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL] -#define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH] -#define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H] -#define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL] -#define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH] -#define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32 -#define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L] -#define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL] -#define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH] -#define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H] -#define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL] -#define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH] -#define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32 -#define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L] -#define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL] -#define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH] -#define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H] -#define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL] -#define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH] -#define RSCAN0TMID78 RSCAN0.TMID78.UINT32 -#define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L] -#define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL] -#define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH] -#define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H] -#define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL] -#define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH] -#define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32 -#define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L] -#define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL] -#define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH] -#define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H] -#define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL] -#define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH] -#define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32 -#define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L] -#define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL] -#define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH] -#define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H] -#define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL] -#define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH] -#define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32 -#define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L] -#define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL] -#define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH] -#define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H] -#define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL] -#define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH] -#define RSCAN0TMID79 RSCAN0.TMID79.UINT32 -#define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L] -#define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL] -#define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH] -#define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H] -#define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL] -#define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH] -#define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32 -#define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L] -#define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL] -#define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH] -#define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H] -#define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL] -#define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH] -#define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32 -#define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L] -#define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL] -#define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH] -#define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H] -#define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL] -#define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH] -#define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32 -#define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L] -#define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL] -#define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH] -#define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H] -#define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL] -#define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH] -#define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32 -#define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L] -#define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL] -#define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH] -#define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H] -#define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL] -#define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH] -#define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32 -#define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L] -#define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL] -#define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH] -#define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H] -#define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL] -#define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH] -#define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32 -#define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L] -#define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL] -#define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH] -#define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H] -#define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL] -#define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH] -#define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32 -#define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L] -#define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL] -#define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH] -#define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H] -#define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL] -#define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH] -#define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32 -#define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L] -#define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL] -#define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH] -#define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H] -#define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL] -#define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH] /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ /* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h index 0fbd14e702..5c63e29346 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h @@ -18,27 +18,173 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : rspi_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef RSPI_IODEFINE_H #define RSPI_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -#include "reg32_t.h" +#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ +#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ +#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ +#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ +#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ -struct st_rspi -{ /* RSPI */ + +/* Start of channel array defines of RSPI */ + +/* Channel array defines of RSPI */ +/*(Sample) value = RSPI[ channel ]->SPCR; */ +#define RSPI_COUNT (5) +#define RSPI_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of RSPI */ + + +#define SPCR_0 (RSPI0.SPCR) +#define SSLP_0 (RSPI0.SSLP) +#define SPPCR_0 (RSPI0.SPPCR) +#define SPSR_0 (RSPI0.SPSR) +#define SPDR_0 (RSPI0.SPDR.UINT32) +#define SPDR_0L (RSPI0.SPDR.UINT16[R_IO_L]) +#define SPDR_0H (RSPI0.SPDR.UINT16[R_IO_H]) +#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL]) +#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH]) +#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL]) +#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH]) +#define SPSCR_0 (RSPI0.SPSCR) +#define SPSSR_0 (RSPI0.SPSSR) +#define SPBR_0 (RSPI0.SPBR) +#define SPDCR_0 (RSPI0.SPDCR) +#define SPCKD_0 (RSPI0.SPCKD) +#define SSLND_0 (RSPI0.SSLND) +#define SPND_0 (RSPI0.SPND) +#define SPCMD0_0 (RSPI0.SPCMD0) +#define SPCMD1_0 (RSPI0.SPCMD1) +#define SPCMD2_0 (RSPI0.SPCMD2) +#define SPCMD3_0 (RSPI0.SPCMD3) +#define SPBFCR_0 (RSPI0.SPBFCR) +#define SPBFDR_0 (RSPI0.SPBFDR) +#define SPCR_1 (RSPI1.SPCR) +#define SSLP_1 (RSPI1.SSLP) +#define SPPCR_1 (RSPI1.SPPCR) +#define SPSR_1 (RSPI1.SPSR) +#define SPDR_1 (RSPI1.SPDR.UINT32) +#define SPDR_1L (RSPI1.SPDR.UINT16[R_IO_L]) +#define SPDR_1H (RSPI1.SPDR.UINT16[R_IO_H]) +#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL]) +#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH]) +#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL]) +#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH]) +#define SPSCR_1 (RSPI1.SPSCR) +#define SPSSR_1 (RSPI1.SPSSR) +#define SPBR_1 (RSPI1.SPBR) +#define SPDCR_1 (RSPI1.SPDCR) +#define SPCKD_1 (RSPI1.SPCKD) +#define SSLND_1 (RSPI1.SSLND) +#define SPND_1 (RSPI1.SPND) +#define SPCMD0_1 (RSPI1.SPCMD0) +#define SPCMD1_1 (RSPI1.SPCMD1) +#define SPCMD2_1 (RSPI1.SPCMD2) +#define SPCMD3_1 (RSPI1.SPCMD3) +#define SPBFCR_1 (RSPI1.SPBFCR) +#define SPBFDR_1 (RSPI1.SPBFDR) +#define SPCR_2 (RSPI2.SPCR) +#define SSLP_2 (RSPI2.SSLP) +#define SPPCR_2 (RSPI2.SPPCR) +#define SPSR_2 (RSPI2.SPSR) +#define SPDR_2 (RSPI2.SPDR.UINT32) +#define SPDR_2L (RSPI2.SPDR.UINT16[R_IO_L]) +#define SPDR_2H (RSPI2.SPDR.UINT16[R_IO_H]) +#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL]) +#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH]) +#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL]) +#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH]) +#define SPSCR_2 (RSPI2.SPSCR) +#define SPSSR_2 (RSPI2.SPSSR) +#define SPBR_2 (RSPI2.SPBR) +#define SPDCR_2 (RSPI2.SPDCR) +#define SPCKD_2 (RSPI2.SPCKD) +#define SSLND_2 (RSPI2.SSLND) +#define SPND_2 (RSPI2.SPND) +#define SPCMD0_2 (RSPI2.SPCMD0) +#define SPCMD1_2 (RSPI2.SPCMD1) +#define SPCMD2_2 (RSPI2.SPCMD2) +#define SPCMD3_2 (RSPI2.SPCMD3) +#define SPBFCR_2 (RSPI2.SPBFCR) +#define SPBFDR_2 (RSPI2.SPBFDR) +#define SPCR_3 (RSPI3.SPCR) +#define SSLP_3 (RSPI3.SSLP) +#define SPPCR_3 (RSPI3.SPPCR) +#define SPSR_3 (RSPI3.SPSR) +#define SPDR_3 (RSPI3.SPDR.UINT32) +#define SPDR_3L (RSPI3.SPDR.UINT16[R_IO_L]) +#define SPDR_3H (RSPI3.SPDR.UINT16[R_IO_H]) +#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL]) +#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH]) +#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL]) +#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH]) +#define SPSCR_3 (RSPI3.SPSCR) +#define SPSSR_3 (RSPI3.SPSSR) +#define SPBR_3 (RSPI3.SPBR) +#define SPDCR_3 (RSPI3.SPDCR) +#define SPCKD_3 (RSPI3.SPCKD) +#define SSLND_3 (RSPI3.SSLND) +#define SPND_3 (RSPI3.SPND) +#define SPCMD0_3 (RSPI3.SPCMD0) +#define SPCMD1_3 (RSPI3.SPCMD1) +#define SPCMD2_3 (RSPI3.SPCMD2) +#define SPCMD3_3 (RSPI3.SPCMD3) +#define SPBFCR_3 (RSPI3.SPBFCR) +#define SPBFDR_3 (RSPI3.SPBFDR) +#define SPCR_4 (RSPI4.SPCR) +#define SSLP_4 (RSPI4.SSLP) +#define SPPCR_4 (RSPI4.SPPCR) +#define SPSR_4 (RSPI4.SPSR) +#define SPDR_4 (RSPI4.SPDR.UINT32) +#define SPDR_4L (RSPI4.SPDR.UINT16[R_IO_L]) +#define SPDR_4H (RSPI4.SPDR.UINT16[R_IO_H]) +#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL]) +#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH]) +#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL]) +#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH]) +#define SPSCR_4 (RSPI4.SPSCR) +#define SPSSR_4 (RSPI4.SPSSR) +#define SPBR_4 (RSPI4.SPBR) +#define SPDCR_4 (RSPI4.SPDCR) +#define SPCKD_4 (RSPI4.SPCKD) +#define SSLND_4 (RSPI4.SSLND) +#define SPND_4 (RSPI4.SPND) +#define SPCMD0_4 (RSPI4.SPCMD0) +#define SPCMD1_4 (RSPI4.SPCMD1) +#define SPCMD2_4 (RSPI4.SPCMD2) +#define SPCMD3_4 (RSPI4.SPCMD3) +#define SPBFCR_4 (RSPI4.SPBFCR) +#define SPBFDR_4 (RSPI4.SPBFDR) + +#define SPCMD_COUNT (4) + + +typedef struct st_rspi +{ + /* RSPI */ volatile uint8_t SPCR; /* SPCR */ volatile uint8_t SSLP; /* SSLP */ volatile uint8_t SPPCR; /* SPPCR */ volatile uint8_t SPSR; /* SPSR */ - union reg32_t SPDR; /* SPDR */ + union iodefine_reg32_t SPDR; /* SPDR */ volatile uint8_t SPSCR; /* SPSCR */ volatile uint8_t SPSSR; /* SPSSR */ @@ -48,7 +194,8 @@ struct st_rspi volatile uint8_t SSLND; /* SSLND */ volatile uint8_t SPND; /* SPND */ volatile uint8_t dummy1[1]; /* */ -#define SPCMD_COUNT 4 + +/* #define SPCMD_COUNT (4) */ volatile uint16_t SPCMD0; /* SPCMD0 */ volatile uint16_t SPCMD1; /* SPCMD1 */ volatile uint16_t SPCMD2; /* SPCMD2 */ @@ -57,148 +204,21 @@ struct st_rspi volatile uint8_t SPBFCR; /* SPBFCR */ volatile uint8_t dummy3[1]; /* */ volatile uint16_t SPBFDR; /* SPBFDR */ -}; +} r_io_rspi_t; -#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ -#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ -#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ -#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ -#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ +/* Channel array defines of RSPI (2)*/ +#ifdef DECLARE_RSPI_CHANNELS +volatile struct st_rspi* RSPI[ RSPI_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSPI_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSPI_CHANNELS */ +/* End of channel array defines of RSPI (2)*/ -/* Start of channnel array defines of RSPI */ - -/* Channnel array defines of RSPI */ -/*(Sample) value = RSPI[ channel ]->SPCR; */ -#define RSPI_COUNT 5 -#define RSPI_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of RSPI */ - - -#define SPCR_0 RSPI0.SPCR -#define SSLP_0 RSPI0.SSLP -#define SPPCR_0 RSPI0.SPPCR -#define SPSR_0 RSPI0.SPSR -#define SPDR_0 RSPI0.SPDR.UINT32 -#define SPDR_0L RSPI0.SPDR.UINT16[L] -#define SPDR_0H RSPI0.SPDR.UINT16[H] -#define SPDR_0LL RSPI0.SPDR.UINT8[LL] -#define SPDR_0LH RSPI0.SPDR.UINT8[LH] -#define SPDR_0HL RSPI0.SPDR.UINT8[HL] -#define SPDR_0HH RSPI0.SPDR.UINT8[HH] -#define SPSCR_0 RSPI0.SPSCR -#define SPSSR_0 RSPI0.SPSSR -#define SPBR_0 RSPI0.SPBR -#define SPDCR_0 RSPI0.SPDCR -#define SPCKD_0 RSPI0.SPCKD -#define SSLND_0 RSPI0.SSLND -#define SPND_0 RSPI0.SPND -#define SPCMD0_0 RSPI0.SPCMD0 -#define SPCMD1_0 RSPI0.SPCMD1 -#define SPCMD2_0 RSPI0.SPCMD2 -#define SPCMD3_0 RSPI0.SPCMD3 -#define SPBFCR_0 RSPI0.SPBFCR -#define SPBFDR_0 RSPI0.SPBFDR -#define SPCR_1 RSPI1.SPCR -#define SSLP_1 RSPI1.SSLP -#define SPPCR_1 RSPI1.SPPCR -#define SPSR_1 RSPI1.SPSR -#define SPDR_1 RSPI1.SPDR.UINT32 -#define SPDR_1L RSPI1.SPDR.UINT16[L] -#define SPDR_1H RSPI1.SPDR.UINT16[H] -#define SPDR_1LL RSPI1.SPDR.UINT8[LL] -#define SPDR_1LH RSPI1.SPDR.UINT8[LH] -#define SPDR_1HL RSPI1.SPDR.UINT8[HL] -#define SPDR_1HH RSPI1.SPDR.UINT8[HH] -#define SPSCR_1 RSPI1.SPSCR -#define SPSSR_1 RSPI1.SPSSR -#define SPBR_1 RSPI1.SPBR -#define SPDCR_1 RSPI1.SPDCR -#define SPCKD_1 RSPI1.SPCKD -#define SSLND_1 RSPI1.SSLND -#define SPND_1 RSPI1.SPND -#define SPCMD0_1 RSPI1.SPCMD0 -#define SPCMD1_1 RSPI1.SPCMD1 -#define SPCMD2_1 RSPI1.SPCMD2 -#define SPCMD3_1 RSPI1.SPCMD3 -#define SPBFCR_1 RSPI1.SPBFCR -#define SPBFDR_1 RSPI1.SPBFDR -#define SPCR_2 RSPI2.SPCR -#define SSLP_2 RSPI2.SSLP -#define SPPCR_2 RSPI2.SPPCR -#define SPSR_2 RSPI2.SPSR -#define SPDR_2 RSPI2.SPDR.UINT32 -#define SPDR_2L RSPI2.SPDR.UINT16[L] -#define SPDR_2H RSPI2.SPDR.UINT16[H] -#define SPDR_2LL RSPI2.SPDR.UINT8[LL] -#define SPDR_2LH RSPI2.SPDR.UINT8[LH] -#define SPDR_2HL RSPI2.SPDR.UINT8[HL] -#define SPDR_2HH RSPI2.SPDR.UINT8[HH] -#define SPSCR_2 RSPI2.SPSCR -#define SPSSR_2 RSPI2.SPSSR -#define SPBR_2 RSPI2.SPBR -#define SPDCR_2 RSPI2.SPDCR -#define SPCKD_2 RSPI2.SPCKD -#define SSLND_2 RSPI2.SSLND -#define SPND_2 RSPI2.SPND -#define SPCMD0_2 RSPI2.SPCMD0 -#define SPCMD1_2 RSPI2.SPCMD1 -#define SPCMD2_2 RSPI2.SPCMD2 -#define SPCMD3_2 RSPI2.SPCMD3 -#define SPBFCR_2 RSPI2.SPBFCR -#define SPBFDR_2 RSPI2.SPBFDR -#define SPCR_3 RSPI3.SPCR -#define SSLP_3 RSPI3.SSLP -#define SPPCR_3 RSPI3.SPPCR -#define SPSR_3 RSPI3.SPSR -#define SPDR_3 RSPI3.SPDR.UINT32 -#define SPDR_3L RSPI3.SPDR.UINT16[L] -#define SPDR_3H RSPI3.SPDR.UINT16[H] -#define SPDR_3LL RSPI3.SPDR.UINT8[LL] -#define SPDR_3LH RSPI3.SPDR.UINT8[LH] -#define SPDR_3HL RSPI3.SPDR.UINT8[HL] -#define SPDR_3HH RSPI3.SPDR.UINT8[HH] -#define SPSCR_3 RSPI3.SPSCR -#define SPSSR_3 RSPI3.SPSSR -#define SPBR_3 RSPI3.SPBR -#define SPDCR_3 RSPI3.SPDCR -#define SPCKD_3 RSPI3.SPCKD -#define SSLND_3 RSPI3.SSLND -#define SPND_3 RSPI3.SPND -#define SPCMD0_3 RSPI3.SPCMD0 -#define SPCMD1_3 RSPI3.SPCMD1 -#define SPCMD2_3 RSPI3.SPCMD2 -#define SPCMD3_3 RSPI3.SPCMD3 -#define SPBFCR_3 RSPI3.SPBFCR -#define SPBFDR_3 RSPI3.SPBFDR -#define SPCR_4 RSPI4.SPCR -#define SSLP_4 RSPI4.SSLP -#define SPPCR_4 RSPI4.SPPCR -#define SPSR_4 RSPI4.SPSR -#define SPDR_4 RSPI4.SPDR.UINT32 -#define SPDR_4L RSPI4.SPDR.UINT16[L] -#define SPDR_4H RSPI4.SPDR.UINT16[H] -#define SPDR_4LL RSPI4.SPDR.UINT8[LL] -#define SPDR_4LH RSPI4.SPDR.UINT8[LH] -#define SPDR_4HL RSPI4.SPDR.UINT8[HL] -#define SPDR_4HH RSPI4.SPDR.UINT8[HH] -#define SPSCR_4 RSPI4.SPSCR -#define SPSSR_4 RSPI4.SPSSR -#define SPBR_4 RSPI4.SPBR -#define SPDCR_4 RSPI4.SPDCR -#define SPCKD_4 RSPI4.SPCKD -#define SSLND_4 RSPI4.SSLND -#define SPND_4 RSPI4.SPND -#define SPCMD0_4 RSPI4.SPCMD0 -#define SPCMD1_4 RSPI4.SPCMD1 -#define SPCMD2_4 RSPI4.SPCMD2 -#define SPCMD3_4 RSPI4.SPCMD3 -#define SPBFCR_4 RSPI4.SPBFCR -#define SPBFDR_4 RSPI4.SPBFDR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h index 6cfb46dde3..1df2c7c3d1 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h @@ -18,20 +18,50 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : rtc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef RTC_IODEFINE_H #define RTC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_rtc -{ /* RTC */ +#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */ + + +#define RTCR64CNT (RTC.R64CNT) +#define RTCRSECCNT (RTC.RSECCNT) +#define RTCRMINCNT (RTC.RMINCNT) +#define RTCRHRCNT (RTC.RHRCNT) +#define RTCRWKCNT (RTC.RWKCNT) +#define RTCRDAYCNT (RTC.RDAYCNT) +#define RTCRMONCNT (RTC.RMONCNT) +#define RTCRYRCNT (RTC.RYRCNT) +#define RTCRSECAR (RTC.RSECAR) +#define RTCRMINAR (RTC.RMINAR) +#define RTCRHRAR (RTC.RHRAR) +#define RTCRWKAR (RTC.RWKAR) +#define RTCRDAYAR (RTC.RDAYAR) +#define RTCRMONAR (RTC.RMONAR) +#define RTCRCR1 (RTC.RCR1) +#define RTCRCR2 (RTC.RCR2) +#define RTCRYRAR (RTC.RYRAR) +#define RTCRCR3 (RTC.RCR3) +#define RTCRCR5 (RTC.RCR5) +#define RTCRFRH (RTC.RFRH) +#define RTCRFRL (RTC.RFRL) + + +typedef struct st_rtc +{ + /* RTC */ volatile uint8_t R64CNT; /* R64CNT */ volatile uint8_t dummy537[1]; /* */ volatile uint8_t RSECCNT; /* RSECCNT */ @@ -71,32 +101,11 @@ struct st_rtc volatile uint8_t dummy554[3]; /* */ volatile uint16_t RFRH; /* RFRH */ volatile uint16_t RFRL; /* RFRL */ -}; +} r_io_rtc_t; -#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */ - - -#define RTCR64CNT RTC.R64CNT -#define RTCRSECCNT RTC.RSECCNT -#define RTCRMINCNT RTC.RMINCNT -#define RTCRHRCNT RTC.RHRCNT -#define RTCRWKCNT RTC.RWKCNT -#define RTCRDAYCNT RTC.RDAYCNT -#define RTCRMONCNT RTC.RMONCNT -#define RTCRYRCNT RTC.RYRCNT -#define RTCRSECAR RTC.RSECAR -#define RTCRMINAR RTC.RMINAR -#define RTCRHRAR RTC.RHRAR -#define RTCRWKAR RTC.RWKAR -#define RTCRDAYAR RTC.RDAYAR -#define RTCRMONAR RTC.RMONAR -#define RTCRCR1 RTC.RCR1 -#define RTCRCR2 RTC.RCR2 -#define RTCRYRAR RTC.RYRAR -#define RTCRCR3 RTC.RCR3 -#define RTCRCR5 RTC.RCR5 -#define RTCRFRH RTC.RFRH -#define RTCRFRL RTC.RFRL /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h index 9a710604ce..de594577e2 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h @@ -18,21 +18,137 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : scif_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SCIF_IODEFINE_H #define SCIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ /* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_scif -{ /* SCIF */ +#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */ +#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */ +#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */ +#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */ +#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */ +#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */ +#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */ +#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */ + + +/* Start of channel array defines of SCIF */ + +/* Channel array defines of SCIF */ +/*(Sample) value = SCIF[ channel ]->SCSMR; */ +#define SCIF_COUNT (8) +#define SCIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SCIF */ + + +#define SCSMR_0 (SCIF0.SCSMR) +#define SCBRR_0 (SCIF0.SCBRR) +#define SCSCR_0 (SCIF0.SCSCR) +#define SCFTDR_0 (SCIF0.SCFTDR) +#define SCFSR_0 (SCIF0.SCFSR) +#define SCFRDR_0 (SCIF0.SCFRDR) +#define SCFCR_0 (SCIF0.SCFCR) +#define SCFDR_0 (SCIF0.SCFDR) +#define SCSPTR_0 (SCIF0.SCSPTR) +#define SCLSR_0 (SCIF0.SCLSR) +#define SCEMR_0 (SCIF0.SCEMR) +#define SCSMR_1 (SCIF1.SCSMR) +#define SCBRR_1 (SCIF1.SCBRR) +#define SCSCR_1 (SCIF1.SCSCR) +#define SCFTDR_1 (SCIF1.SCFTDR) +#define SCFSR_1 (SCIF1.SCFSR) +#define SCFRDR_1 (SCIF1.SCFRDR) +#define SCFCR_1 (SCIF1.SCFCR) +#define SCFDR_1 (SCIF1.SCFDR) +#define SCSPTR_1 (SCIF1.SCSPTR) +#define SCLSR_1 (SCIF1.SCLSR) +#define SCEMR_1 (SCIF1.SCEMR) +#define SCSMR_2 (SCIF2.SCSMR) +#define SCBRR_2 (SCIF2.SCBRR) +#define SCSCR_2 (SCIF2.SCSCR) +#define SCFTDR_2 (SCIF2.SCFTDR) +#define SCFSR_2 (SCIF2.SCFSR) +#define SCFRDR_2 (SCIF2.SCFRDR) +#define SCFCR_2 (SCIF2.SCFCR) +#define SCFDR_2 (SCIF2.SCFDR) +#define SCSPTR_2 (SCIF2.SCSPTR) +#define SCLSR_2 (SCIF2.SCLSR) +#define SCEMR_2 (SCIF2.SCEMR) +#define SCSMR_3 (SCIF3.SCSMR) +#define SCBRR_3 (SCIF3.SCBRR) +#define SCSCR_3 (SCIF3.SCSCR) +#define SCFTDR_3 (SCIF3.SCFTDR) +#define SCFSR_3 (SCIF3.SCFSR) +#define SCFRDR_3 (SCIF3.SCFRDR) +#define SCFCR_3 (SCIF3.SCFCR) +#define SCFDR_3 (SCIF3.SCFDR) +#define SCSPTR_3 (SCIF3.SCSPTR) +#define SCLSR_3 (SCIF3.SCLSR) +#define SCEMR_3 (SCIF3.SCEMR) +#define SCSMR_4 (SCIF4.SCSMR) +#define SCBRR_4 (SCIF4.SCBRR) +#define SCSCR_4 (SCIF4.SCSCR) +#define SCFTDR_4 (SCIF4.SCFTDR) +#define SCFSR_4 (SCIF4.SCFSR) +#define SCFRDR_4 (SCIF4.SCFRDR) +#define SCFCR_4 (SCIF4.SCFCR) +#define SCFDR_4 (SCIF4.SCFDR) +#define SCSPTR_4 (SCIF4.SCSPTR) +#define SCLSR_4 (SCIF4.SCLSR) +#define SCEMR_4 (SCIF4.SCEMR) +#define SCSMR_5 (SCIF5.SCSMR) +#define SCBRR_5 (SCIF5.SCBRR) +#define SCSCR_5 (SCIF5.SCSCR) +#define SCFTDR_5 (SCIF5.SCFTDR) +#define SCFSR_5 (SCIF5.SCFSR) +#define SCFRDR_5 (SCIF5.SCFRDR) +#define SCFCR_5 (SCIF5.SCFCR) +#define SCFDR_5 (SCIF5.SCFDR) +#define SCSPTR_5 (SCIF5.SCSPTR) +#define SCLSR_5 (SCIF5.SCLSR) +#define SCEMR_5 (SCIF5.SCEMR) +#define SCSMR_6 (SCIF6.SCSMR) +#define SCBRR_6 (SCIF6.SCBRR) +#define SCSCR_6 (SCIF6.SCSCR) +#define SCFTDR_6 (SCIF6.SCFTDR) +#define SCFSR_6 (SCIF6.SCFSR) +#define SCFRDR_6 (SCIF6.SCFRDR) +#define SCFCR_6 (SCIF6.SCFCR) +#define SCFDR_6 (SCIF6.SCFDR) +#define SCSPTR_6 (SCIF6.SCSPTR) +#define SCLSR_6 (SCIF6.SCLSR) +#define SCEMR_6 (SCIF6.SCEMR) +#define SCSMR_7 (SCIF7.SCSMR) +#define SCBRR_7 (SCIF7.SCBRR) +#define SCSCR_7 (SCIF7.SCSCR) +#define SCFTDR_7 (SCIF7.SCFTDR) +#define SCFSR_7 (SCIF7.SCFSR) +#define SCFRDR_7 (SCIF7.SCFRDR) +#define SCFCR_7 (SCIF7.SCFCR) +#define SCFDR_7 (SCIF7.SCFDR) +#define SCSPTR_7 (SCIF7.SCSPTR) +#define SCLSR_7 (SCIF7.SCLSR) +#define SCEMR_7 (SCIF7.SCEMR) + + +typedef struct st_scif +{ + /* SCIF */ volatile uint16_t SCSMR; /* SCSMR */ volatile uint8_t dummy1[2]; /* */ volatile uint8_t SCBRR; /* SCBRR */ @@ -54,129 +170,21 @@ struct st_scif volatile uint16_t SCLSR; /* SCLSR */ volatile uint8_t dummy10[2]; /* */ volatile uint16_t SCEMR; /* SCEMR */ -}; +} r_io_scif_t; -#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */ -#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */ -#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */ -#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */ -#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */ -#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */ -#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */ -#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */ - -#define P_SCIF0 (0xE8007000uL) /* SCIF0 */ -#define P_SCIF1 (0xE8007800uL) /* SCIF1 */ -#define P_SCIF2 (0xE8008000uL) /* SCIF2 */ -#define P_SCIF3 (0xE8008800uL) /* SCIF3 */ -#define P_SCIF4 (0xE8009000uL) /* SCIF4 */ -#define P_SCIF5 (0xE8009800uL) /* SCIF5 */ -#define P_SCIF6 (0xE800A000uL) /* SCIF6 */ -#define P_SCIF7 (0xE800A800uL) /* SCIF7 */ +/* Channel array defines of SCIF (2)*/ +#ifdef DECLARE_SCIF_CHANNELS +volatile struct st_scif* SCIF[ SCIF_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCIF_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCIF_CHANNELS */ +/* End of channel array defines of SCIF (2)*/ -/* Start of channnel array defines of SCIF */ - -/* Channnel array defines of SCIF */ -/*(Sample) value = SCIF[ channel ]->SCSMR; */ -#define SCIF_COUNT 8 -#define SCIF_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of SCIF */ - - -#define SCSMR_0 SCIF0.SCSMR -#define SCBRR_0 SCIF0.SCBRR -#define SCSCR_0 SCIF0.SCSCR -#define SCFTDR_0 SCIF0.SCFTDR -#define SCFSR_0 SCIF0.SCFSR -#define SCFRDR_0 SCIF0.SCFRDR -#define SCFCR_0 SCIF0.SCFCR -#define SCFDR_0 SCIF0.SCFDR -#define SCSPTR_0 SCIF0.SCSPTR -#define SCLSR_0 SCIF0.SCLSR -#define SCEMR_0 SCIF0.SCEMR -#define SCSMR_1 SCIF1.SCSMR -#define SCBRR_1 SCIF1.SCBRR -#define SCSCR_1 SCIF1.SCSCR -#define SCFTDR_1 SCIF1.SCFTDR -#define SCFSR_1 SCIF1.SCFSR -#define SCFRDR_1 SCIF1.SCFRDR -#define SCFCR_1 SCIF1.SCFCR -#define SCFDR_1 SCIF1.SCFDR -#define SCSPTR_1 SCIF1.SCSPTR -#define SCLSR_1 SCIF1.SCLSR -#define SCEMR_1 SCIF1.SCEMR -#define SCSMR_2 SCIF2.SCSMR -#define SCBRR_2 SCIF2.SCBRR -#define SCSCR_2 SCIF2.SCSCR -#define SCFTDR_2 SCIF2.SCFTDR -#define SCFSR_2 SCIF2.SCFSR -#define SCFRDR_2 SCIF2.SCFRDR -#define SCFCR_2 SCIF2.SCFCR -#define SCFDR_2 SCIF2.SCFDR -#define SCSPTR_2 SCIF2.SCSPTR -#define SCLSR_2 SCIF2.SCLSR -#define SCEMR_2 SCIF2.SCEMR -#define SCSMR_3 SCIF3.SCSMR -#define SCBRR_3 SCIF3.SCBRR -#define SCSCR_3 SCIF3.SCSCR -#define SCFTDR_3 SCIF3.SCFTDR -#define SCFSR_3 SCIF3.SCFSR -#define SCFRDR_3 SCIF3.SCFRDR -#define SCFCR_3 SCIF3.SCFCR -#define SCFDR_3 SCIF3.SCFDR -#define SCSPTR_3 SCIF3.SCSPTR -#define SCLSR_3 SCIF3.SCLSR -#define SCEMR_3 SCIF3.SCEMR -#define SCSMR_4 SCIF4.SCSMR -#define SCBRR_4 SCIF4.SCBRR -#define SCSCR_4 SCIF4.SCSCR -#define SCFTDR_4 SCIF4.SCFTDR -#define SCFSR_4 SCIF4.SCFSR -#define SCFRDR_4 SCIF4.SCFRDR -#define SCFCR_4 SCIF4.SCFCR -#define SCFDR_4 SCIF4.SCFDR -#define SCSPTR_4 SCIF4.SCSPTR -#define SCLSR_4 SCIF4.SCLSR -#define SCEMR_4 SCIF4.SCEMR -#define SCSMR_5 SCIF5.SCSMR -#define SCBRR_5 SCIF5.SCBRR -#define SCSCR_5 SCIF5.SCSCR -#define SCFTDR_5 SCIF5.SCFTDR -#define SCFSR_5 SCIF5.SCFSR -#define SCFRDR_5 SCIF5.SCFRDR -#define SCFCR_5 SCIF5.SCFCR -#define SCFDR_5 SCIF5.SCFDR -#define SCSPTR_5 SCIF5.SCSPTR -#define SCLSR_5 SCIF5.SCLSR -#define SCEMR_5 SCIF5.SCEMR -#define SCSMR_6 SCIF6.SCSMR -#define SCBRR_6 SCIF6.SCBRR -#define SCSCR_6 SCIF6.SCSCR -#define SCFTDR_6 SCIF6.SCFTDR -#define SCFSR_6 SCIF6.SCFSR -#define SCFRDR_6 SCIF6.SCFRDR -#define SCFCR_6 SCIF6.SCFCR -#define SCFDR_6 SCIF6.SCFDR -#define SCSPTR_6 SCIF6.SCSPTR -#define SCLSR_6 SCIF6.SCLSR -#define SCEMR_6 SCIF6.SCEMR -#define SCSMR_7 SCIF7.SCSMR -#define SCBRR_7 SCIF7.SCBRR -#define SCSCR_7 SCIF7.SCSCR -#define SCFTDR_7 SCIF7.SCFTDR -#define SCFSR_7 SCIF7.SCFSR -#define SCFRDR_7 SCIF7.SCFRDR -#define SCFCR_7 SCIF7.SCFCR -#define SCFDR_7 SCIF7.SCFDR -#define SCSPTR_7 SCIF7.SCSPTR -#define SCLSR_7 SCIF7.SCLSR -#define SCEMR_7 SCIF7.SCEMR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ /* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h index 2ddf1e61d9..fad306aca1 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h @@ -18,20 +18,63 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : scim_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SCIM_IODEFINE_H #define SCIM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_scim -{ /* SCIM */ +#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ +#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ + + +/* Start of channel array defines of SCIM */ + +/* Channel array defines of SCIM */ +/*(Sample) value = SCIM[ channel ]->SMR; */ +#define SCIM_COUNT (2) +#define SCIM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIM0, &SCIM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SCIM */ + + +#define SMR0 (SCIM0.SMR) +#define BRR0 (SCIM0.BRR) +#define SCR0 (SCIM0.SCR) +#define TDR0 (SCIM0.TDR) +#define SSR0 (SCIM0.SSR) +#define RDR0 (SCIM0.RDR) +#define SCMR0 (SCIM0.SCMR) +#define SEMR0 (SCIM0.SEMR) +#define SNFR0 (SCIM0.SNFR) +#define SECR0 (SCIM0.SECR) +#define SMR1 (SCIM1.SMR) +#define BRR1 (SCIM1.BRR) +#define SCR1 (SCIM1.SCR) +#define TDR1 (SCIM1.TDR) +#define SSR1 (SCIM1.SSR) +#define RDR1 (SCIM1.RDR) +#define SCMR1 (SCIM1.SCMR) +#define SEMR1 (SCIM1.SEMR) +#define SNFR1 (SCIM1.SNFR) +#define SECR1 (SCIM1.SECR) + + +typedef struct st_scim +{ + /* SCIM */ volatile uint8_t SMR; /* SMR */ volatile uint8_t BRR; /* BRR */ volatile uint8_t SCR; /* SCR */ @@ -43,45 +86,21 @@ struct st_scim volatile uint8_t SNFR; /* SNFR */ volatile uint8_t dummy1[4]; /* */ volatile uint8_t SECR; /* SECR */ -}; +} r_io_scim_t; -#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ -#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ +/* Channel array defines of SCIM (2)*/ +#ifdef DECLARE_SCIM_CHANNELS +volatile struct st_scim* SCIM[ SCIM_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCIM_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCIM_CHANNELS */ +/* End of channel array defines of SCIM (2)*/ -/* Start of channnel array defines of SCIM */ - -/* Channnel array defines of SCIM */ -/*(Sample) value = SCIM[ channel ]->SMR; */ -#define SCIM_COUNT 2 -#define SCIM_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCIM0, &SCIM1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of SCIM */ - - -#define SMR0 SCIM0.SMR -#define BRR0 SCIM0.BRR -#define SCR0 SCIM0.SCR -#define TDR0 SCIM0.TDR -#define SSR0 SCIM0.SSR -#define RDR0 SCIM0.RDR -#define SCMR0 SCIM0.SCMR -#define SEMR0 SCIM0.SEMR -#define SNFR0 SCIM0.SNFR -#define SECR0 SCIM0.SECR -#define SMR1 SCIM1.SMR -#define BRR1 SCIM1.BRR -#define SCR1 SCIM1.SCR -#define TDR1 SCIM1.TDR -#define SSR1 SCIM1.SSR -#define RDR1 SCIM1.RDR -#define SCMR1 SCIM1.SCMR -#define SEMR1 SCIM1.SEMR -#define SNFR1 SCIM1.SNFR -#define SECR1 SCIM1.SECR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h index a6d5646dcc..4293ec4277 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h @@ -18,61 +18,427 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : scux_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SCUX_IODEFINE_H #define SCUX_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_scux -{ /* SCUX */ +#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ + + +/* Start of channel array defines of SCUX */ + +/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT (4) +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ +#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ +#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ +#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ + + +/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT (2) +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ +#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ + + +/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT (4) +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ +#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ +#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ +#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ + + +/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT (4) +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ +#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ +#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ +#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ + + +/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT (4) +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ +#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ +#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ +#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ + + +/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT (4) +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ +#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ +#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ +#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ + +/* End of channel array defines of SCUX */ + + +#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0) +#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0) +#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1) +#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1) +#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2) +#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2) +#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3) +#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3) +#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0) +#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0) +#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1) +#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1) +#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2) +#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2) +#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3) +#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3) +#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0) +#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0) +#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0) +#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0) +#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0) +#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0) +#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0) +#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1) +#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1) +#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1) +#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1) +#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1) +#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1) +#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1) +#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2) +#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2) +#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2) +#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2) +#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2) +#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2) +#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2) +#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3) +#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3) +#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3) +#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3) +#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3) +#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3) +#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3) +#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0) +#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0) +#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0) +#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0) +#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0) +#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0) +#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1) +#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1) +#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1) +#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1) +#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1) +#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1) +#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2) +#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2) +#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2) +#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2) +#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2) +#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2) +#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3) +#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3) +#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3) +#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3) +#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3) +#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3) +#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0) +#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0) +#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0) +#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0) +#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0) +#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0) +#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0) +#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0) +#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0) +#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0) +#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0) +#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0) +#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0) +#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0) +#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0) +#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0) +#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0) +#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0) +#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0) +#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0) +#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0) +#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0) +#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0) +#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0) +#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0) +#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1) +#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1) +#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1) +#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1) +#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1) +#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1) +#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1) +#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1) +#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1) +#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1) +#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1) +#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1) +#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1) +#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1) +#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1) +#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1) +#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1) +#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1) +#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1) +#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1) +#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1) +#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1) +#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1) +#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1) +#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1) +#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0) +#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0) +#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0) +#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0) +#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0) +#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0) +#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0) +#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0) +#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0) +#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0) +#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0) +#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0) +#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0) +#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0) +#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0) +#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0) +#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0) +#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0) +#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0) +#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0) +#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0) +#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1) +#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1) +#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1) +#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1) +#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1) +#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1) +#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1) +#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1) +#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1) +#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1) +#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1) +#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1) +#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1) +#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1) +#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1) +#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1) +#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1) +#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1) +#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1) +#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1) +#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1) +#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2) +#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2) +#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2) +#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2) +#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2) +#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2) +#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2) +#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2) +#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2) +#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2) +#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2) +#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2) +#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2) +#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2) +#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2) +#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2) +#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2) +#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2) +#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2) +#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2) +#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2) +#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3) +#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3) +#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3) +#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3) +#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3) +#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3) +#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3) +#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3) +#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3) +#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3) +#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3) +#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3) +#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3) +#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3) +#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3) +#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3) +#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3) +#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3) +#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3) +#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3) +#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3) +#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0) +#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0) +#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0) +#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0) +#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0) +#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0) +#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0) +#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0) +#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0) +#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0) +#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0) +#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM) +#define SCUXDMACR_CIM (SCUX.DMACR_CIM) +#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32) +#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L]) +#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H]) +#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32) +#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L]) +#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H]) +#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32) +#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L]) +#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H]) +#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32) +#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L]) +#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H]) +#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32) +#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L]) +#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H]) +#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32) +#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L]) +#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H]) +#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32) +#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L]) +#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H]) +#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32) +#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L]) +#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H]) +#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM) +#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM) +#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM) +#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM) +#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM) +#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM) +#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM) +#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM) +#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM) +#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM) +#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM) +#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM) +#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM) +#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM) +#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM) +#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM) + +#define SCUX_DMATDnCIM_COUNT (4) +#define SCUX_DMATUnCIM_COUNT (4) +#define SCUX_FDTSELnCIM_COUNT (4) +#define SCUX_FUTSELnCIM_COUNT (4) +#define SCUX_SRCRSELnCIM_COUNT (4) + + +typedef struct st_scux +{ + /* SCUX */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ volatile uint8_t dummy259[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */ volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */ volatile uint8_t dummy260[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */ volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */ volatile uint8_t dummy261[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */ volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */ volatile uint8_t dummy262[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ volatile uint8_t dummy263[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */ volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */ volatile uint8_t dummy264[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */ volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */ volatile uint8_t dummy265[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */ volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */ volatile uint8_t dummy266[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ @@ -82,8 +448,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ volatile uint8_t dummy267[4]; /* */ volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy268[224]; /* */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */ volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */ @@ -93,8 +461,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */ volatile uint8_t dummy269[4]; /* */ volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy270[224]; /* */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */ volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */ @@ -104,8 +474,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */ volatile uint8_t dummy271[4]; /* */ volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy272[224]; /* */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */ volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */ @@ -115,8 +487,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */ volatile uint8_t dummy273[4]; /* */ volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy274[224]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ @@ -125,8 +499,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ volatile uint8_t dummy275[4]; /* */ volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy276[228]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */ volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */ @@ -135,8 +511,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */ volatile uint8_t dummy277[4]; /* */ volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy278[228]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */ volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */ @@ -145,8 +523,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */ volatile uint8_t dummy279[4]; /* */ volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy280[228]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */ volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */ @@ -155,8 +535,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */ volatile uint8_t dummy281[4]; /* */ volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy282[228]; /* */ + /* start of struct st_scux_from_srcir0_2src0_n */ volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ @@ -185,8 +567,10 @@ struct st_scux volatile uint8_t dummy284[4]; /* */ volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ + /* end of struct st_scux_from_srcir0_2src0_n */ volatile uint8_t dummy285[148]; /* */ + /* start of struct st_scux_from_srcir0_2src0_n */ volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */ volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */ @@ -215,8 +599,10 @@ struct st_scux volatile uint8_t dummy287[4]; /* */ volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */ volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */ + /* end of struct st_scux_from_srcir0_2src0_n */ volatile uint8_t dummy288[148]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ @@ -240,8 +626,10 @@ struct st_scux volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ volatile uint8_t dummy289[4]; /* */ volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy290[168]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */ volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */ @@ -265,8 +653,10 @@ struct st_scux volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */ volatile uint8_t dummy291[4]; /* */ volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy292[168]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */ volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */ @@ -290,8 +680,10 @@ struct st_scux volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */ volatile uint8_t dummy293[4]; /* */ volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy294[168]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */ volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */ @@ -315,6 +707,7 @@ struct st_scux volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */ volatile uint8_t dummy295[4]; /* */ volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy296[168]; /* */ volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */ @@ -331,12 +724,14 @@ struct st_scux volatile uint8_t dummy297[212]; /* */ volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */ volatile uint32_t DMACR_CIM; /* DMACR_CIM */ -#define SCUX_DMATDn_CIM_COUNT 4 + +/* #define SCUX_DMATDnCIM_COUNT (4) */ union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */ union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */ union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */ union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */ -#define SCUX_DMATUn_CIM_COUNT 4 + +/* #define SCUX_DMATUnCIM_COUNT (4) */ union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */ union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */ union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */ @@ -344,45 +739,51 @@ struct st_scux volatile uint8_t dummy298[16]; /* */ volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */ -#define SCUX_FDTSELn_CIM_COUNT 4 + +/* #define SCUX_FDTSELnCIM_COUNT (4) */ volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */ volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */ volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */ volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */ -#define SCUX_FUTSELn_CIM_COUNT 4 + +/* #define SCUX_FUTSELnCIM_COUNT (4) */ volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */ volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */ volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */ volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */ volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */ volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */ -#define SCUX_SRCRSELn_CIM_COUNT 4 + +/* #define SCUX_SRCRSELnCIM_COUNT (4) */ volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */ volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */ volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */ volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */ volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */ -}; +} r_io_scux_t; -struct st_scux_from_ipcir_ipc0_n +typedef struct st_scux_from_ipcir_ipc0_n { + volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ volatile uint8_t dummy1[248]; /* */ -}; +} r_io_scux_from_ipcir_ipc0_n_t; -struct st_scux_from_opcir_opc0_n +typedef struct st_scux_from_opcir_opc0_n { + volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ volatile uint8_t dummy1[248]; /* */ -}; +} r_io_scux_from_opcir_opc0_n_t; -struct st_scux_from_ffdir_ffd0_n +typedef struct st_scux_from_ffdir_ffd0_n { + volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ @@ -391,11 +792,12 @@ struct st_scux_from_ffdir_ffd0_n volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ volatile uint8_t dummy1[4]; /* */ volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ -}; +} r_io_scux_from_ffdir_ffd0_n_t; -struct st_scux_from_ffuir_ffu0_n +typedef struct st_scux_from_ffuir_ffu0_n { + volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ @@ -403,11 +805,12 @@ struct st_scux_from_ffuir_ffu0_n volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ volatile uint8_t dummy1[4]; /* */ volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ -}; +} r_io_scux_from_ffuir_ffu0_n_t; -struct st_scux_from_srcir0_2src0_n +typedef struct st_scux_from_srcir0_2src0_n { + volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ @@ -435,11 +838,12 @@ struct st_scux_from_srcir0_2src0_n volatile uint8_t dummy2[4]; /* */ volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ -}; +} r_io_scux_from_srcir0_2src0_n_t; -struct st_scux_from_dvuir_dvu0_n +typedef struct st_scux_from_dvuir_dvu0_n { + volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ @@ -462,347 +866,56 @@ struct st_scux_from_dvuir_dvu0_n volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ volatile uint8_t dummy1[4]; /* */ volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ -}; +} r_io_scux_from_dvuir_dvu0_n_t; -#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ +/* Channel array defines of SCUX (2)*/ +#ifdef DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS +volatile struct st_scux_from_dvuir_dvu0_n* SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_srcir0_2src0_n* SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ffuir_ffu0_n* SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ffdir_ffd0_n* SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_opcir_opc0_n* SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ipcir_ipc0_n* SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */ +/* End of channel array defines of SCUX (2)*/ -/* Start of channnel array defines of SCUX */ - -/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ -#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4 -#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ -#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ -#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ -#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ - - -/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ -#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2 -#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ -#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ - - -/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ -#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4 -#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ -#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ -#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ -#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ - - -/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ -#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4 -#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ -#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ -#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ -#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ - - -/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ -#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4 -#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ -#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ -#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ -#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ - - -/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ -#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4 -#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ -#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ -#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ -#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ - -/* End of channnel array defines of SCUX */ - - -#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0 -#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0 -#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1 -#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1 -#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2 -#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2 -#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3 -#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3 -#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0 -#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0 -#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1 -#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1 -#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2 -#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2 -#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3 -#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3 -#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0 -#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0 -#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0 -#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0 -#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0 -#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0 -#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0 -#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1 -#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1 -#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1 -#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1 -#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1 -#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1 -#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1 -#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2 -#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2 -#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2 -#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2 -#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2 -#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2 -#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2 -#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3 -#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3 -#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3 -#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3 -#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3 -#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3 -#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3 -#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0 -#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0 -#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0 -#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0 -#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0 -#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0 -#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1 -#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1 -#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1 -#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1 -#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1 -#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1 -#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2 -#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2 -#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2 -#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2 -#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2 -#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2 -#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3 -#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3 -#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3 -#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3 -#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3 -#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3 -#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0 -#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0 -#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0 -#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0 -#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0 -#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0 -#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0 -#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0 -#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0 -#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0 -#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0 -#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0 -#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0 -#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0 -#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0 -#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0 -#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0 -#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0 -#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0 -#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0 -#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0 -#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0 -#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0 -#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0 -#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0 -#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1 -#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1 -#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1 -#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1 -#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1 -#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1 -#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1 -#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1 -#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1 -#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1 -#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1 -#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1 -#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1 -#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1 -#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1 -#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1 -#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1 -#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1 -#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1 -#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1 -#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1 -#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1 -#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1 -#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1 -#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1 -#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0 -#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0 -#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0 -#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0 -#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0 -#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0 -#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0 -#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0 -#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0 -#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0 -#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0 -#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0 -#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0 -#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0 -#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0 -#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0 -#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0 -#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0 -#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0 -#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0 -#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0 -#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1 -#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1 -#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1 -#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1 -#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1 -#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1 -#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1 -#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1 -#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1 -#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1 -#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1 -#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1 -#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1 -#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1 -#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1 -#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1 -#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1 -#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1 -#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1 -#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1 -#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1 -#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2 -#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2 -#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2 -#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2 -#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2 -#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2 -#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2 -#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2 -#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2 -#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2 -#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2 -#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2 -#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2 -#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2 -#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2 -#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2 -#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2 -#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2 -#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2 -#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2 -#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2 -#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3 -#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3 -#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3 -#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3 -#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3 -#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3 -#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3 -#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3 -#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3 -#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3 -#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3 -#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3 -#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3 -#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3 -#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3 -#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3 -#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3 -#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3 -#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3 -#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3 -#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3 -#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0 -#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0 -#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0 -#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0 -#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0 -#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0 -#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0 -#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0 -#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0 -#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0 -#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0 -#define SCUXSWRSR_CIM SCUX.SWRSR_CIM -#define SCUXDMACR_CIM SCUX.DMACR_CIM -#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32 -#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L] -#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H] -#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32 -#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L] -#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H] -#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32 -#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L] -#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H] -#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32 -#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L] -#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H] -#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32 -#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L] -#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H] -#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32 -#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L] -#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H] -#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32 -#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L] -#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H] -#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32 -#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L] -#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H] -#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM -#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM -#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM -#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM -#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM -#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM -#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM -#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM -#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM -#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM -#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM -#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM -#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM -#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM -#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM -#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h index 78abfc08e8..dd6dee41d8 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h @@ -18,27 +18,20 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : sdg_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SDG_IODEFINE_H #define SDG_IODEFINE_H - -struct st_sdg -{ /* SDG */ - volatile uint8_t SGCR1; /* SGCR1 */ - volatile uint8_t SGCSR; /* SGCSR */ - volatile uint8_t SGCR2; /* SGCR2 */ - volatile uint8_t SGLR; /* SGLR */ - volatile uint8_t SGTFR; /* SGTFR */ - volatile uint8_t SGSFR; /* SGSFR */ -}; - +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ #define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */ #define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */ @@ -46,41 +39,69 @@ struct st_sdg #define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */ -/* Start of channnel array defines of SDG */ +/* Start of channel array defines of SDG */ -/* Channnel array defines of SDG */ +/* Channel array defines of SDG */ /*(Sample) value = SDG[ channel ]->SGCR1; */ -#define SDG_COUNT 4 +#define SDG_COUNT (4) #define SDG_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &SDG0, &SDG1, &SDG2, &SDG3 \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of SDG */ +/* End of channel array defines of SDG */ -#define SGCR1_0 SDG0.SGCR1 -#define SGCSR_0 SDG0.SGCSR -#define SGCR2_0 SDG0.SGCR2 -#define SGLR_0 SDG0.SGLR -#define SGTFR_0 SDG0.SGTFR -#define SGSFR_0 SDG0.SGSFR -#define SGCR1_1 SDG1.SGCR1 -#define SGCSR_1 SDG1.SGCSR -#define SGCR2_1 SDG1.SGCR2 -#define SGLR_1 SDG1.SGLR -#define SGTFR_1 SDG1.SGTFR -#define SGSFR_1 SDG1.SGSFR -#define SGCR1_2 SDG2.SGCR1 -#define SGCSR_2 SDG2.SGCSR -#define SGCR2_2 SDG2.SGCR2 -#define SGLR_2 SDG2.SGLR -#define SGTFR_2 SDG2.SGTFR -#define SGSFR_2 SDG2.SGSFR -#define SGCR1_3 SDG3.SGCR1 -#define SGCSR_3 SDG3.SGCSR -#define SGCR2_3 SDG3.SGCR2 -#define SGLR_3 SDG3.SGLR -#define SGTFR_3 SDG3.SGTFR -#define SGSFR_3 SDG3.SGSFR +#define SGCR1_0 (SDG0.SGCR1) +#define SGCSR_0 (SDG0.SGCSR) +#define SGCR2_0 (SDG0.SGCR2) +#define SGLR_0 (SDG0.SGLR) +#define SGTFR_0 (SDG0.SGTFR) +#define SGSFR_0 (SDG0.SGSFR) +#define SGCR1_1 (SDG1.SGCR1) +#define SGCSR_1 (SDG1.SGCSR) +#define SGCR2_1 (SDG1.SGCR2) +#define SGLR_1 (SDG1.SGLR) +#define SGTFR_1 (SDG1.SGTFR) +#define SGSFR_1 (SDG1.SGSFR) +#define SGCR1_2 (SDG2.SGCR1) +#define SGCSR_2 (SDG2.SGCSR) +#define SGCR2_2 (SDG2.SGCR2) +#define SGLR_2 (SDG2.SGLR) +#define SGTFR_2 (SDG2.SGTFR) +#define SGSFR_2 (SDG2.SGSFR) +#define SGCR1_3 (SDG3.SGCR1) +#define SGCSR_3 (SDG3.SGCSR) +#define SGCR2_3 (SDG3.SGCR2) +#define SGLR_3 (SDG3.SGLR) +#define SGTFR_3 (SDG3.SGTFR) +#define SGSFR_3 (SDG3.SGSFR) + + +typedef struct st_sdg +{ + /* SDG */ + volatile uint8_t SGCR1; /* SGCR1 */ + volatile uint8_t SGCSR; /* SGCSR */ + volatile uint8_t SGCR2; /* SGCR2 */ + volatile uint8_t SGLR; /* SGLR */ + volatile uint8_t SGTFR; /* SGTFR */ + volatile uint8_t SGSFR; /* SGSFR */ +} r_io_sdg_t; + + +/* Channel array defines of SDG (2)*/ +#ifdef DECLARE_SDG_CHANNELS +volatile struct st_sdg* SDG[ SDG_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SDG_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SDG_CHANNELS */ +/* End of channel array defines of SDG (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h index 6f69f80850..a7e4c82529 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h @@ -18,19 +18,43 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : spdif_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SPDIF_IODEFINE_H #define SPDIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ -struct st_spdif -{ /* SPDIF */ +#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */ + + +#define SPDIFTLCA (SPDIF.TLCA) +#define SPDIFTRCA (SPDIF.TRCA) +#define SPDIFTLCS (SPDIF.TLCS) +#define SPDIFTRCS (SPDIF.TRCS) +#define SPDIFTUI (SPDIF.TUI) +#define SPDIFRLCA (SPDIF.RLCA) +#define SPDIFRRCA (SPDIF.RRCA) +#define SPDIFRLCS (SPDIF.RLCS) +#define SPDIFRRCS (SPDIF.RRCS) +#define SPDIFRUI (SPDIF.RUI) +#define SPDIFCTRL (SPDIF.CTRL) +#define SPDIFSTAT (SPDIF.STAT) +#define SPDIFTDAD (SPDIF.TDAD) +#define SPDIFRDAD (SPDIF.RDAD) + + +typedef struct st_spdif +{ + /* SPDIF */ volatile uint32_t TLCA; /* TLCA */ volatile uint32_t TRCA; /* TRCA */ volatile uint32_t TLCS; /* TLCS */ @@ -45,24 +69,11 @@ struct st_spdif volatile uint32_t STAT; /* STAT */ volatile uint32_t TDAD; /* TDAD */ volatile uint32_t RDAD; /* RDAD */ -}; +} r_io_spdif_t; -#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */ - - -#define SPDIFTLCA SPDIF.TLCA -#define SPDIFTRCA SPDIF.TRCA -#define SPDIFTLCS SPDIF.TLCS -#define SPDIFTRCS SPDIF.TRCS -#define SPDIFTUI SPDIF.TUI -#define SPDIFRLCA SPDIF.RLCA -#define SPDIFRRCA SPDIF.RRCA -#define SPDIFRLCS SPDIF.RLCS -#define SPDIFRRCS SPDIF.RRCS -#define SPDIFRUI SPDIF.RUI -#define SPDIFCTRL SPDIF.CTRL -#define SPDIFSTAT SPDIF.STAT -#define SPDIFTDAD SPDIF.TDAD -#define SPDIFRDAD SPDIF.RDAD +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h index d25b903b89..6615aea8f7 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h @@ -18,20 +18,139 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : spibsc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SPIBSC_IODEFINE_H #define SPIBSC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_spibsc -{ /* SPIBSC */ +#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */ +#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */ + + +/* Start of channel array defines of SPIBSC */ + +/* Channel array defines of SPIBSC */ +/*(Sample) value = SPIBSC[ channel ]->CMNCR; */ +#define SPIBSC_COUNT (2) +#define SPIBSC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SPIBSC0, &SPIBSC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SPIBSC */ + + +#define CMNCR_0 (SPIBSC0.CMNCR) +#define SSLDR_0 (SPIBSC0.SSLDR) +#define SPBCR_0 (SPIBSC0.SPBCR) +#define DRCR_0 (SPIBSC0.DRCR) +#define DRCMR_0 (SPIBSC0.DRCMR) +#define DREAR_0 (SPIBSC0.DREAR) +#define DROPR_0 (SPIBSC0.DROPR) +#define DRENR_0 (SPIBSC0.DRENR) +#define SMCR_0 (SPIBSC0.SMCR) +#define SMCMR_0 (SPIBSC0.SMCMR) +#define SMADR_0 (SPIBSC0.SMADR) +#define SMOPR_0 (SPIBSC0.SMOPR) +#define SMENR_0 (SPIBSC0.SMENR) +#define SMRDR0_0 (SPIBSC0.SMRDR0.UINT32) +#define SMRDR0_0L (SPIBSC0.SMRDR0.UINT16[R_IO_L]) +#define SMRDR0_0H (SPIBSC0.SMRDR0.UINT16[R_IO_H]) +#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL]) +#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH]) +#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL]) +#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH]) +#define SMRDR1_0 (SPIBSC0.SMRDR1.UINT32) +#define SMRDR1_0L (SPIBSC0.SMRDR1.UINT16[R_IO_L]) +#define SMRDR1_0H (SPIBSC0.SMRDR1.UINT16[R_IO_H]) +#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL]) +#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH]) +#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL]) +#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH]) +#define SMWDR0_0 (SPIBSC0.SMWDR0.UINT32) +#define SMWDR0_0L (SPIBSC0.SMWDR0.UINT16[R_IO_L]) +#define SMWDR0_0H (SPIBSC0.SMWDR0.UINT16[R_IO_H]) +#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL]) +#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH]) +#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL]) +#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH]) +#define SMWDR1_0 (SPIBSC0.SMWDR1.UINT32) +#define SMWDR1_0L (SPIBSC0.SMWDR1.UINT16[R_IO_L]) +#define SMWDR1_0H (SPIBSC0.SMWDR1.UINT16[R_IO_H]) +#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL]) +#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH]) +#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL]) +#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH]) +#define CMNSR_0 (SPIBSC0.CMNSR) +#define CKDLY_0 (SPIBSC0.CKDLY) +#define DRDMCR_0 (SPIBSC0.DRDMCR) +#define DRDRENR_0 (SPIBSC0.DRDRENR) +#define SMDMCR_0 (SPIBSC0.SMDMCR) +#define SMDRENR_0 (SPIBSC0.SMDRENR) +#define SPODLY_0 (SPIBSC0.SPODLY) +#define CMNCR_1 (SPIBSC1.CMNCR) +#define SSLDR_1 (SPIBSC1.SSLDR) +#define SPBCR_1 (SPIBSC1.SPBCR) +#define DRCR_1 (SPIBSC1.DRCR) +#define DRCMR_1 (SPIBSC1.DRCMR) +#define DREAR_1 (SPIBSC1.DREAR) +#define DROPR_1 (SPIBSC1.DROPR) +#define DRENR_1 (SPIBSC1.DRENR) +#define SMCR_1 (SPIBSC1.SMCR) +#define SMCMR_1 (SPIBSC1.SMCMR) +#define SMADR_1 (SPIBSC1.SMADR) +#define SMOPR_1 (SPIBSC1.SMOPR) +#define SMENR_1 (SPIBSC1.SMENR) +#define SMRDR0_1 (SPIBSC1.SMRDR0.UINT32) +#define SMRDR0_1L (SPIBSC1.SMRDR0.UINT16[R_IO_L]) +#define SMRDR0_1H (SPIBSC1.SMRDR0.UINT16[R_IO_H]) +#define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL]) +#define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH]) +#define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL]) +#define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH]) +#define SMRDR1_1 (SPIBSC1.SMRDR1.UINT32) +#define SMRDR1_1L (SPIBSC1.SMRDR1.UINT16[R_IO_L]) +#define SMRDR1_1H (SPIBSC1.SMRDR1.UINT16[R_IO_H]) +#define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL]) +#define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH]) +#define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL]) +#define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH]) +#define SMWDR0_1 (SPIBSC1.SMWDR0.UINT32) +#define SMWDR0_1L (SPIBSC1.SMWDR0.UINT16[R_IO_L]) +#define SMWDR0_1H (SPIBSC1.SMWDR0.UINT16[R_IO_H]) +#define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL]) +#define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH]) +#define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL]) +#define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH]) +#define SMWDR1_1 (SPIBSC1.SMWDR1.UINT32) +#define SMWDR1_1L (SPIBSC1.SMWDR1.UINT16[R_IO_L]) +#define SMWDR1_1H (SPIBSC1.SMWDR1.UINT16[R_IO_H]) +#define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL]) +#define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH]) +#define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL]) +#define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH]) +#define CMNSR_1 (SPIBSC1.CMNSR) +#define CKDLY_1 (SPIBSC1.CKDLY) +#define DRDMCR_1 (SPIBSC1.DRDMCR) +#define DRDRENR_1 (SPIBSC1.DRDRENR) +#define SMDMCR_1 (SPIBSC1.SMDMCR) +#define SMDRENR_1 (SPIBSC1.SMDRENR) +#define SPODLY_1 (SPIBSC1.SPODLY) + + +typedef struct st_spibsc +{ + /* SPIBSC */ volatile uint32_t CMNCR; /* CMNCR */ volatile uint32_t SSLDR; /* SSLDR */ volatile uint32_t SPBCR; /* SPBCR */ @@ -52,122 +171,29 @@ struct st_spibsc union iodefine_reg32_t SMWDR1; /* SMWDR1 */ volatile uint32_t CMNSR; /* CMNSR */ - volatile uint8_t dummy2[12]; /* */ + volatile uint8_t dummy2[4]; /* */ + volatile uint32_t CKDLY; /* CKDLY */ + volatile uint8_t dummy3[4]; /* */ volatile uint32_t DRDMCR; /* DRDMCR */ volatile uint32_t DRDRENR; /* DRDRENR */ volatile uint32_t SMDMCR; /* SMDMCR */ volatile uint32_t SMDRENR; /* SMDRENR */ -}; + volatile uint32_t SPODLY; /* SPODLY */ +} r_io_spibsc_t; -#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */ -#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */ +/* Channel array defines of SPIBSC (2)*/ +#ifdef DECLARE_SPIBSC_CHANNELS +volatile struct st_spibsc* SPIBSC[ SPIBSC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SPIBSC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SPIBSC_CHANNELS */ +/* End of channel array defines of SPIBSC (2)*/ -/* Start of channnel array defines of SPIBSC */ - -/* Channnel array defines of SPIBSC */ -/*(Sample) value = SPIBSC[ channel ]->CMNCR; */ -#define SPIBSC_COUNT 2 -#define SPIBSC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SPIBSC0, &SPIBSC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of SPIBSC */ - - -#define CMNCR_0 SPIBSC0.CMNCR -#define SSLDR_0 SPIBSC0.SSLDR -#define SPBCR_0 SPIBSC0.SPBCR -#define DRCR_0 SPIBSC0.DRCR -#define DRCMR_0 SPIBSC0.DRCMR -#define DREAR_0 SPIBSC0.DREAR -#define DROPR_0 SPIBSC0.DROPR -#define DRENR_0 SPIBSC0.DRENR -#define SMCR_0 SPIBSC0.SMCR -#define SMCMR_0 SPIBSC0.SMCMR -#define SMADR_0 SPIBSC0.SMADR -#define SMOPR_0 SPIBSC0.SMOPR -#define SMENR_0 SPIBSC0.SMENR -#define SMRDR0_0 SPIBSC0.SMRDR0.UINT32 -#define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L] -#define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H] -#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL] -#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH] -#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL] -#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH] -#define SMRDR1_0 SPIBSC0.SMRDR1.UINT32 -#define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L] -#define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H] -#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL] -#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH] -#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL] -#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH] -#define SMWDR0_0 SPIBSC0.SMWDR0.UINT32 -#define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L] -#define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H] -#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL] -#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH] -#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL] -#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH] -#define SMWDR1_0 SPIBSC0.SMWDR1.UINT32 -#define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L] -#define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H] -#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL] -#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH] -#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL] -#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH] -#define CMNSR_0 SPIBSC0.CMNSR -#define DRDMCR_0 SPIBSC0.DRDMCR -#define DRDRENR_0 SPIBSC0.DRDRENR -#define SMDMCR_0 SPIBSC0.SMDMCR -#define SMDRENR_0 SPIBSC0.SMDRENR -#define CMNCR_1 SPIBSC1.CMNCR -#define SSLDR_1 SPIBSC1.SSLDR -#define SPBCR_1 SPIBSC1.SPBCR -#define DRCR_1 SPIBSC1.DRCR -#define DRCMR_1 SPIBSC1.DRCMR -#define DREAR_1 SPIBSC1.DREAR -#define DROPR_1 SPIBSC1.DROPR -#define DRENR_1 SPIBSC1.DRENR -#define SMCR_1 SPIBSC1.SMCR -#define SMCMR_1 SPIBSC1.SMCMR -#define SMADR_1 SPIBSC1.SMADR -#define SMOPR_1 SPIBSC1.SMOPR -#define SMENR_1 SPIBSC1.SMENR -#define SMRDR0_1 SPIBSC1.SMRDR0.UINT32 -#define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L] -#define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H] -#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL] -#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH] -#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL] -#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH] -#define SMRDR1_1 SPIBSC1.SMRDR1.UINT32 -#define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L] -#define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H] -#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL] -#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH] -#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL] -#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH] -#define SMWDR0_1 SPIBSC1.SMWDR0.UINT32 -#define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L] -#define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H] -#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL] -#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH] -#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL] -#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH] -#define SMWDR1_1 SPIBSC1.SMWDR1.UINT32 -#define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L] -#define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H] -#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL] -#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH] -#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL] -#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH] -#define CMNSR_1 SPIBSC1.CMNSR -#define DRDMCR_1 SPIBSC1.DRDMCR -#define DRDRENR_1 SPIBSC1.DRDRENR -#define SMDMCR_1 SPIBSC1.SMDMCR -#define SMDRENR_1 SPIBSC1.SMDRENR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h index 045551c9f2..c0134a5d62 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h @@ -18,20 +18,107 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ssif_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SSIF_IODEFINE_H #define SSIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ssif -{ /* SSIF */ +#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */ +#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */ +#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */ +#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */ +#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */ +#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */ + + +/* Start of channel array defines of SSIF */ + +/* Channel array defines of SSIF */ +/*(Sample) value = SSIF[ channel ]->SSICR; */ +#define SSIF_COUNT (6) +#define SSIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SSIF */ + + +#define SSICR_0 (SSIF0.SSICR) +#define SSISR_0 (SSIF0.SSISR) +#define SSIFCR_0 (SSIF0.SSIFCR) +#define SSIFSR_0 (SSIF0.SSIFSR) +#define SSIFTDR_0 (SSIF0.SSIFTDR) +#define SSIFRDR_0 (SSIF0.SSIFRDR) +#define SSITDMR_0 (SSIF0.SSITDMR) +#define SSIFCCR_0 (SSIF0.SSIFCCR) +#define SSIFCMR_0 (SSIF0.SSIFCMR) +#define SSIFCSR_0 (SSIF0.SSIFCSR) +#define SSICR_1 (SSIF1.SSICR) +#define SSISR_1 (SSIF1.SSISR) +#define SSIFCR_1 (SSIF1.SSIFCR) +#define SSIFSR_1 (SSIF1.SSIFSR) +#define SSIFTDR_1 (SSIF1.SSIFTDR) +#define SSIFRDR_1 (SSIF1.SSIFRDR) +#define SSITDMR_1 (SSIF1.SSITDMR) +#define SSIFCCR_1 (SSIF1.SSIFCCR) +#define SSIFCMR_1 (SSIF1.SSIFCMR) +#define SSIFCSR_1 (SSIF1.SSIFCSR) +#define SSICR_2 (SSIF2.SSICR) +#define SSISR_2 (SSIF2.SSISR) +#define SSIFCR_2 (SSIF2.SSIFCR) +#define SSIFSR_2 (SSIF2.SSIFSR) +#define SSIFTDR_2 (SSIF2.SSIFTDR) +#define SSIFRDR_2 (SSIF2.SSIFRDR) +#define SSITDMR_2 (SSIF2.SSITDMR) +#define SSIFCCR_2 (SSIF2.SSIFCCR) +#define SSIFCMR_2 (SSIF2.SSIFCMR) +#define SSIFCSR_2 (SSIF2.SSIFCSR) +#define SSICR_3 (SSIF3.SSICR) +#define SSISR_3 (SSIF3.SSISR) +#define SSIFCR_3 (SSIF3.SSIFCR) +#define SSIFSR_3 (SSIF3.SSIFSR) +#define SSIFTDR_3 (SSIF3.SSIFTDR) +#define SSIFRDR_3 (SSIF3.SSIFRDR) +#define SSITDMR_3 (SSIF3.SSITDMR) +#define SSIFCCR_3 (SSIF3.SSIFCCR) +#define SSIFCMR_3 (SSIF3.SSIFCMR) +#define SSIFCSR_3 (SSIF3.SSIFCSR) +#define SSICR_4 (SSIF4.SSICR) +#define SSISR_4 (SSIF4.SSISR) +#define SSIFCR_4 (SSIF4.SSIFCR) +#define SSIFSR_4 (SSIF4.SSIFSR) +#define SSIFTDR_4 (SSIF4.SSIFTDR) +#define SSIFRDR_4 (SSIF4.SSIFRDR) +#define SSITDMR_4 (SSIF4.SSITDMR) +#define SSIFCCR_4 (SSIF4.SSIFCCR) +#define SSIFCMR_4 (SSIF4.SSIFCMR) +#define SSIFCSR_4 (SSIF4.SSIFCSR) +#define SSICR_5 (SSIF5.SSICR) +#define SSISR_5 (SSIF5.SSISR) +#define SSIFCR_5 (SSIF5.SSIFCR) +#define SSIFSR_5 (SSIF5.SSIFSR) +#define SSIFTDR_5 (SSIF5.SSIFTDR) +#define SSIFRDR_5 (SSIF5.SSIFRDR) +#define SSITDMR_5 (SSIF5.SSITDMR) +#define SSIFCCR_5 (SSIF5.SSIFCCR) +#define SSIFCMR_5 (SSIF5.SSIFCMR) +#define SSIFCSR_5 (SSIF5.SSIFCSR) + + +typedef struct st_ssif +{ + /* SSIF */ volatile uint32_t SSICR; /* SSICR */ volatile uint32_t SSISR; /* SSISR */ volatile uint8_t dummy1[8]; /* */ @@ -43,89 +130,21 @@ struct st_ssif volatile uint32_t SSIFCCR; /* SSIFCCR */ volatile uint32_t SSIFCMR; /* SSIFCMR */ volatile uint32_t SSIFCSR; /* SSIFCSR */ -}; +} r_io_ssif_t; -#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */ -#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */ -#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */ -#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */ -#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */ -#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */ +/* Channel array defines of SSIF (2)*/ +#ifdef DECLARE_SSIF_CHANNELS +volatile struct st_ssif* SSIF[ SSIF_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SSIF_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SSIF_CHANNELS */ +/* End of channel array defines of SSIF (2)*/ -/* Start of channnel array defines of SSIF */ - -/* Channnel array defines of SSIF */ -/*(Sample) value = SSIF[ channel ]->SSICR; */ -#define SSIF_COUNT 6 -#define SSIF_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of SSIF */ - - -#define SSICR_0 SSIF0.SSICR -#define SSISR_0 SSIF0.SSISR -#define SSIFCR_0 SSIF0.SSIFCR -#define SSIFSR_0 SSIF0.SSIFSR -#define SSIFTDR_0 SSIF0.SSIFTDR -#define SSIFRDR_0 SSIF0.SSIFRDR -#define SSITDMR_0 SSIF0.SSITDMR -#define SSIFCCR_0 SSIF0.SSIFCCR -#define SSIFCMR_0 SSIF0.SSIFCMR -#define SSIFCSR_0 SSIF0.SSIFCSR -#define SSICR_1 SSIF1.SSICR -#define SSISR_1 SSIF1.SSISR -#define SSIFCR_1 SSIF1.SSIFCR -#define SSIFSR_1 SSIF1.SSIFSR -#define SSIFTDR_1 SSIF1.SSIFTDR -#define SSIFRDR_1 SSIF1.SSIFRDR -#define SSITDMR_1 SSIF1.SSITDMR -#define SSIFCCR_1 SSIF1.SSIFCCR -#define SSIFCMR_1 SSIF1.SSIFCMR -#define SSIFCSR_1 SSIF1.SSIFCSR -#define SSICR_2 SSIF2.SSICR -#define SSISR_2 SSIF2.SSISR -#define SSIFCR_2 SSIF2.SSIFCR -#define SSIFSR_2 SSIF2.SSIFSR -#define SSIFTDR_2 SSIF2.SSIFTDR -#define SSIFRDR_2 SSIF2.SSIFRDR -#define SSITDMR_2 SSIF2.SSITDMR -#define SSIFCCR_2 SSIF2.SSIFCCR -#define SSIFCMR_2 SSIF2.SSIFCMR -#define SSIFCSR_2 SSIF2.SSIFCSR -#define SSICR_3 SSIF3.SSICR -#define SSISR_3 SSIF3.SSISR -#define SSIFCR_3 SSIF3.SSIFCR -#define SSIFSR_3 SSIF3.SSIFSR -#define SSIFTDR_3 SSIF3.SSIFTDR -#define SSIFRDR_3 SSIF3.SSIFRDR -#define SSITDMR_3 SSIF3.SSITDMR -#define SSIFCCR_3 SSIF3.SSIFCCR -#define SSIFCMR_3 SSIF3.SSIFCMR -#define SSIFCSR_3 SSIF3.SSIFCSR -#define SSICR_4 SSIF4.SSICR -#define SSISR_4 SSIF4.SSISR -#define SSIFCR_4 SSIF4.SSIFCR -#define SSIFSR_4 SSIF4.SSIFSR -#define SSIFTDR_4 SSIF4.SSIFTDR -#define SSIFRDR_4 SSIF4.SSIFRDR -#define SSITDMR_4 SSIF4.SSITDMR -#define SSIFCCR_4 SSIF4.SSIFCCR -#define SSIFCMR_4 SSIF4.SSIFCMR -#define SSIFCSR_4 SSIF4.SSIFCSR -#define SSICR_5 SSIF5.SSICR -#define SSISR_5 SSIF5.SSISR -#define SSIFCR_5 SSIF5.SSIFCR -#define SSIFSR_5 SSIF5.SSIFSR -#define SSIFTDR_5 SSIF5.SSIFTDR -#define SSIFRDR_5 SSIF5.SSIFRDR -#define SSITDMR_5 SSIF5.SSITDMR -#define SSIFCCR_5 SSIF5.SSIFCCR -#define SSIFCMR_5 SSIF5.SSIFCMR -#define SSIFCSR_5 SSIF5.SSIFCSR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h index 97e15c8455..a8e60a2647 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h @@ -18,20 +18,365 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : usb20_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef USB20_IODEFINE_H #define USB20_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_usb20 -{ /* USB20 */ +#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */ +#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */ + + +/* Start of channel array defines of USB20 */ + +/* Channel array defines of USB20 */ +/*(Sample) value = USB20[ channel ]->SYSCFG0; */ +#define USB20_COUNT (2) +#define USB20_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &USB200, &USB201 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channel array defines of USB20_FROM_D0FIFOB0 */ +/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */ +#define USB20_FROM_D0FIFOB0_COUNT (2) +#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \ + &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */ +#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */ +#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */ +#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */ + + + + +/* Channel array defines of USB20_FROM_PIPE1ATRE */ +/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */ +#define USB20_FROM_PIPE1ATRE_COUNT (5) +#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \ + &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */ +#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */ +#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */ +#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */ +#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */ +#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */ +#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */ +#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */ +#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */ +#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */ + + + + +/* Channel array defines of USB20_FROM_D0FIFOSEL */ +/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */ +#define USB20_FROM_D0FIFOSEL_COUNT (2) +#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \ + &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */ +#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */ +#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */ +#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */ + + +/* End of channel array defines of USB20 */ + + +#define SYSCFG0_0 (USB200.SYSCFG0) +#define BUSWAIT_0 (USB200.BUSWAIT) +#define SYSSTS0_0 (USB200.SYSSTS0) +#define DVSTCTR0_0 (USB200.DVSTCTR0) +#define TESTMODE_0 (USB200.TESTMODE) +#define D0FBCFG_0 (USB200.D0FBCFG) +#define D1FBCFG_0 (USB200.D1FBCFG) +#define CFIFO_0 (USB200.CFIFO.UINT32) +#define CFIFO_0L (USB200.CFIFO.UINT16[R_IO_L]) +#define CFIFO_0H (USB200.CFIFO.UINT16[R_IO_H]) +#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL]) +#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH]) +#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL]) +#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH]) +#define D0FIFO_0 (USB200.D0FIFO.UINT32) +#define D0FIFO_0L (USB200.D0FIFO.UINT16[R_IO_L]) +#define D0FIFO_0H (USB200.D0FIFO.UINT16[R_IO_H]) +#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL]) +#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH]) +#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL]) +#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH]) +#define D1FIFO_0 (USB200.D1FIFO.UINT32) +#define D1FIFO_0L (USB200.D1FIFO.UINT16[R_IO_L]) +#define D1FIFO_0H (USB200.D1FIFO.UINT16[R_IO_H]) +#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL]) +#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH]) +#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL]) +#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH]) +#define CFIFOSEL_0 (USB200.CFIFOSEL) +#define CFIFOCTR_0 (USB200.CFIFOCTR) +#define D0FIFOSEL_0 (USB200.D0FIFOSEL) +#define D0FIFOCTR_0 (USB200.D0FIFOCTR) +#define D1FIFOSEL_0 (USB200.D1FIFOSEL) +#define D1FIFOCTR_0 (USB200.D1FIFOCTR) +#define INTENB0_0 (USB200.INTENB0) +#define INTENB1_0 (USB200.INTENB1) +#define BRDYENB_0 (USB200.BRDYENB) +#define NRDYENB_0 (USB200.NRDYENB) +#define BEMPENB_0 (USB200.BEMPENB) +#define SOFCFG_0 (USB200.SOFCFG) +#define INTSTS0_0 (USB200.INTSTS0) +#define INTSTS1_0 (USB200.INTSTS1) +#define BRDYSTS_0 (USB200.BRDYSTS) +#define NRDYSTS_0 (USB200.NRDYSTS) +#define BEMPSTS_0 (USB200.BEMPSTS) +#define FRMNUM_0 (USB200.FRMNUM) +#define UFRMNUM_0 (USB200.UFRMNUM) +#define USBADDR_0 (USB200.USBADDR) +#define USBREQ_0 (USB200.USBREQ) +#define USBVAL_0 (USB200.USBVAL) +#define USBINDX_0 (USB200.USBINDX) +#define USBLENG_0 (USB200.USBLENG) +#define DCPCFG_0 (USB200.DCPCFG) +#define DCPMAXP_0 (USB200.DCPMAXP) +#define DCPCTR_0 (USB200.DCPCTR) +#define PIPESEL_0 (USB200.PIPESEL) +#define PIPECFG_0 (USB200.PIPECFG) +#define PIPEBUF_0 (USB200.PIPEBUF) +#define PIPEMAXP_0 (USB200.PIPEMAXP) +#define PIPEPERI_0 (USB200.PIPEPERI) +#define PIPE1CTR_0 (USB200.PIPE1CTR) +#define PIPE2CTR_0 (USB200.PIPE2CTR) +#define PIPE3CTR_0 (USB200.PIPE3CTR) +#define PIPE4CTR_0 (USB200.PIPE4CTR) +#define PIPE5CTR_0 (USB200.PIPE5CTR) +#define PIPE6CTR_0 (USB200.PIPE6CTR) +#define PIPE7CTR_0 (USB200.PIPE7CTR) +#define PIPE8CTR_0 (USB200.PIPE8CTR) +#define PIPE9CTR_0 (USB200.PIPE9CTR) +#define PIPEACTR_0 (USB200.PIPEACTR) +#define PIPEBCTR_0 (USB200.PIPEBCTR) +#define PIPECCTR_0 (USB200.PIPECCTR) +#define PIPEDCTR_0 (USB200.PIPEDCTR) +#define PIPEECTR_0 (USB200.PIPEECTR) +#define PIPEFCTR_0 (USB200.PIPEFCTR) +#define PIPE1TRE_0 (USB200.PIPE1TRE) +#define PIPE1TRN_0 (USB200.PIPE1TRN) +#define PIPE2TRE_0 (USB200.PIPE2TRE) +#define PIPE2TRN_0 (USB200.PIPE2TRN) +#define PIPE3TRE_0 (USB200.PIPE3TRE) +#define PIPE3TRN_0 (USB200.PIPE3TRN) +#define PIPE4TRE_0 (USB200.PIPE4TRE) +#define PIPE4TRN_0 (USB200.PIPE4TRN) +#define PIPE5TRE_0 (USB200.PIPE5TRE) +#define PIPE5TRN_0 (USB200.PIPE5TRN) +#define PIPEBTRE_0 (USB200.PIPEBTRE) +#define PIPEBTRN_0 (USB200.PIPEBTRN) +#define PIPECTRE_0 (USB200.PIPECTRE) +#define PIPECTRN_0 (USB200.PIPECTRN) +#define PIPEDTRE_0 (USB200.PIPEDTRE) +#define PIPEDTRN_0 (USB200.PIPEDTRN) +#define PIPEETRE_0 (USB200.PIPEETRE) +#define PIPEETRN_0 (USB200.PIPEETRN) +#define PIPEFTRE_0 (USB200.PIPEFTRE) +#define PIPEFTRN_0 (USB200.PIPEFTRN) +#define PIPE9TRE_0 (USB200.PIPE9TRE) +#define PIPE9TRN_0 (USB200.PIPE9TRN) +#define PIPEATRE_0 (USB200.PIPEATRE) +#define PIPEATRN_0 (USB200.PIPEATRN) +#define DEVADD0_0 (USB200.DEVADD0) +#define DEVADD1_0 (USB200.DEVADD1) +#define DEVADD2_0 (USB200.DEVADD2) +#define DEVADD3_0 (USB200.DEVADD3) +#define DEVADD4_0 (USB200.DEVADD4) +#define DEVADD5_0 (USB200.DEVADD5) +#define DEVADD6_0 (USB200.DEVADD6) +#define DEVADD7_0 (USB200.DEVADD7) +#define DEVADD8_0 (USB200.DEVADD8) +#define DEVADD9_0 (USB200.DEVADD9) +#define DEVADDA_0 (USB200.DEVADDA) +#define SUSPMODE_0 (USB200.SUSPMODE) +#define D0FIFOB0_0 (USB200.D0FIFOB0) +#define D0FIFOB1_0 (USB200.D0FIFOB1) +#define D0FIFOB2_0 (USB200.D0FIFOB2) +#define D0FIFOB3_0 (USB200.D0FIFOB3) +#define D0FIFOB4_0 (USB200.D0FIFOB4) +#define D0FIFOB5_0 (USB200.D0FIFOB5) +#define D0FIFOB6_0 (USB200.D0FIFOB6) +#define D0FIFOB7_0 (USB200.D0FIFOB7) +#define D1FIFOB0_0 (USB200.D1FIFOB0) +#define D1FIFOB1_0 (USB200.D1FIFOB1) +#define D1FIFOB2_0 (USB200.D1FIFOB2) +#define D1FIFOB3_0 (USB200.D1FIFOB3) +#define D1FIFOB4_0 (USB200.D1FIFOB4) +#define D1FIFOB5_0 (USB200.D1FIFOB5) +#define D1FIFOB6_0 (USB200.D1FIFOB6) +#define D1FIFOB7_0 (USB200.D1FIFOB7) +#define SYSCFG0_1 (USB201.SYSCFG0) +#define BUSWAIT_1 (USB201.BUSWAIT) +#define SYSSTS0_1 (USB201.SYSSTS0) +#define DVSTCTR0_1 (USB201.DVSTCTR0) +#define TESTMODE_1 (USB201.TESTMODE) +#define D0FBCFG_1 (USB201.D0FBCFG) +#define D1FBCFG_1 (USB201.D1FBCFG) +#define CFIFO_1 (USB201.CFIFO.UINT32) +#define CFIFO_1L (USB201.CFIFO.UINT16[R_IO_L]) +#define CFIFO_1H (USB201.CFIFO.UINT16[R_IO_H]) +#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL]) +#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH]) +#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL]) +#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH]) +#define D0FIFO_1 (USB201.D0FIFO.UINT32) +#define D0FIFO_1L (USB201.D0FIFO.UINT16[R_IO_L]) +#define D0FIFO_1H (USB201.D0FIFO.UINT16[R_IO_H]) +#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL]) +#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH]) +#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL]) +#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH]) +#define D1FIFO_1 (USB201.D1FIFO.UINT32) +#define D1FIFO_1L (USB201.D1FIFO.UINT16[R_IO_L]) +#define D1FIFO_1H (USB201.D1FIFO.UINT16[R_IO_H]) +#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL]) +#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH]) +#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL]) +#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH]) +#define CFIFOSEL_1 (USB201.CFIFOSEL) +#define CFIFOCTR_1 (USB201.CFIFOCTR) +#define D0FIFOSEL_1 (USB201.D0FIFOSEL) +#define D0FIFOCTR_1 (USB201.D0FIFOCTR) +#define D1FIFOSEL_1 (USB201.D1FIFOSEL) +#define D1FIFOCTR_1 (USB201.D1FIFOCTR) +#define INTENB0_1 (USB201.INTENB0) +#define INTENB1_1 (USB201.INTENB1) +#define BRDYENB_1 (USB201.BRDYENB) +#define NRDYENB_1 (USB201.NRDYENB) +#define BEMPENB_1 (USB201.BEMPENB) +#define SOFCFG_1 (USB201.SOFCFG) +#define INTSTS0_1 (USB201.INTSTS0) +#define INTSTS1_1 (USB201.INTSTS1) +#define BRDYSTS_1 (USB201.BRDYSTS) +#define NRDYSTS_1 (USB201.NRDYSTS) +#define BEMPSTS_1 (USB201.BEMPSTS) +#define FRMNUM_1 (USB201.FRMNUM) +#define UFRMNUM_1 (USB201.UFRMNUM) +#define USBADDR_1 (USB201.USBADDR) +#define USBREQ_1 (USB201.USBREQ) +#define USBVAL_1 (USB201.USBVAL) +#define USBINDX_1 (USB201.USBINDX) +#define USBLENG_1 (USB201.USBLENG) +#define DCPCFG_1 (USB201.DCPCFG) +#define DCPMAXP_1 (USB201.DCPMAXP) +#define DCPCTR_1 (USB201.DCPCTR) +#define PIPESEL_1 (USB201.PIPESEL) +#define PIPECFG_1 (USB201.PIPECFG) +#define PIPEBUF_1 (USB201.PIPEBUF) +#define PIPEMAXP_1 (USB201.PIPEMAXP) +#define PIPEPERI_1 (USB201.PIPEPERI) +#define PIPE1CTR_1 (USB201.PIPE1CTR) +#define PIPE2CTR_1 (USB201.PIPE2CTR) +#define PIPE3CTR_1 (USB201.PIPE3CTR) +#define PIPE4CTR_1 (USB201.PIPE4CTR) +#define PIPE5CTR_1 (USB201.PIPE5CTR) +#define PIPE6CTR_1 (USB201.PIPE6CTR) +#define PIPE7CTR_1 (USB201.PIPE7CTR) +#define PIPE8CTR_1 (USB201.PIPE8CTR) +#define PIPE9CTR_1 (USB201.PIPE9CTR) +#define PIPEACTR_1 (USB201.PIPEACTR) +#define PIPEBCTR_1 (USB201.PIPEBCTR) +#define PIPECCTR_1 (USB201.PIPECCTR) +#define PIPEDCTR_1 (USB201.PIPEDCTR) +#define PIPEECTR_1 (USB201.PIPEECTR) +#define PIPEFCTR_1 (USB201.PIPEFCTR) +#define PIPE1TRE_1 (USB201.PIPE1TRE) +#define PIPE1TRN_1 (USB201.PIPE1TRN) +#define PIPE2TRE_1 (USB201.PIPE2TRE) +#define PIPE2TRN_1 (USB201.PIPE2TRN) +#define PIPE3TRE_1 (USB201.PIPE3TRE) +#define PIPE3TRN_1 (USB201.PIPE3TRN) +#define PIPE4TRE_1 (USB201.PIPE4TRE) +#define PIPE4TRN_1 (USB201.PIPE4TRN) +#define PIPE5TRE_1 (USB201.PIPE5TRE) +#define PIPE5TRN_1 (USB201.PIPE5TRN) +#define PIPEBTRE_1 (USB201.PIPEBTRE) +#define PIPEBTRN_1 (USB201.PIPEBTRN) +#define PIPECTRE_1 (USB201.PIPECTRE) +#define PIPECTRN_1 (USB201.PIPECTRN) +#define PIPEDTRE_1 (USB201.PIPEDTRE) +#define PIPEDTRN_1 (USB201.PIPEDTRN) +#define PIPEETRE_1 (USB201.PIPEETRE) +#define PIPEETRN_1 (USB201.PIPEETRN) +#define PIPEFTRE_1 (USB201.PIPEFTRE) +#define PIPEFTRN_1 (USB201.PIPEFTRN) +#define PIPE9TRE_1 (USB201.PIPE9TRE) +#define PIPE9TRN_1 (USB201.PIPE9TRN) +#define PIPEATRE_1 (USB201.PIPEATRE) +#define PIPEATRN_1 (USB201.PIPEATRN) +#define DEVADD0_1 (USB201.DEVADD0) +#define DEVADD1_1 (USB201.DEVADD1) +#define DEVADD2_1 (USB201.DEVADD2) +#define DEVADD3_1 (USB201.DEVADD3) +#define DEVADD4_1 (USB201.DEVADD4) +#define DEVADD5_1 (USB201.DEVADD5) +#define DEVADD6_1 (USB201.DEVADD6) +#define DEVADD7_1 (USB201.DEVADD7) +#define DEVADD8_1 (USB201.DEVADD8) +#define DEVADD9_1 (USB201.DEVADD9) +#define DEVADDA_1 (USB201.DEVADDA) +#define SUSPMODE_1 (USB201.SUSPMODE) +#define D0FIFOB0_1 (USB201.D0FIFOB0) +#define D0FIFOB1_1 (USB201.D0FIFOB1) +#define D0FIFOB2_1 (USB201.D0FIFOB2) +#define D0FIFOB3_1 (USB201.D0FIFOB3) +#define D0FIFOB4_1 (USB201.D0FIFOB4) +#define D0FIFOB5_1 (USB201.D0FIFOB5) +#define D0FIFOB6_1 (USB201.D0FIFOB6) +#define D0FIFOB7_1 (USB201.D0FIFOB7) +#define D1FIFOB0_1 (USB201.D1FIFOB0) +#define D1FIFOB1_1 (USB201.D1FIFOB1) +#define D1FIFOB2_1 (USB201.D1FIFOB2) +#define D1FIFOB3_1 (USB201.D1FIFOB3) +#define D1FIFOB4_1 (USB201.D1FIFOB4) +#define D1FIFOB5_1 (USB201.D1FIFOB5) +#define D1FIFOB6_1 (USB201.D1FIFOB6) +#define D1FIFOB7_1 (USB201.D1FIFOB7) + +#define USB20_D0FBCFG_COUNT (2) +#define USB20_D0FIFO_COUNT (2) +#define USB20_INTENB0_COUNT (2) +#define USB20_INTSTS0_COUNT (2) +#define USB20_PIPE1CTR_COUNT (0xF) +#define USB20_DEVADD0_COUNT (0xB) +#define USB20_D0FIFOB0_COUNT (0x8) + + +typedef struct st_usb20 +{ + /* USB20 */ volatile uint16_t SYSCFG0; /* SYSCFG0 */ volatile uint16_t BUSWAIT; /* BUSWAIT */ volatile uint16_t SYSSTS0; /* SYSSTS0 */ @@ -40,26 +385,33 @@ struct st_usb20 volatile uint8_t dummy2[2]; /* */ volatile uint16_t TESTMODE; /* TESTMODE */ volatile uint8_t dummy3[2]; /* */ -#define USB20_D0FBCFG_COUNT 2 + +/* #define USB20_D0FBCFG_COUNT (2) */ volatile uint16_t D0FBCFG; /* D0FBCFG */ volatile uint16_t D1FBCFG; /* D1FBCFG */ union iodefine_reg32_t CFIFO; /* CFIFO */ -#define USB20_D0FIFO_COUNT 2 + +/* #define USB20_D0FIFO_COUNT (2) */ union iodefine_reg32_t D0FIFO; /* D0FIFO */ union iodefine_reg32_t D1FIFO; /* D1FIFO */ volatile uint16_t CFIFOSEL; /* CFIFOSEL */ volatile uint16_t CFIFOCTR; /* CFIFOCTR */ volatile uint8_t dummy4[4]; /* */ + /* start of struct st_usb20_from_d0fifosel */ volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ + /* end of struct st_usb20_from_d0fifosel */ + /* start of struct st_usb20_from_d0fifosel */ volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */ volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */ + /* end of struct st_usb20_from_d0fifosel */ -#define USB20_INTENB0_COUNT 2 + +/* #define USB20_INTENB0_COUNT (2) */ volatile uint16_t INTENB0; /* INTENB0 */ volatile uint16_t INTENB1; /* INTENB1 */ volatile uint8_t dummy5[2]; /* */ @@ -68,7 +420,8 @@ struct st_usb20 volatile uint16_t BEMPENB; /* BEMPENB */ volatile uint16_t SOFCFG; /* SOFCFG */ volatile uint8_t dummy6[2]; /* */ -#define USB20_INTSTS0_COUNT 2 + +/* #define USB20_INTSTS0_COUNT (2) */ volatile uint16_t INTSTS0; /* INTSTS0 */ volatile uint16_t INTSTS1; /* INTSTS1 */ volatile uint8_t dummy7[2]; /* */ @@ -93,7 +446,8 @@ struct st_usb20 volatile uint16_t PIPEBUF; /* PIPEBUF */ volatile uint16_t PIPEMAXP; /* PIPEMAXP */ volatile uint16_t PIPEPERI; /* PIPEPERI */ -#define USB20_PIPE1CTR_COUNT 0xF + +/* #define USB20_PIPE1CTR_COUNT (0xF) */ volatile uint16_t PIPE1CTR; /* PIPE1CTR */ volatile uint16_t PIPE2CTR; /* PIPE2CTR */ volatile uint16_t PIPE3CTR; /* PIPE3CTR */ @@ -110,25 +464,35 @@ struct st_usb20 volatile uint16_t PIPEECTR; /* PIPEECTR */ volatile uint16_t PIPEFCTR; /* PIPEFCTR */ volatile uint8_t dummy11[2]; /* */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE1TRE; /* PIPE1TRE */ volatile uint16_t PIPE1TRN; /* PIPE1TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE2TRE; /* PIPE2TRE */ volatile uint16_t PIPE2TRN; /* PIPE2TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE3TRE; /* PIPE3TRE */ volatile uint16_t PIPE3TRN; /* PIPE3TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE4TRE; /* PIPE4TRE */ volatile uint16_t PIPE4TRN; /* PIPE4TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE5TRE; /* PIPE5TRE */ volatile uint16_t PIPE5TRN; /* PIPE5TRN */ + /* end of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPEBTRE; /* PIPEBTRE */ volatile uint16_t PIPEBTRN; /* PIPEBTRN */ @@ -145,7 +509,8 @@ struct st_usb20 volatile uint16_t PIPEATRE; /* PIPEATRE */ volatile uint16_t PIPEATRN; /* PIPEATRN */ volatile uint8_t dummy12[16]; /* */ -#define USB20_DEVADD0_COUNT 0xB + +/* #define USB20_DEVADD0_COUNT (0xB) */ volatile uint16_t DEVADD0; /* DEVADD0 */ volatile uint16_t DEVADD1; /* DEVADD1 */ volatile uint16_t DEVADD2; /* DEVADD2 */ @@ -160,6 +525,7 @@ struct st_usb20 volatile uint8_t dummy13[28]; /* */ volatile uint16_t SUSPMODE; /* SUSPMODE */ volatile uint8_t dummy14[92]; /* */ + /* start of struct st_usb20_from_dmfifob0 */ volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ @@ -169,7 +535,9 @@ struct st_usb20 volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ + /* end of struct st_usb20_from_dmfifob0 */ + /* start of struct st_usb20_from_dmfifob0 */ volatile uint32_t D1FIFOB0; /* D1FIFOB0 */ volatile uint32_t D1FIFOB1; /* D1FIFOB1 */ @@ -179,27 +547,32 @@ struct st_usb20 volatile uint32_t D1FIFOB5; /* D1FIFOB5 */ volatile uint32_t D1FIFOB6; /* D1FIFOB6 */ volatile uint32_t D1FIFOB7; /* D1FIFOB7 */ + /* end of struct st_usb20_from_dmfifob0 */ -}; +} r_io_usb20_t; -struct st_usb20_from_d0fifosel +typedef struct st_usb20_from_d0fifosel { + volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ -}; +} r_io_usb20_from_d0fifosel_t; -struct st_usb20_from_pipe1tre +typedef struct st_usb20_from_pipe1tre { + volatile uint16_t PIPE1TRE; /* PIPE1TRE */ volatile uint16_t PIPE1TRN; /* PIPE1TRN */ -}; +} r_io_usb20_from_pipe1tre_t; -struct st_usb20_from_dmfifob0 +typedef struct st_usb20_from_dmfifob0 { -#define USB20_D0FIFOB0_COUNT 0x8 + + +/* #define USB20_D0FIFOB0_COUNT (0x8) */ volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ @@ -208,339 +581,42 @@ struct st_usb20_from_dmfifob0 volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ -}; +} r_io_usb20_from_dmfifob0_t; -#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */ -#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */ +/* Channel array defines of USB20 (2)*/ +#ifdef DECLARE_USB20_CHANNELS +volatile struct st_usb20* USB20[ USB20_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_CHANNELS */ + +#ifdef DECLARE_USB20_FROM_D0FIFOB0_CHANNELS +volatile struct st_usb20_from_dmfifob0* USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_D0FIFOB0_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */ + +#ifdef DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS +volatile struct st_usb20_from_pipe1tre* USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_PIPE1ATRE_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */ + +#ifdef DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS +volatile struct st_usb20_from_d0fifosel* USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_D0FIFOSEL_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */ +/* End of channel array defines of USB20 (2)*/ -/* Start of channnel array defines of USB20 */ - -/* Channnel array defines of USB20 */ -/*(Sample) value = USB20[ channel ]->SYSCFG0; */ -#define USB20_COUNT 2 -#define USB20_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &USB200, &USB201 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - - - -/* Channnel array defines of USB20_FROM_D0FIFOB0 */ -/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */ -#define USB20_FROM_D0FIFOB0_COUNT 2 -#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \ - &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */ -#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */ -#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */ -#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */ - - - - -/* Channnel array defines of USB20_FROM_PIPE1ATRE */ -/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */ -#define USB20_FROM_PIPE1ATRE_COUNT 5 -#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \ - &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */ -#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */ -#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */ -#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */ -#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */ -#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */ -#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */ -#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */ -#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */ -#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */ - - - - -/* Channnel array defines of USB20_FROM_D0FIFOSEL */ -/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */ -#define USB20_FROM_D0FIFOSEL_COUNT 2 -#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \ - &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */ -#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */ -#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */ -#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */ - - -/* End of channnel array defines of USB20 */ - - -#define SYSCFG0_0 USB200.SYSCFG0 -#define BUSWAIT_0 USB200.BUSWAIT -#define SYSSTS0_0 USB200.SYSSTS0 -#define DVSTCTR0_0 USB200.DVSTCTR0 -#define TESTMODE_0 USB200.TESTMODE -#define D0FBCFG_0 USB200.D0FBCFG -#define D1FBCFG_0 USB200.D1FBCFG -#define CFIFO_0 USB200.CFIFO.UINT32 -#define CFIFO_0L USB200.CFIFO.UINT16[L] -#define CFIFO_0H USB200.CFIFO.UINT16[H] -#define CFIFO_0LL USB200.CFIFO.UINT8[LL] -#define CFIFO_0LH USB200.CFIFO.UINT8[LH] -#define CFIFO_0HL USB200.CFIFO.UINT8[HL] -#define CFIFO_0HH USB200.CFIFO.UINT8[HH] -#define D0FIFO_0 USB200.D0FIFO.UINT32 -#define D0FIFO_0L USB200.D0FIFO.UINT16[L] -#define D0FIFO_0H USB200.D0FIFO.UINT16[H] -#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL] -#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH] -#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL] -#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH] -#define D1FIFO_0 USB200.D1FIFO.UINT32 -#define D1FIFO_0L USB200.D1FIFO.UINT16[L] -#define D1FIFO_0H USB200.D1FIFO.UINT16[H] -#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL] -#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH] -#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL] -#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH] -#define CFIFOSEL_0 USB200.CFIFOSEL -#define CFIFOCTR_0 USB200.CFIFOCTR -#define D0FIFOSEL_0 USB200.D0FIFOSEL -#define D0FIFOCTR_0 USB200.D0FIFOCTR -#define D1FIFOSEL_0 USB200.D1FIFOSEL -#define D1FIFOCTR_0 USB200.D1FIFOCTR -#define INTENB0_0 USB200.INTENB0 -#define INTENB1_0 USB200.INTENB1 -#define BRDYENB_0 USB200.BRDYENB -#define NRDYENB_0 USB200.NRDYENB -#define BEMPENB_0 USB200.BEMPENB -#define SOFCFG_0 USB200.SOFCFG -#define INTSTS0_0 USB200.INTSTS0 -#define INTSTS1_0 USB200.INTSTS1 -#define BRDYSTS_0 USB200.BRDYSTS -#define NRDYSTS_0 USB200.NRDYSTS -#define BEMPSTS_0 USB200.BEMPSTS -#define FRMNUM_0 USB200.FRMNUM -#define UFRMNUM_0 USB200.UFRMNUM -#define USBADDR_0 USB200.USBADDR -#define USBREQ_0 USB200.USBREQ -#define USBVAL_0 USB200.USBVAL -#define USBINDX_0 USB200.USBINDX -#define USBLENG_0 USB200.USBLENG -#define DCPCFG_0 USB200.DCPCFG -#define DCPMAXP_0 USB200.DCPMAXP -#define DCPCTR_0 USB200.DCPCTR -#define PIPESEL_0 USB200.PIPESEL -#define PIPECFG_0 USB200.PIPECFG -#define PIPEBUF_0 USB200.PIPEBUF -#define PIPEMAXP_0 USB200.PIPEMAXP -#define PIPEPERI_0 USB200.PIPEPERI -#define PIPE1CTR_0 USB200.PIPE1CTR -#define PIPE2CTR_0 USB200.PIPE2CTR -#define PIPE3CTR_0 USB200.PIPE3CTR -#define PIPE4CTR_0 USB200.PIPE4CTR -#define PIPE5CTR_0 USB200.PIPE5CTR -#define PIPE6CTR_0 USB200.PIPE6CTR -#define PIPE7CTR_0 USB200.PIPE7CTR -#define PIPE8CTR_0 USB200.PIPE8CTR -#define PIPE9CTR_0 USB200.PIPE9CTR -#define PIPEACTR_0 USB200.PIPEACTR -#define PIPEBCTR_0 USB200.PIPEBCTR -#define PIPECCTR_0 USB200.PIPECCTR -#define PIPEDCTR_0 USB200.PIPEDCTR -#define PIPEECTR_0 USB200.PIPEECTR -#define PIPEFCTR_0 USB200.PIPEFCTR -#define PIPE1TRE_0 USB200.PIPE1TRE -#define PIPE1TRN_0 USB200.PIPE1TRN -#define PIPE2TRE_0 USB200.PIPE2TRE -#define PIPE2TRN_0 USB200.PIPE2TRN -#define PIPE3TRE_0 USB200.PIPE3TRE -#define PIPE3TRN_0 USB200.PIPE3TRN -#define PIPE4TRE_0 USB200.PIPE4TRE -#define PIPE4TRN_0 USB200.PIPE4TRN -#define PIPE5TRE_0 USB200.PIPE5TRE -#define PIPE5TRN_0 USB200.PIPE5TRN -#define PIPEBTRE_0 USB200.PIPEBTRE -#define PIPEBTRN_0 USB200.PIPEBTRN -#define PIPECTRE_0 USB200.PIPECTRE -#define PIPECTRN_0 USB200.PIPECTRN -#define PIPEDTRE_0 USB200.PIPEDTRE -#define PIPEDTRN_0 USB200.PIPEDTRN -#define PIPEETRE_0 USB200.PIPEETRE -#define PIPEETRN_0 USB200.PIPEETRN -#define PIPEFTRE_0 USB200.PIPEFTRE -#define PIPEFTRN_0 USB200.PIPEFTRN -#define PIPE9TRE_0 USB200.PIPE9TRE -#define PIPE9TRN_0 USB200.PIPE9TRN -#define PIPEATRE_0 USB200.PIPEATRE -#define PIPEATRN_0 USB200.PIPEATRN -#define DEVADD0_0 USB200.DEVADD0 -#define DEVADD1_0 USB200.DEVADD1 -#define DEVADD2_0 USB200.DEVADD2 -#define DEVADD3_0 USB200.DEVADD3 -#define DEVADD4_0 USB200.DEVADD4 -#define DEVADD5_0 USB200.DEVADD5 -#define DEVADD6_0 USB200.DEVADD6 -#define DEVADD7_0 USB200.DEVADD7 -#define DEVADD8_0 USB200.DEVADD8 -#define DEVADD9_0 USB200.DEVADD9 -#define DEVADDA_0 USB200.DEVADDA -#define SUSPMODE_0 USB200.SUSPMODE -#define D0FIFOB0_0 USB200.D0FIFOB0 -#define D0FIFOB1_0 USB200.D0FIFOB1 -#define D0FIFOB2_0 USB200.D0FIFOB2 -#define D0FIFOB3_0 USB200.D0FIFOB3 -#define D0FIFOB4_0 USB200.D0FIFOB4 -#define D0FIFOB5_0 USB200.D0FIFOB5 -#define D0FIFOB6_0 USB200.D0FIFOB6 -#define D0FIFOB7_0 USB200.D0FIFOB7 -#define D1FIFOB0_0 USB200.D1FIFOB0 -#define D1FIFOB1_0 USB200.D1FIFOB1 -#define D1FIFOB2_0 USB200.D1FIFOB2 -#define D1FIFOB3_0 USB200.D1FIFOB3 -#define D1FIFOB4_0 USB200.D1FIFOB4 -#define D1FIFOB5_0 USB200.D1FIFOB5 -#define D1FIFOB6_0 USB200.D1FIFOB6 -#define D1FIFOB7_0 USB200.D1FIFOB7 -#define SYSCFG0_1 USB201.SYSCFG0 -#define BUSWAIT_1 USB201.BUSWAIT -#define SYSSTS0_1 USB201.SYSSTS0 -#define DVSTCTR0_1 USB201.DVSTCTR0 -#define TESTMODE_1 USB201.TESTMODE -#define D0FBCFG_1 USB201.D0FBCFG -#define D1FBCFG_1 USB201.D1FBCFG -#define CFIFO_1 USB201.CFIFO.UINT32 -#define CFIFO_1L USB201.CFIFO.UINT16[L] -#define CFIFO_1H USB201.CFIFO.UINT16[H] -#define CFIFO_1LL USB201.CFIFO.UINT8[LL] -#define CFIFO_1LH USB201.CFIFO.UINT8[LH] -#define CFIFO_1HL USB201.CFIFO.UINT8[HL] -#define CFIFO_1HH USB201.CFIFO.UINT8[HH] -#define D0FIFO_1 USB201.D0FIFO.UINT32 -#define D0FIFO_1L USB201.D0FIFO.UINT16[L] -#define D0FIFO_1H USB201.D0FIFO.UINT16[H] -#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL] -#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH] -#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL] -#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH] -#define D1FIFO_1 USB201.D1FIFO.UINT32 -#define D1FIFO_1L USB201.D1FIFO.UINT16[L] -#define D1FIFO_1H USB201.D1FIFO.UINT16[H] -#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL] -#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH] -#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL] -#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH] -#define CFIFOSEL_1 USB201.CFIFOSEL -#define CFIFOCTR_1 USB201.CFIFOCTR -#define D0FIFOSEL_1 USB201.D0FIFOSEL -#define D0FIFOCTR_1 USB201.D0FIFOCTR -#define D1FIFOSEL_1 USB201.D1FIFOSEL -#define D1FIFOCTR_1 USB201.D1FIFOCTR -#define INTENB0_1 USB201.INTENB0 -#define INTENB1_1 USB201.INTENB1 -#define BRDYENB_1 USB201.BRDYENB -#define NRDYENB_1 USB201.NRDYENB -#define BEMPENB_1 USB201.BEMPENB -#define SOFCFG_1 USB201.SOFCFG -#define INTSTS0_1 USB201.INTSTS0 -#define INTSTS1_1 USB201.INTSTS1 -#define BRDYSTS_1 USB201.BRDYSTS -#define NRDYSTS_1 USB201.NRDYSTS -#define BEMPSTS_1 USB201.BEMPSTS -#define FRMNUM_1 USB201.FRMNUM -#define UFRMNUM_1 USB201.UFRMNUM -#define USBADDR_1 USB201.USBADDR -#define USBREQ_1 USB201.USBREQ -#define USBVAL_1 USB201.USBVAL -#define USBINDX_1 USB201.USBINDX -#define USBLENG_1 USB201.USBLENG -#define DCPCFG_1 USB201.DCPCFG -#define DCPMAXP_1 USB201.DCPMAXP -#define DCPCTR_1 USB201.DCPCTR -#define PIPESEL_1 USB201.PIPESEL -#define PIPECFG_1 USB201.PIPECFG -#define PIPEBUF_1 USB201.PIPEBUF -#define PIPEMAXP_1 USB201.PIPEMAXP -#define PIPEPERI_1 USB201.PIPEPERI -#define PIPE1CTR_1 USB201.PIPE1CTR -#define PIPE2CTR_1 USB201.PIPE2CTR -#define PIPE3CTR_1 USB201.PIPE3CTR -#define PIPE4CTR_1 USB201.PIPE4CTR -#define PIPE5CTR_1 USB201.PIPE5CTR -#define PIPE6CTR_1 USB201.PIPE6CTR -#define PIPE7CTR_1 USB201.PIPE7CTR -#define PIPE8CTR_1 USB201.PIPE8CTR -#define PIPE9CTR_1 USB201.PIPE9CTR -#define PIPEACTR_1 USB201.PIPEACTR -#define PIPEBCTR_1 USB201.PIPEBCTR -#define PIPECCTR_1 USB201.PIPECCTR -#define PIPEDCTR_1 USB201.PIPEDCTR -#define PIPEECTR_1 USB201.PIPEECTR -#define PIPEFCTR_1 USB201.PIPEFCTR -#define PIPE1TRE_1 USB201.PIPE1TRE -#define PIPE1TRN_1 USB201.PIPE1TRN -#define PIPE2TRE_1 USB201.PIPE2TRE -#define PIPE2TRN_1 USB201.PIPE2TRN -#define PIPE3TRE_1 USB201.PIPE3TRE -#define PIPE3TRN_1 USB201.PIPE3TRN -#define PIPE4TRE_1 USB201.PIPE4TRE -#define PIPE4TRN_1 USB201.PIPE4TRN -#define PIPE5TRE_1 USB201.PIPE5TRE -#define PIPE5TRN_1 USB201.PIPE5TRN -#define PIPEBTRE_1 USB201.PIPEBTRE -#define PIPEBTRN_1 USB201.PIPEBTRN -#define PIPECTRE_1 USB201.PIPECTRE -#define PIPECTRN_1 USB201.PIPECTRN -#define PIPEDTRE_1 USB201.PIPEDTRE -#define PIPEDTRN_1 USB201.PIPEDTRN -#define PIPEETRE_1 USB201.PIPEETRE -#define PIPEETRN_1 USB201.PIPEETRN -#define PIPEFTRE_1 USB201.PIPEFTRE -#define PIPEFTRN_1 USB201.PIPEFTRN -#define PIPE9TRE_1 USB201.PIPE9TRE -#define PIPE9TRN_1 USB201.PIPE9TRN -#define PIPEATRE_1 USB201.PIPEATRE -#define PIPEATRN_1 USB201.PIPEATRN -#define DEVADD0_1 USB201.DEVADD0 -#define DEVADD1_1 USB201.DEVADD1 -#define DEVADD2_1 USB201.DEVADD2 -#define DEVADD3_1 USB201.DEVADD3 -#define DEVADD4_1 USB201.DEVADD4 -#define DEVADD5_1 USB201.DEVADD5 -#define DEVADD6_1 USB201.DEVADD6 -#define DEVADD7_1 USB201.DEVADD7 -#define DEVADD8_1 USB201.DEVADD8 -#define DEVADD9_1 USB201.DEVADD9 -#define DEVADDA_1 USB201.DEVADDA -#define SUSPMODE_1 USB201.SUSPMODE -#define D0FIFOB0_1 USB201.D0FIFOB0 -#define D0FIFOB1_1 USB201.D0FIFOB1 -#define D0FIFOB2_1 USB201.D0FIFOB2 -#define D0FIFOB3_1 USB201.D0FIFOB3 -#define D0FIFOB4_1 USB201.D0FIFOB4 -#define D0FIFOB5_1 USB201.D0FIFOB5 -#define D0FIFOB6_1 USB201.D0FIFOB6 -#define D0FIFOB7_1 USB201.D0FIFOB7 -#define D1FIFOB0_1 USB201.D1FIFOB0 -#define D1FIFOB1_1 USB201.D1FIFOB1 -#define D1FIFOB2_1 USB201.D1FIFOB2 -#define D1FIFOB3_1 USB201.D1FIFOB3 -#define D1FIFOB4_1 USB201.D1FIFOB4 -#define D1FIFOB5_1 USB201.D1FIFOB5 -#define D1FIFOB6_1 USB201.D1FIFOB6 -#define D1FIFOB7_1 USB201.D1FIFOB7 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h index d20922524e..3c962342e5 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h @@ -18,21 +18,1004 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : vdc5_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef VDC5_IODEFINE_H #define VDC5_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_vdc5 -{ /* VDC5 */ +#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ +#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ + + +/* Start of channel array defines of VDC5 */ + +/* Channel array defines of VDC5 */ +/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ +#define VDC5_COUNT (2) +#define VDC5_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &VDC50, &VDC51 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */ +/*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC50_FROM_GR2_AB7_ARRAY_COUNT (2) +#define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ + &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ +#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ +#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ +#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ + + + + +/* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ + &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ +#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ +#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ +#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ + + + + +/* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */ +/*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ +#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT (2) +#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ + &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ +#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ +#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ +#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ + + + + +/* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ +#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ + &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ +#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ +#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ +#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ + + + + +/* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ +#define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ + &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ +#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ +#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ +#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ + + + + +/* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */ +/*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC50_FROM_GR0_AB7_ARRAY_COUNT (2) +#define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ + &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ +#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ +#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ +#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ + + + + +/* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ + &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ +#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ +#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ +#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ + + +/* End of channel array defines of VDC5 */ + + +#define VDC50INP_UPDATE (VDC50.INP_UPDATE) +#define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT) +#define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT) +#define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ) +#define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ) +#define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE) +#define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0) +#define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1) +#define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE) +#define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0) +#define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1) +#define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0) +#define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1) +#define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0) +#define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1) +#define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG) +#define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE) +#define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1) +#define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2) +#define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3) +#define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4) +#define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5) +#define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6) +#define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7) +#define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9) +#define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0) +#define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT) +#define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1) +#define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2) +#define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3) +#define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4) +#define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5) +#define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6) +#define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7) +#define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1) +#define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2) +#define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3) +#define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4) +#define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5) +#define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6) +#define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7) +#define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8) +#define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1) +#define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE) +#define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1) +#define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2) +#define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3) +#define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4) +#define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5) +#define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6) +#define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7) +#define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8) +#define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9) +#define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10) +#define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11) +#define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1) +#define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0) +#define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1) +#define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2) +#define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3) +#define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD) +#define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT) +#define VDC50GR0_UPDATE (VDC50.GR0_UPDATE) +#define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD) +#define VDC50GR0_FLM1 (VDC50.GR0_FLM1) +#define VDC50GR0_FLM2 (VDC50.GR0_FLM2) +#define VDC50GR0_FLM3 (VDC50.GR0_FLM3) +#define VDC50GR0_FLM4 (VDC50.GR0_FLM4) +#define VDC50GR0_FLM5 (VDC50.GR0_FLM5) +#define VDC50GR0_FLM6 (VDC50.GR0_FLM6) +#define VDC50GR0_AB1 (VDC50.GR0_AB1) +#define VDC50GR0_AB2 (VDC50.GR0_AB2) +#define VDC50GR0_AB3 (VDC50.GR0_AB3) +#define VDC50GR0_AB7 (VDC50.GR0_AB7) +#define VDC50GR0_AB8 (VDC50.GR0_AB8) +#define VDC50GR0_AB9 (VDC50.GR0_AB9) +#define VDC50GR0_AB10 (VDC50.GR0_AB10) +#define VDC50GR0_AB11 (VDC50.GR0_AB11) +#define VDC50GR0_BASE (VDC50.GR0_BASE) +#define VDC50GR0_CLUT (VDC50.GR0_CLUT) +#define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE) +#define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET) +#define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1) +#define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2) +#define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3) +#define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1) +#define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2) +#define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3) +#define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4) +#define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5) +#define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6) +#define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1) +#define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2) +#define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE) +#define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0) +#define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1) +#define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0) +#define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1) +#define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0) +#define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1) +#define VDC50GR2_UPDATE (VDC50.GR2_UPDATE) +#define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD) +#define VDC50GR2_FLM1 (VDC50.GR2_FLM1) +#define VDC50GR2_FLM2 (VDC50.GR2_FLM2) +#define VDC50GR2_FLM3 (VDC50.GR2_FLM3) +#define VDC50GR2_FLM4 (VDC50.GR2_FLM4) +#define VDC50GR2_FLM5 (VDC50.GR2_FLM5) +#define VDC50GR2_FLM6 (VDC50.GR2_FLM6) +#define VDC50GR2_AB1 (VDC50.GR2_AB1) +#define VDC50GR2_AB2 (VDC50.GR2_AB2) +#define VDC50GR2_AB3 (VDC50.GR2_AB3) +#define VDC50GR2_AB4 (VDC50.GR2_AB4) +#define VDC50GR2_AB5 (VDC50.GR2_AB5) +#define VDC50GR2_AB6 (VDC50.GR2_AB6) +#define VDC50GR2_AB7 (VDC50.GR2_AB7) +#define VDC50GR2_AB8 (VDC50.GR2_AB8) +#define VDC50GR2_AB9 (VDC50.GR2_AB9) +#define VDC50GR2_AB10 (VDC50.GR2_AB10) +#define VDC50GR2_AB11 (VDC50.GR2_AB11) +#define VDC50GR2_BASE (VDC50.GR2_BASE) +#define VDC50GR2_CLUT (VDC50.GR2_CLUT) +#define VDC50GR2_MON (VDC50.GR2_MON) +#define VDC50GR3_UPDATE (VDC50.GR3_UPDATE) +#define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD) +#define VDC50GR3_FLM1 (VDC50.GR3_FLM1) +#define VDC50GR3_FLM2 (VDC50.GR3_FLM2) +#define VDC50GR3_FLM3 (VDC50.GR3_FLM3) +#define VDC50GR3_FLM4 (VDC50.GR3_FLM4) +#define VDC50GR3_FLM5 (VDC50.GR3_FLM5) +#define VDC50GR3_FLM6 (VDC50.GR3_FLM6) +#define VDC50GR3_AB1 (VDC50.GR3_AB1) +#define VDC50GR3_AB2 (VDC50.GR3_AB2) +#define VDC50GR3_AB3 (VDC50.GR3_AB3) +#define VDC50GR3_AB4 (VDC50.GR3_AB4) +#define VDC50GR3_AB5 (VDC50.GR3_AB5) +#define VDC50GR3_AB6 (VDC50.GR3_AB6) +#define VDC50GR3_AB7 (VDC50.GR3_AB7) +#define VDC50GR3_AB8 (VDC50.GR3_AB8) +#define VDC50GR3_AB9 (VDC50.GR3_AB9) +#define VDC50GR3_AB10 (VDC50.GR3_AB10) +#define VDC50GR3_AB11 (VDC50.GR3_AB11) +#define VDC50GR3_BASE (VDC50.GR3_BASE) +#define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT) +#define VDC50GR3_MON (VDC50.GR3_MON) +#define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE) +#define VDC50GAM_SW (VDC50.GAM_SW) +#define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1) +#define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2) +#define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3) +#define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4) +#define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5) +#define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6) +#define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7) +#define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8) +#define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9) +#define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10) +#define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11) +#define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12) +#define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13) +#define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14) +#define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15) +#define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16) +#define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1) +#define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2) +#define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3) +#define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4) +#define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5) +#define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6) +#define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7) +#define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8) +#define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE) +#define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1) +#define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2) +#define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3) +#define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4) +#define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5) +#define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6) +#define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7) +#define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8) +#define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9) +#define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10) +#define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11) +#define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12) +#define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13) +#define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14) +#define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15) +#define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16) +#define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1) +#define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2) +#define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3) +#define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4) +#define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5) +#define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6) +#define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7) +#define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8) +#define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE) +#define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1) +#define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2) +#define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3) +#define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4) +#define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5) +#define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6) +#define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7) +#define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8) +#define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9) +#define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10) +#define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11) +#define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12) +#define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13) +#define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14) +#define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15) +#define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16) +#define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1) +#define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2) +#define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3) +#define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4) +#define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5) +#define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6) +#define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7) +#define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8) +#define VDC50TCON_UPDATE (VDC50.TCON_UPDATE) +#define VDC50TCON_TIM (VDC50.TCON_TIM) +#define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1) +#define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2) +#define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1) +#define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2) +#define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1) +#define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2) +#define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1) +#define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2) +#define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1) +#define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2) +#define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1) +#define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2) +#define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1) +#define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2) +#define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE) +#define VDC50OUT_UPDATE (VDC50.OUT_UPDATE) +#define VDC50OUT_SET (VDC50.OUT_SET) +#define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1) +#define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2) +#define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST) +#define VDC50OUT_PDTHA (VDC50.OUT_PDTHA) +#define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE) +#define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1) +#define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2) +#define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3) +#define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4) +#define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5) +#define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6) +#define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK) +#define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT) +#define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE) +#define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1) +#define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2) +#define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3) +#define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4) +#define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5) +#define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6) +#define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7) +#define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9) +#define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0) +#define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT) +#define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1) +#define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2) +#define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3) +#define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4) +#define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5) +#define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6) +#define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7) +#define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1) +#define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2) +#define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3) +#define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4) +#define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5) +#define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6) +#define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7) +#define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8) +#define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1) +#define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE) +#define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1) +#define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2) +#define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3) +#define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4) +#define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5) +#define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6) +#define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7) +#define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8) +#define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9) +#define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10) +#define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11) +#define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1) +#define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0) +#define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1) +#define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2) +#define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3) +#define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD) +#define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT) +#define VDC50GR1_UPDATE (VDC50.GR1_UPDATE) +#define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD) +#define VDC50GR1_FLM1 (VDC50.GR1_FLM1) +#define VDC50GR1_FLM2 (VDC50.GR1_FLM2) +#define VDC50GR1_FLM3 (VDC50.GR1_FLM3) +#define VDC50GR1_FLM4 (VDC50.GR1_FLM4) +#define VDC50GR1_FLM5 (VDC50.GR1_FLM5) +#define VDC50GR1_FLM6 (VDC50.GR1_FLM6) +#define VDC50GR1_AB1 (VDC50.GR1_AB1) +#define VDC50GR1_AB2 (VDC50.GR1_AB2) +#define VDC50GR1_AB3 (VDC50.GR1_AB3) +#define VDC50GR1_AB4 (VDC50.GR1_AB4) +#define VDC50GR1_AB5 (VDC50.GR1_AB5) +#define VDC50GR1_AB6 (VDC50.GR1_AB6) +#define VDC50GR1_AB7 (VDC50.GR1_AB7) +#define VDC50GR1_AB8 (VDC50.GR1_AB8) +#define VDC50GR1_AB9 (VDC50.GR1_AB9) +#define VDC50GR1_AB10 (VDC50.GR1_AB10) +#define VDC50GR1_AB11 (VDC50.GR1_AB11) +#define VDC50GR1_BASE (VDC50.GR1_BASE) +#define VDC50GR1_CLUT (VDC50.GR1_CLUT) +#define VDC50GR1_MON (VDC50.GR1_MON) +#define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE) +#define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET) +#define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1) +#define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2) +#define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3) +#define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1) +#define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2) +#define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3) +#define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4) +#define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5) +#define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6) +#define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1) +#define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2) +#define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE) +#define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0) +#define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1) +#define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0) +#define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1) +#define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0) +#define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1) +#define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE) +#define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1) +#define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2) +#define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3) +#define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4) +#define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5) +#define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6) +#define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7) +#define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE) +#define VDC50GR_VIN_MON (VDC50.GR_VIN_MON) +#define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE) +#define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1) +#define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2) +#define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3) +#define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4) +#define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5) +#define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6) +#define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7) +#define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1) +#define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2) +#define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3) +#define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7) +#define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1) +#define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2) +#define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3) +#define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8) +#define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1) +#define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE) +#define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1) +#define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2) +#define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3) +#define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4) +#define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5) +#define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6) +#define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7) +#define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE) +#define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD) +#define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1) +#define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2) +#define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3) +#define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4) +#define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5) +#define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6) +#define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1) +#define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2) +#define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3) +#define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7) +#define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8) +#define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9) +#define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10) +#define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11) +#define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE) +#define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT) +#define VDC50GR_OIR_MON (VDC50.GR_OIR_MON) +#define VDC51INP_UPDATE (VDC51.INP_UPDATE) +#define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT) +#define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT) +#define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ) +#define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ) +#define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE) +#define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0) +#define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1) +#define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE) +#define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0) +#define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1) +#define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0) +#define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1) +#define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0) +#define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1) +#define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG) +#define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE) +#define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1) +#define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2) +#define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3) +#define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4) +#define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5) +#define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6) +#define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7) +#define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9) +#define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0) +#define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT) +#define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1) +#define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2) +#define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3) +#define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4) +#define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5) +#define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6) +#define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7) +#define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1) +#define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2) +#define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3) +#define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4) +#define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5) +#define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6) +#define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7) +#define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8) +#define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1) +#define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE) +#define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1) +#define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2) +#define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3) +#define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4) +#define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5) +#define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6) +#define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7) +#define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8) +#define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9) +#define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10) +#define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11) +#define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1) +#define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0) +#define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1) +#define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2) +#define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3) +#define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD) +#define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT) +#define VDC51GR0_UPDATE (VDC51.GR0_UPDATE) +#define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD) +#define VDC51GR0_FLM1 (VDC51.GR0_FLM1) +#define VDC51GR0_FLM2 (VDC51.GR0_FLM2) +#define VDC51GR0_FLM3 (VDC51.GR0_FLM3) +#define VDC51GR0_FLM4 (VDC51.GR0_FLM4) +#define VDC51GR0_FLM5 (VDC51.GR0_FLM5) +#define VDC51GR0_FLM6 (VDC51.GR0_FLM6) +#define VDC51GR0_AB1 (VDC51.GR0_AB1) +#define VDC51GR0_AB2 (VDC51.GR0_AB2) +#define VDC51GR0_AB3 (VDC51.GR0_AB3) +#define VDC51GR0_AB7 (VDC51.GR0_AB7) +#define VDC51GR0_AB8 (VDC51.GR0_AB8) +#define VDC51GR0_AB9 (VDC51.GR0_AB9) +#define VDC51GR0_AB10 (VDC51.GR0_AB10) +#define VDC51GR0_AB11 (VDC51.GR0_AB11) +#define VDC51GR0_BASE (VDC51.GR0_BASE) +#define VDC51GR0_CLUT (VDC51.GR0_CLUT) +#define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE) +#define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET) +#define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1) +#define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2) +#define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3) +#define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1) +#define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2) +#define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3) +#define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4) +#define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5) +#define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6) +#define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1) +#define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2) +#define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE) +#define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0) +#define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1) +#define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0) +#define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1) +#define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0) +#define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1) +#define VDC51GR2_UPDATE (VDC51.GR2_UPDATE) +#define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD) +#define VDC51GR2_FLM1 (VDC51.GR2_FLM1) +#define VDC51GR2_FLM2 (VDC51.GR2_FLM2) +#define VDC51GR2_FLM3 (VDC51.GR2_FLM3) +#define VDC51GR2_FLM4 (VDC51.GR2_FLM4) +#define VDC51GR2_FLM5 (VDC51.GR2_FLM5) +#define VDC51GR2_FLM6 (VDC51.GR2_FLM6) +#define VDC51GR2_AB1 (VDC51.GR2_AB1) +#define VDC51GR2_AB2 (VDC51.GR2_AB2) +#define VDC51GR2_AB3 (VDC51.GR2_AB3) +#define VDC51GR2_AB4 (VDC51.GR2_AB4) +#define VDC51GR2_AB5 (VDC51.GR2_AB5) +#define VDC51GR2_AB6 (VDC51.GR2_AB6) +#define VDC51GR2_AB7 (VDC51.GR2_AB7) +#define VDC51GR2_AB8 (VDC51.GR2_AB8) +#define VDC51GR2_AB9 (VDC51.GR2_AB9) +#define VDC51GR2_AB10 (VDC51.GR2_AB10) +#define VDC51GR2_AB11 (VDC51.GR2_AB11) +#define VDC51GR2_BASE (VDC51.GR2_BASE) +#define VDC51GR2_CLUT (VDC51.GR2_CLUT) +#define VDC51GR2_MON (VDC51.GR2_MON) +#define VDC51GR3_UPDATE (VDC51.GR3_UPDATE) +#define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD) +#define VDC51GR3_FLM1 (VDC51.GR3_FLM1) +#define VDC51GR3_FLM2 (VDC51.GR3_FLM2) +#define VDC51GR3_FLM3 (VDC51.GR3_FLM3) +#define VDC51GR3_FLM4 (VDC51.GR3_FLM4) +#define VDC51GR3_FLM5 (VDC51.GR3_FLM5) +#define VDC51GR3_FLM6 (VDC51.GR3_FLM6) +#define VDC51GR3_AB1 (VDC51.GR3_AB1) +#define VDC51GR3_AB2 (VDC51.GR3_AB2) +#define VDC51GR3_AB3 (VDC51.GR3_AB3) +#define VDC51GR3_AB4 (VDC51.GR3_AB4) +#define VDC51GR3_AB5 (VDC51.GR3_AB5) +#define VDC51GR3_AB6 (VDC51.GR3_AB6) +#define VDC51GR3_AB7 (VDC51.GR3_AB7) +#define VDC51GR3_AB8 (VDC51.GR3_AB8) +#define VDC51GR3_AB9 (VDC51.GR3_AB9) +#define VDC51GR3_AB10 (VDC51.GR3_AB10) +#define VDC51GR3_AB11 (VDC51.GR3_AB11) +#define VDC51GR3_BASE (VDC51.GR3_BASE) +#define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT) +#define VDC51GR3_MON (VDC51.GR3_MON) +#define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE) +#define VDC51GAM_SW (VDC51.GAM_SW) +#define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1) +#define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2) +#define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3) +#define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4) +#define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5) +#define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6) +#define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7) +#define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8) +#define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9) +#define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10) +#define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11) +#define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12) +#define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13) +#define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14) +#define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15) +#define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16) +#define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1) +#define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2) +#define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3) +#define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4) +#define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5) +#define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6) +#define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7) +#define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8) +#define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE) +#define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1) +#define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2) +#define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3) +#define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4) +#define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5) +#define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6) +#define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7) +#define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8) +#define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9) +#define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10) +#define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11) +#define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12) +#define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13) +#define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14) +#define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15) +#define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16) +#define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1) +#define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2) +#define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3) +#define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4) +#define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5) +#define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6) +#define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7) +#define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8) +#define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE) +#define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1) +#define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2) +#define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3) +#define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4) +#define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5) +#define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6) +#define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7) +#define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8) +#define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9) +#define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10) +#define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11) +#define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12) +#define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13) +#define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14) +#define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15) +#define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16) +#define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1) +#define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2) +#define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3) +#define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4) +#define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5) +#define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6) +#define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7) +#define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8) +#define VDC51TCON_UPDATE (VDC51.TCON_UPDATE) +#define VDC51TCON_TIM (VDC51.TCON_TIM) +#define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1) +#define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2) +#define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1) +#define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2) +#define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1) +#define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2) +#define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1) +#define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2) +#define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1) +#define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2) +#define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1) +#define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2) +#define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1) +#define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2) +#define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE) +#define VDC51OUT_UPDATE (VDC51.OUT_UPDATE) +#define VDC51OUT_SET (VDC51.OUT_SET) +#define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1) +#define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2) +#define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST) +#define VDC51OUT_PDTHA (VDC51.OUT_PDTHA) +#define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE) +#define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1) +#define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2) +#define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3) +#define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4) +#define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5) +#define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6) +#define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK) +#define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT) +#define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE) +#define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1) +#define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2) +#define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3) +#define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4) +#define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5) +#define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6) +#define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7) +#define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9) +#define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0) +#define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT) +#define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1) +#define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2) +#define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3) +#define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4) +#define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5) +#define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6) +#define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7) +#define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1) +#define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2) +#define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3) +#define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4) +#define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5) +#define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6) +#define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7) +#define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8) +#define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1) +#define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE) +#define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1) +#define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2) +#define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3) +#define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4) +#define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5) +#define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6) +#define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7) +#define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8) +#define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9) +#define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10) +#define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11) +#define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1) +#define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0) +#define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1) +#define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2) +#define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3) +#define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD) +#define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT) +#define VDC51GR1_UPDATE (VDC51.GR1_UPDATE) +#define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD) +#define VDC51GR1_FLM1 (VDC51.GR1_FLM1) +#define VDC51GR1_FLM2 (VDC51.GR1_FLM2) +#define VDC51GR1_FLM3 (VDC51.GR1_FLM3) +#define VDC51GR1_FLM4 (VDC51.GR1_FLM4) +#define VDC51GR1_FLM5 (VDC51.GR1_FLM5) +#define VDC51GR1_FLM6 (VDC51.GR1_FLM6) +#define VDC51GR1_AB1 (VDC51.GR1_AB1) +#define VDC51GR1_AB2 (VDC51.GR1_AB2) +#define VDC51GR1_AB3 (VDC51.GR1_AB3) +#define VDC51GR1_AB4 (VDC51.GR1_AB4) +#define VDC51GR1_AB5 (VDC51.GR1_AB5) +#define VDC51GR1_AB6 (VDC51.GR1_AB6) +#define VDC51GR1_AB7 (VDC51.GR1_AB7) +#define VDC51GR1_AB8 (VDC51.GR1_AB8) +#define VDC51GR1_AB9 (VDC51.GR1_AB9) +#define VDC51GR1_AB10 (VDC51.GR1_AB10) +#define VDC51GR1_AB11 (VDC51.GR1_AB11) +#define VDC51GR1_BASE (VDC51.GR1_BASE) +#define VDC51GR1_CLUT (VDC51.GR1_CLUT) +#define VDC51GR1_MON (VDC51.GR1_MON) +#define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE) +#define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET) +#define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1) +#define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2) +#define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3) +#define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1) +#define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2) +#define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3) +#define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4) +#define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5) +#define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6) +#define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1) +#define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2) +#define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE) +#define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0) +#define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1) +#define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0) +#define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1) +#define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0) +#define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1) +#define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE) +#define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1) +#define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2) +#define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3) +#define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4) +#define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5) +#define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6) +#define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7) +#define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE) +#define VDC51GR_VIN_MON (VDC51.GR_VIN_MON) +#define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE) +#define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1) +#define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2) +#define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3) +#define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4) +#define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5) +#define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6) +#define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7) +#define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1) +#define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2) +#define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3) +#define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7) +#define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1) +#define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2) +#define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3) +#define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8) +#define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1) +#define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE) +#define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1) +#define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2) +#define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3) +#define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4) +#define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5) +#define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6) +#define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7) +#define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE) +#define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD) +#define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1) +#define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2) +#define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3) +#define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4) +#define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5) +#define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6) +#define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1) +#define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2) +#define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3) +#define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7) +#define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8) +#define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9) +#define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10) +#define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11) +#define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE) +#define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT) +#define VDC51GR_OIR_MON (VDC51.GR_OIR_MON) + +#define VDC5_IMGCNT_NR_CNT0_COUNT (2) +#define VDC5_SC0_SCL0_FRC1_COUNT (7) +#define VDC5_SC0_SCL0_DS1_COUNT (7) +#define VDC5_SC0_SCL0_US1_COUNT (8) +#define VDC5_SC0_SCL1_WR1_COUNT (4) +#define VDC5_SC0_SCL1_PBUF0_COUNT (4) +#define VDC5_GR0_FLM1_COUNT (6) +#define VDC5_GR0_AB1_COUNT (3) +#define VDC5_ADJ0_ENH_TIM1_COUNT (3) +#define VDC5_ADJ0_ENH_SHP1_COUNT (6) +#define VDC5_ADJ0_ENH_LTI1_COUNT (2) +#define VDC5_GR2_FLM1_COUNT (6) +#define VDC5_GR2_AB1_COUNT (3) +#define VDC5_GR3_FLM1_COUNT (6) +#define VDC5_GR3_AB1_COUNT (3) +#define VDC5_GAM_G_LUT1_COUNT (16) +#define VDC5_GAM_G_AREA1_COUNT (8) +#define VDC5_GAM_B_LUT1_COUNT (16) +#define VDC5_GAM_B_AREA1_COUNT (8) +#define VDC5_GAM_R_LUT1_COUNT (16) +#define VDC5_GAM_R_AREA1_COUNT (8) +#define VDC5_TCON_TIM_STVA1_COUNT (2) +#define VDC5_TCON_TIM_STVB1_COUNT (2) +#define VDC5_TCON_TIM_STH1_COUNT (2) +#define VDC5_TCON_TIM_STB1_COUNT (2) +#define VDC5_TCON_TIM_CPV1_COUNT (2) +#define VDC5_TCON_TIM_POLA1_COUNT (2) +#define VDC5_TCON_TIM_POLB1_COUNT (2) +#define VDC5_OUT_BRIGHT1_COUNT (2) +#define VDC5_SYSCNT_INT1_COUNT (6) +#define VDC5_SC1_SCL0_FRC1_COUNT (7) +#define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) +#define VDC5_SC1_SC1_SCL0_US1_COUNT (8) +#define VDC5_SC1_SCL1_WR1_COUNT (4) +#define VDC5_SC1_SCL1_PBUF0_COUNT (4) +#define VDC5_GR1_FLM1_COUNT (6) +#define VDC5_GR1_AB1_COUNT (3) +#define VDC5_ADJ1_ENH_TIM1_COUNT (3) +#define VDC5_ADJ1_ENH_SHP1_COUNT (6) +#define VDC5_ADJ1_ENH_LTI1_COUNT (2) +#define VDC5_GR_VIN_AB1_COUNT (7) +#define VDC5_OIR_SCL0_FRC1_COUNT (7) +#define VDC5_OIR_SCL0_DS1_COUNT (3) +#define VDC5_OIR_SCL1_WR1_COUNT (4) +#define VDC5_GR_OIR_FLM1_COUNT (6) +#define VDC5_GR_OIR_AB1_COUNT (3) + + +typedef struct st_vdc5 +{ + /* VDC5 */ volatile uint32_t INP_UPDATE; /* INP_UPDATE */ volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */ volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */ @@ -40,7 +1023,8 @@ struct st_vdc5 volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */ volatile uint8_t dummy1[108]; /* */ volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */ -#define VDC5_IMGCNT_NR_CNT0_COUNT 2 + +/* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */ volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */ volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */ volatile uint8_t dummy2[20]; /* */ @@ -54,9 +1038,11 @@ struct st_vdc5 volatile uint8_t dummy3[4]; /* */ volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */ volatile uint8_t dummy4[60]; /* */ + /* start of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ -#define VDC5_SC0_SCL0_FRC1_COUNT 7 + +/* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */ volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ @@ -68,7 +1054,8 @@ struct st_vdc5 volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ -#define VDC5_SC0_SCL0_DS1_COUNT 7 + +/* #define VDC5_SC0_SCL0_DS1_COUNT (7) */ volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ @@ -76,7 +1063,8 @@ struct st_vdc5 volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ -#define VDC5_SC0_SCL0_US1_COUNT 8 + +/* #define VDC5_SC0_SCL0_US1_COUNT (8) */ volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ @@ -90,7 +1078,8 @@ struct st_vdc5 volatile uint8_t dummy7[16]; /* */ volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ volatile uint8_t dummy8[4]; /* */ -#define VDC5_SC0_SCL1_WR1_COUNT 4 + +/* #define VDC5_SC0_SCL1_WR1_COUNT (4) */ volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ @@ -102,35 +1091,44 @@ struct st_vdc5 volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ + /* end of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */ volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */ + /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ -#define VDC5_SC0_SCL1_PBUF0_COUNT 4 + +/* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */ volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ + /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ volatile uint8_t dummy10[44]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ -#define VDC5_GR0_FLM1_COUNT 6 + +/* #define VDC5_GR0_FLM1_COUNT (6) */ volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ -#define VDC5_GR0_AB1_COUNT 3 + +/* #define VDC5_GR0_AB1_COUNT (3) */ volatile uint32_t GR0_AB1; /* GR0_AB1 */ volatile uint32_t GR0_AB2; /* GR0_AB2 */ volatile uint32_t GR0_AB3; /* GR0_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint8_t dummy11[12]; /* */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR0_AB7; /* GR0_AB7 */ volatile uint32_t GR0_AB8; /* GR0_AB8 */ @@ -138,24 +1136,29 @@ struct st_vdc5 volatile uint32_t GR0_AB10; /* GR0_AB10 */ volatile uint32_t GR0_AB11; /* GR0_AB11 */ volatile uint32_t GR0_BASE; /* GR0_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR0_CLUT; /* GR0_CLUT */ volatile uint8_t dummy12[44]; /* */ + /* start of struct st_vdc5_from_adj0_update */ volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ -#define VDC5_ADJ0_ENH_TIM1_COUNT 3 + +/* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */ volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ -#define VDC5_ADJ0_ENH_SHP1_COUNT 6 + +/* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */ volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ -#define VDC5_ADJ0_ENH_LTI1_COUNT 2 + +/* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */ volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ @@ -165,26 +1168,32 @@ struct st_vdc5 volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ + /* end of struct st_vdc5_from_adj0_update */ volatile uint8_t dummy13[48]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */ volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */ -#define VDC5_GR2_FLM1_COUNT 6 + +/* #define VDC5_GR2_FLM1_COUNT (6) */ volatile uint32_t GR2_FLM1; /* GR2_FLM1 */ volatile uint32_t GR2_FLM2; /* GR2_FLM2 */ volatile uint32_t GR2_FLM3; /* GR2_FLM3 */ volatile uint32_t GR2_FLM4; /* GR2_FLM4 */ volatile uint32_t GR2_FLM5; /* GR2_FLM5 */ volatile uint32_t GR2_FLM6; /* GR2_FLM6 */ -#define VDC5_GR2_AB1_COUNT 3 + +/* #define VDC5_GR2_AB1_COUNT (3) */ volatile uint32_t GR2_AB1; /* GR2_AB1 */ volatile uint32_t GR2_AB2; /* GR2_AB2 */ volatile uint32_t GR2_AB3; /* GR2_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint32_t GR2_AB4; /* GR2_AB4 */ volatile uint32_t GR2_AB5; /* GR2_AB5 */ volatile uint32_t GR2_AB6; /* GR2_AB6 */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR2_AB7; /* GR2_AB7 */ volatile uint32_t GR2_AB8; /* GR2_AB8 */ @@ -192,28 +1201,34 @@ struct st_vdc5 volatile uint32_t GR2_AB10; /* GR2_AB10 */ volatile uint32_t GR2_AB11; /* GR2_AB11 */ volatile uint32_t GR2_BASE; /* GR2_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR2_CLUT; /* GR2_CLUT */ volatile uint32_t GR2_MON; /* GR2_MON */ volatile uint8_t dummy14[40]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */ volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */ -#define VDC5_GR3_FLM1_COUNT 6 + +/* #define VDC5_GR3_FLM1_COUNT (6) */ volatile uint32_t GR3_FLM1; /* GR3_FLM1 */ volatile uint32_t GR3_FLM2; /* GR3_FLM2 */ volatile uint32_t GR3_FLM3; /* GR3_FLM3 */ volatile uint32_t GR3_FLM4; /* GR3_FLM4 */ volatile uint32_t GR3_FLM5; /* GR3_FLM5 */ volatile uint32_t GR3_FLM6; /* GR3_FLM6 */ -#define VDC5_GR3_AB1_COUNT 3 + +/* #define VDC5_GR3_AB1_COUNT (3) */ volatile uint32_t GR3_AB1; /* GR3_AB1 */ volatile uint32_t GR3_AB2; /* GR3_AB2 */ volatile uint32_t GR3_AB3; /* GR3_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint32_t GR3_AB4; /* GR3_AB4 */ volatile uint32_t GR3_AB5; /* GR3_AB5 */ volatile uint32_t GR3_AB6; /* GR3_AB6 */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR3_AB7; /* GR3_AB7 */ volatile uint32_t GR3_AB8; /* GR3_AB8 */ @@ -221,13 +1236,15 @@ struct st_vdc5 volatile uint32_t GR3_AB10; /* GR3_AB10 */ volatile uint32_t GR3_AB11; /* GR3_AB11 */ volatile uint32_t GR3_BASE; /* GR3_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */ volatile uint32_t GR3_MON; /* GR3_MON */ volatile uint8_t dummy15[40]; /* */ volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */ volatile uint32_t GAM_SW; /* GAM_SW */ -#define VDC5_GAM_G_LUT1_COUNT 16 + +/* #define VDC5_GAM_G_LUT1_COUNT (16) */ volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */ volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */ volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */ @@ -244,7 +1261,8 @@ struct st_vdc5 volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */ volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */ volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */ -#define VDC5_GAM_G_AREA1_COUNT 8 + +/* #define VDC5_GAM_G_AREA1_COUNT (8) */ volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */ volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */ volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */ @@ -256,7 +1274,8 @@ struct st_vdc5 volatile uint8_t dummy16[24]; /* */ volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */ volatile uint8_t dummy17[4]; /* */ -#define VDC5_GAM_B_LUT1_COUNT 16 + +/* #define VDC5_GAM_B_LUT1_COUNT (16) */ volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */ volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */ volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */ @@ -273,7 +1292,8 @@ struct st_vdc5 volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */ volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */ volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */ -#define VDC5_GAM_B_AREA1_COUNT 8 + +/* #define VDC5_GAM_B_AREA1_COUNT (8) */ volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */ volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */ volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */ @@ -285,7 +1305,8 @@ struct st_vdc5 volatile uint8_t dummy18[24]; /* */ volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */ volatile uint8_t dummy19[4]; /* */ -#define VDC5_GAM_R_LUT1_COUNT 16 + +/* #define VDC5_GAM_R_LUT1_COUNT (16) */ volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */ volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */ volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */ @@ -302,7 +1323,8 @@ struct st_vdc5 volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */ volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */ volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */ -#define VDC5_GAM_R_AREA1_COUNT 8 + +/* #define VDC5_GAM_R_AREA1_COUNT (8) */ volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */ volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */ volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */ @@ -314,32 +1336,40 @@ struct st_vdc5 volatile uint8_t dummy20[24]; /* */ volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */ volatile uint32_t TCON_TIM; /* TCON_TIM */ -#define VDC5_TCON_TIM_STVA1_COUNT 2 + +/* #define VDC5_TCON_TIM_STVA1_COUNT (2) */ volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */ volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */ -#define VDC5_TCON_TIM_STVB1_COUNT 2 + +/* #define VDC5_TCON_TIM_STVB1_COUNT (2) */ volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */ volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */ -#define VDC5_TCON_TIM_STH1_COUNT 2 + +/* #define VDC5_TCON_TIM_STH1_COUNT (2) */ volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */ volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */ -#define VDC5_TCON_TIM_STB1_COUNT 2 + +/* #define VDC5_TCON_TIM_STB1_COUNT (2) */ volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */ volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */ -#define VDC5_TCON_TIM_CPV1_COUNT 2 + +/* #define VDC5_TCON_TIM_CPV1_COUNT (2) */ volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */ volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */ -#define VDC5_TCON_TIM_POLA1_COUNT 2 + +/* #define VDC5_TCON_TIM_POLA1_COUNT (2) */ volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */ volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */ -#define VDC5_TCON_TIM_POLB1_COUNT 2 + +/* #define VDC5_TCON_TIM_POLB1_COUNT (2) */ volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */ volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */ volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */ volatile uint8_t dummy21[60]; /* */ volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */ volatile uint32_t OUT_SET; /* OUT_SET */ -#define VDC5_OUT_BRIGHT1_COUNT 2 + +/* #define VDC5_OUT_BRIGHT1_COUNT (2) */ volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */ volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */ volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */ @@ -347,7 +1377,8 @@ struct st_vdc5 volatile uint8_t dummy22[12]; /* */ volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */ volatile uint8_t dummy23[88]; /* */ -#define VDC5_SYSCNT_INT1_COUNT 6 + +/* #define VDC5_SYSCNT_INT1_COUNT (6) */ volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */ volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */ volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */ @@ -357,9 +1388,11 @@ struct st_vdc5 volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */ volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */ volatile uint8_t dummy24[356]; /* */ + /* start of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */ -#define VDC5_SC1_SCL0_FRC1_COUNT 7 + +/* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */ volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */ volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */ volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */ @@ -371,7 +1404,8 @@ struct st_vdc5 volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */ volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */ volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */ -#define VDC5_SC1_SC1_SCL0_DS1_COUNT 7 + +/* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */ volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */ volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */ volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */ @@ -379,7 +1413,8 @@ struct st_vdc5 volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */ volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */ volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */ -#define VDC5_SC1_SC1_SCL0_US1_COUNT 8 + +/* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */ volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */ volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */ volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */ @@ -393,7 +1428,8 @@ struct st_vdc5 volatile uint8_t dummy27[16]; /* */ volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */ volatile uint8_t dummy28[4]; /* */ -#define VDC5_SC1_SCL1_WR1_COUNT 4 + +/* #define VDC5_SC1_SCL1_WR1_COUNT (4) */ volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */ volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */ volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */ @@ -405,37 +1441,46 @@ struct st_vdc5 volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */ volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */ volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */ + /* end of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */ volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */ + /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ -#define VDC5_SC1_SCL1_PBUF0_COUNT 4 + +/* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */ volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */ volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */ volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */ volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */ volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */ volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */ + /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ volatile uint8_t dummy30[44]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */ volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */ -#define VDC5_GR1_FLM1_COUNT 6 + +/* #define VDC5_GR1_FLM1_COUNT (6) */ volatile uint32_t GR1_FLM1; /* GR1_FLM1 */ volatile uint32_t GR1_FLM2; /* GR1_FLM2 */ volatile uint32_t GR1_FLM3; /* GR1_FLM3 */ volatile uint32_t GR1_FLM4; /* GR1_FLM4 */ volatile uint32_t GR1_FLM5; /* GR1_FLM5 */ volatile uint32_t GR1_FLM6; /* GR1_FLM6 */ -#define VDC5_GR1_AB1_COUNT 3 + +/* #define VDC5_GR1_AB1_COUNT (3) */ volatile uint32_t GR1_AB1; /* GR1_AB1 */ volatile uint32_t GR1_AB2; /* GR1_AB2 */ volatile uint32_t GR1_AB3; /* GR1_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint32_t GR1_AB4; /* GR1_AB4 */ volatile uint32_t GR1_AB5; /* GR1_AB5 */ volatile uint32_t GR1_AB6; /* GR1_AB6 */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR1_AB7; /* GR1_AB7 */ volatile uint32_t GR1_AB8; /* GR1_AB8 */ @@ -443,25 +1488,30 @@ struct st_vdc5 volatile uint32_t GR1_AB10; /* GR1_AB10 */ volatile uint32_t GR1_AB11; /* GR1_AB11 */ volatile uint32_t GR1_BASE; /* GR1_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR1_CLUT; /* GR1_CLUT */ volatile uint32_t GR1_MON; /* GR1_MON */ volatile uint8_t dummy31[40]; /* */ + /* start of struct st_vdc5_from_adj0_update */ volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */ volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */ -#define VDC5_ADJ1_ENH_TIM1_COUNT 3 + +/* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */ volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */ volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */ volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */ -#define VDC5_ADJ1_ENH_SHP1_COUNT 6 + +/* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */ volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */ volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */ volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */ volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */ volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */ volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */ -#define VDC5_ADJ1_ENH_LTI1_COUNT 2 + +/* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */ volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */ volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */ volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */ @@ -471,11 +1521,13 @@ struct st_vdc5 volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */ volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */ volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */ + /* end of struct st_vdc5_from_adj0_update */ volatile uint8_t dummy32[48]; /* */ volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */ volatile uint8_t dummy33[28]; /* */ -#define VDC5_GR_VIN_AB1_COUNT 7 + +/* #define VDC5_GR_VIN_AB1_COUNT (7) */ volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */ volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */ volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */ @@ -489,7 +1541,8 @@ struct st_vdc5 volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */ volatile uint8_t dummy36[40]; /* */ volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */ -#define VDC5_OIR_SCL0_FRC1_COUNT 7 + +/* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */ volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */ volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */ volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */ @@ -498,7 +1551,8 @@ struct st_vdc5 volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */ volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */ volatile uint8_t dummy37[12]; /* */ -#define VDC5_OIR_SCL0_DS1_COUNT 3 + +/* #define VDC5_OIR_SCL0_DS1_COUNT (3) */ volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */ volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */ volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */ @@ -514,7 +1568,8 @@ struct st_vdc5 volatile uint8_t dummy41[16]; /* */ volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */ volatile uint8_t dummy42[4]; /* */ -#define VDC5_OIR_SCL1_WR1_COUNT 4 + +/* #define VDC5_OIR_SCL1_WR1_COUNT (4) */ volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */ volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */ volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */ @@ -526,14 +1581,16 @@ struct st_vdc5 volatile uint8_t dummy44[88]; /* */ volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */ volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */ -#define VDC5_GR_OIR_FLM1_COUNT 6 + +/* #define VDC5_GR_OIR_FLM1_COUNT (6) */ volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */ volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */ volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */ volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */ volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */ volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */ -#define VDC5_GR_OIR_AB1_COUNT 3 + +/* #define VDC5_GR_OIR_AB1_COUNT (3) */ volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */ volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */ volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */ @@ -546,11 +1603,12 @@ struct st_vdc5 volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */ volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */ volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */ -}; +} r_io_vdc5_t; -struct st_vdc5_from_gr0_update +typedef struct st_vdc5_from_gr0_update { + volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ @@ -562,22 +1620,24 @@ struct st_vdc5_from_gr0_update volatile uint32_t GR0_AB1; /* GR0_AB1 */ volatile uint32_t GR0_AB2; /* GR0_AB2 */ volatile uint32_t GR0_AB3; /* GR0_AB3 */ -}; +} r_io_vdc5_from_gr0_update_t; -struct st_vdc5_from_gr0_ab7 +typedef struct st_vdc5_from_gr0_ab7 { + volatile uint32_t GR0_AB7; /* GR0_AB7 */ volatile uint32_t GR0_AB8; /* GR0_AB8 */ volatile uint32_t GR0_AB9; /* GR0_AB9 */ volatile uint32_t GR0_AB10; /* GR0_AB10 */ volatile uint32_t GR0_AB11; /* GR0_AB11 */ volatile uint32_t GR0_BASE; /* GR0_BASE */ -}; +} r_io_vdc5_from_gr0_ab7_t; -struct st_vdc5_from_adj0_update +typedef struct st_vdc5_from_adj0_update { + volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ @@ -598,11 +1658,12 @@ struct st_vdc5_from_adj0_update volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ -}; +} r_io_vdc5_from_adj0_update_t; -struct st_vdc5_from_sc0_scl0_update +typedef struct st_vdc5_from_sc0_scl0_update { + volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ @@ -646,951 +1707,82 @@ struct st_vdc5_from_sc0_scl0_update volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ -}; +} r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */; -struct st_vdc5_from_sc0_scl1_pbuf0 +typedef struct st_vdc5_from_sc0_scl1_pbuf0 { + volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ -}; +} r_io_vdc5_from_sc0_scl1_pbuf0_t; -#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ -#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ +/* Channel array defines of VDC5 (2)*/ +#ifdef DECLARE_VDC5_CHANNELS +volatile struct st_vdc5* VDC5[ VDC5_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC5_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC5_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS +volatile struct st_vdc5_from_sc0_scl1_pbuf0* VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_sc0_scl0_update* VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_adj0_update* VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */ +/* End of channel array defines of VDC5 (2)*/ -/* Start of channnel array defines of VDC5 */ - -/* Channnel array defines of VDC5 */ -/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ -#define VDC5_COUNT 2 -#define VDC5_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &VDC50, &VDC51 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - - - -/* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ -#define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2 -#define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ - &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ -#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ -#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ -#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ - - - - -/* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ -#define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ - &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ -#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ -#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ -#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ - - - - -/* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */ -/*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ -#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2 -#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ - &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ -#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ -#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ -#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ - - - - -/* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ -#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ - &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ -#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ -#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ -#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ - - - - -/* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ -#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ - &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ -#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ -#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ -#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ - - - - -/* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ -#define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2 -#define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ - &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ -#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ -#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ -#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ - - - - -/* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ -#define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ - &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ -#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ -#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ -#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ - - -/* End of channnel array defines of VDC5 */ - - -#define VDC50INP_UPDATE VDC50.INP_UPDATE -#define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT -#define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT -#define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ -#define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ -#define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE -#define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0 -#define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1 -#define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE -#define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0 -#define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1 -#define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0 -#define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1 -#define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0 -#define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1 -#define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG -#define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE -#define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1 -#define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2 -#define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3 -#define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4 -#define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5 -#define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6 -#define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7 -#define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9 -#define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0 -#define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT -#define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1 -#define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2 -#define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3 -#define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4 -#define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5 -#define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6 -#define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7 -#define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1 -#define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2 -#define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3 -#define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4 -#define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5 -#define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6 -#define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7 -#define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8 -#define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1 -#define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE -#define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1 -#define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2 -#define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3 -#define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4 -#define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5 -#define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6 -#define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7 -#define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8 -#define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9 -#define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10 -#define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11 -#define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1 -#define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0 -#define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1 -#define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2 -#define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3 -#define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD -#define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT -#define VDC50GR0_UPDATE VDC50.GR0_UPDATE -#define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD -#define VDC50GR0_FLM1 VDC50.GR0_FLM1 -#define VDC50GR0_FLM2 VDC50.GR0_FLM2 -#define VDC50GR0_FLM3 VDC50.GR0_FLM3 -#define VDC50GR0_FLM4 VDC50.GR0_FLM4 -#define VDC50GR0_FLM5 VDC50.GR0_FLM5 -#define VDC50GR0_FLM6 VDC50.GR0_FLM6 -#define VDC50GR0_AB1 VDC50.GR0_AB1 -#define VDC50GR0_AB2 VDC50.GR0_AB2 -#define VDC50GR0_AB3 VDC50.GR0_AB3 -#define VDC50GR0_AB7 VDC50.GR0_AB7 -#define VDC50GR0_AB8 VDC50.GR0_AB8 -#define VDC50GR0_AB9 VDC50.GR0_AB9 -#define VDC50GR0_AB10 VDC50.GR0_AB10 -#define VDC50GR0_AB11 VDC50.GR0_AB11 -#define VDC50GR0_BASE VDC50.GR0_BASE -#define VDC50GR0_CLUT VDC50.GR0_CLUT -#define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE -#define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET -#define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1 -#define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2 -#define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3 -#define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1 -#define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2 -#define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3 -#define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4 -#define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5 -#define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6 -#define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1 -#define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2 -#define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE -#define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0 -#define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1 -#define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0 -#define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1 -#define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0 -#define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1 -#define VDC50GR2_UPDATE VDC50.GR2_UPDATE -#define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD -#define VDC50GR2_FLM1 VDC50.GR2_FLM1 -#define VDC50GR2_FLM2 VDC50.GR2_FLM2 -#define VDC50GR2_FLM3 VDC50.GR2_FLM3 -#define VDC50GR2_FLM4 VDC50.GR2_FLM4 -#define VDC50GR2_FLM5 VDC50.GR2_FLM5 -#define VDC50GR2_FLM6 VDC50.GR2_FLM6 -#define VDC50GR2_AB1 VDC50.GR2_AB1 -#define VDC50GR2_AB2 VDC50.GR2_AB2 -#define VDC50GR2_AB3 VDC50.GR2_AB3 -#define VDC50GR2_AB4 VDC50.GR2_AB4 -#define VDC50GR2_AB5 VDC50.GR2_AB5 -#define VDC50GR2_AB6 VDC50.GR2_AB6 -#define VDC50GR2_AB7 VDC50.GR2_AB7 -#define VDC50GR2_AB8 VDC50.GR2_AB8 -#define VDC50GR2_AB9 VDC50.GR2_AB9 -#define VDC50GR2_AB10 VDC50.GR2_AB10 -#define VDC50GR2_AB11 VDC50.GR2_AB11 -#define VDC50GR2_BASE VDC50.GR2_BASE -#define VDC50GR2_CLUT VDC50.GR2_CLUT -#define VDC50GR2_MON VDC50.GR2_MON -#define VDC50GR3_UPDATE VDC50.GR3_UPDATE -#define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD -#define VDC50GR3_FLM1 VDC50.GR3_FLM1 -#define VDC50GR3_FLM2 VDC50.GR3_FLM2 -#define VDC50GR3_FLM3 VDC50.GR3_FLM3 -#define VDC50GR3_FLM4 VDC50.GR3_FLM4 -#define VDC50GR3_FLM5 VDC50.GR3_FLM5 -#define VDC50GR3_FLM6 VDC50.GR3_FLM6 -#define VDC50GR3_AB1 VDC50.GR3_AB1 -#define VDC50GR3_AB2 VDC50.GR3_AB2 -#define VDC50GR3_AB3 VDC50.GR3_AB3 -#define VDC50GR3_AB4 VDC50.GR3_AB4 -#define VDC50GR3_AB5 VDC50.GR3_AB5 -#define VDC50GR3_AB6 VDC50.GR3_AB6 -#define VDC50GR3_AB7 VDC50.GR3_AB7 -#define VDC50GR3_AB8 VDC50.GR3_AB8 -#define VDC50GR3_AB9 VDC50.GR3_AB9 -#define VDC50GR3_AB10 VDC50.GR3_AB10 -#define VDC50GR3_AB11 VDC50.GR3_AB11 -#define VDC50GR3_BASE VDC50.GR3_BASE -#define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT -#define VDC50GR3_MON VDC50.GR3_MON -#define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE -#define VDC50GAM_SW VDC50.GAM_SW -#define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1 -#define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2 -#define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3 -#define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4 -#define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5 -#define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6 -#define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7 -#define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8 -#define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9 -#define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10 -#define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11 -#define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12 -#define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13 -#define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14 -#define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15 -#define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16 -#define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1 -#define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2 -#define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3 -#define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4 -#define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5 -#define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6 -#define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7 -#define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8 -#define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE -#define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1 -#define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2 -#define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3 -#define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4 -#define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5 -#define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6 -#define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7 -#define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8 -#define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9 -#define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10 -#define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11 -#define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12 -#define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13 -#define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14 -#define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15 -#define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16 -#define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1 -#define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2 -#define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3 -#define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4 -#define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5 -#define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6 -#define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7 -#define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8 -#define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE -#define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1 -#define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2 -#define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3 -#define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4 -#define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5 -#define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6 -#define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7 -#define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8 -#define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9 -#define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10 -#define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11 -#define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12 -#define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13 -#define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14 -#define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15 -#define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16 -#define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1 -#define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2 -#define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3 -#define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4 -#define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5 -#define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6 -#define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7 -#define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8 -#define VDC50TCON_UPDATE VDC50.TCON_UPDATE -#define VDC50TCON_TIM VDC50.TCON_TIM -#define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1 -#define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2 -#define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1 -#define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2 -#define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1 -#define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2 -#define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1 -#define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2 -#define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1 -#define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2 -#define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1 -#define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2 -#define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1 -#define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2 -#define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE -#define VDC50OUT_UPDATE VDC50.OUT_UPDATE -#define VDC50OUT_SET VDC50.OUT_SET -#define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1 -#define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2 -#define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST -#define VDC50OUT_PDTHA VDC50.OUT_PDTHA -#define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE -#define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1 -#define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2 -#define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3 -#define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4 -#define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5 -#define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6 -#define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK -#define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT -#define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE -#define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1 -#define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2 -#define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3 -#define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4 -#define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5 -#define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6 -#define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7 -#define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9 -#define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0 -#define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT -#define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1 -#define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2 -#define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3 -#define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4 -#define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5 -#define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6 -#define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7 -#define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1 -#define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2 -#define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3 -#define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4 -#define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5 -#define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6 -#define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7 -#define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8 -#define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1 -#define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE -#define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1 -#define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2 -#define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3 -#define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4 -#define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5 -#define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6 -#define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7 -#define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8 -#define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9 -#define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10 -#define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11 -#define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1 -#define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0 -#define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1 -#define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2 -#define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3 -#define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD -#define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT -#define VDC50GR1_UPDATE VDC50.GR1_UPDATE -#define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD -#define VDC50GR1_FLM1 VDC50.GR1_FLM1 -#define VDC50GR1_FLM2 VDC50.GR1_FLM2 -#define VDC50GR1_FLM3 VDC50.GR1_FLM3 -#define VDC50GR1_FLM4 VDC50.GR1_FLM4 -#define VDC50GR1_FLM5 VDC50.GR1_FLM5 -#define VDC50GR1_FLM6 VDC50.GR1_FLM6 -#define VDC50GR1_AB1 VDC50.GR1_AB1 -#define VDC50GR1_AB2 VDC50.GR1_AB2 -#define VDC50GR1_AB3 VDC50.GR1_AB3 -#define VDC50GR1_AB4 VDC50.GR1_AB4 -#define VDC50GR1_AB5 VDC50.GR1_AB5 -#define VDC50GR1_AB6 VDC50.GR1_AB6 -#define VDC50GR1_AB7 VDC50.GR1_AB7 -#define VDC50GR1_AB8 VDC50.GR1_AB8 -#define VDC50GR1_AB9 VDC50.GR1_AB9 -#define VDC50GR1_AB10 VDC50.GR1_AB10 -#define VDC50GR1_AB11 VDC50.GR1_AB11 -#define VDC50GR1_BASE VDC50.GR1_BASE -#define VDC50GR1_CLUT VDC50.GR1_CLUT -#define VDC50GR1_MON VDC50.GR1_MON -#define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE -#define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET -#define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1 -#define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2 -#define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3 -#define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1 -#define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2 -#define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3 -#define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4 -#define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5 -#define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6 -#define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1 -#define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2 -#define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE -#define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0 -#define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1 -#define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0 -#define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1 -#define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0 -#define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1 -#define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE -#define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1 -#define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2 -#define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3 -#define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4 -#define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5 -#define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6 -#define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7 -#define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE -#define VDC50GR_VIN_MON VDC50.GR_VIN_MON -#define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE -#define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1 -#define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2 -#define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3 -#define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4 -#define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5 -#define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6 -#define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7 -#define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1 -#define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2 -#define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3 -#define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7 -#define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1 -#define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2 -#define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3 -#define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8 -#define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1 -#define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE -#define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1 -#define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2 -#define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3 -#define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4 -#define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5 -#define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6 -#define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7 -#define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE -#define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD -#define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1 -#define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2 -#define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3 -#define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4 -#define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5 -#define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6 -#define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1 -#define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2 -#define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3 -#define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7 -#define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8 -#define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9 -#define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10 -#define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11 -#define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE -#define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT -#define VDC50GR_OIR_MON VDC50.GR_OIR_MON -#define VDC51INP_UPDATE VDC51.INP_UPDATE -#define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT -#define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT -#define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ -#define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ -#define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE -#define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0 -#define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1 -#define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE -#define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0 -#define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1 -#define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0 -#define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1 -#define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0 -#define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1 -#define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG -#define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE -#define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1 -#define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2 -#define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3 -#define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4 -#define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5 -#define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6 -#define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7 -#define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9 -#define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0 -#define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT -#define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1 -#define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2 -#define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3 -#define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4 -#define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5 -#define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6 -#define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7 -#define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1 -#define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2 -#define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3 -#define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4 -#define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5 -#define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6 -#define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7 -#define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8 -#define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1 -#define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE -#define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1 -#define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2 -#define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3 -#define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4 -#define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5 -#define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6 -#define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7 -#define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8 -#define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9 -#define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10 -#define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11 -#define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1 -#define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0 -#define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1 -#define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2 -#define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3 -#define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD -#define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT -#define VDC51GR0_UPDATE VDC51.GR0_UPDATE -#define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD -#define VDC51GR0_FLM1 VDC51.GR0_FLM1 -#define VDC51GR0_FLM2 VDC51.GR0_FLM2 -#define VDC51GR0_FLM3 VDC51.GR0_FLM3 -#define VDC51GR0_FLM4 VDC51.GR0_FLM4 -#define VDC51GR0_FLM5 VDC51.GR0_FLM5 -#define VDC51GR0_FLM6 VDC51.GR0_FLM6 -#define VDC51GR0_AB1 VDC51.GR0_AB1 -#define VDC51GR0_AB2 VDC51.GR0_AB2 -#define VDC51GR0_AB3 VDC51.GR0_AB3 -#define VDC51GR0_AB7 VDC51.GR0_AB7 -#define VDC51GR0_AB8 VDC51.GR0_AB8 -#define VDC51GR0_AB9 VDC51.GR0_AB9 -#define VDC51GR0_AB10 VDC51.GR0_AB10 -#define VDC51GR0_AB11 VDC51.GR0_AB11 -#define VDC51GR0_BASE VDC51.GR0_BASE -#define VDC51GR0_CLUT VDC51.GR0_CLUT -#define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE -#define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET -#define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1 -#define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2 -#define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3 -#define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1 -#define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2 -#define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3 -#define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4 -#define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5 -#define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6 -#define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1 -#define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2 -#define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE -#define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0 -#define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1 -#define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0 -#define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1 -#define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0 -#define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1 -#define VDC51GR2_UPDATE VDC51.GR2_UPDATE -#define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD -#define VDC51GR2_FLM1 VDC51.GR2_FLM1 -#define VDC51GR2_FLM2 VDC51.GR2_FLM2 -#define VDC51GR2_FLM3 VDC51.GR2_FLM3 -#define VDC51GR2_FLM4 VDC51.GR2_FLM4 -#define VDC51GR2_FLM5 VDC51.GR2_FLM5 -#define VDC51GR2_FLM6 VDC51.GR2_FLM6 -#define VDC51GR2_AB1 VDC51.GR2_AB1 -#define VDC51GR2_AB2 VDC51.GR2_AB2 -#define VDC51GR2_AB3 VDC51.GR2_AB3 -#define VDC51GR2_AB4 VDC51.GR2_AB4 -#define VDC51GR2_AB5 VDC51.GR2_AB5 -#define VDC51GR2_AB6 VDC51.GR2_AB6 -#define VDC51GR2_AB7 VDC51.GR2_AB7 -#define VDC51GR2_AB8 VDC51.GR2_AB8 -#define VDC51GR2_AB9 VDC51.GR2_AB9 -#define VDC51GR2_AB10 VDC51.GR2_AB10 -#define VDC51GR2_AB11 VDC51.GR2_AB11 -#define VDC51GR2_BASE VDC51.GR2_BASE -#define VDC51GR2_CLUT VDC51.GR2_CLUT -#define VDC51GR2_MON VDC51.GR2_MON -#define VDC51GR3_UPDATE VDC51.GR3_UPDATE -#define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD -#define VDC51GR3_FLM1 VDC51.GR3_FLM1 -#define VDC51GR3_FLM2 VDC51.GR3_FLM2 -#define VDC51GR3_FLM3 VDC51.GR3_FLM3 -#define VDC51GR3_FLM4 VDC51.GR3_FLM4 -#define VDC51GR3_FLM5 VDC51.GR3_FLM5 -#define VDC51GR3_FLM6 VDC51.GR3_FLM6 -#define VDC51GR3_AB1 VDC51.GR3_AB1 -#define VDC51GR3_AB2 VDC51.GR3_AB2 -#define VDC51GR3_AB3 VDC51.GR3_AB3 -#define VDC51GR3_AB4 VDC51.GR3_AB4 -#define VDC51GR3_AB5 VDC51.GR3_AB5 -#define VDC51GR3_AB6 VDC51.GR3_AB6 -#define VDC51GR3_AB7 VDC51.GR3_AB7 -#define VDC51GR3_AB8 VDC51.GR3_AB8 -#define VDC51GR3_AB9 VDC51.GR3_AB9 -#define VDC51GR3_AB10 VDC51.GR3_AB10 -#define VDC51GR3_AB11 VDC51.GR3_AB11 -#define VDC51GR3_BASE VDC51.GR3_BASE -#define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT -#define VDC51GR3_MON VDC51.GR3_MON -#define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE -#define VDC51GAM_SW VDC51.GAM_SW -#define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1 -#define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2 -#define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3 -#define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4 -#define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5 -#define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6 -#define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7 -#define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8 -#define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9 -#define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10 -#define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11 -#define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12 -#define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13 -#define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14 -#define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15 -#define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16 -#define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1 -#define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2 -#define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3 -#define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4 -#define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5 -#define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6 -#define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7 -#define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8 -#define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE -#define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1 -#define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2 -#define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3 -#define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4 -#define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5 -#define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6 -#define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7 -#define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8 -#define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9 -#define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10 -#define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11 -#define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12 -#define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13 -#define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14 -#define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15 -#define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16 -#define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1 -#define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2 -#define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3 -#define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4 -#define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5 -#define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6 -#define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7 -#define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8 -#define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE -#define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1 -#define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2 -#define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3 -#define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4 -#define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5 -#define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6 -#define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7 -#define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8 -#define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9 -#define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10 -#define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11 -#define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12 -#define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13 -#define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14 -#define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15 -#define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16 -#define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1 -#define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2 -#define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3 -#define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4 -#define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5 -#define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6 -#define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7 -#define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8 -#define VDC51TCON_UPDATE VDC51.TCON_UPDATE -#define VDC51TCON_TIM VDC51.TCON_TIM -#define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1 -#define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2 -#define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1 -#define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2 -#define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1 -#define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2 -#define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1 -#define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2 -#define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1 -#define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2 -#define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1 -#define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2 -#define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1 -#define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2 -#define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE -#define VDC51OUT_UPDATE VDC51.OUT_UPDATE -#define VDC51OUT_SET VDC51.OUT_SET -#define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1 -#define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2 -#define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST -#define VDC51OUT_PDTHA VDC51.OUT_PDTHA -#define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE -#define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1 -#define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2 -#define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3 -#define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4 -#define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5 -#define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6 -#define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK -#define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT -#define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE -#define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1 -#define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2 -#define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3 -#define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4 -#define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5 -#define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6 -#define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7 -#define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9 -#define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0 -#define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT -#define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1 -#define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2 -#define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3 -#define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4 -#define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5 -#define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6 -#define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7 -#define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1 -#define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2 -#define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3 -#define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4 -#define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5 -#define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6 -#define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7 -#define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8 -#define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1 -#define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE -#define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1 -#define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2 -#define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3 -#define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4 -#define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5 -#define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6 -#define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7 -#define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8 -#define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9 -#define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10 -#define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11 -#define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1 -#define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0 -#define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1 -#define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2 -#define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3 -#define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD -#define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT -#define VDC51GR1_UPDATE VDC51.GR1_UPDATE -#define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD -#define VDC51GR1_FLM1 VDC51.GR1_FLM1 -#define VDC51GR1_FLM2 VDC51.GR1_FLM2 -#define VDC51GR1_FLM3 VDC51.GR1_FLM3 -#define VDC51GR1_FLM4 VDC51.GR1_FLM4 -#define VDC51GR1_FLM5 VDC51.GR1_FLM5 -#define VDC51GR1_FLM6 VDC51.GR1_FLM6 -#define VDC51GR1_AB1 VDC51.GR1_AB1 -#define VDC51GR1_AB2 VDC51.GR1_AB2 -#define VDC51GR1_AB3 VDC51.GR1_AB3 -#define VDC51GR1_AB4 VDC51.GR1_AB4 -#define VDC51GR1_AB5 VDC51.GR1_AB5 -#define VDC51GR1_AB6 VDC51.GR1_AB6 -#define VDC51GR1_AB7 VDC51.GR1_AB7 -#define VDC51GR1_AB8 VDC51.GR1_AB8 -#define VDC51GR1_AB9 VDC51.GR1_AB9 -#define VDC51GR1_AB10 VDC51.GR1_AB10 -#define VDC51GR1_AB11 VDC51.GR1_AB11 -#define VDC51GR1_BASE VDC51.GR1_BASE -#define VDC51GR1_CLUT VDC51.GR1_CLUT -#define VDC51GR1_MON VDC51.GR1_MON -#define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE -#define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET -#define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1 -#define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2 -#define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3 -#define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1 -#define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2 -#define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3 -#define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4 -#define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5 -#define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6 -#define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1 -#define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2 -#define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE -#define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0 -#define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1 -#define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0 -#define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1 -#define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0 -#define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1 -#define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE -#define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1 -#define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2 -#define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3 -#define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4 -#define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5 -#define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6 -#define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7 -#define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE -#define VDC51GR_VIN_MON VDC51.GR_VIN_MON -#define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE -#define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1 -#define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2 -#define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3 -#define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4 -#define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5 -#define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6 -#define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7 -#define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1 -#define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2 -#define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3 -#define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7 -#define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1 -#define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2 -#define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3 -#define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8 -#define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1 -#define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE -#define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1 -#define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2 -#define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3 -#define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4 -#define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5 -#define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6 -#define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7 -#define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE -#define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD -#define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1 -#define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2 -#define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3 -#define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4 -#define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5 -#define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6 -#define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1 -#define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2 -#define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3 -#define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7 -#define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8 -#define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9 -#define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10 -#define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11 -#define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE -#define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT -#define VDC51GR_OIR_MON VDC51.GR_OIR_MON /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h index 0ee2a53210..82b448e56c 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h @@ -18,29 +18,40 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : wdt_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef WDT_IODEFINE_H #define WDT_IODEFINE_H - -struct st_wdt -{ /* WDT */ - volatile uint16_t WTCSR; /* WTCSR */ - volatile uint16_t WTCNT; /* WTCNT */ - volatile uint16_t WRCSR; /* WRCSR */ -}; - +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ #define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */ -#define WDTWTCSR WDT.WTCSR -#define WDTWTCNT WDT.WTCNT -#define WDTWRCSR WDT.WRCSR +#define WDTWTCSR (WDT.WTCSR) +#define WDTWTCNT (WDT.WTCNT) +#define WDTWRCSR (WDT.WRCSR) + + +typedef struct st_wdt +{ + /* WDT */ + volatile uint16_t WTCSR; /* WTCSR */ + volatile uint16_t WTCNT; /* WTCNT */ + volatile uint16_t WRCSR; /* WRCSR */ +} r_io_wdt_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c deleted file mode 100644 index ed05e4c50d..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c +++ /dev/null @@ -1,243 +0,0 @@ -/**************************************************************************//** - * @file mmu_Renesas_RZ_A1.c - * @brief MMU Startup File for - * mmu_Renesas_RZ_A1 Device Series - * @version V1.01 - * @date 2 Aug 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ -#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -//Note: You should use the Shareable attribute carefully. -//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings. -//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - - -//Following MMU configuration is expected -//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -//Domain 0 is always the Client domain -//Descriptors place all memory in domain 0 -//There are no restrictions by privilege level (PL0 can access all memory) - -#include -#include "VKRZA1H.h" - -//Import symbols from linker -extern uint32_t Image$$VECTORS$$Base; -extern uint32_t Image$$RO_DATA$$Base; -extern uint32_t Image$$RW_DATA$$Base; -extern uint32_t Image$$ZI_DATA$$Base; -#if !defined ( __ICCARM__ ) -extern uint32_t Image$$TTB$$ZI$$Base; -#endif - -#if defined( __CC_ARM ) -#elif defined( __ICCARM__ ) -#else -extern uint32_t Image$$RW_DATA_NC$$Base; -extern uint32_t Image$$ZI_DATA_NC$$Base; -#endif - -extern uint32_t Image$$VECTORS$$Limit; -extern uint32_t Image$$RO_DATA$$Limit; -extern uint32_t Image$$RW_DATA$$Limit; -extern uint32_t Image$$ZI_DATA$$Limit; -#if defined( __CC_ARM ) -#else -extern uint32_t Image$$RW_DATA_NC$$Limit; -extern uint32_t Image$$ZI_DATA_NC$$Limit; -#endif - -#if defined( __ICCARM__ ) -#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1) -#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1) -#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1) -#define ZI_DATA_SIZE (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1) -#else -#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) -#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) -#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) -#define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1) -#endif - -#if defined( __CC_ARM ) -#else -#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) -#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) -#endif - -static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; //generic -static uint32_t Page_L1_64k = 0x0; //generic -static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 - -#if defined ( __ICCARM__ ) -__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram"; -uint32_t Image$$VECTORS$$Base; -uint32_t Image$$RO_DATA$$Base; -uint32_t Image$$RW_DATA$$Base; -uint32_t Image$$ZI_DATA$$Base; - -uint32_t Image$$VECTORS$$Limit; -uint32_t Image$$RO_DATA$$Limit; -uint32_t Image$$RW_DATA$$Limit; -uint32_t Image$$ZI_DATA$$Limit; -#endif - -void create_translation_table(void) -{ - mmu_region_attributes_Type region; -#if defined ( __ICCARM__ ) -#pragma section=".intvec" -#pragma section=".rodata" -#pragma section=".rwdata" -#pragma section=".bss" - - Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec"); - Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec")); - Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata"); - Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata")); - Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); - Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata")); - Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss"); - Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss")); -#endif - /* - * Generate descriptors. Refer to VKRZA1H.h to get information about attributes - * - */ - //Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - //Create descriptors for peripherals - section_device_ro(Sect_Device_RO, region); - section_device_rw(Sect_Device_RW, region); - section_normal_nc(Sect_Normal_NC, region); - //Create descriptors for 64k pages - page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); - //Create descriptors for 4k pages - page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - /* - * Define MMU flat-map regions and attributes - * - */ - - //Create 4GB of faulting entries - __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); - - // R7S72100 memory map. - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); - -#if defined( __ICCARM__ ) - //Define Image - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW); -#else - //Define Image - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW); -#endif - -#if defined( __CC_ARM ) - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC); -#elif defined ( __ICCARM__ ) - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC); - -#else - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC); -#endif - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x0 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x1 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x1 (Inner WB WA) */ - __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); -} - - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c new file mode 100644 index 0000000000..f97edff22f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c @@ -0,0 +1,281 @@ +/**************************************************************************//** + * @file mmu_VK_RZ_A1H.c + * @brief MMU Configuration for RZ_A1H Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf + + Memory Type +0xffffffff |--------------------------| ------------ + | Peripherals | Device +0xfcf00000 |--------------------------| ------------ + | Page Fault | Fault +0xe8300000 |--------------------------| ------------ + | Peripherals | Device +0xe8000000 |--------------------------| ------------ + | Page Fault | Fault +0x60A00000 |--------------------------| ------------ + | On Chip RAM (10M) Mirror | Fault +0x60000000 |--------------------------| ------------ + | SPI multi I/O 64MB | Fault +0x5c000000 |--------------------------| ------------ + | SPI multi I/O 64MB | Fault +0x58000000 |--------------------------| ------------ + | CS5 Mirror | Fault +0x54000000 |--------------------------| ------------ + | CS4 Mirror | Fault +0x50000000 |--------------------------| ------------ + | CS3 Mirror | Fault +0x4c000000 |--------------------------| ------------ + | CS2 Mirror | Fault +0x48000000 |--------------------------| ------------ + | CS1 Mirror | Fault +0x44000000 |--------------------------| ------------ + | CS0 Mirror | Fault +0x40000000 |--------------------------| ------------ + | BSC | RW +0x3ff00000 |--------------------------| ------------ + | SPI_MIO_BASE | RW +0x3fe00000 |--------------------------| ------------ + | Page Fault | Fault +0x20A00000 |--------------------------| ------------ + | On Chip RAM (10M) | RW +0x20000000 |--------------------------| ------------ + | SPI multi I/O 64MB | RO +0x1c000000 |--------------------------| ------------ + | SPI multi I/O 64MB | RO +0x18000000 |--------------------------| ------------ + | CS5 User Area 64MB | RW +0x14000000 |--------------------------| ------------ + | CS4 User Area 64MB | RW +0x10000000 |--------------------------| ------------ + | CS3 SDRAM 64MB | RW +0x0c000000 |--------------------------| ------------ + | CS2 SDRAM 64MB | RW +0x08000000 |--------------------------| ------------ + | CS1 NOR Flash 64MB | RO +0x04000000 |--------------------------| ------------ + | CS0 NOR Flash 64MB | RO +0x00000000 |--------------------------| ------------ +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 +//There are no restrictions by privilege level (PL0 can access all memory) + + +#include "VK_RZ_A1H.h" + +//Import symbols from linker +extern uint32_t Image$$VECTORS$$Base; +extern uint32_t Image$$RO_DATA$$Base; +extern uint32_t Image$$RW_DATA$$Base; +extern uint32_t Image$$RW_IRAM1$$Base; +#if !defined ( __ICCARM__ ) +extern uint32_t Image$$TTB$$ZI$$Base; +#endif + +#if defined( __CC_ARM ) +#elif defined( __ICCARM__ ) +#else +extern uint32_t Image$$RW_DATA_NC$$Base; +extern uint32_t Image$$ZI_DATA_NC$$Base; +#endif + +extern uint32_t Image$$VECTORS$$Limit; +extern uint32_t Image$$RO_DATA$$Limit; +extern uint32_t Image$$RW_DATA$$Limit; +extern uint32_t Image$$RW_IRAM1$$Limit; +#if defined( __CC_ARM ) +#else +extern uint32_t Image$$RW_DATA_NC$$Limit; +extern uint32_t Image$$ZI_DATA_NC$$Limit; +#endif + +#if defined( __ICCARM__ ) +#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1) +#define RW_IRAM1_SIZE (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1) +#else +#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) +#define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1) +#endif + +#if defined( __CC_ARM ) +#else +#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) +#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) +#endif + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +#if defined ( __ICCARM__ ) +__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram"; +uint32_t Image$$VECTORS$$Base; +uint32_t Image$$RO_DATA$$Base; +uint32_t Image$$RW_DATA$$Base; +uint32_t Image$$RW_IRAM1$$Base; + +uint32_t Image$$VECTORS$$Limit; +uint32_t Image$$RO_DATA$$Limit; +uint32_t Image$$RW_DATA$$Limit; +uint32_t Image$$RW_IRAM1$$Limit; +#endif + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; +#if defined ( __ICCARM__ ) +#pragma section=".intvec" +#pragma section=".rodata" +#pragma section=".rwdata" +#pragma section=".bss" + + Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec"); + Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec")); + Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata"); + Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata")); + Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); + Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata")); + Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss"); + Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss")); +#endif + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + section_normal_nc(Sect_Normal_NC, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Create 4GB of faulting entries + MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); + + // R7S72100 memory map. + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); + +#if defined( __ICCARM__ ) + //Define Image + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); +#else + //Define Image + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); +#endif + +#if defined( __CC_ARM ) + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); +#elif defined ( __ICCARM__ ) + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); + +#else + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC); +#endif + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x0 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x1 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x1 (Inner WB WA) */ + __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c index 13f0eb250f..d04267618c 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c @@ -33,7 +33,6 @@ Includes , "Project Includes" #include "VKRZA1H.h" #include "wdt_iodefine.h" #include "nvic_wrapper.h" -#include "gic.h" /****************************************************************************** Typedef definitions @@ -71,7 +70,7 @@ void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) uint32_t NVIC_GetPriorityGrouping(void) { - return GIC_GetBinaryPoint(0); + return GIC_GetBinaryPoint(); } @@ -214,14 +213,16 @@ uint32_t ITM_SendChar (uint32_t ch) } -int32_t ITM_ReceiveChar (void) { +int32_t ITM_ReceiveChar (void) +{ /* Not support this function */ /* Use mbed Serial */ return (-1); /* no character available */ } -int32_t ITM_CheckChar (void) { +int32_t ITM_CheckChar (void) +{ /* Not support this function */ /* Use mbed Serial */ return (0); /* no character available */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c new file mode 100644 index 0000000000..e5b259184a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c @@ -0,0 +1,201 @@ +/**************************************************************************//** + * @file os_tick_ostm.c + * @brief CMSIS OS Tick implementation for OS Timer + * @version V1.0.1 + * @date 19. September 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef MBED_CONF_RTOS_PRESENT + +#include "os_tick.h" +#include "irq_ctrl.h" + +#include + +#include + + +// Define OS TImer interrupt priority +#ifndef OSTM_IRQ_PRIORITY +#define OSTM_IRQ_PRIORITY 0xFFU +#endif + +// Define OS Timer channel and interrupt number +#define OSTM (OSTM0) +#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) + + +static uint32_t OSTM_Clock; // Timer tick frequency +static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag + + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) +{ + uint32_t clock; + uint32_t prio; + uint32_t bits; + + if (freq == 0U) { + return (-1); + } + + OSTM_PendIRQ = 0U; + + // Get CPG.FRQCR[IFC] bits + clock = (CPG.FRQCR >> 8) & 0x03; + + // Determine Divider 2 output clock by using SystemCoreClock + if (clock == 0x03U) { + clock = (SystemCoreClock * 3U); + } + else if (clock == 0x01U) { + clock = (SystemCoreClock * 3U)/2U; + } + else { + clock = SystemCoreClock; + } + + // Determine tick frequency + clock = clock / freq; + + // Save frequency for later + OSTM_Clock = clock; + + // Enable OSTM clock + CPG.STBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); + + // Stop the OSTM counter + OSTM.OSTMnTT = 0x01U; + + // Set interval timer mode and disable interrupts when counting starts + OSTM.OSTMnCTL = 0x00U; + + // Set compare value + OSTM.OSTMnCMP = clock - 1U; + + // Disable corresponding IRQ + IRQ_Disable (OSTM_IRQn); + IRQ_ClearPending(OSTM_IRQn); + + // Determine number of implemented priority bits + IRQ_SetPriority (OSTM_IRQn, 0xFFU); + + prio = IRQ_GetPriority (OSTM_IRQn); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (OSTM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set OSTM interrupt priority + IRQ_SetPriority(OSTM_IRQn, prio-1U); + + // Set edge-triggered, non-secure, single CPU targeted IRQ + IRQ_SetMode (OSTM_IRQn, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(OSTM_IRQn, (IRQHandler_t)handler); + + // Enable corresponding IRQ + IRQ_Enable (OSTM_IRQn); + + return (0); +} + +/// Enable OS Tick. +int32_t OS_Tick_Enable (void) +{ + + if (OSTM_PendIRQ != 0U) { + OSTM_PendIRQ = 0U; + IRQ_SetPending (OSTM_IRQn); + } + + // Start the OSTM counter + OSTM.OSTMnTS = 0x01U; + + return (0); +} + +/// Disable OS Tick. +int32_t OS_Tick_Disable (void) +{ + + // Stop the OSTM counter + OSTM.OSTMnTT = 0x01U; + + if (IRQ_GetPending(OSTM_IRQn) != 0) { + IRQ_ClearPending (OSTM_IRQn); + OSTM_PendIRQ = 1U; + } + + return (0); +} + +// Acknowledge OS Tick IRQ. +int32_t OS_Tick_AcknowledgeIRQ (void) +{ + return (IRQ_ClearPending (OSTM_IRQn)); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) +{ + return (OSTM_IRQn); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) +{ + return (OSTM_Clock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) +{ + return (OSTM.OSTMnCMP + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) +{ + uint32_t cmp = OSTM.OSTMnCMP; + return (cmp - OSTM.OSTMnCNT); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) +{ + return (IRQ_GetPending(OSTM_IRQn)); +} + +#endif + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c deleted file mode 100644 index eb6d80a8e2..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************//** - * @file pl310.c - * @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions - * @version - * @date 3 December 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ -#include "VKRZA1H.h" - -//Cache Sync operation -void PL310_Sync(void) -{ - PL310->CACHE_SYNC = 0x0; -} - -//return Cache controller cache ID -int PL310_GetID (void) -{ - return PL310->CACHE_ID; -} - -//return Cache controller cache Type -int PL310_GetType (void) -{ - return PL310->CACHE_TYPE; -} - -//Invalidate all cache by way -void PL310_InvAllByWay (void) -{ - unsigned int assoc; - - if (PL310->AUX_CNT & (1<<16)) - assoc = 16; - else - assoc = 8; - - PL310->INV_WAY = (1 << assoc) - 1; - while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate - - PL310_Sync(); -} - -//Clean and Invalidate all cache by way -void PL310_CleanInvAllByWay (void) -{ - unsigned int assoc; - - if (PL310->AUX_CNT & (1<<16)) - assoc = 16; - else - assoc = 8; - - PL310->CLEAN_INV_WAY = (1 << assoc) - 1; - while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate - - PL310_Sync(); -} - -//Enable Cache -void PL310_Enable(void) -{ - PL310->CONTROL = 0; - PL310->INTERRUPT_CLEAR = 0x000001FFuL; - PL310->DEBUG_CONTROL = 0; - PL310->DATA_LOCK_0_WAY = 0; - PL310->CACHE_SYNC = 0; - - PL310->CONTROL = 0x01; - PL310_Sync(); -} -//Disable Cache -void PL310_Disable(void) -{ - PL310->CONTROL = 0x00; - PL310_Sync(); -} - -//Invalidate cache by physical address -void PL310_InvPa (void *pa) -{ - PL310->INV_LINE_PA = (unsigned int)pa; - PL310_Sync(); -} - -//Clean cache by physical address -void PL310_CleanPa (void *pa) -{ - PL310->CLEAN_LINE_PA = (unsigned int)pa; - PL310_Sync(); -} - -//Clean and invalidate cache by physical address -void PL310_CleanInvPa (void *pa) -{ - PL310->CLEAN_INV_LINE_PA = (unsigned int)pa; - PL310_Sync(); -} - - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h deleted file mode 100644 index 0960a4d1f3..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************//** - * @file pl310.h - * @brief Implementation of pl310 functions - * @version - * @date 11 June 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef __PL310 -#define __PL310 - -typedef struct -{ - __I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */ - __I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */ - uint32_t RESERVED0[0x3e]; - __IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */ - __IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */ - uint32_t RESERVED1[0x3e]; - __IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */ - __IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */ - __IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */ - uint32_t RESERVED2[0x2]; - __IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */ - __I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */ - __I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */ - __O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */ - uint32_t RESERVED3[0x143]; - __IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */ - uint32_t RESERVED4[0xf]; - __IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */ - uint32_t RESERVED6[2]; - __IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */ - uint32_t RESERVED5[0xc]; - __IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */ - uint32_t RESERVED7[1]; - __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */ - __IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */ - uint32_t RESERVED8[0xc]; - __IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */ - uint32_t RESERVED9[1]; - __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */ - __IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */ - uint32_t RESERVED10[0x40]; - __IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */ - __IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */ - __IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */ - __IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */ - __IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */ - __IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */ - __IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */ - __IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */ - __IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */ - __IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */ - __IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */ - __IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */ - __IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */ - __IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */ - __IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */ - __IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */ - uint32_t RESERVED11[0x4]; - __IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */ - __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */ - uint32_t RESERVED12[0xaa]; - __IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */ - __IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */ - uint32_t RESERVED13[0xce]; - __IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */ - -} PL310_TypeDef; - -#define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */ - -extern int PL310_GetID (void); -extern int PL310_GetType (void); -extern void PL310_InvAllByWay (void); -extern void PL310_CleanInvAllByWay(void); -extern void PL310_Enable(void); -extern void PL310_Disable(void); -extern void PL310_InvPa (void *); -extern void PL310_CleanPa (void *); -extern void PL310_CleanInvPa (void *); - -#endif - - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c deleted file mode 100644 index 8017e372a3..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c +++ /dev/null @@ -1,521 +0,0 @@ -/**************************************************************************//** - * @file system_VKRZA1H.c - * @brief CMSIS Device System Source File for - * ARM Cortex-A9 Device Series - * @version V1.00 - * @date 09 January 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#include -#include "VKRZA1H.h" -#include "RZ_A1_Init.h" - - -#if defined(__ARMCC_VERSION) -extern void $Super$$main(void); -__asm void FPUEnable(void); -#else -void FPUEnable(void); - -#endif - -#define FRQCR_IFC_MSK (0x0030) -#define FRQCR_IFC_SHFT (8) -#define FRQCR_IFC_1P1 (0) /* x1/1 */ -#define FRQCR_IFC_2P3 (1) /* x2/3 */ -#define FRQCR_IFC_1P3 (3) /* x1/3 */ - -uint32_t IRQNestLevel; -unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 -uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the cache. - * - * @param none - * @return none - * - * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode. - */ -#if defined(__ARMCC_VERSION) -#pragma push -#pragma arm - -void InitMemorySubsystem(void) { - - /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before - * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. - * You are not required to invalidate the main TLB, even though it is recommended for safety - * reasons. This ensures compatibility with future revisions of the processor. */ - - unsigned int l2_id; - - /* Invalidate undefined data */ - __ca9u_inv_tlb_all(); - __v7_inv_icache_all(); - __v7_inv_dcache_all(); - __v7_inv_btac(); - - /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and - * invalidate in order to flush the valid data to the next level cache. - */ - __enable_mmu(); - - /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ - __enable_caches(); - __enable_btac(); - - /* If present, you may also need to Invalidate and Enable L2 cache here */ - l2_id = PL310_GetID(); - if (l2_id) - { - PL310_InvAllByWay(); - PL310_Enable(); - } -} -#pragma pop - -#elif defined(__GNUC__) - -void InitMemorySubsystem(void) { - - /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before - * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. - * You are not required to invalidate the main TLB, even though it is recommended for safety - * reasons. This ensures compatibility with future revisions of the processor. */ - - unsigned int l2_id; - - /* Invalidate undefined data */ - __ca9u_inv_tlb_all(); - __v7_inv_icache_all(); - __v7_inv_dcache_all(); - __v7_inv_btac(); - - /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and - * invalidate in order to flush the valid data to the next level cache. - */ - __enable_mmu(); - - /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ - __enable_caches(); - __enable_btac(); - - /* If present, you may also need to Invalidate and Enable L2 cache here */ - l2_id = PL310_GetID(); - if (l2_id) - { - PL310_InvAllByWay(); - PL310_Enable(); - } -} -#elif defined ( __ICCARM__ ) - -void InitMemorySubsystem(void) { - - /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before - * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. - * You are not required to invalidate the main TLB, even though it is recommended for safety - * reasons. This ensures compatibility with future revisions of the processor. */ - - unsigned int l2_id; - - /* Invalidate undefined data */ - __ca9u_inv_tlb_all(); - __v7_inv_icache_all(); - __v7_inv_dcache_all(); - __v7_inv_btac(); - - /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and - * invalidate in order to flush the valid data to the next level cache. - */ - __enable_mmu(); - - /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ - __enable_caches(); - __enable_btac(); - - /* If present, you may also need to Invalidate and Enable L2 cache here */ - l2_id = PL310_GetID(); - if (l2_id) - { - PL310_InvAllByWay(); - PL310_Enable(); - } -} -#else - -#endif - - -IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; - -uint32_t IRQCount = sizeof IRQTable / 4; - -uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) -{ - if (irq < IRQCount) { - IRQTable[irq] = handler; - return 0; - } - else { - return 1; - } -} - -uint32_t InterruptHandlerUnregister (IRQn_Type irq) -{ - if (irq < IRQCount) { - IRQTable[irq] = 0; - return 0; - } - else { - return 1; - } -} - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock. - */ -void SystemCoreClockUpdate (void) -{ - uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT; - - switch (frqcr_ifc) { - case FRQCR_IFC_1P1: - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; - break; - case FRQCR_IFC_2P3: - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3; - break; - case FRQCR_IFC_1P3: - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3; - break; - default: - /* do nothing */ - break; - } -} - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ - IRQNestLevel = 0; -/* do not use global variables because this function is called before - reaching pre-main. RW section maybe overwritten afterwards. */ - RZ_A1_InitClock(); - RZ_A1_InitBus(); - - //Configure GIC ICDICFR GIC_SetICDICFR() - GIC_Enable(); - __enable_irq(); - -} - - -//Fault Status Register (IFSR/DFSR) definitions -#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup -#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external -#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external -#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external -#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external -#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external -#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal -#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal -#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal -#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal -#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal -#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal -#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal -#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal -#define FSR_DEBUG_EVENT 0x02 //internal -#define FSR_SYNC_EXT_ABORT 0x08 //sync/external -#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external -#define FSR_LOCKDOWN 0x14 //internal -#define FSR_COPROCESSOR_ABORT 0x1a //internal -#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external -#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external -#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external - -void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { - uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status - - switch(FS) { - //Synchronous parity errors - retry - case FSR_SYNC_PARITY_ERROR: - case FSR_SYNC_PARITY_TTB_WALK_FIRST: - case FSR_SYNC_PARITY_TTB_WALK_SECOND: - return; - - //Your code here. Value in DFAR is invalid for some fault statuses. - case FSR_ALIGNMENT_FAULT: - case FSR_INSTRUCTION_CACHE_MAINTENANCE: - case FSR_SYNC_EXT_TTB_WALK_FIRST: - case FSR_SYNC_EXT_TTB_WALK_SECOND: - case FSR_TRANSLATION_FAULT_FIRST: - case FSR_TRANSLATION_FAULT_SECOND: - case FSR_ACCESS_FLAG_FAULT_FIRST: - case FSR_ACCESS_FLAG_FAULT_SECOND: - case FSR_DOMAIN_FAULT_FIRST: - case FSR_DOMAIN_FAULT_SECOND: - case FSR_PERMISION_FAULT_FIRST: - case FSR_PERMISION_FAULT_SECOND: - case FSR_DEBUG_EVENT: - case FSR_SYNC_EXT_ABORT: - case FSR_TLB_CONFLICT_ABORT: - case FSR_LOCKDOWN: - case FSR_COPROCESSOR_ABORT: - case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid - case FSR_ASYNC_PARITY_ERROR: //DFAR invalid - default: - while(1); - } -} - -void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { - uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status - - switch(FS) { - //Synchronous parity errors - retry - case FSR_SYNC_PARITY_ERROR: - case FSR_SYNC_PARITY_TTB_WALK_FIRST: - case FSR_SYNC_PARITY_TTB_WALK_SECOND: - return; - - //Your code here. Value in IFAR is invalid for some fault statuses. - case FSR_SYNC_EXT_TTB_WALK_FIRST: - case FSR_SYNC_EXT_TTB_WALK_SECOND: - case FSR_TRANSLATION_FAULT_FIRST: - case FSR_TRANSLATION_FAULT_SECOND: - case FSR_ACCESS_FLAG_FAULT_FIRST: - case FSR_ACCESS_FLAG_FAULT_SECOND: - case FSR_DOMAIN_FAULT_FIRST: - case FSR_DOMAIN_FAULT_SECOND: - case FSR_PERMISION_FAULT_FIRST: - case FSR_PERMISION_FAULT_SECOND: - case FSR_DEBUG_EVENT: //IFAR invalid - case FSR_SYNC_EXT_ABORT: - case FSR_TLB_CONFLICT_ABORT: - case FSR_LOCKDOWN: - case FSR_COPROCESSOR_ABORT: - default: - while(1); - } -} - -//returns amount to decrement lr by -//this will be 0 when we have emulated the instruction and want to execute the next instruction -//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2) -//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4) -uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { - const unsigned int THUMB = 2; - const unsigned int ARM = 4; - //Lazy VFP/NEON initialisation and switching - - // (ARM ARM section A7.5) VFP data processing instruction? - // (ARM ARM section A7.6) VFP/NEON register load/store instruction? - // (ARM ARM section A7.8) VFP/NEON register data transfer instruction? - // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction? - if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) || - (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) { - if (((opcode & 0x00000E00) >> 9) == 5) { - FPUEnable(); - return state; - } - } - - // (ARM ARM section A7.4) NEON data processing instruction? - if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) || - (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) || - // (ARM ARM section A7.7) NEON load/store instruction? - (state == ARM && ((opcode >> 24) == 0xF4)) || - (state == THUMB && ((opcode >> 24) == 0xF9))) { - FPUEnable(); - return state; - } - - //Add code here for other Undef cases - while(1); -} - -#if defined(__ARMCC_VERSION) -#pragma push -#pragma arm -//Critical section, called from undef handler, so systick is disabled -__asm void FPUEnable(void) { - ARM - - //Permit access to VFP/NEON, registers by modifying CPACR - MRC p15,0,R1,c1,c0,2 - ORR R1,R1,#0x00F00000 - MCR p15,0,R1,c1,c0,2 - - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted - ISB - - //Enable VFP/NEON - VMRS R1,FPEXC - ORR R1,R1,#0x40000000 - VMSR FPEXC,R1 - - //Initialise VFP/NEON registers to 0 - MOV R2,#0 - //Initialise D16 registers to 0 - VMOV D0, R2,R2 - VMOV D1, R2,R2 - VMOV D2, R2,R2 - VMOV D3, R2,R2 - VMOV D4, R2,R2 - VMOV D5, R2,R2 - VMOV D6, R2,R2 - VMOV D7, R2,R2 - VMOV D8, R2,R2 - VMOV D9, R2,R2 - VMOV D10,R2,R2 - VMOV D11,R2,R2 - VMOV D12,R2,R2 - VMOV D13,R2,R2 - VMOV D14,R2,R2 - VMOV D15,R2,R2 - //Initialise D32 registers to 0 - VMOV D16,R2,R2 - VMOV D17,R2,R2 - VMOV D18,R2,R2 - VMOV D19,R2,R2 - VMOV D20,R2,R2 - VMOV D21,R2,R2 - VMOV D22,R2,R2 - VMOV D23,R2,R2 - VMOV D24,R2,R2 - VMOV D25,R2,R2 - VMOV D26,R2,R2 - VMOV D27,R2,R2 - VMOV D28,R2,R2 - VMOV D29,R2,R2 - VMOV D30,R2,R2 - VMOV D31,R2,R2 - //Initialise FPSCR to a known state - VMRS R2,FPSCR - LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - AND R2,R2,R3 - VMSR FPSCR,R2 - - BX LR -} -#pragma pop - -#elif defined(__GNUC__) -void FPUEnable(void) { - __asm__ ( - ".ARM;" - - //Permit access to VFP/NEON, registers by modifying CPACR - "MRC p15,0,R1,c1,c0,2;" - "ORR R1,R1,#0x00F00000;" - "MCR p15,0,R1,c1,c0,2;" - - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted - "ISB;" - - //Enable VFP/NEON - "VMRS R1,FPEXC;" - "ORR R1,R1,#0x40000000;" - "VMSR FPEXC,R1;" - - //Initialise VFP/NEON registers to 0 - "MOV R2,#0;" - //Initialise D16 registers to 0 - "VMOV D0, R2,R2;" - "VMOV D1, R2,R2;" - "VMOV D2, R2,R2;" - "VMOV D3, R2,R2;" - "VMOV D4, R2,R2;" - "VMOV D5, R2,R2;" - "VMOV D6, R2,R2;" - "VMOV D7, R2,R2;" - "VMOV D8, R2,R2;" - "VMOV D9, R2,R2;" - "VMOV D10,R2,R2;" - "VMOV D11,R2,R2;" - "VMOV D12,R2,R2;" - "VMOV D13,R2,R2;" - "VMOV D14,R2,R2;" - "VMOV D15,R2,R2;" - //Initialise D32 registers to 0 - "VMOV D16,R2,R2;" - "VMOV D17,R2,R2;" - "VMOV D18,R2,R2;" - "VMOV D19,R2,R2;" - "VMOV D20,R2,R2;" - "VMOV D21,R2,R2;" - "VMOV D22,R2,R2;" - "VMOV D23,R2,R2;" - "VMOV D24,R2,R2;" - "VMOV D25,R2,R2;" - "VMOV D26,R2,R2;" - "VMOV D27,R2,R2;" - "VMOV D28,R2,R2;" - "VMOV D29,R2,R2;" - "VMOV D30,R2,R2;" - "VMOV D31,R2,R2;" - - //Initialise FPSCR to a known state - "VMRS R2,FPSCR;" - "LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - "AND R2,R2,R3;" - "VMSR FPSCR,R2;" - - //"BX LR;" - : - : - :"r1", "r2", "r3"); - return; -} -#else -#endif - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h deleted file mode 100644 index f04b37b8a4..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************//** - * @file system_VKRZA1H.h - * @brief CMSIS Device System Header File for - * ARMCA9 Device Series - * @version V1.00 - * @date 11 June 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __SYSTEM_VKRZA1H -#define __SYSTEM_VKRZA1H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -typedef void(*IRQHandler)(); -uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); -uint32_t InterruptHandlerUnregister(IRQn_Type); - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the Systd short int16_t;emCoreClock variable. - */ -extern void SystemInit (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_VKRZA1H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c new file mode 100644 index 0000000000..dc7ac712b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c @@ -0,0 +1,157 @@ +/****************************************************************************** + * @file system_VK_RZ_A1H_H.c + * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "RZ_A1_Init.h" +#include "irq_ctrl.h" + +#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040) +#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040) +#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu) + +/* + Port 0 (P0) MD pin assignment + P0_0: MD_BOOT0 + P0_1: MD_BOOT1 + P0_2: MD_CLK + P0_3: MD_CLKS + */ + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) + { + uint32_t freq; + uint16_t mode; + uint16_t ifc; + + mode = (GPIO.PPR0 >> 2U) & 0x01U; + + if (mode == 0) { + /* Clock Mode 0 */ + /* CLKIN is between 10MHz and 13.33MHz */ + /* Divider 1 uses 1/1 ratio, PLL x30 is ON */ + freq = CM0_RENESAS_RZ_A1_CLKIN * 30U; + } else { + /* Clock Mode 1 */ + /* CLKIN is 48MHz */ + /* Divider 1 uses 1/4 ratio, PLL x32 is ON */ + freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U; +} + + /* Get CPG.FRQCR[IFC] bits */ + ifc = (CPG.FRQCR >> 8U) & 0x03U; + + /* Determine Divider 2 output clock */ + if (ifc == 0x03U) { + /* Division ratio is 1/3 */ + freq = (freq / 3U); + } + else { + if (ifc == 0x01U) { + /* Division ratio is 2/3 */ + freq = (freq * 2U) / 3U; + } +} + + SystemCoreClock = freq; +} + +/*---------------------------------------------------------------------------- + IRQ Handler Register/Unregister + *----------------------------------------------------------------------------*/ +uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) +{ + return IRQ_SetHandler(irq, handler); +} + +uint32_t InterruptHandlerUnregister (IRQn_Type irq) +{ + return IRQ_SetHandler(irq, (IRQHandler_t)NULL); +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +/* do not use global variables because this function is called before + reaching pre-main. RW section maybe overwritten afterwards. */ + + // Enable SRAM write access + CPG.SYSCR3 = 0x0F; + + RZ_A1_InitClock(); + RZ_A1_InitBus(); + + // Invalidate entire Unified TLB + __set_TLBIALL(0); + + // Invalidate entire branch predictor array + __set_BPIALL(0); + __DSB(); + __ISB(); + + // Invalidate instruction cache and flush branch target cache + __set_ICIALLU(0); + __DSB(); + __ISB(); + + // Invalidate data cache + L1C_InvalidateDCacheAll(); + + // Create Translation Table + MMU_CreateTranslationTable(); + + // Enable MMU + MMU_Enable(); + + // Enable Caches + L1C_EnableCaches(); + L1C_EnableBTAC(); + +#if (__L2C_PRESENT == 1) + L2C_InvAllByWay(); + // Enable L2C + L2C_Enable(); +#endif + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + // IRQ Initialize + IRQ_Initialize(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h new file mode 100644 index 0000000000..ef8754d873 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * @file system_VK_RZ_A1H.h + * @brief CMSIS Device System Header File for ARM Cortex-A Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_VK_RZ_A1H_H +#define __SYSTEM_VK_RZ_A1H_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + \brief Interrupt Handler Register. + + Registers an Interrupt Handler into the IRQ Table. + */ +extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); + +/** + \brief Interrupt Handler Unregister. + + Unregisters an Interrupt Handler from the IRQ Table. + */ +extern uint32_t InterruptHandlerUnregister(IRQn_Type); + +/** + \brief Create Translation Table. + + Creates Memory Management Unit Translation Table. + */ +extern void MMU_CreateTranslationTable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_VK_RZ_A1H_H */ diff --git a/targets/TARGET_RENESAS/mbed_rtx.h b/targets/TARGET_RENESAS/mbed_rtx.h index 08f4a53bc5..f7c91c6a21 100644 --- a/targets/TARGET_RENESAS/mbed_rtx.h +++ b/targets/TARGET_RENESAS/mbed_rtx.h @@ -18,7 +18,7 @@ #include -#if defined(TARGET_RZ_A1H) || defined(TARGET_GR_LYCHEE) +#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H) || defined(TARGET_GR_LYCHEE) #define OS_IDLE_THREAD_STACK_SIZE 512 #if defined(__CC_ARM) diff --git a/targets/targets.json b/targets/targets.json index a685eb4d80..cf419d241e 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2698,8 +2698,8 @@ }, "VK_RZ_A1H": { "inherits": ["RZ_A1XX"], - "extra_labels": ["RZA1H", "VKRZA1H"], - "release_versions": [] + "extra_labels_add": ["RZA1H", "VKRZA1H"], + "release_versions": ["2", "5"] }, "GR_LYCHEE": { "inherits": ["RZ_A1XX"], From 0d8874cdce96a511075d2ce1461bd2b1ba586fbc Mon Sep 17 00:00:00 2001 From: ccli8 Date: Mon, 19 Mar 2018 17:52:01 +0800 Subject: [PATCH 095/118] Remove unnecessary UART INT in UART DMA transfer In UART DMA transfer, it is PDMA INT rather than UART INT to go INT path --- targets/TARGET_NUVOTON/TARGET_M451/serial_api.c | 8 ++++++++ targets/TARGET_NUVOTON/TARGET_M480/serial_api.c | 8 ++++++++ targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c | 8 ++++++++ targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c | 8 ++++++++ 4 files changed, 32 insertions(+) diff --git a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c index 382ea3e7e7..5c6b3335fc 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c @@ -503,6 +503,10 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx // Register DMA event handler dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); serial_tx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer } @@ -566,6 +570,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt // Register DMA event handler dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); serial_rx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer } } diff --git a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c index 25695156a3..04c15c21d4 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c @@ -561,6 +561,10 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx // Register DMA event handler dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); serial_tx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer } @@ -622,6 +626,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt // Register DMA event handler dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); serial_rx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer } } diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c index 7810d00977..4a7b26d608 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c @@ -458,6 +458,10 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx // Register DMA event handler dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); serial_tx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_IER_THRE_IE_Msk); PDMA_Trigger(obj->serial.dma_chn_id_tx); ((UART_T *) NU_MODBASE(obj->serial.uart))->CTL |= UART_CTL_DMA_TX_EN_Msk; // Start DMA transfer } @@ -514,6 +518,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt // Register DMA event handler dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); serial_rx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk)); PDMA_Trigger(obj->serial.dma_chn_id_rx); ((UART_T *) NU_MODBASE(obj->serial.uart))->CTL |= UART_CTL_DMA_RX_EN_Msk; // Start DMA transfer } diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c index be8e304c4e..37d66761e7 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c @@ -543,6 +543,10 @@ int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx // Register DMA event handler dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); serial_tx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer } @@ -604,6 +608,10 @@ void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_widt // Register DMA event handler dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); serial_rx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer } } From 3445a3a2410ff02db5c0f2046aa383cd141598d0 Mon Sep 17 00:00:00 2001 From: Tony Wu Date: Tue, 13 Mar 2018 18:32:24 +0800 Subject: [PATCH 096/118] armcc - remove fromelf output before regenerating Fix armcc recompile errors during elf2bin stage. Errors shown as follows: Elf2Bin: mbed-os-example-wifi Error: Q0147E: Failed to create Directory .\BUILD\REALTEK_RTL8195AM\ARM\mbed-os-example-wifi.bin\IMAGE2_TABLE: File exists Finished: 0 information, 0 warning and 1 error messages. [ERROR] Error: Q0147E: Failed to create Directory .\BUILD\REALTEK_RTL8195AM\ARM\mbed-os-example-wifi.bin\IMAGE2_TABLE: File exists Finished: 0 information, 0 warning and 1 error messages. Signed-off-by: Tony Wu --- tools/toolchains/arm.py | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/tools/toolchains/arm.py b/tools/toolchains/arm.py index 5d36c37d44..9bb21ece5f 100644 --- a/tools/toolchains/arm.py +++ b/tools/toolchains/arm.py @@ -19,9 +19,10 @@ from builtins import str import re from copy import copy -from os.path import join, dirname, splitext, basename, exists, relpath -from os import makedirs, write, curdir +from os.path import join, dirname, splitext, basename, exists, relpath, isfile +from os import makedirs, write, curdir, remove from tempfile import mkstemp +from shutil import rmtree from tools.toolchains import mbedToolchain, TOOLCHAIN_PATHS from tools.hooks import hook_tool @@ -254,6 +255,14 @@ class ARM(mbedToolchain): bin_arg = {".bin": "--bin", ".hex": "--i32"}[fmt] cmd = [self.elf2bin, bin_arg, '-o', bin, elf] cmd = self.hook.get_cmdline_binary(cmd) + + # remove target binary file/path + if exists(bin): + if isfile(bin): + remove(bin) + else: + rmtree(bin) + self.cc_verbose("FromELF: %s" % ' '.join(cmd)) self.default_cmd(cmd) From 9502d6b7c58ec15426c789584d1c8477b515bf77 Mon Sep 17 00:00:00 2001 From: Hugues de Valon Date: Mon, 8 Jan 2018 15:19:48 +0000 Subject: [PATCH 097/118] CM3DS: switch to larger memories for code and data This patch changes the linker files and defines to use the ZBT SSRAM instead of the FPGA Block RAM for code and data. The section 4.1.1, Code and RAM memory map, of the CM3DS Eval RTL and testbench user guide explains the available memories. This switch improves code memory from 256 kB to 4 MB and data memory from 128 kB to 4 MB. However, the ZBT SSRAM1 for code memory begins at 0x00400000 while the processor can only boot at address 0x00000000 which means that it expects the vector table to be at that address. That is why we have to create 2 load regions in the linker scripts: one with only the vector table at address 0x0 and one with code + data at address 0x00400000. Because of these two load regions, linker will produce different behaviours: * GCC_ARM and IAR will only create 1 binary with both load regions padding with 0 in between. The binary will then be very large (at least 4 MB) and the flash process will take longer. * ARM and ARMC6 will create 2 binaries for the two load regions. The load addresses of the two binaries can be written in the images.txt file on the MPS2 board. You can also use the --bincombined option of fromelf utility to produce only 1 large binary. This patch also adds the memory_zones.h file to try to put in common all the memory addresses that were previously hard coded in the linker scripts / startup files. With that patch in, the simplest option is to directly use the .elf file with the MPS2, which is only possible with mbb_v225.ebf and more recent firmwares. It will now be the default for CM3DS. This commit works with greentea thanks to the now merged pull request ARMmbed/htrun#181 in order to copy .elf file to the MPS2 board. Signed-off-by: Hugues de Valon --- .../TARGET_CM3DS_MPS2/README.md | 62 +++++++++++++++++++ .../device/TOOLCHAIN_ARM_STD/MPS2.sct | 25 +++++--- .../device/TOOLCHAIN_ARM_STD/startup_MPS2.S | 6 +- .../device/TOOLCHAIN_GCC_ARM/MPS2.ld | 26 ++++---- .../device/TOOLCHAIN_IAR/MPS2.icf | 62 ++++++++++++------- .../TARGET_CM3DS_MPS2/device/cmsis_nvic.h | 29 ++++++++- .../TARGET_CM3DS_MPS2/device/memory_zones.h | 56 +++++++++++++++++ targets/TARGET_ARM_SSG/mbed_rtx.h | 14 ++++- targets/targets.json | 1 + 9 files changed, 229 insertions(+), 52 deletions(-) create mode 100644 targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md create mode 100644 targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/memory_zones.h diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md new file mode 100644 index 0000000000..2d7495b8a0 --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md @@ -0,0 +1,62 @@ +# Cortex-M3 Design Start Eval package example on MPS2+ board + +This folder includes the port of mbed OS on the example system of the Cortex-M3 +Design Start Eval package. This example is implemented in FPGA on the MPS2+ +board. Please check the [mbed page](https://os.mbed.com/platforms/ARM-CM3DS/) of +this target for more information. +For convenience, this target is called **CM3DS**. + +## Compiling :construction_worker: + +The target name is `ARM_CM3DS_MPS2`, you should be able to compile mbed OS +projects for CM3DS with: + +```bash +mbed compile -t COMPILER -m ARM_CM3DS_MPS2 +``` + +The following compilers are supported (replace `COMPILER` with): + +* `ARM` for Arm Compiler version 5 +* `GCC_ARM` for GNU Compiler for Arm +* `IAR` for IAR compiler + +## Running :running: + +Because of the new memory configuration introduced in commit `CM3DS: switch to +larger memories for code and data` it +has become more easy (and portable amoung all compilers) to use `.elf` files +instead of `.bin`. `.elf` files are now the default for CM3DS projects and only +they will be generated out of the compilation. +For `.elf` files to work, you will need **at least version 2.2.5** of the MPS2+ +firmware. You can find firmware version 2.2.6 and instructions on how to put it +in the MPS2+ board [here](https://community.arm.com/processors/designstart/f/discussions/9727/mps2-firmware-for-mbed). + +## Testing :zap: + +If you want to execute the mbed OS greentea tests on CM3DS, you will need +**at least firmware version 2.2.6**. + +* `mbedls` does not automatically recognize which serial port is linked to the +board. Check it manually and create a file named `mbedls.json` containing +(at the same level than where you execute all commands): +```bash +{ + "50040200074D652F3828F333": { + "serial_port": "/dev/ttyUSB0" + } +} +``` +Replace `/dev/ttyUSB0` with your correct serial port +(something like `COM6` on Windows). + +* `mbedls` does not link CM3DS target ID with its name so execute the command: +```bash +mbedls --mock 5004:ARM_CM3DS_MPS2 +``` + +* You can now compile and run the tests :+1: : +```bash +mbed test -m ARM_CM3DS_MPS2 -t COMPILER +``` + diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/MPS2.sct index a4f545c2ad..060d82bc38 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/MPS2.sct +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/MPS2.sct @@ -1,7 +1,9 @@ +#! armcc -E + /* * MPS2 CMSIS Library * - * Copyright (c) 2006-2017 ARM Limited. All rights reserved. + * Copyright (c) 2006-2018 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -22,16 +24,25 @@ ************************************************************* */ -LR_IROM1 0x00000000 0x00040000 { ; load region size_region - ER_IROM1 0x00000000 0x00040000 { ; load address = execution address +#include "../memory_zones.h" +#include "../cmsis_nvic.h" + +; The vector table is loaded at address 0x00000000 in Flash memory region. +LR_IROM1 FLASH_START FLASH_SIZE { + ER_IROM1 FLASH_START FLASH_SIZE { *.o (RESET, +First) + } +} + +; Rest of the code is loaded to the ZBT SSRAM1. +LR_IROM2 ZBT_SSRAM1_START ZBT_SSRAM1_SIZE { + ER_IROM2 ZBT_SSRAM1_START ZBT_SSRAM1_SIZE { *(InRoot$$Sections) .ANY (+RO) } - ; Total: 80 vectors = 320 bytes (0x140) to be reserved in RAM - ; This is a bit more than is necessary based on the number of - ; exception handlers. - RW_IRAM1 (0x20000000+0x140) (0x20000-0x140) { ; RW data + ; At execution, RAM is set to be in ZBT SSRAM2 and 3, just after the vector + ; table previously moved from Flash. + RW_IRAM1 (ZBT_SSRAM23_START + NVIC_VECTORS_SIZE) (ZBT_SSRAM23_SIZE - NVIC_VECTORS_SIZE) { .ANY (+RW +ZI) } } diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.S b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.S index 93c14e2d1f..8399347cf7 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.S +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.S @@ -1,7 +1,7 @@ /* * MPS2 CMSIS Library * - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -20,11 +20,11 @@ * * This file is derivative of CMSIS V5.00 startup_ARMCM3.s * -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ +#include "memory_zones.h" -__initial_sp EQU 0x20020000 ; Top of RAM +__initial_sp EQU ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE ; Top of ZBT SSRAM2 and 3, used for data PRESERVE8 THUMB diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_GCC_ARM/MPS2.ld b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_GCC_ARM/MPS2.ld index f5bbdd4080..2e16e6f297 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_GCC_ARM/MPS2.ld +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_GCC_ARM/MPS2.ld @@ -1,8 +1,5 @@ /* - * MPS2 CMSIS Library - */ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -17,21 +14,20 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - */ -/* + * * This file is derivative of CMSIS V5.00 gcc_arm.ld + * + * Linker script for mbed CM3DS on MPS2 */ -/* Linker script for mbed CM3DS on MPS2 */ -/* Linker script to configure memory regions. */ -/* The length of the VECTORS region is a bit larger than - * is necessary based on the number of exception handlers. - */ +#include "../memory_zones.h" +#include "../cmsis_nvic.h" + MEMORY { - VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400 - FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400 - RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 + VECTORS (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE + FLASH (rx) : ORIGIN = ZBT_SSRAM1_START, LENGTH = ZBT_SSRAM1_SIZE + RAM (rwx) : ORIGIN = ZBT_SSRAM23_START, LENGTH = ZBT_SSRAM23_SIZE } /* Linker script to place sections and symbol values. Should be used together @@ -66,7 +62,7 @@ HEAP_SIZE = 0x4000; STACK_SIZE = 0x1000; /* Size of the vector table in SRAM */ -M_VECTOR_RAM_SIZE = 0x140; +M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE; SECTIONS { diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/MPS2.icf b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/MPS2.icf index 0c3b737744..e888b99dbc 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/MPS2.icf +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/MPS2.icf @@ -1,8 +1,5 @@ /* - * MPS2 CMSIS Library - */ -/* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -19,26 +16,49 @@ * limitations under the License. */ -/* The RAM region doesn't start at the beginning of the RAM address - * space to create space for the vector table copied over to the RAM by mbed. - * The space left is a bit bigger than is necessary based on the number of - * interrupt handlers. +/* + * WARNING: these symbols are the same as the defines in ../memory_zones.h but + * can not be included here. Please make sure that the two definitions match. */ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000140; -define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; -/*-Sizes-*/ +/* Code memory zones */ +define symbol FLASH_START = 0x00000000; +define symbol FLASH_SIZE = 0x00040000; /* 256 KiB */ +define symbol ZBT_SSRAM1_START = 0x00400000; +define symbol ZBT_SSRAM1_SIZE = 0x00400000; /* 4 MiB */ + +/* Data memory zones */ +define symbol SRAM0_START = 0x20000000; +define symbol SRAM0_SIZE = 0x00008000; /* 32 KiB */ +define symbol SRAM1_START = 0x20008000; +define symbol SRAM1_SIZE = 0x00008000; /* 32 KiB */ +define symbol SRAM2_START = 0x20010000; +define symbol SRAM2_SIZE = 0x00008000; /* 32 KiB */ +define symbol SRAM3_START = 0x20018000; +define symbol SRAM3_SIZE = 0x00008000; /* 32 KiB */ +define symbol ZBT_SSRAM23_START = 0x20400000; +define symbol ZBT_SSRAM23_SIZE = 0x00400000; /* 4 MiB */ + +/* NVIC vector numbers and size. */ +define symbol NVIC_NUM_VECTORS = 16 + 57; +define symbol NVIC_VECTORS_SIZE = NVIC_NUM_VECTORS * 4; + +/* Specials */ +define symbol __ICFEDIT_intvec_start__ = FLASH_START; + +/* Memory Regions */ +define symbol __ICFEDIT_region_ROM_start__ = ZBT_SSRAM1_START; +define symbol __ICFEDIT_region_ROM_end__ = ZBT_SSRAM1_START + ZBT_SSRAM1_SIZE - 1; +/* + * At execution, RAM is set to be in ZBT SSRAM2 and 3, just after the vector + * table previously moved from Flash. + */ +define symbol __ICFEDIT_region_RAM_start__ = ZBT_SSRAM23_START + NVIC_VECTORS_SIZE; +define symbol __ICFEDIT_region_RAM_end__ = ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE; + +/* Sizes */ /* Heap and Stack size */ -define symbol __ICFEDIT_size_heap__ = 0x4000; +define symbol __ICFEDIT_size_heap__ = 0xF000; define symbol __ICFEDIT_size_cstack__ = 0x1000; -/**** End of ICF editor section. ###ICF###*/ define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/cmsis_nvic.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/cmsis_nvic.h index 5181aaac5c..be4fb3a8fe 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/cmsis_nvic.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/cmsis_nvic.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2015-2017 ARM Limited + * Copyright (c) 2015-2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -14,12 +14,35 @@ * limitations under the License. * * CMSIS-style functionality to support dynamic vectors + * + * This file is included in ARM and GCC_ARM linker scripts. + * + * WARNING: IAR does not include this file and re-define these values in + * MPS2.icf file. Please make sure that the two files share the same values. */ +#include "memory_zones.h" + #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -#define NVIC_NUM_VECTORS (16 + 48) -#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 /* Location of vectors in RAM */ +/* + * 16 vectors for initial stack pointer and internal exceptions (defined in + * Armv7-M ARM). + * 57 vectors for external interrupts (defined in CM3DS Eval RTL and Testbench + * User Guide). + */ +#define NVIC_NUM_VECTORS (16 + 57) + +/* + * Location of vectors in RAM, they are copied at boot from adress 0x00000000 to + * that address. + */ +#define NVIC_RAM_VECTOR_ADDRESS ZBT_SSRAM23_START + +/* + * Size of the whole vector table in bytes. Each vector is on 32 bits. + */ +#define NVIC_VECTORS_SIZE (NVIC_NUM_VECTORS * 4) #endif /* MBED_CMSIS_NVIC_H */ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/memory_zones.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/memory_zones.h new file mode 100644 index 0000000000..7d0fca598b --- /dev/null +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/memory_zones.h @@ -0,0 +1,56 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * This file contains the information of memory zones for code and data on + * CM3DS. + * It is used in startup code and linker scripts of supported compilers (ARM and + * GCC_ARM). + * + * WARNING: IAR does not include this file and re-define these values in + * MPS2.icf file. Please make sure that the two files share the same values. + * + * These memory zones are defined in section 4.1.1 of CM3DS Eval RTL and + * Testbench User Guide. + */ + +#ifndef MEMORY_ZONES_H +#define MEMORY_ZONES_H + +/* + * Code memory zones + * Please note that CM3DS on MPS2 does not contain any persistent flash memory. + * The FLASH memory zone is a 256 KiB SRAM block in the FPGA and named FLASH + * only to keep the same name than in the CM3DS Eval RTL and Testbench User + * Guide. + */ +#define FLASH_START 0x00000000 +#define FLASH_SIZE 0x00040000 /* 256 KiB */ +#define ZBT_SSRAM1_START 0x00400000 +#define ZBT_SSRAM1_SIZE 0x00400000 /* 4 MiB */ + +/* Data memory zones */ +#define SRAM0_START 0x20000000 +#define SRAM0_SIZE 0x00008000 /* 32 KiB */ +#define SRAM1_START 0x20008000 +#define SRAM1_SIZE 0x00008000 /* 32 KiB */ +#define SRAM2_START 0x20010000 +#define SRAM2_SIZE 0x00008000 /* 32 KiB */ +#define SRAM3_START 0x20018000 +#define SRAM3_SIZE 0x00008000 /* 32 KiB */ +#define ZBT_SSRAM23_START 0x20400000 +#define ZBT_SSRAM23_SIZE 0x00400000 /* 4 MiB */ + +#endif /* MEMORY_ZONES_H */ + diff --git a/targets/TARGET_ARM_SSG/mbed_rtx.h b/targets/TARGET_ARM_SSG/mbed_rtx.h index 0a743ccb8a..9a757249fd 100644 --- a/targets/TARGET_ARM_SSG/mbed_rtx.h +++ b/targets/TARGET_ARM_SSG/mbed_rtx.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2017 ARM Limited + * Copyright (c) 2016-2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -17,12 +17,20 @@ #ifndef MBED_MBED_RTX_H #define MBED_MBED_RTX_H -#if defined(TARGET_BEETLE) || defined(TARGET_CM3DS_MPS2) +#if defined(TARGET_BEETLE) #ifndef INITIAL_SP #define INITIAL_SP (0x20020000UL) #endif +#elif defined(TARGET_CM3DS_MPS2) + +#include "memory_zones.h" + +#ifndef INITIAL_SP +#define INITIAL_SP (ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE) #endif -#endif // MBED_MBED_RTX_H +#endif /* defined(TARGET_...) */ + +#endif /* MBED_MBED_RTX_H */ diff --git a/targets/targets.json b/targets/targets.json index cf419d241e..a0276a7185 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2664,6 +2664,7 @@ "core": "Cortex-M3", "supported_toolchains": ["ARM", "GCC_ARM", "IAR"], "extra_labels": ["ARM_SSG", "CM3DS_MPS2"], + "OUTPUT_EXT": "elf", "macros": ["CMSDK_CM3DS"], "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC", "LOWPOWERTIMER"], "release_versions": ["2", "5"], From 1b581736c95c0fae0c3b9b5f41dad44d6e2c02b6 Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Wed, 28 Feb 2018 19:48:36 -0600 Subject: [PATCH 098/118] Copy edit README.md Copy edit for branding, consistent tense and consistent style. --- .../TARGET_CM3DS_MPS2/README.md | 36 +++++++++---------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md index 2d7495b8a0..93d8d53897 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md @@ -2,13 +2,13 @@ This folder includes the port of mbed OS on the example system of the Cortex-M3 Design Start Eval package. This example is implemented in FPGA on the MPS2+ -board. Please check the [mbed page](https://os.mbed.com/platforms/ARM-CM3DS/) of +board. Please check the [Mbed page](https://os.mbed.com/platforms/ARM-CM3DS/) of this target for more information. For convenience, this target is called **CM3DS**. -## Compiling :construction_worker: +## Compiling -The target name is `ARM_CM3DS_MPS2`, you should be able to compile mbed OS +The target name is `ARM_CM3DS_MPS2`, you should be able to compile Mbed OS projects for CM3DS with: ```bash @@ -17,28 +17,28 @@ mbed compile -t COMPILER -m ARM_CM3DS_MPS2 The following compilers are supported (replace `COMPILER` with): -* `ARM` for Arm Compiler version 5 -* `GCC_ARM` for GNU Compiler for Arm -* `IAR` for IAR compiler +* `ARM` for Arm Compiler version 5. +* `GCC_ARM` for GNU Compiler for Arm. +* `IAR` for IAR compiler. -## Running :running: +## Running Because of the new memory configuration introduced in commit `CM3DS: switch to -larger memories for code and data` it -has become more easy (and portable amoung all compilers) to use `.elf` files +larger memories for code and data`, it +has become easier (and portable amoung all compilers) to use `.elf` files instead of `.bin`. `.elf` files are now the default for CM3DS projects and only -they will be generated out of the compilation. -For `.elf` files to work, you will need **at least version 2.2.5** of the MPS2+ -firmware. You can find firmware version 2.2.6 and instructions on how to put it -in the MPS2+ board [here](https://community.arm.com/processors/designstart/f/discussions/9727/mps2-firmware-for-mbed). +they will be generated from the compilation. +For `.elf` files to work, you need **at least version 2.2.5** of the MPS2+ +firmware. For more information, please see the [firmware version 2.2.6 and instructions on how to put it +in the MPS2+ board](https://community.arm.com/processors/designstart/f/discussions/9727/mps2-firmware-for-mbed). -## Testing :zap: +## Testing -If you want to execute the mbed OS greentea tests on CM3DS, you will need +If you want to execute the Mbed OS greentea tests on CM3DS, you need **at least firmware version 2.2.6**. * `mbedls` does not automatically recognize which serial port is linked to the -board. Check it manually and create a file named `mbedls.json` containing +board. Check it manually, and create a file named `mbedls.json` containing (at the same level than where you execute all commands): ```bash { @@ -50,12 +50,12 @@ board. Check it manually and create a file named `mbedls.json` containing Replace `/dev/ttyUSB0` with your correct serial port (something like `COM6` on Windows). -* `mbedls` does not link CM3DS target ID with its name so execute the command: +* `mbedls` does not link CM3DS target ID with its name, so execute the command: ```bash mbedls --mock 5004:ARM_CM3DS_MPS2 ``` -* You can now compile and run the tests :+1: : +* You can now compile and run the tests ```bash mbed test -m ARM_CM3DS_MPS2 -t COMPILER ``` From 5cf249ac4c68634a6b5d28f6ef50daef26f5b0ed Mon Sep 17 00:00:00 2001 From: Amanda Butler Date: Fri, 9 Mar 2018 19:06:39 -0600 Subject: [PATCH 099/118] Copy edit README.md Copy edit for active voice, branding, spelling and other minor grammar fixes. --- .../TARGET_CM3DS_MPS2/README.md | 23 +++++++++++-------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md index 93d8d53897..76ea486418 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/README.md @@ -1,21 +1,21 @@ # Cortex-M3 Design Start Eval package example on MPS2+ board -This folder includes the port of mbed OS on the example system of the Cortex-M3 +This folder includes the port of Mbed OS on the example system of the Cortex-M3 Design Start Eval package. This example is implemented in FPGA on the MPS2+ -board. Please check the [Mbed page](https://os.mbed.com/platforms/ARM-CM3DS/) of -this target for more information. +board. Please see this target's [Mbed page](https://os.mbed.com/platforms/ARM-CM3DS/) +for more information. For convenience, this target is called **CM3DS**. ## Compiling -The target name is `ARM_CM3DS_MPS2`, you should be able to compile Mbed OS +The target name is `ARM_CM3DS_MPS2`. You can compile Mbed OS projects for CM3DS with: ```bash mbed compile -t COMPILER -m ARM_CM3DS_MPS2 ``` -The following compilers are supported (replace `COMPILER` with): +Mbed OS supports the following compilers (replace `COMPILER` with): * `ARM` for Arm Compiler version 5. * `GCC_ARM` for GNU Compiler for Arm. @@ -25,9 +25,9 @@ The following compilers are supported (replace `COMPILER` with): Because of the new memory configuration introduced in commit `CM3DS: switch to larger memories for code and data`, it -has become easier (and portable amoung all compilers) to use `.elf` files -instead of `.bin`. `.elf` files are now the default for CM3DS projects and only -they will be generated from the compilation. +has become easier (and portable among all compilers) to use `.elf` files +instead of `.bin`. `.elf` files are now the default for CM3DS projects, and compilation +generates only them. For `.elf` files to work, you need **at least version 2.2.5** of the MPS2+ firmware. For more information, please see the [firmware version 2.2.6 and instructions on how to put it in the MPS2+ board](https://community.arm.com/processors/designstart/f/discussions/9727/mps2-firmware-for-mbed). @@ -40,6 +40,7 @@ If you want to execute the Mbed OS greentea tests on CM3DS, you need * `mbedls` does not automatically recognize which serial port is linked to the board. Check it manually, and create a file named `mbedls.json` containing (at the same level than where you execute all commands): + ```bash { "50040200074D652F3828F333": { @@ -47,16 +48,18 @@ board. Check it manually, and create a file named `mbedls.json` containing } } ``` + Replace `/dev/ttyUSB0` with your correct serial port (something like `COM6` on Windows). * `mbedls` does not link CM3DS target ID with its name, so execute the command: + ```bash mbedls --mock 5004:ARM_CM3DS_MPS2 ``` -* You can now compile and run the tests +* You can now compile and run the tests: + ```bash mbed test -m ARM_CM3DS_MPS2 -t COMPILER ``` - From 1a2b41ce34f8a2b2fca5a15bc1eca538ddab9899 Mon Sep 17 00:00:00 2001 From: Christopher Haster Date: Thu, 15 Mar 2018 16:19:04 -0500 Subject: [PATCH 100/118] equeue: Added profiling reports to Travis --- .travis.yml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/.travis.yml b/.travis.yml index ff8445a5fa..8259c65d7a 100644 --- a/.travis.yml +++ b/.travis.yml @@ -115,6 +115,24 @@ matrix: - python tools/make.py -t GCC_ARM -m DISCO_F401VC --source=. --build=BUILD/DISCO_F401VC/GCC_ARM -j0 # Run local equeue tests - make -C $EVENTS/equeue test + # Run profiling tests + - make -C $EVENTS/equeue prof | tee prof + after_success: + # update status if we succeeded, compare with master if possible + - | + CURR=$(grep -o '[0-9]\+ cycles' prof | awk '{sum += $1} END {print sum}') + PREV=$(curl https://api.github.com/repos/$TRAVIS_REPO_SLUG/status/master \ + | jq -re "select(.sha != \"$TRAVIS_COMMIT\") + | .statuses[] | select(.context == \"travis-ci/$NAME\").description + | capture(\"runtime is (?[0-9]+)\").runtime" \ + || echo 0) + + STATUSM="Passed, runtime is ${CURR} cycles" + if [ "$PREV" -ne 0 ] + then + STATUSM="$STATUSM ($(python -c "print '%+d' % ($CURR-$PREV)") cycles)" + fi + - bash -c "$STATUS" success "$STATUSM" - env: - NAME=littlefs From b7441114fd2f3ec87fef01cf6db36d3f82c634e6 Mon Sep 17 00:00:00 2001 From: Kevin Bracey Date: Tue, 28 Nov 2017 12:10:53 +0200 Subject: [PATCH 101/118] Remove unnecessary casts The volatile qualifier on the __LDREX/__STREX prototypes only means that it's safe to use them on volatile objects. Doesn't mean you actually have to pass them volatile pointers. Adding the volatile is a bit like doing strlen((const char *) ptr) because you've got a non-const pointer. --- platform/mbed_critical.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/platform/mbed_critical.c b/platform/mbed_critical.c index 98f1478520..eb1f4c2593 100644 --- a/platform/mbed_critical.c +++ b/platform/mbed_critical.c @@ -119,26 +119,26 @@ void core_util_critical_section_exit(void) bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue) { do { - uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr); + uint8_t currentValue = __LDREXB(ptr); if (currentValue != *expectedCurrentValue) { *expectedCurrentValue = currentValue; __CLREX(); return false; } - } while (__STREXB(desiredValue, (volatile uint8_t*)ptr)); + } while (__STREXB(desiredValue, ptr)); return true; } bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue) { do { - uint16_t currentValue = __LDREXH((volatile uint16_t*)ptr); + uint16_t currentValue = __LDREXH(ptr); if (currentValue != *expectedCurrentValue) { *expectedCurrentValue = currentValue; __CLREX(); return false; } - } while (__STREXH(desiredValue, (volatile uint16_t*)ptr)); + } while (__STREXH(desiredValue, ptr)); return true; } @@ -146,13 +146,13 @@ bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uin bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue) { do { - uint32_t currentValue = __LDREXW((volatile uint32_t*)ptr); + uint32_t currentValue = __LDREXW(ptr); if (currentValue != *expectedCurrentValue) { *expectedCurrentValue = currentValue; __CLREX(); return false; } - } while (__STREXW(desiredValue, (volatile uint32_t*)ptr)); + } while (__STREXW(desiredValue, ptr)); return true; } @@ -160,8 +160,8 @@ uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta) { uint8_t newValue; do { - newValue = __LDREXB((volatile uint8_t*)valuePtr) + delta; - } while (__STREXB(newValue, (volatile uint8_t*)valuePtr)); + newValue = __LDREXB(valuePtr) + delta; + } while (__STREXB(newValue, valuePtr)); return newValue; } @@ -169,8 +169,8 @@ uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta) { uint16_t newValue; do { - newValue = __LDREXH((volatile uint16_t*)valuePtr) + delta; - } while (__STREXH(newValue, (volatile uint16_t*)valuePtr)); + newValue = __LDREXH(valuePtr) + delta; + } while (__STREXH(newValue, valuePtr)); return newValue; } @@ -178,8 +178,8 @@ uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta) { uint32_t newValue; do { - newValue = __LDREXW((volatile uint32_t*)valuePtr) + delta; - } while (__STREXW(newValue, (volatile uint32_t*)valuePtr)); + newValue = __LDREXW(valuePtr) + delta; + } while (__STREXW(newValue, valuePtr)); return newValue; } @@ -188,8 +188,8 @@ uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta) { uint8_t newValue; do { - newValue = __LDREXB((volatile uint8_t*)valuePtr) - delta; - } while (__STREXB(newValue, (volatile uint8_t*)valuePtr)); + newValue = __LDREXB(valuePtr) - delta; + } while (__STREXB(newValue, valuePtr)); return newValue; } @@ -197,8 +197,8 @@ uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta) { uint16_t newValue; do { - newValue = __LDREXH((volatile uint16_t*)valuePtr) - delta; - } while (__STREXH(newValue, (volatile uint16_t*)valuePtr)); + newValue = __LDREXH(valuePtr) - delta; + } while (__STREXH(newValue, valuePtr)); return newValue; } @@ -206,8 +206,8 @@ uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta) { uint32_t newValue; do { - newValue = __LDREXW((volatile uint32_t*)valuePtr) - delta; - } while (__STREXW(newValue, (volatile uint32_t*)valuePtr)); + newValue = __LDREXW(valuePtr) - delta; + } while (__STREXW(newValue, valuePtr)); return newValue; } From c6ab7de915dc6fc70d5322ce9e354c464b283ae8 Mon Sep 17 00:00:00 2001 From: Kevin Bracey Date: Tue, 28 Nov 2017 12:45:50 +0200 Subject: [PATCH 102/118] Add volatile qualifiers to atomic functions The atomic functions preserve volatile semantics - they only perform the accesses specified. Add the volatile qualifier to the value pointer to reflect this. This does not change existing caller code - it's equivalent to adding a const qualifier to indicate we don't write to a pointer - it means people can pass us qualified pointers without casts, letting the compile check const- or volatile-correctness. This is consistent with C11 , which volatile-qualifies its equivalent functions. Note that this useage of volatile has nothing to do with the atomicity - objects accessed via the atomic functions do not need to be volatile. But it does permit these calls to be used on objects which have been declared volatile. --- platform/mbed_critical.c | 48 ++++++++++++++++++++-------------------- platform/mbed_critical.h | 24 ++++++++++---------- 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/platform/mbed_critical.c b/platform/mbed_critical.c index eb1f4c2593..d9dcc78a4b 100644 --- a/platform/mbed_critical.c +++ b/platform/mbed_critical.c @@ -116,7 +116,7 @@ void core_util_critical_section_exit(void) #pragma diag_suppress 3731 #endif -bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue) +bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue) { do { uint8_t currentValue = __LDREXB(ptr); @@ -129,7 +129,7 @@ bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_ return true; } -bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue) +bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue) { do { uint16_t currentValue = __LDREXH(ptr); @@ -143,7 +143,7 @@ bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uin } -bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue) +bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue) { do { uint32_t currentValue = __LDREXW(ptr); @@ -156,7 +156,7 @@ bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uin return true; } -uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta) +uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta) { uint8_t newValue; do { @@ -165,7 +165,7 @@ uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta) return newValue; } -uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta) +uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta) { uint16_t newValue; do { @@ -174,7 +174,7 @@ uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta) return newValue; } -uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta) +uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta) { uint32_t newValue; do { @@ -184,7 +184,7 @@ uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta) } -uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta) +uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta) { uint8_t newValue; do { @@ -193,7 +193,7 @@ uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta) return newValue; } -uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta) +uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta) { uint16_t newValue; do { @@ -202,7 +202,7 @@ uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta) return newValue; } -uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta) +uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta) { uint32_t newValue; do { @@ -213,7 +213,7 @@ uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta) #else -bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue) +bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue) { bool success; uint8_t currentValue; @@ -230,7 +230,7 @@ bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_ return success; } -bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue) +bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue) { bool success; uint16_t currentValue; @@ -248,7 +248,7 @@ bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uin } -bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue) +bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue) { bool success; uint32_t currentValue; @@ -266,7 +266,7 @@ bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uin } -uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta) +uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta) { uint8_t newValue; core_util_critical_section_enter(); @@ -276,7 +276,7 @@ uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta) return newValue; } -uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta) +uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta) { uint16_t newValue; core_util_critical_section_enter(); @@ -286,7 +286,7 @@ uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta) return newValue; } -uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta) +uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta) { uint32_t newValue; core_util_critical_section_enter(); @@ -297,7 +297,7 @@ uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta) } -uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta) +uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta) { uint8_t newValue; core_util_critical_section_enter(); @@ -307,7 +307,7 @@ uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta) return newValue; } -uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta) +uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta) { uint16_t newValue; core_util_critical_section_enter(); @@ -317,7 +317,7 @@ uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta) return newValue; } -uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta) +uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta) { uint32_t newValue; core_util_critical_section_enter(); @@ -330,18 +330,18 @@ uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta) #endif -bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue) { +bool core_util_atomic_cas_ptr(void * volatile *ptr, void **expectedCurrentValue, void *desiredValue) { return core_util_atomic_cas_u32( - (uint32_t *)ptr, + (volatile uint32_t *)ptr, (uint32_t *)expectedCurrentValue, (uint32_t)desiredValue); } -void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta) { - return (void *)core_util_atomic_incr_u32((uint32_t *)valuePtr, (uint32_t)delta); +void *core_util_atomic_incr_ptr(void * volatile *valuePtr, ptrdiff_t delta) { + return (void *)core_util_atomic_incr_u32((volatile uint32_t *)valuePtr, (uint32_t)delta); } -void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta) { - return (void *)core_util_atomic_decr_u32((uint32_t *)valuePtr, (uint32_t)delta); +void *core_util_atomic_decr_ptr(void * volatile *valuePtr, ptrdiff_t delta) { + return (void *)core_util_atomic_decr_u32((volatile uint32_t *)valuePtr, (uint32_t)delta); } diff --git a/platform/mbed_critical.h b/platform/mbed_critical.h index f428e86032..17ec788934 100644 --- a/platform/mbed_critical.h +++ b/platform/mbed_critical.h @@ -144,7 +144,7 @@ bool core_util_in_critical_section(void); * always succeeds if the current value is expected, as per the pseudocode * above; it will not spuriously fail as "atomic_compare_exchange_weak" may. */ -bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue); +bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue); /** * Atomic compare and set. It compares the contents of a memory location to a @@ -201,7 +201,7 @@ bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_ * always succeeds if the current value is expected, as per the pseudocode * above; it will not spuriously fail as "atomic_compare_exchange_weak" may. */ -bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue); +bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue); /** * Atomic compare and set. It compares the contents of a memory location to a @@ -258,7 +258,7 @@ bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uin * above; it will not spuriously fail as "atomic_compare_exchange_weak" may. * } */ -bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue); +bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue); /** * Atomic compare and set. It compares the contents of a memory location to a @@ -315,7 +315,7 @@ bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uin * always succeeds if the current value is expected, as per the pseudocode * above; it will not spuriously fail as "atomic_compare_exchange_weak" may. */ -bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue); +bool core_util_atomic_cas_ptr(void * volatile *ptr, void **expectedCurrentValue, void *desiredValue); /** * Atomic increment. @@ -323,7 +323,7 @@ bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *des * @param delta The amount being incremented. * @return The new incremented value. */ -uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta); +uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta); /** * Atomic increment. @@ -331,7 +331,7 @@ uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta); * @param delta The amount being incremented. * @return The new incremented value. */ -uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta); +uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta); /** * Atomic increment. @@ -339,7 +339,7 @@ uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta); * @param delta The amount being incremented. * @return The new incremented value. */ -uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta); +uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta); /** * Atomic increment. @@ -350,7 +350,7 @@ uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta); * @note The type of the pointer argument is not taken into account * and the pointer is incremented by bytes. */ -void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta); +void *core_util_atomic_incr_ptr(void * volatile *valuePtr, ptrdiff_t delta); /** * Atomic decrement. @@ -358,7 +358,7 @@ void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta); * @param delta The amount being decremented. * @return The new decremented value. */ -uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta); +uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta); /** * Atomic decrement. @@ -366,7 +366,7 @@ uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta); * @param delta The amount being decremented. * @return The new decremented value. */ -uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta); +uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta); /** * Atomic decrement. @@ -374,7 +374,7 @@ uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta); * @param delta The amount being decremented. * @return The new decremented value. */ -uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta); +uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta); /** * Atomic decrement. @@ -385,7 +385,7 @@ uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta); * @note The type of the pointer argument is not taken into account * and the pointer is decremented by bytes */ -void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta); +void *core_util_atomic_decr_ptr(void * volatile *valuePtr, ptrdiff_t delta); #ifdef __cplusplus } // extern "C" From 3fdce9bd395178006ba4e42cb0537f8ff0dceb68 Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Tue, 13 Mar 2018 15:29:49 +0000 Subject: [PATCH 103/118] PR template: fix task --- .github/pull_request_template.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index 80506a0647..804346f215 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -14,8 +14,8 @@ Please tick one of the following types --> -- [ ] Fix -- [ ] Refactor -- [ ] New target -- [ ] Feature -- [ ] Breaking change +* [ ] Fix +* [ ] Refactor +* [ ] New target +* [ ] Feature +* [ ] Breaking change From aca6620091c9afe582db4ee0afcad0b1c2d6632a Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Tue, 13 Mar 2018 15:30:22 +0000 Subject: [PATCH 104/118] PR template: only one should be checked --- .github/pull_request_template.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index 804346f215..fdcb84e214 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -11,7 +11,7 @@ * [ ] Fix From d07086c03dafbb3402a250a3712db5924584e4b6 Mon Sep 17 00:00:00 2001 From: Martin Kojtal <0xc0170@gmail.com> Date: Tue, 20 Mar 2018 11:56:03 +0000 Subject: [PATCH 105/118] PR template: do not use task list --- .github/pull_request_template.md | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index fdcb84e214..ef0af9c397 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -11,11 +11,17 @@ -* [ ] Fix -* [ ] Refactor -* [ ] New target -* [ ] Feature -* [ ] Breaking change +[ ] Fix +[ ] Refactor +[ ] New target +[ ] Feature +[ ] Breaking change From c9a727e1a5eb38be2aa68bbe018f6c7ba5994916 Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Tue, 20 Mar 2018 13:14:47 +0100 Subject: [PATCH 106/118] STM32L4 ADC Internal Channel : correct sampling time --- .../TARGET_STM/TARGET_STM32L4/analogin_device.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c b/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c index 550589f311..290207f43a 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c @@ -105,9 +105,16 @@ uint16_t adc_read(analogin_t *obj) ADC_ChannelConfTypeDef sConfig = {0}; // Configure ADC channel + sConfig.Rank = ADC_REGULAR_RANK_1; + sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5; // default value (1.5 us for 80MHz clock) + sConfig.SingleDiff = ADC_SINGLE_ENDED; + sConfig.OffsetNumber = ADC_OFFSET_NONE; + sConfig.Offset = 0; + switch (obj->channel) { case 0: sConfig.Channel = ADC_CHANNEL_VREFINT; + sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; // Minimum ADC sampling time when reading the internal reference voltage is 4us break; case 1: sConfig.Channel = ADC_CHANNEL_1; @@ -159,20 +166,16 @@ uint16_t adc_read(analogin_t *obj) break; case 17: sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; + sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; // Minimum ADC sampling time when reading the temperature is 5us break; case 18: sConfig.Channel = ADC_CHANNEL_VBAT; + sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5; // Minimum ADC sampling time when reading the VBAT is 12us break; default: return 0; } - sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5; - sConfig.SingleDiff = ADC_SINGLE_ENDED; - sConfig.OffsetNumber = ADC_OFFSET_NONE; - sConfig.Offset = 0; - HAL_ADC_ConfigChannel(&obj->handle, &sConfig); HAL_ADC_Start(&obj->handle); // Start conversion From 0b866b7d292472d503df4148da6a5929e541e93e Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 21 Mar 2018 10:13:06 +0100 Subject: [PATCH 107/118] STM32L4 ADC correct internal channel management --- .../TARGET_STM32L4/device/stm32l4xx_hal_adc.c | 104 ++++++++---------- 1 file changed, 44 insertions(+), 60 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c index c9c033cbc6..a152b9e040 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c @@ -2312,7 +2312,6 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Single or differential mode */ - /* - Internal measurement channels: Vbat/VrefInt/TempSensor */ if (ADC_IS_ENABLE(hadc) == RESET) { /* Set mode single-ended or differential input of the selected ADC channel */ @@ -2325,71 +2324,56 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime); } - /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ - /* If internal channel selected, enable dedicated internal buffers and */ - /* paths. */ - /* Note: these internal measurement paths can be disabled using */ - /* HAL_ADC_DeInit(). */ - - /* Configuration of common ADC parameters */ - /* If the requested internal measurement path has already been enabled, */ - /* bypass the configuration processing. */ - if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || - ( (sConfig->Channel == ADC_CHANNEL_VBAT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || - ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && - ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) - ) + } + + /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ + /* If internal channel selected, enable dedicated internal buffers and */ + /* paths. */ + /* Note: these internal measurement paths can be disabled using */ + /* HAL_ADC_DeInit(). */ + + /* Configuration of common ADC parameters */ + /* If the requested internal measurement path has already been enabled, */ + /* bypass the configuration processing. */ + if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || + ( (sConfig->Channel == ADC_CHANNEL_VBAT) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || + ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && + ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) + ) + { + /* Configuration of common ADC parameters (continuation) */ + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) { - /* Configuration of common ADC parameters (continuation) */ - - /* Software is allowed to change common parameters only when all ADCs */ - /* of the common group are disabled. */ - if ((ADC_IS_ENABLE(hadc) == RESET) && - (ADC_ANY_OTHER_ENABLED(hadc) == RESET) ) + if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) { - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + + /* Delay for temperature sensor stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles. */ + wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2))); + while(wait_loop_index != 0) { - if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - - /* Delay for temperature sensor stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles. */ - wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2))); - while(wait_loop_index != 0) - { - wait_loop_index--; - } - } - } - else if (sConfig->Channel == ADC_CHANNEL_VBAT) - { - if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - } - } - else if (sConfig->Channel == ADC_CHANNEL_VREFINT) - { - if (ADC_VREFINT_INSTANCE(hadc)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); - } + wait_loop_index--; } } - /* If the requested internal measurement path has already been */ - /* enabled and other ADC of the common group are enabled, internal */ - /* measurement paths cannot be enabled. */ - else + } + else if (sConfig->Channel == ADC_CHANNEL_VBAT) + { + if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); + } + } + else if (sConfig->Channel == ADC_CHANNEL_VREFINT) + { + if (ADC_VREFINT_INSTANCE(hadc)) + { + LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); } } } From 1965c111c509e6b7a53660de37d9a59235a6ddd0 Mon Sep 17 00:00:00 2001 From: Steven Cartmell Date: Thu, 15 Mar 2018 15:49:42 +0000 Subject: [PATCH 108/118] Replace runtime strip_path function with compiler intrinsic equivalents Sleep manager tracing strips the path from filenames and uses the result as an identifier to track drivers that unlock/lock sleep tracing. Replace the function that strips the path from the string, replace this function with a new macro, __FILENAME__ which performs the same action in a compiler specific manner. - GCC_ARM, use __builtin_strrchr which is optimized out at compile time. - ARM, use __MODULE__ which returns the filename without path. - IAR, specifiy the --no_path_in_file_macros compiler flag. --- hal/mbed_sleep_manager.c | 32 ++++++-------------------------- platform/mbed_power_mgmt.h | 27 +++++++++++++++++---------- tools/profiles/debug.json | 3 ++- tools/profiles/develop.json | 3 ++- 4 files changed, 27 insertions(+), 38 deletions(-) diff --git a/hal/mbed_sleep_manager.c b/hal/mbed_sleep_manager.c index 79fbc58d52..a5f5e3f883 100644 --- a/hal/mbed_sleep_manager.c +++ b/hal/mbed_sleep_manager.c @@ -42,23 +42,6 @@ typedef struct sleep_statistic { static sleep_statistic_t sleep_stats[STATISTIC_COUNT]; -static const char* strip_path(const char* const filename) -{ - char *output = strrchr(filename, '/'); - - if (output != NULL) { - return output + 1; - } - - output = strrchr(filename, '\\'); - - if (output != NULL) { - return output + 1; - } - - return filename; -} - static sleep_statistic_t* sleep_tracker_find(const char *const filename) { char temp[IDENTIFIER_WIDTH]; @@ -115,34 +98,31 @@ static void sleep_tracker_print_stats(void) void sleep_tracker_lock(const char* const filename, int line) { - const char* const stripped_path = strip_path(filename); - - sleep_statistic_t* stat = sleep_tracker_find(stripped_path); + sleep_statistic_t *stat = sleep_tracker_find(filename); // Entry for this driver does not exist, create one. if (stat == NULL) { - stat = sleep_tracker_add(stripped_path); + stat = sleep_tracker_add(filename); } core_util_atomic_incr_u8(&stat->count, 1); - debug("LOCK: %s, ln: %i, lock count: %u\r\n", stripped_path, line, deep_sleep_lock); + debug("LOCK: %s, ln: %i, lock count: %u\r\n", filename, line, deep_sleep_lock); } void sleep_tracker_unlock(const char* const filename, int line) { - const char* const stripped_path = strip_path(filename); - sleep_statistic_t* stat = sleep_tracker_find(stripped_path); + sleep_statistic_t *stat = sleep_tracker_find(filename); // Entry for this driver does not exist, something went wrong. if (stat == NULL) { - debug("Unlocking sleep for driver that was not previously locked: %s, ln: %i\r\n", stripped_path, line); + debug("Unlocking sleep for driver that was not previously locked: %s, ln: %i\r\n", filename, line); return; } core_util_atomic_decr_u8(&stat->count, 1); - debug("UNLOCK: %s, ln: %i, lock count: %u\r\n", stripped_path, line, deep_sleep_lock); + debug("UNLOCK: %s, ln: %i, lock count: %u\r\n", filename, line, deep_sleep_lock); } #endif // MBED_SLEEP_TRACING_ENABLED diff --git a/platform/mbed_power_mgmt.h b/platform/mbed_power_mgmt.h index c70fb515f9..c82e180d1a 100644 --- a/platform/mbed_power_mgmt.h +++ b/platform/mbed_power_mgmt.h @@ -68,18 +68,26 @@ extern "C" { void sleep_tracker_lock(const char *const filename, int line); void sleep_tracker_unlock(const char *const filename, int line); -#define sleep_manager_lock_deep_sleep() \ - do \ - { \ - sleep_manager_lock_deep_sleep_internal(); \ - sleep_tracker_lock(__FILE__, __LINE__); \ - } while (0); +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#define __FILENAME__ __MODULE__ +#elif defined(__GNUC__) +#define __FILENAME__ (__builtin_strrchr(__FILE__, '/') ? __builtin_strrchr(__FILE__, '/') + 1 : __builtin_strrchr(__FILE__, '\\') ? __builtin_strrchr(__FILE__, '\\') + 1 : __FILE__) +#else +#define __FILENAME__ __FILE__ +#endif -#define sleep_manager_unlock_deep_sleep() \ +#define sleep_manager_lock_deep_sleep() \ do \ { \ - sleep_manager_unlock_deep_sleep_internal(); \ - sleep_tracker_unlock(__FILE__, __LINE__); \ + sleep_manager_lock_deep_sleep_internal(); \ + sleep_tracker_lock(__FILENAME__, __LINE__); \ + } while (0); + +#define sleep_manager_unlock_deep_sleep() \ + do \ + { \ + sleep_manager_unlock_deep_sleep_internal(); \ + sleep_tracker_unlock(__FILENAME__, __LINE__); \ } while (0); #else @@ -121,7 +129,6 @@ void sleep_manager_unlock_deep_sleep_internal(void); */ bool sleep_manager_can_deep_sleep(void); - /** Enter auto selected sleep mode. It chooses the sleep or deeepsleep modes based * on the deepsleep locking counter * diff --git a/tools/profiles/debug.json b/tools/profiles/debug.json index b5229e2e1a..33af224240 100644 --- a/tools/profiles/debug.json +++ b/tools/profiles/debug.json @@ -51,7 +51,8 @@ "common": [ "--no_wrap_diagnostics", "-e", "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-On", "-r", "-DMBED_DEBUG", - "-DMBED_TRAP_ERRORS_ENABLED=1", "--enable_restrict"], + "-DMBED_TRAP_ERRORS_ENABLED=1", "--enable_restrict", + "--no_path_in_file_macros"], "asm": [], "c": ["--vla"], "cxx": ["--guard_calls", "--no_static_destruction"], diff --git a/tools/profiles/develop.json b/tools/profiles/develop.json index 7858826722..720c0ff843 100644 --- a/tools/profiles/develop.json +++ b/tools/profiles/develop.json @@ -46,7 +46,8 @@ "IAR": { "common": [ "--no_wrap_diagnostics", "-e", - "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh", "--enable_restrict"], + "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh", "--enable_restrict", + "--no_path_in_file_macros"], "asm": [], "c": ["--vla"], "cxx": ["--guard_calls", "--no_static_destruction"], From 87029c6af4df0a1d72724498c6f8a1805f28e2b9 Mon Sep 17 00:00:00 2001 From: Steven Cartmell Date: Thu, 15 Mar 2018 17:21:29 +0000 Subject: [PATCH 109/118] Refactor sleep tracing driver identifier to be pointer to the driver filepath. The use of __FILE__ macro to get a usable identifier from the driver path causes the path of the file to be stored in the .text region of the binary. Given that this remains for the entire duration of the program, storing a pointer to this string as an identifier is more efficient than copying the contents of the string during lookup/insertion. --- hal/mbed_sleep_manager.c | 25 ++++++------------------- 1 file changed, 6 insertions(+), 19 deletions(-) diff --git a/hal/mbed_sleep_manager.c b/hal/mbed_sleep_manager.c index a5f5e3f883..6c699b751a 100644 --- a/hal/mbed_sleep_manager.c +++ b/hal/mbed_sleep_manager.c @@ -30,13 +30,11 @@ static uint16_t deep_sleep_lock = 0U; #ifdef MBED_SLEEP_TRACING_ENABLED -// Length of the identifier extracted from the driver name to store for logging. -#define IDENTIFIER_WIDTH 15 // Number of drivers that can be stored in the structure #define STATISTIC_COUNT 10 typedef struct sleep_statistic { - char identifier[IDENTIFIER_WIDTH]; + const char* identifier; uint8_t count; } sleep_statistic_t; @@ -44,13 +42,8 @@ static sleep_statistic_t sleep_stats[STATISTIC_COUNT]; static sleep_statistic_t* sleep_tracker_find(const char *const filename) { - char temp[IDENTIFIER_WIDTH]; - strncpy(temp, filename, IDENTIFIER_WIDTH); - temp[IDENTIFIER_WIDTH - 1] = '\0'; - - // Search for the a driver matching the current name and return it's index for (int i = 0; i < STATISTIC_COUNT; ++i) { - if (strcmp(sleep_stats[i].identifier, temp) == 0) { + if (sleep_stats[i].identifier == filename) { return &sleep_stats[i]; } } @@ -60,15 +53,9 @@ static sleep_statistic_t* sleep_tracker_find(const char *const filename) static sleep_statistic_t* sleep_tracker_add(const char* const filename) { - char temp[IDENTIFIER_WIDTH]; - strncpy(temp, filename, IDENTIFIER_WIDTH); - temp[IDENTIFIER_WIDTH - 1] = '\0'; - for (int i = 0; i < STATISTIC_COUNT; ++i) { - if (sleep_stats[i].identifier[0] == '\0') { - core_util_critical_section_enter(); - strncpy(sleep_stats[i].identifier, temp, sizeof(temp)); - core_util_critical_section_exit(); + if (sleep_stats[i].identifier == NULL) { + sleep_stats[i].identifier = filename; return &sleep_stats[i]; } @@ -87,12 +74,12 @@ static void sleep_tracker_print_stats(void) continue; } - if (sleep_stats[i].identifier[0] == '\0') { + if (sleep_stats[i].identifier == NULL) { return; } debug("[id: %s, count: %u]\r\n", sleep_stats[i].identifier, - sleep_stats[i].count); + sleep_stats[i].count); } } From 6c04d9e46830f4825c2dfdc446bbb1a332db3a28 Mon Sep 17 00:00:00 2001 From: Steven Cartmell Date: Fri, 16 Mar 2018 14:41:56 +0000 Subject: [PATCH 110/118] Remove superfluous compiler check in macro --- platform/mbed_power_mgmt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform/mbed_power_mgmt.h b/platform/mbed_power_mgmt.h index c82e180d1a..6e59929533 100644 --- a/platform/mbed_power_mgmt.h +++ b/platform/mbed_power_mgmt.h @@ -68,7 +68,7 @@ extern "C" { void sleep_tracker_lock(const char *const filename, int line); void sleep_tracker_unlock(const char *const filename, int line); -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +#if defined(__CC_ARM) #define __FILENAME__ __MODULE__ #elif defined(__GNUC__) #define __FILENAME__ (__builtin_strrchr(__FILE__, '/') ? __builtin_strrchr(__FILE__, '/') + 1 : __builtin_strrchr(__FILE__, '\\') ? __builtin_strrchr(__FILE__, '\\') + 1 : __FILE__) From 4ff6dd27bea6a640a774a94b43aaa9ad39a24c84 Mon Sep 17 00:00:00 2001 From: Steven Cartmell Date: Mon, 19 Mar 2018 13:22:33 +0000 Subject: [PATCH 111/118] Remove IAR compiler flag change from PR --- tools/profiles/debug.json | 3 +-- tools/profiles/develop.json | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/tools/profiles/debug.json b/tools/profiles/debug.json index 33af224240..b5229e2e1a 100644 --- a/tools/profiles/debug.json +++ b/tools/profiles/debug.json @@ -51,8 +51,7 @@ "common": [ "--no_wrap_diagnostics", "-e", "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-On", "-r", "-DMBED_DEBUG", - "-DMBED_TRAP_ERRORS_ENABLED=1", "--enable_restrict", - "--no_path_in_file_macros"], + "-DMBED_TRAP_ERRORS_ENABLED=1", "--enable_restrict"], "asm": [], "c": ["--vla"], "cxx": ["--guard_calls", "--no_static_destruction"], diff --git a/tools/profiles/develop.json b/tools/profiles/develop.json index 720c0ff843..7858826722 100644 --- a/tools/profiles/develop.json +++ b/tools/profiles/develop.json @@ -46,8 +46,7 @@ "IAR": { "common": [ "--no_wrap_diagnostics", "-e", - "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh", "--enable_restrict", - "--no_path_in_file_macros"], + "--diag_suppress=Pa050,Pa084,Pa093,Pa082", "-Oh", "--enable_restrict"], "asm": [], "c": ["--vla"], "cxx": ["--guard_calls", "--no_static_destruction"], From 43e646d74fea0ad2fffb198de6389617ffd1d6bb Mon Sep 17 00:00:00 2001 From: Steven Cartmell Date: Tue, 20 Mar 2018 14:23:00 +0000 Subject: [PATCH 112/118] Fix issues with __FILENAME__ macro - Move macro definition to mbed_toolchain.h - Remove double underscores from macro which are reserved. - Fix macro for IAR until compiler flags to disable path are added again. --- platform/mbed_power_mgmt.h | 28 ++++++++++------------------ platform/mbed_toolchain.h | 16 +++++++++++++++- 2 files changed, 25 insertions(+), 19 deletions(-) diff --git a/platform/mbed_power_mgmt.h b/platform/mbed_power_mgmt.h index 6e59929533..6e4540ca1c 100644 --- a/platform/mbed_power_mgmt.h +++ b/platform/mbed_power_mgmt.h @@ -68,26 +68,18 @@ extern "C" { void sleep_tracker_lock(const char *const filename, int line); void sleep_tracker_unlock(const char *const filename, int line); -#if defined(__CC_ARM) -#define __FILENAME__ __MODULE__ -#elif defined(__GNUC__) -#define __FILENAME__ (__builtin_strrchr(__FILE__, '/') ? __builtin_strrchr(__FILE__, '/') + 1 : __builtin_strrchr(__FILE__, '\\') ? __builtin_strrchr(__FILE__, '\\') + 1 : __FILE__) -#else -#define __FILENAME__ __FILE__ -#endif - -#define sleep_manager_lock_deep_sleep() \ - do \ - { \ - sleep_manager_lock_deep_sleep_internal(); \ - sleep_tracker_lock(__FILENAME__, __LINE__); \ +#define sleep_manager_lock_deep_sleep() \ + do \ + { \ + sleep_manager_lock_deep_sleep_internal(); \ + sleep_tracker_lock(MBED_FILENAME, __LINE__); \ } while (0); -#define sleep_manager_unlock_deep_sleep() \ - do \ - { \ - sleep_manager_unlock_deep_sleep_internal(); \ - sleep_tracker_unlock(__FILENAME__, __LINE__); \ +#define sleep_manager_unlock_deep_sleep() \ + do \ + { \ + sleep_manager_unlock_deep_sleep_internal(); \ + sleep_tracker_unlock(MBED_FILENAME, __LINE__); \ } while (0); #else diff --git a/platform/mbed_toolchain.h b/platform/mbed_toolchain.h index f51e1f4c11..e345cc914e 100644 --- a/platform/mbed_toolchain.h +++ b/platform/mbed_toolchain.h @@ -376,13 +376,27 @@ #endif #endif +// Macro containing the filename part of the value of __FILE__. Defined as +// string literal. +#ifndef MBED_FILENAME +#if defined(__CC_ARM) +#define MBED_FILENAME __MODULE__ +#elif defined(__GNUC__) +#define MBED_FILENAME (__builtin_strrchr(__FILE__, '/') ? __builtin_strrchr(__FILE__, '/') + 1 : __builtin_strrchr(__FILE__, '\\') ? __builtin_strrchr(__FILE__, '\\') + 1 : __FILE__) +#elif defined(__ICCARM__) +#define MBED_FILENAME (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : strrchr(__FILE__, '\\') ? strrchr(__FILE__, '\\') + 1 : __FILE__) +#else +#define MBED_FILENAME __FILE__ +#endif +#endif // #ifndef MBED_FILENAME + // FILEHANDLE declaration #if defined(TOOLCHAIN_ARM) #include #endif #ifndef FILEHANDLE -typedef int FILEHANDLE; + typedef int FILEHANDLE; #endif // Backwards compatibility From 7138038a6a3a209880164aefd8bd8cd2eab47bd7 Mon Sep 17 00:00:00 2001 From: Jimmy Brisson Date: Wed, 21 Mar 2018 10:50:56 -0500 Subject: [PATCH 113/118] Correct get_config imports --- tools/get_config.py | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/tools/get_config.py b/tools/get_config.py index ceda6d5cb8..a78a33db17 100644 --- a/tools/get_config.py +++ b/tools/get_config.py @@ -16,6 +16,7 @@ See the License for the specific language governing permissions and limitations under the License. """ +from __future__ import print_function import sys from os.path import isdir, abspath, dirname, join from os import _exit @@ -28,8 +29,8 @@ from tools.utils import args_error from tools.options import get_default_options_parser from tools.options import extract_mcus from tools.build_api import get_config -from config import Config -from utils import argparse_filestring_type +from tools.config import Config +from tools.utils import argparse_filestring_type try: import tools.private_settings as ps except: @@ -62,31 +63,31 @@ if __name__ == '__main__': try: params, macros, features = get_config(options.source_dir, target, toolchain) if not params and not macros: - print "No configuration data available." + print("No configuration data available.") _exit(0) if params: - print "Configuration parameters" - print "------------------------" + print("Configuration parameters") + print("------------------------") for p in sorted(params): for s in options.prefix: if p.startswith(s): print(str(params[p]) if not options.verbose else params[p].get_verbose_description()) break - print "" + print("") - print "Macros" - print "------" + print("Macros") + print("------") if macros: - print 'Defined with "macros":', Config.config_macros_to_macros(macros) - print "Generated from configuration parameters:", Config.parameters_to_macros(params) + print('Defined with "macros":', Config.config_macros_to_macros(macros)) + print("Generated from configuration parameters:", Config.parameters_to_macros(params)) - except KeyboardInterrupt, e: - print "\n[CTRL+c] exit" - except Exception,e: + except KeyboardInterrupt as e: + print("\n[CTRL+c] exit") + except Exception as e: if options.verbose: import traceback traceback.print_exc(file=sys.stdout) else: - print "[ERROR] %s" % str(e) + print("[ERROR] %s" % str(e)) sys.exit(1) From 038ede386adb26d3ea8f0e57fc242ac634cef868 Mon Sep 17 00:00:00 2001 From: ccli8 Date: Thu, 22 Mar 2018 16:45:01 +0800 Subject: [PATCH 114/118] Fix page size in flash IAP In Mbed OS, page size is program unit, which is different than FMC definition. After fixing page size, we can pass NVSTORE test (mbed-os-features-nvstore-tests-nvstore-functionality). --- targets/TARGET_NUVOTON/TARGET_M451/flash_api.c | 3 ++- targets/TARGET_NUVOTON/TARGET_M480/flash_api.c | 3 ++- targets/TARGET_NUVOTON/TARGET_NUC472/flash_api.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/targets/TARGET_NUVOTON/TARGET_M451/flash_api.c b/targets/TARGET_NUVOTON/TARGET_M451/flash_api.c index 01e19a20fd..96baa166c7 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/flash_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/flash_api.c @@ -65,7 +65,8 @@ static const sector_info_t sectors_info[] = { }; static const flash_target_config_t flash_target_config = { - .page_size = 0x800, // 2 KB + .page_size = 4, // 4 bytes + // Here page_size is program unit, which is different than FMC definition. .flash_start = 0x0, .flash_size = 0x40000, // 256 KB .sectors = sectors_info, diff --git a/targets/TARGET_NUVOTON/TARGET_M480/flash_api.c b/targets/TARGET_NUVOTON/TARGET_M480/flash_api.c index a5913d4a52..cc2eeffb08 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/flash_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/flash_api.c @@ -69,7 +69,8 @@ static const sector_info_t sectors_info[] = { }; static const flash_target_config_t flash_target_config = { - .page_size = 0x200, // 512 bytes + .page_size = 4, // 4 bytes + // Here page_size is program unit, which is different than FMC definition. .flash_start = 0x0, .flash_size = 0x80000, // 512 KB .sectors = sectors_info, diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/flash_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/flash_api.c index 0d3a74ffbb..8da24b1b29 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/flash_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/flash_api.c @@ -67,7 +67,8 @@ static const sector_info_t sectors_info[] = { }; static const flash_target_config_t flash_target_config = { - .page_size = 0x800, // 2 KB + .page_size = 4, // 4 bytes + // Here page_size is program unit, which is different than FMC definition. .flash_start = 0x0, .flash_size = 0x80000, // 512 KB .sectors = sectors_info, From c4aed9d34025e04c7bd6803777c47cde285105fa Mon Sep 17 00:00:00 2001 From: Cruz Monrreal II Date: Thu, 22 Mar 2018 15:08:21 -0500 Subject: [PATCH 115/118] Modified apt-get retry logic with Travis CI retry feature --- .travis.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index 8259c65d7a..a2d58e3d5c 100644 --- a/.travis.yml +++ b/.travis.yml @@ -31,7 +31,7 @@ before_install: # Setup ppa to make sure arm-none-eabi-gcc is correct version - sudo add-apt-repository -y ppa:team-gcc-arm-embedded/ppa # Loop until update succeeds (timeouts can occur) - - while [ -n "$(sudo apt-get update 2>&1 |grep Failed)" ]; do :; done + - travis_retry $(! sudo apt-get update 2>&1 |grep Failed) after_success: - bash -c "$STATUS" success "Local $NAME testing has passed" From 20d9b4a17ec9c5925758e7423731bef4762bae02 Mon Sep 17 00:00:00 2001 From: adbridge Date: Mon, 26 Mar 2018 18:52:33 +0100 Subject: [PATCH 116/118] Update Mbed version block for patch release --- mbed.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mbed.h b/mbed.h index 78fcad486d..9237daa2a4 100644 --- a/mbed.h +++ b/mbed.h @@ -22,7 +22,7 @@ // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 #define MBED_MINOR_VERSION 8 -#define MBED_PATCH_VERSION 0 +#define MBED_PATCH_VERSION 1 #else // mbed 2 From 3ba208a96dcdf29542ef64f4eeb3978f546b18c3 Mon Sep 17 00:00:00 2001 From: Antti Yli-Tokola Date: Thu, 22 Feb 2018 17:57:12 +0200 Subject: [PATCH 117/118] Update mbed-coap to version 4.3.0 Add new api to clear whole sent blockwise message list --- .../FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md | 6 ++++++ .../mbed-coap/mbed-coap/sn_coap_protocol.h | 9 ++++++++ .../FEATURE_COMMON_PAL/mbed-coap/module.json | 2 +- .../mbed-coap/source/sn_coap_protocol.c | 21 +++++++++++++++++++ 4 files changed, 37 insertions(+), 1 deletion(-) diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md index 5578d8fc1f..95d4b0f81e 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md +++ b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md @@ -1,5 +1,11 @@ # Change Log +## [v4.3.0](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.3.0) +**New feature:** +- Add new API which clears the whole sent blockwise message list + +-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.2.0...v4.3.0) + ## [v4.2.0](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.2.0) **New feature:** - Add new API to remove sent blockwise message from the linked list diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h b/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h index e71a367244..345c3672e6 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h +++ b/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h @@ -247,6 +247,15 @@ extern int8_t sn_coap_convert_block_size(uint16_t block_size); */ extern int8_t sn_coap_protocol_handle_block2_response_internally(struct coap_s *handle, uint8_t handle_response); +/** + * \fn void sn_coap_protocol_clear_sent_blockwise_messages(struct coap_s *handle) + * + * \brief This function clears all the sent blockwise messages from the linked list. + * + * \param *handle Pointer to CoAP library handle + */ +extern void sn_coap_protocol_clear_sent_blockwise_messages(struct coap_s *handle); + #endif /* SN_COAP_PROTOCOL_H_ */ #ifdef __cplusplus diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/module.json b/features/FEATURE_COMMON_PAL/mbed-coap/module.json index 07db997ae1..b54fb79b9c 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/module.json +++ b/features/FEATURE_COMMON_PAL/mbed-coap/module.json @@ -1,6 +1,6 @@ { "name": "mbed-coap", - "version": "4.2.0", + "version": "4.3.0", "description": "COAP library", "keywords": [ "coap", diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c index 472f2361aa..6cdcb7ea95 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c @@ -256,6 +256,27 @@ int8_t sn_coap_protocol_set_block_size(struct coap_s *handle, uint16_t block_siz } +void sn_coap_protocol_clear_sent_blockwise_messages(struct coap_s *handle) +{ + (void) handle; +#if SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE + if (handle == NULL) { + return; + } + + /* Loop all stored Blockwise messages in Linked list */ + ns_list_foreach_safe(coap_blockwise_msg_s, removed_blocwise_msg_ptr, &handle->linked_list_blockwise_sent_msgs) { + if (removed_blocwise_msg_ptr->coap_msg_ptr) { + handle->sn_coap_protocol_free(removed_blocwise_msg_ptr->coap_msg_ptr->payload_ptr); + removed_blocwise_msg_ptr->coap_msg_ptr->payload_ptr = 0; + sn_coap_parser_release_allocated_coap_msg_mem(handle, removed_blocwise_msg_ptr->coap_msg_ptr); + removed_blocwise_msg_ptr->coap_msg_ptr = 0; + } + sn_coap_protocol_linked_list_blockwise_msg_remove(handle, removed_blocwise_msg_ptr); + } +#endif +} + int8_t sn_coap_protocol_set_duplicate_buffer_size(struct coap_s *handle, uint8_t message_count) { (void) handle; From a48b62d1a6e6e46654a3db26321050fd83892e16 Mon Sep 17 00:00:00 2001 From: Antti Yli-Tokola Date: Wed, 14 Mar 2018 15:34:15 +0200 Subject: [PATCH 118/118] Update mbed-coap to version 4.4.0 Make sn_coap_protocol_send_rst as public needed for CoAP ping sending Allow disabling resendings by defining SN_COAP_DISABLE_RESENDINGS --- features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md | 7 +++++++ .../mbed-coap/mbed-coap/sn_coap_protocol.h | 12 ++++++++++++ .../mbed-coap/mbed-coap/sn_config.h | 9 +++++++++ features/FEATURE_COMMON_PAL/mbed-coap/module.json | 2 +- .../source/include/sn_coap_protocol_internal.h | 4 ++++ .../mbed-coap/source/sn_coap_protocol.c | 5 +++-- 6 files changed, 36 insertions(+), 3 deletions(-) diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md index 95d4b0f81e..a3e87e1116 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md +++ b/features/FEATURE_COMMON_PAL/mbed-coap/CHANGELOG.md @@ -1,5 +1,12 @@ # Change Log +## [v4.4.0](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.4.0) +**New feature:** +- Make sn_coap_protocol_send_rst as public needed for CoAP ping sending +- Allow disabling resendings by defining SN_COAP_DISABLE_RESENDINGS + +-[Full Changelog](https://github.com/ARMmbed/mbed-coap/compare/v4.3.0...v4.4.0) + ## [v4.3.0](https://github.com/ARMmbed/mbed-coap/releases/tag/v4.3.0) **New feature:** - Add new API which clears the whole sent blockwise message list diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h b/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h index 345c3672e6..624faf3c78 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h +++ b/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_coap_protocol.h @@ -256,6 +256,18 @@ extern int8_t sn_coap_protocol_handle_block2_response_internally(struct coap_s * */ extern void sn_coap_protocol_clear_sent_blockwise_messages(struct coap_s *handle); +/** + * \fn void sn_coap_protocol_send_rst(struct coap_s *handle, uint16_t msg_id, sn_nsdl_addr_s *addr_ptr, void *param) + * + * \brief This function sends a RESET message. + * + * \param *handle Pointer to CoAP library handle + * \param msg_id Message id. + * \param addr_ptr Pointer to destination address where CoAP message will be sent + * \param param Pointer that will be passed to tx function callback + */ +extern void sn_coap_protocol_send_rst(struct coap_s *handle, uint16_t msg_id, sn_nsdl_addr_s *addr_ptr, void *param); + #endif /* SN_COAP_PROTOCOL_H_ */ #ifdef __cplusplus diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_config.h b/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_config.h index 7331195042..57fc98c8d4 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_config.h +++ b/features/FEATURE_COMMON_PAL/mbed-coap/mbed-coap/sn_config.h @@ -54,6 +54,15 @@ */ #undef COAP_DISABLE_OBS_FEATURE +/** + * \def SN_COAP_DISABLE_RESENDINGS + * + * \brief Disables resending feature. Resending feature should not be needed + * when using CoAP with TCP transport for example. By default resendings are + * enabled. Set to 1 to disable. + */ +#undef SN_COAP_DISABLE_RESENDINGS /* 0 */ // < Default re-sending are not disabled. Set to 1 to disable re-sendings + /** * \def SN_COAP_RESENDING_QUEUE_SIZE_MSGS * diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/module.json b/features/FEATURE_COMMON_PAL/mbed-coap/module.json index b54fb79b9c..333e89c82c 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/module.json +++ b/features/FEATURE_COMMON_PAL/mbed-coap/module.json @@ -1,6 +1,6 @@ { "name": "mbed-coap", - "version": "4.3.0", + "version": "4.4.0", "description": "COAP library", "keywords": [ "coap", diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h b/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h index d8c85b54ab..986f8c844e 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/include/sn_coap_protocol_internal.h @@ -39,7 +39,11 @@ struct sn_coap_hdr_; /* * * * * * * * * * * */ /* * For Message resending * */ +#ifdef SN_COAP_DISABLE_RESENDINGS +#define ENABLE_RESENDINGS 0 /* Disable resendings */ +#else #define ENABLE_RESENDINGS 1 /**< Enable / Disable resending from library in building */ +#endif #define SN_COAP_RESENDING_MAX_COUNT 3 /**< Default number of re-sendings */ diff --git a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c index 6cdcb7ea95..147a12292b 100644 --- a/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c +++ b/features/FEATURE_COMMON_PAL/mbed-coap/source/sn_coap_protocol.c @@ -47,7 +47,6 @@ /* * * * LOCAL FUNCTION PROTOTYPES * * * */ /* * * * * * * * * * * * * * * * * * * * */ -static void sn_coap_protocol_send_rst(struct coap_s *handle, uint16_t msg_id, sn_nsdl_addr_s *addr_ptr, void *param); #if SN_COAP_DUPLICATION_MAX_MSGS_COUNT/* If Message duplication detection is not used at all, this part of code will not be compiled */ static void sn_coap_protocol_linked_list_duplication_info_store(struct coap_s *handle, sn_nsdl_addr_s *src_addr_ptr, uint16_t msg_id, void *param); static coap_duplication_info_s *sn_coap_protocol_linked_list_duplication_info_search(struct coap_s *handle, sn_nsdl_addr_s *scr_addr_ptr, uint16_t msg_id); @@ -667,6 +666,8 @@ sn_coap_hdr_s *sn_coap_protocol_parse(struct coap_s *handle, sn_nsdl_addr_s *src /* Check if there is no room to store message for duplication detection purposes */ if (stored_duplication_msgs_count >= handle->sn_coap_duplication_buffer_size) { + tr_debug("sn_coap_protocol_parse - duplicate list full, dropping oldest"); + /* Get oldest stored duplication message */ coap_duplication_info_s *stored_duplication_info_ptr = ns_list_get_first(&handle->linked_list_duplication_msgs); @@ -1028,7 +1029,7 @@ uint32_t sn_coap_calculate_new_resend_time(const uint32_t current_time, const ui #endif /* ENABLE_RESENDINGS */ -static void sn_coap_protocol_send_rst(struct coap_s *handle, uint16_t msg_id, sn_nsdl_addr_s *addr_ptr, void *param) +void sn_coap_protocol_send_rst(struct coap_s *handle, uint16_t msg_id, sn_nsdl_addr_s *addr_ptr, void *param) { uint8_t packet_ptr[4];